Re: [PATCH v2 00/29] Add support for MT8196 clock controllers

["Nícolas F. R. A. Prado" <nfraprado@collabora.com>]

On Tue, 2025-06-24 at 16:31 +0200, Laura Nao wrote:
> Add support for MT8196 clock controllers
> 
> This patch series introduces support for the clock controllers on the
> MediaTek MT8196 platform, following up on an earlier submission[1].
> 
> MT8196 uses a hardware voting mechanism to control some of the clock
> muxes
> and gates, along with a fence register responsible for tracking PLL
> and mux
> gate readiness. The series introduces support for these voting and
> fence
> mechanisms, and includes drivers for all clock controllers on the
> platform.
> 
> [1]
> https://lore.kernel.org/all/20250307032942.10447-1-guangjie.song@mediatek.com/
> 
> Changes in v2:
> - Fixed incorrect ID numbering in mediatek,mt8196-clock.h
> - Improved description for 'mediatek,hardware-voter' in
> mediatek,mt8196-clock.yaml and mediatek,mt8196-sys-clock.yaml
> - Added description for '#reset-cells' in mediatek,mt8196-clock.yaml
> - Added missing mediatek,mt8196-vdisp-ao compatible in
> mediatek,mt8196-clock.yaml
> - Fixed license in mediatek,mt8196-resets.h
> - Fixed missing of_match_table in clk-mt8196-vdisp_ao.c
> - Squashed commit adding UFS and PEXTP reset controller support
> - Reordered commits to place reset controller binding before
> dependent drivers
> - Added R-b tags
> 
> Link to v1:
> https://lore.kernel.org/all/20250623102940.214269-1-laura.nao@collabora.com/
> 
> AngeloGioacchino Del Regno (1):
>   dt-bindings: reset: Add MediaTek MT8196 Reset Controller binding
> 
> Laura Nao (28):
>   clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable
> control
>   clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and
> FENC
>   clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and
>     FENC
>   clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()
>   clk: mediatek: clk-mux: Add ops for mux gates with HW voter and
> FENC
>   clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use
>     mtk_gate struct
>   clk: mediatek: clk-gate: Add ops for gates with HW voter
>   clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
>   dt-bindings: clock: mediatek: Describe MT8196 peripheral clock
>     controllers
>   clk: mediatek: Add MT8196 apmixedsys clock support
>   clk: mediatek: Add MT8196 topckgen clock support
>   clk: mediatek: Add MT8196 topckgen2 clock support
>   clk: mediatek: Add MT8196 vlpckgen clock support
>   clk: mediatek: Add MT8196 peripheral clock support
>   clk: mediatek: Add MT8196 ufssys clock support
>   clk: mediatek: Add MT8196 pextpsys clock support
>   clk: mediatek: Add MT8196 adsp clock support
>   clk: mediatek: Add MT8196 I2C clock support
>   clk: mediatek: Add MT8196 mcu clock support
>   clk: mediatek: Add MT8196 mdpsys clock support
>   clk: mediatek: Add MT8196 mfg clock support
>   clk: mediatek: Add MT8196 disp0 clock support
>   clk: mediatek: Add MT8196 disp1 clock support
>   clk: mediatek: Add MT8196 disp-ao clock support
>   clk: mediatek: Add MT8196 ovl0 clock support
>   clk: mediatek: Add MT8196 ovl1 clock support
>   clk: mediatek: Add MT8196 vdecsys clock support
>   clk: mediatek: Add MT8196 vencsys clock support

For the whole series:

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

(as I internally reviewed it before submission)

-- 
Thanks,

Nícolas