Re: [net-next,PATCH] enetc: Set eMDIO MDC rate to 2.5 MHz only on i.MX95

[Marek Vasut <marex@nabladev.com>]

On 10/8/26 2:22 AM, Jakub Kicinski wrote:
> On Mon, 05 Oct 2026 15:30:10 +0000 netdev-bot+sashiko@kernel.org wrote:
>>> -#define ENETC_EMDIO_CFG \
>>> +#define ENETC_EMDIO_CFG(mdc_div) \
>>>   	(MDIO_CFG_HOLD(2) | \
>>> -	 MDIO_CFG_CLKDIV(66) | \
>>> +	 MDIO_CFG_CLKDIV(mdc_div) | \
>>>   	 MDIO_CFG_NEG)
>>
>> [Severity: High]
>> What divider do the other users of these accessors get?
>>
>> The exported enetc_mdio_read_c22(), enetc_mdio_write_c22(),
>> enetc_mdio_read_c45() and enetc_mdio_write_c45() are shared with several
>> bus constructors. Only enetc_pci_mdio_probe() sets mdc_div.
>>
>> These constructors install the same accessors but set only hw and
>> mdio_base:
>>
>>    enetc_mdio_probe() in enetc_pf_common.c (PF external MDIO, LS1028A
>>    and ENETC4)
>>    enetc_imdio_create() in enetc_pf_common.c (internal Lynx PCS MDIO)
>>    netc_port_create_emdio_bus() in drivers/net/dsa/netc/netc_main.c
>>    vsc9959_mdio_bus_alloc() in drivers/net/dsa/ocelot/felix_vsc9959.c
>>
>> For example:
>>
>> enetc_pf_common.c:enetc_mdio_probe() {
>>      ...
>>      bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
>>      ...
>>      mdio_priv->hw = &pf->si->hw;
>>      if (is_enetc_rev1(pf->si))
>>          mdio_priv->mdio_base = ENETC_EMDIO_BASE;
>>      else
>>          mdio_priv->mdio_base = ENETC4_EMDIO_BASE;
>>      ...
>> }
>>
>> mdiobus_alloc_size() allocates the priv area with kzalloc(), so mdc_div
>> stays 0. MDIO_CFG_CLKDIV(x) is ((((x) >> 1) & 0xff) << 8).
>>
>> As a result, every C22/C45 transaction on these buses would write a zero
>> clock divider into ENETC_MDIO_CFG. Before 587acb86d646 the value was 258,
>> and after it the value was 66.
> 
> Looks legit.

Let me fill the default into Ocelot and enetc_pf_common.c