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Subject: Re: [PATCH bpf-next 2/2] arm64, bpf: support more atomic operations
To:     John Fastabend <john.fastabend@gmail.com>,
        Alexei Starovoitov <ast@kernel.org>
CC:     Martin KaFai Lau <kafai@fb.com>, Yonghong Song <yhs@fb.com>,
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References: <20220121135632.136976-1-houtao1@huawei.com>
 <20220121135632.136976-3-houtao1@huawei.com>
 <61f23655411bc_57f032084@john.notmuch>
 <8b67fa3d-f83c-85a5-5159-70b0f913833a@huawei.com>
 <61f35869ba5a_738dc20823@john.notmuch>
From:   Hou Tao <houtao1@huawei.com>
Message-ID: <cf4f75c9-dccb-913f-4527-d358cf653f93@huawei.com>
Date:   Fri, 28 Jan 2022 17:18:35 +0800
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Hi,

On 1/28/2022 10:43 AM, John Fastabend wrote:
> Hou Tao wrote:
>> Hi,
>>
>> On 1/27/2022 2:06 PM, John Fastabend wrote:
>>> Hou Tao wrote:
>>>> Atomics for eBPF patch series adds support for atomic[64]_fetch_add,
>>>> atomic[64]_[fetch_]{and,or,xor} and atomic[64]_{xchg|cmpxchg}, but
>>>> it only add support for x86-64, so support these atomic operations
>>>> for arm64 as well.
snip
>>>> +
>>>> +	switch (insn->imm) {
>>> Diff'ing X86 implementation which has a BPF_SUB case how is it avoided
>>> here?
>> I think it is just left over from patchset [1], because according to the LLVM
>> commit [2]
>> __sync_fetch_and_sub(&addr, value) is implemented by __sync_fetch_and_add(&addr,
>> -value).
>> I will post a patch to remove it.
> OK in that case LGTM with the caveat not an ARM expert.
>
> Acked-by: John Fastabend <john.fastabend@gmail.com>
Thanks for your Acked-by.

Regards,
Tao