[PATCH V2 0/1] DSA: Enable cascading for multiple 6131 chips

[PATCH V2 0/1] DSA: Enable cascading for multiple 6131 chips

[Barry Grussling]

I found that the Cascade Port field of the 6131 was always set
to 0xe which results in from_cpu frames being discarded.  This
means cascading style multi chip DSA configuration didn't work
for me.  I am a little confused by this since we configure the
DSA routing table a little further down in the function.

It seems like we need to enable cascading by setting the
Cascade Port field to 0xf if we are in a multi-chip scenario.

V2 changes are for whitespace to meet coding style.

Barry Grussling (1):
  Allow cascading to work with 6131 chip

 net/dsa/mv88e6131.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

[PATCH V2 1/1] Allow cascading to work with 6131 chip

[Barry Grussling]

---
 net/dsa/mv88e6131.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/net/dsa/mv88e6131.c b/net/dsa/mv88e6131.c
index 45f7411..dc43419 100644
--- a/net/dsa/mv88e6131.c
+++ b/net/dsa/mv88e6131.c
@@ -118,10 +118,14 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
 	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
 
 	/*
-	 * Disable cascade port functionality, and set the switch's
+	 * Disable cascade port functionality unless this device is
+	 * used in a cascade configuration, and set the switch's
 	 * DSA device number.
 	 */
-	REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
+	if (ds->dst->pd->nr_chips > 1)
+		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
+	else
+		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
 
 	/*
 	 * Send all frames with destination addresses matching
-- 
1.7.0.4

Re: [PATCH V2 1/1] Allow cascading to work with 6131 chip

[David Miller]

From: Barry Grussling <barry@grussling.com>
Date: Tue, 21 Jun 2011 07:55:56 -0700

> ---
>  net/dsa/mv88e6131.c |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)

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