* [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII
2026-01-28 9:53 [PATCH v5 0/3] s32g: Use a syscon for GPR Dan Carpenter
@ 2026-01-28 9:54 ` Dan Carpenter
2026-01-28 12:30 ` Jan Petrous
2026-01-28 9:54 ` [PATCH v5 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2026-01-28 9:54 ` [PATCH v5 3/3] dts: s32g: Add GPR syscon region Dan Carpenter
2 siblings, 1 reply; 6+ messages in thread
From: Dan Carpenter @ 2026-01-28 9:54 UTC (permalink / raw)
To: Jan Petrous
Cc: s32, Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, linaro-s32, imx
On the s32 chipsets the GMAC_0_CTRL_STS register is in GPR region.
Originally, accessing this register was done in a sort of ad-hoc way,
but we want to use the syscon interface to do it.
This is a little bit ugly because we have to maintain backwards
compatibility to the old device trees so we have to support both ways
to access this register.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v5: Return an error if regmap_write() fails
v4: no change
v3: no change
v2: Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/
.../net/ethernet/stmicro/stmmac/dwmac-s32.c | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
index 5a485ee98fa7..af594a096676 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
@@ -11,12 +11,14 @@
#include <linux/device.h>
#include <linux/ethtool.h>
#include <linux/io.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/of_address.h>
#include <linux/phy.h>
#include <linux/phylink.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/stmmac.h>
#include "stmmac_platform.h"
@@ -32,6 +34,8 @@
struct s32_priv_data {
void __iomem *ioaddr;
void __iomem *ctrl_sts;
+ struct regmap *sts_regmap;
+ unsigned int sts_offset;
struct device *dev;
phy_interface_t *intf_mode;
struct clk *tx_clk;
@@ -40,11 +44,17 @@ struct s32_priv_data {
static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
{
- writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
+ int ret = 0;
+
+ if (gmac->ctrl_sts)
+ writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
+ else
+ ret = regmap_write(gmac->sts_regmap, gmac->sts_offset,
+ S32_PHY_INTF_SEL_RGMII);
dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
- return 0;
+ return ret;
}
static int s32_gmac_init(struct device *dev, void *priv)
@@ -125,10 +135,16 @@ static int s32_dwmac_probe(struct platform_device *pdev)
"dt configuration failed\n");
/* PHY interface mode control reg */
- gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
- if (IS_ERR(gmac->ctrl_sts))
- return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
- "S32CC config region is missing\n");
+ gmac->sts_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+ "nxp,phy-sel", 1, &gmac->sts_offset);
+ if (gmac->sts_regmap == ERR_PTR(-EPROBE_DEFER))
+ return PTR_ERR(gmac->sts_regmap);
+ if (IS_ERR(gmac->sts_regmap)) {
+ gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
+ if (IS_ERR(gmac->ctrl_sts))
+ return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
+ "S32CC config region is missing\n");
+ }
/* tx clock */
gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII
2026-01-28 9:54 ` [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
@ 2026-01-28 12:30 ` Jan Petrous
0 siblings, 0 replies; 6+ messages in thread
From: Jan Petrous @ 2026-01-28 12:30 UTC (permalink / raw)
To: Dan Carpenter
Cc: s32, Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, linaro-s32, imx
On Wed, Jan 28, 2026 at 12:54:01PM +0300, Dan Carpenter wrote:
> On the s32 chipsets the GMAC_0_CTRL_STS register is in GPR region.
> Originally, accessing this register was done in a sort of ad-hoc way,
> but we want to use the syscon interface to do it.
>
> This is a little bit ugly because we have to maintain backwards
> compatibility to the old device trees so we have to support both ways
> to access this register.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> v5: Return an error if regmap_write() fails
> v4: no change
> v3: no change
> v2: Fix forward porting bug. s/PHY_INTF_SEL_RGMII/S32_PHY_INTF_SEL_RGMII/
>
> .../net/ethernet/stmicro/stmmac/dwmac-s32.c | 28 +++++++++++++++----
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> index 5a485ee98fa7..af594a096676 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> @@ -11,12 +11,14 @@
> #include <linux/device.h>
> #include <linux/ethtool.h>
> #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of_mdio.h>
> #include <linux/of_address.h>
> #include <linux/phy.h>
> #include <linux/phylink.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/stmmac.h>
>
> #include "stmmac_platform.h"
> @@ -32,6 +34,8 @@
> struct s32_priv_data {
> void __iomem *ioaddr;
> void __iomem *ctrl_sts;
> + struct regmap *sts_regmap;
> + unsigned int sts_offset;
> struct device *dev;
> phy_interface_t *intf_mode;
> struct clk *tx_clk;
> @@ -40,11 +44,17 @@ struct s32_priv_data {
>
> static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
> {
> - writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
> + int ret = 0;
> +
> + if (gmac->ctrl_sts)
> + writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
> + else
> + ret = regmap_write(gmac->sts_regmap, gmac->sts_offset,
> + S32_PHY_INTF_SEL_RGMII);
>
> dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
>
> - return 0;
> + return ret;
> }
>
> static int s32_gmac_init(struct device *dev, void *priv)
> @@ -125,10 +135,16 @@ static int s32_dwmac_probe(struct platform_device *pdev)
> "dt configuration failed\n");
>
> /* PHY interface mode control reg */
> - gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
> - if (IS_ERR(gmac->ctrl_sts))
> - return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
> - "S32CC config region is missing\n");
> + gmac->sts_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
> + "nxp,phy-sel", 1, &gmac->sts_offset);
> + if (gmac->sts_regmap == ERR_PTR(-EPROBE_DEFER))
> + return PTR_ERR(gmac->sts_regmap);
> + if (IS_ERR(gmac->sts_regmap)) {
> + gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
> + if (IS_ERR(gmac->ctrl_sts))
> + return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
> + "S32CC config region is missing\n");
> + }
>
> /* tx clock */
> gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");
> --
> 2.51.0
>
Reviewed-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Thanks.
/Jan
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
2026-01-28 9:53 [PATCH v5 0/3] s32g: Use a syscon for GPR Dan Carpenter
2026-01-28 9:54 ` [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
@ 2026-01-28 9:54 ` Dan Carpenter
2026-01-29 5:10 ` [v5,2/3] " Jakub Kicinski
2026-01-28 9:54 ` [PATCH v5 3/3] dts: s32g: Add GPR syscon region Dan Carpenter
2 siblings, 1 reply; 6+ messages in thread
From: Dan Carpenter @ 2026-01-28 9:54 UTC (permalink / raw)
To: Jan Petrous
Cc: s32, Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
netdev, devicetree, linux-kernel, linaro-s32, imx
The S32 chipsets have a GPR region which has a miscellaneous registers
including the GMAC_0_CTRL_STS register. Originally, this code accessed
that register in a sort of ad-hoc way, but it's cleaner to use a
syscon interface to access these registers.
We still need to maintain the old method of accessing the GMAC register
but using a syscon will let us access other registers more cleanly.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
v5: Add Rob's R-b tag
v4: Fix the formatting issue Rob pointed out
v3: Better documentation about what GMAC_0_CTRL_STS register does.
v2: Add the vendor prefix to the phandle
Fix the documentation
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 2b8b74c5feec..65633b10e49e 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
@@ -32,6 +32,18 @@ properties:
- description: Main GMAC registers
- description: GMAC PHY mode control register
+ nxp,phy-sel:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the GPR syscon node
+ - description: offset of PHY selection register
+ description:
+ This phandle points to the GMAC_0_CTRL_STS register which controls the
+ GMAC_0 configuration options. The register lets you select the PHY
+ interface and the PHY mode. It also controls if the FTM_0 or FTM_1
+ FlexTimer Modules connect to GMAC_O.
+
interrupts:
maxItems: 1
@@ -74,6 +86,7 @@ examples:
compatible = "nxp,s32g2-dwmac";
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [v5,2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
2026-01-28 9:54 ` [PATCH v5 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
@ 2026-01-29 5:10 ` Jakub Kicinski
0 siblings, 0 replies; 6+ messages in thread
From: Jakub Kicinski @ 2026-01-29 5:10 UTC (permalink / raw)
To: dan.carpenter
Cc: Jakub Kicinski, jan.petrous, davem, edumazet, pabeni,
mcoquelin.stm32, imx, chester62515, mbrugger, netdev, s32,
conor+dt, andrew+netdev, robh, kernel, linux-stm32, shawnguo,
linux-kernel, ghennadi.procopciuc, linaro-s32, linux-arm-kernel,
alexandre.torgue, krzk+dt, devicetree, festevam, s.hauer
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
This commit adds the nxp,phy-sel property to the S32 DWMAC binding,
allowing access to the GMAC_0_CTRL_STS register via a syscon interface
instead of the previous ad-hoc direct register mapping.
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..65633b10e49e 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
[ ... ]
> + nxp,phy-sel:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: phandle to the GPR syscon node
> + - description: offset of PHY selection register
> + description:
> + This phandle points to the GMAC_0_CTRL_STS register which controls the
> + GMAC_0 configuration options. The register lets you select the PHY
> + interface and the PHY mode. It also controls if the FTM_0 or FTM_1
> + FlexTimer Modules connect to GMAC_O.
^^^^^^
Should this be GMAC_0 (with a zero) instead of GMAC_O (with a letter O)?
The rest of the description uses GMAC_0_CTRL_STS and GMAC_0 consistently.
--
pw-bot: cr
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 3/3] dts: s32g: Add GPR syscon region
2026-01-28 9:53 [PATCH v5 0/3] s32g: Use a syscon for GPR Dan Carpenter
2026-01-28 9:54 ` [PATCH v5 1/3] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
2026-01-28 9:54 ` [PATCH v5 2/3] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
@ 2026-01-28 9:54 ` Dan Carpenter
2 siblings, 0 replies; 6+ messages in thread
From: Dan Carpenter @ 2026-01-28 9:54 UTC (permalink / raw)
To: Chester Lin
Cc: Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel,
imx, devicetree, linux-kernel, netdev, linaro-s32
Add the GPR syscon region for the s32 chipset.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v5: no change
v4: no change
v3: no change
v2: Remove #address-cells and #size-cells
arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..b954952d962b 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon@4007c000 {
+ compatible = "nxp,s32g2-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ };
+
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -731,6 +736,7 @@ gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..be03db737384 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 {
};
};
+ gpr: syscon@4007c000 {
+ compatible = "nxp,s32g3-gpr", "syscon";
+ reg = <0x4007c000 0x3000>;
+ };
+
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
@@ -808,6 +813,7 @@ gmac0: ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
+ nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread