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Tue, 6 Oct 2026 07:21:48 -0700 From: Petr Machata To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Wentao Liang" , Subject: [PATCH net 0/2] mlxsw: Fix port range register leak Date: Tue, 6 Oct 2026 16:21:27 +0200 Message-ID: X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F63:EE_|CYYPR12MB8731:EE_ X-MS-Office365-Filtering-Correlation-Id: 401beede-b255-4676-f494-08df23b53f09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|82310400026|376014|36860700016|18002099003|10067099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: T61XiP8V6KNQElBxiiFiBzfjHXraLt453LS8APz9Pc/PqDx2+4zz0HAwWtMsip4OSKHRYGyZO61FXJTcXY6PD8ziBtWh23/cIA0236Bm9UFrW8SxH1Ufr62D1x+F+eXQkWD7pCZSq7N4S3A1OCz4g9gvYfU/WmK8MOvVPE4Mkr1lfEZlhlYQZYrC8StksVLcM8DZOm33lB8NyDTd85odDb97QedFaE7vJu1UtfM7FgPHjFlgPhV0IvgcZXtKmgsLpOU3QzkqDPFeaQZbkL48S/NyF1f6atXnpqOT/PI2k3WEW2DDGORlZqIc6bcIn2d6nhDHLwCbpN4E+mAWTsdqGbdtAHzBuG8A29cNjkzCajj0aUGzPlQKeuzob9qEifUxBBbxaQDPty+ETm+0f/5sKqfxQDwiYJ0JuU0o2rIeDTKcq+aMitqrOPA/UtUJJCE1l9r/ggIoFqDSb568conz6Gk7bvJKcQ/bgQEHCtwRs14NDEbMI+bkbmlLir8dPQ/1/w+YFfaYPwnck1Pjwvug3SiSEqhfTOzLOOV3hja7+F3EQla3gBtxDK42+rFw7a4LBPOMKJKqDyi4LzDJlyYz5QSTMAaq0pN0JLJf/aiX1/xMLNYJDZ87TjVZgDnpRemh4mj7ue6WKaUJu8eXISwO/wwLDkccPN2zabeyODh1gQJJ6CdlXScJ2/KxsD6MpS3ug+coTbAnFoFAxHXvVwLPYA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(82310400026)(376014)(36860700016)(18002099003)(10067099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zR2Ytik44K6oODu+Z4xSqhzTHPebUgjK+Jc3+4fyn/zgH581yaTbYbiUrJDg8jQFH7N8YZFOngTnbaKm4tmDdtRgNhx4J07b8KVPhPw46uieZ/A+5Om4JW2+YWlzTn0Db26MX1zBgpxOZUalWA1/izTlWIrQcnvutBo0wcLzrTPLugWaAxwGwiyfG27HRRz3zTRPHfnfut33sneoUOpocHD7sydYJzyp/0ZOO+zfJm8utUPlcCH8jqWpq8I+QvJx10WJhD+v4GWuFFYwJ5wwuRuBIs7hsFsn5wJj5UQCOTdG/A8FPovTWTdwPIWvFahbRthvD+TuJAifYlmz2lQoz1GGQcK2q52sLbQy4RfPQP7shbPHd1DBjpdvfB1StupND3DcUpV+C54iXU/498/Mh1YSCyAlHNusfdkEJAbqKCaegIBNQPYtI3EZ7Fbf0wVy X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2026 14:22:26.2072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 401beede-b255-4676-f494-08df23b53f09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8731 When the mlxsw driver parses a port range template rule, it acquires the actual port range registers. The parsing is only done to determine the element usage, so the registers can be deallocated right away, but this is never done, and the registers are leaked. Plug this leak and add a selftest that would have caught it. Petr Machata (2): mlxsw: spectrum_flower: Fix port range register leak in tmplt_create() selftests: mlxsw: Test port range occupancy on template create .../net/ethernet/mellanox/mlxsw/spectrum.h | 2 ++ .../ethernet/mellanox/mlxsw/spectrum_acl.c | 10 +++++-- .../ethernet/mellanox/mlxsw/spectrum_flower.c | 9 +++++-- .../drivers/net/mlxsw/port_range_occ.sh | 26 +++++++++++++++++++ 4 files changed, 43 insertions(+), 4 deletions(-) -- 2.55.0