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Mon, 09 Nov 2026 20:24:12 -0800 (PST) Received: from cantal.lan ([58.136.75.91]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3751fe32276sm3116950eec.8.2026.11.09.20.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 20:24:11 -0800 (PST) From: James Clark To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones Cc: Siddharth Vadapalli , Roger Quadros , Sebastian Andrzej Siewior , Martin Kaistra , Vadim Fedorenko , Rahul Sharma , Robert Nelson , Nishanth Menon , Vignesh Raghavendra , Chintan Vankar , netdev@vger.kernel.org, devicetree@vger.kernel.org, mfd@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next 0/3] net: ethernet: ti: am65-cpts: add PTP_SYS_OFFSET_PRECISE support Date: Tue, 10 Nov 2026 11:24:00 +0700 Message-ID: X-Mailer: git-send-email 2.56.0 X-Mailing-List: netdev@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds PTP_SYS_OFFSET_PRECISE to the CPTS driver for TI K3 SoCs. This brings a similar hardware-supported level of precision to the transfer of time from the PHC to the system clock as already exists for the transfer of time into the PHC, whether over the network using hardware timestamping of packets, or from a GNSS receiver using hardware timestamping of its PPS signal. The system counter of these SoCs, the Global Timebase Counter (GTC), can export one of its bits on a push event output. The Time Sync Router can route that output to a CPTS hardware timestamp input. The CPTS then timestamps edges that fall at known counter values, so each timestamp gives an exact pair of PHC time and system counter value. This is similar to the PCIe PTM integration on these SoCs, where a selected bit of the PTM timer drives a push input of the PCIe CPTS. Patch 1 adds a syscon compatible for the GTC register frame that selects the bit. Patch 2 adds a ti,gtc-push property to the CPTS binding, which names that syscon and the CPTS input. Patch 3 implements getcrosststamp. The series does not set up the Time Sync Router. Mainline has no binding for it on the J722S, so for now a board overlay sets the route, as it does for ti,pps. With Rahul Sharma's proposed binding for the router [1], the CPTS node could select the route itself. ti,gtc-push would stay the same. Tested on a BeagleY-AI (AM67A / J722S), a BeagleBone AI-64 (TDA4VM / J721E) and a BeaglePlay (AM625). With this series, phc2sys steering the system clock from a free-running PHC sees an offset that never varies by more than 1ns, whether idle or under memory load. Since the PHC and the system counter run from the same oscillator, this is the noise of PTP_SYS_OFFSET_PRECISE itself. Without this series, phc2sys falls back to PTP_SYS_OFFSET_EXTENDED and the offset has a standard deviation of 2.5 to 10ns when idle and 22 to 31ns under load, with excursions of up to 200ns. When the PHC is disciplined (by ptp4l or ts2phc, to within 4 to 7ns rms of its reference), the offset seen by phc2sys with this series has a standard deviation of 2 to 5ns, whether idle or under memory load. Without this series, it has a standard deviation of 5 to 12ns when idle and 22 to 29ns under load, again with excursions of up to 200ns. PTP_SYS_OFFSET_PRECISE has a fixed bias, the capture delay of the push event through the Time Sync Router and the CPTS input (about 11ns, plus an undocumented delay in the GTC), which did not measurably change under any load or CPU clock. This series does not correct for this bias. The driver similarly does not correct for timestamping delay on extts inputs, nor for ingress/egress latency in hardware timestamping of packets. It turns out that the bias in PTP_SYS_OFFSET_PRECISE and the delay in extts timestamping largely cancel each other out. The offset of PTP_SYS_OFFSET_EXTENDED relative to PTP_SYS_OFFSET_PRECISE is about -50ns when idle, and moves by up to 40ns with memory load and by up to 60ns with CPU clock frequency. The implementation was also stress tested by using ntpperf to load the CPTS (-D 0 -M at 15,000/s and -N 0 at 5,000/s). No errors or wrong pairs were seen. To try it on a BeagleY-AI, apply this overlay: // SPDX-License-Identifier: GPL-2.0-only OR MIT /dts-v1/; /plugin/; &{/} { #address-cells = <2>; #size-cells = <2>; wkup_gtc: syscon@a80000 { compatible = "ti,am654-gtc", "syscon"; reg = <0x0 0xa80000 0x0 0x400>; }; }; &cbass_main { #address-cells = <2>; #size-cells = <2>; timesync_router: pinctrl@a40000 { compatible = "pinctrl-single"; reg = <0x0 0xa40000 0x0 0x400>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x000107ff>; pinctrl-names = "default"; pinctrl-0 = <>c_push_route>; gtc_push_route: gtc-push-route { /* input 11 (GTC push event) -> output 14 (CPTS HW5_TS_PUSH) */ pinctrl-single,pins = <0x3c 0x1000b>; }; }; }; &{/bus@f0000/ethernet@8000000/cpts@3d000} { ti,gtc-push = <&wkup_gtc 4>; }; I used an LLM coding assistant to help prepare this series. [1] https://lore.kernel.org/all/20260828100615.1700223-1-r-sharma3@ti.com/ James Clark (3): dt-bindings: mfd: syscon: add ti,am654-gtc dt-bindings: net: ti,k3-am654-cpts: add ti,gtc-push net: ethernet: ti: am65-cpts: implement PTP_SYS_OFFSET_PRECISE .../devicetree/bindings/mfd/syscon.yaml | 1 + .../bindings/net/ti,k3-am654-cpts.yaml | 17 ++ drivers/net/ethernet/ti/am65-cpts.c | 289 ++++++++++++++++++ 3 files changed, 307 insertions(+) base-commit: fa5196392691051963726787944db872420dfa75 -- 2.56.0