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([2a0d:3344:5521:6b10:58fd:68f:7756:389d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f63ec7f55sm32452689f8f.18.2026.07.21.00.22.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 00:22:19 -0700 (PDT) Message-ID: Date: Tue, 21 Jul 2026 09:22:17 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v10 0/4] net: stmmac: eic7700: add eth1 variant support and update delay bindings To: lizhi2@eswincomputing.com, devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.chevallier@bootlin.com Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, pritesh.patel@einfochips.com, weishangjuan@eswincomputing.com, horms@kernel.org References: <20260707064033.1265-1-lizhi2@eswincomputing.com> From: Paolo Abeni Content-Language: en-US In-Reply-To: <20260707064033.1265-1-lizhi2@eswincomputing.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/7/26 8:40 AM, lizhi2@eswincomputing.com wrote: > From: Zhi Li > > This series updates Ethernet support for the ESWIN EIC7700 SoC, > including support for the eth1 MAC variant. > > The series includes DT binding updates and stmmac glue driver updates > for the EIC7700 Ethernet controller. > > The changes include: > - Update the tx-internal-delay-ps binding property from a fixed enum > list to a range-based definition, and make it optional with the > corresponding driver update. > > - Add support for the EIC7700 eth1 MAC variant, which has > silicon-specific RX sampling behavior and TX timing characteristics. > A dedicated compatible string is introduced for this hardware variant, > and the driver applies the required RX clock inversion handling and > timing adjustments. > > Due to silicon characteristics, the eth1 interface has a fixed TX > internal delay of approximately 2 ns and an RX sampling skew of 4-5 ns > that cannot be compensated solely by standard RGMII delay settings. > The binding models the effective TX delay range of this variant, while > the driver handles the required hardware-specific timing configuration. > > Only the DT bindings and driver patches are included in this series. The > DTS changes are intentionally omitted for the following reasons: > - The HSP bus infrastructure is being introduced by Pinkesh Vaghela's > DT series [0], currently under review. > - The HSPCRG clock/reset series [1] provides additional infrastructure > for the HSP subsystem. > > Once these dependencies are merged, a follow-up DT series will enable > Ethernet, USB, eMMC, and SD across the HSP bus. > > Reference: > [0] https://lore.kernel.org/lkml/20260706081055.1126275-1-pinkesh.vaghela@einfochips.com/ > [1] https://lore.kernel.org/all/20260605060730.1605-1-dongxuyang@eswincomputing.com/ Applied, thanks! /P