[PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign

[PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign

[Ivan Vecera]

The output pin phase adjustment functions incorrectly negate the phase
compensation value.

Per the ZL3073x datasheet, the output phase compensation register is
simply a signed two's complement integer where:
 - Positive values move the phase later in time
 - Negative values move the phase earlier in time

No negation is required. The erroneous negation caused phase adjustments
to be applied in the wrong direction.

Note that input pin phase adjustment correctly uses negation because the
hardware has an inverted convention for input references (positive moves
phase earlier, negative moves phase later).

Fixes: 6287262f761e ("dpll: zl3073x: Add support to adjust phase")
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
---
 drivers/dpll/zl3073x/dpll.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c
index 9879d85d29af..a8001c976038 100644
--- a/drivers/dpll/zl3073x/dpll.c
+++ b/drivers/dpll/zl3073x/dpll.c
@@ -1039,10 +1039,8 @@ zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
 	out_id = zl3073x_output_pin_out_get(pin->id);
 	out = zl3073x_out_state_get(zldev, out_id);
 
-	/* Convert value to ps and reverse two's complement negation applied
-	 * during 'set'
-	 */
-	*phase_adjust = -out->phase_comp * pin->phase_gran;
+	/* The value in the register is expressed in half synth clock cycles. */
+	*phase_adjust = out->phase_comp * pin->phase_gran;
 
 	return 0;
 }
@@ -1064,10 +1062,8 @@ zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin,
 	out_id = zl3073x_output_pin_out_get(pin->id);
 	out = *zl3073x_out_state_get(zldev, out_id);
 
-	/* The value in the register is stored as two's complement negation
-	 * of requested value and expressed in half synth clock cycles.
-	 */
-	out.phase_comp = -phase_adjust / pin->phase_gran;
+	/* The value in the register is expressed in half synth clock cycles. */
+	out.phase_comp = phase_adjust / pin->phase_gran;
 
 	/* Update output configuration from mailbox */
 	return zl3073x_out_state_set(zldev, out_id, &out);
-- 
2.52.0

Re: [PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign

[Vadim Fedorenko]

On 05/02/2026 18:10, Ivan Vecera wrote:
> The output pin phase adjustment functions incorrectly negate the phase
> compensation value.
> 
> Per the ZL3073x datasheet, the output phase compensation register is
> simply a signed two's complement integer where:
>   - Positive values move the phase later in time
>   - Negative values move the phase earlier in time
> 
> No negation is required. The erroneous negation caused phase adjustments
> to be applied in the wrong direction.
> 
> Note that input pin phase adjustment correctly uses negation because the
> hardware has an inverted convention for input references (positive moves
> phase earlier, negative moves phase later).

Is it common for DPLLs to act this way?

> 
> Fixes: 6287262f761e ("dpll: zl3073x: Add support to adjust phase")
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>

Anyways, with datasheet info being correctly read, the change LGTM
Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>

Re: [PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign

[Ivan Vecera]

On 2/6/26 3:04 PM, Vadim Fedorenko wrote:
> On 05/02/2026 18:10, Ivan Vecera wrote:
>> The output pin phase adjustment functions incorrectly negate the phase
>> compensation value.
>>
>> Per the ZL3073x datasheet, the output phase compensation register is
>> simply a signed two's complement integer where:
>>   - Positive values move the phase later in time
>>   - Negative values move the phase earlier in time
>>
>> No negation is required. The erroneous negation caused phase adjustments
>> to be applied in the wrong direction.
>>
>> Note that input pin phase adjustment correctly uses negation because the
>> hardware has an inverted convention for input references (positive moves
>> phase earlier, negative moves phase later).
> 
> Is it common for DPLLs to act this way?

I don't now if this is common for DPLLs but for ZL3073x family chips the
datasheet says:

<cite>
ref_phase_offset_compensation:
==============================
Phase offset compensation for references. The value is specified as a
signed two's complement, in units of ps. A positive value moves the
phase of any DPLL that locks to this reference earlier in time (more to
the left on a scope). A negative value moves the phase of any DPLL that
locks to this reference later in time (more to the right on a scope).

output_phase_compensation:
==========================
Output phase shift, expressed in 1/2 synth clock cycles. Two-complement
signed integer.
A positive value moves the phase of the output later in time (more to
the right on a scope). A negative value moves the phase earlier in time
(more to the left on a scope).
</cite>

So for input pins the value must be negated, while for output pins it
is not.
>>
>> Fixes: 6287262f761e ("dpll: zl3073x: Add support to adjust phase")
>> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
> 
> Anyways, with datasheet info being correctly read, the change LGTM
> Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
> 
Thanks,
Ivan

Re: [PATCH net] dpll: zl3073x: Fix output pin phase adjustment sign

[patchwork-bot+netdevbpf]

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Thu,  5 Feb 2026 19:10:55 +0100 you wrote:
> The output pin phase adjustment functions incorrectly negate the phase
> compensation value.
> 
> Per the ZL3073x datasheet, the output phase compensation register is
> simply a signed two's complement integer where:
>  - Positive values move the phase later in time
>  - Negative values move the phase earlier in time
> 
> [...]

Here is the summary with links:
  - [net] dpll: zl3073x: Fix output pin phase adjustment sign
    https://git.kernel.org/netdev/net/c/5d41f95f5d0b

You are awesome, thank you!
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