From: Paolo Abeni <pabeni@redhat.com>
To: Huacai Chen <chenhuacai@loongson.cn>,
Huacai Chen <chenhuacai@kernel.org>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>
Cc: Yanteng Si <si.yanteng@linux.dev>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Jose Abreu <joabreu@synopsys.com>,
Serge Semin <fancer.lancer@gmail.com>,
loongarch@lists.linux.dev, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Hongliang Wang <wanghongliang@loongson.cn>
Subject: Re: [PATCH V2 net-next] net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz
Date: Thu, 5 Feb 2026 15:39:28 +0100 [thread overview]
Message-ID: <d4329f05-b9c1-46ef-b2fe-a078f9618892@redhat.com> (raw)
In-Reply-To: <20260203062901.2158236-1-chenhuacai@loongson.cn>
On 2/3/26 7:29 AM, Huacai Chen wrote:
> Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
> and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
> Loongson STMMAC use 125MHz clocks and need 62 freq division to within
> 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
> to 100-150MHz, otherwise some PHYs may link fail.
>
> Cc: stable@vger.kernel.org
> Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson")
> Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This should go via the 'net' tree right?
/P
next prev parent reply other threads:[~2026-02-05 14:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-03 6:29 [PATCH V2 net-next] net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz Huacai Chen
2026-02-05 14:39 ` Paolo Abeni [this message]
2026-02-06 2:30 ` patchwork-bot+netdevbpf
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