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Fri, 10 Jan 2025 14:05:05 GMT Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A6AE5805F; Fri, 10 Jan 2025 14:05:05 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B06C5805D; Fri, 10 Jan 2025 14:05:01 +0000 (GMT) Received: from [9.61.139.65] (unknown [9.61.139.65]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTP; Fri, 10 Jan 2025 14:05:01 +0000 (GMT) Message-ID: Date: Fri, 10 Jan 2025 08:05:00 -0600 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: =?UTF-8?B?UmU6IOWbnuimhjog5Zue6KaGOiBbUEFUQ0ggdjIgMDUvMTBdIEFSTTog?= =?UTF-8?Q?dts=3A_aspeed=3A_system1=3A_Add_RGMII_support?= To: Jacky Chou , Andrew Lunn Cc: "andrew+netdev@lunn.ch" , "andrew@codeconstruct.com.au" , "conor+dt@kernel.org" , "davem@davemloft.net" , "devicetree@vger.kernel.org" , "eajames@linux.ibm.com" , "edumazet@google.com" , "joel@jms.id.au" , "krzk+dt@kernel.org" , "kuba@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "minyard@acm.org" , "netdev@vger.kernel.org" , "openipmi-developer@lists.sourceforge.net" , "pabeni@redhat.com" , "ratbert@faraday-tech.com" , "robh@kernel.org" References: <0c42bbd8-c09d-407b-8400-d69a82f7b248@lunn.ch> <59116067-0caa-4666-b8dc-9b3125a37e6f@lunn.ch> <8042c67c-04d3-41c0-9e88-8ce99839f70b@lunn.ch> Content-Language: en-US From: Ninad Palsule In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: MeLhr7O8jd-8ePzsQCuKHXgiTwl7M1Df X-Proofpoint-GUID: pZcWXJhEmsFDJ3lvW_ilyppMTvEAo7cz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501100110 Hi Jacky, On 1/10/25 03:15, Jacky Chou wrote: > Hi Andrew, > > Thank you for your reply. > >>> I think the code already exist in the mainline: >>> https://github.com/torvalds/linux/blob/master/drivers/clk/clk-ast2600. >>> c#L595 >>> >>> It is configuring SCU register in the ast2600 SOC to introduce delays. >>> The mac is part of the SOC. >> I could be reading this wrong, but that appears to create a gated clock. >> >> hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, >> scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0, >> &aspeed_g6_clk_lock); >> >> /** >> * clk_hw_register_gate - register a gate clock with the clock framework >> * @dev: device that is registering this clock >> * @name: name of this clock >> * @parent_name: name of this clock's parent >> * @flags: framework-specific flags for this clock >> * @reg: register address to control gating of this clock >> * @bit_idx: which bit in the register controls gating of this clock >> * @clk_gate_flags: gate-specific flags for this clock >> * @lock: shared register lock for this clock */ >> >> There is nothing here about writing a value into @reg at creation time to give >> it a default value. If you look at the vendor code, it has extra writes, but i don't >> see anything like that in mainline. > Agree. You are right. This part is used to create a gated clock. > We will configure these RGMII delay in bootloader like U-boot. > Therefore, here does not configure delay again. > > Currently, the delay of RGMII is configured in SCU region not in ftgma100 region. > And I studied ethernet-controller.yaml file, as you said, it has defined about rgmii > delay property for MAC side to set. > My plan is that I will move this delay setting to ftgmac100 driver from SCU. > Add a SCU syscon property for ftgmac100 driver configures the RGMII delay. > > // aspeed-g6.dtsi > mac0: ethernet@1e660000 { > compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; > reg = <0x1e660000 0x180>; > interrupts = ; > clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; > aspeed,scu = <&syscon>; ------> add > status = "disabled"; > }; > > Because AST2600 MAC1/2 RGMII delay setting in scu region is combined to one 32-bit register, > MAC3/4 is also. I will also use 'aliase' to get MAC index to set delay in scu. > > // aspeed-g6.dtsi > aliases { > .......... > mac0 = &mac0; > mac1 = &mac1; > mac2 = &mac2; > mac4 = &mac3; > }; > > Then, we can use rx-internal-delay-ps and tx-internal-delay-ps property to configure delay > In ftgmac100 driver. Thanks. When are you planning to push this change? I might need to hold on to mac changes until then. Regards, Ninad > > If you have any questions, please let me know. Thank you. > > Thanks, > Jacky