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From: "Frank Wunderlich" Message-ID: TLS-Required: No Subject: Re: [PATCH v4 net-next 5/5] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap" To: "Vladimir Oltean" Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, "Daniel Golle" , "Horatiu Vultur" , "=?utf-8?B?QmriiJriiI9ybiBNb3Jr?=" , "Andrew Lunn" , "Heiner Kallweit" , "Russell King" , "David S. Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Matthias Brugger" , "AngeloGioacchino Del Regno" , "Eric Woudstra" , "Alexander Couzens" , "Chester A. Unal" , "DENG Qingfang" , "Sean Wang" , "Felix Fietkau" In-Reply-To: <20260326215404.krh6v3mmnqdlndli@skbuf> References: <20260119091220.1493761-1-vladimir.oltean@nxp.com> <20260119091220.1493761-6-vladimir.oltean@nxp.com> <20260326215404.krh6v3mmnqdlndli@skbuf> X-Migadu-Flow: FLOW_OUT Hi Vladimir Thanks for the patch and sorry for my delay...i was away this weekend so = i was not able to test. traffic works again (but there is only read now) and this is the result o= f your debug prints: root@bpi-r3:~# dmesg | grep SGMSYS_QPHY_WRAP_CTRL [ 2.706963] SGMSYS_QPHY_WRAP_CTRL =3D 0x501, intending to write 0x500 [ 9.134081] SGMSYS_QPHY_WRAP_CTRL =3D 0x500, intending to write 0x500 R3/mt7986 has 2 MAC, and switch is on the first, so value will change, no= t sure why this is different. i have not found SGMSYS_QPHY_WRAP_CTRL or something related with polarity= in ethernet/mac-=20 (drivers/net/ethernet/mediatek/mtk_eth_soc.c)=20or switch-driver (drivers= /net/dsa/mt7530{,-mdio}.c) in case they manipulate this register too (of course they should not). Al= so looked into the pcs-handling in both drivers, but see nothing related to polarity. And looked for poss= ible duplicate register const definition (other name for 0xec). regards Frank Am 26. M=C3=A4rz 2026 um 22:54 schrieb "Vladimir Oltean" : >=20 >=20Hi Frank, >=20 >=20On Tue, Mar 24, 2026 at 06:36:44AM +0000, Frank Wunderlich wrote: >=20 >=20>=20 >=20> Hi, > >=20=20 >=20> looks like this patch breaks BPI-R3 serdes between mt7986 SoC and = mt7531 switch in 7.0 (6.19 is ok). > > in ethtool i see only tx on mac but no rx. if i revert this patch i = can ping through dsa-ports again. > >=20=20 >=20> i did not completely understanding the code with the default-pol a= s it is now splitted between rx and tx. > >=20=20 >=20> mt7986 and this board does not have mediatek,pnswap set, so the fi= nal regmap_update_bits writes val=3D0, > > before there was only write to this register on invert mode...but i = guess this should not break. Maybe some > > kind of timing issue between mac and switch? > >=20=20 >=20> maybe reverting this patch skips changes made here: > > bde1ae2d52ab 2026-01-19 net: pcs: pcs-mtk-lynxi: pass SGMIISYS OF no= de to PCS > >=20=20 >=20> I resend as last try was sending as html (option "always send as t= ext" in webmailer seems to be ignored > > somehow, had to choose "unformatted" in this response too). > >=20=20 >=20> regards Frank > >=20 >=20Sorry for the delay. >=20 >=20If writing val=3D0 breaks the link, I'm curious > (a) whether it still breaks if we don't write anything at all > (b) what was the register value originally >=20 >=20Could you please test the patch below and let me know what it prints, > and whether traffic passes with it applied? >=20 >=20-- >8 -- > diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-= lynxi.c > index c12f8087af9b..5c5f45b93b82 100644 > --- a/drivers/net/pcs/pcs-mtk-lynxi.c > +++ b/drivers/net/pcs/pcs-mtk-lynxi.c > @@ -126,7 +126,7 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_l= ynxi *mpcs, > { > struct fwnode_handle *fwnode =3D mpcs->fwnode, *pcs_fwnode; > unsigned int pol, default_pol =3D PHY_POL_NORMAL; > - unsigned int val =3D 0; > + unsigned int val =3D 0, tmp; > int ret; >=20=20 >=20 if (fwnode_property_read_bool(fwnode, "mediatek,pnswap")) > @@ -153,8 +153,14 @@ static int mtk_pcs_config_polarity(struct mtk_pcs_= lynxi *mpcs, > if (pol =3D=3D PHY_POL_INVERT) > val |=3D SGMII_PN_SWAP_TX; >=20=20 >=20- return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, > - SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val); > + ret =3D regmap_read(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, &tmp); > + if (ret) > + return ret; > + > + pr_err("SGMSYS_QPHY_WRAP_CTRL =3D 0x%x, intending to write 0x%lx\n", > + tmp, (tmp & ~(SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX)) | val); > + > + return 0; > } >=20=20 >=20 static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned in= t neg_mode, > -- >8 -- >=20 regards=20Frank