Re: [PATCH net-next 3/5] dpll: zl3073x: Implement phase offset monitor feature

[Ivan Vecera <ivecera@redhat.com>]

On 15. 07. 25 3:02 odp., Paolo Abeni wrote:
> On 7/10/25 5:38 PM, Ivan Vecera wrote:
>> @@ -536,8 +539,38 @@ zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin,
>>   		return 0;
>>   	}
>>   
>> -	/* Report the latest measured phase offset for the connected ref */
>> -	*phase_offset = pin->phase_offset * DPLL_PHASE_OFFSET_DIVIDER;
>> +	ref_phase = pin->phase_offset;
>> +
>> +	/* The DPLL being locked to a higher freq than the current ref
>> +	 * the phase offset is modded to the period of the signal
>> +	 * the dpll is locked to.
>> +	 */
>> +	if (ZL3073X_DPLL_REF_IS_VALID(conn_ref) && conn_ref != ref) {
>> +		u32 conn_freq, ref_freq;
>> +
>> +		/* Get frequency of connected ref */
>> +		rc = zl3073x_dpll_input_ref_frequency_get(zldpll, conn_ref,
>> +							  &conn_freq);
>> +		if (rc)
>> +			return rc;
>> +
>> +		/* Get frequency of given ref */
>> +		rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref,
>> +							  &ref_freq);
>> +		if (rc)
>> +			return rc;
>> +
>> +		if (conn_freq > ref_freq) {
>> +			s64 conn_period;
>> +			int div_factor;
>> +
>> +			conn_period = div_s64(PSEC_PER_SEC, conn_freq);
>> +			div_factor = div64_s64(ref_phase, conn_period);
>> +			ref_phase -= conn_period * div_factor;
> 
> It's not obvious to me that the above div64_s64() will yield a 32b value
> for every possible arguments/configuration. Possibly a comment would
> help (or just use s64 for div_factor).

Practically it should not happen due to maximal reference frequency but
it will be safer use s64 here also for div_factor..

Will fix in v2.

Thanks,
Ivan