From: Andrew Lunn <andrew@lunn.ch>
To: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Cc: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, hkallweit1@gmail.com,
linux@armlinux.org.uk, netdev@vger.kernel.org,
UNGLinuxDriver@microchip.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 2/3] net: ethernet: oa_tc6: deliver the PHY interrupt to phylib
Date: Wed, 2 Sep 2026 02:43:36 +0200 [thread overview]
Message-ID: <dbb77cce-b574-42d9-8a26-a12a0446d1b9@lunn.ch> (raw)
In-Reply-To: <20260901130948.212914-3-parthiban.veerasooran@microchip.com>
On Tue, Sep 01, 2026 at 06:39:47PM +0530, Parthiban Veerasooran wrote:
> The integrated PHY has no dedicated interrupt line; its interrupt is
> delivered in-band as the PHYINT bit in STATUS0, which raises the MAC-PHY
> SPI interrupt via the extended status. phy_mac_interrupt() only triggers
> a link-status re-read and cannot make the PHY driver read and acknowledge
> its interrupt source registers, so expose the PHY interrupt to phylib as a
> nested virtual IRQ instead.
>
> Use dummy_irq_chip as the irqchip, map a virtual IRQ and assign it to
> phydev->irq before phy_connect_direct() so phylib enters interrupt mode
> and uses the PHY driver's config_intr/handle_interrupt. Unmask PHYINT in
> INT_MASK0, and when it is seen in the extended status, dispatch
> handle_nested_irq() synchronously from the sleepable threaded IRQ. PHYINT
> is level triggered, so acking the PHY source there clears it before the
> next data chunk, avoiding a storm.
9.2.8.7 PHYINT
Physical Layer Interrupt. When set, this bit indicates a service
request from the underlying physical layer block. Many physical
layer implementations support an interrupt output for signaling
events to the station controller. This bit is optional and will be
implemented only if the underlying physical layer supports
generating interrupts to a higher level. When implemented, this bit
shall be cleared by acknowledging the underlying physical layer
interrupt source(s). When not implemented, this bit shall be
reserved with a read- only value of zero.
At the moment, phylib is polling the PHY. That is guaranteed to work.
The standard indicates this interrupt is optional. It might not be
implemented. phylib assumes that if there is an interrupt, the
interrupt works, and it does not poll. So any hardware which does not
implement this interrupt is now broken.
Please find a way not to break other devices.
Andrew
---
pw-bot: cr
next prev parent reply other threads:[~2026-09-02 0:43 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 13:09 [PATCH net-next 0/3] net: microchip_t1s: fix collision detection on PLCA status change Parthiban Veerasooran
2026-09-01 13:09 ` [PATCH net-next 1/3] net: phy: " Parthiban Veerasooran
2026-09-01 13:09 ` [PATCH net-next 2/3] net: ethernet: oa_tc6: deliver the PHY interrupt to phylib Parthiban Veerasooran
2026-09-02 0:30 ` Andrew Lunn
2026-09-03 13:23 ` Parthiban Veerasooran
2026-09-03 14:14 ` Andrew Lunn
2026-09-02 0:43 ` Andrew Lunn [this message]
2026-09-03 13:02 ` Parthiban Veerasooran
2026-09-03 13:54 ` Andrew Lunn
2026-09-01 13:09 ` [PATCH net-next 3/3] net: phy: microchip_t1s: fix collision detection for LAN867X Rev.D0 Parthiban Veerasooran
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