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From: "Frank Wunderlich" Message-ID: TLS-Required: No Subject: Re: [PATCH v4 net-next 5/5] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap" To: "Vladimir Oltean" , netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, "Daniel Golle" , "Horatiu Vultur" , "=?utf-8?B?QmrDuHJuIE1vcms=?=" , "Andrew Lunn" , "Heiner Kallweit" , "Russell King" , "David S. Miller" , "Eric Dumazet" , "Jakub Kicinski" , "Paolo Abeni" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Matthias Brugger" , "AngeloGioacchino Del Regno" , "Eric Woudstra" , "Alexander Couzens" , "Chester A. Unal" , "DENG Qingfang" , "Sean Wang" , "Felix Fietkau" In-Reply-To: <20260119091220.1493761-6-vladimir.oltean@nxp.com> References: <20260119091220.1493761-1-vladimir.oltean@nxp.com> <20260119091220.1493761-6-vladimir.oltean@nxp.com> X-Migadu-Flow: FLOW_OUT Hi, looks like this patch breaks BPI-R3 serdes between mt7986 SoC and mt7531 = switch in 7.0 (6.19 is ok). in ethtool i see only tx on mac but no rx. if i revert this patch i can p= ing through dsa-ports again. i did not completely understanding the code with the default-pol as it is= now splitted between rx and tx. mt7986 and this board does not have mediatek,pnswap set, so the final re= gmap_update_bits writes val=3D0, before there was only write to this register on invert mode...but i guess= this should not break. Maybe some kind of timing issue between mac and switch? maybe reverting this patch skips changes made here: bde1ae2d52ab 2026-01-19 net: pcs: pcs-mtk-lynxi: pass SGMIISYS OF node to= PCS I resend as last try was sending as html (option "always send as text" in= webmailer seems to be ignored somehow, had to choose "unformatted" in this response too). regards Frank Am 19. Januar 2026 um 10:12 schrieb "Vladimir Oltean" : >=20 >=20Prefer the new "rx-polarity" and "tx-polarity" properties, which in t= his > case have the advantage that polarity inversion can be specified per > direction (and per protocol, although this isn't useful here). >=20 >=20We use the vendor specific ones as fallback if the standard descripti= on > doesn't exist. >=20 >=20Daniel, referring to the Mediatek SDK, clarifies that the combined > SGMII_PN_SWAP_TX_RX register field should be split like this: bit 0 is > TX and bit 1 is RX: > https://lore.kernel.org/linux-phy/aSW--slbJWpXK0nv@makrotopia.org/ >=20 >=20Suggested-by: Daniel Golle > Signed-off-by: Vladimir Oltean > --- > v3->v4: none > v2->v3: s/GENERIC_PHY_COMMON_PROPS/PHY_COMMON_PROPS/ > v1->v2: patch is new >=20 >=20 drivers/net/pcs/Kconfig | 1 + > drivers/net/pcs/pcs-mtk-lynxi.c | 50 +++++++++++++++++++++++++++++---- > 2 files changed, 45 insertions(+), 6 deletions(-) >=20 >=20diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig > index ecbc3530e780..e417fd66f660 100644 > --- a/drivers/net/pcs/Kconfig > +++ b/drivers/net/pcs/Kconfig > @@ -20,6 +20,7 @@ config PCS_LYNX >=20=20 >=20 config PCS_MTK_LYNXI > tristate > + select PHY_COMMON_PROPS > select REGMAP > help > This module provides helpers to phylink for managing the LynxI PCS > diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-= lynxi.c > index 7f719da5812e..74dbce205f71 100644 > --- a/drivers/net/pcs/pcs-mtk-lynxi.c > +++ b/drivers/net/pcs/pcs-mtk-lynxi.c > @@ -11,6 +11,7 @@ > #include > #include > #include > +#include > #include > #include >=20=20 >=20@@ -62,8 +63,9 @@ >=20=20 >=20 /* Register to QPHY wrapper control */ > #define SGMSYS_QPHY_WRAP_CTRL 0xec > -#define SGMII_PN_SWAP_MASK GENMASK(1, 0) > -#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1)) > +#define SGMII_PN_SWAP_RX BIT(1) > +#define SGMII_PN_SWAP_TX BIT(0) > + >=20=20 >=20 /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap and= associated > * data > @@ -121,6 +123,42 @@ static void mtk_pcs_lynxi_get_state(struct phylink= _pcs *pcs, > FIELD_GET(SGMII_LPA, adv)); > } >=20=20 >=20+static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs, > + phy_interface_t interface) > +{ > + struct fwnode_handle *fwnode =3D mpcs->fwnode, *pcs_fwnode; > + unsigned int pol, default_pol =3D PHY_POL_NORMAL; > + unsigned int val =3D 0; > + int ret; > + > + if (fwnode_property_read_bool(fwnode, "mediatek,pnswap")) > + default_pol =3D PHY_POL_INVERT; > + > + pcs_fwnode =3D fwnode_get_named_child_node(fwnode, "pcs"); > + > + ret =3D phy_get_rx_polarity(pcs_fwnode, phy_modes(interface), > + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), > + default_pol, &pol); > + if (ret) { > + fwnode_handle_put(pcs_fwnode); > + return ret; > + } > + if (pol =3D=3D PHY_POL_INVERT) > + val |=3D SGMII_PN_SWAP_RX; > + > + ret =3D phy_get_tx_polarity(pcs_fwnode, phy_modes(interface), > + BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT), > + default_pol, &pol); > + fwnode_handle_put(pcs_fwnode); > + if (ret) > + return ret; > + if (pol =3D=3D PHY_POL_INVERT) > + val |=3D SGMII_PN_SWAP_TX; > + > + return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, > + SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val); > +} > + > static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int = neg_mode, > phy_interface_t interface, > const unsigned long *advertising, > @@ -130,6 +168,7 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs = *pcs, unsigned int neg_mode, > bool mode_changed =3D false, changed; > unsigned int rgc3, sgm_mode, bmcr; > int advertise, link_timer; > + int ret; >=20=20 >=20 advertise =3D phylink_mii_c22_pcs_encode_advertisement(interface, > advertising); > @@ -169,10 +208,9 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs= *pcs, unsigned int neg_mode, > regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0, > SGMII_SW_RESET); >=20=20 >=20- if (fwnode_property_read_bool(mpcs->fwnode, "mediatek,pnswap")) > - regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL, > - SGMII_PN_SWAP_MASK, > - SGMII_PN_SWAP_TX_RX); > + ret =3D mtk_pcs_config_polarity(mpcs, interface); > + if (ret) > + return ret; >=20=20 >=20 if (interface =3D=3D PHY_INTERFACE_MODE_2500BASEX) > rgc3 =3D SGMII_PHY_SPEED_3_125G; > --=20 >=202.34.1 >=20 regards=20Frank