From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A7443E492; Wed, 8 Jul 2026 12:29:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783513753; cv=pass; b=ONGvUjXaRu5OvqxO+mPDZcJ3bMzR6l00BNPR+j2TF4kmgHJAus86If2b7M0civ1cMG46CQmQ1y8xeOGLa0GmL2OHcb3ZAJubsVHqyC9neiK8wgm4oC4kslWPVwvtQyEJ/r7jzhZroN+L8w/myy3iT2ibjgX8GTkfYgCrSvBUHDw= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783513753; c=relaxed/simple; bh=hNxi3I7/AjHCOFwddBwrPLCzilKwHtStVx43u1/rLDU=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=B6GJNT0p95tBMNxy6Mwk/yI/l9DM4cm35P3X2SoGuZSfp6+QGM32VCmzcwB7VEc3lESA9xVOfAROvPItJMLyjVHAlzp1mOz8gN4fs2rl+rxapyXJKE24qhrE7JH3q3SFEG59ZSTgE7YyIWlkSbnSAUUhRN2ogZOcxxL3PL3TP3A= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=louisalexis.eyraud@collabora.com header.b=h6bRTRdC; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=louisalexis.eyraud@collabora.com header.b="h6bRTRdC" ARC-Seal: i=1; a=rsa-sha256; t=1783513718; cv=none; d=zohomail.com; s=zohoarc; b=dmk5QtOSqylrvj1O3kiWrYo5jOBHtMdHnLgwpkgK/OeYJcaygEFc908bdEjJcwFL8duOUKfqaBXGOC+SRZSCHufdPYaYi9PLGNM8bRxhcFLFnofEyRbsoTBNyULAcUmy14ns31kQof4IQPKzXk0XT8RQSPfV+HzfwpBImuFSjoI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1783513718; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=QCvu92owlqFigfn30SNdUxyYgy9yaDdYJCfmb5B8+hA=; b=TUVE5cAWvaUKOL/7VkXKNsheZFAnqsjFihWOVi5E8/Lf3tOGzoa/GO+f4zkq6Tnoe+IopkOelUVU/gUR72HtIh4Cuvzg1DGca0jE5//B0m0MTT5dIGFCJ1yRRuscfQIB3dWcW5Zc8zDQl5E1y6DCGRw/JiBf04r8cl6BSbEceZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=louisalexis.eyraud@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1783513718; s=zohomail; d=collabora.com; i=louisalexis.eyraud@collabora.com; h=Message-ID:Subject:Subject:From:From:To:To:Cc:Cc:Date:Date:In-Reply-To:References:Content-Type:Content-Transfer-Encoding:MIME-Version:Message-Id:Reply-To; bh=QCvu92owlqFigfn30SNdUxyYgy9yaDdYJCfmb5B8+hA=; b=h6bRTRdCEfGpTsXUdZushp4txBmx8lAJ2sgujTR/sAo9JJSBSlceJfhV4vZkaYkY rtrySVIeuYT8F3dzrFdpWNZza1RcYhMupJRR8ITAYN7hBDSSyKEo6vz8FjpFDY09sUP Nkn2iZd7+RFWywEK1Pwpr2rr8GIUn8Cc/b1GUQZQ= Received: by mx.zohomail.com with SMTPS id 1783513715946883.1743690151607; Wed, 8 Jul 2026 05:28:35 -0700 (PDT) Message-ID: Subject: Re: [PATCH net-next 5/6] net: stmmac: mediatek: add support for TX deallocation adjustment feature From: Louis-Alexis Eyraud To: Maxime Chevallier , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Coquelin , Alexandre Torgue Cc: rmk+kernel@armlinux.org.uk, kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Date: Wed, 08 Jul 2026 14:28:30 +0200 In-Reply-To: <2a421449-01eb-4066-8c19-d554ff8e4f6e@bootlin.com> References: <20260707-dwmac-mediatek-mt8189-v1-0-17f345eaaca3@collabora.com> <20260707-dwmac-mediatek-mt8189-v1-5-17f345eaaca3@collabora.com> <2a421449-01eb-4066-8c19-d554ff8e4f6e@bootlin.com> Organization: Collabora Ltd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.60.2 (3.60.2-1.fc44) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External Hi Maxime, On Tue, 2026-07-07 at 11:11 +0200, Maxime Chevallier wrote: > Hi, >=20 > On 7/7/26 10:21, Louis-Alexis Eyraud wrote: > > The MT8189 SoC has in the Ethernet control 0 register from the > > peripheral configuration (pericfg) additional bits to adjust the TX > > deallocation. > >=20 > > In preparation of MT8189 SoC support, add its definition, use in > > the > > set_delay_v2 callback, and a support flag in the platform data. >=20 > Can you elaborate a bit on this ? I don't quite get what you mean by > "tx deallocation", this seems to have to do with RGMII timings from > the register access pattern, but the local boolean flag for the > feature > is named "use_stage_fine", I'm failing to connect all the dots here > with the different terminology in use :( >=20 The data sheets I have, don't have info regarding this register, so I'll try to get more and improve commit and/or code description. I'll also check if the register definition name is consistent (downstream driver and upstream u-boot use this stage fine term). The use_stage_fine feature flag could be renamed anyway to match what it does. > >=20 > > Signed-off-by: Louis-Alexis Eyraud > > > > --- > > =C2=A0.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c=C2=A0=C2=A0 | 25 > > ++++++++++++++++------ > > =C2=A01 file changed, 19 insertions(+), 6 deletions(-) > >=20 > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > index bcc0baef3f71..6b0a42b5839f 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > @@ -37,7 +37,8 @@ > > =C2=A0#define ETH_FINE_DLY_RXC BIT(0) > > =C2=A0 > > =C2=A0/* Peri Configuration register for mt8189 */ > > -#define MT8189_CTRL0_TXC_OUT_OP BIT(20) > > +#define MT8189_CTRL0_TXC_OUT_OP BIT(20) >=20 > Extra whitespace inserted here :) >=20 Oops, to be fixed in v2 Regards, Louis-Alexis > Thanks, >=20 > Maxime