Re: [PATCH iwl-net v4] ice: fix missing dpll notifications for SW pins

[Ivan Vecera <ivecera@redhat.com>]

On 3/19/26 9:52 PM, Petr Oros wrote:
> The SMA/U.FL pin redesign (commit 2dd5d03c77e2 ("ice: redesign dpll
> sma/u.fl pins control")) introduced software-controlled pins that wrap
> backing CGU input/output pins, but never updated the notification and
> data paths to propagate pin events to these SW wrappers.
> 
> There are three problems:
> 
> 1) ice_dpll_notify_changes() sends dpll_pin_change_ntf() only for the
>     direct CGU input pin stored in d->active_input.  When the active
>     input changes, SW pins (SMA/U.FL) that wrap the old or new active
>     input never receive a change notification.  As a result, userspace
>     consumers such as synce4l that monitor SMA pins via dpll netlink
>     never learn when the pin state transitions (e.g. from SELECTABLE to
>     CONNECTED).
> 
> 2) ice_dpll_phase_offset_get() returns p->phase_offset for non-active
>     SW pins, but this field is never updated for SW pins.  The PPS phase
>     offset monitor updates the backing CGU input's phase_offset
>     (p->input->phase_offset), not the SW pin's own field.  As a result
>     non-active SW pins always report zero phase offset even when the
>     backing CGU input has valid PPS measurements.
> 
> 3) ice_dpll_pins_notify_mask() does not propagate phase offset change
>     notifications to SW pins either.  When a HW CGU pin gets a phase
>     offset change notification, the SMA/U.FL pin wrapping it is never
>     notified, so userspace consumers (ts2phc, synce4l) monitoring SW
>     pins via dpll netlink never receive phase offset updates.
> 
> Fix all three by:
> 
>   - In ice_dpll_phase_offset_get(), return the backing CGU input's
>     phase_offset for input-direction SW pins instead of the SW pin's own
>     (always zero) field.
> 
>   - Introduce ice_dpll_pin_ntf(), a thin wrapper around
>     dpll_pin_change_ntf() that also sends notifications to any
>     registered SMA/U.FL pin whose backing CGU input matches.  Replace
>     all direct dpll_pin_change_ntf() calls in the periodic notification
>     paths with ice_dpll_pin_ntf(), so SW pins are automatically notified
>     whenever their backing HW pin is.
> 
> Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> Signed-off-by: Petr Oros <poros@redhat.com>
> ---
> v4:
>   - expanded scope to also fix phase offset reporting and phase offset
>     notifications for SW pins (problems 2 and 3 above)
>   - replaced ice_dpll_sw_pin_needs_notify() with ice_dpll_pin_ntf(),
>     a unified wrapper that covers all notification paths
>   - squashed into a single patch
> v3: https://lore.kernel.org/all/20260220140700.2910174-1-poros@redhat.com/
>   - added kdoc for ice_dpll_sw_pin_needs_notify() helper
> v2: https://lore.kernel.org/all/20260219131500.2271897-1-poros@redhat.com/
>   - extracted ice_dpll_sw_pin_needs_notify() helper for readability
>   - moved loop variable into for() scope
> v1: https://lore.kernel.org/all/20260218211414.1411163-1-poros@redhat.com/
> ---
>   drivers/net/ethernet/intel/ice/ice_dpll.c | 47 +++++++++++++++++------
>   1 file changed, 36 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 62f75701d65205..5cfa19da099bfc 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -1915,7 +1915,10 @@ ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
>   				       d->active_input == p->input->pin))
>   		*phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
>   	else if (d->phase_offset_monitor_period)
> -		*phase_offset = p->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
> +		*phase_offset = (p->input &&
> +				 p->direction == DPLL_PIN_DIRECTION_INPUT ?
> +				 p->input->phase_offset :
> +				 p->phase_offset) * ICE_DPLL_PHASE_OFFSET_FACTOR;
>   	else
>   		*phase_offset = 0;
>   	mutex_unlock(&pf->dplls.lock);
> @@ -2609,6 +2612,27 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
>   	return pci_get_dsn(pf->pdev);
>   }
>   
> +/**
> + * ice_dpll_pin_ntf - notify pin change including any SW pin wrappers
> + * @dplls: pointer to dplls struct
> + * @pin: the dpll_pin that changed
> + *
> + * Send a change notification for @pin and for any registered SMA/U.FL pin
> + * whose backing CGU input matches @pin.
> + */
> +static void ice_dpll_pin_ntf(struct ice_dplls *dplls, struct dpll_pin *pin)
> +{
> +	dpll_pin_change_ntf(pin);
> +	for (int i = 0; i < ICE_DPLL_PIN_SW_NUM; i++) {
> +		if (dplls->sma[i].pin && dplls->sma[i].input &&
> +		    dplls->sma[i].input->pin == pin)
> +			dpll_pin_change_ntf(dplls->sma[i].pin);
> +		if (dplls->ufl[i].pin && dplls->ufl[i].input &&
> +		    dplls->ufl[i].input->pin == pin)
> +			dpll_pin_change_ntf(dplls->ufl[i].pin);
> +	}
> +}
> +
>   /**
>    * ice_dpll_notify_changes - notify dpll subsystem about changes
>    * @d: pointer do dpll
> @@ -2617,6 +2641,7 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
>    */
>   static void ice_dpll_notify_changes(struct ice_dpll *d)
>   {
> +	struct ice_dplls *dplls = &d->pf->dplls;
>   	bool pin_notified = false;
>   
>   	if (d->prev_dpll_state != d->dpll_state) {
> @@ -2625,17 +2650,17 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
>   	}
>   	if (d->prev_input != d->active_input) {
>   		if (d->prev_input)
> -			dpll_pin_change_ntf(d->prev_input);
> +			ice_dpll_pin_ntf(dplls, d->prev_input);
>   		d->prev_input = d->active_input;
>   		if (d->active_input) {
> -			dpll_pin_change_ntf(d->active_input);
> +			ice_dpll_pin_ntf(dplls, d->active_input);
>   			pin_notified = true;
>   		}
>   	}
>   	if (d->prev_phase_offset != d->phase_offset) {
>   		d->prev_phase_offset = d->phase_offset;
>   		if (!pin_notified && d->active_input)
> -			dpll_pin_change_ntf(d->active_input);
> +			ice_dpll_pin_ntf(dplls, d->active_input);
>   	}
>   }
>   
> @@ -2664,6 +2689,7 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf)
>   
>   /**
>    * ice_dpll_pins_notify_mask - notify dpll subsystem about bulk pin changes
> + * @dplls: pointer to dplls struct
>    * @pins: array of ice_dpll_pin pointers registered within dpll subsystem
>    * @pin_num: number of pins
>    * @phase_offset_ntf_mask: bitmask of pin indexes to notify
> @@ -2673,15 +2699,14 @@ static bool ice_dpll_is_pps_phase_monitor(struct ice_pf *pf)
>    *
>    * Context: Must be called while pf->dplls.lock is released.
>    */
> -static void ice_dpll_pins_notify_mask(struct ice_dpll_pin *pins,
> +static void ice_dpll_pins_notify_mask(struct ice_dplls *dplls,
> +				      struct ice_dpll_pin *pins,
>   				      u8 pin_num,
>   				      u32 phase_offset_ntf_mask)
>   {
> -	int i = 0;
> -
> -	for (i = 0; i < pin_num; i++)
> -		if (phase_offset_ntf_mask & (1 << i))
> -			dpll_pin_change_ntf(pins[i].pin);
> +	for (int i = 0; i < pin_num; i++)
> +		if (phase_offset_ntf_mask & BIT(i))
> +			ice_dpll_pin_ntf(dplls, pins[i].pin);
>   }
>   
>   /**
> @@ -2857,7 +2882,7 @@ static void ice_dpll_periodic_work(struct kthread_work *work)
>   	ice_dpll_notify_changes(de);
>   	ice_dpll_notify_changes(dp);
>   	if (phase_offset_ntf)
> -		ice_dpll_pins_notify_mask(d->inputs, d->num_inputs,
> +		ice_dpll_pins_notify_mask(d, d->inputs, d->num_inputs,
>   					  phase_offset_ntf);
>   
>   resched:

Good catch, Petr.

Reviewed-by: Ivan Vecera <ivecera@redhat.com>