From: Matthias Brugger <mbrugger@suse.com>
To: jan.petrous@oss.nxp.com, Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Chester Lin <chester62515@gmail.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
NXP S32 Linux Team <s32@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
devicetree@vger.kernel.org
Subject: Re: [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs
Date: Wed, 21 Jan 2026 17:15:08 +0100 [thread overview]
Message-ID: <ea1af06b-fb85-4131-bad3-00d12c032c1f@suse.com> (raw)
In-Reply-To: <20260121-dwmac_multi_irq-v2-3-3b829230d071@oss.nxp.com>
On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The GMAC Ethernet controller found on S32G2/S32G3 and S32R45
> contains up to 5 RX and 5 TX channels.
> It can operate in two interrupt modes:
>
> 1) Sharing IRQ mode: only MAC IRQ line is used
> for all channels.
>
> 2) Multiple IRQ mode: every channel uses two IRQ lines,
> one for RX and second for TX.
>
> Specify all IRQ twins for all channels.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++---
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++---
> 2 files changed, 46 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..5a553d503137 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
> * NXP S32G2 SoC family
> *
> * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 {
> reg = <0x4033c000 0x2000>, /* gmac IP */
> <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index eff7673e7f34..e1f248d3aedb 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
> *
> * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> * Ciprian Costea <ciprianmarian.costea@nxp.com>
> @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 {
> reg = <0x4033c000 0x2000>, /* gmac IP */
> <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> status = "disabled";
>
next prev parent reply other threads:[~2026-01-21 16:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
2026-01-21 16:15 ` Matthias Brugger [this message]
2026-01-21 14:23 ` [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
2026-01-21 16:16 ` Matthias Brugger
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