* [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers
@ 2026-01-21 14:23 Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-01-21 14:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, Jan Petrous (OSS)
The stmmac core supports two interrupt modes, controlled by the
flag STMMAC_FLAG_MULTI_MSI_EN:
- When the flag is set, the driver uses multi-channel IRQ mode (Multi-IRQ).
- Otherwise, a single IRQ line is requested (aka MAC-IRQ):
static int stmmac_request_irq(struct net_device *dev)
{
/* Request the IRQ lines */
if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN)
ret = stmmac_request_irq_multi_msi(dev);
else
ret = stmmac_request_irq_single(dev);
}
At present, only PCI drivers (Intel and Loongson) make use of the Multi-IRQ
mode. This concept can be extended to DT-based embedded glue drivers
(dwmac-xxx.c).
This series adds support for reading per-channel IRQs from the DT node and
reuses the existing STMMAC_FLAG_MULTI_MSI_EN flag to enable multi-IRQ
operation in platform drivers.
The final decision if Multi-IRQ gets enabled remains on glue driver
to allow implementing any reguirements/limitions the focused platform
needs.
NXP S32G2/S32G3/S32R SoCs integrate the DWMAC IP with multi-channel
interrupt support. The dwmac-s32.c driver change is provided as an example of
enabling multi-IRQ mode for non-PCI drivers.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
Changes in v2:
- Fixed incorrect buffer len for 'rx-queue-%d' property check
- Added backward compatibility to not break old settings
- Fixed DT example in yaml
- Link to v1: https://lore.kernel.org/r/20251214-dwmac_multi_irq-v1-0-36562ab0e9f7@oss.nxp.com
---
Jan Petrous (OSS) (4):
net: stmmac: platform: read channels irq
dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
arm64: dts: s32: set Ethernet channel irqs
stmmac: s32: enable support for Multi-IRQ mode
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 ++++++++++++--
arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 ++++++++++++--
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 ++++++-
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 38 +++++++++++++++++++-
5 files changed, 132 insertions(+), 13 deletions(-)
---
base-commit: cb015814f8b6eebcbb8e46e111d108892c5e6821
change-id: 20251209-dwmac_multi_irq-9d8f60462cc1
Best regards,
--
Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
@ 2026-01-21 14:23 ` Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-01-21 14:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode
for platform glue drivers.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 38 +++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8979a50b5507..f10a691b8add 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk);
int stmmac_get_platform_resources(struct platform_device *pdev,
struct stmmac_resources *stmmac_res)
{
+ char name[16];
+ int i;
+
memset(stmmac_res, 0, sizeof(*stmmac_res));
/* Get IRQ information early to have an ability to ask for deferred
@@ -743,7 +746,40 @@ int stmmac_get_platform_resources(struct platform_device *pdev,
stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0);
- return PTR_ERR_OR_ZERO(stmmac_res->addr);
+ if (IS_ERR(stmmac_res->addr))
+ return PTR_ERR(stmmac_res->addr);
+
+ /* RX channels irq */
+ for (i = 0; i < MTL_MAX_RX_QUEUES; i++) {
+ scnprintf(name, sizeof(name), "rx-queue-%d", i);
+ stmmac_res->rx_irq[i] = platform_get_irq_byname_optional(pdev,
+ name);
+ if (stmmac_res->rx_irq[i] < 0) {
+ if (stmmac_res->rx_irq[i] == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i);
+
+ /* Stop on first unset rx-queue-%i property member */
+ break;
+ }
+ }
+
+ /* TX channels irq */
+ for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
+ scnprintf(name, sizeof(name), "tx-queue-%d", i);
+ stmmac_res->tx_irq[i] = platform_get_irq_byname_optional(pdev,
+ name);
+ if (stmmac_res->tx_irq[i] < 0) {
+ if (stmmac_res->tx_irq[i] == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i);
+
+ /* Stop on first unset tx-queue-%i property member */
+ break;
+ }
+ }
+
+ return 0;
}
EXPORT_SYMBOL_GPL(stmmac_get_platform_resources);
--
2.47.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
@ 2026-01-21 14:23 ` Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
3 siblings, 1 reply; 9+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-01-21 14:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
set them to allow using Multi-IRQ mode when supported.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++---
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 2b8b74c5feec..e1ebc3bea095 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright 2021-2024 NXP
+# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
@@ -33,10 +33,22 @@ properties:
- description: GMAC PHY mode control register
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 11
interrupt-names:
- const: macirq
+ - items:
+ - const: macirq
+ - const: rx-queue-0
+ - const: tx-queue-0
+ - const: rx-queue-1
+ - const: tx-queue-1
+ - const: rx-queue-2
+ - const: tx-queue-2
+ - const: rx-queue-3
+ - const: tx-queue-3
+ - const: rx-queue-4
+ - const: tx-queue-4
clocks:
items:
@@ -75,8 +87,28 @@ examples:
reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
--
2.47.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
@ 2026-01-21 14:23 ` Jan Petrous via B4 Relay
2026-01-21 16:15 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
3 siblings, 1 reply; 9+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-01-21 14:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The GMAC Ethernet controller found on S32G2/S32G3 and S32R45
contains up to 5 RX and 5 TX channels.
It can operate in two interrupt modes:
1) Sharing IRQ mode: only MAC IRQ line is used
for all channels.
2) Multiple IRQ mode: every channel uses two IRQ lines,
one for RX and second for TX.
Specify all IRQ twins for all channels.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++---
arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++---
2 files changed, 46 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..5a553d503137 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 {
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index eff7673e7f34..e1f248d3aedb 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 {
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
--
2.47.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
` (2 preceding siblings ...)
2026-01-21 14:23 ` [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
@ 2026-01-21 14:23 ` Jan Petrous via B4 Relay
2026-01-21 16:16 ` Matthias Brugger
3 siblings, 1 reply; 9+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-01-21 14:23 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
To get enabled Multi-IRQ mode, the driver checks:
1) property of 'snps,mtl-xx-config' subnode
defines 'snps,xx-queues-to-use' bigger then one, ie:
ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
...
snps,mtl-rx-config = <&mtl_rx_setup>;
...
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <2>;
};
2) queue based IRQs are set, ie:
ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
...
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 0: tx, rx */
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 1: tx, rx */
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq",
"tx-queue-0", "rx-queue-0",
"tx-queue-1", "rx-queue-1";
If those prerequisites are met, the driver switch to Multi-IRQ mode,
using per-queue IRQs for rx/tx data pathr:
[ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQ) selected
Now the driver owns all queues IRQs:
root@s32g399aevb3:~# grep eth /proc/interrupts
29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0
31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1
32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2
33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3
34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4
35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0
36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1
37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2
38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3
39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4
Otherwise, if one of the prerequisite don't met, the driver
continue with MAC IRQ mode:
[ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected
And only MAC IRQ will be attached:
root@s32g399aevb3:~# grep eth /proc/interrupts
29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
What represents the original MAC IRQ mode and is fully backward
compatible.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
index 5a485ee98fa7..823700219534 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
@@ -2,7 +2,7 @@
/*
* NXP S32G/R GMAC glue layer
*
- * Copyright 2019-2024 NXP
+ * Copyright 2019-2026 NXP
*
*/
@@ -149,6 +149,17 @@ static int s32_dwmac_probe(struct platform_device *pdev)
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
+
+ /* Check for multi-IRQ config. Assumption: symetrical rx/tx queues */
+ if (plat->rx_queues_to_use > 1 &&
+ (res.rx_irq[0] >= 0 || res.tx_irq[0] >= 0)) {
+ plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
+ dev_info(dev, "Multi-IRQ mode (per queue IRQ) selected\n");
+ } else {
+ dev_info(dev, "MAC IRQ mode selected\n");
+ }
+
+ plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
plat->rx_fifo_size = 20480;
plat->tx_fifo_size = 20480;
--
2.47.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
@ 2026-01-21 16:14 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2026-01-21 16:14 UTC (permalink / raw)
To: jan.petrous, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Chester Lin, Ghennadi Procopciuc, NXP S32 Linux Team, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree
On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode
> for platform glue drivers.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 38 +++++++++++++++++++++-
> 1 file changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> index 8979a50b5507..f10a691b8add 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> @@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk);
> int stmmac_get_platform_resources(struct platform_device *pdev,
> struct stmmac_resources *stmmac_res)
> {
> + char name[16];
> + int i;
> +
> memset(stmmac_res, 0, sizeof(*stmmac_res));
>
> /* Get IRQ information early to have an ability to ask for deferred
> @@ -743,7 +746,40 @@ int stmmac_get_platform_resources(struct platform_device *pdev,
>
> stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0);
>
> - return PTR_ERR_OR_ZERO(stmmac_res->addr);
> + if (IS_ERR(stmmac_res->addr))
> + return PTR_ERR(stmmac_res->addr);
> +
> + /* RX channels irq */
> + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) {
> + scnprintf(name, sizeof(name), "rx-queue-%d", i);
> + stmmac_res->rx_irq[i] = platform_get_irq_byname_optional(pdev,
> + name);
> + if (stmmac_res->rx_irq[i] < 0) {
> + if (stmmac_res->rx_irq[i] == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> + dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i);
> +
> + /* Stop on first unset rx-queue-%i property member */
> + break;
> + }
> + }
> +
> + /* TX channels irq */
> + for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
> + scnprintf(name, sizeof(name), "tx-queue-%d", i);
> + stmmac_res->tx_irq[i] = platform_get_irq_byname_optional(pdev,
> + name);
> + if (stmmac_res->tx_irq[i] < 0) {
> + if (stmmac_res->tx_irq[i] == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> + dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i);
> +
> + /* Stop on first unset tx-queue-%i property member */
> + break;
> + }
> + }
> +
> + return 0;
> }
> EXPORT_SYMBOL_GPL(stmmac_get_platform_resources);
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
2026-01-21 14:23 ` [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
@ 2026-01-21 16:14 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2026-01-21 16:14 UTC (permalink / raw)
To: jan.petrous, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Chester Lin, Ghennadi Procopciuc, NXP S32 Linux Team, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree
On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> set them to allow using Multi-IRQ mode when supported.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 42 +++++++++++++++++++---
> 1 file changed, 37 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> index 2b8b74c5feec..e1ebc3bea095 100644
> --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> -# Copyright 2021-2024 NXP
> +# Copyright 2021-2026 NXP
> %YAML 1.2
> ---
> $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
> @@ -33,10 +33,22 @@ properties:
> - description: GMAC PHY mode control register
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 11
>
> interrupt-names:
> - const: macirq
> + - items:
> + - const: macirq
> + - const: rx-queue-0
> + - const: tx-queue-0
> + - const: rx-queue-1
> + - const: tx-queue-1
> + - const: rx-queue-2
> + - const: tx-queue-2
> + - const: rx-queue-3
> + - const: tx-queue-3
> + - const: rx-queue-4
> + - const: tx-queue-4
>
> clocks:
> items:
> @@ -75,8 +87,28 @@ examples:
> reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
> <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs
2026-01-21 14:23 ` [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
@ 2026-01-21 16:15 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2026-01-21 16:15 UTC (permalink / raw)
To: jan.petrous, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Chester Lin, Ghennadi Procopciuc, NXP S32 Linux Team, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree
On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The GMAC Ethernet controller found on S32G2/S32G3 and S32R45
> contains up to 5 RX and 5 TX channels.
> It can operate in two interrupt modes:
>
> 1) Sharing IRQ mode: only MAC IRQ line is used
> for all channels.
>
> 2) Multiple IRQ mode: every channel uses two IRQ lines,
> one for RX and second for TX.
>
> Specify all IRQ twins for all channels.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++---
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++---
> 2 files changed, 46 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..5a553d503137 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
> * NXP S32G2 SoC family
> *
> * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 {
> reg = <0x4033c000 0x2000>, /* gmac IP */
> <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index eff7673e7f34..e1f248d3aedb 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
> *
> * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
> * Ciprian Costea <ciprianmarian.costea@nxp.com>
> @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 {
> reg = <0x4033c000 0x2000>, /* gmac IP */
> <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 0: tx, rx */
> + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 1: tx, rx */
> + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 2: tx, rx */
> + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 3: tx, rx */
> + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + /* CHN 4: tx, rx */
> + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0", "rx-queue-0",
> + "tx-queue-1", "rx-queue-1",
> + "tx-queue-2", "rx-queue-2",
> + "tx-queue-3", "rx-queue-3",
> + "tx-queue-4", "rx-queue-4";
> snps,mtl-rx-config = <&mtl_rx_setup>;
> snps,mtl-tx-config = <&mtl_tx_setup>;
> status = "disabled";
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode
2026-01-21 14:23 ` [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
@ 2026-01-21 16:16 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2026-01-21 16:16 UTC (permalink / raw)
To: jan.petrous, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Chester Lin, Ghennadi Procopciuc, NXP S32 Linux Team, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree
On 21/01/2026 15:23, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> To get enabled Multi-IRQ mode, the driver checks:
>
> 1) property of 'snps,mtl-xx-config' subnode
> defines 'snps,xx-queues-to-use' bigger then one, ie:
>
> ethernet@4033c000 {
> compatible = "nxp,s32g2-dwmac";
> ...
> snps,mtl-rx-config = <&mtl_rx_setup>;
> ...
>
> mtl_rx_setup: rx-queues-config {
> snps,rx-queues-to-use = <2>;
> };
>
> 2) queue based IRQs are set, ie:
>
> ethernet@4033c000 {
> compatible = "nxp,s32g2-dwmac";
> ...
> interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> /* CHN 0: tx, rx */
> <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> /* CHN 1: tx, rx */
> <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq",
> "tx-queue-0", "rx-queue-0",
> "tx-queue-1", "rx-queue-1";
>
> If those prerequisites are met, the driver switch to Multi-IRQ mode,
> using per-queue IRQs for rx/tx data pathr:
>
> [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQ) selected
>
> Now the driver owns all queues IRQs:
>
> root@s32g399aevb3:~# grep eth /proc/interrupts
> 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
> 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0
> 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1
> 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2
> 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3
> 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4
> 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0
> 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1
> 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2
> 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3
> 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4
>
> Otherwise, if one of the prerequisite don't met, the driver
> continue with MAC IRQ mode:
>
> [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected
>
> And only MAC IRQ will be attached:
>
> root@s32g399aevb3:~# grep eth /proc/interrupts
> 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
>
> What represents the original MAC IRQ mode and is fully backward
> compatible.
>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> index 5a485ee98fa7..823700219534 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
> @@ -2,7 +2,7 @@
> /*
> * NXP S32G/R GMAC glue layer
> *
> - * Copyright 2019-2024 NXP
> + * Copyright 2019-2026 NXP
> *
> */
>
> @@ -149,6 +149,17 @@ static int s32_dwmac_probe(struct platform_device *pdev)
> plat->core_type = DWMAC_CORE_GMAC4;
> plat->pmt = 1;
> plat->flags |= STMMAC_FLAG_SPH_DISABLE;
> +
> + /* Check for multi-IRQ config. Assumption: symetrical rx/tx queues */
> + if (plat->rx_queues_to_use > 1 &&
> + (res.rx_irq[0] >= 0 || res.tx_irq[0] >= 0)) {
> + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
> + dev_info(dev, "Multi-IRQ mode (per queue IRQ) selected\n");
> + } else {
> + dev_info(dev, "MAC IRQ mode selected\n");
> + }
> +
> + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
> plat->rx_fifo_size = 20480;
> plat->tx_fifo_size = 20480;
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2026-01-21 16:16 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-21 14:23 [PATCH RFC v2 0/4] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-01-21 14:23 ` [PATCH RFC v2 1/4] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
2026-01-21 16:14 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 3/4] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
2026-01-21 16:15 ` Matthias Brugger
2026-01-21 14:23 ` [PATCH RFC v2 4/4] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
2026-01-21 16:16 ` Matthias Brugger
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