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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jason Gunthorpe , Jay Cornwall , Felix Kuehling , Niklas Schnelle , Alexander Schmidt , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org, Gerd Bayer Date: Thu, 06 Nov 2025 13:16:18 +0100 In-Reply-To: <20251106101917.GB15456@unreal> References: <20251105-mlxatomics-v1-0-10c71649e08d@linux.ibm.com> <20251105-mlxatomics-v1-2-10c71649e08d@linux.ibm.com> <20251106101917.GB15456@unreal> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=StmdKfO0 c=1 sm=1 tr=0 ts=690c9198 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=VwQbUJbxAAAA:8 a=Wqnc6qscLTDqH0BWY3YA:9 a=QEXdDO2ut3YA:10 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-ORIG-GUID: 29QpuMSFYT_8eQVmRwQQ1-q_U7vXVlaq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAxMDAxOCBTYWx0ZWRfX/nw8E0gojWEo cDLMydgSGUHYHoV4feP32uTZ8CH+21y0jeiMp226rS7ElAbdWv9BisKMQIajo500ATC/xmlJj28 8NczSmwZGru7t3D2JnyFgQ8ROdO2zTPOJFJyaOYV55aCvKWcujzaMD8G3+8/uZpqFYxGRI/HZXV y164QJOr1SWfqRY2mIOFrkOftygxj1XLYGdR5cB+cfFs5P6nOETV7AQNNqY+ign4Gw4EiTw/U3u BYwR+RhwJLdoGXqvaI+RYrlal+yYVPCepoyStTf+KBTw4jRP6Gerxkbo1jWcxOiW/pECySUjHN/ T2NTIJMsb/sZCNDDreW/6GVe3KY88aTX1Z88MLrsKKAgO+DnU7tTFliDhBe0zVb9hNSNpI5R/LQ dSHJbN2JlyJW3pzuCS/nuevG6njghw== X-Proofpoint-GUID: tN-EXOMwLVamCrHKgK8oMSNrxEBUos5k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-06_03,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2511010018 On Thu, 2025-11-06 at 12:19 +0200, Leon Romanovsky wrote: > On Wed, Nov 05, 2025 at 06:55:14PM +0100, Gerd Bayer wrote: > > Pass fully populated capability bit-mask requesting support for all 3 > > sizes of AtomicOps at once when attempting to enable AtomicOps for PCI > > function. > >=20 > > When called individually, pci_enable_atomic_ops_to_root() may enable th= e > > device to send requests as soon as one size is supported. According to > > PCIe Spec 7.0 Section 6.15.3.1 support of 32-bit and 64-bit AtomicOps > > completer capabilities are tied together for root-ports. Only the > > 128-bit/CAS completer capabilities is an optional feature, but still we > > might end up end up enabling AtomicOps despite 128-bit/CAS is not > > supported at the root-port. > >=20 > > Signed-off-by: Gerd Bayer > > --- > > drivers/infiniband/hw/mlx5/data_direct.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > >=20 > > diff --git a/drivers/infiniband/hw/mlx5/data_direct.c b/drivers/infinib= and/hw/mlx5/data_direct.c > > index b81ac5709b56f6ac0d9f60572ce7144258fa2794..112185be53f1ccc6a797e12= 9f24432bdc86008ae 100644 > > --- a/drivers/infiniband/hw/mlx5/data_direct.c > > +++ b/drivers/infiniband/hw/mlx5/data_direct.c > > @@ -179,9 +179,9 @@ static int mlx5_data_direct_probe(struct pci_dev *p= dev, const struct pci_device_ > > if (err) > > goto err_disable; > > =20 > > - if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32= ) && > > - pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64= ) && > > - pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP12= 8)) > > + if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32= | > > + PCI_EXP_DEVCAP2_ATOMIC_COMP64 | > > + PCI_EXP_DEVCAP2_ATOMIC_COMP128)) >=20 > I would expect some new define which combines all together, with some > comment why it exists: > #define PCI_ATOMIC_COMP_v7 PCI_EXP_DEVCAP2_ATOMIC_COMP32 | PCI_EXP_DEVCA= P2_ATOMIC_COMP64 | PCI_EXP_DEVCAP2_ATOMIC_COMP128 I see your point. I don't understand the _v7, though. Reading PCI Express spec 7.0 section 6.15.3.1 where for root ports basically just 3 combinations are specified: - No support (all 3 sizes off) - Basic support (32-bit and 64-bit supported) - Full support (Base + 128-bit CAS supported) I would propose to add the following combined defines to include/uapi/linux/pci_regs.h - and then use them here: #PCI_EXP_RP_ATOMIC_COMP_BASE(_SUPPORT) to be the "or" of _COMP32 and _COMP64 and=20 #PCI_EXP_RP_ATOMIC_COMP_FULL(_SUPPORT) to include also 128-bit But I guess that becomes a PCI question then. @Bjorn? > Anyway the change looks right to me. >=20 > Thanks, > Acked-by: Leon Romanovsky