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Thu, 15 Oct 2026 00:15:02 -0700 (PDT) X-Received: by 2002:a17:90b:1d4f:b0:3a8:c0cd:57f3 with SMTP id 98e67ed59e1d1-3ab3a94ff23mr14061583a91.18.1792048501560; Thu, 15 Oct 2026 00:15:01 -0700 (PDT) Received: from [10.217.216.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ac944511c7sm3221300a91.10.2026.10.15.00.14.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Oct 2026 00:15:00 -0700 (PDT) Message-ID: Date: Thu, 15 Oct 2026 12:44:51 +0530 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Richard Cochran , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfX/6ysjU4rRvV+ uqG+odUzh6NHhuJKtbZoZfapHe0PPSOnz0kHSLaYruxtaRnyQ8papr6Y6kPGhAMKPblxHIoqspV z5A6sJ8mTCtidIF14OS5rSg/964lOx4xhqeitHt+daez4Oc7aohm8CFrKqld9WXGH+rEkp7boj7 HnYv7fyo4Na3PTJJ5UyqWHQti8CZ5xFLr8ZiUm6yNbgNKcaqOiqfzMK7ECRVxyJY+wKQe4H41G9 hVVj9nZ9CSUudldEho59UA1wg10pRND5AuebAnAdzXfdaG6cmfJ63e8CaroCLn/qBE/UH61vpqY qj6bXSNko97Fa5A3rEmLxb5VmcIZuFvjRD78tyrFyiSGQBE9I7s9/s0IYxCBGYmOwdLbXIaIP/q WJoTGOSsYwRaGmrL21BFNagYUagqYx8JudLKE+C2ZwGg0Jq6hIDsDi/iq+HCzb/blUAZp9dBNTT BrWp+TNTSYwO+ScIZmA== X-Proofpoint-GUID: erYe46URg2kBjcq7bLak8SeGBo-Bf6wG X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE1MDAyOCBTYWx0ZWRfX8+vJyv+SGv0R LqsuXvheJSMgKjIXjXoMrLojY20rZYqcDStOFypWwyOQh20MJ45Ruf5k0IfKBRAH35/Hqom1d9z ouNCTLXTebl+vtL9lyYWwmkaHokKzoY= X-Proofpoint-ORIG-GUID: erYe46URg2kBjcq7bLak8SeGBo-Bf6wG X-Authority-Analysis: v=2.4 cv=V/noQuni c=1 sm=1 tr=0 ts=6ad07d76 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=CaCc2b9mPIm3Huh5NNcA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610150028 On 6/9/2026 6:58 PM, Konrad Dybcio wrote: > On 6/2/26 5:21 PM, Taniya Das wrote: >> Add pinctrl states for the GP M/N divider clock output pin across >> multiple Qualcomm SoCs: >> >> wire it to the GP M/N clock controller node via pinctrl-0. >> - kodiak (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). >> - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). >> - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). >> >> Signed-off-by: Taniya Das >> --- > > Please squash the pinctrl addition and clock controller node addition > patches together (single logical change), and separate them per-platform Sure Konrad, will take care. -- Thanks, Taniya Das