From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43B11C43381 for ; Thu, 21 Feb 2019 08:50:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0E45A20880 for ; Thu, 21 Feb 2019 08:50:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726545AbfBUIu2 (ORCPT ); Thu, 21 Feb 2019 03:50:28 -0500 Received: from relay9-d.mail.gandi.net ([217.70.183.199]:36387 "EHLO relay9-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725858AbfBUIu2 (ORCPT ); Thu, 21 Feb 2019 03:50:28 -0500 X-Greylist: delayed 150209 seconds by postgrey-1.27 at vger.kernel.org; Thu, 21 Feb 2019 03:50:28 EST X-Originating-IP: 90.88.23.190 Received: from aptenodytes (aaubervilliers-681-1-81-190.w90-88.abo.wanadoo.fr [90.88.23.190]) (Authenticated sender: paul.kocialkowski@bootlin.com) by relay9-d.mail.gandi.net (Postfix) with ESMTPSA id 8FDA2FF81A; Thu, 21 Feb 2019 08:50:26 +0000 (UTC) Message-ID: Subject: Re: Handling an Extra Signal at PHY Reset From: Paul Kocialkowski To: Andrew Lunn Cc: Florian Fainelli , Heiner Kallweit , netdev@vger.kernel.org, Thomas Petazzoni , =?ISO-8859-1?Q?Myl=E8ne?= Josserand Date: Thu, 21 Feb 2019 09:50:26 +0100 In-Reply-To: <20190221014938.GQ14879@lunn.ch> References: <20190221014938.GQ14879@lunn.ch> Organization: Bootlin Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Andrew, On Thu, 2019-02-21 at 02:49 +0100, Andrew Lunn wrote: > On Tue, Feb 19, 2019 at 10:14:20AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > We are dealing with an Ethernet PHY (Marvell 88E1512) that comes with a > > CONFIG pin that must be connected to one of the other pins of the PHY > > to configure the LSB of the PHY address as well as I/O voltages (see > > section 2.18.1 Hardware Configuration of the datasheet). It must be > > connected "soon after reset" for the PHY to be correctly configured. > > Hi Paul > > Turns out the datasheet is publicly available. > > So you can at run-time configure the voltage. Page 2, register 24, bit > 13. > > So back to my last question. Can you address the PHY without using the > switch? Even if it has the wrong voltage? > > If you can, you could set the correct voltage in the probe() function. Thanks for looking into our issue :) I did some more investigating in the meantime, and the hardware logic actually connects our CONFIG and LED pins when the controlling GPIO is open-drain. I can also confirm that it does not prevent contacting the PHY on the MDIO bus, contrary to what I have stated previously. So the important step for us to do is to disconnect the CONFIG and LED pins (at least so we can see our LED blink properly) once the PHY was reset. But we can't really rely on the fact that the pins were connected before PHY reset (e.g. U-Boot may have disconnected them already to use Ethernet) so we still need a way to connect them before the PHY reset from the MDIO bus core hits, and disconnect them after that. Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com