From: Alejandro Lucero Palau <alucerop@amd.com>
To: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>,
alejandro.lucero-palau@amd.com
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-cxl@vger.kernel.org, netdev@vger.kernel.org,
dan.j.williams@intel.com, edward.cree@amd.com,
davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com,
edumazet@google.com, dave.jiang@intel.com
Subject: Re: [PATCH v23 19/22] cxl: Allow region creation by type2 drivers
Date: Thu, 19 Feb 2026 10:48:52 +0000 [thread overview]
Message-ID: <f1725a2d-8b94-4149-a49f-7ea8b40a5d59@amd.com> (raw)
In-Reply-To: <c7024d3a-36e4-4e7e-934c-46c7c26b43ba@amd.com>
On 2/11/26 22:11, Cheatham, Benjamin wrote:
> On 2/1/2026 9:54 AM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Creating a CXL region requires userspace intervention through the cxl
>> sysfs files. Type2 support should allow accelerator drivers to create
>> such cxl region from kernel code.
>>
>> Adding that functionality and integrating it with current support for
>> memory expanders.
>>
>> Based on https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> drivers/cxl/core/region.c | 131 ++++++++++++++++++++++++++++++++++++--
>> include/cxl/cxl.h | 3 +
>> 2 files changed, 127 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>> index 63c2aeb2ee1f..293e63dfef22 100644
>> --- a/drivers/cxl/core/region.c
>> +++ b/drivers/cxl/core/region.c
>> @@ -2944,6 +2944,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name)
>> return to_cxl_region(region_dev);
>> }
>>
>> +static void drop_region(struct cxl_region *cxlr)
>> +{
>> + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
>> + struct cxl_port *port = cxlrd_to_port(cxlrd);
>> +
>> + devm_release_action(port->uport_dev, __unregister_region, cxlr);
>> +}
>> +
>> static ssize_t delete_region_store(struct device *dev,
>> struct device_attribute *attr,
>> const char *buf, size_t len)
>> @@ -4047,14 +4055,12 @@ static int __construct_region(struct cxl_region *cxlr,
>> return 0;
>> }
>>
>> -/* Establish an empty region covering the given HPA range */
>> -static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>> - struct cxl_endpoint_decoder *cxled)
>> +static struct cxl_region *construct_region_begin(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder *cxled)
>> {
>> struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
>> - struct cxl_port *port = cxlrd_to_port(cxlrd);
>> struct cxl_dev_state *cxlds = cxlmd->cxlds;
>> - int rc, part = READ_ONCE(cxled->part);
>> + int part = READ_ONCE(cxled->part);
>> struct cxl_region *cxlr;
>>
>> do {
>> @@ -4063,13 +4069,26 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>> cxled->cxld.target_type);
>> } while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY);
>>
>> - if (IS_ERR(cxlr)) {
>> + if (IS_ERR(cxlr))
>> dev_err(cxlmd->dev.parent,
>> "%s:%s: %s failed assign region: %ld\n",
>> dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev),
>> __func__, PTR_ERR(cxlr));
>> +
>> + return cxlr;
>> +}
>> +
>> +/* Establish an empty region covering the given HPA range */
>> +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder *cxled)
>> +{
>> + struct cxl_port *port = cxlrd_to_port(cxlrd);
>> + struct cxl_region *cxlr;
>> + int rc;
>> +
>> + cxlr = construct_region_begin(cxlrd, cxled);
>> + if (IS_ERR(cxlr))
>> return cxlr;
>> - }
>>
>> rc = __construct_region(cxlr, cxlrd, cxled);
>> if (rc) {
>> @@ -4080,6 +4099,104 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>> return cxlr;
>> }
>>
>> +DEFINE_FREE(cxl_region_drop, struct cxl_region *, if (_T) drop_region(_T))
> This needs to be "if (!IS_ERR_OR_NULL(_T) drop_region(_T)". If construct_region_begin() returns an
> error pointer, drop_region() will be called with it as of now leading to a garbage pointer deref.
That's true. I will fix it.
Thank you!
>> +
>> +static struct cxl_region *
>> +__construct_new_region(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder **cxled, int ways)
>> +{
>> + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled[0]);
>> + struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
>> + struct cxl_region_params *p;
>> + resource_size_t size = 0;
>> + int rc, i;
>> +
>> + struct cxl_region *cxlr __free(cxl_region_drop) =
>> + construct_region_begin(cxlrd, cxled[0]);
>> + if (IS_ERR(cxlr))
>> + return cxlr;
>> +
>> + guard(rwsem_write)(&cxl_rwsem.region);
>> +
>> + /*
>> + * Sanity check. This should not happen with an accel driver handling
>> + * the region creation.
>> + */
>> + p = &cxlr->params;
>> + if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) {
>> + dev_err(cxlmd->dev.parent,
>> + "%s:%s: %s unexpected region state\n",
>> + dev_name(&cxlmd->dev), dev_name(&cxled[0]->cxld.dev),
>> + __func__);
>> + return ERR_PTR(-EBUSY);
>> + }
>> +
>> + rc = set_interleave_ways(cxlr, ways);
>> + if (rc)
>> + return ERR_PTR(rc);
>> +
>> + rc = set_interleave_granularity(cxlr, cxld->interleave_granularity);
>> + if (rc)
>> + return ERR_PTR(rc);
>> +
>> + scoped_guard(rwsem_read, &cxl_rwsem.dpa) {
>> + for (i = 0; i < ways; i++) {
>> + if (!cxled[i]->dpa_res)
>> + return ERR_PTR(-EINVAL);
>> + size += resource_size(cxled[i]->dpa_res);
>> + }
>> +
>> + rc = alloc_hpa(cxlr, size);
>> + if (rc)
>> + return ERR_PTR(rc);
>> +
>> + for (i = 0; i < ways; i++) {
>> + rc = cxl_region_attach(cxlr, cxled[i], 0);
> Position parameter is hardcoded to 0. It should be set to i, right? This kind of goes back to my
> issues in patch 12/22; the interleaving functionality is there but it looks unused.
>
>> + if (rc)
>> + return ERR_PTR(rc);
>> + }
>> + }
>> +
>> + rc = cxl_region_decode_commit(cxlr);
>> + if (rc)
>> + return ERR_PTR(rc);
>> +
>> + p->state = CXL_CONFIG_COMMIT;
>> +
>> + return no_free_ptr(cxlr);
>> +}
>> +
>> +/**
>> + * cxl_create_region - Establish a region given an endpoint decoder
>> + * @cxlrd: root decoder to allocate HPA
>> + * @cxled: endpoint decoders with reserved DPA capacity
>> + * @ways: interleave ways required
>> + *
>> + * Returns a fully formed region in the commit state and attached to the
>> + * cxl_region driver.
>> + */
>> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder **cxled,
>> + int ways)
>> +{
>> + struct cxl_region *cxlr;
>> +
>> + mutex_lock(&cxlrd->range_lock);
>> + cxlr = __construct_new_region(cxlrd, cxled, ways);
>> + mutex_unlock(&cxlrd->range_lock);
>> + if (IS_ERR(cxlr))
>> + return cxlr;
>> +
>> + if (device_attach(&cxlr->dev) <= 0) {
>> + dev_err(&cxlr->dev, "failed to create region\n");
>> + drop_region(cxlr);
>> + return ERR_PTR(-ENODEV);
>> + }
>> +
>> + return cxlr;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_create_region, "CXL");
>> +
>> static struct cxl_region *
>> cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *hpa)
>> {
>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>> index 4802371db00e..50acbd13bcf8 100644
>> --- a/include/cxl/cxl.h
>> +++ b/include/cxl/cxl.h
>> @@ -281,4 +281,7 @@ struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
>> enum cxl_partition_mode mode,
>> resource_size_t alloc);
>> int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
>> +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd,
>> + struct cxl_endpoint_decoder **cxled,
>> + int ways);
>> #endif /* __CXL_CXL_H__ */
next prev parent reply other threads:[~2026-02-19 10:48 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-01 15:54 [PATCH v23 00/22] Type2 device basic support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 01/22] cxl: Add type2 " alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-19 8:52 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 02/22] sfc: add cxl support alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 03/22] cxl: Move pci generic code alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 04/22] cxl/sfc: Map cxl component regs alejandro.lucero-palau
2026-03-20 17:22 ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 05/22] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2026-03-20 17:24 ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 06/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 07/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 08/22] cxl/hdm: Add support for getting region from committed decoder alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-12 9:16 ` Alejandro Lucero Palau
2026-03-09 22:49 ` PJ Waskiewicz
2026-03-10 13:54 ` Alejandro Lucero Palau
2026-03-13 2:03 ` Dan Williams
2026-03-13 13:10 ` Alejandro Lucero Palau
2026-03-16 14:33 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 09/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 10/22] cxl: Export function for unwinding cxl by accelerators alejandro.lucero-palau
2026-02-19 23:16 ` Dave Jiang
2026-02-21 4:48 ` Gregory Price
2026-02-01 15:54 ` [PATCH v23 11/22] sfc: obtain decoder and region if committed by firmware alejandro.lucero-palau
2026-02-11 22:10 ` Cheatham, Benjamin
2026-02-19 8:55 ` Alejandro Lucero Palau
2026-02-19 23:31 ` Dave Jiang
2026-02-20 8:08 ` Alejandro Lucero Palau
2026-03-20 17:25 ` Edward Cree
2026-02-01 15:54 ` [PATCH v23 12/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2026-02-11 22:10 ` Cheatham, Benjamin
2026-02-19 9:58 ` Alejandro Lucero Palau
2026-02-19 17:29 ` Cheatham, Benjamin
2026-02-20 15:42 ` Dave Jiang
2026-02-26 16:13 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 13/22] sfc: get root decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 14/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2026-02-11 22:10 ` Cheatham, Benjamin
2026-02-11 22:12 ` Cheatham, Benjamin
2026-02-19 10:26 ` Alejandro Lucero Palau
2026-02-13 16:14 ` [PATCH " Gregory Price
2026-02-16 12:34 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 15/22] sfc: get endpoint decoder alejandro.lucero-palau
2026-02-01 15:54 ` [PATCH v23 16/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 17/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-19 10:40 ` Alejandro Lucero Palau
2026-02-19 17:29 ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 18/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-01 15:54 ` [PATCH v23 19/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2026-02-11 22:11 ` Cheatham, Benjamin
2026-02-19 10:48 ` Alejandro Lucero Palau [this message]
2026-02-01 15:54 ` [PATCH v23 20/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2026-02-11 22:10 ` Cheatham, Benjamin
2026-02-19 10:50 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 21/22] sfc: create cxl region alejandro.lucero-palau
2026-02-13 16:14 ` [PATCH " Gregory Price
2026-02-20 8:00 ` Alejandro Lucero Palau
2026-02-01 15:54 ` [PATCH v23 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2026-02-13 16:14 ` [PATCH " Gregory Price
2026-02-20 8:04 ` Alejandro Lucero Palau
2026-02-11 22:12 ` [PATCH v23 00/22] Type2 device basic support Cheatham, Benjamin
2026-03-09 22:43 ` PJ Waskiewicz
2026-03-10 14:02 ` Alejandro Lucero Palau
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