From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH 1/7] dt-bindings: Add Cavium Octeon Common Ethernet Interface. Date: Wed, 1 Nov 2017 18:26:34 -0700 Message-ID: References: <20171102003606.19913-1-david.daney@cavium.com> <20171102003606.19913-2-david.daney@cavium.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: linux-kernel@vger.kernel.org, "Steven J. Hill" , devicetree@vger.kernel.org, Carlos Munoz To: Florian Fainelli , David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org, James Hogan , netdev@vger.kernel.org, "David S. Miller" , Rob Herring , Mark Rutland , "Williams, Aaron" Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-Id: netdev.vger.kernel.org On 11/01/2017 06:09 PM, Florian Fainelli wrote: > On 11/01/2017 05:36 PM, David Daney wrote: >> From: Carlos Munoz >> >> Add bindings for Common Ethernet Interface (BGX) block. >> >> Signed-off-by: Carlos Munoz >> Signed-off-by: Steven J. Hill >> Signed-off-by: David Daney >> --- > [snip] >> +Properties: >> + >> +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs. >> + >> +- reg: The index of the interface within the BGX block. >> + >> +- local-mac-address: Mac address for the interface. >> + >> +- phy-handle: phandle to the phy node connected to the interface. >> + >> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting. >> + Needed by the Micrel PHY. > > Is not that implied by an appropriate "phy-mode" property already? I think you are correct. That string never appears in the source code, so I am going to remove that property from the binding document for the next revision of the patch set. Thanks, David Daney