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From: Sean Anderson <sean.anderson@linux.dev>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Gupta, Suraj" <Suraj.Gupta2@amd.com>,
	"andrew+netdev@lunn.ch" <andrew+netdev@lunn.ch>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	"vkoul@kernel.org" <vkoul@kernel.org>,
	"Simek, Michal" <michal.simek@amd.com>,
	"Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>,
	"horms@kernel.org" <horms@kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"git (AMD-Xilinx)" <git@amd.com>,
	"Katakam, Harini" <harini.katakam@amd.com>
Subject: Re: [PATCH net-next] net: xilinx: axienet: Configure and report coalesce parameters in DMAengine flow
Date: Thu, 29 May 2025 12:35:09 -0400	[thread overview]
Message-ID: <f445b132-98c5-4f38-bd3e-172bc8645a03@linux.dev> (raw)
In-Reply-To: <6c99b7f5-b529-4efd-a065-1e0ebf01468e@lunn.ch>

On 5/29/25 12:29, Andrew Lunn wrote:
>> Yeah, but the reason is that you are trading latency for throughput.
>> There is only one queue, so when the interface is saturated you will not
>> get good latency anyway (since latency-sensitive packets will get
>> head-of-line blocked). But when activity is sparse you can good latency
>> if there is no coalescing. So I think coalescing should only be used
>> when there is a lot of traffic. Hence why I only adjusted the settings
>> once I implemented DIM. I think you should be able to implement it by
>> calling net_dim from axienet_dma_rx_cb, but it will not be as efficient
>> without NAPI.
>> 
>> Actually, if you are looking into improving performance, I think lack of
>> NAPI is probably the biggest limitation with the dmaengine backend.
> 
> It latency is the goal, especially for mixing high and low priority
> traffic, having BQL implemented is also important. Does this driver
> have that?
> 
> 	Andrew

Yes, see commit c900e49d58eb ("net: xilinx: axienet: Implement BQL").

--Sean

  reply	other threads:[~2025-05-29 16:35 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-25 10:22 [PATCH net-next] net: xilinx: axienet: Configure and report coalesce parameters in DMAengine flow Suraj Gupta
2025-05-26  0:36 ` kernel test robot
2025-05-27 16:16 ` Sean Anderson
2025-05-28 12:00   ` Gupta, Suraj
2025-05-28 13:09     ` Subbaraya Sundeep
2025-05-29 16:17     ` Sean Anderson
2025-05-29 16:29       ` Andrew Lunn
2025-05-29 16:35         ` Sean Anderson [this message]
2025-05-30 10:18       ` Gupta, Suraj
2025-05-30 11:53         ` Gupta, Suraj
2025-05-30 20:44         ` Sean Anderson
2025-06-03 11:07           ` Gupta, Suraj
2025-06-09 16:22             ` Sean Anderson

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