From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5093F42AA9; Thu, 13 Mar 2025 20:22:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741897351; cv=none; b=IqTf0H2OtCfpfES6pDZMu1oJS5gboVIejCfAGg17cmdWQJrlKkjus/UMyKoOVNwheNNR/KPlqyULBXENIBl5mB+zsm60OIh2TOvvQwAO3Ael24wjelgnPKg3v+LUXtpUzDL5eCS4gPENadaUcyKOcdHZtp7BAgZsVb510p6rasI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741897351; c=relaxed/simple; bh=2Ubrn3vw5OoeA0jFCkzjYo3i5zUpGJxfx7CRuIQHoUM=; h=Message-ID:Content-Type:MIME-Version:In-Reply-To:References: Subject:From:Cc:To:Date; b=YyNserH5XL3MXocTA6QROOf6u2eTb0JniCCG+j6FwdBIjVLUAJuJ+Mk4Bs2D3KxNvQLquQEPW89WmRVWUrH/+kwInweC3y0FrtuIMSwl5BzHuHrEUT53eVyM6MEx+7u34DSEd8DEGtIAfCWTeTp9NHKvGjBdcrWjMqA/Bq8lkys= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XJjow640; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XJjow640" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A611EC4CEDD; Thu, 13 Mar 2025 20:22:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1741897350; bh=2Ubrn3vw5OoeA0jFCkzjYo3i5zUpGJxfx7CRuIQHoUM=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=XJjow640+p8SFFIt3qd7pSc55KNUf2aPDnh5lFC7h7Tp/OGU02NUQ1KgmtGdblwd+ XODsUZgTqEDlAwzaU8b8+x1cmywLuVsahRSiN80au+vheAXHAtC+s3fIolSgpUJBBC umINKQgxcqUjIw5pZW3KY07cGjnsG1otzBZcML2xd3FWe7GBhQMheq1sduVTtcL3eC h/f8JkJ2xUHaTaqVXBcdQGJbty+398gIzl8diIEj122H6uZdQxsVjoxD6u+KECMHG/ b4d4OTBnYSxeG3mZcWeiImnh+vDak8EcKliw34XpTbpQBXNLzYDm4wiIlZ/7ZnyGCO kOwsRl6ln0DEw== Message-ID: Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20250226232320.93791-1-inochiama@gmail.com> <20250226232320.93791-2-inochiama@gmail.com> <2c00c1fba1cd8115205efe265b7f1926.sboyd@kernel.org> Subject: Re: [PATCH v3 1/2] dt-bindings: clock: sophgo: add clock controller for SG2044 From: Stephen Boyd Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Yixun Lan , Longbin Li , Krzysztof Kozlowski To: Chen Wang , Conor Dooley , Inochi Amaoto , Krzysztof Kozlowski , Michael Turquette , Richard Cochran , Rob Herring Date: Thu, 13 Mar 2025 13:22:28 -0700 User-Agent: alot/0.12.dev8+g17a99a841c4b Quoting Inochi Amaoto (2025-03-12 18:08:11) > On Wed, Mar 12, 2025 at 04:43:51PM -0700, Stephen Boyd wrote: > > Quoting Inochi Amaoto (2025-03-12 16:29:43) > > > On Wed, Mar 12, 2025 at 04:14:37PM -0700, Stephen Boyd wrote: > > > > Quoting Inochi Amaoto (2025-03-11 16:31:29) > > > > >=20 > > > > > > or if that syscon node should just have the #clock-cells proper= ty as > > > > > > part of the node instead. > > > > >=20 > > > > > This is not match the hardware I think. The pll area is on the mi= ddle > > > > > of the syscon and is hard to be separated as a subdevice of the s= yscon > > > > > or just add "#clock-cells" to the syscon device. It is better to= handle > > > > > them in one device/driver. So let the clock device reference it. > > > >=20 > > > > This happens all the time. We don't need a syscon for that unless t= he > > > > registers for the pll are both inside the syscon and in the register > > > > space 0x50002000. Is that the case?=20 > > >=20 > > > Yes, the clock has two areas, one in the clk controller and one in > > > the syscon, the vendor said this design is a heritage from other SoC. > >=20 > > My question is more if the PLL clk_ops need to access both the syscon > > register range and the clk controller register range. What part of the > > PLL clk_ops needs to access the clk controller at 0x50002000? > >=20 >=20 > The PLL clk_ops does nothing, but there is an implicit dependency: > When the PLL change rate, the mux attached to it must switch to=20 > another source to keep the output clock stable. This is the only > thing it needed. I haven't looked at the clk_ops in detail (surprise! :) but that sounds a lot like the parent of the mux is the PLL and there's some "safe" source that is needed temporarily while the PLL is reprogrammed for a new rate. Is that right? I recall the notifier is in the driver so this sounds like that sort of design.