* [PATCH net-next v3] r8169: add support for RTL8125cp
@ 2026-02-02 10:58 javen
2026-02-02 20:50 ` Heiner Kallweit
2026-02-02 23:54 ` Jakub Kicinski
0 siblings, 2 replies; 6+ messages in thread
From: javen @ 2026-02-02 10:58 UTC (permalink / raw)
To: hkallweit1, nic_swsd, andrew+netdev, davem, edumazet, kuba,
pabeni, horms
Cc: netdev, linux-kernel, Javen Xu
From: Javen Xu <javen_xu@realsil.com.cn>
This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
different and firmware for RTL8125cp.
Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
---
v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43, 0x10,
0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2 means
'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
---
drivers/net/ethernet/realtek/r8169.h | 1 +
drivers/net/ethernet/realtek/r8169_main.c | 6 +++++
.../net/ethernet/realtek/r8169_phy_config.c | 22 +++++++++++++++++++
3 files changed, 29 insertions(+)
diff --git a/drivers/net/ethernet/realtek/r8169.h b/drivers/net/ethernet/realtek/r8169.h
index aed4cf852091..0b9c1d4eb48b 100644
--- a/drivers/net/ethernet/realtek/r8169.h
+++ b/drivers/net/ethernet/realtek/r8169.h
@@ -68,6 +68,7 @@ enum mac_version {
RTL_GIGA_MAC_VER_61,
RTL_GIGA_MAC_VER_63,
RTL_GIGA_MAC_VER_64,
+ RTL_GIGA_MAC_VER_65,
RTL_GIGA_MAC_VER_66,
RTL_GIGA_MAC_VER_70,
RTL_GIGA_MAC_VER_80,
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 2f7d9809c373..d040f2074db6 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -60,6 +60,7 @@
#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
#define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw"
#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
+#define FIRMWARE_8125CP_1 "rtl_nic/rtl8125cp-1.fw"
#define FIRMWARE_9151A_1 "rtl_nic/rtl9151a-1.fw"
#define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
#define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
@@ -112,6 +113,9 @@ static const struct rtl_chip_info {
/* 8125BP family. */
{ 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
+ /* 8125CP family*/
+ { 0x7cf, 0x708, RTL_GIGA_MAC_VER_65, "RTL8125CP", FIRMWARE_8125CP_1 },
+
/* 8125D family. */
{ 0x7cf, 0x68b, RTL_GIGA_MAC_VER_64, "RTL9151A", FIRMWARE_9151A_1 },
{ 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 },
@@ -802,6 +806,7 @@ MODULE_FIRMWARE(FIRMWARE_8125D_1);
MODULE_FIRMWARE(FIRMWARE_8125D_2);
MODULE_FIRMWARE(FIRMWARE_8125K_1);
MODULE_FIRMWARE(FIRMWARE_8125BP_2);
+MODULE_FIRMWARE(FIRMWARE_8125CP_1);
MODULE_FIRMWARE(FIRMWARE_9151A_1);
MODULE_FIRMWARE(FIRMWARE_8126A_2);
MODULE_FIRMWARE(FIRMWARE_8126A_3);
@@ -4021,6 +4026,7 @@ static void rtl_hw_config(struct rtl8169_private *tp)
[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
[RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
+ [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d,
[RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
[RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
[RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a,
diff --git a/drivers/net/ethernet/realtek/r8169_phy_config.c b/drivers/net/ethernet/realtek/r8169_phy_config.c
index 032d9d2cfa2a..a880df7c1f70 100644
--- a/drivers/net/ethernet/realtek/r8169_phy_config.c
+++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
@@ -1102,6 +1102,27 @@ static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
rtl8125_config_eee_phy(phydev);
}
+static void rtl8125cp_hw_phy_config(struct rtl8169_private *tp,
+ struct phy_device *phydev)
+{
+ r8169_apply_firmware(tp);
+ rtl8168g_enable_gphy_10m(phydev);
+
+ phy_modify_paged(phydev, 0xad0, 0x17, 0x007f, 0x000b);
+ phy_modify_paged(phydev, 0xad7, 0x14, 0x0000, BIT(4));
+ rtl8125_phy_param(phydev, 0x807f, 0xff00, 0x5300);
+ r8168g_phy_param(phydev, 0x81b8, 0xffff, 0x00b4);
+ r8168g_phy_param(phydev, 0x81ba, 0xffff, 0x00e4);
+ r8168g_phy_param(phydev, 0x81c5, 0xffff, 0x0104);
+ r8168g_phy_param(phydev, 0x81d0, 0xffff, 0x054d);
+ phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003);
+ phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, BIT(7));
+
+ rtl8125_legacy_force_mode(phydev);
+ rtl8168g_disable_aldps(phydev);
+ rtl8125_config_eee_phy(phydev);
+}
+
static void rtl8125bp_hw_phy_config(struct rtl8169_private *tp,
struct phy_device *phydev)
{
@@ -1344,6 +1365,7 @@ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
[RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
[RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
[RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
+ [RTL_GIGA_MAC_VER_65] = rtl8125cp_hw_phy_config,
[RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config,
[RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config,
[RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config,
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH net-next v3] r8169: add support for RTL8125cp
2026-02-02 10:58 [PATCH net-next v3] r8169: add support for RTL8125cp javen
@ 2026-02-02 20:50 ` Heiner Kallweit
2026-02-03 7:58 ` javen
2026-02-02 23:54 ` Jakub Kicinski
1 sibling, 1 reply; 6+ messages in thread
From: Heiner Kallweit @ 2026-02-02 20:50 UTC (permalink / raw)
To: javen, nic_swsd, andrew+netdev, davem, edumazet, kuba, pabeni,
horms
Cc: netdev, linux-kernel
On 2/2/2026 11:58 AM, javen wrote:
> From: Javen Xu <javen_xu@realsil.com.cn>
>
> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
> different and firmware for RTL8125cp.
>
> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>
> ---
> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43, 0x10,
> 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>
> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2 means
> 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
ALDPS is disabled two lines later in rtl8125cp_hw_phy_config().
So why bother with ALDPS settings if ALDPS is disabled anyway?
And a formal note:
A new version of a patch should be submitted >=24h later, to leave
time for further review comments.
> ---
> drivers/net/ethernet/realtek/r8169.h | 1 +
> drivers/net/ethernet/realtek/r8169_main.c | 6 +++++
> .../net/ethernet/realtek/r8169_phy_config.c | 22 +++++++++++++++++++
> 3 files changed, 29 insertions(+)
>
> diff --git a/drivers/net/ethernet/realtek/r8169.h b/drivers/net/ethernet/realtek/r8169.h
> index aed4cf852091..0b9c1d4eb48b 100644
> --- a/drivers/net/ethernet/realtek/r8169.h
> +++ b/drivers/net/ethernet/realtek/r8169.h
> @@ -68,6 +68,7 @@ enum mac_version {
> RTL_GIGA_MAC_VER_61,
> RTL_GIGA_MAC_VER_63,
> RTL_GIGA_MAC_VER_64,
> + RTL_GIGA_MAC_VER_65,
> RTL_GIGA_MAC_VER_66,
> RTL_GIGA_MAC_VER_70,
> RTL_GIGA_MAC_VER_80,
> diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
> index 2f7d9809c373..d040f2074db6 100644
> --- a/drivers/net/ethernet/realtek/r8169_main.c
> +++ b/drivers/net/ethernet/realtek/r8169_main.c
> @@ -60,6 +60,7 @@
> #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw"
> #define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw"
> #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw"
> +#define FIRMWARE_8125CP_1 "rtl_nic/rtl8125cp-1.fw"
> #define FIRMWARE_9151A_1 "rtl_nic/rtl9151a-1.fw"
> #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw"
> #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw"
> @@ -112,6 +113,9 @@ static const struct rtl_chip_info {
> /* 8125BP family. */
> { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 },
>
> + /* 8125CP family*/
> + { 0x7cf, 0x708, RTL_GIGA_MAC_VER_65, "RTL8125CP", FIRMWARE_8125CP_1 },
> +
> /* 8125D family. */
> { 0x7cf, 0x68b, RTL_GIGA_MAC_VER_64, "RTL9151A", FIRMWARE_9151A_1 },
> { 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 },
> @@ -802,6 +806,7 @@ MODULE_FIRMWARE(FIRMWARE_8125D_1);
> MODULE_FIRMWARE(FIRMWARE_8125D_2);
> MODULE_FIRMWARE(FIRMWARE_8125K_1);
> MODULE_FIRMWARE(FIRMWARE_8125BP_2);
> +MODULE_FIRMWARE(FIRMWARE_8125CP_1);
> MODULE_FIRMWARE(FIRMWARE_9151A_1);
> MODULE_FIRMWARE(FIRMWARE_8126A_2);
> MODULE_FIRMWARE(FIRMWARE_8126A_3);
> @@ -4021,6 +4026,7 @@ static void rtl_hw_config(struct rtl8169_private *tp)
> [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
> [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
> [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
> + [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d,
> [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
> [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
> [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a,
> diff --git a/drivers/net/ethernet/realtek/r8169_phy_config.c b/drivers/net/ethernet/realtek/r8169_phy_config.c
> index 032d9d2cfa2a..a880df7c1f70 100644
> --- a/drivers/net/ethernet/realtek/r8169_phy_config.c
> +++ b/drivers/net/ethernet/realtek/r8169_phy_config.c
> @@ -1102,6 +1102,27 @@ static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
> rtl8125_config_eee_phy(phydev);
> }
>
> +static void rtl8125cp_hw_phy_config(struct rtl8169_private *tp,
> + struct phy_device *phydev)
> +{
> + r8169_apply_firmware(tp);
> + rtl8168g_enable_gphy_10m(phydev);
> +
> + phy_modify_paged(phydev, 0xad0, 0x17, 0x007f, 0x000b);
> + phy_modify_paged(phydev, 0xad7, 0x14, 0x0000, BIT(4));
> + rtl8125_phy_param(phydev, 0x807f, 0xff00, 0x5300);
> + r8168g_phy_param(phydev, 0x81b8, 0xffff, 0x00b4);
> + r8168g_phy_param(phydev, 0x81ba, 0xffff, 0x00e4);
> + r8168g_phy_param(phydev, 0x81c5, 0xffff, 0x0104);
> + r8168g_phy_param(phydev, 0x81d0, 0xffff, 0x054d);
> + phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003);
> + phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, BIT(7));
> +
> + rtl8125_legacy_force_mode(phydev);
> + rtl8168g_disable_aldps(phydev);
> + rtl8125_config_eee_phy(phydev);
> +}
> +
> static void rtl8125bp_hw_phy_config(struct rtl8169_private *tp,
> struct phy_device *phydev)
> {
> @@ -1344,6 +1365,7 @@ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
> [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
> [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
> [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
> + [RTL_GIGA_MAC_VER_65] = rtl8125cp_hw_phy_config,
> [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config,
> [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config,
> [RTL_GIGA_MAC_VER_80] = rtl8127a_1_hw_phy_config,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net-next v3] r8169: add support for RTL8125cp
2026-02-02 10:58 [PATCH net-next v3] r8169: add support for RTL8125cp javen
2026-02-02 20:50 ` Heiner Kallweit
@ 2026-02-02 23:54 ` Jakub Kicinski
1 sibling, 0 replies; 6+ messages in thread
From: Jakub Kicinski @ 2026-02-02 23:54 UTC (permalink / raw)
To: javen
Cc: hkallweit1, nic_swsd, andrew+netdev, davem, edumazet, pabeni,
horms, netdev, linux-kernel
On Mon, 2 Feb 2026 18:58:28 +0800 javen wrote:
> +static void rtl8125cp_hw_phy_config(struct rtl8169_private *tp,
> + struct phy_device *phydev)
Please run checkpatch on your patches:
CHECK: Alignment should match open parenthesis
#76: FILE: drivers/net/ethernet/realtek/r8169_phy_config.c:1106:
+static void rtl8125cp_hw_phy_config(struct rtl8169_private *tp,
+ struct phy_device *phydev)
--
pw-bot: cr
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net-next v3] r8169: add support for RTL8125cp
2026-02-02 20:50 ` Heiner Kallweit
@ 2026-02-03 7:58 ` javen
2026-02-03 20:13 ` Heiner Kallweit
0 siblings, 1 reply; 6+ messages in thread
From: javen @ 2026-02-03 7:58 UTC (permalink / raw)
To: hkallweit1
Cc: andrew+netdev, davem, edumazet, horms, javen_xu, kuba,
linux-kernel, netdev, nic_swsd, pabeni
>On 2/2/2026 11:58 AM, javen wrote:
>> From: Javen Xu <javen_xu@realsil.com.cn>
>>
>> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
>> different and firmware for RTL8125cp.
>>
>> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>>
>> ---
>> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43,
>> 0x10, 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>>
>> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
>> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2
>> means 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
>
>ALDPS is disabled two lines later in rtl8125cp_hw_phy_config().
>So why bother with ALDPS settings if ALDPS is disabled anyway?
Bit 2 means 'ENABLE ALDPS', we prefer to treat it as a master switch that controls
some sub-features like bit 1(ALDPS PLL OFF) and bit 12(ALDPS XTAL OFF), instead of
controlling these sub-features individually. And bit 0(link speed 10m PLL OFF)
has noting to do with aldps.
Thanks,
Javen Xu
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net-next v3] r8169: add support for RTL8125cp
2026-02-03 7:58 ` javen
@ 2026-02-03 20:13 ` Heiner Kallweit
2026-02-04 7:09 ` javen
0 siblings, 1 reply; 6+ messages in thread
From: Heiner Kallweit @ 2026-02-03 20:13 UTC (permalink / raw)
To: javen
Cc: andrew+netdev, davem, edumazet, horms, kuba, linux-kernel, netdev,
nic_swsd, pabeni
On 2/3/2026 8:58 AM, javen wrote:
>> On 2/2/2026 11:58 AM, javen wrote:
>
>>> From: Javen Xu <javen_xu@realsil.com.cn>
>
>>>
>
>>> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
>
>>> different and firmware for RTL8125cp.
>
>>>
>
>>> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>
>>>
>
>>> ---
>
>>> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43,
>
>>> 0x10, 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>
>>>
>
>>> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
>
>>> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2
>
>>> means 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
>
>>
>
>> ALDPS is disabled two lines later in rtl8125cp_hw_phy_config().
>
>> So why bother with ALDPS settings if ALDPS is disabled anyway?
>
>
>
> Bit 2 means 'ENABLE ALDPS', we prefer to treat it as a master switch that controls
>
> some sub-features like bit 1(ALDPS PLL OFF) and bit 12(ALDPS XTAL OFF), instead of
>
> controlling these sub-features individually. And bit 0(link speed 10m PLL OFF)
>
> has noting to do with aldps.
>
I see, you changed the value of a43/10 to 0x0003 in v3. Then just this question:
Few lines later ALDPS gets disabled, so is it beneficial to set bit 1 here?
Thanks for mentioning that bit 0 isn't related to ALDPS.
>
>
> Thanks,
>
> Javen Xu
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH net-next v3] r8169: add support for RTL8125cp
2026-02-03 20:13 ` Heiner Kallweit
@ 2026-02-04 7:09 ` javen
0 siblings, 0 replies; 6+ messages in thread
From: javen @ 2026-02-04 7:09 UTC (permalink / raw)
To: hkallweit1
Cc: andrew+netdev, davem, edumazet, horms, javen_xu, kuba,
linux-kernel, netdev, nic_swsd, pabeni
>On 2/3/2026 8:58 AM, javen wrote:
>>>> On 2/2/2026 11:58 AM, javen wrote:
>>
>>>> From: Javen Xu <javen_xu@realsil.com.cn>
>>
>>>>
>>
>>>> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
>>
>>>> different and firmware for RTL8125cp.
>>
>>>>
>>
>>>> Signed-off-by: Javen Xu <javen_xu@realsil.com.cn>
>>
>>>>
>>
>>>> ---
>>
>>>> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43,
>>
>>>> 0x10, 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>>
>>>>
>>
>>>> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
>>
>>>> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2
>>
>>>> means 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
>>
>>>
>>
>>> ALDPS is disabled two lines later in rtl8125cp_hw_phy_config().
>>
>>> So why bother with ALDPS settings if ALDPS is disabled anyway?
>>
>>
>>
>> Bit 2 means 'ENABLE ALDPS', we prefer to treat it as a master switch that controls
>>
>> some sub-features like bit 1(ALDPS PLL OFF) and bit 12(ALDPS XTAL OFF), instead of
>>
>> controlling these sub-features individually. And bit 0(link speed 10m PLL OFF)
>>
>> has noting to do with aldps.
>>
>I see, you changed the value of a43/10 to 0x0003 in v3. Then just this question:
>Few lines later ALDPS gets disabled, so is it beneficial to set bit 1 here?
>Thanks for mentioning that bit 0 isn't related to ALDPS.
>
Bit 2 acts like a lock that controls bit 1. If bit 2 = 0, bit 1 has no effect even if set,
so pre-setting bit 1 causes no side effects. The reason why we set bit 1 here is that If we
need to enable bit1(aldps pll off) later, just set bit 2 to enable aldps without any additional
bits write(means we do not need to set bit 1 again).
Alternatively, you can view this as initialization related to aldps. if aldps(bit 2) is enabled later,
these related functions will be enabled at the same time(like bit 1).
Thanks,
Javen Xu
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-02-04 7:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-02-02 10:58 [PATCH net-next v3] r8169: add support for RTL8125cp javen
2026-02-02 20:50 ` Heiner Kallweit
2026-02-03 7:58 ` javen
2026-02-03 20:13 ` Heiner Kallweit
2026-02-04 7:09 ` javen
2026-02-02 23:54 ` Jakub Kicinski
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