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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Eric Woudstra , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH net-next v2 05/10] net: phy: air: move the EN8811H firmware download into the library Date: Fri, 4 Sep 2026 19:02:59 +0000 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The EN8811H firmware loader is welded to the PHY driver, but the next patch adds an MDIO device driver that must perform the same download before any phy_device exists. Move the download engine into the shared library, typed on the MDIO device like the buckpbus core. The moved helpers take the bus lock and save and restore the page register themselves, since phy_select_page() needs a phy_device. The status poll now asks for the MMD register through the Clause 22 indirection unconditionally. phy_read_mmd() used to resolve that from phydev->is_c45, which is false for every device tree describing the Clause 22 PHYs this library serves, so hardcoding it changes nothing any board runs today. The version read at the end is now checked. en8811h_print_fw_version() threw its result away, so a bus error there left the version at zero and let probe continue; the load fails instead. Assisted-by: LLM Signed-off-by: Aleksei Sviridkin --- drivers/net/phy/air_en8811h.c | 139 +----------------- drivers/net/phy/air_phy_lib.c | 260 ++++++++++++++++++++++++++++++++++ drivers/net/phy/air_phy_lib.h | 24 ++++ 3 files changed, 288 insertions(+), 135 deletions(-) diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c index 38eb18f0e9bb..2f6ed30ba24d 100644 --- a/drivers/net/phy/air_en8811h.c +++ b/drivers/net/phy/air_en8811h.c @@ -20,21 +20,15 @@ #include #include #include -#include #include "air_phy_lib.h" #define EN8811H_PHY_ID 0x03a2a411 #define AN8811HB_PHY_ID 0xc0ff04a0 -#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" -#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" #define AN8811HB_MD32_DM "airoha/an8811hb/EthMD32_CRC.DM.bin" #define AN8811HB_MD32_DSP "airoha/an8811hb/EthMD32_CRC.DSP.bin" -#define AIR_FW_ADDR_DM 0x00000000 -#define AIR_FW_ADDR_DSP 0x00100000 - /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) @@ -44,8 +38,6 @@ #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc /* Registers on MDIO_MMD_VEND1 */ -#define EN8811H_PHY_FW_STATUS 0x8009 -#define EN8811H_PHY_READY 0x02 #define AIR_PHY_MCU_CMD_0 0x800b #define AIR_PHY_MCU_CMD_1 0x800c @@ -108,8 +100,6 @@ #define EN8811H_2P5G_LPA 0x3b30 #define EN8811H_2P5G_LPA_2P5G BIT(0) -#define EN8811H_FW_VERSION 0x3b3c - #define EN8811H_POLARITY 0xca0f8 #define EN8811H_POLARITY_TX_NORMAL BIT(0) #define EN8811H_POLARITY_RX_REVERSE BIT(1) @@ -122,12 +112,6 @@ #define EN8811H_CLK_CGM 0xcf958 #define EN8811H_CLK_CGM_CKO BIT(26) -#define EN8811H_FW_CTRL_1 0x0f0018 -#define EN8811H_FW_CTRL_1_START 0x0 -#define EN8811H_FW_CTRL_1_FINISH 0x1 -#define EN8811H_FW_CTRL_2 0x800000 -#define EN8811H_FW_CTRL_2_LOADING BIT(11) - #define AN8811HB_CRC_PM_SET1 0xf020c #define AN8811HB_CRC_PM_MON2 0xf0218 #define AN8811HB_CRC_PM_MON3 0xf021c @@ -270,80 +254,9 @@ static int __air_pbus_reg_write(struct mdio_device *mdiodev, upper_16_bits(pbus_data)); } -static int __air_write_buf(struct phy_device *phydev, u32 address, - const struct firmware *fw) -{ - unsigned int offset; - int ret; - u16 val; - - ret = __phy_write(phydev, AIR_BPBUS_MODE, AIR_BPBUS_MODE_ADDR_INCR); - if (ret < 0) - return ret; - - ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, - upper_16_bits(address)); - if (ret < 0) - return ret; - - ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, - lower_16_bits(address)); - if (ret < 0) - return ret; - - for (offset = 0; offset < fw->size; offset += 4) { - val = get_unaligned_le16(&fw->data[offset + 2]); - ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, val); - if (ret < 0) - return ret; - - val = get_unaligned_le16(&fw->data[offset]); - ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, val); - if (ret < 0) - return ret; - } - - return 0; -} - -static int air_write_buf(struct phy_device *phydev, u32 address, - const struct firmware *fw) -{ - int saved_page; - int ret = 0; - - saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4); - - if (saved_page >= 0) { - ret = __air_write_buf(phydev, address, fw); - if (ret < 0) - phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, - address, ret); - } - - return phy_restore_page(phydev, saved_page, ret); -} - static int en8811h_wait_mcu_ready(struct phy_device *phydev) { - int ret, reg_value; - - ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); - if (ret) - return ret; - - /* Because of mdio-lock, may have to wait for multiple loads */ - ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, - EN8811H_PHY_FW_STATUS, reg_value, - reg_value == EN8811H_PHY_READY, - 20000, 7500000, true); - if (ret) { - phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); - return -ENODEV; - } - - return 0; + return air_en8811h_wait_mcu_ready(&phydev->mdio); } static int an8811hb_check_crc(struct phy_device *phydev, u32 set1, @@ -405,7 +318,7 @@ static int an8811hb_load_file(struct phy_device *phydev, const char *name, if (ret < 0) return ret; - ret = air_write_buf(phydev, address, fw); + ret = air_fw_write_buf(&phydev->mdio, address, fw); release_firmware(fw); return ret; } @@ -501,54 +414,10 @@ static int an8811hb_load_firmware(struct phy_device *phydev) static int en8811h_load_firmware(struct phy_device *phydev) { - struct device *dev = &phydev->mdio.dev; - const struct firmware *fw1, *fw2; + struct en8811h_priv *priv = phydev->priv; int ret; - ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); - if (ret < 0) - return ret; - - ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev); - if (ret < 0) - goto en8811h_load_firmware_rel1; - - ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_START); - if (ret < 0) - goto en8811h_load_firmware_out; - - ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, - EN8811H_FW_CTRL_2_LOADING); - if (ret < 0) - goto en8811h_load_firmware_out; - - ret = air_write_buf(phydev, AIR_FW_ADDR_DM, fw1); - if (ret < 0) - goto en8811h_load_firmware_out; - - ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2); - if (ret < 0) - goto en8811h_load_firmware_out; - - ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2, - EN8811H_FW_CTRL_2_LOADING, 0); - if (ret < 0) - goto en8811h_load_firmware_out; - - ret = en8811h_wait_mcu_ready(phydev); - if (ret < 0) - goto en8811h_load_firmware_out; - - en8811h_print_fw_version(phydev); - -en8811h_load_firmware_out: - release_firmware(fw2); - -en8811h_load_firmware_rel1: - release_firmware(fw1); - + ret = air_en8811h_fw_download(&phydev->mdio, &priv->firmware_version); if (ret < 0) phydev_err(phydev, "Load firmware failed: %d\n", ret); diff --git a/drivers/net/phy/air_phy_lib.c b/drivers/net/phy/air_phy_lib.c index e314717843ae..2f3e5b71abac 100644 --- a/drivers/net/phy/air_phy_lib.c +++ b/drivers/net/phy/air_phy_lib.c @@ -8,11 +8,16 @@ */ #include +#include +#include +#include #include #include +#include #include #include "air_phy_lib.h" +#include "phylib.h" static int __air_buckpbus_reg_read(struct mdio_device *mdiodev, u32 pbus_address, u32 *pbus_data) @@ -198,6 +203,261 @@ int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, } EXPORT_SYMBOL_GPL(air_phy_buckpbus_reg_modify); +static int __air_write_buf(struct mdio_device *mdiodev, u32 address, + const struct firmware *fw) +{ + unsigned int offset; + int ret; + u16 val; + + ret = __mdiodev_write(mdiodev, AIR_BPBUS_MODE, + AIR_BPBUS_MODE_ADDR_INCR); + if (ret < 0) + return ret; + + ret = __mdiodev_write(mdiodev, AIR_BPBUS_WR_ADDR_HIGH, + upper_16_bits(address)); + if (ret < 0) + return ret; + + ret = __mdiodev_write(mdiodev, AIR_BPBUS_WR_ADDR_LOW, + lower_16_bits(address)); + if (ret < 0) + return ret; + + for (offset = 0; offset < fw->size; offset += 4) { + val = get_unaligned_le16(&fw->data[offset + 2]); + ret = __mdiodev_write(mdiodev, AIR_BPBUS_WR_DATA_HIGH, val); + if (ret < 0) + return ret; + + val = get_unaligned_le16(&fw->data[offset]); + ret = __mdiodev_write(mdiodev, AIR_BPBUS_WR_DATA_LOW, val); + if (ret < 0) + return ret; + } + + return 0; +} + +/* phy_select_page() needs a phy_device, which does not exist yet. */ +static int __air_mdio_select_page(struct mdio_device *mdiodev, int page) +{ + int saved_page, ret; + + saved_page = __mdiodev_read(mdiodev, AIR_EXT_PAGE_ACCESS); + if (saved_page < 0) + return saved_page; + + if (saved_page != page) { + ret = __mdiodev_write(mdiodev, AIR_EXT_PAGE_ACCESS, page); + if (ret < 0) + return ret; + } + + return saved_page; +} + +static int __air_mdio_restore_page(struct mdio_device *mdiodev, + int saved_page, int page, int ret) +{ + int restore; + + if (saved_page != page) { + restore = __mdiodev_write(mdiodev, AIR_EXT_PAGE_ACCESS, + saved_page); + if (ret >= 0 && restore < 0) + ret = restore; + } + + return ret; +} + +int air_fw_write_buf(struct mdio_device *mdiodev, u32 address, + const struct firmware *fw) +{ + int saved_page, ret; + + mdiodev_lock(mdiodev); + + saved_page = __air_mdio_select_page(mdiodev, AIR_PHY_PAGE_EXTENDED_4); + if (saved_page < 0) { + ret = saved_page; + } else { + ret = __air_write_buf(mdiodev, address, fw); + ret = __air_mdio_restore_page(mdiodev, saved_page, + AIR_PHY_PAGE_EXTENDED_4, ret); + } + + mdiodev_unlock(mdiodev); + return ret; +} +EXPORT_SYMBOL_GPL(air_fw_write_buf); + +static int air_mdio_buckpbus_reg_read(struct mdio_device *mdiodev, + u32 pbus_address, u32 *pbus_data) +{ + int saved_page, ret; + + mdiodev_lock(mdiodev); + + saved_page = __air_mdio_select_page(mdiodev, AIR_PHY_PAGE_EXTENDED_4); + if (saved_page < 0) { + ret = saved_page; + } else { + ret = __air_buckpbus_reg_read(mdiodev, pbus_address, pbus_data); + ret = __air_mdio_restore_page(mdiodev, saved_page, + AIR_PHY_PAGE_EXTENDED_4, ret); + } + + mdiodev_unlock(mdiodev); + return ret; +} + +static int air_mdio_buckpbus_reg_write(struct mdio_device *mdiodev, + u32 pbus_address, u32 pbus_data) +{ + int saved_page, ret; + + mdiodev_lock(mdiodev); + + saved_page = __air_mdio_select_page(mdiodev, AIR_PHY_PAGE_EXTENDED_4); + if (saved_page < 0) { + ret = saved_page; + } else { + ret = __air_buckpbus_reg_write(mdiodev, pbus_address, + pbus_data); + ret = __air_mdio_restore_page(mdiodev, saved_page, + AIR_PHY_PAGE_EXTENDED_4, ret); + } + + mdiodev_unlock(mdiodev); + return ret; +} + +static int air_mdio_buckpbus_reg_modify(struct mdio_device *mdiodev, + u32 pbus_address, u32 mask, u32 set) +{ + int saved_page, ret; + + mdiodev_lock(mdiodev); + + saved_page = __air_mdio_select_page(mdiodev, AIR_PHY_PAGE_EXTENDED_4); + if (saved_page < 0) { + ret = saved_page; + } else { + ret = __air_buckpbus_reg_modify(mdiodev, pbus_address, + mask, set); + ret = __air_mdio_restore_page(mdiodev, saved_page, + AIR_PHY_PAGE_EXTENDED_4, ret); + } + + mdiodev_unlock(mdiodev); + return ret; +} + +static int air_mmd_status_read(struct mdio_device *mdiodev) +{ + int ret; + + mdiodev_lock(mdiodev); + ret = mmd_phy_read(mdiodev->bus, mdiodev->addr, false, + MDIO_MMD_VEND1, EN8811H_PHY_FW_STATUS); + mdiodev_unlock(mdiodev); + + return ret; +} + +int air_en8811h_wait_mcu_ready(struct mdio_device *mdiodev) +{ + int ret, reg_value; + + ret = air_mdio_buckpbus_reg_write(mdiodev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); + if (ret) + return ret; + + /* Because of mdio-lock, may have to wait for multiple loads. A read + * error ends the poll at once, like phy_read_mmd_poll_timeout() + * would: the bus is not going to heal within the timeout. + */ + ret = read_poll_timeout(air_mmd_status_read, reg_value, + reg_value < 0 || + reg_value == EN8811H_PHY_READY, + 20000, 7500000, true, mdiodev); + if (reg_value < 0) + return reg_value; + if (ret) { + dev_err(&mdiodev->dev, "MCU not ready: 0x%x\n", reg_value); + return -ENODEV; + } + + return 0; +} +EXPORT_SYMBOL_GPL(air_en8811h_wait_mcu_ready); + +int air_en8811h_fw_download(struct mdio_device *mdiodev, u32 *fw_version) +{ + const struct firmware *fw1, *fw2; + struct device *dev = &mdiodev->dev; + int ret; + + ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev); + if (ret < 0) + return ret; + + ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev); + if (ret < 0) + goto air_fw_download_rel1; + + ret = air_mdio_buckpbus_reg_write(mdiodev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); + if (ret < 0) + goto air_fw_download_out; + + ret = air_mdio_buckpbus_reg_modify(mdiodev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, + EN8811H_FW_CTRL_2_LOADING); + if (ret < 0) + goto air_fw_download_out; + + ret = air_fw_write_buf(mdiodev, AIR_FW_ADDR_DM, fw1); + if (ret < 0) + goto air_fw_download_out; + + ret = air_fw_write_buf(mdiodev, AIR_FW_ADDR_DSP, fw2); + if (ret < 0) + goto air_fw_download_out; + + ret = air_mdio_buckpbus_reg_modify(mdiodev, EN8811H_FW_CTRL_2, + EN8811H_FW_CTRL_2_LOADING, 0); + if (ret < 0) + goto air_fw_download_out; + + ret = air_en8811h_wait_mcu_ready(mdiodev); + if (ret < 0) + goto air_fw_download_out; + + ret = air_mdio_buckpbus_reg_read(mdiodev, EN8811H_FW_VERSION, + fw_version); + if (ret < 0) + goto air_fw_download_out; + + dev_info(dev, "MD32 firmware version: %08x\n", *fw_version); + +air_fw_download_out: + release_firmware(fw2); + +air_fw_download_rel1: + release_firmware(fw1); + + /* No error print: callers log on their own terms, and a poller + * would repeat it on every retry. + */ + return ret; +} +EXPORT_SYMBOL_GPL(air_en8811h_fw_download); + int air_phy_read_page(struct phy_device *phydev) { return __phy_read(phydev, AIR_EXT_PAGE_ACCESS); diff --git a/drivers/net/phy/air_phy_lib.h b/drivers/net/phy/air_phy_lib.h index 01bb32e7c7c9..2a4c156d6396 100644 --- a/drivers/net/phy/air_phy_lib.h +++ b/drivers/net/phy/air_phy_lib.h @@ -29,6 +29,23 @@ #define AIR_BPBUS_RD_DATA_HIGH 0x17 #define AIR_BPBUS_RD_DATA_LOW 0x18 +#define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" +#define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" + +#define AIR_FW_ADDR_DM 0x00000000 +#define AIR_FW_ADDR_DSP 0x00100000 + +#define EN8811H_FW_CTRL_1 0x0f0018 +#define EN8811H_FW_CTRL_1_START 0x0 +#define EN8811H_FW_CTRL_1_FINISH 0x1 +#define EN8811H_FW_CTRL_2 0x800000 +#define EN8811H_FW_CTRL_2_LOADING BIT(11) + +#define EN8811H_PHY_FW_STATUS 0x8009 +#define EN8811H_PHY_READY 0x02 + +#define EN8811H_FW_VERSION 0x3b3c + int air_phy_buckpbus_reg_modify(struct phy_device *phydev, u32 pbus_address, u32 mask, u32 set); int air_phy_buckpbus_reg_read(struct phy_device *phydev, u32 pbus_address, @@ -38,4 +55,11 @@ int air_phy_buckpbus_reg_write(struct phy_device *phydev, u32 pbus_address, int air_phy_read_page(struct phy_device *phydev); int air_phy_write_page(struct phy_device *phydev, int page); +struct firmware; + +int air_fw_write_buf(struct mdio_device *mdiodev, u32 address, + const struct firmware *fw); +int air_en8811h_wait_mcu_ready(struct mdio_device *mdiodev); +int air_en8811h_fw_download(struct mdio_device *mdiodev, u32 *fw_version); + #endif /* __AIR_PHY_LIB_H */ -- 2.53.0