Re: [PATCH net-next V4 04/11] net/mlx5: qos: Add ifc support for cross-esw scheduling

[Tariq Toukan <ttoukan.linux@gmail.com>]

This IFC patch is targeted to mlx5-next.
Sorry for the confusion.

On 03/12/2024 22:29, Tariq Toukan wrote:
> From: Cosmin Ratiu <cratiu@nvidia.com>
> 
> This adds the capability bit and the vport element fields related to
> cross-esw scheduling.
> 
> Signed-off-by: Cosmin Ratiu <cratiu@nvidia.com>
> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
> ---
>   include/linux/mlx5/mlx5_ifc.h | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
> index 8b202521b774..5451ff1d4356 100644
> --- a/include/linux/mlx5/mlx5_ifc.h
> +++ b/include/linux/mlx5/mlx5_ifc.h
> @@ -1095,7 +1095,9 @@ struct mlx5_ifc_qos_cap_bits {
>   	u8         log_esw_max_sched_depth[0x4];
>   	u8         reserved_at_10[0x10];
>   
> -	u8         reserved_at_20[0xb];
> +	u8         reserved_at_20[0x9];
> +	u8         esw_cross_esw_sched[0x1];
> +	u8         reserved_at_2a[0x1];
>   	u8         log_max_qos_nic_queue_group[0x5];
>   	u8         reserved_at_30[0x10];
>   
> @@ -4139,13 +4141,16 @@ struct mlx5_ifc_tsar_element_bits {
>   };
>   
>   struct mlx5_ifc_vport_element_bits {
> -	u8         reserved_at_0[0x10];
> +	u8         reserved_at_0[0x4];
> +	u8         eswitch_owner_vhca_id_valid[0x1];
> +	u8         eswitch_owner_vhca_id[0xb];
>   	u8         vport_number[0x10];
>   };
>   
>   struct mlx5_ifc_vport_tc_element_bits {
>   	u8         traffic_class[0x4];
> -	u8         reserved_at_4[0xc];
> +	u8         eswitch_owner_vhca_id_valid[0x1];
> +	u8         eswitch_owner_vhca_id[0xb];
>   	u8         vport_number[0x10];
>   };
>