From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Zxyan Zhu <zxyan0222@gmail.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next] net: stmmac: dwxgmac2: configure INTM for per-channel interrupt routing
Date: Thu, 23 Jul 2026 15:50:50 +0200 [thread overview]
Message-ID: <f979a974-a9ad-4f4d-9e57-9f88900298a2@bootlin.com> (raw)
In-Reply-To: <20260723132457.3061337-1-zxyan0222@gmail.com>
Hi,
On 7/23/26 15:24, Zxyan Zhu wrote:
> The XGMAC DMA_MODE register has an INTM field (bits 13:12) that
> controls interrupt routing behavior for DMA transfer completion
> events:
>
> 00 (default): sbd_perch_* are pulse signals, sbd_intr_o is also
> asserted for each completion event.
> 01: sbd_perch_* are level signals, sbd_intr_o is NOT
> asserted for packet transfer completion events.
>
> When multi-MSI is enabled (dma_cfg->multi_msi_en), per-channel TX/RX
> interrupts are expected to arrive on their dedicated lines
> (sbd_perch_tx_intr_o / sbd_perch_rx_intr_o). In the default INTM=00
> mode, sbd_intr_o also fires for DMA completion events, but the
> multi-MSI handler stmmac_mac_interrupt() only processes MAC-layer
> events (LPI, PMT, timestamps) and does not service DMA channels,
> silently dropping the interrupt.
>
> Set INTM to mode 1 when multi-MSI is enabled, following the same
> pattern as the GMAC4 DMA_BUS_MODE_INTM configuration in commit
> 6ccf12ae111e ("net: stmmac: use interrupt mode INTM=1 for multi-MSI").
>
> Signed-off-by: Zxyan Zhu <zxyan0222@gmail.com>
Same logic as in dwmac4, this looks good to me,
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
next prev parent reply other threads:[~2026-07-23 13:50 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 13:24 [PATCH net-next] net: stmmac: dwxgmac2: configure INTM for per-channel interrupt routing Zxyan Zhu
2026-07-23 13:50 ` Maxime Chevallier [this message]
2026-07-28 1:16 ` Jakub Kicinski
2026-07-28 3:43 ` Zxyan Zhu
2026-07-28 22:19 ` Jakub Kicinski
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