Re: 2.6.20-rc7: known regressions (v2) (part 1)

[ebiederm@xmission.com (Eric W. Biederman)]

Auke Kok <auke-jan.h.kok@intel.com> writes:

> maybe I've been unclear, but here's how e1000 detects link changes:
>
> 1) by checking every 2 seconds in the watchdog by reading PHY registers
> 2) by receiving an interrupt from the NIC with the LSI bit in the interrupt
> control register
>
> if the link is down to start with, the watchdog will obviously spot a 'link up'
> change since it doesn't use any interrupts.
>
> The link interrupt (LSI) is a generic interrupt that comes over the same vector
> (be it MSI or not) as RX interrupts, and in your case doesn't arrive at all,
> which should be demonstrateable if you set e.g. the watchdog interval to 30
> seconds and unplug the cable - the driver won't spot the link change until the
> watchdog fires a lot later than you unplugged the cable.
>
>> The behavior I observe on 2.6.19 is better than 2.6.20-rc7. Link status
>> interrupts seem to work but rx/tx does not. A few more details here:
>>
> <http://www.kroptech.com/~adk0212/mailimport/showmsg.php?msg_id=3339092450&db_name=linux_kernel>
>
>> I'm going to test 2.6.16 thru 2.6.20-rc7 this weekend and will report
>> back any variations in behavior I notice.
>
> that would be a good start, but I still think that you might have a broken
> bridge on that system. Anyway, thanks for digging into this.

Right.  The basic question is on a problem system are MSI interrupts
from the card in /proc/interrupts observed.  If interrupts are not
observed (as it sounds like is the case) it is most likely something
outside of the card, and driver.  If interrupts are observed but the
card does not work correctly it could be a card or driver bug.

Ok.  In the archives I finally found the output of cat
/proc/interrupts and there were none.

This is a PCI-E to Hypertransport system from the lspci output.

Can I get the corresponding lspci -xxx output.  I suspect the BIOS
did not program the hypertransport MSI mapping capabilities correctly.
All it has to do is set the enable but still, occasionally BIOS
writers miss the most amazing things.

If that is the case with just a little creativity we should be able to
write a pci quirk that will enable the MSI mapping capability on this
class of systems and save ourselves a lot of trouble.

Although I thought I did see a quirk that disabled MSI if the enable
bit was not set.  Hmm.

Anyway please the lspci -xxx output.  Although if someone could teach
lspci to decode the hypertransport MSI mapping capability so that
lspic -vvv gave us this information that would be great too.

Eric