From mboxrd@z Thu Jan 1 00:00:00 1970 From: Krzysztof Halasa Subject: Re: E100 RX ring buffers continued... Date: Sat, 22 Aug 2009 17:32:35 +0200 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: David Miller , Jeff Kirsher , Jesse Brandeburg , Bruce Allan , PJ Waskiewicz , John Ronciak To: Return-path: Received: from khc.piap.pl ([195.187.100.11]:50734 "EHLO khc.piap.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754943AbZHVPcf (ORCPT ); Sat, 22 Aug 2009 11:32:35 -0400 In-Reply-To: (Krzysztof Halasa's message of "Sat\, 22 Aug 2009 16\:09\:00 +0200") Sender: netdev-owner@vger.kernel.org List-ID: Krzysztof Halasa writes: > There is also apparently unsupported and mostly undocumented "flexible > mode". The question to Intel's experts: can the flexible mode be used > anyway? I can write the code, but need info about eg. the data > structures (RFD, how does it work in flexible mode) and a confirmation > the silicon (or maybe which silicon) will work with it. I can see there is some "erratum" in 82559 related to flexible RX mode. It seems we're not affected, though - it requires more than 1 RBD (per RFD I hope) for the problem to happen. Do I get it right? -- Krzysztof Halasa