* Re: [PATCH 2/5] forcedeth: interrupt handling cleanup
From: Jeff Garzik @ 2007-10-07 11:40 UTC (permalink / raw)
To: Yinghai Lu; +Cc: netdev, Ayaz Abdulla, LKML, Andrew Morton
In-Reply-To: <86802c440710062143x3bb801c3obb91292208073588@mail.gmail.com>
Yinghai Lu wrote:
> On 10/6/07, Jeff Garzik <jeff@garzik.org> wrote:
>> commit a606d2a111cdf948da5d69eb1de5526c5c2dafef
>> Author: Jeff Garzik <jeff@garzik.org>
>> Date: Fri Oct 5 22:56:05 2007 -0400
>>
>> [netdrvr] forcedeth: interrupt handling cleanup
>>
>> * nv_nic_irq_optimized() and nv_nic_irq_other() were complete duplicates
>> of nv_nic_irq(), with the exception of one function call. Consolidate
>> all three into a single interrupt handler, deleting a lot of redundant
>> code.
>>
>> * greatly simplify irq handler locking.
>>
>> Prior to this change, the irq handler(s) would acquire and release
>> np->lock for each action (RX, TX, other events).
>>
>> For the common case -- RX or TX work -- the lock is always acquired,
>> making all successive acquire/release combinations largely redundant.
>>
>> Acquire the lock at the beginning of the irq handler, and release it at
>> the end of the irq handler. This is simple, easy, and obvious.
>>
>> * remove irq handler work loop.
>>
>> All interesting events emanating from the irq handler either have
>> their own work loops, or they poke a timer into action.
>>
>> Therefore, delete the pointless master interrupt handler work loop.
>>
>> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
>>
>> drivers/net/forcedeth.c | 325 +++++++++++-------------------------------------
>> 1 file changed, 77 insertions(+), 248 deletions(-)
>>
> any chance to create three verion irq handlers for ioapic, msi, msi-x...?
>
> MACRO or inline function?
MSI-X already has its own separate interrupt handlers. MSI and INTx
call the same interrupt handling code, like the unmodified driver goes.
Creating an MSI-specific irq handler would not save very much AFAICS,
but I might be missing something.
Do you have ideas/suggestions for a different method?
Jeff
^ permalink raw reply
* 2.6.23-rc8-mm2 BUG: register_netdevice() issue as (ab)used by ISDN
From: Andreas Mohr @ 2007-10-07 12:06 UTC (permalink / raw)
To: isdn4linux; +Cc: netdev, akpm
[not necessarily a very recent regression, used 2.6.19 kernels before...]
Hi all,
wondered why my main internet server (headless!) didn't come up properly
on a new 2.6.23-rc8-mm2
(connections almost completely refused: firewalling not executed due to
earlier OOPS?).
Upon LILO emergency fallback into an older version (2.6.16...) saw this
in /var/log/messages:
Oct 7 13:07:34 gate kernel: e100: Intel(R) PRO/100 Network Driver, 3.5.23-k4-NAPI
Oct 7 13:07:34 gate kernel: e100: Copyright(c) 1999-2006 Intel Corporation
Oct 7 13:07:34 gate kernel: Atmel at76x USB Wireless LAN Driver 0.16 loading
Oct 7 13:07:34 gate kernel: eth2: MAC address 00:05:5d:95:ab:f0
Oct 7 13:07:34 gate kernel: eth2: firmware version 1.101.5-84
Oct 7 13:07:34 gate kernel: eth2: regulatory domain 0x30: ETSI (most of Europe)
Oct 7 13:07:34 gate kernel: usbcore: registered new interface driver at76_usb
Oct 7 13:07:34 gate kernel: Netfilter messages via NETLINK v0.30.
Oct 7 13:07:34 gate kernel: nf_conntrack version 0.5.0 (2048 buckets, 8192 max)
Oct 7 13:07:34 gate kernel: nf_conntrack_ipv4: Unknown parameter `hashsize'
Oct 7 13:07:34 gate kernel: ip_tables: (C) 2000-2006 Netfilter Core Team
Oct 7 13:07:34 gate kernel: process `syslogd' is using obsolete setsockopt SO_BSD
COMPAT
Oct 7 13:07:40 gate kernel: ------------[ cut here ]------------
Oct 7 13:07:40 gate kernel: kernel BUG at net/core/dev.c:3485!
Oct 7 13:07:40 gate kernel: invalid opcode: 0000 [#1]
Oct 7 13:07:40 gate kernel: last sysfs file: /devices/platform/sis5595.656/temp1_
max
Oct 7 13:07:40 gate kernel: Modules linked in: xt_state xt_limit xt_tcpudp xt_mul
tiport iptable_mangle iptable_nat nf_conntrack_ipv4 iptable_filter ip_tables nf_na
t_tftp nf_conntrack_tftp nf_nat_h323 nf_conntrack_h323 nf_nat_irc nf_nat_ftp nf_co
nntrack_irc nf_conntrack_ftp ipt_MASQUERADE nf_nat nf_conntrack nfnetlink ipt_REJE
CT ipt_LOG x_tables at76_usb firmware_class e100 ohci_hcd usbcore i2c_sis630 i2c_s
is5595 i2c_core sis5595 hisax isdn eepro100
Oct 7 13:07:40 gate kernel:
Oct 7 13:07:40 gate kernel: Pid: 2235, comm: isdnctrl Not tainted (2.6.23-rc8-mm2
-gate #1)
Oct 7 13:07:40 gate kernel: EIP: 0060:[<c029ad8a>] EFLAGS: 00010246 CPU: 0
Oct 7 13:07:40 gate kernel: EIP is at register_netdevice+0x6d/0x2c1
Oct 7 13:07:40 gate kernel: EAX: 00000000 EBX: c786501c ECX: 00000000 EDX: 00000d
99
Oct 7 13:07:40 gate kernel: ESI: c786501c EDI: 00000000 EBP: c1657d08 ESP: c1657c
ec
Oct 7 13:07:40 gate kernel: DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 0068
Oct 7 13:07:40 gate kernel: Process isdnctrl (pid: 2235, ti=c1656000 task=c14c306
0 task.ti=c1656000)
Oct 7 13:07:40 gate kernel: Stack: c786501c 00000000 c1657d00 c0309ec6 c1657d68 c
786501c 00000000 c1657d18
Oct 7 13:07:40 gate kernel: c029b010 c1657d68 c7865000 c1657d38 c885a0fa c
884e39c c8864598 c786501c
Oct 7 13:07:40 gate kernel: c1657d68 00000000 bfbf779d c1657f60 c886484d c
212ef80 c1561980 c1805ab0
Oct 7 13:07:40 gate kernel: Call Trace:
Oct 7 13:07:40 gate kernel: [<c029b010>] register_netdev+0x32/0x3f
Oct 7 13:07:40 gate kernel: [<c885a0fa>] isdn_net_new+0x111/0x2ca [isdn]
Oct 7 13:07:40 gate kernel: [<c886484d>] isdn_ioctl+0x2b5/0xb46 [isdn]
Oct 7 13:07:40 gate kernel: [<c015f53c>] do_ioctl+0x40/0x50
Oct 7 13:07:40 gate kernel: [<c015f738>] vfs_ioctl+0x1ec/0x203
Oct 7 13:07:40 gate kernel: [<c015f780>] sys_ioctl+0x31/0x49
Oct 7 13:07:40 gate kernel: [<c0103e12>] syscall_call+0x7/0xb
Oct 7 13:07:40 gate kernel: [<b7f54de4>] 0xb7f54de4
Oct 7 13:07:40 gate kernel: =======================
Oct 7 13:07:40 gate kernel: Code: e8 3f a5 e6 ff ba 99 0d 00 00 b8 b4 3c 38 c0 e8
96 82 e7 ff 83 bb 20 02 00 00 00 74 04 0f 0b eb fe 8b 83 80 02 00 00 85 c0 75 04
<0f> 0b eb fe 89 45 f0 b9 4c 2e 48 c0 ba 8e 3e 38 c0 8d 83 78 01
Oct 7 13:07:40 gate kernel: EIP: [<c029ad8a>] register_netdevice+0x6d/0x2c1 SS:ES
P 0068:c1657cec
Oct 7 13:18:17 gate syslogd 1.4.1#20: restart.
Oct 7 13:18:17 gate kernel: klogd 1.4.1#20, log source = /proc/kmsg started.
Oct 7 13:18:17 gate kernel: Linux version 2.6.16-cks11-gate (root@gate) (gcc vers
ion 4.0.4 20060507 (prerelease) (Debian 4.0.3-3)) #1 Sat May 27 14:45:18 CEST 2006
[logging was then back into 2.6.16 above]
2.6.23-rc8-mm2/net/core/dev.c/register_netdevice():
int register_netdevice(struct net_device *dev)
{
struct hlist_head *head;
struct hlist_node *p;
int ret;
struct net *net;
BUG_ON(dev_boot_phase);
ASSERT_RTNL();
might_sleep();
/* When net_device's are persistent, this will be fatal. */
BUG_ON(dev->reg_state != NETREG_UNINITIALIZED);
BUG_ON(!dev->nd_net);
net = dev->nd_net;
spin_lock_init(&dev->queue_lock);
spin_lock_init(&dev->_xmit_lock);
netdev_set_lockdep_class(&dev->_xmit_lock, dev->type);
dev->xmit_lock_owner = -1;
spin_lock_init(&dev->ingress_lock);
dev->iflink = -1;
/* Init, if this function is available */
if (dev->init) {
ret = dev->init(dev);
if (ret) {
if (ret > 0)
ret = -EIO;
goto out;
}
}
objdump -D linux-2.6.23-rc8-mm2/vmlinux|less :
c029ad1d <register_netdevice>:
c029ad1d: 55 push %ebp
c029ad1e: 89 e5 mov %esp,%ebp
c029ad20: 57 push %edi
c029ad21: 56 push %esi
c029ad22: 53 push %ebx
c029ad23: 89 c3 mov %eax,%ebx
c029ad25: 83 ec 10 sub $0x10,%esp
c029ad28: 83 3d 4c fa 41 c0 00 cmpl $0x0,0xc041fa4c
c029ad2f: 74 04 je c029ad35 <register_netdevice+0x18>
c029ad31: 0f 0b ud2a
c029ad33: eb fe jmp c029ad33 <register_netdevice+0x16>
c029ad35: e8 7e 7f 00 00 call c02a2cb8 <rtnl_trylock>
c029ad3a: 85 c0 test %eax,%eax
c029ad3c: 74 26 je c029ad64 <register_netdevice+0x47>
c029ad3e: e8 79 78 00 00 call c02a25bc <rtnl_unlock>
c029ad43: c7 44 24 08 97 0d 00 movl $0xd97,0x8(%esp)
c029ad4a: 00
c029ad4b: c7 44 24 04 b4 3c 38 movl $0xc0383cb4,0x4(%esp)
c029ad52: c0
c029ad53: c7 04 24 c3 3c 38 c0 movl $0xc0383cc3,(%esp)
c029ad5a: e8 13 e3 e7 ff call c0119072 <printk>
c029ad5f: e8 3f a5 e6 ff call c01052a3 <dump_stack>
c029ad64: ba 99 0d 00 00 mov $0xd99,%edx
c029ad69: b8 b4 3c 38 c0 mov $0xc0383cb4,%eax
c029ad6e: e8 96 82 e7 ff call c0113009 <__might_sleep>
c029ad73: 83 bb 20 02 00 00 00 cmpl $0x0,0x220(%ebx)
c029ad7a: 74 04 je c029ad80 <register_netdevice+0x63>
c029ad7c: 0f 0b ud2a
c029ad7e: eb fe jmp c029ad7e <register_netdevice+0x61>
c029ad80: 8b 83 80 02 00 00 mov 0x280(%ebx),%eax
c029ad86: 85 c0 test %eax,%eax
c029ad88: 75 04 jne c029ad8e <register_netdevice+0x71>
c029ad8a: 0f 0b ud2a
c029ad8c: eb fe jmp c029ad8c <register_netdevice+0x6f>
c029ad8e: 89 45 f0 mov %eax,0xfffffff0(%ebp)
c029ad91: b9 4c 2e 48 c0 mov $0xc0482e4c,%ecx
c029ad96: ba 8e 3e 38 c0 mov $0xc0383e8e,%edx
c029ad9b: 8d 83 78 01 00 00 lea 0x178(%ebx),%eax
c029ada1: e8 8e d9 f7 ff call c0218734 <__spin_lock_init>
c029ada6: 8d 83 b4 01 00 00 lea 0x1b4(%ebx),%eax
c029adac: b9 4c 2e 48 c0 mov $0xc0482e4c,%ecx
c029adb1: ba 9f 3e 38 c0 mov $0xc0383e9f,%edx
c029adb6: e8 79 d9 f7 ff call c0218734 <__spin_lock_init>
c029adbb: ba b0 3e 38 c0 mov $0xc0383eb0,%edx
c029adc0: b9 4c 2e 48 c0 mov $0xc0482e4c,%ecx
c029adc5: c7 83 c4 01 00 00 ff movl $0xffffffff,0x1c4(%ebx)
c029adcc: ff ff ff
c029adcf: 8d 83 a0 01 00 00 lea 0x1a0(%ebx),%eax
c029add5: e8 5a d9 f7 ff call c0218734 <__spin_lock_init>
c029adda: 8b 53 40 mov 0x40(%ebx),%edx
c029addd: c7 43 50 ff ff ff ff movl $0xffffffff,0x50(%ebx)
c029ade4: 85 d2 test %edx,%edx
c029ade6: 74 1b je c029ae03 <register_netdevice+0xe6>
Since EIP is c029ad8a, following the code flow it clearly looks to me
as if it's the
BUG_ON(!dev->nd_net);
check which caused the BUG message.
This is a K6-3/450@150 running Debian stable.
lsmod (NOTE: this is on 2.6.16!!):
Module Size Used by
sch_ingress 4356 1
cls_u32 7044 5
sch_tbf 6272 1
sch_sfq 5632 4
sch_htb 15616 1
ppp_async 11648 1
crc_ccitt 2176 1 ppp_async
ipt_ULOG 7712 1
xt_state 2176 4
xt_limit 2688 11
xt_tcpudp 3328 48
ipt_multiport 2560 10
iptable_mangle 2816 0
iptable_nat 7684 1
iptable_filter 3072 1
ip_tables 11736 3 iptable_mangle,iptable_nat,iptable_filter
ip_nat_tftp 1920 0
ip_conntrack_tftp 4244 1 ip_nat_tftp
ip_nat_irc 2688 0
ip_nat_ftp 3200 0
ip_conntrack_irc 6680 1 ip_nat_irc
ip_conntrack_ftp 7324 1 ip_nat_ftp
ipt_MASQUERADE 3712 1
ip_nat 15764 5 iptable_nat,ip_nat_tftp,ip_nat_irc,ip_nat_ftp,ipt_MASQUERADE
ip_conntrack 44196 10 xt_state,iptable_nat,ip_nat_tftp,ip_conntrack_tftp,ip_nat_irc,ip_nat_ftp,ip_conntrack_irc,ip_conntrack_ftp,ipt_MASQUERADE,ip_nat
ipt_REJECT 5248 0
ipt_LOG 6144 11
x_tables 12292 10 ipt_ULOG,xt_state,xt_limit,xt_tcpudp,ipt_multiport,iptable_nat,ip_tables,ipt_MASQUERADE,ipt_REJECT,ipt_LOG
e100 33284 0
at76c503_rfmd 5260 0
firmware_class 10112 1 at76c503_rfmd
at76c503 79840 1 at76c503_rfmd
at76_usbdfu 4996 1 at76c503
ohci_hcd 29700 0
usbcore 126240 5 at76c503_rfmd,at76c503,at76_usbdfu,ohci_hcd
i2c_sis630 8844 0
i2c_sis5595 7940 0
sis5595 14216 0
i2c_isa 5888 1 sis5595
i2c_core 22144 4 i2c_sis630,i2c_sis5595,sis5595,i2c_isa
hisax 175100 2
isdn 108864 5 hisax
eepro100 29456 0
root@gate:/usr/src/linux-2.6.23-rc8-mm2/net# dpkg -l|grep isdn
ii isdnlog 3.9.20060704-3 ISDN connection logger
ii isdnlog-data 3.9.20060704-3 data for isdnlog users
ii isdnutils 3.9.20060704-3 Most important ISDN-related packages and uti
ii isdnutils-base 3.9.20060704-3 ISDN utilities, the basic (minimal) set
ii isdnutils-xtools 3.9.20060704-3 ISDN utilities that use X
ii isdnvboxclient 3.9.20060704-3 ISDN answering machine, client
ii isdnvboxserver 3.9.20060704-3 ISDN answering machine, server
CONFIG_ISDN=m
CONFIG_ISDN_I4L=m
CONFIG_ISDN_PPP=y
CONFIG_ISDN_PPP_VJ=y
CONFIG_ISDN_MPP=y
# CONFIG_IPPP_FILTER is not set
CONFIG_ISDN_PPP_BSDCOMP=m
CONFIG_ISDN_AUDIO=y
# CONFIG_ISDN_TTY_FAX is not set
#
# ISDN feature submodules
#
CONFIG_ISDN_DRV_LOOP=m
# CONFIG_ISDN_DIVERSION is not set
#
# ISDN4Linux hardware drivers
#
#
# Passive cards
#
CONFIG_ISDN_DRV_HISAX=m
#
# D-channel protocol features
#
CONFIG_HISAX_EURO=y
CONFIG_DE_AOC=y
# CONFIG_HISAX_NO_SENDCOMPLETE is not set
# CONFIG_HISAX_NO_LLC is not set
# CONFIG_HISAX_NO_KEYPAD is not set
# CONFIG_HISAX_1TR6 is not set
# CONFIG_HISAX_NI1 is not set
CONFIG_HISAX_MAX_CARDS=8
#
# HiSax supported cards
#
# CONFIG_HISAX_16_0 is not set
CONFIG_HISAX_16_3=y
CONFIG_HISAX_TELESPCI=y
# CONFIG_HISAX_S0BOX is not set
# CONFIG_HISAX_AVM_A1 is not set
CONFIG_HISAX_FRITZPCI=y
# CONFIG_HISAX_AVM_A1_PCMCIA is not set
# CONFIG_HISAX_ELSA is not set
# CONFIG_HISAX_IX1MICROR2 is not set
# CONFIG_HISAX_DIEHLDIVA is not set
# CONFIG_HISAX_ASUSCOM is not set
# CONFIG_HISAX_TELEINT is not set
# CONFIG_HISAX_HFCS is not set
# CONFIG_HISAX_SEDLBAUER is not set
CONFIG_HISAX_SPORTSTER=y
# CONFIG_HISAX_MIC is not set
# CONFIG_HISAX_NETJET is not set
# CONFIG_HISAX_NETJET_U is not set
# CONFIG_HISAX_NICCY is not set
# CONFIG_HISAX_ISURF is not set
# CONFIG_HISAX_HSTSAPHIR is not set
# CONFIG_HISAX_BKM_A4T is not set
# CONFIG_HISAX_SCT_QUADRO is not set
# CONFIG_HISAX_GAZEL is not set
CONFIG_HISAX_HFC_PCI=y
CONFIG_HISAX_W6692=y
# CONFIG_HISAX_HFC_SX is not set
# CONFIG_HISAX_DEBUG is not set
#
# HiSax PCMCIA card service modules
#
#
# HiSax sub driver modules
#
# CONFIG_HISAX_ST5481 is not set
# CONFIG_HISAX_HFCUSB is not set
# CONFIG_HISAX_HFC4S8S is not set
CONFIG_HISAX_FRITZ_PCIPNP=m
#
# Active cards
#
# CONFIG_ISDN_DRV_ICN is not set
# CONFIG_ISDN_DRV_PCBIT is not set
# CONFIG_ISDN_DRV_SC is not set
# CONFIG_ISDN_DRV_ACT2000 is not set
# CONFIG_HYSDN is not set
# CONFIG_ISDN_DRV_GIGASET is not set
# CONFIG_ISDN_CAPI is not set
# CONFIG_PHONE is not set
lspci (NOTE: on 2.6.16!!):
00:09.0 Network controller: Cologne Chip Designs GmbH ISDN network controller [HFC-PCI] (rev 02)
I used to have an ISA-based card (Teles?) in there, replaced by the PCI one
about 2 years ago.
grep isdnctrl /etc/isdn/*:
/etc/isdn/device.ippp0:# Read the isdnctrl manpage for more info.
/etc/isdn/device.ippp0: isdnctrl addif ${device}
/etc/isdn/device.ippp0: isdnctrl eaz ${device} $LOCALMSN
/etc/isdn/device.ippp0: # "name". More than one number can be set by calling isdnc
trl addphone
/etc/isdn/device.ippp0: isdnctrl addphone ${device} out $LEADINGZE
RO$MSN
/etc/isdn/device.ippp0: # disabled. More than one number can be set by calling isd
nctrl addphone
/etc/isdn/device.ippp0: # isdnctrl addphone ${device} in $MSN
/etc/isdn/device.ippp0: # been added to the access list with isdnctrl addphone nam
e in.
/etc/isdn/device.ippp0: isdnctrl secure ${device} on
/etc/isdn/device.ippp0: isdnctrl huptimeout ${device} 180 # XXX_
/etc/isdn/device.ippp0: #isdnctrl dialmax ${device} 3
/etc/isdn/device.ippp0: #isdnctrl ihup ${device} on
/etc/isdn/device.ippp0: isdnctrl encap ${device} $ENCAP
/etc/isdn/device.ippp0: isdnctrl l2_prot ${device} hdlc
/etc/isdn/device.ippp0: isdnctrl l3_prot ${device} trans
/etc/isdn/device.ippp0: isdnctrl verbose 2
/etc/isdn/device.ippp0: #isdnctrl chargehup ${device} on
/etc/isdn/device.ippp0: #isdnctrl chargeint ${device} NUM
/etc/isdn/device.ippp0: #isdnctrl callback ${device} MODE
/etc/isdn/device.ippp0: #isdnctrl cbdelay ${device} SECONDS
/etc/isdn/device.ippp0: #isdnctrl cbhup ${device} MODE
/etc/isdn/device.ippp0: # See also : isdnctrl(8), isdnctrl help text
/etc/isdn/device.ippp0: isdnctrl pppbind ${device} $bindnum
/etc/isdn/device.ippp0: isdnctrl dialmode $device $DIALMODE >/dev/null 2>&1
/etc/isdn/device.ippp0: isdnctrl dialmode $device off >/dev/null 2>&1
/etc/isdn/device.ippp0: isdnctrl delif $device 2> /dev/null
/etc/isdn/init.d.functions: # can't count on "isdnctrl status all" working yet,
unfortunately...
/etc/isdn/init.d.functions: DEVS=`/usr/sbin/isdnctrl list all | grep 'Current
setup' | cut -f2 -d"'" | sort`
/etc/isdn/init.d.functions: if [ ! -e /dev/isdnctrl ]; then
/etc/isdn/init.d.functions: cd /dev && ln -s isdnctrl0 isdnctrl
/etc/isdn/init.d.functions: cardnum=0 # counts in channels, just like /dev/is
dnctrlX
/etc/isdn/init.d.functions: for optionfile in /etc/isdn/isdnlog.isdnctrl[02468]
; do
/etc/isdn/init.d.functions: devicenum=${device#isdnctrl}
/etc/isdn/init.d.functions: # test for isdnctrl dualmode. With dualmode, on
e isdnlog listens to
/etc/isdn/init.d.functions: for optionfile in /etc/isdn/isdnlog.isdnctrl?; do
/etc/isdn/init.d.functions: for optionfile in /etc/isdn/isdnlog.isdnctrl?; do
/etc/isdn/init.d.functions: /usr/sbin/isdnctrl delif $device >/
dev/null 2>&1 || true
/etc/isdn/init.d.functions: /usr/sbin/isdnctrl delif $device >/dev/null
2>&1 || true
/etc/isdn/netdown.old:eval `grep '^ isdnctrl addphone' /etc/isdn/device.ippp0
| sed 's,addphone,delphone,'`
/etc/isdn/netdown.old:/sbin/isdnctrl hangup ippp0
/etc/isdn/netup.old:eval `grep '^ isdnctrl addphone' /etc/isdn/device.ippp0`
/etc/isdn/stop: /usr/sbin/isdnctrl system off
/etc/isdn/xisdnload-netdown:# script again). So, putting "isdnctrl dialmode all of
f" here is not that
/etc/isdn/xisdnload-netdown:# useful, as you have to do "isdnctrl dialmode all aut
o" manually...
/etc/isdn/xisdnload-netdown:/usr/sbin/isdnctrl hangup ippp0 > /dev/null
/etc/isdn/xmonisdn-netdown:/usr/sbin/isdnctrl dialmode all off
/etc/isdn/xmonisdn-netup:/usr/sbin/isdnctrl dialmode all auto
I intend to still try to get it up and running with 2.6.23-rc8-mm2 today
(with some workarounds hopefully, maybe even disabling ISDN completely)...
The last running kernel (I didn't have newer ones in between), up for some 110
days was 2.6.19-cks2 (IOW, I cannot quite say that
"this is an important regression, it has been broken very recently").
Thanks,
Andreas Mohr
^ permalink raw reply
* Re: 2.6.23-rc8-mm2 BUG: register_netdevice() issue as (ab)used by ISDN
From: Jeff Garzik @ 2007-10-07 12:24 UTC (permalink / raw)
To: Andreas Mohr; +Cc: isdn4linux, netdev, akpm
In-Reply-To: <20071007120653.GA16184@rhlx01.hs-esslingen.de>
Andreas Mohr wrote:
> I intend to still try to get it up and running with 2.6.23-rc8-mm2 today
> (with some workarounds hopefully, maybe even disabling ISDN completely)...
>
> The last running kernel (I didn't have newer ones in between), up for some 110
> days was 2.6.19-cks2 (IOW, I cannot quite say that
> "this is an important regression, it has been broken very recently").
It definitely looks like ISDN is somehow to blame. Any chance you could
try git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.24.git ?
That would help narrow down the problem to a very-large set of
networking changes pending for 2.6.24.
If you can isolate it to net-2.6.24, it should be easily bisect-able
from there, if you have the patience :)
Jeff
^ permalink raw reply
* [NET] IPv6 oops bisected
From: Jeff Garzik @ 2007-10-07 12:52 UTC (permalink / raw)
To: netdev; +Cc: Linux Kernel Mailing List, Andrew Morton, den, David Miller
[-- Attachment #1: Type: text/plain, Size: 334 bytes --]
The commit
commit 5f5dace1ce001b24fb8286e09ffd3c4d2b547e09
Author: Denis V. Lunev <den@openvz.org>
Date: Thu Sep 27 12:41:26 2007 -0700
[NET]: Various dst_ifdown routines to catch refcounting bugs
causes a 100% reproducible oops in net-2.6.24.git, in ip6_route_add().
Platform: x86-64 Fedora 7
Config and lspci attached.
[-- Attachment #2: lspci.txt --]
[-- Type: text/plain, Size: 2579 bytes --]
00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3)
00:01.0 ISA bridge: nVidia Corporation CK804 ISA Bridge (rev a3)
00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2)
00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2)
00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3)
00:04.0 Multimedia audio controller: nVidia Corporation CK804 AC'97 Audio Controller (rev a2)
00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev f2)
00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3)
00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3)
00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2)
00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3)
00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3)
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration
00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map
00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller
00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control
05:05.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link)
40:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
40:01.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01)
40:02.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12)
40:02.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01)
41:04.0 VGA compatible controller: nVidia Corporation NV17 [GeForce4 MX 440] (rev a3)
61:04.0 SCSI storage controller: Marvell Technology Group Ltd. Unknown device 6042 (rev 02)
61:06.0 SCSI storage controller: LSI Logic / Symbios Logic 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI (rev 07)
61:06.1 SCSI storage controller: LSI Logic / Symbios Logic 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI (rev 07)
80:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3)
80:01.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3)
[-- Attachment #3: config.txt --]
[-- Type: text/plain, Size: 37276 bytes --]
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc9
# Sun Oct 7 08:44:56 2007
#
CONFIG_X86_64=y
CONFIG_64BIT=y
CONFIG_X86=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_ZONE_DMA32=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_SEMAPHORE_SLEEPERS=y
CONFIG_MMU=y
CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_X86_CMPXCHG=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_DMI=y
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
CONFIG_AUDIT=y
# CONFIG_AUDITSYSCALL is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CPUSETS is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_BLK_DEV_BSG=y
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# Processor type and features
#
CONFIG_X86_PC=y
# CONFIG_X86_VSMP is not set
CONFIG_MK8=y
# CONFIG_MPSC is not set
# CONFIG_MCORE2 is not set
# CONFIG_GENERIC_CPU is not set
CONFIG_X86_L1_CACHE_BYTES=64
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_INTERNODE_CACHE_BYTES=64
CONFIG_X86_TSC=y
CONFIG_X86_GOOD_APIC=y
# CONFIG_MICROCODE is not set
CONFIG_X86_MSR=m
CONFIG_X86_CPUID=m
CONFIG_X86_IO_APIC=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_MTRR=y
CONFIG_SMP=y
# CONFIG_SCHED_SMT is not set
CONFIG_SCHED_MC=y
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
# CONFIG_PREEMPT_BKL is not set
CONFIG_NUMA=y
# CONFIG_K8_NUMA is not set
CONFIG_NODES_SHIFT=6
CONFIG_X86_64_ACPI_NUMA=y
# CONFIG_NUMA_EMU is not set
CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_SELECT_MEMORY_MODEL=y
# CONFIG_FLATMEM_MANUAL is not set
CONFIG_DISCONTIGMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_DISCONTIGMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_NEED_MULTIPLE_NODES=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MIGRATION=y
CONFIG_RESOURCES_64BIT=y
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
CONFIG_OUT_OF_LINE_PFN_TO_PAGE=y
CONFIG_NR_CPUS=16
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_IOMMU=y
# CONFIG_CALGARY_IOMMU is not set
CONFIG_SWIOTLB=y
CONFIG_X86_MCE=y
# CONFIG_X86_MCE_INTEL is not set
CONFIG_X86_MCE_AMD=y
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
# CONFIG_RELOCATABLE is not set
CONFIG_PHYSICAL_START=0x200000
CONFIG_SECCOMP=y
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
CONFIG_K8_NB=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_ISA_DMA_API=y
CONFIG_GENERIC_PENDING_IRQ=y
#
# Power management options
#
CONFIG_PM=y
# CONFIG_PM_LEGACY is not set
# CONFIG_PM_DEBUG is not set
CONFIG_PM_SLEEP_SMP=y
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND_SMP_POSSIBLE=y
CONFIG_SUSPEND=y
CONFIG_HIBERNATION_SMP_POSSIBLE=y
# CONFIG_HIBERNATION is not set
CONFIG_ACPI=y
CONFIG_ACPI_SLEEP=y
# CONFIG_ACPI_PROCFS is not set
CONFIG_ACPI_PROC_EVENT=y
CONFIG_ACPI_AC=y
# CONFIG_ACPI_BATTERY is not set
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_FAN=y
# CONFIG_ACPI_DOCK is not set
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_NUMA=y
# CONFIG_ACPI_ASUS is not set
# CONFIG_ACPI_TOSHIBA is not set
CONFIG_ACPI_BLACKLIST_YEAR=0
# CONFIG_ACPI_DEBUG is not set
CONFIG_ACPI_EC=y
CONFIG_ACPI_POWER=y
CONFIG_ACPI_SYSTEM=y
CONFIG_X86_PM_TIMER=y
CONFIG_ACPI_CONTAINER=y
# CONFIG_ACPI_SBS is not set
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_TABLE=y
# CONFIG_CPU_FREQ_DEBUG is not set
CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
#
# CPUFreq processor drivers
#
CONFIG_X86_POWERNOW_K8=m
CONFIG_X86_POWERNOW_K8_ACPI=y
# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
CONFIG_X86_ACPI_CPUFREQ=m
#
# shared options
#
# CONFIG_X86_ACPI_CPUFREQ_PROC_INTF is not set
# CONFIG_X86_SPEEDSTEP_LIB is not set
#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCIEPORTBUS=y
CONFIG_HOTPLUG_PCI_PCIE=m
# CONFIG_HOTPLUG_PCI_PCIE_POLL_EVENT_MODE is not set
CONFIG_PCIEAER=y
CONFIG_ARCH_SUPPORTS_MSI=y
CONFIG_PCI_MSI=y
# CONFIG_PCI_DEBUG is not set
CONFIG_HT_IRQ=y
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_FAKE is not set
CONFIG_HOTPLUG_PCI_ACPI=m
# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=y
CONFIG_IA32_EMULATION=y
# CONFIG_IA32_AOUT is not set
CONFIG_COMPAT=y
CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
CONFIG_SYSVIPC_COMPAT=y
#
# Networking
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
CONFIG_XFRM=y
CONFIG_XFRM_USER=m
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
CONFIG_NET_KEY=m
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
# CONFIG_IP_PNP is not set
CONFIG_NET_IPIP=m
# CONFIG_NET_IPGRE is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
CONFIG_IPV6_PRIVACY=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
# CONFIG_IPV6_MIP6 is not set
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
CONFIG_IPV6_SIT=m
CONFIG_IPV6_TUNNEL=m
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=m
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
CONFIG_PNP=y
# CONFIG_PNP_DEBUG is not set
#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_FD=y
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=m
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=m
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=m
CONFIG_CHR_DEV_ST=m
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=m
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
CONFIG_SCSI_SAS_ATTRS=m
CONFIG_SCSI_SAS_LIBSAS=m
CONFIG_SCSI_SAS_ATA=y
# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
CONFIG_SCSI_AIC94XX=m
# CONFIG_AIC94XX_DEBUG is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_FC is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_LPFC is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
CONFIG_ATA=m
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_ACPI=y
CONFIG_SATA_AHCI=m
CONFIG_SATA_SVW=m
CONFIG_ATA_PIIX=m
CONFIG_SATA_MV=m
CONFIG_SATA_NV=m
CONFIG_PDC_ADMA=m
CONFIG_SATA_QSTOR=m
CONFIG_SATA_PROMISE=m
CONFIG_SATA_SX4=m
CONFIG_SATA_SIL=m
CONFIG_SATA_SIL24=m
CONFIG_SATA_SIS=m
CONFIG_SATA_ULI=m
CONFIG_SATA_VIA=m
CONFIG_SATA_VITESSE=m
CONFIG_SATA_INIC162X=m
CONFIG_PATA_ALI=m
CONFIG_PATA_AMD=m
CONFIG_PATA_ARTOP=m
CONFIG_PATA_ATIIXP=m
CONFIG_PATA_CMD640_PCI=m
CONFIG_PATA_CMD64X=m
CONFIG_PATA_CS5520=m
CONFIG_PATA_CS5530=m
CONFIG_PATA_CYPRESS=m
CONFIG_PATA_EFAR=m
CONFIG_ATA_GENERIC=m
CONFIG_PATA_HPT366=m
CONFIG_PATA_HPT37X=m
CONFIG_PATA_HPT3X2N=m
CONFIG_PATA_HPT3X3=m
CONFIG_PATA_HPT3X3_DMA=y
CONFIG_PATA_IT821X=m
CONFIG_PATA_IT8213=m
CONFIG_PATA_JMICRON=m
CONFIG_PATA_TRIFLEX=m
CONFIG_PATA_MARVELL=m
CONFIG_PATA_MPIIX=m
CONFIG_PATA_OLDPIIX=m
CONFIG_PATA_NETCELL=m
CONFIG_PATA_NS87410=m
CONFIG_PATA_OPTI=m
CONFIG_PATA_OPTIDMA=m
CONFIG_PATA_PDC_OLD=m
CONFIG_PATA_RADISYS=m
CONFIG_PATA_RZ1000=m
CONFIG_PATA_SC1200=m
CONFIG_PATA_SERVERWORKS=m
CONFIG_PATA_PDC2027X=m
CONFIG_PATA_SIL680=m
CONFIG_PATA_SIS=m
CONFIG_PATA_VIA=m
CONFIG_PATA_WINBOND=m
# CONFIG_MD is not set
#
# Fusion MPT device support
#
CONFIG_FUSION=y
CONFIG_FUSION_SPI=m
# CONFIG_FUSION_FC is not set
# CONFIG_FUSION_SAS is not set
CONFIG_FUSION_MAX_SGE=128
CONFIG_FUSION_CTL=m
# CONFIG_FUSION_LOGGING is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
CONFIG_IEEE1394=y
#
# Subsystem Options
#
# CONFIG_IEEE1394_VERBOSEDEBUG is not set
#
# Controllers
#
CONFIG_IEEE1394_PCILYNX=m
CONFIG_IEEE1394_OHCI1394=m
#
# Protocols
#
CONFIG_IEEE1394_VIDEO1394=m
CONFIG_IEEE1394_SBP2=m
# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y
CONFIG_IEEE1394_ETH1394=m
CONFIG_IEEE1394_DV1394=m
CONFIG_IEEE1394_RAWIO=m
# CONFIG_I2O is not set
# CONFIG_MACINTOSH_DRIVERS is not set
CONFIG_NETDEVICES=y
# CONFIG_NETDEVICES_MULTIQUEUE is not set
CONFIG_DUMMY=m
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=m
# CONFIG_VETH is not set
# CONFIG_NET_SB1000 is not set
# CONFIG_IP1000 is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=m
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
CONFIG_FORCEDETH=m
# CONFIG_FORCEDETH_NAPI is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
# CONFIG_E100 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_SC92031 is not set
CONFIG_NETDEV_1000=y
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_E1000E is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_SK98LIN is not set
# CONFIG_VIA_VELOCITY is not set
# CONFIG_TIGON3 is not set
# CONFIG_BNX2 is not set
# CONFIG_QLA3XXX is not set
# CONFIG_ATL1 is not set
CONFIG_NETDEV_10000=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGB is not set
# CONFIG_S2IO is not set
# CONFIG_MYRI10GE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TEHUTI is not set
# CONFIG_TR is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET_MII is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PCSPKR=y
# CONFIG_INPUT_ATLAS_BTNS is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
CONFIG_INPUT_UINPUT=m
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIO_RAW=m
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_SERIAL_8250_PCI=y
CONFIG_SERIAL_8250_PNP=y
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
CONFIG_NVRAM=y
CONFIG_RTC=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
CONFIG_AGP=y
CONFIG_AGP_AMD64=y
# CONFIG_AGP_INTEL is not set
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_VIA is not set
CONFIG_DRM=m
# CONFIG_DRM_TDFX is not set
# CONFIG_DRM_R128 is not set
# CONFIG_DRM_RADEON is not set
# CONFIG_DRM_MGA is not set
# CONFIG_DRM_SIS is not set
# CONFIG_DRM_VIA is not set
# CONFIG_DRM_SAVAGE is not set
# CONFIG_MWAVE is not set
# CONFIG_PC8736x_GPIO is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_HPET=y
# CONFIG_HPET_RTC_IRQ is not set
CONFIG_HPET_MMAP=y
# CONFIG_HANGCHECK_TIMER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
CONFIG_I2C=m
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=m
#
# I2C Algorithms
#
CONFIG_I2C_ALGOBIT=m
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
# CONFIG_I2C_I801 is not set
# CONFIG_I2C_I810 is not set
# CONFIG_I2C_PIIX4 is not set
CONFIG_I2C_NFORCE2=m
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_PROSAVAGE is not set
# CONFIG_I2C_SAVAGE4 is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
# CONFIG_I2C_VOODOO3 is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
#
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
CONFIG_HWMON_VID=m
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
CONFIG_SENSORS_K8TEMP=y
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_FSCHER is not set
# CONFIG_SENSORS_FSCPOS is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_CORETEMP is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
CONFIG_SENSORS_SMSC47M1=m
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
CONFIG_SENSORS_W83781D=m
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_SENSORS_APPLESMC is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
# CONFIG_FB is not set
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
# CONFIG_VIDEO_SELECT is not set
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
CONFIG_SOUND=y
#
# Advanced Linux Sound Architecture
#
CONFIG_SND=y
CONFIG_SND_TIMER=m
CONFIG_SND_PCM=m
CONFIG_SND_RAWMIDI=m
CONFIG_SND_SEQUENCER=m
CONFIG_SND_SEQ_DUMMY=m
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=m
CONFIG_SND_PCM_OSS=m
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_RTCTIMER=m
CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
#
# Generic devices
#
CONFIG_SND_MPU401_UART=m
CONFIG_SND_AC97_CODEC=m
# CONFIG_SND_DUMMY is not set
CONFIG_SND_VIRMIDI=m
# CONFIG_SND_MTPAV is not set
CONFIG_SND_SERIAL_U16550=m
CONFIG_SND_MPU401=m
#
# PCI devices
#
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALS4000 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CS5530 is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
CONFIG_SND_HDA_INTEL=m
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
CONFIG_SND_INTEL8X0=m
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
CONFIG_SND_AC97_POWER_SAVE=y
#
# USB devices
#
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
#
# System on Chip audio support
#
# CONFIG_SND_SOC is not set
#
# SoC Audio support for SuperH
#
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
CONFIG_AC97_BUS=m
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
#
# USB Input Devices
#
CONFIG_USB_HID=y
# CONFIG_USB_HIDINPUT_POWERBOOK is not set
CONFIG_HID_FF=y
CONFIG_HID_PID=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_PANTHERLORD_FF is not set
# CONFIG_THRUSTMASTER_FF is not set
# CONFIG_ZEROPLUS_FF is not set
CONFIG_USB_HIDDEV=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_SUSPEND=y
# CONFIG_USB_PERSIST is not set
# CONFIG_USB_OTG is not set
#
# USB Host Controller Drivers
#
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_EHCI_SPLIT_ISO=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=m
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
CONFIG_USB_PRINTER=m
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# may also be needed; see USB_STORAGE Help for more information
#
CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
CONFIG_USB_STORAGE_DATAFAB=y
CONFIG_USB_STORAGE_FREECOM=y
CONFIG_USB_STORAGE_DPCM=y
# CONFIG_USB_STORAGE_USBAT is not set
CONFIG_USB_STORAGE_SDDR09=y
CONFIG_USB_STORAGE_SDDR55=y
CONFIG_USB_STORAGE_JUMPSHOT=y
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_KARMA is not set
CONFIG_USB_LIBUSUAL=y
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_MON is not set
#
# USB port drivers
#
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_AUERSWALD is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_PHIDGET is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB DSL modem support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
#
# SPI RTC drivers
#
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=m
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
# CONFIG_VIRTUALIZATION is not set
#
# Userspace I/O
#
# CONFIG_UIO is not set
#
# Firmware Drivers
#
CONFIG_EDD=m
# CONFIG_DELL_RBU is not set
# CONFIG_DCDBAS is not set
CONFIG_DMIID=y
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=m
CONFIG_EXT3_FS_XATTR=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4DEV_FS=m
CONFIG_EXT4DEV_FS_XATTR=y
CONFIG_EXT4DEV_FS_POSIX_ACL=y
# CONFIG_EXT4DEV_FS_SECURITY is not set
CONFIG_JBD=m
# CONFIG_JBD_DEBUG is not set
CONFIG_JBD2=m
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
CONFIG_AUTOFS4_FS=m
# CONFIG_FUSE_FS is not set
CONFIG_GENERIC_ACL=y
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
# CONFIG_ZISOFS is not set
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_RAMFS=y
CONFIG_CONFIGFS_FS=m
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=y
CONFIG_NFS_DIRECTIO=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=m
CONFIG_LOCKD_V4=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=m
CONFIG_SUNRPC_GSS=m
CONFIG_SUNRPC_BIND34=y
CONFIG_RPCSEC_GSS_KRB5=m
CONFIG_RPCSEC_GSS_SPKM3=m
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
CONFIG_NLS_CODEPAGE_949=m
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=y
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Instrumentation Support
#
# CONFIG_PROFILING is not set
# CONFIG_KPROBES is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHEDSTATS=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_FRAME_POINTER is not set
# CONFIG_FORCED_INLINING is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_DEBUG_RODATA is not set
# CONFIG_IOMMU_DEBUG is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_NULL is not set
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_GF128MUL is not set
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
# CONFIG_CRYPTO_SERPENT is not set
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_AES_X86_64=y
CONFIG_CRYPTO_CAST5=m
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_CRC32C=m
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_HW is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
^ permalink raw reply
* Re: 2.6.23-rc8-mm2 BUG: register_netdevice() issue as (ab)used by ISDN
From: Andreas Mohr @ 2007-10-07 13:17 UTC (permalink / raw)
To: Jeff Garzik; +Cc: Andreas Mohr, isdn4linux, netdev, akpm
In-Reply-To: <4708D00D.8030307@garzik.org>
On Sun, Oct 07, 2007 at 08:24:45AM -0400, Jeff Garzik wrote:
> It definitely looks like ISDN is somehow to blame. Any chance you could
> try git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.24.git ?
I'm afraid I won't make it, since this server is not at my home
location, is a ""production"" server and takes only exactly 200 minutes
for a kernel build (K6-3/150).
I thus decided to now try plain 2.6.23-rc8 whether it's "corrupted", too.
> That would help narrow down the problem to a very-large set of
> networking changes pending for 2.6.24.
...only if I have a known-working very recent version, which is exactly
the problem now.
Andreas Mohr
^ permalink raw reply
* Re: [NET] IPv6 oops bisected
From: Jeff Garzik @ 2007-10-07 13:33 UTC (permalink / raw)
To: netdev
Cc: Herbert Xu, Linux Kernel Mailing List, Andrew Morton, den,
David Miller
In-Reply-To: <4708D677.1030601@garzik.org>
Jeff Garzik wrote:
> The commit
>
> commit 5f5dace1ce001b24fb8286e09ffd3c4d2b547e09
> Author: Denis V. Lunev <den@openvz.org>
> Date: Thu Sep 27 12:41:26 2007 -0700
>
> [NET]: Various dst_ifdown routines to catch refcounting bugs
>
> causes a 100% reproducible oops in net-2.6.24.git, in ip6_route_add().
>
> Platform: x86-64 Fedora 7
>
> Config and lspci attached.
And indeed, reverting this commit with 'patch -R' makes things work again.
Jeff
^ permalink raw reply
* Re: [NET] IPv6 oops bisected
From: Denis V. Lunev @ 2007-10-07 13:49 UTC (permalink / raw)
To: Jeff Garzik
Cc: netdev, Herbert Xu, Linux Kernel Mailing List, Andrew Morton, den,
David Miller
In-Reply-To: <4708E016.9020300@garzik.org>
Jeff Garzik wrote:
> Jeff Garzik wrote:
>> The commit
>>
>> commit 5f5dace1ce001b24fb8286e09ffd3c4d2b547e09
>> Author: Denis V. Lunev <den@openvz.org>
>> Date: Thu Sep 27 12:41:26 2007 -0700
>>
>> [NET]: Various dst_ifdown routines to catch refcounting bugs
>>
>> causes a 100% reproducible oops in net-2.6.24.git, in ip6_route_add().
>>
>> Platform: x86-64 Fedora 7
>>
>> Config and lspci attached.
>
> And indeed, reverting this commit with 'patch -R' makes things work again.
>
> Jeff
Can you me command to execute to reproduce the problem? and oops if
possible.
Regards,
Den
^ permalink raw reply
* Re: [PATCH 3/5] forcedeth: process TX completions using NAPI
From: Jeff Garzik @ 2007-10-07 14:39 UTC (permalink / raw)
To: netdev, Ayaz Abdulla; +Cc: LKML, Andrew Morton, Yinghai Lu, Ingo Molnar
In-Reply-To: <20071006151438.GC17488@havoc.gtf.org>
[-- Attachment #1: Type: text/plain, Size: 499 bytes --]
Jeff Garzik wrote:
> commit 57cbfacc00d69be2ba02b65d1021442273b76263
> Author: Jeff Garzik <jeff@garzik.org>
> Date: Fri Oct 5 23:25:56 2007 -0400
>
> [netdrvr] forcedeth: process TX completions using NAPI
>
> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
>
> drivers/net/forcedeth.c | 143 +++++++++++++++++++++++++++---------------------
> 1 file changed, 83 insertions(+), 60 deletions(-)
The attached patch fixes an obvious bug. Once applied, TX NAPI actually
works :)
[-- Attachment #2: patch.fe3 --]
[-- Type: text/plain, Size: 530 bytes --]
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 1c236e6..e25c05e 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -3059,7 +3059,7 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
static int nv_napi_tx_poll(struct napi_struct *napi, int budget)
{
- struct fe_priv *np = container_of(napi, struct fe_priv, napi);
+ struct fe_priv *np = container_of(napi, struct fe_priv, tx_napi);
struct net_device *dev = np->dev;
u8 __iomem *base = get_hwbase(dev);
unsigned long flags;
^ permalink raw reply related
* Re: [PATCH 6/n] forcedeth: protect slow path with mutex
From: Jeff Garzik @ 2007-10-07 14:40 UTC (permalink / raw)
To: netdev, Ayaz Abdulla; +Cc: LKML, Andrew Morton
In-Reply-To: <20071007112347.GA23577@havoc.gtf.org>
[-- Attachment #1: Type: text/plain, Size: 919 bytes --]
Jeff Garzik wrote:
> commit abca163a14b28c234df9bf38034bc967ff81c3aa
> Author: Jeff Garzik <jeff@garzik.org>
> Date: Sun Oct 7 07:22:14 2007 -0400
>
> [netdrvr] forcedeth: wrap slow path hw manipulation inside hw_mutex
>
> * This makes sure everybody who wants to start/stop the RX and TX engines
> first acquires this mutex.
>
> * tx_timeout code was deleted, replaced by scheduling reset_task.
>
> * linkchange moved to a workqueue (always inside hw_mutex)
>
> * simplified irq handling a bit
>
> * make sure to disable workqueues before NAPI
>
> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
>
> drivers/net/forcedeth.c | 272 ++++++++++++++++++++++++++++++------------------
> 1 file changed, 175 insertions(+), 97 deletions(-)
You will need the attached patch to even build (oops).
Also, testing shows there is a mutex deadlock somewhere.
[-- Attachment #2: patch.fe6 --]
[-- Type: text/plain, Size: 603 bytes --]
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index d1c1efa..91926b1 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -2929,6 +2929,7 @@ static void nv_linkchange_task(struct work_struct *work)
static void nv_link_irq(struct net_device *dev)
{
+ struct fe_priv *np = netdev_priv(dev);
u8 __iomem *base = get_hwbase(dev);
u32 miistat;
@@ -4378,6 +4379,7 @@ static int nv_ethtool_begin (struct net_device *dev)
struct fe_priv *np = get_nvpriv(dev);
mutex_lock(&np->hw_mutex);
+ return 0;
}
static void nv_ethtool_complete (struct net_device *dev)
^ permalink raw reply related
* Re: [PATCH 0/5] forcedeth: several proposed updates for testing
From: Jeff Garzik @ 2007-10-07 14:47 UTC (permalink / raw)
To: netdev, Ayaz Abdulla; +Cc: LKML, Andrew Morton, Yinghai Lu, Ingo Molnar
In-Reply-To: <20071006151250.GA17020@havoc.gtf.org>
Jeff Garzik wrote:
> The 'fe-lock' branch of
> git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/netdev-2.6.git fe-lock
>
> contains the following changes that I would like to get tested:
>
> [netdrvr] forcedeth: make NAPI unconditional
> [netdrvr] forcedeth: interrupt handling cleanup
> [netdrvr] forcedeth: process TX completions using NAPI
> [netdrvr] forcedeth: internal simplification and cleanups
> [netdrvr] forcedeth: timer overhaul
OK, I've successfully tested patches 1-5 on an AMD64 system with
00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3)
A trivial s/napi/tx_napi/ fix must be applied to patch #3 (sent in
separate email). Once that is done, the patchset works flawlessly here,
passing simple RX, TX, RX+TX TCP stress tests.
I never ran into any TX problems, of the type hinted at by the "Known
bugs" section at the top of forcedeth.c. Either (a) my chip does not
have that bug, (b) my chip needs DEV_NEED_TIMERIRQ for other reasons, or
(c) the issue is not a hardware issue but a driver bug that is now fixed.
I'm going to hope its (c), <grin> But only testing will tell.
Jeff
P.S. Depending on when this gets fixed, you might have to revert
net-2.6.24.git commit 5f5dace1ce001b24fb8286e09ffd3c4d2b547e09 ("[NET]:
Various dst_ifdown routines to catch refcounting bugs").
^ permalink raw reply
* Re: [NET] IPv6 oops bisected
From: Jeff Garzik @ 2007-10-07 14:56 UTC (permalink / raw)
To: Denis V. Lunev
Cc: netdev, Herbert Xu, Linux Kernel Mailing List, Andrew Morton, den,
David Miller
In-Reply-To: <4708E3CF.4000401@gmail.com>
Denis V. Lunev wrote:
> Jeff Garzik wrote:
>> Jeff Garzik wrote:
>>> The commit
>>>
>>> commit 5f5dace1ce001b24fb8286e09ffd3c4d2b547e09
>>> Author: Denis V. Lunev <den@openvz.org>
>>> Date: Thu Sep 27 12:41:26 2007 -0700
>>>
>>> [NET]: Various dst_ifdown routines to catch refcounting bugs
>>>
>>> causes a 100% reproducible oops in net-2.6.24.git, in ip6_route_add().
>>>
>>> Platform: x86-64 Fedora 7
>>>
>>> Config and lspci attached.
>> And indeed, reverting this commit with 'patch -R' makes things work again.
>>
>> Jeff
>
> Can you me command to execute to reproduce the problem? and oops if
> possible.
The command is Fedora 7 initscripts...
(typing in by hand)
/etc/sysconfig/network-scripts/network-functions-ipv6: line 246: 1760 Killed
LC_ALL=C /sbin/ip $options
NULL pointer dereference at 0x000003f8
backtrace:
:ipv6:ip6_route_add+0x1b1/0x543
rtnetlink_rcv_msg
inet6_rtm_newroute
netlink_run_queue
rtnetlink_rcv
netlink_data_ready
netlink_sendskb
netlink_sendmsg
sock_send_msg
mntput_no_expire
autoremove_wake_function
find_lock_page
zone_statistics
get_page_from_freelist
__alloc_pages
move_addr_to_kernel
verify_iovec
sys_sendmsg
^ permalink raw reply
* Re: [RFC][PATCH 1/2] TCP: fix lost retransmit detection
From: Ilpo Järvinen @ 2007-10-07 15:11 UTC (permalink / raw)
To: takano; +Cc: Netdev, y-kodama
In-Reply-To: <20071006.231714.41173786.davem@davemloft.net>
...Dropped DaveM from cc, I guess he knows the things I describe below
already... :-)
On Sat, 6 Oct 2007, David Miller wrote:
> From: TAKANO Ryousei <takano@axe-inc.co.jp>
> Date: Sun, 07 Oct 2007 14:51:00 +0900 (JST)
>
> > BTW, what is difference among netdev-2.6,
netdev-2.6 is for network device drivers (stuff under drivers/net)
> net-2.6 (net-2.6.24), and
> > tcp-2.6? I am not familiar with linux kernel development process.
>
> net-2.6.24 tree is current new development
>
> net-2.6 tree is only bug fixes
>
> tcp-2.6 is an old abandonded tree that holds lots of old
> TCP work, most of which is merged already, but one part
> (my RB-Tree SACK patches) are not integrated yet.
In addition, when Linus releases a new kernel (2.6.23), the net-2.6.24
becomes net-2.6 (the old one ceases to exist). At some point of 2.6.24-rc
series, net-2.6.25 gets opened by DaveM, usually it's not available right
after closure of 2.6.24 merge window. ...Then again, the trees are
again rotated when a next official release is made...
--
i.
^ permalink raw reply
* Re: [PATCH][TG3]Some cleanups
From: jamal @ 2007-10-07 15:12 UTC (permalink / raw)
To: Michael Chan; +Cc: Matt Carlson, netdev
In-Reply-To: <1191417527.4357.25.camel@localhost>
[-- Attachment #1: Type: text/plain, Size: 556 bytes --]
On Wed, 2007-03-10 at 09:18 -0400, jamal wrote:
> On Tue, 2007-02-10 at 16:33 -0700, Michael Chan wrote:
>
> > Seems ok to me. I think we should make it more clear that we're
> > skipping over the VLAN tag:
> >
> > (struct tg3_tx_cbdata *)&((__skb)->cb[sizeof(struct vlan_skb_tx_cookie)])
> >
>
> Will do - thanks Michael.
Ok, attached patch against net-2.6.24 from this morning. I am setting up
some equipment for testing as i type this - so i will test for any
regressions. If you dont hear from me on the subject then all went ok.
cheers,
jamal
[-- Attachment #2: oct7-tg3-p1 --]
[-- Type: text/plain, Size: 13573 bytes --]
[TG3] Some cleanups
Make the xmit path code better functionally organized and more readable.
Matt Carlson contributed the moving of the VLAN formatting into
XXXX_prep_frame() portion and Michael Chan eyeballed the patch and
made it better.
Signed-off-by: Jamal Hadi Salim <hadi@cyberus.ca>
---
commit 190674ff1fe0b7bddf038c2bfddf45b9c6418e2a
tree d6f03d10d94a39ad22fd590b30c6d50c81f3eb5c
parent 0a14acec89454d350c1bd141b3309df421433f3c
author Jamal Hadi Salim <hadi@cyberus.ca> Sun, 07 Oct 2007 08:10:32 -0400
committer Jamal Hadi Salim <hadi@cyberus.ca> Sun, 07 Oct 2007 08:10:32 -0400
drivers/net/tg3.c | 281 ++++++++++++++++++++++++++++++++---------------------
1 files changed, 172 insertions(+), 109 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d4ac6e9..ce6f02f 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3910,47 +3910,72 @@ static void tg3_set_txd(struct tg3 *tp, int entry,
txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
}
-/* hard_start_xmit for devices that don't have any bugs and
- * support TG3_FLG2_HW_TSO_2 only.
- */
-static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
+struct tg3_tx_cbdata {
+ u32 base_flags;
+ unsigned int mss;
+};
+/* using cb[8] skips over the VLAN tag:
+ * (struct tg3_tx_cbdata *)&((__skb)->cb[sizeof(struct vlan_skb_tx_cookie)])
+*/
+#define TG3_SKB_CB(__skb) ((struct tg3_tx_cbdata *)&((__skb)->cb[8]))
+#define NETDEV_TX_DROPPED -5
+
+static int tg3_prep_bug_frame(struct sk_buff *skb, struct net_device *dev)
{
+ struct tg3_tx_cbdata *cb = TG3_SKB_CB(skb);
+#if TG3_VLAN_TAG_USED
struct tg3 *tp = netdev_priv(dev);
- dma_addr_t mapping;
- u32 len, entry, base_flags, mss;
+ u32 vlantag = 0;
- len = skb_headlen(skb);
+ if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
+ vlantag = (TXD_FLAG_VLAN | (vlan_tx_tag_get(skb) << 16));
- /* We are running in BH disabled context with netif_tx_lock
- * and TX reclaim runs via tp->napi.poll inside of a software
- * interrupt. Furthermore, IRQ processing runs lockless so we have
- * no IRQ context deadlocks to worry about either. Rejoice!
- */
- if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
- if (!netif_queue_stopped(dev)) {
- netif_stop_queue(dev);
+ cb->base_flags = vlantag;
+#endif
- /* This is a hard error, log it. */
- printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
- "queue awake!\n", dev->name);
+ cb->mss = skb_shinfo(skb)->gso_size;
+ if (cb->mss != 0) {
+ if (skb_header_cloned(skb) &&
+ pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
+ dev_kfree_skb(skb);
+ return NETDEV_TX_DROPPED;
}
- return NETDEV_TX_BUSY;
+
+ cb->base_flags |= (TXD_FLAG_CPU_PRE_DMA |
+ TXD_FLAG_CPU_POST_DMA);
}
- entry = tp->tx_prod;
- base_flags = 0;
- mss = 0;
- if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+ if (skb->ip_summed == CHECKSUM_PARTIAL)
+ cb->base_flags |= TXD_FLAG_TCPUDP_CSUM;
+
+ return NETDEV_TX_OK;
+}
+
+static int tg3_prep_frame(struct sk_buff *skb, struct net_device *dev)
+{
+ struct tg3_tx_cbdata *cb = TG3_SKB_CB(skb);
+#if TG3_VLAN_TAG_USED
+ struct tg3 *tp = netdev_priv(dev);
+ u32 vlantag = 0;
+
+ if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
+ vlantag = (TXD_FLAG_VLAN | (vlan_tx_tag_get(skb) << 16));
+
+ cb->base_flags = vlantag;
+#endif
+
+ cb->mss = skb_shinfo(skb)->gso_size;
+ if (cb->mss != 0) {
int tcp_opt_len, ip_tcp_len;
if (skb_header_cloned(skb) &&
pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
dev_kfree_skb(skb);
- goto out_unlock;
+ return NETDEV_TX_DROPPED;
}
if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
- mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
+ cb->mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
else {
struct iphdr *iph = ip_hdr(skb);
@@ -3958,32 +3983,58 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
iph->check = 0;
- iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
- mss |= (ip_tcp_len + tcp_opt_len) << 9;
+ iph->tot_len = htons(cb->mss + ip_tcp_len
+ + tcp_opt_len);
+ cb->mss |= (ip_tcp_len + tcp_opt_len) << 9;
}
- base_flags |= (TXD_FLAG_CPU_PRE_DMA |
+ cb->base_flags |= (TXD_FLAG_CPU_PRE_DMA |
TXD_FLAG_CPU_POST_DMA);
tcp_hdr(skb)->check = 0;
}
else if (skb->ip_summed == CHECKSUM_PARTIAL)
- base_flags |= TXD_FLAG_TCPUDP_CSUM;
-#if TG3_VLAN_TAG_USED
- if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
- base_flags |= (TXD_FLAG_VLAN |
- (vlan_tx_tag_get(skb) << 16));
-#endif
+ cb->base_flags |= TXD_FLAG_TCPUDP_CSUM;
+
+ return NETDEV_TX_OK;
+}
+
+void tg3_complete_xmit(struct net_device *dev)
+{
+ struct tg3 *tp = netdev_priv(dev);
+ u32 entry = tp->tx_prod;
+
+ /* Packets are ready, update Tx producer idx local and on card. */
+ tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
+
+ if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
+ netif_stop_queue(dev);
+ if (tg3_tx_avail(tp) >= TG3_TX_WAKEUP_THRESH(tp))
+ netif_wake_queue(dev);
+ }
+
+ mmiowb();
+ dev->trans_start = jiffies;
+}
+static int tg3_enqueue(struct sk_buff *skb, struct net_device *dev)
+{
+ struct tg3 *tp = netdev_priv(dev);
+ dma_addr_t mapping;
+ u32 len, entry;
+ struct tg3_tx_cbdata *cb = TG3_SKB_CB(skb);
+
+ entry = tp->tx_prod;
+ len = skb_headlen(skb);
/* Queue skb data, a.k.a. the main skb fragment. */
mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
tp->tx_buffers[entry].skb = skb;
pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
- tg3_set_txd(tp, entry, mapping, len, base_flags,
- (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
+ tg3_set_txd(tp, entry, mapping, len, cb->base_flags,
+ (skb_shinfo(skb)->nr_frags == 0) | (cb->mss << 1));
entry = NEXT_TX(entry);
@@ -4005,28 +4056,51 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
tg3_set_txd(tp, entry, mapping, len,
- base_flags, (i == last) | (mss << 1));
+ cb->base_flags,
+ (i == last) | (cb->mss << 1));
entry = NEXT_TX(entry);
}
}
- /* Packets are ready, update Tx producer idx local and on card. */
- tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
-
tp->tx_prod = entry;
- if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
- netif_stop_queue(dev);
- if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
- netif_wake_queue(tp->dev);
- }
+ return NETDEV_TX_OK;
+}
+
+/* hard_start_xmit for devices that don't have any bugs and
+ * support TG3_FLG2_HW_TSO_2 only.
+ */
+static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct tg3 *tp = netdev_priv(dev);
+ int ret = tg3_prep_frame(skb, dev);
+ /* XXX: original code did mmiowb(); on failure,
+ * I dont think thats necessary
+ */
+ if (unlikely(ret != NETDEV_TX_OK))
+ return NETDEV_TX_OK;
-out_unlock:
- mmiowb();
+ /* We are running in BH disabled context with netif_tx_lock
+ * and TX reclaim runs via tp->poll inside of a software
+ * interrupt. Furthermore, IRQ processing runs lockless so we have
+ * no IRQ context deadlocks to worry about either. Rejoice!
+ */
+ if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
+ if (!netif_queue_stopped(dev)) {
+ netif_stop_queue(dev);
- dev->trans_start = jiffies;
+ /* This is a hard error, log it. */
+ printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
+ "queue awake!\n", dev->name);
+ }
+ return NETDEV_TX_BUSY;
+ }
- return NETDEV_TX_OK;
+ ret = tg3_enqueue(skb, dev);
+ if (ret == NETDEV_TX_OK)
+ tg3_complete_xmit(dev);
+
+ return ret;
}
static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
@@ -4067,46 +4141,19 @@ tg3_tso_bug_end:
/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
* support TG3_FLG2_HW_TSO_1 or firmware TSO only.
*/
-static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
+static int tg3_enqueue_buggy(struct sk_buff *skb, struct net_device *dev)
{
struct tg3 *tp = netdev_priv(dev);
dma_addr_t mapping;
- u32 len, entry, base_flags, mss;
+ u32 len, entry;
int would_hit_hwbug;
+ struct tg3_tx_cbdata *cb = TG3_SKB_CB(skb);
- len = skb_headlen(skb);
- /* We are running in BH disabled context with netif_tx_lock
- * and TX reclaim runs via tp->napi.poll inside of a software
- * interrupt. Furthermore, IRQ processing runs lockless so we have
- * no IRQ context deadlocks to worry about either. Rejoice!
- */
- if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
- if (!netif_queue_stopped(dev)) {
- netif_stop_queue(dev);
-
- /* This is a hard error, log it. */
- printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
- "queue awake!\n", dev->name);
- }
- return NETDEV_TX_BUSY;
- }
-
- entry = tp->tx_prod;
- base_flags = 0;
- if (skb->ip_summed == CHECKSUM_PARTIAL)
- base_flags |= TXD_FLAG_TCPUDP_CSUM;
- mss = 0;
- if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+ if (cb->mss != 0) {
struct iphdr *iph;
int tcp_opt_len, ip_tcp_len, hdr_len;
- if (skb_header_cloned(skb) &&
- pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
- dev_kfree_skb(skb);
- goto out_unlock;
- }
-
tcp_opt_len = tcp_optlen(skb);
ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
@@ -4115,15 +4162,13 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
(tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
return (tg3_tso_bug(tp, skb));
- base_flags |= (TXD_FLAG_CPU_PRE_DMA |
- TXD_FLAG_CPU_POST_DMA);
iph = ip_hdr(skb);
iph->check = 0;
- iph->tot_len = htons(mss + hdr_len);
+ iph->tot_len = htons(cb->mss + hdr_len);
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
tcp_hdr(skb)->check = 0;
- base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
+ cb->base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
} else
tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
iph->daddr, 0,
@@ -4136,22 +4181,19 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
- mss |= (tsflags << 11);
+ cb->mss |= (tsflags << 11);
}
} else {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
- base_flags |= tsflags << 12;
+ cb->base_flags |= tsflags << 12;
}
}
}
-#if TG3_VLAN_TAG_USED
- if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
- base_flags |= (TXD_FLAG_VLAN |
- (vlan_tx_tag_get(skb) << 16));
-#endif
+ len = skb_headlen(skb);
+ entry = tp->tx_prod;
/* Queue skb data, a.k.a. the main skb fragment. */
mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
@@ -4164,8 +4206,8 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
if (tg3_4g_overflow_test(mapping, len))
would_hit_hwbug = 1;
- tg3_set_txd(tp, entry, mapping, len, base_flags,
- (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
+ tg3_set_txd(tp, entry, mapping, len, cb->base_flags,
+ (skb_shinfo(skb)->nr_frags == 0) | (cb->mss << 1));
entry = NEXT_TX(entry);
@@ -4194,10 +4236,11 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
tg3_set_txd(tp, entry, mapping, len,
- base_flags, (i == last)|(mss << 1));
+ cb->base_flags,
+ (i == last)|(cb->mss << 1));
else
tg3_set_txd(tp, entry, mapping, len,
- base_flags, (i == last));
+ cb->base_flags, (i == last));
entry = NEXT_TX(entry);
}
@@ -4214,28 +4257,48 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
* failure, silently drop this packet.
*/
if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
- &start, base_flags, mss))
- goto out_unlock;
+ &start, cb->base_flags,
+ cb->mss)) {
+ mmiowb();
+ return NETDEV_TX_OK;
+ }
entry = start;
}
- /* Packets are ready, update Tx producer idx local and on card. */
- tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
-
tp->tx_prod = entry;
- if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
- netif_stop_queue(dev);
- if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
- netif_wake_queue(tp->dev);
- }
+ return NETDEV_TX_OK;
+}
+
+static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
+{
+ struct tg3 *tp = netdev_priv(dev);
+ int ret = tg3_prep_bug_frame(skb, dev);
-out_unlock:
- mmiowb();
+ if (unlikely(ret != NETDEV_TX_OK))
+ return NETDEV_TX_OK;
- dev->trans_start = jiffies;
+ /* We are running in BH disabled context with netif_tx_lock
+ * and TX reclaim runs via tp->poll inside of a software
+ * interrupt. Furthermore, IRQ processing runs lockless so we have
+ * no IRQ context deadlocks to worry about either. Rejoice!
+ */
+ if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
+ if (!netif_queue_stopped(dev)) {
+ netif_stop_queue(dev);
- return NETDEV_TX_OK;
+ /* This is a hard error, log it. */
+ printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
+ "queue awake!\n", dev->name);
+ }
+ return NETDEV_TX_BUSY;
+ }
+
+ ret = tg3_enqueue_buggy(skb, dev);
+ if (ret == NETDEV_TX_OK)
+ tg3_complete_xmit(dev);
+
+ return ret;
}
static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
^ permalink raw reply related
* [PATCH][E1000E] some cleanups
From: jamal @ 2007-10-07 16:15 UTC (permalink / raw)
To: Kok, Auke; +Cc: netdev
In-Reply-To: <1191417498.4357.23.camel@localhost>
[-- Attachment #1: Type: text/plain, Size: 1108 bytes --]
Ok, here you go; the explanation is below. This is from net-2.6.24 of
early this AM. I saw a patch you posted that is derived from Krishna;
although it hasnt showed up in the tree - i have considered those
changes and this patch adds a little more optimization in case of
errors.
I will send you a patch to kill LLTX the sooner this shows up somewhere.
cheers,
jamal
On Wed, 2007-03-10 at 09:18 -0400, jamal wrote:
> The cleanup is to break up the code so it is functionally more readable
> from a perspective of the 4 distinct parts in ->hard_start_xmit():
>
> a) packet formatting (example: vlan, mss, descriptor counting, etc.)
> b) chip-specific formatting
> c) enqueueing the packet on a DMA ring
> d) IO operations to complete packet transmit, tell DMA engine to chew
> on, tx completion interrupts, set last tx time, etc.
>
> Each of those steps sitting in different functions accumulates state
> that is used in the next steps. cb stores this state because it a
> scratchpad the driver owns. You could create some other structure and
> pass it around the iteration, but why waste more bytes.
[-- Attachment #2: e1000e-p1 --]
[-- Type: text/x-patch, Size: 6356 bytes --]
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index 4a21d7d..26d35bb 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -3417,51 +3417,60 @@ static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
return __e1000_maybe_stop_tx(netdev, size);
}
+/* This structure cannot be larger than 40B given it uses skb->cb[8] */
+struct e1000_tx_cbdata {
+ int count;
+ unsigned int max_per_txd;
+ unsigned int nr_frags;
+ unsigned int mss;
+ unsigned int tx_flags;
+};
+
+/* we avoid cb[0] because it is used by VLAN cookie
+ * struct vlan_skb_tx_cookie
+*/
+#define E1000_SKB_CB(__skb) ((struct e1000_tx_cbdata *)&((__skb)->cb[8]))
+#define NETDEV_TX_DROPPED -5
#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
-static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
+
+static int e1000_prep_frame(struct sk_buff *skb, struct net_device *netdev)
{
struct e1000_adapter *adapter = netdev_priv(netdev);
- struct e1000_ring *tx_ring = adapter->tx_ring;
- unsigned int first;
- unsigned int max_per_txd = E1000_MAX_PER_TXD;
- unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
- unsigned int tx_flags = 0;
unsigned int len = skb->len;
- unsigned long irq_flags;
- unsigned int nr_frags = 0;
- unsigned int mss = 0;
- int count = 0;
- int tso;
+ unsigned int max_txd_pwr;
+ struct e1000_tx_cbdata *cb;
unsigned int f;
- len -= skb->data_len;
-
- if (test_bit(__E1000_DOWN, &adapter->state)) {
- dev_kfree_skb_any(skb);
- return NETDEV_TX_OK;
- }
if (skb->len <= 0) {
dev_kfree_skb_any(skb);
- return NETDEV_TX_OK;
+ return NETDEV_TX_DROPPED;
}
- mss = skb_shinfo(skb)->gso_size;
+ max_txd_pwr = E1000_MAX_TXD_PWR;
+ cb = E1000_SKB_CB(skb);
+ cb->nr_frags = 0;
+ cb->mss = 0;
+ cb->count = 0;
+ cb->max_per_txd = E1000_MAX_PER_TXD;
+
+ len -= skb->data_len;
+ cb->mss = skb_shinfo(skb)->gso_size;
/* The controller does a simple calculation to
* make sure there is enough room in the FIFO before
* initiating the DMA for each buffer. The calc is:
* 4 = ceil(buffer len/mss). To make sure we don't
* overrun the FIFO, adjust the max buffer len if mss
* drops. */
- if (mss) {
+ if (cb->mss) {
u8 hdr_len;
- max_per_txd = min(mss << 2, max_per_txd);
- max_txd_pwr = fls(max_per_txd) - 1;
+ cb->max_per_txd = min(cb->mss << 2, cb->max_per_txd);
+ max_txd_pwr = fls(cb->max_per_txd) - 1;
/* TSO Workaround for 82571/2/3 Controllers -- if skb->data
* points to just header, pull a few bytes of payload from
* frags into skb->data */
hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
- if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
+ if (skb->data_len && (hdr_len == len )) {
unsigned int pull_size;
pull_size = min((unsigned int)4, skb->data_len);
@@ -3469,43 +3478,66 @@ static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
ndev_err(netdev,
"__pskb_pull_tail failed.\n");
dev_kfree_skb_any(skb);
- return NETDEV_TX_OK;
+ return NETDEV_TX_DROPPED;
}
len = skb->len - skb->data_len;
}
}
/* reserve a descriptor for the offload context */
- if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
- count++;
- count++;
+ if ((cb->mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
+ cb->count++;
+ cb->count++;
- count += TXD_USE_COUNT(len, max_txd_pwr);
+ cb->count += TXD_USE_COUNT(len, max_txd_pwr);
- nr_frags = skb_shinfo(skb)->nr_frags;
- for (f = 0; f < nr_frags; f++)
- count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
+ cb->nr_frags = skb_shinfo(skb)->nr_frags;
+ for (f = 0; f < cb->nr_frags; f++)
+ cb->count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
max_txd_pwr);
if (adapter->hw.mac.tx_pkt_filtering)
e1000_transfer_dhcp_info(adapter, skb);
+ if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
+ cb->tx_flags |= E1000_TX_FLAGS_VLAN;
+ cb->tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
+ }
+
+ return NETDEV_TX_OK;
+}
+
+static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
+{
+ int ret = NETDEV_TX_OK;
+ struct e1000_adapter *adapter = netdev_priv(netdev);
+ struct e1000_ring *tx_ring = adapter->tx_ring;
+ unsigned int first;
+ unsigned long irq_flags;
+ int tso;
+ struct e1000_tx_cbdata *cb;
+
+ ret = e1000_prep_frame(skb, netdev);
+ if (unlikely(ret != NETDEV_TX_OK))
+ return NETDEV_TX_OK;
+
+ if (test_bit(__E1000_DOWN, &adapter->state)) {
+ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
if (!spin_trylock_irqsave(&adapter->tx_queue_lock, irq_flags))
/* Collision - tell upper layer to requeue */
return NETDEV_TX_LOCKED;
+ cb = E1000_SKB_CB(skb);
/* need: count + 2 desc gap to keep tail from touching
* head, otherwise try next time */
- if (e1000_maybe_stop_tx(netdev, count + 2)) {
+ if (e1000_maybe_stop_tx(netdev, cb->count + 2)) {
spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
return NETDEV_TX_BUSY;
}
- if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
- tx_flags |= E1000_TX_FLAGS_VLAN;
- tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
- }
-
first = tx_ring->next_to_use;
tso = e1000_tso(adapter, skb);
@@ -3516,25 +3548,25 @@ static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
}
if (tso)
- tx_flags |= E1000_TX_FLAGS_TSO;
+ cb->tx_flags |= E1000_TX_FLAGS_TSO;
else if (e1000_tx_csum(adapter, skb))
- tx_flags |= E1000_TX_FLAGS_CSUM;
+ cb->tx_flags |= E1000_TX_FLAGS_CSUM;
/* Old method was to assume IPv4 packet by default if TSO was enabled.
* 82571 hardware supports TSO capabilities for IPv6 as well...
* no longer assume, we must. */
if (skb->protocol == htons(ETH_P_IP))
- tx_flags |= E1000_TX_FLAGS_IPV4;
+ cb->tx_flags |= E1000_TX_FLAGS_IPV4;
- count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
- if (count < 0) {
+ cb->count = e1000_tx_map(adapter, skb, first, cb->max_per_txd, cb->nr_frags, cb->mss);
+ if (cb->count < 0) {
/* handle pci_map_single() error in e1000_tx_map */
dev_kfree_skb_any(skb);
spin_unlock_irqrestore(&adapter->tx_queue_lock, irq_flags);
- return NETDEV_TX_OK;
+ return NETDEV_TX_BUSY;
}
- e1000_tx_queue(adapter, tx_flags, count);
+ e1000_tx_queue(adapter, cb->tx_flags, cb->count);
netdev->trans_start = jiffies;
^ permalink raw reply related
* [BNX2X][PATCH 0/8] New driver for Broadcom 10Gb Ethernet, take two.
From: Eliezer Tamir @ 2007-10-07 16:20 UTC (permalink / raw)
To: davem@davemloft.net, jeff@garzik.org, netdev@vger.kernel.org,
Michael Chan, eilong
This is an initial version of the BNX2X, the Linux driver for the
BCM5771X 10Gb Ethernet controller family.
Although the chip is very different from the 5706-8 family we based the
driver code on the BNX2 driver.
Since the hardware is supposed to be generally available soon I have
posted an initial version and after hearing all the comments I am
reposting with changes to address them.
Some planned feature are still under development, but we want to get
whatever we have out now so people can start using the HW.
Main changes from first version.
* Fixed most issues raised by Michael Buesch. (Thanks Michael!)
* Some slow path bug fixes.
* Yitchak Gertner re-grouped the code in a more logical manner.
* A lot of work was done to get the generated code to comply with coding
style requirements.
Known issues/TODO.
* Move slowpath event handling from tasklet to workqueue context. This
will allow replacing the busy waits in the link management code with sleeps.
Please consider applying to 2.6.24
Thanks
Eliezer
^ permalink raw reply
* [BNX2X][PATCH 1/8] add bnx2x to Kconfig and Makefile
From: Eliezer Tamir @ 2007-10-07 16:21 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
Add bnx2x to Kconfig and Makefile
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com>
---
drivers/net/Kconfig | 9 +++++++++
drivers/net/Makefile | 1 +
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 467532c..fbb69ac 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2630,6 +2630,15 @@ config TEHUTI
help
Tehuti Networks 10G Ethernet NIC
+config BNX2X
+ tristate "Broadcom NetXtremeII XGb support"
+ depends on PCI
+ help
+ This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
+
+ To compile this driver as a module, choose M here: the module
+ will be called bnx2x. This is recommended.
+
endif # NETDEV_10000
source "drivers/net/tokenring/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6220c50..51f3ea7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_STNIC) += stnic.o 8390.o
obj-$(CONFIG_FEALNX) += fealnx.o
obj-$(CONFIG_TIGON3) += tg3.o
obj-$(CONFIG_BNX2) += bnx2.o
+obj-$(CONFIG_BNX2X) += bnx2x.o
spidernet-y += spider_net.o spider_net_ethtool.o
obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
--
1.4.2
^ permalink raw reply related
* [BNX2X][PATCH 2/8] bnx2x.c
From: Eliezer Tamir @ 2007-10-07 16:22 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x.c - main .c file.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x.c | 8873
+++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 8873 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c
new file mode 100644
index 0000000..9317fdb
--- /dev/null
+++ b/drivers/net/bnx2x.c
@@ -0,0 +1,8873 @@
+/* bnx2x.c: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Written by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
+ * Based on code from Michael Chan's bnx2 driver
+ * UDP CSUM errata workaround by Arik Gendelman
+ * Slowpath rework by Vladislav Zolotarov
+ * Statistics and Link managment by Yitchak Gertner
+ *
+ */
+
+/* define this to make the driver freeze on error
+ * -for now this is the defualt.
+ */
+#define BNX2X_STOP_ON_ERROR
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/device.h> /* for dev_info() */
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#ifdef NETIF_F_HW_VLAN_TX
+ #include <linux/if_vlan.h>
+ #define BCM_VLAN 1
+#endif
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/checksum.h>
+#include <linux/workqueue.h>
+#include <linux/crc32.h>
+#include <linux/prefetch.h>
+#include <linux/zlib.h>
+
+#include "bnx2x_hsi.h"
+#include "bnx2x.h"
+#include "bnx2x_init.h"
+#include "bnx2x_self_test.h"
+
+
+#define DRV_MODULE_VERSION "0.40.10"
+#define DRV_MODULE_RELDATE "$DateTime: 2007/09/24 08:56:36 $"
+#define BNX2X_BC_VER 0x040004
+
+/* Time in jiffies before concluding the transmitter is hung. */
+#define TX_TIMEOUT (5*HZ)
+
+static const char version[] __devinitdata =
+ "Broadcom NetXtreme II 577xx 10Gigabit Ethernet Driver "
+ DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
+
+MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>");
+MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_MODULE_VERSION);
+MODULE_INFO(cvs_version, "$Revision: #302 $");
+
+static int use_inta;
+static int poll;
+static int onefunc;
+static int nomcp;
+static int debug;
+module_param(use_inta, int, 0);
+module_param(poll, int, 0);
+module_param(onefunc, int, 0);
+module_param(debug, int, 0);
+MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
+MODULE_PARM_DESC(poll, "use polling (for debug)");
+MODULE_PARM_DESC(onefunc, "enable only first function");
+MODULE_PARM_DESC(nomcp, "ignore managment CPU (Implies onefunc)");
+MODULE_PARM_DESC(debug, "defualt debug msglevel");
+
+enum bnx2x_board_type{
+ BCM57710 = 0,
+};
+
+/* indexed by board_t, above */
+static const struct {
+ char *name;
+} board_info[] __devinitdata = {
+ { "Broadcom NetXtreme II BCM57710 XGb" },
+};
+
+#ifndef PCI_DEVICE_ID_NX2_57710
+#define PCI_DEVICE_ID_NX2_57710 0x164e
+#endif
+
+static const struct pci_device_id bnx2x_pci_tbl[] = {
+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
+ { 0 }
+};
+
+MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+/* does not need locking since it is used only at init */
+static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
+{
+ pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
+ pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
+ pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
+ PCICFG_VENDOR_ID_OFFSET);
+}
+
+#ifdef BNX2X_IND_RD
+static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
+{
+ u32 val;
+
+ pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
+ pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
+ pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
+ PCICFG_VENDOR_ID_OFFSET);
+
+ return val;
+}
+#endif
+
+/* copy command into DMAE command memory */
+static void bnx2x_post_dmae(struct bnx2x *bp, int idx)
+{
+ struct dmae_command *dmae = &bp->dmae;
+ u32 cmd_offset;
+ int i;
+
+ cmd_offset = (DMAE_REGISTERS_CMD_MEM +
+ sizeof(struct dmae_command) * idx);
+ for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
+ REG_WR32(bp, GRCBASE_DMAE, cmd_offset + i*4,
+ *(((u32 *)dmae) + i));
+
+/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
+ idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
+ }
+}
+
+/* DMAE command positions used
+ * Port0 14
+ * Port1 15
+ */
+static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
+ u32 wb_addr, u32 wb_len)
+{
+ struct dmae_command *dmae = &bp->dmae;
+ int port = bp->port;
+ u32 *wb_comp = bnx2x_sp(bp, wb_comp);
+ int timeout = 200;
+
+ memset(dmae, 0, sizeof(struct dmae_command));
+
+ dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
+ dmae->src_addr_lo = U64_LO(dma_addr);
+ dmae->src_addr_hi = U64_HI(dma_addr);
+ dmae->dst_addr_lo = wb_addr >> 2;
+ dmae->dst_addr_hi = 0;
+ dmae->len = wb_len;
+ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+ dmae->comp_val = BNX2X_WB_COMP_VAL;
+
+/*
+ DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
+ DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
+ "dst_addr [%x:%08x (%08x)]\n"
+ DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
+ dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
+ dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, wb_addr,
+ dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
+*/
+/*
+ DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+ bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
+ bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
+*/
+
+ *wb_comp = 0;
+
+ bnx2x_post_dmae(bp, port ? 15 : 14);
+
+ REG_WR32(bp, GRCBASE_DMAE,
+ (bp->port ? DMAE_REGISTERS_GO_C15 :
+ DMAE_REGISTERS_GO_C14), 1);
+ udelay(5);
+ while (*wb_comp != BNX2X_WB_COMP_VAL) {
+/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
+ udelay(5);
+ if (!timeout) {
+ BNX2X_ERR("dmae timeout!\n");
+ break;
+ }
+ timeout--;
+ }
+}
+
+#ifdef BNX2X_DMAE_RD
+static void bnx2x_read_dmae(struct bnx2x *bp, u32 wb_addr, u32 wb_len)
+{
+ struct dmae_command *dmae = &bp->dmae;
+ int port = bp->port;
+ u32 *wb_comp = bnx2x_sp(bp, wb_comp);
+ int timeout = 200;
+
+ memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
+ memset(dmae, 0, sizeof(struct dmae_command));
+
+ dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
+ dmae->src_addr_lo = wb_addr >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
+ dmae->len = wb_len;
+ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+ dmae->comp_val = BNX2X_WB_COMP_VAL;
+
+/*
+ DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
+ DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
+ "dst_addr [%x:%08x (%08x)]\n"
+ DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
+ dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
+ dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, wb_addr,
+ dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
+*/
+
+ *wb_comp = 0;
+
+ bnx2x_post_dmae(bp, port ? 15 : 14);
+
+ REG_WR32(bp, GRCBASE_DMAE,
+ (bp->port ? DMAE_REGISTERS_GO_C15 :
+ DMAE_REGISTERS_GO_C14), 1);
+ udelay(5);
+ while (*wb_comp != BNX2X_WB_COMP_VAL) {
+ udelay(5);
+ if (!timeout) {
+ BNX2X_ERR("dmae timeout!\n");
+ break;
+ }
+ timeout--;
+ }
+/*
+ DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+ bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
+ bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
+*/
+}
+#endif
+
+static void bnx2x_panic_dump(struct bnx2x *bp)
+{
+ int i;
+ u16 j, start, end;
+
+ BNX2X_ERR("begin crash dump -----------------\n");
+
+ for_each_queue(bp, i) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+ struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
+
+ BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
+ " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)"
+ " *rx_cons_sb(%x) rx_comp_prod(%x)"
+ " rx_comp_cons(%x) fp_c_idx(%x) fp_u_idx(%x)"
+ " bd data(%x,%x)\n",
+ i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
+ fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb,
+ fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx,
+ fp->fp_u_idx, hw_prods->packets_prod,
+ hw_prods->bds_prod);
+
+ start = TX_BD(*fp->tx_cons_sb - 10);
+ end = TX_BD(*fp->tx_cons_sb + 245);
+ for (j = start; j < end; j++) {
+ struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
+
+ BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
+ sw_bd->skb, sw_bd->first_bd);
+ }
+
+ start = TX_BD(fp->tx_bd_cons - 10);
+ end = TX_BD(fp->tx_bd_cons + 254);
+ for (j = start; j < end; j++) {
+ u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
+
+ BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
+ j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
+ }
+
+ start = RX_BD(*fp->rx_cons_sb - 10);
+ end = RX_BD(*fp->rx_cons_sb + 503);
+ for (j = start; j < end; j++) {
+ u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
+ struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
+
+ BNX2X_ERR("rx_bd[%x]=[%x:%x:%x:%x] sw_bd=[%p]\n",
+ j, rx_bd[0], rx_bd[1], rx_bd[2], rx_bd[3],
+ sw_bd->skb);
+ }
+
+ start = RX_BD(fp->rx_comp_cons - 10);
+ end = RX_BD(fp->rx_comp_cons + 503);
+ for (j = start; j < end; j++) {
+ u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
+
+ BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
+ j, cqe[0], cqe[1], cqe[2], cqe[3]);
+ }
+ }
+
+ BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_t_idx(%u)"
+ " def_x_idx(%u) def_att_idx(%u) attn_state(%u)"
+ " spq_prod_idx(%u) spq_con_idx(%u)\n",
+ bp->def_c_idx, bp->def_u_idx, bp->def_t_idx, bp->def_x_idx,
+ bp->def_att_idx, bp->attn_state, bp->spq_prod_idx,
+ bp->spq_con_idx);
+
+ bnx2x_idle_chk(bp);
+ bnx2x_mc_assert(bp);
+ BNX2X_ERR("end crash dump -----------------\n");
+
+ bp->stats_state = STATS_STATE_DISABLE;
+ DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
+}
+
+static void bnx2x_enable_int(struct bnx2x *bp)
+{
+ int port = bp->port;
+ u32 addr = port ? HC_REGISTERS_CONFIG_1 : HC_REGISTERS_CONFIG_0;
+ u32 val = REG_RD(bp, GRCBASE_HC, addr);
+ int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
+
+ if (msix) {
+ val &= ~HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0;
+ val |= (HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0 |
+ HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0);
+ } else {
+ val |= (HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0 |
+ HC_CONFIG_0_REGISTERS_INT_LINE_EN_0 |
+ HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0);
+ val &= ~HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0;
+ }
+
+ DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) msi %d\n",
+ val, port, GRCBASE_HC + addr, msix);
+
+ REG_WR(bp, GRCBASE_HC, addr, val);
+}
+
+static void bnx2x_disable_int(struct bnx2x *bp)
+{
+ int port = bp->port;
+ u32 addr = port ? HC_REGISTERS_CONFIG_1 : HC_REGISTERS_CONFIG_0;
+ u32 val = REG_RD(bp, GRCBASE_HC, addr);
+
+ val &= ~(HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0 |
+ HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0 |
+ HC_CONFIG_0_REGISTERS_INT_LINE_EN_0 |
+ HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0);
+
+ DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
+ val, port, GRCBASE_HC + addr);
+
+ REG_WR(bp, GRCBASE_HC, addr, val);
+ if (REG_RD(bp, GRCBASE_HC, addr) != val) {
+ BNX2X_ERR("BUG! proper val not read from IGU!\n");
+ }
+}
+
+static void bnx2x_disable_int_sync(struct bnx2x *bp)
+{
+ int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
+ int i;
+
+ atomic_inc(&bp->intr_sem);
+ bnx2x_disable_int(bp);
+
+ /* Disable SP tasklet */
+ tasklet_disable(&bp->sp_task);
+
+ if (msix) {
+ for_each_queue(bp, i) {
+ synchronize_irq(bp->msix_table[i].vector);
+ }
+ /* one more for the Slow Path IRQ */
+ synchronize_irq(bp->msix_table[i].vector);
+ } else {
+ synchronize_irq(bp->pdev->irq);
+ }
+}
+
+/* fast path */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id,
+ u8 storm, u16 index, u8 op, u8 update)
+{
+ u16 flags;
+ u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8;
+ u32 command;
+
+ flags = ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
+ (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
+ (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
+ (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
+
+ command = (flags << 16) | index;
+
+ REG_WR(bp, BAR_IGU_INTMEM, igu_addr, command);
+}
+
+static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
+{
+ struct host_status_block *fpsb = fp->status_blk;
+ u16 rc = 0;
+
+ if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
+ fp->fp_c_idx = fpsb->c_status_block.status_block_index;
+ rc |= 1;
+ }
+ if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
+ fp->fp_u_idx = fpsb->u_status_block.status_block_index;
+ rc |= 2;
+ }
+ rmb(); /* TBD chack this */
+ return rc;
+}
+
+static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
+{
+ u16 rx_cons_sb = *fp->rx_cons_sb;
+
+ if ((rx_cons_sb & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
+ rx_cons_sb++;
+
+ if ((rx_cons_sb != fp->rx_comp_cons) ||
+ (*fp->tx_cons_sb != fp->tx_pkt_cons))
+ return 1;
+
+ return 0;
+}
+
+static u16 bnx2x_ack_int(struct bnx2x *bp)
+{
+ u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8;
+ u32 result = REG_RD(bp, BAR_IGU_INTMEM, igu_addr);
+
+/* DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", result,
+ BAR_IGU_INTMEM + igu_addr); */
+
+#ifdef IGU_DEBUG
+#warning IGU_DEBUG active
+ if (result == 0) {
+ BNX2X_ERR("read %x from IGU\n", result);
+ REG_WR(bp, GRCBASE_TIMERS, TM_REGISTERS_TIMER_SOFT_RST, 0);
+ }
+#endif
+ return result;
+}
+
+
+/****************************************************************************
+* fast path service functions
+****************************************************************************/
+
+/* free skb in the packet ring at pos idx
+ return idx of last bd freed */
+static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+ u16 idx)
+{
+ struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
+ struct eth_tx_bd *tx_bd;
+ struct sk_buff *skb = tx_buf->skb;
+ u16 bd_idx = tx_buf->first_bd;
+ int nbd;
+
+ DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
+ idx, tx_buf, skb);
+
+ /* unmap first bd */
+ DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
+ tx_bd = &fp->tx_desc_ring[bd_idx];
+ pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
+ BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
+
+ nbd = tx_bd->nbd - 1;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (nbd > (MAX_SKB_FRAGS + 2)) {
+ BNX2X_ERR("bad nbd!\n");
+ bnx2x_panic();
+ }
+#endif
+
+ /* Skip a parse bd and the TSO split header bd
+ since they have no mapping */
+ if (nbd)
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+
+ if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
+ ETH_TX_BD_FLAGS_TCP_CSUM |
+ ETH_TX_BD_FLAGS_SW_LSO)) {
+ if (--nbd)
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+ tx_bd = &fp->tx_desc_ring[bd_idx];
+ /* is this a TSO heder split bd? */
+ if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
+ if (--nbd)
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+ }
+ }
+
+ /* now free frags */
+ while (nbd > 0) {
+
+ DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
+ tx_bd = &fp->tx_desc_ring[bd_idx];
+ pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
+ BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
+ if (--nbd)
+ bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
+ }
+
+ /* release skb */
+ BUG_TRAP(skb);
+ dev_kfree_skb(skb);
+ tx_buf->first_bd = 0;
+ tx_buf->skb = NULL;
+
+ return bd_idx;
+}
+
+static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
+{
+ u16 used;
+ u32 prod;
+ u32 cons;
+
+ /* Tell compiler that prod and cons can change. */
+ barrier();
+ prod = fp->tx_bd_prod;
+ cons = fp->tx_bd_cons;
+
+ used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons +
+ (cons / TX_DESC_CNT) - (prod / TX_DESC_CNT));
+
+ if (prod >= cons) {
+ /* used = prod - cons - prod/size + cons/size */
+ used -= NUM_TX_BD - NUM_TX_RINGS;
+ }
+
+ BUG_TRAP(used <= fp->bp->tx_ring_size);
+ BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);
+
+ return (fp->bp->tx_ring_size - used);
+}
+
+static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
+{
+ struct bnx2x *bp = fp->bp;
+ u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
+ int done = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return;
+ }
+#endif
+
+ hw_cons = *fp->tx_cons_sb;
+ sw_cons = fp->tx_pkt_cons;
+
+ while (sw_cons != hw_cons) {
+ u16 pkt_cons;
+
+ pkt_cons = TX_BD(sw_cons);
+
+ /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
+
+ DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %d\n",
+ hw_cons, sw_cons, pkt_cons);
+
+/* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
+ rmb();
+ prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
+ }
+*/
+ bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
+ sw_cons++;
+ done++;
+
+ if (done == work) {
+ break;
+ }
+ }
+
+ fp->tx_pkt_cons = sw_cons;
+ fp->tx_bd_cons = bd_cons;
+
+ /* Need to make the tx_cons update visible to start_xmit()
+ * before checking for netif_queue_stopped(). Without the
+ * memory barrier, there is a small possibility that start_xmit()
+ * will miss it and cause the queue to be stopped forever.
+ */
+ smp_mb();
+
+ /* TBD need a thresh? */
+ if (unlikely(netif_queue_stopped(bp->dev))) {
+ netif_tx_lock(bp->dev);
+ if ((netif_queue_stopped(bp->dev)) &&
+ (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)) {
+ netif_wake_queue(bp->dev);
+ }
+ netif_tx_unlock(bp->dev);
+ }
+}
+
+static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
+ union eth_rx_cqe *rr_cqe)
+{
+ struct bnx2x *bp = fp->bp;
+ int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+ int command = ((rr_cqe->ramrod_cqe.conn_and_cmd_data) >>
+ COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT);
+
+ DP(NETIF_MSG_RX_STATUS,
+ "fp %d cid %d got ramrod #%d state is %x type is %d\n",
+ fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type);
+
+ bp->spq_left++;
+
+ switch (command | bp->state) {
+ case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
+ DP(NETIF_MSG_IFUP, "got setup ramrod\n");
+ bp->state = BNX2X_STATE_OPEN;
+ break;
+
+ case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
+ DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
+ bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
+ fp->state = BNX2X_FP_STATE_HALTED;
+ break;
+
+ case (RAMROD_CMD_ID_ETH_PORT_DEL | BNX2X_STATE_CLOSING_WAIT4_DELETE):
+ DP(NETIF_MSG_IFDOWN, "got delete ramrod\n");
+ bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
+ break;
+
+ case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
+ DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
+ break;
+
+ default:
+ BNX2X_ERR("unexpected ramrod (%d) state is %x\n",
+ command, bp->state);
+ }
+}
+
+static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp, u16 index)
+{
+ struct sk_buff *skb;
+ struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
+ struct eth_rx_bd *rxbd = &fp->rx_desc_ring[index];
+ dma_addr_t mapping;
+
+ skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
+ if (unlikely(skb == NULL)) {
+ return -ENOMEM;
+ }
+
+ mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
+ PCI_DMA_FROMDEVICE);
+ if (unlikely(dma_mapping_error(mapping))) {
+ dev_kfree_skb(skb);
+ return -ENOMEM;
+ }
+
+ rx_buf->skb = skb;
+ pci_unmap_addr_set(rx_buf, mapping, mapping);
+#ifdef BNX2X_STOP_ON_ERROR
+ rxbd->reserved = fp->last_alloc++;
+#else
+ rxbd->reserved = 0;
+#endif
+ rxbd->len = bp->rx_buf_use_size;
+ rxbd->addr_hi = U64_HI(mapping);
+ rxbd->addr_lo = U64_LO(mapping);
+
+ return 0;
+}
+
+/* note that we are not allocating a new skb,
+ * we are just moving one from cons to prod
+ * we are not creating a new mapping,
+ * so there is no need to check for dma_mapping_error().
+ */
+static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
+ struct sk_buff *skb, u16 cons, u16 prod)
+{
+ struct bnx2x *bp = fp->bp;
+ struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
+ struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
+ struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
+ struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
+
+ pci_dma_sync_single_for_device(bp->pdev,
+ pci_unmap_addr(cons_rx_buf, mapping),
+ bp->rx_offset + RX_COPY_THRESH,
+ PCI_DMA_FROMDEVICE);
+
+ prod_rx_buf->skb = cons_rx_buf->skb;
+ pci_unmap_addr_set(prod_rx_buf, mapping,
+ pci_unmap_addr(cons_rx_buf, mapping));
+ *prod_bd = *cons_bd;
+#ifdef BNX2X_STOP_ON_ERROR
+ prod_bd->reserved = fp->last_alloc++;
+#endif
+}
+
+static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
+{
+ struct bnx2x *bp = fp->bp;
+ u16 bd_cons, bd_prod, comp_ring_prod, comp_ring_cons;
+ u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
+ int rx_pkt = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return 0;
+ }
+#endif
+
+ hw_comp_cons = *fp->rx_cons_sb;
+ if ((hw_comp_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
+ hw_comp_cons++;
+ }
+
+ bd_cons = fp->rx_bd_cons;
+ bd_prod = fp->rx_bd_prod;
+ sw_comp_cons = fp->rx_comp_cons;
+ sw_comp_prod = fp->rx_comp_prod;
+
+ /* Memory barrier necessary as speculative reads of the rx
+ * buffer can be ahead of the index in the status block
+ */
+ rmb();
+
+ DP(NETIF_MSG_RX_STATUS,
+ "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
+ fp->index, hw_comp_cons, sw_comp_cons);
+
+ while (sw_comp_cons != hw_comp_cons) {
+ unsigned int len, pad;
+ struct sw_rx_bd *rx_buf;
+ struct sk_buff *skb;
+ union eth_rx_cqe *cqe;
+
+ comp_ring_prod = RX_BD(sw_comp_prod);
+ comp_ring_cons = RX_BD(sw_comp_cons);
+ bd_prod = RX_BD(bd_prod);
+ bd_cons = RX_BD(bd_cons);
+
+ cqe = &fp->rx_comp_ring[comp_ring_cons];
+
+ DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u sw_comp_cons %u"
+ " comp_ring (%u,%u) bd_ring (%u,%u)\n",
+ hw_comp_cons, sw_comp_cons, comp_ring_prod,
+ comp_ring_cons, bd_prod, bd_cons);
+ DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
+ " queue %x vlan %x len %x csum %x\n",
+ cqe->fast_path_cqe.type, cqe->fast_path_cqe.error_flags,
+ cqe->fast_path_cqe.status_flags,
+ cqe->fast_path_cqe.rss_hash_result,
+ cqe->fast_path_cqe.vlan_tag,
+ cqe->fast_path_cqe.pkt_len, cqe->fast_path_cqe.l4_csum);
+
+ /* is this a slowpath msg? */
+ if (unlikely(cqe->fast_path_cqe.type)) {
+ bnx2x_sp_event(fp, cqe);
+ goto next_cqe;
+
+ /* this is an rx packet */
+ } else {
+ rx_buf = &fp->rx_buf_ring[bd_cons];
+ skb = rx_buf->skb;
+
+ len = cqe->fast_path_cqe.pkt_len;
+ pad = cqe->fast_path_cqe.placement_offset;
+
+ pci_dma_sync_single_for_device(bp->pdev,
+ pci_unmap_addr(rx_buf, mapping),
+ pad + RX_COPY_THRESH,
+ PCI_DMA_FROMDEVICE);
+ prefetch(skb);
+ prefetch(((char *)(skb)) + 128);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ BUG_TRAP(fp->rx_desc_ring[bd_cons].reserved ==
+ fp->next_free);
+ fp->next_free++;
+#endif
+ /* is this an error packet? */
+ if (unlikely(cqe->fast_path_cqe.error_flags)) {
+ /* do we sometimes forward error packets anyway? */
+ DP(NETIF_MSG_RX_ERR,
+ "ERROR flags(%u) Rx packet(%u)\n",
+ cqe->fast_path_cqe.error_flags,
+ sw_comp_cons);
+ /* TBD make sure MC counts this as a drop */
+ goto reuse_rx;
+ }
+
+ /* Since we don't have a jumbo ring
+ * copy small packets if mtu > 1500
+ */
+ if ((bp->dev->mtu > 1500) &&
+ (len <= RX_COPY_THRESH)) {
+ struct sk_buff *new_skb;
+
+ new_skb = netdev_alloc_skb(bp->dev,
+ len + pad);
+ if (new_skb == NULL) {
+ DP(NETIF_MSG_RX_ERR,
+ "ERROR packet dropped "
+ "because of alloc failure\n");
+ /* TBD count this as a drop? */
+ goto reuse_rx;
+ }
+
+ /* aligned copy */
+ skb_copy_from_linear_data_offset(skb, pad,
+ new_skb->data
+ + pad, len);
+
+ skb_reserve(new_skb, pad);
+ skb_put(new_skb, len);
+
+ bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
+
+ skb = new_skb;
+
+ } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
+ pci_unmap_single(bp->pdev,
+ pci_unmap_addr(rx_buf,
+ mapping),
+ bp->rx_buf_use_size,
+ PCI_DMA_FROMDEVICE);
+ skb_reserve(skb, pad);
+ skb_put(skb, len);
+
+ } else {
+ DP(NETIF_MSG_RX_ERR,
+ "ERROR packet dropped because "
+ "of alloc failure\n");
+reuse_rx:
+ bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
+ goto next_rx;
+ }
+
+ skb->protocol = eth_type_trans(skb, bp->dev);
+
+ skb->ip_summed = CHECKSUM_NONE;
+ if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ /* TBD do we pass bad csum packets on promisc?
+ * if (unlikely(cqe->fast_path_cqe.error_flags))
+ * skb->ip_summed = CHECKSUM_NONE;
+ */
+ }
+
+#ifdef BCM_VLAN
+ if ((cqe->fast_path_cqe.pars_flags.flags
+ & PARSING_FLAGS_NUMBER_OF_NESTED_VLANS)
+ && (bp->vlgrp != 0)) {
+ vlan_hwaccel_receive_skb(skb, bp->vlgrp,
+ cqe->fast_path_cqe.vlan_tag);
+ } else
+#endif
+ netif_receive_skb(skb);
+
+ bp->dev->last_rx = jiffies;
+
+next_rx:
+ rx_buf->skb = NULL;
+
+ bd_cons = NEXT_RX_IDX(bd_cons);
+ bd_prod = NEXT_RX_IDX(bd_prod);
+next_cqe:
+ sw_comp_prod = NEXT_RX_IDX(sw_comp_prod);
+ sw_comp_cons = NEXT_RX_IDX(sw_comp_cons);
+ rx_pkt++;
+
+ if ((rx_pkt == budget))
+ break;
+ } /* while */
+
+ fp->rx_bd_cons = bd_cons;
+ fp->rx_bd_prod = bd_prod;
+ fp->rx_comp_cons = sw_comp_cons;
+ fp->rx_comp_prod = sw_comp_prod;
+
+ REG_WR(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod);
+
+ mmiowb();
+
+ fp->rx_pkt += rx_pkt;
+ fp->rx_calls++;
+
+ return rx_pkt;
+}
+
+static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
+{
+ struct bnx2x_fastpath *fp = fp_cookie;
+ struct bnx2x *bp = fp->bp;
+ struct net_device *dev = bp->dev;
+
+ DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", fp->index);
+ bnx2x_ack_sb(bp, fp->index, USTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return IRQ_HANDLED;
+ }
+#endif
+
+ prefetch(fp->rx_cons_sb);
+ prefetch(fp->tx_cons_sb);
+ prefetch(&fp->status_blk->c_status_block.status_block_index);
+ prefetch(&fp->status_blk->u_status_block.status_block_index);
+ netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
+{
+ struct net_device *dev = dev_instance;
+ struct bnx2x *bp = netdev_priv(dev);
+ u16 status = bnx2x_ack_int(bp);
+
+ if (unlikely(status == 0)) {
+ DP(NETIF_MSG_INTR, "not our interrupt!\n");
+ return IRQ_NONE;
+ }
+
+ DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return IRQ_HANDLED;
+ }
+#endif
+
+ /* Return here if interrupt is shared and is disabled */
+ if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+ DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+ return IRQ_HANDLED;
+ }
+
+ if (status & 0x2) {
+ struct bnx2x_fastpath *fp = &bp->fp[0];
+
+ prefetch(fp->rx_cons_sb);
+ prefetch(fp->tx_cons_sb);
+ prefetch(&fp->status_blk->c_status_block.status_block_index);
+ prefetch(&fp->status_blk->u_status_block.status_block_index);
+
+ netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
+
+ status &= ~0x2;
+ if (!status) {
+ return IRQ_HANDLED;
+ }
+ }
+
+ if (unlikely(status & 0x1)) {
+ tasklet_schedule(&bp->sp_task);
+
+ status &= ~0x1;
+ if (!status) {
+ return IRQ_HANDLED;
+ }
+ }
+
+ DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n",
+ status);
+
+ return IRQ_HANDLED;
+}
+
+/* end of fast path */
+
+/* PHY/MAC */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
+{
+ u32 val;
+ int port = bp->port;
+
+ NIG_WR(NIG_REGISTERS_LED_MODE_P0 + port*4,
+ ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
+ SHARED_HW_CFG_LED_MODE_SHIFT));
+ NIG_WR(NIG_REGISTERS_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
+
+ switch (speed) {
+ case SPEED_1000:
+ val = 0x3ff;
+ break;
+
+ case SPEED_100:
+ val = 0x7ff;
+ break;
+
+ case SPEED_10:
+ val = 0xfff;
+ break;
+
+ default: /* 2.5G and up */
+ val = 0xff;
+ break;
+ }
+ NIG_WR(NIG_REGISTERS_LED_CONTROL_BLINK_RATE_P0 + port*4, val);
+ NIG_WR(NIG_REGISTERS_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
+}
+
+static void bnx2x_leds_unset(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ NIG_WR(NIG_REGISTERS_LED_10G_P0 + port*4, 0);
+
+ NIG_WR(NIG_REGISTERS_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
+}
+
+static u32 bnx2x_bits_en(struct bnx2x *bp, u32 block, u32 reg,
+ u32 bits)
+{
+ u32 val = REG_RD(bp, block, reg);
+
+ val |= bits;
+ REG_WR(bp, block, reg, val);
+ return val;
+}
+
+static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 block, u32 reg,
+ u32 bits)
+{
+ u32 val = REG_RD(bp, block, reg);
+
+ val &= ~bits;
+ REG_WR(bp, block, reg, val);
+ return val;
+}
+
+static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val)
+{
+ int rc;
+ u32 tmp, i;
+ int port = bp->port;
+ u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n",
+ bp->phy_addr, reg, val); */
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+ REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ udelay(40);
+ }
+
+ tmp = ((bp->phy_addr << 21) | (reg << 16) |
+ (val & EMAC_MDIO_COMM_DATA) |
+ EMAC_MDIO_COMM_COMMAND_WRITE_22 |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+ udelay(5);
+ break;
+ }
+ }
+
+ if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("write phy register failed\n");
+
+ rc = -EBUSY;
+ } else {
+ rc = 0;
+ }
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp |= EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+ }
+
+ return rc;
+}
+
+static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
+{
+ int rc;
+ u32 val, i;
+ int port = bp->port;
+ u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val &= ~EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+ REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ udelay(40);
+ }
+
+ val = ((bp->phy_addr << 21) | (reg << 16) |
+ EMAC_MDIO_COMM_COMMAND_READ_22 |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+ val &= EMAC_MDIO_COMM_DATA;
+ break;
+ }
+ }
+
+ if (val & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("read phy register failed\n");
+
+ *ret_val = 0x0;
+ rc = -EBUSY;
+ } else {
+ *ret_val = val;
+ rc = 0;
+ }
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val |= EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+ }
+
+/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x ret_val 0x%08x\n",
+ bp->phy_addr, reg, *ret_val); */
+
+ return rc;
+}
+
+static int bnx2x_mdio45_write(struct bnx2x *bp, u32 reg, u32 addr, u32 val)
+{
+ int rc = 0;
+ u32 tmp, i;
+ int port = bp->port;
+ u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+ REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ udelay(40);
+ }
+
+ /* set clause 45 mode */
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp |= EMAC_MDIO_MODE_CLAUSE_45;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+
+ /* address */
+ tmp = ((bp->phy_addr << 21) | (reg << 16) | addr |
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+ udelay(5);
+ break;
+ }
+ }
+
+ if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("write phy register failed\n");
+
+ rc = -EBUSY;
+ } else {
+ /* data */
+ tmp = ((bp->phy_addr << 21) | (reg << 16) | val |
+ EMAC_MDIO_COMM_COMMAND_WRITE_45 |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
+ udelay(5);
+ break;
+ }
+ }
+
+ if (tmp & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("write phy register failed\n");
+
+ rc = -EBUSY;
+ }
+ }
+
+ /* unset clause 45 mode */
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp &= ~EMAC_MDIO_MODE_CLAUSE_45;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ tmp = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ tmp |= EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
+ }
+
+ return rc;
+}
+
+static int bnx2x_mdio45_read(struct bnx2x *bp, u32 reg, u32 addr,
+ u32 *ret_val)
+{
+ int rc = 0;
+ u32 val, i;
+ int port = bp->port;
+ u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val &= ~EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+ REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ udelay(40);
+ }
+
+ /* set clause 45 mode */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val |= EMAC_MDIO_MODE_CLAUSE_45;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+
+ /* address */
+ val = ((bp->phy_addr << 21) | (reg << 16) | addr |
+ EMAC_MDIO_COMM_COMMAND_ADDRESS |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+ udelay(5);
+ break;
+ }
+ }
+
+ if (val & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("read phy register failed\n");
+
+ *ret_val = 0;
+ rc = -EBUSY;
+ } else {
+ /* data */
+ val = ((bp->phy_addr << 21) | (reg << 16) |
+ EMAC_MDIO_COMM_COMMAND_READ_45 |
+ EMAC_MDIO_COMM_START_BUSY);
+ EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
+
+ for (i = 0; i < 50; i++) {
+ udelay(10);
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_COMM);
+ if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
+ val &= EMAC_MDIO_COMM_DATA;
+ break;
+ }
+ }
+
+ if (val & EMAC_MDIO_COMM_START_BUSY) {
+ BNX2X_ERR("read phy register failed\n");
+
+ val = 0;
+ rc = -EBUSY;
+ }
+
+ *ret_val = val;
+ }
+
+ /* unset clause 45 mode */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val &= ~EMAC_MDIO_MODE_CLAUSE_45;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+
+ if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
+
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MDIO_MODE);
+ val |= EMAC_MDIO_MODE_AUTO_POLL;
+ EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
+ }
+
+ return rc;
+}
+
+static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 reg, u32 addr, u32
val)
+{
+ int i;
+ u32 rd_val;
+
+ for (i = 0; i < 10; i++) {
+ bnx2x_mdio45_write(bp, reg, addr, val);
+ mdelay(5);
+ bnx2x_mdio45_read(bp, reg, addr, &rd_val);
+ /* if the read value is not the same as the value we wrote,
+ we should write it again */
+ if (rd_val == val) {
+ return 0;
+ }
+ }
+ BNX2X_ERR("MDIO write in CL45 failed\n");
+ return -EBUSY;
+}
+
+/****************************************************************************
+* Deferred Interrupt service functions
+****************************************************************************/
+
+static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
+{
+ u32 ld_pause; /* local driver */
+ u32 lp_pause; /* link partner */
+ u32 pause_result;
+
+ bp->flow_ctrl = 0;
+
+ /* reolve from gp_status in case of AN complete and not sgmii */
+ if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
+ (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
+ (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
+ (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
+ &ld_pause);
+ bnx2x_mdio22_read(bp,
+ MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
+ &lp_pause);
+ pause_result = (ld_pause &
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
+ pause_result |= (lp_pause &
+ MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
+ DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
+
+ switch (pause_result) { /* ASYM P ASYM P */
+ case 0xb: /* 1 0 1 1 */
+ bp->flow_ctrl = FLOW_CTRL_TX;
+ break;
+
+ case 0xe: /* 1 1 1 0 */
+ bp->flow_ctrl = FLOW_CTRL_RX;
+ break;
+
+ case 0x5: /* 0 1 0 1 */
+ case 0x7: /* 0 1 1 1 */
+ case 0xd: /* 1 1 0 1 */
+ case 0xf: /* 1 1 1 1 */
+ bp->flow_ctrl = FLOW_CTRL_BOTH;
+ break;
+
+ default:
+ break;
+ }
+
+ } else { /* forced mode */
+ bp->flow_ctrl = bp->req_flow_ctrl;
+ if (bp->req_flow_ctrl == FLOW_CTRL_AUTO) {
+ bp->flow_ctrl = FLOW_CTRL_BOTH;
+ }
+ }
+ DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
+}
+
+static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
+{
+ bp->link_status = 0;
+
+ if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
+ DP(NETIF_MSG_LINK, "link up\n");
+
+ bp->link_up = 1;
+ bp->link_status |= LINK_STATUS_LINK_UP;
+
+ if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) {
+ bp->duplex = DUPLEX_FULL;
+ } else {
+ bp->duplex = DUPLEX_HALF;
+ }
+
+ bnx2x_flow_ctrl_resolve(bp, gp_status);
+
+ switch (gp_status & GP_STATUS_SPEED_MASK) {
+ case GP_STATUS_10M:
+ bp->line_speed = SPEED_10;
+ if (bp->duplex == DUPLEX_FULL) {
+ bp->link_status |= LINK_10TFD;
+ } else {
+ bp->link_status |= LINK_10THD;
+ }
+ break;
+
+ case GP_STATUS_100M:
+ bp->line_speed = SPEED_100;
+ if (bp->duplex == DUPLEX_FULL) {
+ bp->link_status |= LINK_100TXFD;
+ } else {
+ bp->link_status |= LINK_100TXHD;
+ }
+ break;
+
+ case GP_STATUS_1G:
+ case GP_STATUS_1G_KX:
+ bp->line_speed = SPEED_1000;
+ if (bp->duplex == DUPLEX_FULL) {
+ bp->link_status |= LINK_1000TFD;
+ } else {
+ bp->link_status |= LINK_1000THD;
+ }
+ break;
+
+ case GP_STATUS_2_5G:
+ bp->line_speed = SPEED_2500;
+ if (bp->duplex == DUPLEX_FULL) {
+ bp->link_status |= LINK_2500TFD;
+ } else {
+ bp->link_status |= LINK_2500THD;
+ }
+ break;
+
+ case GP_STATUS_5G:
+ case GP_STATUS_6G:
+ BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
+ gp_status);
+ break;
+
+ case GP_STATUS_10G_KX4:
+ case GP_STATUS_10G_HIG:
+ case GP_STATUS_10G_CX4:
+ bp->line_speed = SPEED_10000;
+ bp->link_status |= LINK_10GTFD;
+ break;
+
+ case GP_STATUS_12G_HIG:
+ bp->line_speed = SPEED_12000;
+ bp->link_status |= LINK_12GTFD;
+ break;
+
+ case GP_STATUS_12_5G:
+ bp->line_speed = SPEED_12500;
+ bp->link_status |= LINK_12_5GTFD;
+ break;
+
+ case GP_STATUS_13G:
+ bp->line_speed = SPEED_13000;
+ bp->link_status |= LINK_13GTFD;
+ break;
+
+ case GP_STATUS_15G:
+ bp->line_speed = SPEED_15000;
+ bp->link_status |= LINK_15GTFD;
+ break;
+
+ case GP_STATUS_16G:
+ bp->line_speed = SPEED_16000;
+ bp->link_status |= LINK_16GTFD;
+ break;
+
+ default:
+ BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
+ gp_status);
+ break;
+ }
+
+ bp->link_status |= LINK_STATUS_SERDES_LINK;
+
+ if (bp->req_autoneg & AUTONEG_SPEED) {
+ bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
+
+ if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+ bp->link_status |=
+ LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
+ }
+ if (bp->autoneg & AUTONEG_PARALLEL) {
+ bp->link_status |=
+ LINK_STATUS_PARALLEL_DETECTION_USED;
+ }
+ }
+
+ if (bp->flow_ctrl & FLOW_CTRL_TX) {
+ bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
+ }
+ if (bp->flow_ctrl & FLOW_CTRL_RX) {
+ bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
+ }
+
+ } else { /* link_down */
+ DP(NETIF_MSG_LINK, "link down\n");
+
+ bp->link_up = 0;
+
+ bp->line_speed = 0;
+ bp->duplex = DUPLEX_FULL;
+ bp->flow_ctrl = 0;
+ }
+
+ DP(NETIF_MSG_LINK, "gp_status 0x%x link_up %d\n"
+ DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x"
+ " link_status 0x%x\n",
+ gp_status, bp->link_up, bp->line_speed, bp->duplex, bp->flow_ctrl,
+ bp->link_status);
+}
+
+static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
+{
+ int port = bp->port;
+
+ /* first reset all status
+ * we asume only one line will be change at a time */
+ bnx2x_bits_dis(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 + port*4,
+ (NIG_XGXS0_LINK_STATUS |
+ NIG_SERDES0_LINK_STATUS |
+ NIG_STATUS_INTERRUPT_XGXS0_LINK10G));
+ if (bp->link_up) {
+ if (is_10g) {
+ /* Disable the 10G link interrupt
+ * by writing 1 to the status register
+ */
+ DP(NETIF_MSG_LINK, "10G XGXS link up\n");
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 +
+ port*4,
+ NIG_STATUS_INTERRUPT_XGXS0_LINK10G);
+
+ } else if (bp->phy_flags & PHY_XGXS_FLAG) {
+ /* Disable the link interrupt
+ * by writing 1 to the relevant lane
+ * in the status register
+ */
+ DP(NETIF_MSG_LINK, "1G XGXS link up\n");
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 +
+ port*4, ((1 << bp->ser_lane) <<
+ NIG_XGXS0_LINK_STATUS_SIZE));
+
+ } else { /* SerDes */
+ DP(NETIF_MSG_LINK, "SerDes link up\n");
+ /* Disable the link interrupt
+ * by writing 1 to the status register
+ */
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 +
+ port*4, NIG_SERDES0_LINK_STATUS);
+ }
+
+ } else { /* link_down */
+ }
+}
+
+static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
+{
+ u32 ext_phy_type;
+ u32 ext_phy_addr;
+ u32 local_phy;
+ u32 val = 0;
+ u32 rx_sd, pcs_status;
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ local_phy = bp->phy_addr;
+ ext_phy_addr = ((bp->ext_phy_config &
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ bp->phy_addr = (u8)ext_phy_addr;
+
+ ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "XGXS Direct\n");
+ val = 1;
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ DP(NETIF_MSG_LINK, "XGXS 8705\n");
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD,
+ EXT_PHY_OPT_LASI_STATUS, &val);
+ DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val);
+
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD,
+ EXT_PHY_OPT_LASI_STATUS, &val);
+ DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val);
+
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
+ val = (rx_sd & 0x1);
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+ DP(NETIF_MSG_LINK, "XGXS 8706\n");
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_LASI_STATUS, &val);
+ DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val);
+
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_LASI_STATUS, &val);
+ DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val);
+
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
+ bnx2x_mdio45_read(bp, EXT_PHY_OPT_PCS_DEVAD,
+ EXT_PHY_OPT_PCS_STATUS, &pcs_status);
+ DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
+ " pcs_status 0x%x\n", rx_sd, pcs_status);
+ /* link is up if both bit 0 of pmd_rx and
+ * bit 0 of pcs_status are set
+ */
+ val = (rx_sd & pcs_status);
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ val = 0;
+ break;
+ }
+ bp->phy_addr = local_phy;
+
+ } else { /* SerDes */
+ ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "SerDes Direct\n");
+ val = 1;
+ break;
+
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+ DP(NETIF_MSG_LINK, "SerDes 5482\n");
+ val = 1;
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ val = 0;
+ break;
+ }
+ }
+
+ return val;
+}
+
+static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
+{
+ int port = bp->port;
+ u32 bmac_addr = port ? NIG_REGISTERS_INGRESS_BMAC1_MEM :
+ NIG_REGISTERS_INGRESS_BMAC0_MEM;
+ u32 wb_write[2];
+ u32 val;
+
+ DP(NETIF_MSG_LINK, "enableing BigMAC\n");
+ /* reset and unreset the BigMac */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_CLEAR,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+ mdelay(5);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_SET,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+ /* enable access for bmac registers */
+ NIG_WR(NIG_REGISTERS_BMAC0_REGS_OUT_EN + port*4, 0x1);
+
+ /* XGXS control */
+ wb_write[0] = 0x3c;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
+ wb_write, 2);
+
+ /* tx MAC SA */
+ wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
+ (bp->dev->dev_addr[3] << 16) |
+ (bp->dev->dev_addr[4] << 8) |
+ bp->dev->dev_addr[5]);
+ wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
+ bp->dev->dev_addr[1]);
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_write, 2);
+
+ /* tx control */
+ val = 0xc0;
+ if (bp->flow_ctrl & FLOW_CTRL_TX) {
+ val |= 0x800000;
+ }
+ wb_write[0] = val;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
+
+ /* set tx mtu */
+ wb_write[0] = bp->rx_buf_use_size;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
+
+ /* mac control */
+ val = 0x3;
+ if (is_lb) {
+ val |= 0x4;
+ DP(NETIF_MSG_LINK, "enable bmac loopback\n");
+ }
+ wb_write[0] = val;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_write, 2);
+
+ /* rx control set to don't strip crc */
+ val = 0x14;
+ if (bp->flow_ctrl & FLOW_CTRL_RX) {
+ val |= 0x20;
+ }
+ wb_write[0] = val;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
+
+ /* set rx mtu */
+ wb_write[0] = bp->rx_buf_use_size;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
+
+ /* set cnt max size */
+ wb_write[0] = bp->rx_buf_use_size;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_write, 2);
+
+ /* configure safc */
+ wb_write[0] = 0x1000200;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
+ wb_write, 2);
+
+ /* fix for emulation */
+ if (CHIP_REV(bp) == CHIP_REV_EMUL) {
+ wb_write[0] = 0xf000;
+ wb_write[1] = 0;
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
+ wb_write, 2);
+ }
+
+ /* reset old bmac stats */
+ memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
+
+ NIG_WR(NIG_REGISTERS_XCM0_OUT_EN + port*4, 0x0);
+
+ /* select XGXS */
+ NIG_WR(NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
+ NIG_WR(NIG_REGISTERS_XGXS_LANE_SEL_P0 + port*4, 0x0);
+
+ /* disable the NIG in/out to the emac */
+ NIG_WR(NIG_REGISTERS_EMAC0_IN_EN + port*4, 0x0);
+ NIG_WR(NIG_REGISTERS_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
+ NIG_WR(NIG_REGISTERS_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
+
+ /* enable the NIG in/out to the bmac */
+ NIG_WR(NIG_REGISTERS_EGRESS_EMAC0_PORT + port*4, 0x0);
+
+ NIG_WR(NIG_REGISTERS_BMAC0_IN_EN + port*4, 0x1);
+ val = 0;
+ if (bp->flow_ctrl & FLOW_CTRL_TX) {
+ val = 1;
+ }
+ NIG_WR(NIG_REGISTERS_BMAC0_PAUSE_OUT_EN + port*4, val);
+ NIG_WR(NIG_REGISTERS_BMAC0_OUT_EN + port*4, 0x1);
+
+ bp->phy_flags |= PHY_BMAC_FLAG;
+
+ bp->stats_state = STATS_STATE_ENABLE;
+}
+
+static void bnx2x_emac_enable(struct bnx2x *bp)
+{
+ u32 val;
+ int port = bp->port;
+ u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+ int timeout = 200;
+
+ DP(NETIF_MSG_LINK, "enableing EMAC\n");
+ /* reset and unreset the emac core */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_CLEAR,
+ (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+ mdelay(5);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_SET,
+ (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
+
+ /* enable emac and not bmac */
+ NIG_WR(NIG_REGISTERS_EGRESS_EMAC0_PORT + port*4, 1);
+
+ /* for paladium */
+ if (CHIP_REV(bp) == CHIP_REV_EMUL) {
+ /* Use lane 1 (of lanes 0-3) */
+ NIG_WR(NIG_REGISTERS_XGXS_LANE_SEL_P0 + port*4, 1);
+ NIG_WR(NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + port*4, 1);
+ }
+ /* for fpga */
+ else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
+ /* Use lane 1 (of lanes 0-3) */
+ NIG_WR(NIG_REGISTERS_XGXS_LANE_SEL_P0 + port*4, 1);
+ NIG_WR(NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + port*4, 0);
+ }
+ /* ASIC */
+ else {
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ DP(NETIF_MSG_LINK, "XGXS\n");
+ /* select the master lanes (out of 0-3) */
+ NIG_WR(NIG_REGISTERS_XGXS_LANE_SEL_P0 + port*4,
+ bp->ser_lane);
+ /* select XGXS */
+ NIG_WR(NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + port*4,
+ 1);
+
+ } else { /* SerDes */
+ DP(NETIF_MSG_LINK, "SerDes\n");
+ /* select SerDes */
+ NIG_WR(NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + port*4,
+ 0);
+ }
+ }
+
+ /* enable emac */
+ NIG_WR(NIG_REGISTERS_NIG_EMAC0_EN + port*4, 1);
+
+ /* init emac - use read-modify-write */
+ /* self clear reset */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MODE);
+ EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
+
+ while (val & EMAC_MODE_RESET) {
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MODE);
+ DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
+ if (!timeout) {
+ BNX2X_ERR("EMAC timeout!\n");
+ break;
+ }
+ timeout--;
+ }
+
+ /* reset tx part */
+ EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
+
+ while (val & EMAC_TX_MODE_RESET) {
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_TX_MODE);
+ DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
+ if (!timeout) {
+ BNX2X_ERR("EMAC timeout!\n");
+ break;
+ }
+ timeout--;
+ }
+
+ if (CHIP_REV_IS_SLOW(bp)) {
+ /* config GMII mode */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MODE);
+ EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
+
+ } else { /* ASIC */
+ /* pause enable/disable */
+ bnx2x_bits_dis(bp, emac_base, EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
+ if (bp->flow_ctrl & FLOW_CTRL_RX) {
+ bnx2x_bits_en(bp, emac_base, EMAC_REG_EMAC_RX_MODE,
+ EMAC_RX_MODE_FLOW_EN);
+ }
+
+ bnx2x_bits_dis(bp, emac_base, EMAC_REG_EMAC_TX_MODE,
+ EMAC_TX_MODE_EXT_PAUSE_EN);
+ if (bp->flow_ctrl & FLOW_CTRL_TX) {
+ bnx2x_bits_en(bp, emac_base, EMAC_REG_EMAC_TX_MODE,
+ EMAC_TX_MODE_EXT_PAUSE_EN);
+ }
+ }
+
+ /* KEEP_VLAN_TAG, promiscous */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_RX_MODE);
+ val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
+ EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
+
+ /* identify magic packets */
+ val = REG_RD(bp, emac_base, EMAC_REG_EMAC_MODE);
+ EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
+
+ /* enable emac for jumbo packets */
+ EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
+ (EMAC_RX_MTU_SIZE_JUMBO_ENA | (bp->rx_buf_use_size)));
+
+ /* strip CRC */
+ NIG_WR(NIG_REGISTERS_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
+
+ val = ((bp->dev->dev_addr[0] << 8) |
+ bp->dev->dev_addr[1]);
+ EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
+
+ val = ((bp->dev->dev_addr[2] << 24) |
+ (bp->dev->dev_addr[3] << 16) |
+ (bp->dev->dev_addr[4] << 8) |
+ bp->dev->dev_addr[5]);
+ EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
+
+ /* disable the NIG in/out to the bmac */
+ NIG_WR(NIG_REGISTERS_BMAC0_IN_EN + port*4, 0x0);
+ NIG_WR(NIG_REGISTERS_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
+ NIG_WR(NIG_REGISTERS_BMAC0_OUT_EN + port*4, 0x0);
+
+ /* enable the NIG in/out to the emac */
+ NIG_WR(NIG_REGISTERS_EMAC0_IN_EN + port*4, 0x1);
+ val = 0;
+ if (bp->flow_ctrl & FLOW_CTRL_TX) {
+ val = 1;
+ }
+ NIG_WR(NIG_REGISTERS_EMAC0_PAUSE_OUT_EN + port*4, val);
+ NIG_WR(NIG_REGISTERS_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
+
+ if (CHIP_REV(bp) == CHIP_REV_FPGA) {
+ /* take the BigMac out of reset */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_SET,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+ /* enable access for bmac registers */
+ NIG_WR(NIG_REGISTERS_BMAC0_REGS_OUT_EN + port*4, 0x1);
+ }
+
+ bp->phy_flags |= PHY_EMAC_FLAG;
+
+ bp->stats_state = STATS_STATE_ENABLE;
+}
+
+static void bnx2x_emac_program(struct bnx2x *bp)
+{
+ u16 mode = 0;
+ int port = bp->port;
+
+ DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
+ bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400, EMAC_REG_EMAC_MODE,
+ (EMAC_MODE_25G_MODE |
+ EMAC_MODE_PORT_MII_10M |
+ EMAC_MODE_HALF_DUPLEX));
+ switch (bp->line_speed) {
+ case SPEED_10:
+ mode |= EMAC_MODE_PORT_MII_10M;
+ break;
+
+ case SPEED_100:
+ mode |= EMAC_MODE_PORT_MII;
+ break;
+
+ case SPEED_1000:
+ mode |= EMAC_MODE_PORT_GMII;
+ break;
+
+ case SPEED_2500:
+ mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
+ break;
+
+ default:
+ /* 10G not valid for EMAC */
+ BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed);
+ break;
+ }
+
+ if (bp->duplex == DUPLEX_HALF) {
+ mode |= EMAC_MODE_HALF_DUPLEX;
+ }
+ bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400,
+ EMAC_REG_EMAC_MODE, mode);
+
+ bnx2x_leds_set(bp, bp->line_speed);
+}
+
+static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
+{
+ u32 lp_up2;
+ u32 tx_driver;
+
+ /* read precomp */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
+ bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
+ bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
+
+ /* bits [10:7] at lp_up2, positioned at [15:12] */
+ lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
+ MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
+ MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
+
+ if ((lp_up2 != 0) &&
+ (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
+ /* replace tx_driver bits [15:12] */
+ tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
+ tx_driver |= lp_up2;
+ bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
+ }
+}
+
+static void bnx2x_pbf_update(struct bnx2x *bp)
+{
+ int port = bp->port;
+ u32 init_crd, crd;
+ u32 count = 1000;
+ u32 pause = 0;
+
+ /* disable port */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
+
+ /* wait for init credit */
+ init_crd = REG_RD(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_INIT_CRD + port*4);
+ crd = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P0_CREDIT + port*8);
+ DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
+
+ while ((init_crd != crd) && count) {
+ mdelay(5);
+
+ crd = REG_RD(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_CREDIT + port*8);
+ count--;
+ }
+ crd = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P0_CREDIT + port*8);
+ if (init_crd != crd) {
+ /* TBD? Assert if still init_crd != crd */
+ BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
+ }
+
+ if (bp->flow_ctrl & FLOW_CTRL_RX) {
+ pause = 1;
+ }
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_PAUSE_ENABLE + port*4, pause);
+ if (pause) {
+ /* update threshold */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_ARB_THRSH + port*4, 0);
+ /* update init credit */
+ init_crd = 778; /* (800-18-4) */
+
+ } else {
+ /* update threshold */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_ARB_THRSH + port*4,
+ bp->rx_buf_use_size/16);
+ /* update init credit */
+ switch (bp->line_speed) {
+ case SPEED_10:
+ case SPEED_100:
+ case SPEED_1000:
+ init_crd = bp->rx_buf_use_size/16 + 55 - 22;
+ break;
+
+ case SPEED_2500:
+ init_crd = bp->rx_buf_use_size/16 + 138 - 22;
+ break;
+
+ case SPEED_10000:
+ init_crd = bp->rx_buf_use_size/16 + 553 - 22;
+ break;
+
+ default:
+ BNX2X_ERR("Invalid line_speed 0x%x\n",
+ bp->line_speed);
+ break;
+ }
+ }
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_P0_INIT_CRD + port*4, init_crd);
+ DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
+ bp->line_speed, init_crd);
+
+ /* probe the credit changes */
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_INIT_P0 + port*4, 0x1);
+ mdelay(5);
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_INIT_P0 + port*4, 0x0);
+
+ /* enable port */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
+}
+
+static void bnx2x_update_mng(struct bnx2x *bp)
+{
+ if (!nomcp) {
+ SHMEM_WR(bp, drv_fw_mb[bp->port].link_status,
+ bp->link_status);
+ }
+}
+
+static void bnx2x_link_report(struct bnx2x *bp)
+{
+ if (bp->link_up) {
+ netif_carrier_on(bp->dev);
+ printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
+
+ printk("%d Mbps ", bp->line_speed);
+
+ if (bp->duplex == DUPLEX_FULL)
+ printk("full duplex");
+ else
+ printk("half duplex");
+
+ if (bp->flow_ctrl) {
+ if (bp->flow_ctrl & FLOW_CTRL_RX) {
+ printk(", receive ");
+ if (bp->flow_ctrl & FLOW_CTRL_TX)
+ printk("& transmit ");
+ } else {
+ printk(", transmit ");
+ }
+ printk("flow control ON");
+ }
+ printk("\n");
+
+ } else { /* link_down */
+ netif_carrier_off(bp->dev);
+ printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name);
+ }
+}
+
+static void bnx2x_link_up(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ /* PBF - link up */
+ bnx2x_pbf_update(bp);
+
+ /* disable drain */
+ NIG_WR(NIG_REGISTERS_EGRESS_DRAIN0_MODE + port*4, 0);
+
+ /* update share memory */
+ bnx2x_update_mng(bp);
+
+ /* indicate link up */
+ bnx2x_link_report(bp);
+}
+
+static void bnx2x_link_down(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ /* notify stats */
+ if (bp->stats_state != STATS_STATE_DISABLE) {
+ bp->stats_state = STATS_STATE_STOP;
+ DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
+ }
+
+ /* indicate link down */
+ bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
+
+ /* reset BigMac */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2_CLEAR,
+ (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
+
+ /* ignore drain flag interrupt */
+ /* activate nig drain */
+ NIG_WR(NIG_REGISTERS_EGRESS_DRAIN0_MODE + port*4, 1);
+
+ /* update share memory */
+ bnx2x_update_mng(bp);
+
+ /* indicate link down */
+ bnx2x_link_report(bp);
+}
+
+/* This function is called upon link interrupt */
+static void bnx2x_link_update(struct bnx2x *bp)
+{
+ u32 gp_status;
+ int port = bp->port;
+ int i;
+ int link_10g;
+
+ DP(NETIF_MSG_LINK, "port %x, is xgxs %x, stat_mask 0x%x, "
+ "int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
+ " 10G %x, XGXS_LINK %x\n",
+ port, (bp->phy_flags & PHY_XGXS_FLAG),
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 + port*4),
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + port*4),
+ bp->nig_mask,
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT + port*0x18),
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS + port*0x3c),
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_XGXS0_STATUS_LINK10G + port*0x68),
+ REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS + port*0x68)
+ );
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
+ /* avoid fast toggling */
+ for (i = 0 ; i < 10 ; i++) {
+ mdelay(10);
+ bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
+ &gp_status);
+ }
+
+ bnx2x_link_settings_status(bp, gp_status);
+
+ /* anything 10 and over uses the bmac */
+ link_10g = ((bp->line_speed >= SPEED_10000) &&
+ (bp->line_speed <= SPEED_16000));
+
+ bnx2x_link_int_ack(bp, link_10g);
+
+ /* link is up only if both local phy and external phy are up */
+ if (bp->link_up && bnx2x_ext_phy_is_link_up(bp)) {
+ if (link_10g) {
+ bnx2x_bmac_enable(bp, 0);
+ bnx2x_leds_set(bp, SPEED_10000);
+
+ } else {
+ bnx2x_emac_enable(bp);
+ bnx2x_emac_program(bp);
+
+ /* AN complete? */
+ if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
+ if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
+ bnx2x_set_sgmii_tx_driver(bp);
+ }/* Not SGMII */
+ }
+ }
+ bnx2x_link_up(bp);
+
+ } else { /* link down */
+ bnx2x_leds_unset(bp);
+ bnx2x_link_down(bp);
+ }
+}
+
+/****************************************************************************
+* Init service functions
+****************************************************************************/
+
+static void bnx2x_set_aer_mmd(struct bnx2x *bp)
+{
+ u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ?
+ (bp->phy_addr + bp->ser_lane) : 0;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
+ bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
+}
+
+static void bnx2x_set_master_ln(struct bnx2x *bp)
+{
+ u32 new_master_ln;
+
+ /* set the master_ln for AN */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
+ bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+ &new_master_ln);
+ bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
+ (new_master_ln | bp->ser_lane));
+}
+
+static void bnx2x_reset_unicore(struct bnx2x *bp)
+{
+ u32 mii_control;
+ int i;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
+ /* reset the unicore */
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
+
+ /* wait for the reset to self clear */
+ for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
+ udelay(5);
+
+ /* the reset erased the previous bank value */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+
+ if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
+ udelay(5);
+ return;
+ }
+ }
+
+ /* TBD? Assert if the control is still in reset */
+ BNX2X_ERR("BUG! unicore is still in reset!\n");
+}
+
+static void bnx2x_set_swap_lanes(struct bnx2x *bp)
+{
+ /* Each two bits represents a lane number:
+ No swap is 0123 => 0x1b no need to enable the swap */
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
+ if (bp->rx_lane_swap != 0x1b) {
+ bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
+ (bp->rx_lane_swap |
+ MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
+ MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
+ } else {
+ bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
+ }
+
+ if (bp->tx_lane_swap != 0x1b) {
+ bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
+ (bp->tx_lane_swap |
+ MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
+ } else {
+ bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
+ }
+}
+
+static void bnx2x_set_parallel_detection(struct bnx2x *bp)
+{
+ u32 control2;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
+ bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ &control2);
+
+ if (bp->autoneg & AUTONEG_PARALLEL) {
+ control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
+ } else {
+ control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
+ }
+ bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
+ control2);
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ DP(NETIF_MSG_LINK, "XGXS\n");
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
+
+ bnx2x_mdio22_write(bp,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
+
+ bnx2x_mdio22_read(bp,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
+ &control2);
+
+ if (bp->autoneg & AUTONEG_PARALLEL) {
+ control2 |=
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
+ } else {
+ control2 &=
+ ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
+ }
+ bnx2x_mdio22_write(bp,
+ MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
+ control2);
+ }
+}
+
+static void bnx2x_set_autoneg(struct bnx2x *bp)
+{
+ u32 reg_val;
+
+ /* CL37 Autoneg */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
+ if ((bp->req_autoneg & AUTONEG_SPEED) &&
+ (bp->autoneg & AUTONEG_CL37)) {
+ /* CL37 Autoneg Enabled */
+ reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
+ } else {
+ /* CL37 Autoneg Disabled */
+ reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
+ }
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+ /* Enable/Disable Autodetection */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
+ bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
+ reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
+
+ if ((bp->req_autoneg & AUTONEG_SPEED) &&
+ (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
+ reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+ } else {
+ reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
+ }
+ bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
+
+ /* Enable TetonII and BAM autoneg */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
+ bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ ®_val);
+ if ((bp->req_autoneg & AUTONEG_SPEED) &&
+ (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
+ /* Enable BAM aneg Mode and TetonII aneg Mode */
+ reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+ } else {
+ /* TetonII and BAM Autoneg Disabled */
+ reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
+ MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
+ }
+ bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
+ reg_val);
+
+ /* Enable Clause 73 Aneg */
+ if ((bp->req_autoneg & AUTONEG_SPEED) &&
+ (bp->autoneg & AUTONEG_CL73)) {
+ /* Enable BAM Station Manager */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
+ bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
+ (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
+
+ /* Merge CL73 and CL37 aneg resolution */
+ bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
+ ®_val);
+ bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
+ (reg_val |
+ MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
+
+ /* Set the CL73 AN speed */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
+ bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
+ /* In the SerDes we support only the 1G.
+ In the XGXS we support the 10G KX4
+ but we currently do not support the KR */
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ DP(NETIF_MSG_LINK, "XGXS\n");
+ /* 10G KX4 */
+ reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
+ } else {
+ DP(NETIF_MSG_LINK, "SerDes\n");
+ /* 1000M KX */
+ reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
+ }
+ bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
+
+ /* CL73 Autoneg Enabled */
+ reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
+ } else {
+ /* CL73 Autoneg Disabled */
+ reg_val = 0;
+ }
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
+ bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
+}
+
+/* program SerDes, forced modes */
+static void bnx2x_program_serdes(struct bnx2x *bp)
+{
+ u32 reg_val;
+
+ /* program duplex, disable autoneg */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
+ reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
+ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
+ if (bp->req_duplex == DUPLEX_FULL) {
+ reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+ }
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
+
+ /* program speed
+ - needed only if the speed is greater than 1G (2.5G or 10G) */
+ if (bp->req_line_speed > SPEED_1000) {
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
+ bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, ®_val);
+ /* clearing the speed value before setting the right speed */
+ reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
+ reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
+ MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
+ if (bp->req_line_speed == SPEED_10000) {
+ reg_val |=
+ MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
+ }
+ bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
+ }
+}
+
+static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
+{
+ u32 val = 0;
+
+ /* configure the 48 bits for BAM AN */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
+
+ /* set extended capabilities */
+ if (bp->advertising & ADVERTISED_2500baseT_Full) {
+ val |= MDIO_OVER_1G_UP1_2_5G;
+ }
+ if (bp->advertising & ADVERTISED_10000baseT_Full) {
+ val |= MDIO_OVER_1G_UP1_10G;
+ }
+ bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
+
+ bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
+}
+
+static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
+{
+ u32 an_adv;
+
+ /* for AN, we are always publishing full duplex */
+ an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
+
+ /* set pause */
+ switch (bp->pause_mode) {
+ case PAUSE_SYMMETRIC:
+ an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
+ break;
+ case PAUSE_ASYMMETRIC:
+ an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
+ break;
+ case PAUSE_BOTH:
+ an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
+ break;
+ case PAUSE_NONE:
+ an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
+ break;
+ }
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
+}
+
+static void bnx2x_restart_autoneg(struct bnx2x *bp)
+{
+ if (bp->autoneg & AUTONEG_CL73) {
+ /* enable and restart clause 73 aneg */
+ u32 an_ctrl;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
+ bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ &an_ctrl);
+ bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ (an_ctrl |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
+ MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
+
+ } else {
+ /* Enable and restart BAM/CL37 aneg */
+ u32 mii_control;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+ MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
+ }
+}
+
+static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
+{
+ u32 control1;
+
+ /* in SGMII mode, the unicore is always slave */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
+ bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ &control1);
+ control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
+ /* set sgmii mode (and not fiber) */
+ control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
+ MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
+ bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
+ control1);
+
+ /* if forced mode */
+ if (!(bp->req_autoneg & AUTONEG_SPEED)) {
+ /* set speed, disable autoneg */
+ u32 mii_control;
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
+ MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
+
+ switch (bp->req_line_speed) {
+ case SPEED_100:
+ mii_control |=
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
+ break;
+ case SPEED_1000:
+ mii_control |=
+ MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
+ break;
+ case SPEED_10:
+ /* there is nothing to set for 10M */
+ break;
+ default:
+ /* invalid speed for SGMII */
+ DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
+ bp->req_line_speed);
+ break;
+ }
+
+ /* setting the full duplex */
+ if (bp->req_duplex == DUPLEX_FULL) {
+ mii_control |=
+ MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
+ }
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ mii_control);
+
+ } else { /* AN mode */
+ /* enable and restart AN */
+ bnx2x_restart_autoneg(bp);
+ }
+}
+
+static void bnx2x_link_int_enable(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ /* setting the status to report on link up
+ for either XGXS or SerDes */
+ bnx2x_bits_dis(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0 + port*4,
+ (NIG_XGXS0_LINK_STATUS |
+ NIG_STATUS_INTERRUPT_XGXS0_LINK10G |
+ NIG_SERDES0_LINK_STATUS));
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ /* TBD -
+ * in force mode (not AN) we can enable just the relevant
+ * interrupt
+ * Even in AN we might enable only one according to the AN
+ * speed mask
+ */
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + port*4,
+ (NIG_MASK_XGXS0_LINK_STATUS |
+ NIG_MASK_XGXS0_LINK10G));
+ DP(NETIF_MSG_LINK, "enable XGXS interrupt\n");
+
+ } else { /* SerDes */
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + port*4,
+ NIG_MASK_SERDES0_LINK_STATUS);
+ DP(NETIF_MSG_LINK, "enable SerDes interrupt\n");
+ }
+}
+
+static void bnx2x_ext_phy_init(struct bnx2x *bp)
+{
+ int port = bp->port;
+ u32 ext_phy_type;
+ u32 ext_phy_addr;
+ u32 local_phy;
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ local_phy = bp->phy_addr;
+ ext_phy_addr = ((bp->ext_phy_config &
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+
+ ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "XGXS Direct\n");
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ DP(NETIF_MSG_LINK, "XGXS 8705\n");
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 +
+ port*4, NIG_MASK_MI_INT);
+ DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
+
+ bp->phy_addr = ext_phy_type;
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_PMD_MISC_CNTL,
+ 0x8288);
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_PHY_IDENTIFIER,
+ 0x7fbf);
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_CMU_PLL_BYPASS,
+ 0x0100);
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_WIS_DEVAD,
+ EXT_PHY_OPT_LASI_CNTL, 0x1);
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+ DP(NETIF_MSG_LINK, "XGXS 8706\n");
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 +
+ port*4, NIG_MASK_MI_INT);
+ DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
+
+ bp->phy_addr = ext_phy_type;
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_PMD_DIGITAL_CNT,
+ 0x400);
+ bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_LASI_CNTL, 0x1);
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ break;
+ }
+ bp->phy_addr = local_phy;
+
+ } else { /* SerDes */
+/* ext_phy_addr = ((bp->ext_phy_config &
+ PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
+ PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
+*/
+ ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "SerDes Direct\n");
+ break;
+
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+ DP(NETIF_MSG_LINK, "SerDes 5482\n");
+ bnx2x_bits_en(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 +
+ port*4, NIG_MASK_MI_INT);
+ DP(NETIF_MSG_LINK, "enabled extenal phy int\n");
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ break;
+ }
+ }
+}
+
+static void bnx2x_ext_phy_reset(struct bnx2x *bp)
+{
+ u32 ext_phy_type;
+ u32 ext_phy_addr;
+ u32 local_phy;
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "XGXS Direct\n");
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+ DP(NETIF_MSG_LINK, "XGXS 8705/6\n");
+ local_phy = bp->phy_addr;
+ ext_phy_addr = ((bp->ext_phy_config &
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
+ PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
+ bp->phy_addr = (u8)ext_phy_addr;
+ bnx2x_mdio45_write(bp, EXT_PHY_OPT_PMA_PMD_DEVAD,
+ EXT_PHY_OPT_CNTL, 0xa040);
+ bp->phy_addr = local_phy;
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ break;
+ }
+
+ } else { /* SerDes */
+ ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+ DP(NETIF_MSG_LINK, "SerDes Direct\n");
+ break;
+
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+ DP(NETIF_MSG_LINK, "SerDes 5482\n");
+ break;
+
+ default:
+ DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ break;
+ }
+ }
+}
+
+static void bnx2x_link_initialize(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ /* disable attentions */
+ bnx2x_bits_dis(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + port*4,
+ (NIG_MASK_XGXS0_LINK_STATUS |
+ NIG_MASK_XGXS0_LINK10G |
+ NIG_MASK_SERDES0_LINK_STATUS |
+ NIG_MASK_MI_INT));
+
+ bnx2x_ext_phy_reset(bp);
+
+ bnx2x_set_aer_mmd(bp);
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ bnx2x_set_master_ln(bp);
+ }
+
+ /* reset the SerDes and wait for reset bit return low */
+ bnx2x_reset_unicore(bp);
+
+ bnx2x_set_aer_mmd(bp);
+
+ /* setting the masterLn_def again after the reset */
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ bnx2x_set_master_ln(bp);
+ bnx2x_set_swap_lanes(bp);
+ }
+
+ /* Set Parallel Detect */
+ if (bp->req_autoneg & AUTONEG_SPEED) {
+ bnx2x_set_parallel_detection(bp);
+ }
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ if (bp->req_line_speed &&
+ bp->req_line_speed < SPEED_1000) {
+ bp->phy_flags |= PHY_SGMII_FLAG;
+ } else {
+ bp->phy_flags &= ~PHY_SGMII_FLAG;
+ }
+ }
+
+ if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
+ u16 bank, rx_eq;
+
+ rx_eq = ((bp->serdes_config &
+ PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
+ PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
+
+ DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
+ for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
+ bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
+ MDIO_SET_REG_BANK(bp, bank);
+ bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
+ ((rx_eq &
+ MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
+ MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
+ }
+
+ /* forced speed requested? */
+ if (!(bp->req_autoneg & AUTONEG_SPEED)) {
+ DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
+
+ /* disable autoneg */
+ bnx2x_set_autoneg(bp);
+
+ /* program speed and duplex */
+ bnx2x_program_serdes(bp);
+
+ } else { /* AN_mode */
+ DP(NETIF_MSG_LINK, "not SGNII, AN\n");
+
+ /* AN enabled */
+ bnx2x_set_brcm_cl37_advertisment(bp);
+
+ /* program duplex & pause advertisment (for aneg) */
+ bnx2x_set_ieee_aneg_advertisment(bp);
+
+ /* enable autoneg */
+ bnx2x_set_autoneg(bp);
+
+ /* enalbe and restart AN */
+ bnx2x_restart_autoneg(bp);
+ }
+
+ } else { /* SGMII mode */
+ DP(NETIF_MSG_LINK, "SGMII\n");
+
+ bnx2x_initialize_sgmii_process(bp);
+ }
+
+ /* enable the interrupt */
+ bnx2x_link_int_enable(bp);
+
+ /* init ext phy and enable link state int */
+ bnx2x_ext_phy_init(bp);
+}
+
+static void bnx2x_phy_deassert(struct bnx2x *bp)
+{
+ int port = bp->port;
+ u32 val;
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ DP(NETIF_MSG_LINK, "XGXS\n");
+ val = XGXS_RESET_BITS;
+
+ } else { /* SerDes */
+ DP(NETIF_MSG_LINK, "SerDes\n");
+ val = SERDES_RESET_BITS;
+ }
+
+ val = val << (port*16);
+
+ /* reset and unreset the SerDes/XGXS */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_3_CLEAR, val);
+ msleep(5);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_3_SET, val);
+}
+
+static int bnx2x_phy_init(struct bnx2x *bp)
+{
+ DP(NETIF_MSG_LINK, "started\n");
+ if (CHIP_REV(bp) == CHIP_REV_FPGA) {
+ bp->phy_flags |= PHY_EMAC_FLAG;
+ bp->link_up = 1;
+ bp->line_speed = SPEED_10000;
+ bp->duplex = DUPLEX_FULL;
+ NIG_WR(NIG_REGISTERS_EGRESS_DRAIN0_MODE + bp->port*4, 0);
+ bnx2x_emac_enable(bp);
+ bnx2x_link_report(bp);
+ return 0;
+
+ } else if (CHIP_REV(bp) == CHIP_REV_EMUL) {
+ bp->phy_flags |= PHY_BMAC_FLAG;
+ bp->link_up = 1;
+ bp->line_speed = SPEED_10000;
+ bp->duplex = DUPLEX_FULL;
+ NIG_WR(NIG_REGISTERS_EGRESS_DRAIN0_MODE + bp->port*4, 0);
+ bnx2x_bmac_enable(bp, 0);
+ bnx2x_link_report(bp);
+ return 0;
+
+ } else {
+ bnx2x_phy_deassert(bp);
+ bnx2x_link_initialize(bp);
+ }
+
+ return 0;
+}
+
+static void bnx2x_link_reset(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ /* disable attentions */
+ bnx2x_bits_dis(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + port*4,
+ (NIG_MASK_XGXS0_LINK_STATUS |
+ NIG_MASK_XGXS0_LINK10G |
+ NIG_MASK_SERDES0_LINK_STATUS |
+ NIG_MASK_MI_INT));
+
+ bnx2x_ext_phy_reset(bp);
+
+ /* reset the SerDes/XGXS */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_3_CLEAR,
+ (0x1ff << (port*16)));
+
+ /* reset EMAC / BMAC and disable NIG interfaces */
+ NIG_WR(NIG_REGISTERS_BMAC0_IN_EN + port*4, 0);
+ NIG_WR(NIG_REGISTERS_BMAC0_OUT_EN + port*4, 0);
+
+ NIG_WR(NIG_REGISTERS_NIG_EMAC0_EN + port*4, 0);
+ NIG_WR(NIG_REGISTERS_EMAC0_IN_EN + port*4, 0);
+ NIG_WR(NIG_REGISTERS_EGRESS_EMAC0_OUT_EN + port*4, 0);
+
+ NIG_WR(NIG_REGISTERS_EGRESS_DRAIN0_MODE + port*4, 1);
+}
+
+#ifdef BNX2X_XGXS_LB
+static void bnx2x_set_xgxs_loopback (struct bnx2x *bp, int is_10g)
+{
+ int port = bp->port;
+
+ if (is_10g) {
+ u32 md_devad;
+
+ DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
+
+ /* change the uni_phy_addr in the nig */
+ REG_RD(bp, GRCBASE_NIG,
+ (NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD + (port*0x18)),
+ &md_devad);
+ NIG_WR(NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD + (port*0x18), 0x5);
+
+ /* change the aer mmd */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
+ bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
+
+ /* config combo IEEE0 control reg for loopback */
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
+ bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
+ 0x6041);
+
+ /* set aer mmd back */
+ bnx2x_set_aer_mmd(bp);
+
+ /* and md_devad */
+ NIG_WR(NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD + (port*0x18),
+ md_devad);
+
+ } else {
+ u32 mii_control;
+
+ DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
+
+ MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
+ bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ &mii_control);
+ bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
+ (mii_control |
+ MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
+ }
+}
+#endif
+
+/* end of PHY/MAC */
+
+/* slow path */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+/* the slow path queue is odd since completions arrive on the fastpath
ring */
+static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
+ u32 data_hi, u32 data_lo, int common)
+{
+ int port = bp->port;
+
+ DP(NETIF_MSG_TIMER,
+ "spe (%x:%x) command %x hw_cid %x data (%x:%x) left %x\n",
+ (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
+ (void *)bp->spq_prod_bd - (void *)bp->spq), command,
+ HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return -EIO;
+ }
+#endif
+
+ spin_lock(&bp->spq_lock);
+
+ if (!bp->spq_left ||
+ (((bp->spq_prod_idx - bp->spq_con_idx) & 0xfff) ==
+ MAX_SP_DESC_CNT)) {
+
+ BNX2X_ERR("BUG! SPQ ring full!\n");
+ spin_unlock(&bp->spq_lock);
+ bnx2x_panic();
+ return -EBUSY;
+ }
+ /* CID needs port number to be encoded int it */
+ bp->spq_prod_bd->hdr.conn_and_cmd_data =
+ ((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(bp, cid));
+ bp->spq_prod_bd->hdr.type = ETH_CONNECTION_TYPE;
+ if (common)
+ bp->spq_prod_bd->hdr.type |=
+ (1 << SPE_HDR_COMMON_RAMROD_SHIFT);
+
+ bp->spq_prod_bd->data.mac_config_addr.hi = data_hi;
+ bp->spq_prod_bd->data.mac_config_addr.lo = data_lo;
+
+ bp->spq_left--;
+
+ if (bp->spq_prod_bd == bp->spq_last_bd) {
+ bp->spq_prod_bd = bp->spq;
+ bp->spq_prod_idx = 0;
+ DP(NETIF_MSG_TIMER, "end of spq\n");
+
+ } else {
+ bp->spq_prod_bd++;
+ bp->spq_prod_idx++;
+ }
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM, XSTORM_SPQ_PROD_OFFSET(port),
+ bp->spq_prod_idx);
+
+ spin_unlock(&bp->spq_lock);
+ return 0;
+}
+
+/* acquire split MCP access lock register */
+static int bnx2x_lock_alr( struct bnx2x *bp)
+{
+ int rc = 0;
+ u32 i, j, val;
+
+ i = 100;
+
+ for (j = 0; j < i*10; j++) {
+ val = 1UL << 31;
+ REG_WR(bp, GRCBASE_MCP, 0x9c, val);
+ val = REG_RD(bp, GRCBASE_MCP, 0x9c);
+ if (val & (1L << 31)) {
+ break;
+ }
+
+ mdelay(5);
+ }
+
+ if (!(val & (1L << 31))) {
+ BNX2X_ERR("Cannot acquire nvram interface\n");
+
+ rc = -EBUSY;
+ }
+
+ return rc;
+}
+
+/* Release split MCP access lock register */
+static void bnx2x_unlock_alr(struct bnx2x *bp)
+{
+ u32 val = 0;
+
+ REG_WR(bp, GRCBASE_MCP, 0x9c, val);
+}
+
+static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
+{
+ struct host_def_status_block *dsb = bp->def_status_blk;
+ u16 rc = 0;
+
+ if (bp->def_att_idx != dsb->atten_status_block.attn_bits_index) {
+
+
+ bp->def_att_idx = dsb->atten_status_block.attn_bits_index;
+ rc |= 1;
+ }
+ if (bp->def_c_idx != dsb->c_def_status_block.status_block_index) {
+ bp->def_c_idx = dsb->c_def_status_block.status_block_index;
+ rc |= 2;
+ }
+ if (bp->def_u_idx != dsb->u_def_status_block.status_block_index) {
+ bp->def_u_idx = dsb->u_def_status_block.status_block_index;
+ rc |= 4;
+ }
+ if (bp->def_x_idx != dsb->x_def_status_block.status_block_index) {
+ bp->def_x_idx = dsb->x_def_status_block.status_block_index;
+ rc |= 8;
+ }
+ if (bp->def_t_idx != dsb->t_def_status_block.status_block_index) {
+ bp->def_t_idx = dsb->t_def_status_block.status_block_index;
+ rc |= 16;
+ }
+ rmb(); /* TBD chack this */
+ return rc;
+}
+
+/****************************************************************************
+* slow path service functions
+****************************************************************************/
+
+static void bnx2x_attn_int_asserted(struct bnx2x *bp, u16 asserted)
+{
+ int port = bp->port;
+ u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8;
+ u32 aeu_addr = port ? MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 :
+ MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0;
+ u32 nig_mask_addr = port ? NIG_REGISTERS_MASK_INTERRUPT_PORT1 :
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0;
+
+ if (~bp->aeu_mask & (asserted & 0xff))
+ BNX2X_ERR("IGU ERROR\n");
+ if (bp->attn_state & asserted)
+ BNX2X_ERR("IGU ERROR\n");
+
+ DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
+ bp->aeu_mask, asserted);
+ bp->aeu_mask &= ~(asserted & 0xff);
+ DP(NETIF_MSG_HW, "after masking: aeu_mask %x\n", bp->aeu_mask);
+
+ REG_WR(bp, GRCBASE_MISC_AEU, aeu_addr, bp->aeu_mask);
+
+ bp->attn_state |= asserted;
+
+ if (asserted & ATTN_HARD_WIRED_MASK) {
+ if (asserted & ATTN_NIG_FOR_FUNC0) {
+ u32 nig_status_port;
+ u32 nig_int_addr = port ?
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT1 :
+ NIG_REGISTERS_STATUS_INTERRUPT_PORT0;
+
+ bp->nig_mask = REG_RD(bp, GRCBASE_NIG, nig_mask_addr);
+ REG_WR(bp, GRCBASE_NIG, nig_mask_addr, 0);
+
+ nig_status_port = REG_RD(bp, GRCBASE_NIG,
+ nig_int_addr);
+ bnx2x_link_update(bp);
+ /* handle unicore attn? */
+ } /* NIG ATTN */
+ if (asserted & ATTN_SW_TIMER_4_FUNC0) {
+ DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
+ }
+ if (asserted & GPIO_2_FUNC0) {
+ DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
+ }
+ if (asserted & GPIO_3_FUNC0) {
+ DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
+ }
+ if (asserted & GPIO_4_FUNC0) {
+ DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
+ }
+ if (asserted & ATTN_GENERAL_ATTN_1) {
+ DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_GENERAL_ATTN_1, 0x0);
+ /* TBD assert and dump */
+ }
+ if (asserted & ATTN_GENERAL_ATTN_2) {
+ DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
+ }
+ if (asserted & ATTN_GENERAL_ATTN_3) {
+ DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
+ }
+ } /* if hardwired */
+
+ DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n", asserted,
+ BAR_IGU_INTMEM + igu_addr);
+ REG_WR(bp, BAR_IGU_INTMEM, igu_addr, asserted);
+
+ /* now set back the mask */
+ if (asserted & (ATTN_NIG_FOR_FUNC0 | ATTN_NIG_FOR_FUNC1)) {
+ REG_WR(bp, GRCBASE_NIG, nig_mask_addr, bp->nig_mask);
+ }
+}
+
+static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u16 deasserted)
+{
+ int port = bp->port;
+ int index;
+ struct attn_route attn;
+ struct attn_route group_mask;
+ u32 reg_addr;
+ u32 val;
+
+ /* need to take HW lock because MCP or other port might also
+ try to handle this event */
+ bnx2x_lock_alr(bp);
+
+ attn.sig[0] = REG_RD(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0 +
+ port*4);
+
+ attn.sig[1] = REG_RD(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0 +
+ port*4);
+
+ attn.sig[2] = REG_RD(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0 +
+ port*4);
+
+ attn.sig[3] = REG_RD(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0 +
+ port*4);
+
+ DP(NETIF_MSG_HW, "attn %llx\n", (unsigned long long)attn.sig[0]);
+
+ for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
+ if (deasserted & (1 << index)) {
+ group_mask = bp->attn_group[index];
+
+ DP(NETIF_MSG_HW, "group[%d]: %llx\n", index,
+ (unsigned long long)group_mask.sig[0]);
+
+ if (attn.sig[3] & group_mask.sig[3] &
+ EVEREST_GEN_ATTN_IN_USE_MASK) {
+
+ if (BNX2X_MC_ASSERT_BITS & attn.sig[3]) {
+
+ BNX2X_ERR("MC assert!\n");
+ bnx2x_panic();
+
+ } else if (BNX2X_MCP_ASSERT & attn.sig[3]) {
+
+ BNX2X_ERR("MCP assert!\n");
+ REG_WR(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_GENERAL_ATTN_11, 0);
+ bnx2x_mc_assert(bp);
+
+ } else {
+ BNX2X_ERR("UNKOWEN HW ASSERT!\n");
+ }
+ }
+
+ if (attn.sig[1] & group_mask.sig[1] &
+ BNX2X_DOORQ_ASSERT) {
+
+ val = REG_RD(bp, GRCBASE_DQ,
+ DORQ_REGISTERS_DORQ_INT_STS_CLR);
+ BNX2X_ERR("DB hw attention 0x%x\n", val);
+ /* DORQ discard attention */
+ if (val & 0x2) {
+ BNX2X_ERR("FATAL error from DORQ\n");
+ }
+ }
+
+ if (attn.sig[2] & group_mask.sig[2] &
+ AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
+
+ val = REG_RD(bp, GRCBASE_PXP,
+ PXP_REGISTERS_PXP_INT_STS_CLR_0);
+ BNX2X_ERR("PXP hw attention 0x%x\n", val);
+ /* RQ_USDMDP_FIFO_OVERFLOW */
+ if (val & 0x18000) {
+ BNX2X_ERR("FATAL error from PXP\n");
+ }
+ }
+
+ if (attn.sig[3] & group_mask.sig[3] &
+ EVEREST_LATCHED_ATTN_IN_USE_MASK) {
+
+ REG_WR(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL,
+ 0x7ff);
+ DP(NETIF_MSG_HW, "got latched bits 0x%x\n",
+ attn.sig[3]);
+ }
+ }
+ }
+
+ bnx2x_unlock_alr(bp);
+
+ reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_PORT_BASE * port) * 8;
+
+ val = ~deasserted;
+/* DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", val,
+ BAR_IGU_INTMEM + reg_addr); */
+ REG_WR32(bp, BAR_IGU_INTMEM, reg_addr, val);
+
+ if (bp->aeu_mask & (deasserted & 0xff))
+ BNX2X_ERR("IGU BUG\n");
+ if (~bp->attn_state & deasserted)
+ BNX2X_ERR("IGU BUG\n");
+
+ reg_addr = port ? MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 :
+ MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0;
+
+ DP(NETIF_MSG_HW, "aeu_mask %x\n", bp->aeu_mask);
+ bp->aeu_mask |= (deasserted & 0xff);
+
+ DP(NETIF_MSG_HW, "new mask %x\n", bp->aeu_mask);
+ REG_WR(bp, GRCBASE_MISC_AEU, reg_addr, bp->aeu_mask);
+
+ DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
+ bp->attn_state &= ~deasserted;
+ DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
+}
+
+static void bnx2x_attn_int(struct bnx2x *bp)
+{
+ /* read local copy of bits */
+ u16 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
+ u16 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
+ u16 attn_state = bp->attn_state;
+
+ /* look for changed bits */
+ u16 asserted = attn_bits & ~attn_ack & ~attn_state;
+ u16 deasserted = ~attn_bits & attn_ack & attn_state;
+
+ DP(NETIF_MSG_HW,
+ "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
+ attn_bits, attn_ack, asserted, deasserted);
+
+ if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
+ BNX2X_ERR("bad attention state\n");
+ }
+
+ /* handle bits that were raised */
+ if (asserted) {
+ bnx2x_attn_int_asserted(bp, asserted);
+ }
+
+ if (deasserted) {
+ bnx2x_attn_int_deasserted(bp, deasserted);
+ }
+}
+
+static void bnx2x_sp_task(unsigned long arg)
+{
+ struct bnx2x *bp = (struct bnx2x *)arg;
+ u16 status;
+
+ /* Return here if interrupt is disabled. */
+ if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+ DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+ return;
+ }
+
+ status = bnx2x_update_dsb_idx(bp);
+ if (status == 0) {
+ BNX2X_ERR("spurious slowpath interrupt!\n");
+ }
+
+ DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status);
+
+ if (status & 0x1) {
+ /* HW attentions */
+ bnx2x_attn_int(bp);
+ }
+
+ /* CStorm events: query_stats, cfc delete ramrods */
+ if (status & 0x2) {
+ bp->stat_pending = 0;
+ }
+
+ if (status & 0x8) { /* spq consumer update */
+ bp->spq_con_idx = *bp->spq_hw_con;
+ DP(NETIF_MSG_INTR, "spq (%d,%d)\n",
+ bp->spq_prod_idx, bp->spq_con_idx);
+ }
+
+ bnx2x_ack_sb(bp, 16, ATTENTION_ID, bp->def_att_idx, IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, 16, USTORM_ID, bp->def_u_idx, IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, 16, CSTORM_ID, bp->def_c_idx, IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, 16, XSTORM_ID, bp->def_x_idx, IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, 16, TSTORM_ID, bp->def_t_idx, IGU_INT_ENABLE, 1);
+}
+
+static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
+{
+ struct net_device *dev = dev_instance;
+ struct bnx2x *bp = netdev_priv(dev);
+
+ /* Return here if interrupt is disabled. */
+ if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
+ DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+ return IRQ_HANDLED;
+ }
+
+ bnx2x_ack_sb(bp, 16, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return IRQ_HANDLED;
+ }
+#endif
+
+ tasklet_schedule(&bp->sp_task);
+
+ return IRQ_HANDLED;
+}
+
+/* end of slow path */
+
+/* Statistics */
+
+/****************************************************************************
+* Macros
+****************************************************************************/
+
+#define UPDATE_STAT(s, t) \
+ do { \
+ estats->t += new->s - old->s; \
+ old->s = new->s; \
+ } while (0)
+
+/* sum[hi:lo] += add[hi:lo] */
+#define ADD_64(s_hi, a_hi, s_lo, a_lo) \
+ do { \
+ s_lo += a_lo; \
+ s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
+ } while (0)
+
+/* difference = minuend - subtrahend */
+#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
+ do { \
+ if (m_lo < s_lo) { /* underflow */ \
+ d_hi = m_hi - s_hi; \
+ if (d_hi > 0) { /* we can 'loan' 1 */ \
+ d_hi--; \
+ d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
+ } else { /* m_hi <= s_hi */ \
+ d_hi = 0; \
+ d_lo = 0; \
+ } \
+ } else { /* m_lo >= s_lo */ \
+ if (m_hi < s_hi) { \
+ d_hi = 0; \
+ d_lo = 0; \
+ } else { /* m_hi >= s_hi */ \
+ d_hi = m_hi - s_hi; \
+ d_lo = m_lo - s_lo; \
+ } \
+ } \
+ } while (0)
+
+/* minuend -= subtrahend */
+#define SUB_64(m_hi, s_hi, m_lo, s_lo) \
+ do { \
+ DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
+ } while (0)
+
+#define UPDATE_STAT64(s_hi, t_hi, s_lo, t_lo) \
+ do { \
+ DIFF_64(diff.hi, new->s_hi, old->s_hi, \
+ diff.lo, new->s_lo, old->s_lo); \
+ old->s_hi = new->s_hi; \
+ old->s_lo = new->s_lo; \
+ ADD_64(estats->t_hi, diff.hi, \
+ estats->t_lo, diff.lo); \
+ } while (0)
+
+/* sum[hi:lo] += add */
+#define ADD_EXTEND_64(s_hi, s_lo, a) \
+ do { \
+ s_lo += a; \
+ s_hi += (s_lo < a) ? 1 : 0; \
+ } while (0)
+
+#define UPDATE_EXTEND_STAT(s, t_hi, t_lo) \
+ do { \
+ ADD_EXTEND_64(estats->t_hi, estats->t_lo, new->s); \
+ } while (0)
+
+#define UPDATE_EXTEND_TSTAT(s, t_hi, t_lo) \
+ do { \
+ diff = tclient->s - old_tclient->s; \
+ old_tclient->s = tclient->s; \
+ ADD_EXTEND_64(estats->t_hi, estats->t_lo, diff); \
+ } while (0)
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+static inline long bnx2x_hilo(u32 *hiref)
+{
+ u32 lo = *(hiref + 1);
+#if (BITS_PER_LONG == 64)
+ u32 hi = *hiref;
+
+ return HILO_U64(hi, lo);
+#else
+ return lo;
+#endif
+}
+
+/****************************************************************************
+* Init service functions
+****************************************************************************/
+
+/* DMAE command positions used
+ * Port0 BIGMAC 0,1 EMAC 2,3,4 NIG 5 MCP 12
+ * Port1 BIGMAC 6,7 EMAC 8,9,10 NIG 11 MCP 13
+ */
+static void bnx2x_init_mac_stats(struct bnx2x *bp)
+{
+ struct dmae_command *dmae = &bp->dmae;
+ int port = bp->port;
+ u32 mac_addr = (GRCBASE_NIG +
+ (port ? NIG_REGISTERS_INGRESS_BMAC1_MEM :
+ NIG_REGISTERS_INGRESS_BMAC0_MEM));
+
+ memset(dmae, 0, sizeof(struct dmae_command));
+
+ /* BIGMAC_REGISTER_TX_STAT_GTPKT - BIGMAC_REGISTER_TX_STAT_GTBYT */
+ dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+ DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
+ dmae->src_addr_lo = (mac_addr + BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
+ dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
+ BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
+ dmae->comp_addr_lo = (GRCBASE_DMAE +
+ (port ? DMAE_REGISTERS_GO_C7 :
+ DMAE_REGISTERS_GO_C1)) >> 2;
+ dmae->comp_val = 1;
+ bnx2x_post_dmae(bp, port ? 6 : 0);
+
+ /* BIGMAC_REGISTER_RX_STAT_GR64 - BIGMAC_REGISTER_RX_STAT_GRIPJ */
+ /* command type and comp val taken from first command */
+ dmae->src_addr_lo = (mac_addr + BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct bmac_stats, rx_gr64));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct bmac_stats, rx_gr64));
+ dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
+ BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
+ dmae->comp_addr_lo = (GRCBASE_DMAE +
+ (port ? DMAE_REGISTERS_GO_C11 :
+ DMAE_REGISTERS_GO_C5)) >> 2;
+ bnx2x_post_dmae(bp, port ? 7 : 1);
+
+
+ mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
+
+ /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT) */
+ dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
+ dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
+ dmae->comp_addr_lo = (GRCBASE_DMAE +
+ (port ? DMAE_REGISTERS_GO_C9 :
+ DMAE_REGISTERS_GO_C3)) >> 2;
+ bnx2x_post_dmae(bp, port ? 8 : 2);
+
+ /* EMAC_REG_EMAC_RX_STAT_AC_28 */
+ dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct emac_stats,
+ rx_falsecarriererrors));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct emac_stats,
+ rx_falsecarriererrors));
+ dmae->len = 1;
+ dmae->comp_addr_lo = (GRCBASE_DMAE +
+ (port ? DMAE_REGISTERS_GO_C10 :
+ DMAE_REGISTERS_GO_C4)) >> 2;
+ bnx2x_post_dmae(bp, port ? 9 : 3);
+
+ /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT) */
+ dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct emac_stats,
+ tx_ifhcoutoctets));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
+ offsetof(struct emac_stats,
+ tx_ifhcoutoctets));
+ dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
+ dmae->comp_addr_lo = (GRCBASE_DMAE +
+ (port ? DMAE_REGISTERS_GO_C11 :
+ DMAE_REGISTERS_GO_C5)) >> 2;
+ bnx2x_post_dmae(bp, port ? 10 : 4);
+
+ /* NIG */
+ dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
+ DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
+ dmae->src_addr_lo = (GRCBASE_NIG +
+ (port ? NIG_REGISTERS_STAT1_BRB_DISCARD :
+ NIG_REGISTERS_STAT0_BRB_DISCARD)) >> 2;
+ dmae->src_addr_hi = 0;
+ dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig));
+ dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig));
+ dmae->len = (sizeof(struct nig_stats) - 2*sizeof(u32)) >> 2;
+ dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig) +
+ offsetof(struct nig_stats, done));
+ dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig) +
+ offsetof(struct nig_stats, done));
+ dmae->comp_val = 0xffffffff;
+ bnx2x_post_dmae(bp, port ? 11 : 5);
+
+ /* MCP */
+ if (bp->fw_mb) {
+ dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
+ /* DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE | */
+ DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
+#ifdef __BIG_ENDIAN
+ DMAE_CMD_ENDIANITY_B_DW_SWAP |
+#else
+ DMAE_CMD_ENDIANITY_DW_SWAP |
+#endif
+ (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
+ dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, eth_stats) +
+ sizeof(u32));
+ dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, eth_stats) +
+ sizeof(u32));
+ dmae->dst_addr_lo = bp->fw_mb >> 2;
+ dmae->dst_addr_hi = 0;
+ dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
+ sizeof(u32)) >> 2;
+ dmae->comp_addr_lo = 0;
+ dmae->comp_addr_hi = 0;
+ dmae->comp_val = 0;
+ bnx2x_post_dmae(bp, port ? 13 : 12);
+ }
+}
+
+static void bnx2x_init_stats(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ bp->stats_state = STATS_STATE_DISABLE;
+
+ bp->old_brb_discard = REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_STAT0_BRB_DISCARD +
+ port*0x38);
+
+ memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
+ memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
+ memset(&bp->net_stats, 0, sizeof(struct net_device_stats));
+
+ bnx2x_init_mac_stats(bp);
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM, XSTORM_STATS_FLAGS_OFFSET(port), 1);
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM, TSTORM_STATS_FLAGS_OFFSET(port), 1);
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
+
+ REG_WR32(bp, BAR_CSTRORM_INTMEM, CSTORM_STATS_FLAGS_OFFSET(port), 0);
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_STATS_FLAGS_OFFSET(port) + 4, 0);
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
+ U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
+ U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port),
+ U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) + 4,
+ U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
+}
+
+static void bnx2x_stop_stats(struct bnx2x *bp)
+{
+ if (bp->stats_state != STATS_STATE_DISABLE) {
+ bp->stats_state = STATS_STATE_STOP;
+ DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
+
+ while (bp->stats_state != STATS_STATE_DISABLE) {
+ msleep(100);
+ }
+ }
+ DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
+}
+
+/****************************************************************************
+* Statistics service functions
+****************************************************************************/
+
+static void bnx2x_update_bmac_stats(struct bnx2x *bp)
+{
+ struct regp diff;
+ struct regp sum;
+ struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac);
+ struct bmac_stats *old = &bp->old_bmac;
+ struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
+
+ sum.hi = 0;
+ sum.lo = 0;
+
+ UPDATE_STAT64(tx_gtbyt.hi, total_bytes_transmitted_hi,
+ tx_gtbyt.lo, total_bytes_transmitted_lo);
+
+ UPDATE_STAT64(tx_gtmca.hi, total_multicast_packets_transmitted_hi,
+ tx_gtmca.lo, total_multicast_packets_transmitted_lo);
+ ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
+
+ UPDATE_STAT64(tx_gtgca.hi, total_broadcast_packets_transmitted_hi,
+ tx_gtgca.lo, total_broadcast_packets_transmitted_lo);
+ ADD_64(sum.hi, diff.hi, sum.lo, diff.lo);
+
+ UPDATE_STAT64(tx_gtpkt.hi, total_unicast_packets_transmitted_hi,
+ tx_gtpkt.lo, total_unicast_packets_transmitted_lo);
+ SUB_64(estats->total_unicast_packets_transmitted_hi, sum.hi,
+ estats->total_unicast_packets_transmitted_lo, sum.lo);
+
+ UPDATE_STAT(tx_gtxpf.lo, pause_xoff_frames_transmitted);
+ UPDATE_STAT(tx_gt64.lo, frames_transmitted_64_bytes);
+ UPDATE_STAT(tx_gt127.lo, frames_transmitted_65_127_bytes);
+ UPDATE_STAT(tx_gt255.lo, frames_transmitted_128_255_bytes);
+ UPDATE_STAT(tx_gt511.lo, frames_transmitted_256_511_bytes);
+ UPDATE_STAT(tx_gt1023.lo, frames_transmitted_512_1023_bytes);
+ UPDATE_STAT(tx_gt1518.lo, frames_transmitted_1024_1522_bytes);
+ UPDATE_STAT(tx_gt2047.lo, frames_transmitted_1523_9022_bytes);
+ UPDATE_STAT(tx_gt4095.lo, frames_transmitted_1523_9022_bytes);
+ UPDATE_STAT(tx_gt9216.lo, frames_transmitted_1523_9022_bytes);
+ UPDATE_STAT(tx_gt16383.lo, frames_transmitted_1523_9022_bytes);
+
+
+ UPDATE_STAT(rx_grfcs.lo, crc_receive_errors);
+ UPDATE_STAT(rx_grund.lo, runt_packets_received);
+ UPDATE_STAT(rx_grovr.lo, jabber_packets_received);
+ UPDATE_STAT(rx_grxpf.lo, pause_xoff_frames_received);
+ UPDATE_STAT(rx_grxcf.lo, control_frames_received);
+ /* UPDATE_STAT(rx_grxpf.lo, control_frames_received); */
+ UPDATE_STAT(rx_grfrg.lo, error_runt_packets_received);
+ UPDATE_STAT(rx_grjbr.lo, error_jabber_packets_received);
+
+ UPDATE_STAT64(rx_grerb.hi, stat_IfHCInBadOctets_hi,
+ rx_grerb.lo, stat_IfHCInBadOctets_lo);
+ UPDATE_STAT64(tx_gtufl.hi, stat_IfHCOutBadOctets_hi,
+ tx_gtufl.lo, stat_IfHCOutBadOctets_lo);
+ UPDATE_STAT(tx_gterr.lo, stat_Dot3statsinternalmactransmiterrors);
+ /* UPDATE_STAT(rx_grxpf.lo, stat_XoffStateEntered); */
+ estats->stat_XoffStateEntered = estats->pause_xoff_frames_received;
+}
+
+static void bnx2x_update_emac_stats(struct bnx2x *bp)
+{
+ struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac);
+ struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
+
+ UPDATE_EXTEND_STAT(tx_ifhcoutoctets, total_bytes_transmitted_hi,
+ total_bytes_transmitted_lo);
+ UPDATE_EXTEND_STAT(tx_ifhcoutucastpkts,
+ total_unicast_packets_transmitted_hi,
+ total_unicast_packets_transmitted_lo);
+ UPDATE_EXTEND_STAT(tx_ifhcoutmulticastpkts,
+ total_multicast_packets_transmitted_hi,
+ total_multicast_packets_transmitted_lo);
+ UPDATE_EXTEND_STAT(tx_ifhcoutbroadcastpkts,
+ total_broadcast_packets_transmitted_hi,
+ total_broadcast_packets_transmitted_lo);
+
+ estats->pause_xon_frames_transmitted += new->tx_outxonsent;
+ estats->pause_xoff_frames_transmitted += new->tx_outxoffsent;
+ estats->single_collision_transmit_frames +=
+ new->tx_dot3statssinglecollisionframes;
+ estats->multiple_collision_transmit_frames +=
+ new->tx_dot3statsmultiplecollisionframes;
+ estats->late_collision_frames += new->tx_dot3statslatecollisions;
+ estats->excessive_collision_frames +=
+ new->tx_dot3statsexcessivecollisions;
+ estats->frames_transmitted_64_bytes += new->tx_etherstatspkts64octets;
+ estats->frames_transmitted_65_127_bytes +=
+ new->tx_etherstatspkts65octetsto127octets;
+ estats->frames_transmitted_128_255_bytes +=
+ new->tx_etherstatspkts128octetsto255octets;
+ estats->frames_transmitted_256_511_bytes +=
+ new->tx_etherstatspkts256octetsto511octets;
+ estats->frames_transmitted_512_1023_bytes +=
+ new->tx_etherstatspkts512octetsto1023octets;
+ estats->frames_transmitted_1024_1522_bytes +=
+ new->tx_etherstatspkts1024octetsto1522octet;
+ estats->frames_transmitted_1523_9022_bytes +=
+ new->tx_etherstatspktsover1522octets;
+
+ estats->crc_receive_errors += new->rx_dot3statsfcserrors;
+ estats->alignment_errors += new->rx_dot3statsalignmenterrors;
+ estats->false_carrier_detections += new->rx_falsecarriererrors;
+ estats->runt_packets_received += new->rx_etherstatsundersizepkts;
+ estats->jabber_packets_received += new->rx_dot3statsframestoolong;
+ estats->pause_xon_frames_received += new->rx_xonpauseframesreceived;
+ estats->pause_xoff_frames_received += new->rx_xoffpauseframesreceived;
+ estats->control_frames_received += new->rx_maccontrolframesreceived;
+ estats->error_runt_packets_received += new->rx_etherstatsfragments;
+ estats->error_jabber_packets_received += new->rx_etherstatsjabbers;
+
+ UPDATE_EXTEND_STAT(rx_ifhcinbadoctets, stat_IfHCInBadOctets_hi,
+ stat_IfHCInBadOctets_lo);
+ UPDATE_EXTEND_STAT(tx_ifhcoutbadoctets, stat_IfHCOutBadOctets_hi,
+ stat_IfHCOutBadOctets_lo);
+ estats->stat_Dot3statsinternalmactransmiterrors +=
+ new->tx_dot3statsinternalmactransmiterrors;
+ estats->stat_Dot3StatsCarrierSenseErrors +=
+ new->rx_dot3statscarriersenseerrors;
+ estats->stat_Dot3StatsDeferredTransmissions +=
+ new->tx_dot3statsdeferredtransmissions;
+ estats->stat_FlowControlDone += new->tx_flowcontroldone;
+ estats->stat_XoffStateEntered += new->rx_xoffstateentered;
+}
+
+static int bnx2x_update_storm_stats(struct bnx2x *bp)
+{
+ struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
+ struct tstorm_common_stats *tstats = &stats->tstorm_common;
+ struct tstorm_per_client_stats *tclient =
+ &tstats->client_statistics[0];
+ struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
+ struct xstorm_common_stats *xstats = &stats->xstorm_common;
+ struct nig_stats *nstats = bnx2x_sp(bp, nig);
+ struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
+ u32 diff;
+
+ /* are DMAE stats valid? */
+ if (nstats->done != 0xffffffff) {
+ DP(BNX2X_MSG_STATS, "stats not updated by dmae\n");
+ return -1;
+ }
+
+ /* are storm stats valid? */
+ if (tstats->done.hi != 0xffffffff) {
+ DP(BNX2X_MSG_STATS, "stats not updated by tstorm\n");
+ return -2;
+ }
+ if (xstats->done.hi != 0xffffffff) {
+ DP(BNX2X_MSG_STATS, "stats not updated by xstorm\n");
+ return -3;
+ }
+
+ estats->total_bytes_received_hi = tclient->total_rcv_bytes.hi;
+ estats->total_bytes_received_lo = tclient->total_rcv_bytes.lo;
+
+ DIFF_64(estats->valid_bytes_received_hi, tclient->total_rcv_bytes.hi,
+ tclient->rcv_error_bytes.hi,
+ estats->valid_bytes_received_lo, tclient->total_rcv_bytes.lo,
+ tclient->rcv_error_bytes.lo);
+
+ UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
+ total_unicast_packets_received_hi,
+ total_unicast_packets_received_lo);
+ UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
+ total_multicast_packets_received_hi,
+ total_multicast_packets_received_lo);
+ UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
+ total_broadcast_packets_received_hi,
+ total_broadcast_packets_received_lo);
+
+ estats->frames_received_64_bytes = tstats->pkts_till_64B;
+ estats->frames_received_65_127_bytes = tstats->pkts_65_to_127B;
+ estats->frames_received_128_255_bytes = tstats->pkts_128_to_255B;
+ estats->frames_received_256_511_bytes = tstats->pkts_256_to_511B;
+ estats->frames_received_512_1023_bytes = tstats->pkts_512_to_1023B;
+ estats->frames_received_1024_1522_bytes = tstats->pkts_1024_to_1522B;
+ estats->frames_received_1523_9022_bytes = tstats->pkts_1523_to_9022B;
+
+ estats->x_total_sent_bytes_hi = xstats->total_sent_bytes.hi;
+ estats->x_total_sent_bytes_lo = xstats->total_sent_bytes.lo;
+ estats->x_total_sent_pkts = xstats->total_sent_pkts;
+
+ estats->t_rcv_unicast_bytes_hi = tclient->rcv_unicast_bytes.hi;
+ estats->t_rcv_unicast_bytes_lo = tclient->rcv_unicast_bytes.lo;
+ estats->t_rcv_broadcast_bytes_hi = tclient->rcv_broadcast_bytes.hi;
+ estats->t_rcv_broadcast_bytes_lo = tclient->rcv_broadcast_bytes.lo;
+ estats->t_rcv_multicast_bytes_hi = tclient->rcv_multicast_bytes.hi;
+ estats->t_rcv_multicast_bytes_lo = tclient->rcv_multicast_bytes.lo;
+ estats->t_total_rcv_pkt = tclient->total_rcv_pkts;
+
+ estats->no_buff_discard = tclient->no_buff_discard;
+ estats->errors_discard = tclient->errors_discard;
+ estats->ttl0_discard = tclient->ttl0_discard;
+ estats->mac_filter_discard = tstats->mac_filter_discard;
+ estats->xxoverflow_discard = tstats->xxoverflow_discard;
+
+ estats->brb_discard += nstats->brb_discard - bp->old_brb_discard;
+ bp->old_brb_discard = nstats->brb_discard;
+
+ estats->brb_packet = nstats->brb_packet;
+ estats->brb_truncate = nstats->brb_truncate;
+ estats->flow_ctrl_discard = nstats->flow_ctrl_discard;
+ estats->flow_ctrl_octets = nstats->flow_ctrl_octets;
+ estats->flow_ctrl_packet = nstats->flow_ctrl_packet;
+ estats->mng_discard = nstats->mng_discard;
+ estats->mng_octet_inp = nstats->mng_octet_inp;
+ estats->mng_octet_out = nstats->mng_octet_out;
+ estats->mng_packet_inp = nstats->mng_packet_inp;
+ estats->mng_packet_out = nstats->mng_packet_out;
+ estats->pbf_octets = nstats->pbf_octets;
+ estats->pbf_packet = nstats->pbf_packet;
+ estats->safc_inp = nstats->safc_inp;
+
+ xstats->done.hi = 0;
+ tstats->done.hi = 0;
+ nstats->done = 0;
+
+ return 0;
+}
+
+static void bnx2x_update_net_stats(struct bnx2x *bp)
+{
+ struct bnx2x_eth_stats *estats = bnx2x_sp(bp, eth_stats);
+
+ bp->net_stats.rx_packets =
+ bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
+ bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
+ bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
+
+ bp->net_stats.tx_packets =
+ bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
+ bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
+ bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
+
+ bp->net_stats.rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
+
+ bp->net_stats.tx_bytes =
+ bnx2x_hilo(&estats->total_bytes_transmitted_hi);
+
+ bp->net_stats.rx_dropped = estats->no_buff_discard;
+ bp->net_stats.tx_dropped = 0;
+
+ bp->net_stats.multicast =
+ bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
+
+ bp->net_stats.collisions =
+ estats->single_collision_transmit_frames +
+ estats->multiple_collision_transmit_frames +
+ estats->late_collision_frames +
+ estats->excessive_collision_frames; /*TBD check this*/
+
+ bp->net_stats.rx_length_errors = estats->runt_packets_received +
+ estats->jabber_packets_received;
+ bp->net_stats.rx_over_errors = estats->no_buff_discard;
+ bp->net_stats.rx_crc_errors = estats->crc_receive_errors;
+ bp->net_stats.rx_frame_errors = estats->alignment_errors;
+ bp->net_stats.rx_fifo_errors = estats->brb_discard +
+ estats->errors_discard;
+ bp->net_stats.rx_missed_errors = estats->xxoverflow_discard;
+
+ bp->net_stats.rx_errors = bp->net_stats.rx_length_errors +
+ bp->net_stats.rx_over_errors +
+ bp->net_stats.rx_crc_errors +
+ bp->net_stats.rx_frame_errors +
+ bp->net_stats.rx_fifo_errors;
+
+ bp->net_stats.tx_aborted_errors = estats->late_collision_frames +
+ estats->excessive_collision_frames;
+ bp->net_stats.tx_carrier_errors = estats->false_carrier_detections;
+ bp->net_stats.tx_fifo_errors = 0;
+ bp->net_stats.tx_heartbeat_errors = 0;
+ bp->net_stats.tx_window_errors = 0;
+
+ bp->net_stats.tx_errors = bp->net_stats.tx_aborted_errors +
+ bp->net_stats.tx_carrier_errors;
+
+ estats->mac_stx_start = ++estats->mac_stx_end;
+}
+
+static void bnx2x_update_stats(struct bnx2x *bp)
+{
+ if (!bnx2x_update_storm_stats(bp)) {
+
+ if (bp->phy_flags & PHY_BMAC_FLAG) {
+ bnx2x_update_bmac_stats(bp);
+
+ } else if (bp->phy_flags & PHY_EMAC_FLAG) {
+ bnx2x_update_emac_stats(bp);
+
+ } else { /* unreached */
+ BNX2X_ERR("no MAC active\n");
+ return;
+ }
+
+ bnx2x_update_net_stats(bp);
+ }
+
+ if (bp->msglevel & NETIF_MSG_TIMER) {
+ printk(KERN_DEBUG "%s:\n"
+ KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
+ " tx pkt (%lx)\n"
+ KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
+ " rx pkt (%lx)\n"
+ KERN_DEBUG " %s (Xoff events %u) brb drops %u\n"
+ KERN_DEBUG " tstats: no_buff_discard %u"
+ " errors_discard %u mac_filter_discard %u"
+ " xxovrflow_discard %u ttl0_discard %u\n",
+ bp->dev->name, bnx2x_tx_avail(bp->fp),
+ *bp->fp->tx_cons_sb, bp->net_stats.tx_packets,
+ (u16)(*bp->fp->rx_cons_sb - bp->fp->rx_comp_cons),
+ *bp->fp->rx_cons_sb, bp->net_stats.rx_packets,
+ netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
+ bp->slowpath->eth_stats.driver_xoff,
+ bp->slowpath->eth_stats.brb_discard,
+ bp->slowpath->eth_stats.no_buff_discard,
+ bp->slowpath->eth_stats.errors_discard,
+ bp->slowpath->eth_stats.mac_filter_discard,
+ bp->slowpath->eth_stats.xxoverflow_discard,
+ bp->slowpath->eth_stats.ttl0_discard);
+ }
+
+ if (bp->state != BNX2X_STATE_OPEN) {
+ DP(BNX2X_MSG_STATS, "state is %x, returning\n", bp->state);
+ return;
+ }
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return;
+ }
+#endif
+
+ if (bp->fw_mb) {
+ REG_WR32(bp, GRCBASE_DMAE,
+ (bp->port ? DMAE_REGISTERS_GO_C13 :
+ DMAE_REGISTERS_GO_C12), 1);
+ }
+
+ if (bp->stats_state != STATS_STATE_ENABLE) {
+ bp->stats_state = STATS_STATE_DISABLE;
+ return;
+ }
+
+ if (bp->phy_flags & PHY_BMAC_FLAG) {
+ REG_WR32(bp, GRCBASE_DMAE,
+ (bp->port ? DMAE_REGISTERS_GO_C6 :
+ DMAE_REGISTERS_GO_C0), 1);
+
+ } else if (bp->phy_flags & PHY_EMAC_FLAG) {
+ REG_WR32(bp, GRCBASE_DMAE,
+ (bp->port ? DMAE_REGISTERS_GO_C8 :
+ DMAE_REGISTERS_GO_C2), 1);
+ }
+
+ if (bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0, 0, 0, 0) == 0) {
+ /* stats ramrod has it's own slot on the spe */
+ bp->spq_left++;
+ bp->stat_pending = 1;
+ }
+}
+
+static void bnx2x_timer(unsigned long data)
+{
+ struct bnx2x *bp = (struct bnx2x *) data;
+
+ if (!netif_running(bp->dev))
+ return;
+
+ if (atomic_read(&bp->intr_sem) != 0)
+ goto bnx2x_restart_timer;
+
+ if (poll) {
+ struct bnx2x_fastpath *fp = &bp->fp[0];
+ int rc;
+
+ bnx2x_tx_int(fp, 1000);
+ rc = bnx2x_rx_int(fp, 1000);
+ }
+
+ if (!nomcp && (bp->bc_ver >= 0x040003)) {
+ int port = bp->port;
+ u32 drv_pulse;
+ u32 mcp_pulse;
+
+ ++bp->fw_drv_pulse_wr_seq;
+ bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
+ /* TBD - add SYSTEM_TIME */
+ drv_pulse = bp->fw_drv_pulse_wr_seq;
+ SHMEM_WR(bp, drv_fw_mb[port].drv_pulse_mb, drv_pulse);
+
+ mcp_pulse = (SHMEM_RD(bp, drv_fw_mb[port].mcp_pulse_mb) &
+ MCP_PULSE_SEQ_MASK);
+ /* The delta between driver pulse and mcp response
+ * should be 1 (before mcp response) or 0 (after mcp response)
+ */
+ if ((drv_pulse != mcp_pulse) &&
+ (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
+ BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
+ drv_pulse, mcp_pulse);
+ }
+ }
+
+ if (bp->stats_state == STATS_STATE_DISABLE)
+ goto bnx2x_restart_timer;
+
+ bnx2x_update_stats(bp);
+
+bnx2x_restart_timer:
+ mod_timer(&bp->timer, jiffies + bp->current_interval);
+}
+
+/* end of Statistics */
+
+/* nic init */
+
+/****************************************************************************
+* nic init service functions
+****************************************************************************/
+
+static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
+ dma_addr_t mapping, int id)
+{
+ int port = bp->port;
+ u64 section;
+ int index;
+
+ /* USTORM */
+ section = ((u64)mapping) + offsetof(struct host_status_block,
+ u_status_block);
+ sb->u_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_USTRORM_INTMEM,
+ USTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
+ REG_WR32(bp, BAR_USTRORM_INTMEM,
+ ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
+ U64_HI(section));
+
+ for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_USTRORM_INTMEM,
+ USTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
+ }
+
+ /* CSTORM */
+ section = ((u64)mapping) + offsetof(struct host_status_block,
+ c_status_block);
+ sb->c_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id), U64_LO(section));
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, id)) + 4),
+ U64_HI(section));
+
+ for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_SB_HC_DISABLE_OFFSET(port, id, index), 0x1);
+ }
+
+ bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+}
+
+static void bnx2x_init_def_sb(struct bnx2x *bp,
+ struct host_def_status_block *def_sb,
+ dma_addr_t mapping, int id)
+{
+ int port = bp->port;
+ int index, val, reg_offset;
+ u64 section;
+
+ /* ATTN */
+ section = ((u64)mapping) + offsetof(struct host_def_status_block,
+ atten_status_block);
+ def_sb->atten_status_block.status_block_id = id;
+
+ reg_offset = (port ? MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_0 :
+ MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_0);
+
+ for (index = 0; index < 3; index++) {
+ bp->attn_group[index].sig[0] =
+ REG_RD(bp, GRCBASE_MISC_AEU, reg_offset + 0x10*index);
+ bp->attn_group[index].sig[1] =
+ REG_RD(bp, GRCBASE_MISC_AEU,
+ reg_offset + 0x4 + 0x10*index);
+ bp->attn_group[index].sig[2] =
+ REG_RD(bp, GRCBASE_MISC_AEU,
+ reg_offset + 0x8 + 0x10*index);
+ bp->attn_group[index].sig[3] =
+ REG_RD(bp, GRCBASE_MISC_AEU,
+ reg_offset + 0xc + 0x10*index);
+ }
+
+ bp->aeu_mask = REG_RD(bp, GRCBASE_MISC_AEU,
+ (port ? MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 :
+ MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0));
+
+ reg_offset = (port ? HC_REGISTERS_ATTN_MSG1_ADDR_L :
+ HC_REGISTERS_ATTN_MSG0_ADDR_L);
+
+ REG_WR(bp, GRCBASE_HC, reg_offset, U64_LO(section));
+ REG_WR(bp, GRCBASE_HC, reg_offset + 4, U64_HI(section));
+
+ reg_offset = (port ? HC_REGISTERS_ATTN_NUM_P1 :
+ HC_REGISTERS_ATTN_NUM_P0);
+
+ val = REG_RD(bp, GRCBASE_HC, reg_offset);
+ val |= id;
+ REG_WR(bp, GRCBASE_HC, reg_offset, val);
+
+ /* USTORM */
+ section = ((u64)mapping) + offsetof(struct host_def_status_block,
+ u_def_status_block);
+ def_sb->u_def_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_USTRORM_INTMEM,
+ USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
+ REG_WR32(bp, BAR_USTRORM_INTMEM,
+ ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
+ U64_HI(section));
+ REG_WR32(bp, BAR_USTRORM_INTMEM,
+ USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+
+ for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_USTRORM_INTMEM,
+ USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
+ }
+
+ /* CSTORM */
+ section = ((u64)mapping) + offsetof(struct host_def_status_block,
+ c_def_status_block);
+ def_sb->c_def_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
+ U64_HI(section));
+ REG_WR32(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+
+ for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
+ }
+
+ /* TSTORM */
+ section = ((u64)mapping) + offsetof(struct host_def_status_block,
+ t_def_status_block);
+ def_sb->t_def_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
+ U64_HI(section));
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+
+ for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
+ }
+
+ /* XSTORM */
+ section = ((u64)mapping) + offsetof(struct host_def_status_block,
+ x_def_status_block);
+ def_sb->x_def_status_block.status_block_id = id;
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section));
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port)) + 4),
+ U64_HI(section));
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
+
+ for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++) {
+ REG_WR16(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1);
+ }
+
+ bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+}
+
+static void bnx2x_update_coalesce(struct bnx2x *bp)
+{
+ int port = bp->port;
+ int i;
+
+ for_each_queue(bp, i) {
+ /* TBD index need to be changed on BE machines! */
+
+ /* HC_INDEX_U_ETH_RX_CQ_CONS */
+ REG_WR8(bp, BAR_USTRORM_INTMEM,
+ USTORM_SB_HC_TIMEOUT_OFFSET(port, i,
+ HC_INDEX_U_ETH_RX_CQ_CONS),
+ bp->rx_ticks_int/12);
+ REG_WR16(bp, BAR_USTRORM_INTMEM,
+ USTORM_SB_HC_DISABLE_OFFSET(port, i,
+ HC_INDEX_U_ETH_RX_CQ_CONS),
+ bp->rx_ticks_int ? 0 : 1);
+
+ /* HC_INDEX_C_ETH_TX_CQ_CONS */
+ REG_WR8(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_SB_HC_TIMEOUT_OFFSET(port, i,
+ HC_INDEX_C_ETH_TX_CQ_CONS),
+ bp->tx_ticks_int/12);
+ REG_WR16(bp, BAR_CSTRORM_INTMEM,
+ CSTORM_SB_HC_DISABLE_OFFSET(port, i,
+ HC_INDEX_C_ETH_TX_CQ_CONS),
+ bp->tx_ticks_int ? 0 : 1);
+ }
+ /* TBD Dynamic HC? */
+}
+
+static void bnx2x_init_rx_rings(struct bnx2x *bp)
+{
+ u16 ring_prod;
+ int i, j;
+ int port = bp->port;
+
+ /* 8 for CRC and VLAN */
+ bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
+ /* 64 for alignment TBD check */
+ bp->rx_buf_size = bp->rx_buf_use_size + 64;
+
+ for_each_queue(bp, j) {
+ struct bnx2x_fastpath *fp = &bp->fp[j];
+
+#ifdef BNX2X_STOP_ON_ERROR
+ fp->last_alloc = fp->next_free = 0;
+#endif
+ fp->rx_bd_cons = 0;
+ fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
+
+ for (i = 1; i <= NUM_RX_RINGS; i++) {
+
+ struct eth_rx_bd *nextbd;
+
+ nextbd = &fp->rx_desc_ring[RX_DESC_CNT * i - 1];
+ nextbd->addr_hi =
+ U64_HI(fp->rx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_RINGS));
+ nextbd->addr_lo =
+ U64_LO(fp->rx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_RINGS));
+
+ nextbd = (struct eth_rx_bd *)
+ &fp->rx_comp_ring[RX_DESC_CNT * i - 1];
+ nextbd->addr_hi =
+ U64_HI(fp->rx_comp_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_RINGS));
+ nextbd->addr_lo =
+ U64_LO(fp->rx_comp_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_RINGS));
+ }
+
+ /* rx completion queue */
+ fp->rx_comp_cons = ring_prod = 0;
+
+ for (i = 0; i < bp->rx_ring_size; i++) {
+ if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
+ BNX2X_ERR("was only able to allocate "
+ "%d rx skbs\n", i);
+ break;
+ }
+ ring_prod = NEXT_RX_IDX(ring_prod);
+ BUG_TRAP(ring_prod > i);
+ }
+
+ fp->rx_bd_prod = fp->rx_comp_prod = ring_prod;
+ fp->rx_pkt = fp->rx_calls = 0;
+
+ /* Warning! this will genrate an interrupt (to the TSTORM) */
+ /* must only be done when chip is initialized */
+ REG_WR(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod);
+ if (j != 0)
+ continue;
+
+ REG_WR(bp, BAR_USTRORM_INTMEM,
+ USTORM_MEM_WORKAROUND_ADDRESS_OFFSET,
+ U64_LO(fp->rx_comp_mapping));
+ REG_WR(bp, BAR_USTRORM_INTMEM,
+ USTORM_MEM_WORKAROUND_ADDRESS_OFFSET + 4,
+ U64_HI(fp->rx_comp_mapping));
+ }
+}
+
+static void bnx2x_init_tx_ring(struct bnx2x *bp)
+{
+ int i, j;
+
+ for_each_queue(bp, j) {
+ struct bnx2x_fastpath *fp = &bp->fp[j];
+
+ for (i = 1; i <= NUM_TX_RINGS; i++) {
+ struct eth_tx_bd *nextbd =
+ &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
+
+ nextbd->addr_hi =
+ U64_HI(fp->tx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_TX_RINGS));
+ nextbd->addr_lo =
+ U64_LO(fp->tx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_TX_RINGS));
+ }
+
+ fp->tx_pkt_prod = 0;
+ fp->tx_pkt_cons = 0;
+ fp->tx_bd_prod = 0;
+ fp->tx_bd_cons = 0;
+ fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
+ fp->tx_pkt = 0;
+ }
+}
+
+static void bnx2x_init_sp_ring(struct bnx2x *bp)
+{
+ int port = bp->port;
+
+ spin_lock_init(&bp->spq_lock);
+
+ bp->spq_left = MAX_SPQ_PENDING;
+ bp->spq_con_idx = 0;
+ bp->spq_hw_con = BNX2X_SPQ_SB_INDEX;
+ bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
+ bp->spq_prod_bd = bp->spq;
+ bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
+ bp->spq_prod_idx = 0;
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM,
+ XSTORM_SPQ_PAGE_BASE_OFFSET(port) + 4,
+ U64_HI(bp->spq_mapping));
+ REG_WR32(bp, BAR_XSTRORM_INTMEM, XSTORM_SPQ_PAGE_BASE_OFFSET(port),
+ U64_LO(bp->spq_mapping));
+
+ REG_WR(bp, GRCBASE_XSEM, XSEM_REGISTERS_FAST_MEMORY +
+ XSTORM_SPQ_PROD_OFFSET(port), bp->spq_prod_idx);
+}
+
+static void bnx2x_init_context(struct bnx2x *bp)
+{
+ int i;
+
+ for_each_queue(bp, i) {
+ struct eth_context *context = bnx2x_sp(bp, context[i].eth);
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ context->xstorm_st_context.tx_bd_page_base_hi =
+ U64_HI(fp->tx_desc_mapping);
+ context->xstorm_st_context.tx_bd_page_base_lo =
+ U64_LO(fp->tx_desc_mapping);
+ context->xstorm_st_context.db_data_addr_hi =
+ U64_HI(fp->tx_prods_mapping);
+ context->xstorm_st_context.db_data_addr_lo =
+ U64_LO(fp->tx_prods_mapping);
+
+ context->ustorm_st_context.rx_bd_page_base_hi =
+ U64_HI(fp->rx_desc_mapping);
+ context->ustorm_st_context.rx_bd_page_base_lo =
+ U64_LO(fp->rx_desc_mapping);
+ context->ustorm_st_context.status_block_id = i;
+ context->ustorm_st_context.sb_index_number =
+ HC_INDEX_U_ETH_RX_CQ_CONS;
+ context->ustorm_st_context.rcq_base_address_hi =
+ U64_HI(fp->rx_comp_mapping);
+ context->ustorm_st_context.rcq_base_address_lo =
+ U64_LO(fp->rx_comp_mapping);
+ context->ustorm_st_context.flags =
+ USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT;
+ context->ustorm_st_context.mc_alignment_size = 64;
+
+ /* TBD get the optimal value from the ARCH */
+ context->cstorm_st_context.sb_index_number =
+ HC_INDEX_C_ETH_TX_CQ_CONS;
+ context->cstorm_st_context.status_block_id = i;
+
+ context->xstorm_ag_context.cdu_reserved =
+ CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
+ CDU_REGION_NUMBER_XCM_AG,
+ ETH_CONNECTION_TYPE);
+ context->ustorm_ag_context.cdu_usage =
+ CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
+ CDU_REGION_NUMBER_UCM_AG,
+ ETH_CONNECTION_TYPE);
+ }
+}
+
+static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
+{
+ int mode = bp->rx_mode;
+ int port = bp->port;
+ struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
+ int i;
+
+ DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
+
+ switch (mode) {
+ case BNX2X_RX_MODE_NONE: /* no Rx */
+ tstorm_mac_filter.ucast_drop_all = 1;
+ tstorm_mac_filter.mcast_drop_all = 1;
+ tstorm_mac_filter.bcast_drop_all = 1;
+ break;
+ case BNX2X_RX_MODE_NORMAL:
+ tstorm_mac_filter.bcast_accept_all = 1;
+ break;
+ case BNX2X_RX_MODE_ALLMULTI:
+ tstorm_mac_filter.mcast_accept_all = 1;
+ tstorm_mac_filter.bcast_accept_all = 1;
+ break;
+ case BNX2X_RX_MODE_PROMISC:
+ tstorm_mac_filter.ucast_accept_all = 1;
+ tstorm_mac_filter.mcast_accept_all = 1;
+ tstorm_mac_filter.bcast_accept_all = 1;
+ break;
+ default:
+ BNX2X_ERR("bad rx mode (%d)\n", mode);
+ }
+
+ for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_MAC_FILTER_CONFIG_OFFSET(port) + i * 4,
+ ((u32 *)&tstorm_mac_filter)[i]);
+
+/* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
+ ((u32 *)&tstorm_mac_filter)[i]); */
+ }
+}
+
+static void bnx2x_set_client_config(struct bnx2x *bp, int client_id)
+{
+#ifdef BCM_VLAN
+ int mode = bp->rx_mode;
+#endif
+ int port = bp->port;
+ struct tstorm_eth_client_config tstorm_client = {0};
+
+ tstorm_client.max_buffer_size = bp->rx_buf_use_size;
+ tstorm_client.statistics_counter_id = 0;
+ tstorm_client.config_flags =
+ TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
+#ifdef BCM_VLAN
+ if (mode && bp->vlgrp) {
+ tstorm_client.config_flags |=
+ TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
+ DP(NETIF_MSG_RX_STATUS, "vlan removal enabled\n");
+ }
+#else
+/* TBD tstorm_client.config_flags |= */
+/* TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE; */
+#endif
+ tstorm_client.drop_flags = (TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR |
+ TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR |
+ TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR |
+ TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR);
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_CLIENT_CONFIG_OFFSET(port, client_id),
+ ((u32 *)&tstorm_client)[0]);
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) + 4,
+ ((u32 *)&tstorm_client)[1]);
+
+/* DP(NETIF_MSG_IFUP, "tstorm_client: 0x%08x 0x%08x\n",
+ ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]); */
+}
+
+static void bnx2x_init_internal(struct bnx2x *bp)
+{
+ int port = bp->port;
+ struct tstorm_eth_port_common_config tstorm_port_config = {0};
+ struct stats_indication_flags stats_flags = {0};
+ int i;
+
+ tstorm_port_config.config_flags = 0;
+ tstorm_port_config.rss_result_mask = 0;
+ tstorm_port_config.leading_client_id = 0;
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM,
+ TSTORM_PORT_COMMON_CONFIG_OFFSET(port),
+ (*(u32 *)&tstorm_port_config));
+
+/* DP(NETIF_MSG_IFUP, "tstorm_port_config: 0x%08x\n",
+ (*(u32 *)&tstorm_port_config)); */
+
+ bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx untill link is up */
+ bnx2x_set_storm_rx_mode(bp);
+
+ for_each_queue(bp, i) {
+ bnx2x_set_client_config(bp, i);
+ }
+
+ stats_flags.collect_eth = 1;
+
+ REG_WR32(bp, BAR_XSTRORM_INTMEM, XSTORM_STATS_FLAGS_OFFSET(port),
+ ((u32 *)&stats_flags)[0]);
+ REG_WR32(bp, BAR_XSTRORM_INTMEM, XSTORM_STATS_FLAGS_OFFSET(port) + 4,
+ ((u32 *)&stats_flags)[1]);
+
+ REG_WR32(bp, BAR_TSTRORM_INTMEM, TSTORM_STATS_FLAGS_OFFSET(port),
+ ((u32 *)&stats_flags)[0]);
+ REG_WR32(bp, BAR_TSTRORM_INTMEM, TSTORM_STATS_FLAGS_OFFSET(port) + 4,
+ ((u32 *)&stats_flags)[1]);
+
+ REG_WR32(bp, BAR_CSTRORM_INTMEM, CSTORM_STATS_FLAGS_OFFSET(port),
+ ((u32 *)&stats_flags)[0]);
+ REG_WR32(bp, BAR_CSTRORM_INTMEM, CSTORM_STATS_FLAGS_OFFSET(port) + 4,
+ ((u32 *)&stats_flags)[1]);
+
+/* DP(NETIF_MSG_IFUP, "stats_flags: 0x%08x 0x%08x\n",
+ ((u32 *)&stats_flags)[0], ((u32 *)&stats_flags)[1]); */
+}
+
+static int bnx2x_nic_init(struct bnx2x *bp)
+{
+ int i, rc = 0;
+
+ for_each_queue(bp, i) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ fp->state = BNX2X_FP_STATE_CLOSED;
+ DP(NETIF_MSG_IFUP, "bnx2x_init_sb(%p,%p,%d);\n",
+ bp, fp->status_blk, i);
+ fp->index = i;
+ bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping, i);
+ }
+
+ bnx2x_init_def_sb(bp, bp->def_status_blk,
+ bp->def_status_blk_mapping, 0x10);
+ bnx2x_update_coalesce(bp);
+ bnx2x_init_rx_rings(bp);
+ bnx2x_init_tx_ring(bp);
+ bnx2x_init_sp_ring(bp);
+ bnx2x_init_context(bp);
+ bnx2x_init_internal(bp);
+ bnx2x_init_stats(bp);
+ bnx2x_enable_int(bp);
+
+ return rc;
+}
+
+/* end of nic init */
+
+/****************************************************************************
+* gzip service functions
+****************************************************************************/
+
+static int bnx2x_gunzip_init(struct bnx2x *bp)
+{
+ bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
+ &bp->gunzip_mapping);
+ if (bp->gunzip_buf == NULL)
+ goto gunzip_nomem1;
+
+ bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
+ if (bp->strm == NULL)
+ goto gunzip_nomem2;
+
+ bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
+ GFP_KERNEL);
+ if (bp->strm->workspace == NULL)
+ goto gunzip_nomem3;
+
+ return 0;
+
+gunzip_nomem3:
+ kfree(bp->strm);
+ bp->strm = NULL;
+
+gunzip_nomem2:
+ pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
+ bp->gunzip_mapping);
+ bp->gunzip_buf = NULL;
+
+gunzip_nomem1:
+ printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
+ " uncompression\n", bp->dev->name);
+ return -ENOMEM;
+}
+
+static void bnx2x_gunzip_end(struct bnx2x *bp)
+{
+ kfree(bp->strm->workspace);
+
+ kfree(bp->strm);
+ bp->strm = NULL;
+
+ if (bp->gunzip_buf) {
+ pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
+ bp->gunzip_mapping);
+ bp->gunzip_buf = NULL;
+ }
+}
+
+static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
+{
+ int n, rc;
+
+ /* check gzip header */
+ if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
+ return -EINVAL;
+
+ n = 10;
+
+#define FNAME 0x8
+
+ if (zbuf[3] & FNAME)
+ while ((zbuf[n++] != 0) && (n < len));
+
+ bp->strm->next_in = zbuf + n;
+ bp->strm->avail_in = len - n;
+ bp->strm->next_out = bp->gunzip_buf;
+ bp->strm->avail_out = FW_BUF_SIZE;
+
+ rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
+ if (rc != Z_OK)
+ return rc;
+
+ rc = zlib_inflate(bp->strm, Z_FINISH);
+
+ bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out) >> 2;
+
+ if ((rc != Z_OK) && (rc != Z_STREAM_END))
+ printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
+ bp->dev->name, bp->strm->msg);
+
+ zlib_inflateEnd(bp->strm);
+
+ if (rc == Z_STREAM_END)
+ return 0;
+
+ return rc;
+}
+
+/* nic load/unload */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+/* cause the NIG to send a loopback debug packet */
+static void bnx2x_lb_pckt(struct bnx2x *bp)
+{
+#ifdef USE_DMAE
+ u32 wb_write[3];
+#endif
+
+ /* Ethernet source and destination addresses */
+#ifdef USE_DMAE
+ wb_write[0] = 0x55555555;
+ wb_write[1] = 0x55555555;
+ wb_write[2] = 0x20; /* SOP */
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB, wb_write, 3);
+#else
+ REG_WR_IND(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB, 0x55555555);
+ REG_WR_IND(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB + 4, 0x55555555);
+ /* SOP */
+ REG_WR_IND(bp, GRCBASE_NIG, NIG_REGISTERS_DEBUG_PACKET_LB + 8, 0x20);
+#endif
+
+ /* NON-IP protocol */
+#ifdef USE_DMAE
+ wb_write[0] = 0x09000000;
+ wb_write[1] = 0x55555555;
+ wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
+ REG_WR_DMAE(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB, wb_write, 3);
+#else
+ REG_WR_IND(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB, 0x09000000);
+ REG_WR_IND(bp, GRCBASE_NIG,
+ NIG_REGISTERS_DEBUG_PACKET_LB + 4, 0x55555555);
+ /* EOP, eop_bvalid = 0 */
+ REG_WR_IND(bp, GRCBASE_NIG, NIG_REGISTERS_DEBUG_PACKET_LB + 8, 0x10);
+#endif
+}
+
+/* some of the internal memories are not directly readable from the driver
+ to test them we send debug packets
+ */
+static int bnx2x_int_mem_test(struct bnx2x *bp)
+{
+ u32 val;
+ u32 count;
+ u8 hw;
+ u8 port;
+ u8 i;
+ u32 factor;
+
+ switch (CHIP_REV(bp)) {
+ case CHIP_REV_EMUL:
+ hw = INIT_EMULATION;
+ factor = 200;
+ break;
+ case CHIP_REV_FPGA:
+ hw = INIT_FPGA;
+ factor = 120;
+ break;
+ default:
+ hw = INIT_ASIC;
+ factor = 1;
+ break;
+ }
+
+ port = PORT0 << bp->port;
+
+ DP(NETIF_MSG_HW, "mem_wrk start part1\n");
+
+ /* Disable inputs of parser neighbor blocks */
+ REG_WR(bp, GRCBASE_TSDM, TSDM_REGISTERS_ENABLE_IN1, 0x0);
+ REG_WR(bp, GRCBASE_TCM, TCM_REGISTERS_PRS_IFEN, 0x0);
+ REG_WR(bp, GRCBASE_CFC, CFC_REGISTERS_DEBUG0, 0x1);
+ NIG_WR(NIG_REGISTERS_PRS_REQ_IN_EN, 0x0);
+
+ /* Write 0 to parser credits for CFC search request */
+ REG_WR(bp, GRCBASE_PRS, PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+ /* send Ethernet packet */
+ bnx2x_lb_pckt(bp);
+
+ /* TODO do i reset NIG statistic ?*/
+ /* Wait until NIG register shows 1 packet of size 0x10 */
+ count = 1000;
+ while (count) {
+#ifdef BNX2X_DMAE_RD
+ bnx2x_read_dmae(bp,
+ (GRCBASE_NIG + NIG_REGISTERS_STAT2_BRB_OCTET), 2);
+ val = *bnx2x_sp(bp, wb_data[0]);
+#else
+ val = REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET);
+ REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET + 4);
+#endif
+ if (val == 0x10) {
+ break;
+ }
+ msleep(10 * factor);
+ count--;
+ }
+ if (val != 0x10) {
+ BNX2X_ERR("NIG timeout val = 0x%x\n", val);
+ return -1;
+ }
+
+ /* Wait until PRS register shows 1 packet */
+ count = 1000;
+ while (count) {
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_NUM_OF_PACKETS);
+
+ if (val == 0x1) {
+ break;
+ }
+ msleep(10 * factor);
+ count--;
+ }
+ if (val != 0x1) {
+ BNX2X_ERR("PRS timeout val = 0x%x\n", val);
+ return -2;
+ }
+
+ /* Reset and init BRB, PRS */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_1_CLEAR, 0x3);
+ msleep(50);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_1_SET, 0x3);
+ msleep(50);
+ bnx2x_init_stage(bp, BLCNUM_BRB1, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_PRS, COMMON);
+
+ DP(NETIF_MSG_HW, "part2\n");
+
+ /* Disable inputs of parser neighbor blocks */
+ REG_WR(bp, GRCBASE_TSDM, TSDM_REGISTERS_ENABLE_IN1, 0x0);
+ REG_WR(bp, GRCBASE_TCM, TCM_REGISTERS_PRS_IFEN, 0x0);
+ REG_WR(bp, GRCBASE_CFC, CFC_REGISTERS_DEBUG0, 0x1);
+ NIG_WR(NIG_REGISTERS_PRS_REQ_IN_EN, 0x0);
+
+ /* Write 0 to parser credits for CFC search request */
+ REG_WR(bp, GRCBASE_PRS, PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT, 0x0);
+
+ /* send 10 Ethernet packets */
+ for (i = 0; i < 10; i++) {
+ bnx2x_lb_pckt(bp);
+ }
+
+ /* Wait until NIG register shows 10 + 1
+ packets of size 11*0x10 = 0xb0 */
+ count = 1000;
+ while (count) {
+#ifdef BNX2X_DMAE_RD
+ bnx2x_read_dmae(bp,
+ (GRCBASE_NIG + NIG_REGISTERS_STAT2_BRB_OCTET), 2);
+ val = *bnx2x_sp(bp, wb_data[0]);
+#else
+ val = REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET);
+ REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET + 4);
+#endif
+ if (val == 0xb0) {
+ break;
+ }
+ msleep(10 * factor);
+ count--;
+ }
+ if (val != 0xb0) {
+ BNX2X_ERR("NIG timeout val = 0x%x\n", val);
+ return -3;
+ }
+
+ /* Wait until PRS register shows 2 packet */
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_NUM_OF_PACKETS);
+
+ if (val != 0x2) {
+ BNX2X_ERR("PRS timeout val = 0x%x\n", val);
+ }
+
+ /* Write 1 to parser credits for CFC search request */
+ REG_WR(bp, GRCBASE_PRS, PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT, 0x1);
+
+ /* Wait until PRS register shows 3 packet */
+ msleep(10 * factor);
+ /* Wait until NIG register shows 1 packet of size 0x10 */
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_NUM_OF_PACKETS);
+
+ if (val != 0x3) {
+ BNX2X_ERR("PRS timeout val = 0x%x\n", val);
+ }
+ /* clear NIG EOP FIFO */
+ for (i = 0; i < 11; i++) {
+ REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_INGRESS_EOP_LB_FIFO);
+ }
+ val = REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_INGRESS_EOP_LB_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("clear of NIG failed\n");
+ return -4;
+ }
+
+ /* Reset and init BRB, PRS, NIG */
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
+ msleep(50);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_1_SET, 0x03);
+ msleep(50);
+ bnx2x_init_stage(bp, BLCNUM_BRB1, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_PRS, COMMON);
+#ifndef BCM_ISCSI
+ /* set NIC mode */
+ REG_WR(bp, GRCBASE_PRS, PRS_REGISTERS_NIC_MODE, 1);
+#endif
+
+ /* Enable inputs of parser neighbor blocks */
+ REG_WR(bp, GRCBASE_TSDM, TSDM_REGISTERS_ENABLE_IN1, 0x7fffffff);
+ REG_WR(bp, GRCBASE_TCM, TCM_REGISTERS_PRS_IFEN, 0x1);
+ REG_WR(bp, GRCBASE_CFC, CFC_REGISTERS_DEBUG0, 0x0);
+ NIG_WR(NIG_REGISTERS_PRS_REQ_IN_EN, 0x1);
+
+ DP(NETIF_MSG_HW, "done\n");
+
+ return 0; /* OK */
+}
+
+static int bnx2x_function_init(struct bnx2x *bp, int mode)
+{
+ int val, i;
+ u16 j, r_order, w_order;
+ int func = bp->port;
+ int port = func ? PORT1 : PORT0;
+#ifdef USE_DMAE
+ u32 wb_write[2];
+#endif
+
+ DP(BNX2X_MSG_MCP, "function is %d mode is %x\n", func, mode);
+ if ((func != 0) && (func != 1)) {
+ BNX2X_ERR("BAD function number (%d)\n", func);
+ return -ENODEV;
+ }
+
+ bnx2x_gunzip_init(bp);
+
+ if (mode & 0x1) { /* init common */
+ DP(BNX2X_MSG_MCP, "starting common init func %d mode %x\n",
+ func, mode);
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_RESET_REG_1, 0xffffffff);
+ REG_WR(bp, GRCBASE_MISC, MISC_REGISTERS_RESET_REG_2, 0xfffc);
+ bnx2x_init_stage(bp, BLCNUM_MISC, COMMON);
+
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_LCPLL_CTRL_REG_2, 0x100);
+ msleep(30);
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_LCPLL_CTRL_REG_2, 0x0);
+
+ bnx2x_init_stage(bp, BLCNUM_PXP, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_PXP2, COMMON);
+
+ pci_read_config_word(bp->pdev,
+ bp->pcie_cap + PCI_EXP_DEVCTL, &j);
+ DP(NETIF_MSG_HW, "read %x from devctl\n", j);
+ w_order = ((j & PCI_EXP_DEVCTL_PAYLOAD) >> 5); /* 0x0x00e0 */
+ r_order = ((j & PCI_EXP_DEVCTL_READRQ) >> 12); /* 0x7000 */
+
+ bnx2x_init_pxp(bp, r_order, w_order);
+
+ if (CHIP_REV(bp) == CHIP_REV_Ax) {
+ /* enable hw interrupt from PXP on usdm
+ overflow bit 16 on INT_MASK_0 */
+ REG_WR(bp, GRCBASE_PXP,
+ PXP_REGISTERS_PXP_INT_MASK_0, 0);
+ }
+
+#ifdef __BIG_ENDIAN
+#warning big endian driver being compiled
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_QM_ENDIAN_M, 1);
+/* REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_TM_ENDIAN_M, 1); */
+/* REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_SRC_ENDIAN_M, 1); */
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_CDU_ENDIAN_M, 1);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_DBG_ENDIAN_M, 1);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_HC_ENDIAN_M, 1);
+
+/* REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_PBF_SWAP_MODE, 1); */
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_QM_SWAP_MODE, 1);
+/* REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_TM_SWAP_MODE, 1); */
+/* REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_SRC_SWAP_MODE, 1); */
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RD_CDURD_SWAP_MODE, 1);
+#endif /* BIG_ENDIAN */
+
+#ifndef BCM_ISCSI
+ /* set NIC mode */
+ REG_WR(bp, GRCBASE_PRS, PRS_REGISTERS_NIC_MODE, 1);
+#endif
+
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_CDU_P_SIZE, 5);
+#ifdef BCM_ISCSI
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_TM_P_SIZE, 5);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_QM_P_SIZE, 5);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_SRC_P_SIZE, 5);
+#endif
+
+ bnx2x_init_stage(bp, BLCNUM_DMAE, COMMON);
+
+ /* let the HW do it's magic ... */
+ msleep(100); /* TBD */
+ /* finish PXP init
+ (can be moved up if we want to use the DMAE) */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_CFG_DONE);
+ if (val != 1) {
+ BNX2X_ERR("PXP2 CFG failed\n");
+ return -EBUSY;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_INIT_DONE);
+ if (val != 1) {
+ BNX2X_ERR("PXP2 RD_INIT failed\n");
+ return -EBUSY;
+ }
+
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_DISABLE_INPUTS, 0);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_DISABLE_INPUTS, 0);
+
+ DMAE_CLR(bp, GRCBASE_TSEM, TSEM_REGISTERS_PRAM, 8);
+
+ bnx2x_init_stage(bp, BLCNUM_TCM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_UCM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_CCM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_XCM, COMMON);
+
+ /* TBD merge with init tool? */
+#ifdef BNX2X_DMAE_RD
+ bnx2x_read_dmae(bp,
+ (GRCBASE_XSEM + XSEM_REGISTERS_PASSIVE_BUFFER), 3);
+ bnx2x_read_dmae(bp,
+ (GRCBASE_CSEM + CSEM_REGISTERS_PASSIVE_BUFFER), 3);
+ bnx2x_read_dmae(bp,
+ (GRCBASE_TSEM + TSEM_REGISTERS_PASSIVE_BUFFER), 3);
+ bnx2x_read_dmae(bp,
+ (GRCBASE_USEM + USEM_REGISTERS_PASSIVE_BUFFER), 3);
+#else
+ REG_RD(bp, GRCBASE_XSEM, XSEM_REGISTERS_PASSIVE_BUFFER);
+ REG_RD(bp, GRCBASE_XSEM, XSEM_REGISTERS_PASSIVE_BUFFER + 4);
+ REG_RD(bp, GRCBASE_XSEM, XSEM_REGISTERS_PASSIVE_BUFFER + 8);
+ REG_RD(bp, GRCBASE_CSEM, CSEM_REGISTERS_PASSIVE_BUFFER);
+ REG_RD(bp, GRCBASE_CSEM, CSEM_REGISTERS_PASSIVE_BUFFER + 4);
+ REG_RD(bp, GRCBASE_CSEM, CSEM_REGISTERS_PASSIVE_BUFFER + 8);
+ REG_RD(bp, GRCBASE_TSEM, TSEM_REGISTERS_PASSIVE_BUFFER);
+ REG_RD(bp, GRCBASE_TSEM, TSEM_REGISTERS_PASSIVE_BUFFER + 4);
+ REG_RD(bp, GRCBASE_TSEM, TSEM_REGISTERS_PASSIVE_BUFFER + 8);
+ REG_RD(bp, GRCBASE_USEM, USEM_REGISTERS_PASSIVE_BUFFER);
+ REG_RD(bp, GRCBASE_USEM, USEM_REGISTERS_PASSIVE_BUFFER + 4);
+ REG_RD(bp, GRCBASE_USEM, USEM_REGISTERS_PASSIVE_BUFFER + 8);
+#endif
+ bnx2x_init_stage(bp, BLCNUM_QM, COMMON);
+ /* softrest pulse */
+ REG_WR(bp, GRCBASE_QM, QM_REGISTERS_SOFT_RESET, 1);
+ REG_WR(bp, GRCBASE_QM, QM_REGISTERS_SOFT_RESET, 0);
+
+#ifdef BCM_ISCSI
+ bnx2x_init_stage(bp, BLCNUM_TIMERS, COMMON);
+#endif
+ bnx2x_init_stage(bp, BLCNUM_DQ, COMMON);
+ REG_WR(bp, GRCBASE_DQ, DORQ_REGISTERS_DPM_CID_OFST,
+ BCM_PAGE_BITS);
+ if (CHIP_REV(bp) == CHIP_REV_Ax) {
+ /* enable hw interrupt from doorbell Q */
+ REG_WR(bp, GRCBASE_DQ,
+ DORQ_REGISTERS_DORQ_INT_MASK, 0);
+ }
+
+ bnx2x_init_stage(bp, BLCNUM_BRB1, COMMON);
+
+ if (CHIP_REV_IS_SLOW(bp)) {
+ /* fix for emulation and FPGA for no pause */
+ REG_WR(bp, GRCBASE_BRB1,
+ BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_0, 513);
+ REG_WR(bp, GRCBASE_BRB1,
+ BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_1, 513);
+ REG_WR(bp, GRCBASE_BRB1,
+ BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_0, 0);
+ REG_WR(bp, GRCBASE_BRB1,
+ BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_1, 0);
+ }
+
+ bnx2x_init_stage(bp, BLCNUM_PRS, COMMON);
+
+ bnx2x_init_stage(bp, BLCNUM_TSDM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_CSDM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_USDM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_XSDM, COMMON);
+
+ bnx2x_zero_intmem(bp);
+
+ bnx2x_init_stage(bp, BLCNUM_TSEM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_USEM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_CSEM, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_XSEM, COMMON);
+
+ /* sync semi rtc */
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
+
+ bnx2x_init_stage(bp, BLCNUM_UPB, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_XPB, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_PBF, COMMON);
+
+#if defined(BCM_ISCSI) | defined(BCM_MULTI)
+ REG_WR(bp, GRCBASE_SRCH, SRC_REGISTERS_SOFT_RST, 1);
+ for (i = SRC_REGISTERS_KEYRSS0_0;
+ i <= SRC_REGISTERS_KEYRSS1_9; i += 4) {
+ REG_WR(bp, GRCBASE_SRCH, i, 0xc0cac01a);
+ /* todo: repleace with something meaningfull */
+ }
+ bnx2x_init_stage(bp, BLCNUM_SRCH, COMMON);
+ REG_WR(bp, GRCBASE_SRCH, SRC_REGISTERS_SOFT_RST, 0);
+#endif
+
+ if (sizeof(union cdu_context) != 1024) {
+ printk(KERN_ALERT PFX "please adjust the size of"
+ " cdu_context(%ld)\n",
+ (long)sizeof(union cdu_context));
+ }
+ val = (4 << 24) + (0 << 12) + 1024;
+ REG_WR(bp, GRCBASE_CDU, CDU_REGISTERS_CDU_GLOBAL_PARAMS, val);
+ bnx2x_init_stage(bp, BLCNUM_CDU, COMMON);
+
+ bnx2x_init_stage(bp, BLCNUM_CFC, COMMON);
+ REG_WR(bp, GRCBASE_CFC, CFC_REGISTERS_INIT_REG, 0x7FF);
+
+ bnx2x_init_stage(bp, BLCNUM_HC, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_MISC_AEU, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_PXPCS, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_EMAC0, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_EMAC1, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_DBU, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_DBG, COMMON);
+ bnx2x_init_stage(bp, BLCNUM_NIG, COMMON);
+
+ if (CHIP_REV_IS_SLOW(bp)) {
+ msleep(200);
+ }
+
+ /* finish CFC init */
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_LL_INIT_DONE);
+ if (val != 1) {
+ BNX2X_ERR("CFC LL_INIT failed\n");
+ return -EBUSY;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_AC_INIT_DONE);
+ if (val != 1) {
+ BNX2X_ERR("CFC AC_INIT failed\n");
+ return -EBUSY;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_CAM_INIT_DONE);
+ if (val != 1) {
+ BNX2X_ERR("CFC CAM_INIT failed\n");
+ return -EBUSY;
+ }
+
+ REG_WR(bp, GRCBASE_CFC, CFC_REGISTERS_DEBUG0, 0);
+
+ /* read NIG statistic
+ to see if this is our first up since powerup */
+#ifdef BNX2X_DMAE_RD
+ bnx2x_read_dmae(bp,
+ (GRCBASE_NIG + NIG_REGISTERS_STAT2_BRB_OCTET), 2);
+ val = *bnx2x_sp(bp, wb_data[0]);
+#else
+ val = REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET);
+ REG_RD(bp, GRCBASE_NIG, NIG_REGISTERS_STAT2_BRB_OCTET + 4);
+#endif
+ /* do internal memory self test */
+ if (val == 0 && bnx2x_int_mem_test(bp)) {
+ BNX2X_ERR("internal mem selftest failed\n");
+ return -EBUSY;
+ }
+ } /* end of common init */
+
+ /* per port init */
+
+ /* the phys address is shifted right 12 bits and has an added
+ 1=valid bit added to the 53rd bit
+ then since this is a wide register(TM)
+ we split it into two 32 bit writes
+ */
+#define ONCHIP_ADDR1(x) ((u32)((u64)x >> 12 & 0xFFFFFFFF))
+#define ONCHIP_ADDR2(x) ((u32)(1 << 20 | (u64)x >> 44))
+#define PXP_ONE_ILT(x) ((x << 10) | x)
+
+ DP(BNX2X_MSG_MCP, "starting per-function init port is %x\n", func);
+
+ REG_WR(bp, GRCBASE_NIG,
+ NIG_REGISTERS_MASK_INTERRUPT_PORT0 + func*4, 0);
+ bnx2x_init_stage(bp, BLCNUM_PXP, port);
+ bnx2x_init_stage(bp, BLCNUM_PXP2, port);
+
+ if (func == 0) {
+ /* offset is 0 */
+#ifdef USE_DMAE
+ wb_write[0] = ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context));
+ wb_write[1] = ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context));
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT, wb_write, 2);
+#else
+ REG_WR_IND(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_ONCHIP_AT,
+ ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context)));
+ REG_WR_IND(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_ONCHIP_AT + 4,
+ ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context)));
+#endif
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_CDU0_L2P, PXP_ONE_ILT(0));
+
+#ifdef BCM_ISCSI
+ /* offset is 1 */
+ wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_TM0_L2P, PXP_ONE_ILT(1));
+
+ /* 3 */
+ wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 2*8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_QM0_L2P, PXP_ONE_ILT(2));
+
+ /* 4 */
+ wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 3*8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_SRC0_L2P, PXP_ONE_ILT(3));
+#endif
+
+ } else {
+ /* second function addresses start from 384 */
+ /* 384 */
+#ifdef USE_DMAE
+ wb_write[0] = ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context));
+ wb_write[1] = ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context));
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 384*8, wb_write, 2);
+#else
+ REG_WR_IND(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 384*8,
+ ONCHIP_ADDR1(bnx2x_sp_mapping(bp, context)));
+ REG_WR_IND(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 384*8 + 4,
+ ONCHIP_ADDR2(bnx2x_sp_mapping(bp, context)));
+#endif
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_CDU1_L2P, PXP_ONE_ILT(384));
+
+#ifdef BCM_ISCSI
+ /* 385 */
+ wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 385*8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_TM1_L2P, PXP_ONE_ILT(385));
+
+ wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 386*8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_QM1_L2P, PXP_ONE_ILT(386));
+
+ wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
+ wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
+ REG_WR_DMAE(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_RQ_ONCHIP_AT + 387*8, wb_write, 2);
+ REG_WR(bp, GRCBASE_PXP2,
+ PXP2_REGISTERS_PSWRQ_SRC1_L2P, PXP_ONE_ILT(387));
+#endif
+ }
+
+ bnx2x_init_stage(bp, BLCNUM_TCM, port);
+ bnx2x_init_stage(bp, BLCNUM_UCM, port);
+ bnx2x_init_stage(bp, BLCNUM_CCM, port);
+ bnx2x_init_stage(bp, BLCNUM_XCM, port);
+
+#ifdef USE_DMAE
+ wb_write[0] = 0;
+ wb_write[1] = 0;
+#endif
+ if (func == 0) {
+ for (i = 0; i < 32; i++) {
+ REG_WR(bp, GRCBASE_QM,
+ QM_REGISTERS_BASEADDR + 4*i, 1024 * 4 * i);
+#ifdef USE_DMAE
+ REG_WR_DMAE(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + i*8, wb_write, 2);
+#else
+ REG_WR_IND(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + i*8, 0);
+ REG_WR_IND(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + i*8 + 4, 0);
+#endif
+ }
+ REG_WR(bp, GRCBASE_QM, QM_REGISTERS_CONNNUM_0, 1024/16 - 1);
+
+ } else {
+ for (i = 0; i < 32; i++) {
+ REG_WR(bp, GRCBASE_QM,
+ QM_REGISTERS_BASEADDR + 4*(32 + i),
+ 1024 * 4 * i);
+#ifdef USE_DMAE
+ REG_WR_DMAE(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + (i + 32)*8,
+ wb_write, 2);
+#else
+ REG_WR_IND(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + (i + 32)*8, 0);
+ REG_WR_IND(bp, GRCBASE_QM,
+ QM_REGISTERS_PTRTBL + (i + 32)*8 + 4, 0);
+#endif
+ }
+ REG_WR(bp, GRCBASE_QM, QM_REGISTERS_CONNNUM_1, 1024/16 - 1);
+ }
+
+ bnx2x_init_stage(bp, BLCNUM_QM, port);
+
+#ifdef BCM_ISCSI
+ REG_WR(bp, GRCBASE_TIMERS,
+ TM_REGISTERS_LIN0_SCAN_TIME + 4*func, 1024/64*20);
+
+ REG_WR(bp, GRCBASE_TIMERS,
+ TM_REGISTERS_LIN0_MAX_ACTIVE_CID + 4*func, 31);
+ bnx2x_init_stage(bp, BLCNUM_TIMERS, port);
+#endif
+ bnx2x_init_stage(bp, BLCNUM_DQ, port);
+ bnx2x_init_stage(bp, BLCNUM_BRB1, port);
+ bnx2x_init_stage(bp, BLCNUM_PRS, port);
+ bnx2x_init_stage(bp, BLCNUM_TSDM, port);
+ bnx2x_init_stage(bp, BLCNUM_CSDM, port);
+ bnx2x_init_stage(bp, BLCNUM_USDM, port);
+ bnx2x_init_stage(bp, BLCNUM_XSDM, port);
+ bnx2x_init_stage(bp, BLCNUM_TSEM, port);
+ bnx2x_init_stage(bp, BLCNUM_USEM, port);
+ bnx2x_init_stage(bp, BLCNUM_CSEM, port);
+ bnx2x_init_stage(bp, BLCNUM_XSEM, port);
+ bnx2x_init_stage(bp, BLCNUM_UPB, port);
+ bnx2x_init_stage(bp, BLCNUM_XPB, port);
+ bnx2x_init_stage(bp, BLCNUM_PBF, port);
+
+ /* configure PBF to work without PAUSE mtu 9000 */
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_P0_PAUSE_ENABLE + 4*func, 0);
+
+ /* update threshold */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_ARB_THRSH + 4*func, (9040/16));
+ /* update init credit */
+ REG_WR(bp, GRCBASE_PBF,
+ PBF_REGISTERS_P0_INIT_CRD + 4*func, (9040/16) + 553 - 22);
+
+ /* probe changes */
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_INIT_P0 + 4*func, 1);
+ msleep(5);
+ REG_WR(bp, GRCBASE_PBF, PBF_REGISTERS_INIT_P0 + 4*func, 0);
+
+#ifdef BCM_ISCSI
+ /* tell the searcher where the T2 table is */
+ REG_WR(bp, GRCBASE_SRCH,
+ SRC_REGISTERS_COUNTFREE0 + 4*func, 16*1024/64);
+
+ wb_write[0] = U64_LO(bp->t2_mapping);
+ wb_write[1] = U64_HI(bp->t2_mapping);
+ REG_WR_DMAE(bp, GRCBASE_SRCH,
+ SRC_REGISTERS_FIRSTFREE0 + 4*func, wb_write, 2);
+ wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
+ wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
+ REG_WR_DMAE(bp, GRCBASE_SRCH,
+ SRC_REGISTERS_LASTFREE0 + 4*func, wb_write, 2);
+
+ REG_WR(bp, GRCBASE_SRCH,
+ SRC_REGISTERS_NUMBER_HASH_BITS0 + 4*func, 10);
+ bnx2x_init_stage(bp, BLCNUM_SRCH, port);
+#endif
+ bnx2x_init_stage(bp, BLCNUM_CDU, port);
+ bnx2x_init_stage(bp, BLCNUM_CFC, port);
+ bnx2x_init_stage(bp, BLCNUM_HC, port);
+ bnx2x_init_stage(bp, BLCNUM_MISC_AEU, port);
+ bnx2x_init_stage(bp, BLCNUM_PXPCS, port);
+ bnx2x_init_stage(bp, BLCNUM_EMAC0, port);
+ bnx2x_init_stage(bp, BLCNUM_EMAC1, port);
+ bnx2x_init_stage(bp, BLCNUM_DBU, port);
+ bnx2x_init_stage(bp, BLCNUM_DBG, port);
+ bnx2x_init_stage(bp, BLCNUM_NIG, port);
+ REG_WR(bp, GRCBASE_NIG,
+ NIG_REGISTERS_XGXS_SERDES0_MODE_SEL + 4*func, 1);
+ bnx2x_init_stage(bp, BLCNUM_MCP, port);
+ bnx2x_init_stage(bp, BLCNUM_DMAE, port);
+
+ bnx2x_link_reset(bp);
+
+ /* Reset pciex errors for debug */
+ REG_WR(bp, GRCBASE_PXPCS, 0x2114, 0xffffffff);
+ REG_WR(bp, GRCBASE_PXPCS, 0x2120, 0xffffffff);
+ REG_WR(bp, GRCBASE_PXPCS, 0x2814, 0xffffffff);
+
+ bnx2x_gunzip_end(bp);
+
+ if (!nomcp) {
+ port = bp->port;
+
+ bp->fw_drv_pulse_wr_seq =
+ (SHMEM_RD(bp, drv_fw_mb[port].drv_pulse_mb) &
+ DRV_PULSE_SEQ_MASK);
+ bp->fw_mb = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_param);
+ DP(BNX2X_MSG_MCP, "drv_pulse 0x%x fw_mb 0x%x\n",
+ bp->fw_drv_pulse_wr_seq, bp->fw_mb);
+ } else {
+ bp->fw_mb = 0;
+ }
+
+ return 0;
+}
+
+static void bnx2x_fw_dump(struct bnx2x *bp)
+{
+ u32 mark, offset;
+ u32 data[9];
+ int word;
+
+ mark = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_SCRATCH + 0xf104);
+ printk(KERN_ERR PFX "begin fw dump (mark %x)\n", mark);
+
+ for (offset = 0xF108; offset <= 0xF900; offset += 0x8*4) {
+ for (word = 0; word < 8; word++) {
+ data[word] = htonl(REG_RD(bp, GRCBASE_MCP,
+ MCP_REG_MCPR_SCRATCH +
+ offset + 4*word));
+ }
+ data[8] = 0x0;
+ if (offset + 0x08000000 > mark) {
+ printk(KERN_ERR PFX "\n*****\n");
+ mark = UINT_MAX;
+ }
+ printk(KERN_ERR PFX "%s", (char *)data);
+ }
+ printk("\n" KERN_ERR PFX "end of fw dump\n");
+}
+
+/* send the MCP a request, block untill there is a reply */
+static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
+{
+ u32 rc = 0;
+ u32 seq = ++bp->fw_seq;
+ int port = bp->port;
+
+ SHMEM_WR(bp, drv_fw_mb[port].drv_mb_header, command|seq);
+ DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", command|seq);
+
+ /* let the FW do it's magic ... */
+ msleep(100); /* TBD */
+
+ if (CHIP_REV_IS_SLOW(bp)) {
+ msleep(900);
+ }
+
+ rc = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_header);
+
+ DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq);
+
+ /* is this a reply to our command? */
+ if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
+ rc &= FW_MSG_CODE_MASK;
+ } else {
+ /* FW BUG! */
+ BNX2X_ERR("FW failed to respond!\n");
+ bnx2x_fw_dump(bp);
+ rc = 0;
+ }
+ return rc;
+}
+
+static void bnx2x_free_mem(struct bnx2x *bp)
+{
+
+#define BNX2X_PCI_FREE(x, y, size) \
+ do { \
+ if (x) { \
+ pci_free_consistent(bp->pdev, size, x, y); \
+ x = NULL; \
+ y = 0; \
+ } \
+ } while (0)
+
+#define BNX2X_KFREE(x) \
+ do { \
+ if (x) { \
+ vfree(x); \
+ x = NULL; \
+ } \
+ } while (0)
+
+ int i;
+
+ /* fastpath */
+ for_each_queue(bp, i) {
+
+ /* Status blocks */
+ BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
+ bnx2x_fp(bp, i, status_blk_mapping),
+ sizeof(struct host_status_block) +
+ sizeof(struct eth_tx_db_data));
+
+ /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
+ BNX2X_KFREE(bnx2x_fp(bp, i, tx_buf_ring));
+ BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
+ bnx2x_fp(bp, i, tx_desc_mapping),
+ sizeof(struct eth_tx_bd) * NUM_TX_BD);
+
+ BNX2X_KFREE(bnx2x_fp(bp, i, rx_buf_ring));
+ BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
+ bnx2x_fp(bp, i, rx_desc_mapping),
+ sizeof(struct eth_rx_bd) * NUM_RX_BD);
+
+ BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
+ bnx2x_fp(bp, i, rx_comp_mapping),
+ sizeof(struct eth_rx_bd) * NUM_RX_BD);
+ }
+
+ /* BNX2X_KFREE(bp->fp); */
+ /* end of fastpath */
+
+ BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
+ (sizeof(struct host_def_status_block)));
+
+ BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
+ (sizeof(struct bnx2x_slowpath)));
+
+#ifdef BCM_ISCSI
+ BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
+ BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
+ BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
+ BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
+#endif
+ BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, PAGE_SIZE);
+
+#undef BNX2X_PCI_FREE
+#undef BNX2X_KFREE
+}
+
+static int bnx2x_alloc_mem(struct bnx2x *bp)
+{
+
+#define BNX2X_PCI_ALLOC(x, y, size) \
+ do { \
+ x = pci_alloc_consistent(bp->pdev, size, y); \
+ if (x == NULL) \
+ goto alloc_mem_err; \
+ memset(x, 0, size); \
+ } while (0)
+
+#define BNX2X_ALLOC(x, size) \
+ do { \
+ x = vmalloc(size); \
+ if (x == NULL) \
+ goto alloc_mem_err; \
+ memset(x, 0, size); \
+ } while (0)
+
+ int i;
+
+ /* fastpath */
+/* BNX2X_ALLOC(bp->fp, sizeof(struct bnx2x_fastpath) * bp->num_queues); */
+
+ for_each_queue(bp, i) {
+ bnx2x_fp(bp, i, bp) = bp;
+
+ /* Status blocks */
+ BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
+ &bnx2x_fp(bp, i, status_blk_mapping),
+ sizeof(struct host_status_block) +
+ sizeof(struct eth_tx_db_data));
+
+ bnx2x_fp(bp, i, hw_tx_prods) =
+ (void *)(bnx2x_fp(bp, i, status_blk) + 1);
+
+ bnx2x_fp(bp, i, tx_prods_mapping) =
+ bnx2x_fp(bp, i, status_blk_mapping) +
+ sizeof(struct host_status_block);
+
+ /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
+ BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
+ sizeof(struct sw_tx_bd) * NUM_TX_BD);
+ BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
+ &bnx2x_fp(bp, i, tx_desc_mapping),
+ sizeof(struct eth_tx_bd) * NUM_TX_BD);
+
+ BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
+ sizeof(struct sw_rx_bd) * NUM_RX_BD);
+ BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
+ &bnx2x_fp(bp, i, rx_desc_mapping),
+ sizeof(struct eth_rx_bd) * NUM_RX_BD);
+
+ BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
+ &bnx2x_fp(bp, i, rx_comp_mapping),
+ sizeof(struct eth_rx_bd) * NUM_RX_BD);
+ }
+ /* end of fastpath */
+
+ BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
+ sizeof(struct host_def_status_block));
+
+ BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
+ sizeof(struct bnx2x_slowpath));
+
+#ifdef BCM_ISCSI
+ BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
+
+ /* Initialize T1 */
+ for (i = 0; i < 64*1024; i += 64) {
+ *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
+ *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
+ }
+
+ /* allocate searcher T2 table
+ we allocate 1/4 of alloc num for T2
+ (which is not entered into the ILT) */
+ BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
+
+ /* Initialize T2 */
+ for (i = 0; i < 16*1024; i += 64) {
+ *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
+ }
+
+ /* now sixup the last line in the block to point to the next block */
+ *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
+
+ /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
+ BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
+
+ /* QM queues (128*MAX_CONN) */
+ BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
+#endif
+
+ /* Slow path ring */
+ BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, PAGE_SIZE);
+
+ return 0;
+
+alloc_mem_err:
+ bnx2x_free_mem(bp);
+ return -ENOMEM;
+
+#undef BNX2X_PCI_ALLOC
+#undef BNX2X_ALLOC
+}
+
+static void bnx2x_free_tx_skbs(struct bnx2x *bp)
+{
+ int i;
+
+ for_each_queue(bp, i) {
+ struct bnx2x_fastpath *fp = &bp->fp[i];
+
+ u16 bd_cons = fp->tx_bd_cons;
+ u16 sw_prod = fp->tx_pkt_prod;
+ u16 sw_cons = fp->tx_pkt_cons;
+
+ BUG_TRAP(fp->tx_buf_ring != NULL);
+
+ while (sw_cons != sw_prod) {
+ bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
+ sw_cons++;
+ }
+ }
+}
+
+static void bnx2x_free_rx_skbs(struct bnx2x *bp)
+{
+ int i, j;
+
+ for_each_queue(bp, j) {
+ struct bnx2x_fastpath *fp = &bp->fp[j];
+
+ BUG_TRAP(fp->rx_buf_ring != NULL);
+
+ for (i = 0; i < NUM_RX_BD; i++) {
+ struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
+ struct sk_buff *skb = rx_buf->skb;
+
+ if (skb == NULL)
+ continue;
+
+ pci_unmap_single(bp->pdev,
+ pci_unmap_addr(rx_buf, mapping),
+ bp->rx_buf_use_size,
+ PCI_DMA_FROMDEVICE);
+
+ rx_buf->skb = NULL;
+
+ dev_kfree_skb(skb);
+ }
+ }
+}
+
+static void bnx2x_free_skbs(struct bnx2x *bp)
+{
+ bnx2x_free_tx_skbs(bp);
+ bnx2x_free_rx_skbs(bp);
+}
+
+static void bnx2x_free_irq(struct bnx2x *bp)
+{
+ int i;
+
+ if (bp->flags & USING_MSIX_FLAG) {
+
+ free_irq(bp->msix_table[0].vector, bp->dev);
+ DP(NETIF_MSG_IFDOWN, "rleased sp irq (%d)\n",
+ bp->msix_table[0].vector);
+
+ for_each_queue(bp, i) {
+ DP(NETIF_MSG_IFDOWN,
+ "about to rlease fp #%d->%d irq state(%x)\n", i,
+ bp->msix_table[i + 1].vector,
+ bnx2x_fp(bp, i, state));
+
+ if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) {
+ free_irq(bp->msix_table[i + 1].vector,
+ &bp->fp[i]);
+ bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_CLOSED;
+
+ } else {
+ DP(NETIF_MSG_IFDOWN, "irq not freed\n");
+ }
+ }
+ pci_disable_msix(bp->pdev);
+ bp->flags &= ~USING_MSIX_FLAG;
+
+ } else {
+ free_irq(bp->pdev->irq, bp->dev);
+ }
+}
+
+static int bnx2x_req_irq(struct bnx2x *bp)
+{
+ int i, rc;
+
+ if (!use_inta) {
+ bp->msix_table[0].entry = 0;
+ for_each_queue(bp, i) {
+ bp->msix_table[i + 1].entry = i + 1;
+ }
+
+ if ((rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
+ bp->num_queues + 1)) == 0) {
+
+ bp->flags |= USING_MSIX_FLAG;
+
+ DP(NETIF_MSG_IFUP, "about to request sp irq\n");
+
+ rc = request_irq(bp->msix_table[0].vector,
+ bnx2x_msix_sp_int, 0,
+ bp->dev->name, bp->dev);
+ DP(NETIF_MSG_IFUP, "returned %d\n", rc);
+ if (rc) {
+ return -1;
+ }
+
+ for_each_queue(bp, i) {
+ DP(NETIF_MSG_IFUP,
+ "about to request fp irq#%d\n", i);
+
+ rc = request_irq(bp->msix_table[i + 1].vector,
+ bnx2x_msix_fp_int, 0,
+ bp->dev->name, &bp->fp[i]);
+ DP(NETIF_MSG_IFUP, "returned %d\n", rc);
+ if (rc) {
+ goto out_irq;
+ }
+ bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
+ }
+ }
+ }
+ if (!(bp->flags & USING_MSIX_FLAG)) {
+ rc = request_irq(bp->pdev->irq, bnx2x_interrupt,
+ IRQF_SHARED, bp->dev->name, bp->dev);
+ if (rc) {
+ return -1;
+ }
+ bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
+ }
+
+ return 0;
+
+out_irq:
+ if (bp->flags & USING_MSIX_FLAG) {
+
+ for_each_queue(bp, i) {
+ DP(NETIF_MSG_IFUP,
+ "failed to load. about to rlease irq#%d\n", i);
+
+ if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) {
+ free_irq(bp->msix_table[i + 1].vector,
+ &bp->fp[i]);
+ bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_CLOSED;
+ DP(NETIF_MSG_IFUP, "rleased irq#%d\n", i);
+ }
+ }
+ free_irq(bp->msix_table[0].vector, bp->dev);
+ pci_disable_msix(bp->pdev);
+ bp->flags &= ~USING_MSIX_FLAG;
+
+ } else {
+ free_irq(bp->pdev->irq, bp->dev);
+ }
+
+ return -1;
+}
+
+/****************************************************************************
+* Init service functions
+****************************************************************************/
+
+static void bnx2x_set_mac_addr(struct bnx2x *bp)
+{
+ struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
+
+ /* CAM allocation
+ * unicasts 0-31:port0 32-63:port1
+ * multicast 64-127:port0 128-191:port1
+ */
+ config->hdr.length_6b = 2;
+ config->hdr.offset = bp->port ? 31 : 0;
+ config->hdr.reserved0 = 0;
+ config->hdr.reserved1 = 0;
+
+ /* primary MAC */
+ config->config_table[0].cam_entry.msb_mac_addr =
+ be16_to_cpu(*(u16 *)&bp->dev->dev_addr[0]);
+ config->config_table[0].cam_entry.middle_mac_addr =
+ be16_to_cpu(*(u16 *)&bp->dev->dev_addr[2]);
+ config->config_table[0].cam_entry.lsb_mac_addr =
+ be16_to_cpu(*(u16 *)&bp->dev->dev_addr[4]);
+ config->config_table[0].cam_entry.flags = bp->port;
+ config->config_table[0].target_table_entry.flags = 0;
+ config->config_table[0].target_table_entry.client_id = 0;
+ config->config_table[0].target_table_entry.vlan_id = 0;
+ DP(NETIF_MSG_RX_STATUS, "setting MAC (%04x:%04x:%04x)\n",
+ config->config_table[0].cam_entry.msb_mac_addr,
+ config->config_table[0].cam_entry.middle_mac_addr,
+ config->config_table[0].cam_entry.lsb_mac_addr);
+
+ /* broadcast */
+ config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
+ config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
+ config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
+ config->config_table[1].cam_entry.flags = bp->port;
+ config->config_table[1].target_table_entry.flags =
+ TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
+ config->config_table[1].target_table_entry.client_id = 0;
+ config->config_table[1].target_table_entry.vlan_id = 0;
+
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+ U64_HI(bnx2x_sp_mapping(bp, mac_config)),
+ U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+}
+
+/* state_p is a pointer to state field, which is checked for a change */
+static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
+ int *state_p, int poll)
+{
+ int i = 0;
+
+ /* DP("waiting for state to become %d on IDX [%d]\n",
+ state, sb_idx); */
+
+ while (*state_p != state) {
+
+ msleep(1);
+
+ if (poll) {
+ /* Get ramrod "send" completion (will only update producer) */
+ bnx2x_rx_int(bp->fp, 10);
+ /* If index is different from 0 -
+ * call for interrupt handling routine for the
+ * appropriate queue to get the ramrod completion */
+ }
+ if (i++ == 5000) {
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static void bnx2x_set_rx_mode(struct net_device *dev);
+
+static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
+{
+ int rc;
+ int i = 0;
+
+ bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
+
+ /* Send LOAD_REQUEST command to MCP.
+ Returns the type of LOAD command: if it is the
+ first port to be initialized common blocks should be
+ initialized, otherwise - not.
+ */
+ if (!nomcp) {
+ rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
+ if (rc == FW_MSG_CODE_DRV_LOAD_REFUSED) {
+ return -EBUSY; /* other port in diagnostic mode */
+ }
+ } else {
+ rc = FW_MSG_CODE_DRV_LOAD_COMMON;
+ }
+
+ bp->num_queues = 1;
+
+ /* Allocate driver's memories */
+ if (bnx2x_alloc_mem(bp))
+ return -ENOMEM;
+
+ /* Initialize the appropriate blocks */
+ if (bnx2x_function_init(bp, (rc == FW_MSG_CODE_DRV_LOAD_COMMON))) {
+ BNX2X_ERR("HW init failed, aborting\n");
+ goto out_error;
+ }
+
+ /* Request IRQ if needed */
+ if (req_irq) {
+ rc = bnx2x_req_irq(bp);
+ if (rc) {
+ goto out_error;
+ }
+ }
+
+ atomic_set(&bp->intr_sem, 0);
+
+ /* Reenable SP tasklet */
+ if (bp->sp_task_en) {
+ tasklet_enable(&bp->sp_task);
+ } else {
+ bp->sp_task_en = 1;
+ }
+
+ /* Setup NIC internals */
+ rc = bnx2x_nic_init(bp); /* also enables interrupts */
+ if (rc) {
+ goto out_skbs;
+ }
+
+ /* Send LOAD_DONE command to MCP */
+ if (!nomcp) {
+ rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
+ DP(NETIF_MSG_IFUP, "rc = 0x%x\n", rc);
+ if (!rc) {
+ goto int_disable;
+ }
+ }
+
+ bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
+
+ /* Enable Rx interrupt handling before sending the ramrod
+ as it's completed on Rx FP queue */
+ napi_enable(&bnx2x_fp(bp, 0, napi));
+
+ /* On default status block */
+ bnx2x_ack_sb(bp, 16, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+ /* On FP */
+ for_each_queue(bp, i)
+ bnx2x_ack_sb(bp, i, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+
+ /* SETUP ramrod */
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
+ /* Wait for completion */
+ rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
+ if (rc) {
+ goto stop_netif;
+ }
+
+ /* Configure CAM */
+ bnx2x_set_mac_addr(bp);
+
+ bnx2x_phy_init(bp);
+
+ /* Start fast path */
+ if (req_irq) { /* IRQ is only requested from bnx2x_open function
+ when Tx queue is initialized for the first time */
+ netif_start_queue(bp->dev);
+ if (bp->flags & USING_MSIX_FLAG) {
+ printk(KERN_INFO PFX "%s: using MSI-X\n",
+ bp->dev->name);
+ }
+
+ /* Otherwise Tx queue should be only reenabled */
+ } else if (netif_running(bp->dev)) {
+ netif_wake_queue(bp->dev);
+ bnx2x_set_rx_mode(bp->dev);
+ }
+
+ /* start the timer */
+ mod_timer(&bp->timer, jiffies + bp->current_interval);
+
+ return 0;
+
+stop_netif:
+ napi_disable(&bnx2x_fp(bp, 0, napi));
+int_disable:
+ bnx2x_disable_int_sync(bp);
+out_skbs:
+ bnx2x_free_skbs(bp);
+ bnx2x_free_irq(bp);
+
+out_error:
+ bnx2x_free_mem(bp);
+
+ /* TBD we really need to reset the chip
+ if we want to recover from this */
+ return rc;
+}
+
+static void bnx2x_netif_stop(struct bnx2x *bp)
+{
+ bp->rx_mode = BNX2X_RX_MODE_NONE;
+ bnx2x_set_storm_rx_mode(bp);
+
+ bnx2x_disable_int_sync(bp);
+ bnx2x_link_reset(bp);
+ napi_disable(&bnx2x_fp(bp, 0, napi));
+ if (netif_running(bp->dev)) {
+ netif_tx_disable(bp->dev);
+ bp->dev->trans_start = jiffies; /* prevent tx timeout */
+ }
+}
+
+static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
+{
+ int port = bp->port;
+
+ DP(NETIF_MSG_IFDOWN, "reset called with code %x\n", reset_code);
+
+ /* Do not rcv packets to BRB */
+ REG_WR(bp, GRCBASE_NIG,
+ NIG_REGISTERS_LLH0_BRB1_DRV_MASK + port*4, 0x0);
+ /* Do not direct rcv packets that are not for MCP to the BRB */
+ REG_WR(bp, GRCBASE_NIG,
+ (port ? NIG_REGISTERS_LLH1_BRB1_NOT_MCP :
+ NIG_REGISTERS_LLH0_BRB1_NOT_MCP), 0x0);
+
+ /* Configure IGU and AEU */
+ REG_WR(bp, GRCBASE_HC, HC_REGISTERS_CONFIG_0 + (port*4), 0x1000);
+ REG_WR(bp, GRCBASE_MISC_AEU,
+ MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0 + (port*4), 0);
+
+ /* TODO Close Doorbells port */
+
+ if (reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
+ /* reset_common */
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_RESET_REG_1_CLEAR, 0xd3ffff7f);
+ REG_WR(bp, GRCBASE_MISC,
+ MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
+ }
+}
+
+static int bnx2x_nic_unload(struct bnx2x *bp, int fre_irq)
+{
+ u32 reset_code = 0;
+ int rc;
+
+ bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
+
+ /* Calling flush_scheduled_work() may deadlock because
+ * linkwatch_event() may be on the workqueue and it will try to get
+ * the rtnl_lock which we are holding.
+ */
+ while (bp->in_reset_task)
+ msleep(1);
+
+ /* Delete the timer: do it before disabling interrupts, as it
+ may be stil STAT_QUERY ramrod pending after stopping the timer */
+ del_timer_sync(&bp->timer);
+
+ /* Wait until stat ramrod returns and all SP tasks complete */
+ while (bp->stat_pending && (bp->spq_left != MAX_SPQ_PENDING)) {
+ msleep(1);
+ }
+
+ /* Stop fast path, disable MAC, disable interrupts
+ This does napi_disable() for us. */
+ bnx2x_netif_stop(bp);
+
+ if (bp->flags & NO_WOL_FLAG)
+ reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
+ else if (bp->wol) {
+ u32 emac_base = bp->port ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
+ u8 *mac_addr = bp->dev->dev_addr;
+ u32 val = (EMAC_MODE_MPKT | EMAC_MODE_MPKT_RCVD |
+ EMAC_MODE_ACPI_RCVD);
+
+ REG_WR(bp, emac_base, EMAC_REG_EMAC_MODE, val);
+
+ val = (mac_addr[0] << 8) | mac_addr[1];
+
+ REG_WR(bp, emac_base, EMAC_REG_EMAC_MAC_MATCH, val);
+
+ val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
+ (mac_addr[4] << 8) | mac_addr[5];
+
+ REG_WR(bp, emac_base, EMAC_REG_EMAC_MAC_MATCH + 4, val);
+
+ reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
+ } else
+ reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
+
+
+ /* Send HALT ramrod */
+ bp->fp[0].state = BNX2X_FP_STATE_HALTING;
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, 0, 0);
+ /* Wait for completion */
+ rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
+ &(bp->fp[0].state), 1);
+ if (rc) {
+ goto error;
+ }
+
+ /* Remember cstorm producer in DSB to track it */
+ bp->dsb_sp_prod_idx = *bp->dsb_sp_prod;
+ /* Send CFC_DELETE ramrod */
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
+ /* Wait for completion to arrive. Do nothing as we are going to reset
+ the chip a few lines later */
+ while (bp->dsb_sp_prod_idx == *bp->dsb_sp_prod) {
+ msleep(1);
+ }
+
+error:
+ if (!nomcp) {
+ rc = bnx2x_fw_command(bp, reset_code);
+ } else {
+ rc = FW_MSG_CODE_DRV_UNLOAD_COMMON;
+ }
+
+ /* Release IRQs */
+ if (fre_irq)
+ bnx2x_free_irq(bp);
+
+ /* Reset the chip */
+ bnx2x_reset_chip(bp, rc);
+
+ /* Report UNLOAD_DONE to MCP */
+ if (!nomcp) {
+ bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
+ }
+ /* Free SKBs and driver internals */
+ bnx2x_free_skbs(bp);
+ bnx2x_free_mem(bp);
+
+ bp->state = BNX2X_STATE_CLOSED;
+ /* Set link down */
+ bp->link_up = 0;
+ netif_carrier_off(bp->dev);
+
+ return 0;
+}
+
+/* end of nic load/unload */
+
+/* ethtool_ops */
+
+/****************************************************************************
+* Init service functions
+****************************************************************************/
+
+static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
+{
+ int port = bp->port;
+ u32 ext_phy_type;
+
+ bp->phy_flags = 0;
+ bp->supported = (SUPPORTED_Autoneg |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause);
+
+ switch (switch_cfg) {
+ case SWITCH_CFG_1G:
+ BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
+
+ ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
+ BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
+ ext_phy_type);
+
+ bp->supported |= (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_2500baseT_Full |
+ SUPPORTED_TP | SUPPORTED_FIBRE);
+ break;
+
+ case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
+ BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
+ ext_phy_type);
+
+ bp->phy_flags |= PHY_SGMII_FLAG;
+
+ bp->supported |= (/* SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |*/
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_TP | SUPPORTED_FIBRE);
+ break;
+
+ default:
+ BNX2X_ERR("NVRAM config error. "
+ "BAD SerDes ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ return;
+ }
+
+ bp->phy_addr = REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_SERDES0_CTRL_PHY_ADDR +
+ port*0x10);
+ BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
+ break;
+
+ case SWITCH_CFG_10G:
+ BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
+
+ bp->phy_flags |= PHY_XGXS_FLAG;
+
+ ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
+ switch (ext_phy_type) {
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
+ BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
+ ext_phy_type);
+
+ bp->supported |= (SUPPORTED_10baseT_Half |
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_2500baseT_Full |
+ SUPPORTED_10000baseT_Full |
+ SUPPORTED_TP | SUPPORTED_FIBRE);
+ break;
+
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
+ case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
+ BNX2X_DEV_INFO("ext_phy_type 0x%x (8705/6)\n",
+ ext_phy_type);
+
+ bp->supported |= (SUPPORTED_10000baseT_Full |
+ SUPPORTED_FIBRE);
+ break;
+
+ default:
+ BNX2X_ERR("NVRAM config error. "
+ "BAD XGXS ext_phy_config 0x%x\n",
+ bp->ext_phy_config);
+ return;
+ }
+
+ bp->phy_addr = REG_RD(bp, GRCBASE_NIG,
+ NIG_REGISTERS_XGXS0_CTRL_PHY_ADDR +
+ port*0x18);
+ BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
+
+ bp->ser_lane = ((bp->lane_config &
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
+ bp->rx_lane_swap = ((bp->lane_config &
+ PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
+ bp->tx_lane_swap = ((bp->lane_config &
+ PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
+ PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
+ BNX2X_DEV_INFO("rx_lane_swap 0x%x tx_lane_swap 0x%x\n",
+ bp->rx_lane_swap, bp->tx_lane_swap);
+ break;
+
+ default:
+ BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
+ bp->link_config);
+ return;
+ }
+
+ /* mask what we support according to speed_cap_mask */
+ if (!(bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
+ bp->supported &= ~SUPPORTED_10baseT_Half;
+ }
+ if (!(bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
+ bp->supported &= ~SUPPORTED_10baseT_Full;
+ }
+ if (!(bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
+ bp->supported &= ~SUPPORTED_100baseT_Half;
+ }
+ if (!(bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
+ bp->supported &= ~SUPPORTED_100baseT_Full;
+ }
+ if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
+ bp->supported &= ~(SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full);
+ }
+ if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
+ bp->supported &= ~SUPPORTED_2500baseT_Full;
+ }
+ if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
+ bp->supported &= ~SUPPORTED_10000baseT_Full;
+ }
+ BNX2X_DEV_INFO("supported 0x%x\n", bp->supported);
+}
+
+static void bnx2x_link_settings_requested(struct bnx2x *bp)
+{
+ bp->req_autoneg = 0;
+ bp->req_duplex = DUPLEX_FULL;
+ switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) {
+ case PORT_FEATURE_LINK_SPEED_AUTO:
+ bp->req_autoneg |= AUTONEG_SPEED;
+ bp->req_line_speed = 0;
+ bp->advertising = bp->supported;
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_10M_FULL:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
+ bp->req_line_speed = SPEED_10;
+ bp->advertising = (ADVERTISED_10baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_10M_HALF:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
+ bp->req_line_speed = SPEED_10;
+ bp->req_duplex = DUPLEX_HALF;
+ bp->advertising = (ADVERTISED_10baseT_Half |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_100M_FULL:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
+ bp->req_line_speed = SPEED_100;
+ bp->advertising = (ADVERTISED_100baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_100M_HALF:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
+ bp->req_line_speed = SPEED_100;
+ bp->req_duplex = DUPLEX_HALF;
+ bp->advertising = (ADVERTISED_100baseT_Half |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_1G:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
+ bp->req_line_speed = SPEED_1000;
+ bp->advertising = (ADVERTISED_1000baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_2_5G:
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) {
+ bp->req_line_speed = SPEED_2500;
+ bp->advertising = (ADVERTISED_2500baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ case PORT_FEATURE_LINK_SPEED_10G_CX4:
+ case PORT_FEATURE_LINK_SPEED_10G_KX4:
+ case PORT_FEATURE_LINK_SPEED_10G_KR:
+ if (!(bp->phy_flags & PHY_XGXS_FLAG)) {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " phy_flags 0x%x\n",
+ bp->link_config, bp->phy_flags);
+ return;
+ }
+ if (bp->speed_cap_mask &
+ PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
+ bp->req_line_speed = SPEED_10000;
+ bp->advertising = (ADVERTISED_10000baseT_Full |
+ ADVERTISED_FIBRE);
+ } else {
+ BNX2X_ERR("NVRAM config error. "
+ "Invalid link_config 0x%x"
+ " speed_cap_mask 0x%x\n",
+ bp->link_config, bp->speed_cap_mask);
+ return;
+ }
+ break;
+
+ default:
+ BNX2X_ERR("NVRAM config error. "
+ "BAD link speed link_config 0x%x\n",
+ bp->link_config);
+ bp->req_autoneg |= AUTONEG_SPEED;
+ bp->req_line_speed = 0;
+ bp->advertising = bp->supported;
+ break;
+ }
+ BNX2X_DEV_INFO("req_line_speed %d req_duplex %d\n",
+ bp->req_line_speed, bp->req_duplex);
+
+ bp->req_flow_ctrl = (bp->link_config &
+ PORT_FEATURE_FLOW_CONTROL_MASK);
+ /* Please refer to Table 28B-3 of the 802.3ab-1999 spec */
+ switch (bp->req_flow_ctrl) {
+ case FLOW_CTRL_AUTO:
+ bp->req_autoneg |= AUTONEG_FLOW_CTRL;
+ bp->pause_mode = PAUSE_BOTH;
+ bp->advertising |= (ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+ break;
+
+ case FLOW_CTRL_TX:
+ bp->pause_mode = PAUSE_ASYMMETRIC;
+ bp->advertising |= ADVERTISED_Asym_Pause;
+ break;
+
+ case FLOW_CTRL_RX:
+ bp->pause_mode = PAUSE_BOTH;
+ bp->advertising |= (ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+ break;
+
+ case FLOW_CTRL_BOTH:
+ bp->pause_mode = PAUSE_SYMMETRIC;
+ bp->advertising |= ADVERTISED_Pause;
+ break;
+
+ case FLOW_CTRL_NONE:
+ default:
+ bp->pause_mode = PAUSE_NONE;
+ bp->advertising &= ~(ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+ break;
+ }
+ BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x\n"
+ KERN_INFO " pause_mode %d advertising 0x%x\n",
+ bp->req_autoneg, bp->req_flow_ctrl,
+ bp->pause_mode, bp->advertising);
+}
+
+static void bnx2x_get_hwinfo(struct bnx2x *bp)
+{
+ u32 val, val2, val3, val4, id;
+ int port = bp->port;
+ u32 switch_cfg;
+
+ bp->shmem_base = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_SHARED_MEM_ADDR);
+ BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base);
+
+ /* Get the chip revision id and number. */
+ /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_CHIP_NUM);
+ id = ((val & 0xffff) << 16);
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_CHIP_REV);
+ id |= ((val & 0xf) << 12);
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_CHIP_METAL);
+ id |= ((val & 0xff) << 4);
+ REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_BOND_ID);
+ id |= (val & 0xf);
+ bp->chip_id = id;
+ BNX2X_DEV_INFO("chip ID is %x\n", id);
+
+ if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) {
+ BNX2X_DEV_INFO("MCP not active\n");
+ nomcp = 1;
+ goto set_mac;
+ }
+
+ val = SHMEM_RD(bp, validity_map[port]);
+ if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
+ != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
+ BNX2X_ERR("MCP validity signature bad\n");
+ }
+
+ bp->fw_seq = (SHMEM_RD(bp, drv_fw_mb[port].drv_mb_header) &
+ DRV_MSG_SEQ_NUMBER_MASK);
+
+ bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
+
+ bp->serdes_config =
+ SHMEM_RD(bp, dev_info.port_hw_config[bp->port].serdes_config);
+ bp->lane_config =
+ SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
+ bp->ext_phy_config =
+ SHMEM_RD(bp,
+ dev_info.port_hw_config[port].external_phy_config);
+ bp->speed_cap_mask =
+ SHMEM_RD(bp,
+ dev_info.port_hw_config[port].speed_capability_mask);
+
+ bp->link_config =
+ SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
+
+ BNX2X_DEV_INFO("hw_config (%08x) serdes_config (%08x)\n"
+ KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n"
+ KERN_INFO " speed_cap_mask (%08x) link_config (%08x)"
+ " fw_seq (%08x)\n",
+ bp->hw_config, bp->serdes_config, bp->lane_config,
+ bp->ext_phy_config, bp->speed_cap_mask,
+ bp->link_config, bp->fw_seq);
+
+ switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK);
+ bnx2x_link_settings_supported(bp, switch_cfg);
+
+ bp->autoneg = (bp->hw_config & SHARED_HW_CFG_AN_ENABLE_MASK);
+ /* for now disable cl73 */
+ bp->autoneg &= ~SHARED_HW_CFG_AN_ENABLE_CL73;
+ BNX2X_DEV_INFO("autoneg 0x%x\n", bp->autoneg);
+
+ bnx2x_link_settings_requested(bp);
+
+ val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
+ val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
+ bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
+ bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
+ bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
+ bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
+ bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
+ bp->dev->dev_addr[5] = (u8)(val & 0xff);
+ memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
+
+ val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
+ val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
+ val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
+ val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
+
+ printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
+ val, val2, val3, val4);
+
+ /* bc ver */
+ if (!nomcp) {
+ bp->bc_ver = val = ((SHMEM_RD(bp, dev_info.bc_rev)) >> 8);
+ BNX2X_DEV_INFO("bc_ver %X\n", val);
+ if (val < BNX2X_BC_VER) {
+ /* for now only warn
+ * later we might need to enforce this */
+ BNX2X_ERR("This driver needs bc_ver %X but found %X,"
+ " please upgrade BC\n", BNX2X_BC_VER, val);
+ }
+ } else {
+ bp->bc_ver = 0;
+ }
+
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_CFG4);
+ bp->flash_size = (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
+ BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
+ bp->flash_size, bp->flash_size);
+
+ return;
+
+set_mac: /* only supposed to happen on emulation/FPGA */
+ BNX2X_ERR("warning constant MAC workaround active\n");
+ bp->dev->dev_addr[0] = 0;
+ bp->dev->dev_addr[1] = 0x50;
+ bp->dev->dev_addr[2] = 0xc2;
+ bp->dev->dev_addr[3] = 0x2c;
+ bp->dev->dev_addr[4] = 0x71;
+ bp->dev->dev_addr[5] = port? 0x0d:0x0e;
+
+ memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
+}
+
+
+/****************************************************************************
+* ethtool service functions
+****************************************************************************/
+/* All ethtool functions called with rtnl_lock */
+
+static int bnx2x_get_settings(struct net_device *dev, struct
ethtool_cmd *cmd)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ cmd->supported = bp->supported;
+ cmd->advertising = bp->advertising;
+
+ if (netif_carrier_ok(dev)) {
+ cmd->speed = bp->line_speed;
+ cmd->duplex = bp->duplex;
+ } else {
+ cmd->speed = bp->req_line_speed;
+ cmd->duplex = bp->req_duplex;
+ }
+
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ cmd->port = PORT_FIBRE;
+ } else {
+ cmd->port = PORT_TP;
+ }
+
+ cmd->phy_address = bp->phy_addr;
+ cmd->transceiver = XCVR_INTERNAL;
+
+ if (bp->req_autoneg & AUTONEG_SPEED) {
+ cmd->autoneg = AUTONEG_ENABLE;
+ } else {
+ cmd->autoneg = AUTONEG_DISABLE;
+ }
+
+ DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
+ DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
+ DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
+ DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
+ cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
+ cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
+ cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
+
+ return 0;
+}
+
+static int bnx2x_set_settings(struct net_device *dev, struct
ethtool_cmd *cmd)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ u32 advertising;
+
+ DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
+ DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
+ DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
+ DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
+ cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
+ cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
+ cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
+
+ switch (cmd->port) {
+ case PORT_TP:
+ if (!(bp->supported & SUPPORTED_TP)) {
+ return -EINVAL;
+ }
+ if (bp->phy_flags & PHY_XGXS_FLAG) {
+ bnx2x_link_reset(bp);
+ bnx2x_link_settings_supported(bp, SWITCH_CFG_1G);
+ bnx2x_phy_deassert(bp);
+ }
+ break;
+
+ case PORT_FIBRE:
+ if (!(bp->supported & SUPPORTED_FIBRE)) {
+ return -EINVAL;
+ }
+ if (!(bp->phy_flags & PHY_XGXS_FLAG)) {
+ bnx2x_link_reset(bp);
+ bnx2x_link_settings_supported(bp, SWITCH_CFG_10G);
+ bnx2x_phy_deassert(bp);
+ }
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (cmd->autoneg == AUTONEG_ENABLE) {
+ /* advertise the requested speed and duplex if supported */
+ cmd->advertising &= bp->supported;
+
+ bp->req_autoneg |= AUTONEG_SPEED;
+ bp->req_line_speed = 0;
+ bp->req_duplex = DUPLEX_FULL;
+ bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising);
+
+ } else { /* forced mode */
+ /* advertise the requested speed and duplex if supported */
+ switch (cmd->speed) {
+ case SPEED_10:
+ if (cmd->duplex == DUPLEX_FULL) {
+ if (!(bp->supported &
+ SUPPORTED_10baseT_Full)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_10baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ if (!(bp->supported &
+ SUPPORTED_10baseT_Half)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_10baseT_Half |
+ ADVERTISED_TP);
+ }
+ break;
+
+ case SPEED_100:
+ if (cmd->duplex == DUPLEX_FULL) {
+ if (!(bp->supported &
+ SUPPORTED_100baseT_Full)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_100baseT_Full |
+ ADVERTISED_TP);
+ } else {
+ if (!(bp->supported &
+ SUPPORTED_100baseT_Half)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_100baseT_Half |
+ ADVERTISED_TP);
+ }
+ break;
+
+ case SPEED_1000:
+ if (cmd->duplex != DUPLEX_FULL) {
+ return -EINVAL;
+ }
+ if (!(bp->supported & SUPPORTED_1000baseT_Full)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_1000baseT_Full |
+ ADVERTISED_TP);
+ break;
+
+ case SPEED_2500:
+ if (cmd->duplex != DUPLEX_FULL) {
+ return -EINVAL;
+ }
+ if (!(bp->supported & SUPPORTED_2500baseT_Full)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_2500baseT_Full |
+ ADVERTISED_TP);
+ break;
+
+ case SPEED_10000:
+ if (cmd->duplex != DUPLEX_FULL) {
+ return -EINVAL;
+ }
+ if (!(bp->supported & SUPPORTED_10000baseT_Full)) {
+ return -EINVAL;
+ }
+ advertising = (ADVERTISED_10000baseT_Full |
+ ADVERTISED_FIBRE);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ bp->req_autoneg &= ~AUTONEG_SPEED;
+ bp->req_line_speed = cmd->speed;
+ bp->req_duplex = cmd->duplex;
+ bp->advertising = advertising;
+ }
+
+ DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_line_speed %d\n"
+ DP_LEVEL " req_duplex %d advertising 0x%x\n",
+ bp->req_autoneg, bp->req_line_speed, bp->req_duplex,
+ bp->advertising);
+
+ bnx2x_stop_stats(bp);
+ bnx2x_link_initialize(bp);
+
+ return 0;
+}
+
+static void bnx2x_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ strcpy(info->driver, DRV_MODULE_NAME);
+ strcpy(info->version, DRV_MODULE_VERSION);
+ snprintf(info->fw_version, 32, "%d.%d.%d:%d (BC VER %x)",
+ BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
+ BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_COMPILE_FLAGS,
+ bp->bc_ver);
+ strcpy(info->bus_info, pci_name(bp->pdev));
+ info->n_stats = BNX2X_NUM_STATS;
+ info->testinfo_len = BNX2X_NUM_TESTS;
+ info->eedump_len = bp->flash_size;
+ info->regdump_len = 0;
+}
+
+static void bnx2x_get_wol(struct net_device *dev, struct
ethtool_wolinfo *wol)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if (bp->flags & NO_WOL_FLAG) {
+ wol->supported = 0;
+ wol->wolopts = 0;
+ } else {
+ wol->supported = WAKE_MAGIC;
+ if (bp->wol)
+ wol->wolopts = WAKE_MAGIC;
+ else
+ wol->wolopts = 0;
+ }
+ memset(&wol->sopass, 0, sizeof(wol->sopass));
+}
+
+static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo
*wol)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if (wol->wolopts & ~WAKE_MAGIC)
+ return -EINVAL;
+
+ if (wol->wolopts & WAKE_MAGIC) {
+ if (bp->flags & NO_WOL_FLAG)
+ return -EINVAL;
+
+ bp->wol = 1;
+ } else {
+ bp->wol = 0;
+ }
+ return 0;
+}
+
+static u32 bnx2x_get_msglevel(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ return bp->msglevel;
+}
+
+static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if (capable(CAP_NET_ADMIN))
+ bp->msglevel = level;
+}
+
+static int bnx2x_nway_reset(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ bnx2x_stop_stats(bp);
+ bnx2x_link_initialize(bp);
+
+ return 0;
+}
+
+static int bnx2x_get_eeprom_len(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ return bp->flash_size;
+}
+
+static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
+{
+ int port = bp->port;
+ int count, i;
+ u32 val = 0;
+
+ /* adjust timeout for emulation/FPGA */
+ count = NVRAM_TIMEOUT_COUNT;
+ if (CHIP_REV(bp) == CHIP_REV_EMUL)
+ count *= 100;
+
+ /* request access to nvram interface */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_SW_ARB,
+ (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
+
+ for (i = 0; i < count*10; i++) {
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_SW_ARB);
+ if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
+ break;
+ }
+
+ udelay(5);
+ }
+
+ if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
+ DP(NETIF_MSG_NVM, "cannot get access to nvram interface\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int bnx2x_release_nvram_lock(struct bnx2x *bp)
+{
+ int port = bp->port;
+ int count, i;
+ u32 val = 0;
+
+ /* adjust timeout for emulation/FPGA */
+ count = NVRAM_TIMEOUT_COUNT;
+ if (CHIP_REV(bp) == CHIP_REV_EMUL)
+ count *= 100;
+
+ /* relinquish nvram interface */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_SW_ARB,
+ (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
+
+ for (i = 0; i < count*10; i++) {
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_SW_ARB);
+ if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
+ break;
+ }
+
+ udelay(5);
+ }
+
+ if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
+ DP(NETIF_MSG_NVM, "cannot free access to nvram interface\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static void bnx2x_enable_nvram_access(struct bnx2x *bp)
+{
+ u32 val;
+
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+ /* enable both bits, even on read */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+ (val | MCPR_NVM_ACCESS_ENABLE_EN |
+ MCPR_NVM_ACCESS_ENABLE_WR_EN));
+}
+
+static void bnx2x_disable_nvram_access(struct bnx2x *bp)
+{
+ u32 val;
+
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
+
+ /* disable both bits, even after read */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
+ (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
+ MCPR_NVM_ACCESS_ENABLE_WR_EN)));
+}
+
+static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32
*ret_val,
+ u32 cmd_flags)
+{
+ int rc;
+ int count, i;
+ u32 val;
+
+ /* build the command word */
+ cmd_flags |= MCPR_NVM_COMMAND_DOIT;
+
+ /* need to clear DONE bit separately */
+ REG_WR(bp, GRCBASE_MCP,
+ MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+ /* address of the NVRAM to read from */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ADDR,
+ (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+ /* issue a read command */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+ /* adjust timeout for emulation/FPGA */
+ count = NVRAM_TIMEOUT_COUNT;
+ if (CHIP_REV(bp) == CHIP_REV_EMUL)
+ count *= 100;
+
+ /* wait for completion */
+ *ret_val = 0;
+ rc = -EBUSY;
+ for (i = 0; i < count; i++) {
+ udelay(5);
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_COMMAND);
+
+ if (val & MCPR_NVM_COMMAND_DONE) {
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_READ);
+ DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
+ /* we read nvram data in cpu order
+ * but ethtool sees it as an array of bytes
+ * converting to big-endian will do the work */
+ val = cpu_to_be32(val);
+ *ret_val = val;
+ rc = 0;
+ break;
+ }
+ }
+
+ return rc;
+}
+
+static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
+ int buf_size)
+{
+ int rc;
+ u32 cmd_flags;
+ u32 val;
+
+ if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+ DP(NETIF_MSG_NVM,
+ "Invalid paramter: offset 0x%x buf_size 0x%x\n",
+ offset, buf_size);
+ return -EINVAL;
+ }
+
+ if (offset + buf_size > bp->flash_size) {
+ DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
+ " buf_size (0x%x) > flash_size (0x%x)\n",
+ offset, buf_size, bp->flash_size);
+ return -EINVAL;
+ }
+
+ /* request access to nvram interface */
+ rc = bnx2x_acquire_nvram_lock(bp);
+ if (rc) {
+ return rc;
+ }
+
+ /* enable access to nvram interface */
+ bnx2x_enable_nvram_access(bp);
+
+ /* read the first word(s) */
+ cmd_flags = MCPR_NVM_COMMAND_FIRST;
+ while ((buf_size > sizeof(u32)) && (rc == 0)) {
+ rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
+ memcpy(ret_buf, &val, 4);
+
+ /* advance to the next dword */
+ offset += sizeof(u32);
+ ret_buf += sizeof(u32);
+ buf_size -= sizeof(u32);
+ cmd_flags = 0;
+ }
+
+ if (rc == 0) {
+ cmd_flags |= MCPR_NVM_COMMAND_LAST;
+ rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
+ memcpy(ret_buf, &val, 4);
+ }
+
+ /* disable access to nvram interface */
+ bnx2x_disable_nvram_access(bp);
+ bnx2x_release_nvram_lock(bp);
+
+ return rc;
+}
+
+static int bnx2x_get_eeprom(struct net_device *dev,
+ struct ethtool_eeprom *eeprom, u8 *eebuf)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ int rc;
+
+ DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
+ DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
+ eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
+ eeprom->len, eeprom->len);
+
+ /* parameters already validated in ethtool_get_eeprom */
+
+ rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
+
+ return rc;
+}
+
+static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
+ u32 cmd_flags)
+{
+ int rc;
+ int count, i;
+
+ /* build the command word */
+ cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
+
+ /* need to clear DONE bit separately */
+ REG_WR(bp, GRCBASE_MCP,
+ MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
+
+ /* write the data */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_WRITE, val);
+
+ /* address of the NVRAM to write to */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_ADDR,
+ (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
+
+ /* issue the write command */
+ REG_WR(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
+
+ /* adjust timeout for emulation/FPGA */
+ count = NVRAM_TIMEOUT_COUNT;
+ if (CHIP_REV(bp) == CHIP_REV_EMUL)
+ count *= 100;
+
+ /* wait for completion */
+ rc = -EBUSY;
+ for (i = 0; i < count; i++) {
+ udelay(5);
+ val = REG_RD(bp, GRCBASE_MCP, MCP_REG_MCPR_NVM_COMMAND);
+ if (val & MCPR_NVM_COMMAND_DONE) {
+ rc = 0;
+ break;
+ }
+ }
+
+ return rc;
+}
+
+#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
+
+static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
+ int buf_size)
+{
+ int rc;
+ u32 cmd_flags;
+ u32 align_offset;
+ u32 val;
+
+ if (offset + buf_size > bp->flash_size) {
+ DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
+ " buf_size (0x%x) > flash_size (0x%x)\n",
+ offset, buf_size, bp->flash_size);
+ return -EINVAL;
+ }
+
+ /* request access to nvram interface */
+ rc = bnx2x_acquire_nvram_lock(bp);
+ if (rc) {
+ return rc;
+ }
+
+ /* enable access to nvram interface */
+ bnx2x_enable_nvram_access(bp);
+
+ cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
+ align_offset = (offset & ~0x03);
+ rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
+
+ if (rc == 0) {
+ val &= ~(0xff << BYTE_OFFSET(offset));
+ val |= (*data_buf << BYTE_OFFSET(offset));
+
+ /* nvram data is returned as an array of bytes
+ * convert it back to cpu order */
+ val = be32_to_cpu(val);
+
+ DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
+
+ rc = bnx2x_nvram_write_dword(bp, align_offset, val,
+ cmd_flags);
+ }
+
+ /* disable access to nvram interface */
+ bnx2x_disable_nvram_access(bp);
+ bnx2x_release_nvram_lock(bp);
+
+ return rc;
+}
+
+static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
+ int buf_size)
+{
+ int rc;
+ u32 cmd_flags;
+ u32 val;
+ u32 written_so_far;
+
+ if (buf_size == 1) { /* ethtool */
+ return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
+ }
+
+ if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
+ DP(NETIF_MSG_NVM,
+ "Invalid paramter: offset 0x%x buf_size 0x%x\n",
+ offset, buf_size);
+ return -EINVAL;
+ }
+
+ if (offset + buf_size > bp->flash_size) {
+ DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +"
+ " buf_size (0x%x) > flash_size (0x%x)\n",
+ offset, buf_size, bp->flash_size);
+ return -EINVAL;
+ }
+
+ /* request access to nvram interface */
+ rc = bnx2x_acquire_nvram_lock(bp);
+ if (rc) {
+ return rc;
+ }
+
+ /* enable access to nvram interface */
+ bnx2x_enable_nvram_access(bp);
+
+ written_so_far = 0;
+ cmd_flags = MCPR_NVM_COMMAND_FIRST;
+ while ((written_so_far < buf_size) && (rc == 0)) {
+ if (written_so_far == (buf_size - sizeof(u32)))
+ cmd_flags |= MCPR_NVM_COMMAND_LAST;
+ else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
+ cmd_flags |= MCPR_NVM_COMMAND_LAST;
+ else if ((offset % NVRAM_PAGE_SIZE) == 0)
+ cmd_flags |= MCPR_NVM_COMMAND_FIRST;
+
+ memcpy(&val, data_buf, 4);
+ DP(NETIF_MSG_NVM, "val 0x%08x\n", val);
+
+ rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
+
+ /* advance to the next dword */
+ offset += sizeof(u32);
+ data_buf += sizeof(u32);
+ written_so_far += sizeof(u32);
+ cmd_flags = 0;
+ }
+
+ /* disable access to nvram interface */
+ bnx2x_disable_nvram_access(bp);
+ bnx2x_release_nvram_lock(bp);
+
+ return rc;
+}
+
+static int bnx2x_set_eeprom(struct net_device *dev,
+ struct ethtool_eeprom *eeprom, u8 *eebuf)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ int rc;
+
+ DP(NETIF_MSG_NVM, "ethtool_eeprom: cmd %d\n"
+ DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
+ eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
+ eeprom->len, eeprom->len);
+
+ /* parameters already validated in ethtool_set_eeprom */
+
+ rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
+
+ return rc;
+}
+
+static int bnx2x_get_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *coal)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ memset(coal, 0, sizeof(struct ethtool_coalesce));
+
+ coal->rx_coalesce_usecs = bp->rx_ticks;
+ coal->tx_coalesce_usecs = bp->tx_ticks;
+ coal->stats_block_coalesce_usecs = bp->stats_ticks;
+
+ return 0;
+}
+
+static int bnx2x_set_coalesce(struct net_device *dev,
+ struct ethtool_coalesce *coal)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
+ if (bp->rx_ticks > 3000)
+ bp->rx_ticks = 3000;
+
+ bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
+ if (bp->tx_ticks > 0x3000)
+ bp->tx_ticks = 0x3000;
+
+ bp->stats_ticks = coal->stats_block_coalesce_usecs;
+ if (bp->stats_ticks > 0xffff00)
+ bp->stats_ticks = 0xffff00;
+ bp->stats_ticks &= 0xffff00;
+
+ if (netif_running(bp->dev)) {
+ bnx2x_update_coalesce(bp);
+ }
+
+ return 0;
+}
+
+static void bnx2x_get_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *ering)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ ering->rx_max_pending = MAX_RX_AVAIL;
+ ering->rx_mini_max_pending = 0;
+ ering->rx_jumbo_max_pending = 0;
+
+ ering->rx_pending = bp->rx_ring_size;
+ ering->rx_mini_pending = 0;
+ ering->rx_jumbo_pending = 0;
+
+ ering->tx_max_pending = MAX_TX_AVAIL;
+ ering->tx_pending = bp->tx_ring_size;
+}
+
+static int bnx2x_set_ringparam(struct net_device *dev,
+ struct ethtool_ringparam *ering)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if ((ering->rx_pending > MAX_RX_AVAIL) ||
+ (ering->tx_pending > MAX_TX_AVAIL) ||
+ (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
+
+ return -EINVAL;
+ }
+ bp->rx_ring_size = ering->rx_pending;
+ bp->tx_ring_size = ering->tx_pending;
+
+ if (netif_running(bp->dev)) {
+ bnx2x_nic_unload(bp, 0);
+ bnx2x_nic_load(bp, 0);
+ }
+
+ return 0;
+}
+
+static void bnx2x_get_pauseparam(struct net_device *dev,
+ struct ethtool_pauseparam *epause)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ epause->autoneg =
+ ((bp->req_autoneg & AUTONEG_FLOW_CTRL) == AUTONEG_FLOW_CTRL);
+ epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) == FLOW_CTRL_RX);
+ epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) == FLOW_CTRL_TX);
+
+ DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
+ DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
+ epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
+}
+
+static int bnx2x_set_pauseparam(struct net_device *dev,
+ struct ethtool_pauseparam *epause)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
+ DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
+ epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
+
+ bp->req_flow_ctrl = FLOW_CTRL_AUTO;
+ if (epause->autoneg) {
+ bp->req_autoneg |= AUTONEG_FLOW_CTRL;
+ bp->pause_mode = PAUSE_BOTH;
+ bp->advertising |= (ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+
+ } else {
+ bp->req_autoneg &= ~AUTONEG_FLOW_CTRL;
+
+ if (epause->rx_pause)
+ bp->req_flow_ctrl |= FLOW_CTRL_RX;
+ if (epause->tx_pause)
+ bp->req_flow_ctrl |= FLOW_CTRL_TX;
+
+ switch (bp->req_flow_ctrl) {
+ case FLOW_CTRL_AUTO:
+ bp->req_flow_ctrl = FLOW_CTRL_NONE;
+ bp->pause_mode = PAUSE_NONE;
+ bp->advertising &= ~(ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+ break;
+
+ case FLOW_CTRL_TX:
+ bp->pause_mode = PAUSE_ASYMMETRIC;
+ bp->advertising |= ADVERTISED_Asym_Pause;
+ break;
+
+ case FLOW_CTRL_RX:
+ bp->pause_mode = PAUSE_BOTH;
+ bp->advertising |= (ADVERTISED_Pause |
+ ADVERTISED_Asym_Pause);
+ break;
+
+ case FLOW_CTRL_BOTH:
+ bp->pause_mode = PAUSE_SYMMETRIC;
+ bp->advertising |= ADVERTISED_Pause;
+ break;
+ }
+ }
+
+ DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n"
+ DP_LEVEL " pause_mode %d advertising 0x%x\n",
+ bp->req_autoneg, bp->req_flow_ctrl, bp->pause_mode,
+ bp->advertising);
+
+ bnx2x_stop_stats(bp);
+ bnx2x_link_initialize(bp);
+
+ return 0;
+}
+
+static u32 bnx2x_get_rx_csum(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ return bp->rx_csum;
+}
+
+static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ bp->rx_csum = data;
+ return 0;
+}
+
+static int bnx2x_set_tso(struct net_device *dev, u32 data)
+{
+ if (data)
+ dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
+ else
+ dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
+ return 0;
+}
+
+static struct {
+ char string[ETH_GSTRING_LEN];
+} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
+ { "idle check (online)" },
+ { "MC Errors (online)" }
+};
+
+static int bnx2x_self_test_count(struct net_device *dev)
+{
+ return BNX2X_NUM_TESTS;
+}
+
+static void bnx2x_self_test(struct net_device *dev,
+ struct ethtool_test *etest, u64 *buf)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
+
+ if (bnx2x_idle_chk(bp) != 0) {
+ buf[0] = 1;
+ etest->flags |= ETH_TEST_FL_FAILED;
+ }
+ if (bnx2x_mc_assert(bp)) {
+ buf[1] = 1;
+ etest->flags |= ETH_TEST_FL_FAILED;
+ }
+ bnx2x_panic_dump(bp);
+}
+
+static struct {
+ char string[ETH_GSTRING_LEN];
+} bnx2x_stats_str_arr[BNX2X_NUM_STATS] = {
+ { "rx_bytes"}, /* 0 */
+ { "rx_error_bytes"}, /* 1 */
+ { "tx_bytes"}, /* 2 */
+ { "tx_error_bytes"}, /* 3 */
+ { "rx_ucast_packets"}, /* 4 */
+ { "rx_mcast_packets"}, /* 5 */
+ { "rx_bcast_packets"}, /* 6 */
+ { "tx_ucast_packets"}, /* 7 */
+ { "tx_mcast_packets"}, /* 8 */
+ { "tx_bcast_packets"}, /* 9 */
+ { "tx_mac_errors"}, /* 10 */
+ { "tx_carrier_errors"}, /* 11 */
+ { "rx_crc_errors"}, /* 12 */
+ { "rx_align_errors"}, /* 13 */
+ { "tx_single_collisions"}, /* 14 */
+ { "tx_multi_collisions"}, /* 15 */
+ { "tx_deferred"}, /* 16 */
+ { "tx_excess_collisions"}, /* 17 */
+ { "tx_late_collisions"}, /* 18 */
+ { "tx_total_collisions"}, /* 19 */
+ { "rx_fragments"}, /* 20 */
+ { "rx_jabbers"}, /* 21 */
+ { "rx_undersize_packets"}, /* 22 */
+ { "rx_oversize_packets"}, /* 23 */
+ { "rx_64_byte_packets"}, /* 24 */
+ { "rx_65_to_127_byte_packets"}, /* 25 */
+ { "rx_128_to_255_byte_packets"}, /* 26 */
+ { "rx_256_to_511_byte_packets"}, /* 27 */
+ { "rx_512_to_1023_byte_packets"}, /* 28 */
+ { "rx_1024_to_1522_byte_packets"}, /* 29 */
+ { "rx_1523_to_9022_byte_packets"}, /* 30 */
+ { "tx_64_byte_packets"}, /* 31 */
+ { "tx_65_to_127_byte_packets"}, /* 32 */
+ { "tx_128_to_255_byte_packets"}, /* 33 */
+ { "tx_256_to_511_byte_packets"}, /* 34 */
+ { "tx_512_to_1023_byte_packets"}, /* 35 */
+ { "tx_1024_to_1522_byte_packets"}, /* 36 */
+ { "tx_1523_to_9022_byte_packets"}, /* 37 */
+ { "rx_xon_frames"}, /* 38 */
+ { "rx_xoff_frames"}, /* 39 */
+ { "tx_xon_frames"}, /* 40 */
+ { "tx_xoff_frames"}, /* 41 */
+ { "rx_mac_ctrl_frames"}, /* 44 */
+ { "rx_filtered_packets"}, /* 43 */
+ { "rx_discards"}, /* 44 */
+};
+
+#define STATS_OFFSET32(offset_name) \
+ (offsetof(struct bnx2x_eth_stats, offset_name) / 4)
+
+static unsigned long bnx2x_stats_offset_arr[BNX2X_NUM_STATS] = {
+ STATS_OFFSET32(total_bytes_received_hi), /* 0 */
+ STATS_OFFSET32(stat_IfHCInBadOctets_hi), /* 1 */
+ STATS_OFFSET32(total_bytes_transmitted_hi), /* 2 */
+ STATS_OFFSET32(stat_IfHCOutBadOctets_hi), /* 3 */
+ STATS_OFFSET32(total_unicast_packets_received_hi), /* 4 */
+ STATS_OFFSET32(total_multicast_packets_received_hi), /* 5 */
+ STATS_OFFSET32(total_broadcast_packets_received_hi), /* 6 */
+ STATS_OFFSET32(total_unicast_packets_transmitted_hi), /* 7 */
+ STATS_OFFSET32(total_multicast_packets_transmitted_hi), /* 8 */
+ STATS_OFFSET32(total_broadcast_packets_transmitted_hi), /* 9 */
+ STATS_OFFSET32(stat_Dot3statsinternalmactransmiterrors), /* 10 */
+ STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), /* 11 */
+ STATS_OFFSET32(crc_receive_errors), /* 12 */
+ STATS_OFFSET32(alignment_errors), /* 13 */
+ STATS_OFFSET32(single_collision_transmit_frames), /* 14 */
+ STATS_OFFSET32(multiple_collision_transmit_frames), /* 15 */
+ STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), /* 16 */
+ STATS_OFFSET32(excessive_collision_frames), /* 17 */
+ STATS_OFFSET32(late_collision_frames), /* 18 */
+ STATS_OFFSET32(number_of_bugs_found_in_stats_spec), /* 19 */
+ STATS_OFFSET32(runt_packets_received), /* 20 */
+ STATS_OFFSET32(jabber_packets_received), /* 21 */
+ STATS_OFFSET32(error_runt_packets_received), /* 22 */
+ STATS_OFFSET32(error_jabber_packets_received), /* 23 */
+ STATS_OFFSET32(frames_received_64_bytes), /* 24 */
+ STATS_OFFSET32(frames_received_65_127_bytes), /* 25 */
+ STATS_OFFSET32(frames_received_128_255_bytes), /* 26 */
+ STATS_OFFSET32(frames_received_256_511_bytes), /* 27 */
+ STATS_OFFSET32(frames_received_512_1023_bytes), /* 28 */
+ STATS_OFFSET32(frames_received_1024_1522_bytes), /* 29 */
+ STATS_OFFSET32(frames_received_1523_9022_bytes), /* 30 */
+ STATS_OFFSET32(frames_transmitted_64_bytes), /* 31 */
+ STATS_OFFSET32(frames_transmitted_65_127_bytes), /* 32 */
+ STATS_OFFSET32(frames_transmitted_128_255_bytes), /* 33 */
+ STATS_OFFSET32(frames_transmitted_256_511_bytes), /* 34 */
+ STATS_OFFSET32(frames_transmitted_512_1023_bytes), /* 35 */
+ STATS_OFFSET32(frames_transmitted_1024_1522_bytes), /* 36 */
+ STATS_OFFSET32(frames_transmitted_1523_9022_bytes), /* 37 */
+ STATS_OFFSET32(pause_xon_frames_received), /* 38 */
+ STATS_OFFSET32(pause_xoff_frames_received), /* 39 */
+ STATS_OFFSET32(pause_xon_frames_transmitted), /* 40 */
+ STATS_OFFSET32(pause_xoff_frames_transmitted), /* 41 */
+ STATS_OFFSET32(control_frames_received), /* 44 */
+ STATS_OFFSET32(mac_filter_discard), /* 43 */
+ STATS_OFFSET32(no_buff_discard), /* 44 */
+};
+
+static u8 bnx2x_stats_len_arr[BNX2X_NUM_STATS] = {
+ 8, 0, 8, 0, 8, 8, 8, 8, 8, 8,
+ 4, 0, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4,
+};
+
+static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8
*buf)
+{
+ switch (stringset) {
+ case ETH_SS_STATS:
+ memcpy(buf, bnx2x_stats_str_arr, sizeof(bnx2x_stats_str_arr));
+ break;
+
+ case ETH_SS_TEST:
+ memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
+ break;
+ }
+}
+
+static int bnx2x_get_stats_count(struct net_device *dev)
+{
+ return BNX2X_NUM_STATS;
+}
+
+static void bnx2x_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats, u64 *buf)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ u32 *hw_stats = (u32 *)bnx2x_sp_check(bp, eth_stats);
+ int i;
+
+ for (i = 0; i < BNX2X_NUM_STATS; i++) {
+ if (bnx2x_stats_len_arr[i] == 0) {
+ /* skip this counter */
+ buf[i] = 0;
+ continue;
+ }
+ if (!hw_stats) {
+ buf[i] = 0;
+ continue;
+ }
+ if (bnx2x_stats_len_arr[i] == 4) {
+ /* 4-byte counter */
+ buf[i] = (u64) *(hw_stats + bnx2x_stats_offset_arr[i]);
+ continue;
+ }
+ /* 8-byte counter */
+ buf[i] = HILO_U64(*(hw_stats + bnx2x_stats_offset_arr[i]),
+ *(hw_stats + bnx2x_stats_offset_arr[i] + 1));
+ }
+}
+
+static int bnx2x_phys_id(struct net_device *dev, u32 data)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ int i;
+
+ if (data == 0)
+ data = 2;
+
+ for (i = 0; i < (data * 2); i++) {
+ if ((i % 2) == 0) {
+ bnx2x_leds_set(bp, SPEED_1000);
+ } else {
+ bnx2x_leds_unset(bp);
+ }
+ msleep_interruptible(500);
+ if (signal_pending(current))
+ break;
+ }
+
+ if (bp->link_up) {
+ bnx2x_leds_set(bp, bp->line_speed);
+ }
+ return 0;
+}
+
+static struct ethtool_ops bnx2x_ethtool_ops = {
+ .get_settings = bnx2x_get_settings,
+ .set_settings = bnx2x_set_settings,
+ .get_drvinfo = bnx2x_get_drvinfo,
+ .get_wol = bnx2x_get_wol,
+ .set_wol = bnx2x_set_wol,
+ .get_msglevel = bnx2x_get_msglevel,
+ .set_msglevel = bnx2x_set_msglevel,
+ .nway_reset = bnx2x_nway_reset,
+ .get_link = ethtool_op_get_link,
+ .get_eeprom_len = bnx2x_get_eeprom_len,
+ .get_eeprom = bnx2x_get_eeprom,
+ .set_eeprom = bnx2x_set_eeprom,
+ .get_coalesce = bnx2x_get_coalesce,
+ .set_coalesce = bnx2x_set_coalesce,
+ .get_ringparam = bnx2x_get_ringparam,
+ .set_ringparam = bnx2x_set_ringparam,
+ .get_pauseparam = bnx2x_get_pauseparam,
+ .set_pauseparam = bnx2x_set_pauseparam,
+ .get_rx_csum = bnx2x_get_rx_csum,
+ .set_rx_csum = bnx2x_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = ethtool_op_set_tx_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = bnx2x_set_tso,
+ .self_test_count = bnx2x_self_test_count,
+ .self_test = bnx2x_self_test,
+ .get_strings = bnx2x_get_strings,
+ .phys_id = bnx2x_phys_id,
+ .get_stats_count = bnx2x_get_stats_count,
+ .get_ethtool_stats = bnx2x_get_ethtool_stats
+};
+
+/* end of ethtool_ops */
+
+/****************************************************************************
+* General service functions
+****************************************************************************/
+
+static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
+{
+ u16 pmcsr;
+
+ pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
+
+ switch (state) {
+ case PCI_D0:
+ pci_write_config_word(bp->pdev,
+ bp->pm_cap + PCI_PM_CTRL,
+ (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
+ PCI_PM_CTRL_PME_STATUS);
+
+ if (pmcsr & PCI_PM_CTRL_STATE_MASK)
+ /* delay required during transition out of D3hot */
+ msleep(20);
+ break;
+
+ case PCI_D3hot:
+ pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
+ pmcsr |= 3;
+
+ if (bp->wol) {
+ pmcsr |= PCI_PM_CTRL_PME_ENABLE;
+ }
+ pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
+ pmcsr);
+
+ /* No more memory access after this point until
+ * device is brought back to D0.
+ */
+ /* udelay(50); TBD */
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/****************************************************************************
+* net_device service functions
+****************************************************************************/
+
+/* Called with rtnl_lock from vlan functions and also netif_tx_lock
+ * from set_multicast.
+ */
+static void bnx2x_set_rx_mode(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ u32 rx_mode = BNX2X_RX_MODE_NORMAL;
+
+ DP(NETIF_MSG_RX_STATUS, "called dev->flags = %x\n", dev->flags);
+
+ if (dev->flags & IFF_PROMISC) {
+ rx_mode = BNX2X_RX_MODE_PROMISC;
+
+ } else if (dev->flags & IFF_ALLMULTI ||
+ dev->mc_count > BNX2X_MAX_MULTICAST) {
+ rx_mode = BNX2X_RX_MODE_ALLMULTI;
+
+ } else { /* some multicasts */
+ int i, old, offset;
+ struct dev_mc_list *mclist;
+ struct mac_configuration_cmd *config =
+ bnx2x_sp(bp, mcast_config);
+
+ for (i = 0, mclist = dev->mc_list;
+ mclist && (i < dev->mc_count);
+ i++, mclist = mclist->next) {
+
+ config->config_table[i].cam_entry.msb_mac_addr =
+ ntohs(*(u16 *)&mclist->dmi_addr[0]);
+ config->config_table[i].cam_entry.middle_mac_addr =
+ ntohs(*(u16 *)&mclist->dmi_addr[2]);
+ config->config_table[i].cam_entry.lsb_mac_addr =
+ ntohs(*(u16 *)&mclist->dmi_addr[4]);
+ config->config_table[i].cam_entry.flags = bp->port;
+ config->config_table[i].target_table_entry.flags = 0;
+ config->config_table[i].target_table_entry.
+ client_id = 0;
+ config->config_table[i].target_table_entry.
+ vlan_id = 0;
+
+ DP(NETIF_MSG_RX_STATUS,
+ "setting MCAST[%d] (%04x:%04x:%04x)\n",
+ i, config->config_table[i].cam_entry.msb_mac_addr,
+ config->config_table[i].cam_entry.middle_mac_addr,
+ config->config_table[i].cam_entry.lsb_mac_addr);
+ }
+ old = config->hdr.length_6b;
+ if (old > i) {
+ for (; i < old; i++) {
+ if (CAM_IS_INVALID(config->config_table[i])) {
+ i--; /* already invalidated */
+ break;
+ }
+ /* invalidate */
+ CAM_INVALIDATE(config->config_table[i]);
+ }
+ }
+
+ if (CHIP_REV_IS_SLOW(bp))
+ offset = BNX2X_MAX_EMUL_MULTI*(1 + bp->port);
+ else
+ offset = BNX2X_MAX_MULTICAST*(1 + bp->port);
+
+ config->hdr.length_6b = i;
+ config->hdr.offset = offset;
+ config->hdr.reserved0 = 0;
+ config->hdr.reserved1 = 0;
+
+ bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
+ U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
+ U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
+ }
+
+ bp->rx_mode = rx_mode;
+ bnx2x_set_storm_rx_mode(bp);
+}
+
+static int bnx2x_poll(struct napi_struct *napi, int budget)
+{
+ struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
+ napi);
+ struct bnx2x *bp = fp->bp;
+ int work_done = 0;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ netif_rx_complete(bp->dev, napi);
+ return 0;
+ }
+#endif
+ prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
+ prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
+ prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
+
+ bnx2x_update_fpsb_idx(fp);
+
+ if (*fp->tx_cons_sb != fp->tx_pkt_cons) {
+ bnx2x_tx_int(fp, budget);
+ }
+
+ if (*fp->rx_cons_sb != fp->rx_comp_cons) {
+ work_done = bnx2x_rx_int(fp, budget);
+ }
+
+ rmb(); /* TBD check */
+
+ if (!bnx2x_has_work(fp)) {
+ netif_rx_complete(bp->dev, napi);
+
+ bnx2x_ack_sb(bp, fp->index, USTORM_ID, fp->fp_u_idx,
+ IGU_INT_NOP, 1);
+ bnx2x_ack_sb(bp, fp->index, CSTORM_ID, fp->fp_c_idx,
+ IGU_INT_ENABLE, 1);
+ }
+
+ return work_done;
+}
+
+/* Called with netif_tx_lock.
+ * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
+ * netif_wake_queue().
+ */
+static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ struct bnx2x_fastpath *fp;
+ struct sw_tx_bd *tx_buf;
+ struct eth_tx_bd *txbd;
+ struct eth_tx_parse_bd *pbd = NULL;
+ u16 pkt_prod, bd_prod;
+ int nbd, fp_index = 0;
+ dma_addr_t mapping;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (unlikely(bp->panic)) {
+ return NETDEV_TX_BUSY;
+ }
+#endif
+
+ fp = &bp->fp[fp_index];
+ if (unlikely(bnx2x_tx_avail(bp->fp) <
+ (skb_shinfo(skb)->nr_frags + 3))) {
+ bp->slowpath->eth_stats.driver_xoff++,
+ netif_stop_queue(dev);
+ BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
+ return NETDEV_TX_BUSY;
+ }
+
+ /*
+ This is a bit ugly. First we use one BD which we mark as start,
+ then for TSO or xsum we have a parsing info BD,
+ and only then we have the rest of the TSO bds.
+ (don't forget to mark the last one as last,
+ and to unmap only AFTER you write to the BD ...)
+ I would like to thank Dov Hirshfeld for this mess.
+ */
+
+ pkt_prod = fp->tx_pkt_prod++;
+ bd_prod = fp->tx_bd_prod;
+
+ pkt_prod = TX_BD(pkt_prod);
+ bd_prod = TX_BD(bd_prod);
+
+ /* get a tx_buff and first bd */
+ tx_buf = &fp->tx_buf_ring[pkt_prod];
+ txbd = &fp->tx_desc_ring[bd_prod];
+
+ txbd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
+ txbd->general_data = (UNICAST_ADDRESS <<
+ ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
+ txbd->general_data |= 1; /* header nbd */
+
+ /* remeber the first bd of the packet */
+ tx_buf->first_bd = bd_prod;
+
+ DP(NETIF_MSG_TX_QUEUED,
+ "sending pkt %u @%p next_idx %u bd %u @%p\n",
+ pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, txbd);
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ u8 len;
+ struct iphdr *iph = ip_hdr(skb);
+
+ txbd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
+
+ /* turn on parsing and get a bd */
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+ pbd = (void *)&fp->tx_desc_ring[bd_prod];
+
+ len = ((u8 *)ip_hdr(skb) - (u8 *)skb->data)/2;
+
+ /* for now NS flag is not used in Linux */
+ pbd->global_data = (len |
+ ((skb->protocol == ETH_P_8021Q) <<
+ ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
+
+ pbd->ip_hlen = ip_hdrlen(skb)/2;
+ pbd->total_hlen = len + pbd->ip_hlen;
+
+ if (iph->protocol == IPPROTO_TCP) {
+ struct tcphdr *th = tcp_hdr(skb);
+ txbd->bd_flags.as_bitfield |=
+ ETH_TX_BD_FLAGS_TCP_CSUM;
+ pbd->tcp_flags = htonl(tcp_flag_word(skb))&0xFFFF;
+ pbd->total_hlen += tcp_hdrlen(skb)/2;
+ pbd->tcp_pseudo_csum = ntohs(th->check);
+
+ } else if (iph->protocol == IPPROTO_UDP) {
+ struct udphdr *uh = udp_hdr(skb);
+ txbd->bd_flags.as_bitfield |=
+ ETH_TX_BD_FLAGS_TCP_CSUM;
+ pbd->total_hlen += 4;
+ pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
+ pbd->cs_offset = 5; /* 10 >> 1*/
+ pbd->tcp_pseudo_csum = 0;
+ /* HW bug: we need to subtract 10 bytes before the
+ * UDP header from the csum
+ */
+ uh->check = (u16) ~csum_fold(csum_sub(uh->check,
+ csum_partial(((u8 *)(uh)-10), 10, 0)));
+ }
+ }
+
+ if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
+ txbd->vlan = vlan_tx_tag_get(skb);
+ txbd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
+ }
+#ifdef BNX2X_STOP_ON_ERROR
+ else {
+ txbd->vlan = pkt_prod;
+ }
+#endif
+
+ mapping = pci_map_single(bp->pdev, skb->data,
+ skb->len, PCI_DMA_TODEVICE);
+
+ txbd->addr_hi = U64_HI(mapping);
+ txbd->addr_lo = U64_LO(mapping);
+ txbd->nbd = nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
+ txbd->nbytes = skb_headlen(skb);
+
+ DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
+ " nbytes %d flags %x vlan %u\n",
+ txbd, txbd->addr_hi, txbd->addr_lo, txbd->nbd,
+ txbd->nbytes, txbd->bd_flags.as_bitfield, txbd->vlan);
+
+ if ((skb_shinfo(skb)->gso_size) &&
+ (skb->len > (bp->dev->mtu + ETH_HLEN))) {
+
+ int hlen = 2*pbd->total_hlen;
+
+ DP(NETIF_MSG_TX_QUEUED,
+ "TSO packet len %d hlen %d total len %d tso size %d\n",
+ skb->len, hlen, skb_headlen(skb), skb_shinfo(skb)->gso_size);
+
+ txbd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
+
+ if (txbd->nbytes > hlen) {
+ /* we split the first bd into headers and data bds
+ * to ease the pain of our fellow micocode engineers
+ * we use one mapping for both bds
+ * So far this has only been observed to happen
+ * in Other Operating Systems(TM)
+ */
+
+ /* first fix first bd */
+ nbd++;
+ txbd->nbd++;
+ txbd->nbytes = hlen;
+
+ /* we only print this as an error
+ * because we don't think this will ever happen.
+ */
+ BNX2X_ERR("TSO split header size is %d (%x:%x)"
+ " nbd %d\n", txbd->nbytes, txbd->addr_hi,
+ txbd->addr_lo, txbd->nbd);
+
+ /* now get a new data bd
+ * (after the pbd) and fill it */
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+ txbd = &fp->tx_desc_ring[bd_prod];
+
+#ifdef BNX2X_STOP_ON_ERROR
+ txbd->vlan = pkt_prod;
+#endif
+ txbd->addr_hi = U64_HI(mapping);
+ txbd->addr_lo = U64_LO(mapping) + hlen;
+ txbd->nbytes = skb_headlen(skb) - hlen;
+ /* this marks the bd
+ * as one that has no individual mapping
+ * the FW ignors this flag in a bd not maked start
+ */
+ txbd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
+ DP(NETIF_MSG_TX_QUEUED,
+ "TSO split data size is %d (%x:%x)\n",
+ txbd->nbytes, txbd->addr_hi, txbd->addr_lo);
+ }
+
+ if (!pbd) {
+ /* supposed to be unreached
+ * (and therefore not handled properly...)
+ */
+ BNX2X_ERR("LSO with no PBD\n");
+ BUG();
+ }
+
+ pbd->lso_mss = skb_shinfo(skb)->gso_size;
+ pbd->tcp_send_seq = ntohl(tcp_hdr(skb)->seq);
+ pbd->ip_id = ntohs(ip_hdr(skb)->id);
+ pbd->tcp_pseudo_csum =
+ ntohs(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
+ ip_hdr(skb)->daddr,
+ 0, IPPROTO_TCP, 0));
+ pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
+ }
+
+ {
+ int i;
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+ txbd = &fp->tx_desc_ring[bd_prod];
+
+ mapping = pci_map_page(bp->pdev, frag->page,
+ frag->page_offset,
+ frag->size, PCI_DMA_TODEVICE);
+
+ txbd->addr_hi = U64_HI(mapping);
+ txbd->addr_lo = U64_LO(mapping);
+ txbd->nbytes = frag->size;
+ txbd->bd_flags.as_bitfield = 0;
+#ifdef BNX2X_STOP_ON_ERROR
+ txbd->vlan = pkt_prod;
+#endif
+ DP(NETIF_MSG_TX_QUEUED, "frag %d bd @%p"
+ " addr (%x:%x) nbytes %d flags %x\n",
+ i, txbd, txbd->addr_hi, txbd->addr_lo,
+ txbd->nbytes, txbd->bd_flags.as_bitfield);
+ } /* for */
+ }
+
+ /* now at last mark the bd as the last bd */
+ txbd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
+
+ DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
+ txbd, txbd->bd_flags.as_bitfield);
+
+ tx_buf->skb = skb;
+
+ bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
+
+ /* now send a tx doorbell, counting the next bd
+ * if the packet contains or ends with it
+ */
+ if (TX_BD_POFF(bd_prod) < nbd)
+ nbd++;
+
+ if (pbd) {
+ DP(NETIF_MSG_TX_QUEUED,
+ "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
+ " tcp_flags %x xsum %x seq %u hlen %u\n",
+ pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
+ pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
+ pbd->tcp_send_seq, pbd->total_hlen);
+ }
+
+ DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %u bd %d\n", nbd, bd_prod);
+
+ fp->hw_tx_prods->bds_prod += nbd;
+ fp->hw_tx_prods->packets_prod++;
+ DOORBELL(bp, fp_index, 0);
+
+ mmiowb();
+
+ fp->tx_bd_prod = bd_prod;
+ dev->trans_start = jiffies;
+
+ if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
+ netif_stop_queue(dev);
+ bp->slowpath->eth_stats.driver_xoff++;
+ if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
+ netif_wake_queue(dev);
+ }
+ fp->tx_pkt++;
+
+ return NETDEV_TX_OK;
+}
+
+static struct net_device_stats *bnx2x_get_stats(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+ return &bp->net_stats;
+}
+
+/* Called with rtnl_lock */
+static int bnx2x_open(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ bnx2x_set_power_state(bp, PCI_D0);
+
+ return bnx2x_nic_load(bp, 1);
+ /* TBD do we revert power state if load fails? */
+}
+
+/* Called with rtnl_lock */
+static int bnx2x_close(struct net_device *dev)
+{
+ int rc;
+ struct bnx2x *bp = netdev_priv(dev);
+
+ /* Unload the driver, release IRQs */
+ rc = bnx2x_nic_unload(bp, 1);
+ if (rc) {
+ BNX2X_ERR("bnx2x_nic_unload failed: %d\n", rc);
+ return rc;
+ }
+ bnx2x_set_power_state(bp, PCI_D3hot);
+
+ return 0;
+}
+
+/* Called with rtnl_lock */
+static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
+{
+ struct sockaddr *addr = p;
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if (!is_valid_ether_addr(addr->sa_data))
+ return -EINVAL;
+
+ memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+ if (netif_running(dev))
+ bnx2x_set_mac_addr(bp);
+
+ return 0;
+}
+
+/* Called with rtnl_lock */
+static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *data = if_mii(ifr);
+ struct bnx2x *bp = netdev_priv(dev);
+ int err;
+
+ switch (cmd) {
+ case SIOCGMIIPHY:
+ data->phy_id = bp->phy_addr;
+
+ /* fallthru */
+ case SIOCGMIIREG: {
+ u32 mii_regval;
+
+ spin_lock_bh(&bp->phy_lock);
+ if (bp->state == BNX2X_STATE_OPEN) {
+ err = bnx2x_mdio22_read(bp, data->reg_num & 0x1f,
+ &mii_regval);
+
+ data->val_out = mii_regval;
+ } else {
+ err = -EAGAIN;
+ }
+ spin_unlock_bh(&bp->phy_lock);
+ return err;
+ }
+
+ case SIOCSMIIREG:
+ if (!capable(CAP_NET_ADMIN)) {
+ return -EPERM;
+ }
+
+ spin_lock_bh(&bp->phy_lock);
+ if (bp->state == BNX2X_STATE_OPEN) {
+ err = bnx2x_mdio22_write(bp, data->reg_num & 0x1f,
+ data->val_in);
+ } else {
+ err = -EAGAIN;
+ }
+ spin_unlock_bh(&bp->phy_lock);
+ return err;
+
+ default:
+ /* do nothing */
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+/* Called with rtnl_lock */
+static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
+ ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
+ return -EINVAL;
+
+ /* This does not race with packet allocation
+ * because the actuall alloc size is
+ * only updated as part of load
+ */
+ dev->mtu = new_mtu;
+
+ if (netif_running(dev)) {
+ bnx2x_nic_unload(bp, 0);
+ bnx2x_nic_load(bp, 0);
+ }
+ return 0;
+}
+
+static void bnx2x_tx_timeout(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ if (!bp->panic) {
+ bnx2x_panic();
+ }
+#endif
+ /* This allows the netif to be shutdown gracefully before resetting */
+ schedule_work(&bp->reset_task);
+}
+
+#ifdef BCM_VLAN
+/* Called with rtnl_lock */
+static void bnx2x_vlan_rx_register(struct net_device *dev,
+ struct vlan_group *vlgrp)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ bp->vlgrp = vlgrp;
+ if (netif_running(dev))
+ bnx2x_set_rx_mode(dev);
+}
+#endif
+
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+static void poll_bnx2x(struct net_device *dev)
+{
+ struct bnx2x *bp = netdev_priv(dev);
+
+ disable_irq(bp->pdev->irq);
+ bnx2x_interrupt(bp->pdev->irq, dev);
+ enable_irq(bp->pdev->irq);
+}
+#endif
+
+static void bnx2x_reset_task(struct work_struct *work)
+{
+ struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
+
+#ifdef BNX2X_STOP_ON_ERROR
+ BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
+ " so reset not done to allow debug dump,\n"
+ KERN_ERR " you will need to reboot when done\n");
+ return;
+#endif
+
+ if (!netif_running(bp->dev))
+ return;
+
+ bp->in_reset_task = 1;
+
+ bnx2x_netif_stop(bp);
+
+ bnx2x_nic_unload(bp, 0);
+ bnx2x_nic_load(bp, 0);
+
+ bp->in_reset_task = 0;
+}
+
+static int __devinit bnx2x_init_board(struct pci_dev *pdev,
+ struct net_device *dev)
+{
+ struct bnx2x *bp;
+ int rc;
+
+ SET_NETDEV_DEV(dev, &pdev->dev);
+ bp = netdev_priv(dev);
+
+ bp->flags = 0;
+ bp->port = PCI_FUNC(pdev->devfn);
+
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
+ goto err_out;
+ }
+
+ if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
+ printk(KERN_ERR PFX "Cannot find PCI device base address,"
+ " aborting\n");
+ rc = -ENODEV;
+ goto err_out_disable;
+ }
+
+ if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
+ printk(KERN_ERR PFX "Cannot find second PCI device"
+ " base address, aborting\n");
+ rc = -ENODEV;
+ goto err_out_disable;
+ }
+
+ rc = pci_request_regions(pdev, DRV_MODULE_NAME);
+ if (rc) {
+ printk(KERN_ERR PFX "Cannot obtain PCI resources,"
+ " aborting\n");
+ goto err_out_disable;
+ }
+
+ pci_set_master(pdev);
+
+ bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
+ if (bp->pm_cap == 0) {
+ printk(KERN_ERR PFX "Cannot find power management"
+ " capability, aborting\n");
+ rc = -EIO;
+ goto err_out_release;
+ }
+
+ bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+ if (bp->pcie_cap == 0) {
+ printk(KERN_ERR PFX "Cannot find PCI Express capability,"
+ " aborting\n");
+ rc = -EIO;
+ goto err_out_release;
+ }
+
+ if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
+ bp->flags |= USING_DAC_FLAG;
+ if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
+ printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
+ " failed, aborting\n");
+ rc = -EIO;
+ goto err_out_release;
+ }
+
+ } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
+ printk(KERN_ERR PFX "System does not support DMA,"
+ " aborting\n");
+ rc = -EIO;
+ goto err_out_release;
+ }
+
+ bp->dev = dev;
+ bp->pdev = pdev;
+
+ spin_lock_init(&bp->phy_lock);
+
+ bp->in_reset_task = 0;
+ INIT_WORK(&bp->reset_task, bnx2x_reset_task);
+
+ bp->sp_task_en = 0;
+ tasklet_init(&bp->sp_task, bnx2x_sp_task, (unsigned long)bp);
+
+ dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
+ dev->mem_end = pci_resource_end(pdev, 0);
+
+ dev->irq = pdev->irq;
+
+ bp->regview = ioremap_nocache(dev->base_addr,
+ pci_resource_len(pdev, 0));
+ if (!bp->regview) {
+ printk(KERN_ERR PFX "Cannot map register space, aborting\n");
+ rc = -ENOMEM;
+ goto err_out_release;
+ }
+
+ bp->doorbells = ioremap_nocache(pci_resource_start(pdev , 2),
+ pci_resource_len(pdev, 2));
+ if (!bp->doorbells) {
+ printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
+ rc = -ENOMEM;
+ goto err_out_unmap;
+ }
+
+ bnx2x_set_power_state(bp, PCI_D0);
+ /* TBD why does open also call this? */
+
+ bnx2x_get_hwinfo(bp);
+
+ if (CHIP_REV(bp) == CHIP_REV_FPGA) {
+ printk(KERN_ERR PFX "FPGA detacted. MCP disabled,"
+ " will only init first device\n");
+ onefunc = 1;
+ nomcp = 1;
+ }
+
+ if (nomcp) {
+ printk(KERN_ERR PFX "MCP disabled, will only"
+ " init first device\n");
+ onefunc = 1;
+ }
+
+ if (onefunc && bp->port) {
+ printk(KERN_ERR PFX "Second device disabled, exiting\n");
+ rc = -ENODEV;
+ goto err_out_unmap;
+ }
+
+ bp->tx_ring_size = MAX_TX_AVAIL;
+ bp->rx_ring_size = MAX_RX_AVAIL;
+
+ bp->rx_csum = 1;
+
+ bp->rx_offset = 0;
+
+ bp->tx_quick_cons_trip_int = 0xff;
+ bp->tx_quick_cons_trip = 0xff;
+ bp->tx_ticks_int = 50;
+ bp->tx_ticks = 50;
+
+ bp->rx_quick_cons_trip_int = 0xff;
+ bp->rx_quick_cons_trip = 0xff;
+ bp->rx_ticks_int = 25;
+ bp->rx_ticks = 25;
+
+ bp->stats_ticks = 1000000 & 0xffff00;
+
+ bp->timer_interval = HZ;
+ bp->current_interval = (poll ? poll : HZ); /*TBD fixme*/
+
+ init_timer(&bp->timer);
+ bp->timer.expires = jiffies + bp->current_interval;
+ bp->timer.data = (unsigned long) bp;
+ bp->timer.function = bnx2x_timer;
+
+ return 0;
+
+err_out_unmap:
+ if (bp->regview) {
+ iounmap(bp->regview);
+ bp->regview = NULL;
+ }
+
+ if (bp->doorbells) {
+ iounmap(bp->doorbells);
+ bp->doorbells = NULL;
+ }
+
+err_out_release:
+ pci_release_regions(pdev);
+
+err_out_disable:
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+
+err_out:
+ return rc;
+}
+
+static int __devinit bnx2x_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ static int version_printed;
+ struct net_device *dev = NULL;
+ struct bnx2x *bp;
+ int rc, i;
+ int port = PCI_FUNC(pdev->devfn);
+
+ if (version_printed++ == 0)
+ printk(KERN_INFO "%s", version);
+
+ /* dev zeroed in init_etherdev */
+ dev = alloc_etherdev(sizeof(*bp));
+ if (!dev)
+ return -ENOMEM;
+
+ netif_carrier_off(dev);
+
+ bp = netdev_priv(dev);
+ bp->msglevel = debug;
+
+ if (port && onefunc) {
+ printk(KERN_ERR PFX "second function disabled. exiting\n");
+ return 0;
+ }
+
+ rc = bnx2x_init_board(pdev, dev);
+ if (rc < 0) {
+ free_netdev(dev);
+ return rc;
+ }
+
+ dev->hard_start_xmit = bnx2x_start_xmit;
+ dev->watchdog_timeo = TX_TIMEOUT;
+
+ dev->get_stats = bnx2x_get_stats;
+ dev->ethtool_ops = &bnx2x_ethtool_ops;
+ dev->open = bnx2x_open;
+ dev->stop = bnx2x_close;
+ dev->set_multicast_list = bnx2x_set_rx_mode;
+ dev->set_mac_address = bnx2x_change_mac_addr;
+ dev->do_ioctl = bnx2x_ioctl;
+ dev->change_mtu = bnx2x_change_mtu;
+ dev->tx_timeout = bnx2x_tx_timeout;
+#ifdef BCM_VLAN
+ dev->vlan_rx_register = bnx2x_vlan_rx_register;
+#endif
+#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
+ dev->poll_controller = poll_bnx2x;
+#endif
+ dev->features |= NETIF_F_SG;
+ if (bp->flags & USING_DAC_FLAG)
+ dev->features |= NETIF_F_HIGHDMA;
+ dev->features |= NETIF_F_IP_CSUM;
+#ifdef BCM_VLAN
+ dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+#endif
+ dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
+
+ netif_napi_add(dev, &bnx2x_fp(bp, 0, napi), bnx2x_poll, 128*4);
+
+ rc = register_netdev(dev);
+ if (rc) {
+ printk(KERN_ERR PFX "Cannot register net device\n");
+ if (bp->regview)
+ iounmap(bp->regview);
+ if (bp->doorbells)
+ iounmap(bp->doorbells);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+ free_netdev(dev);
+ return rc;
+ }
+
+ pci_set_drvdata(pdev, dev);
+
+ bp->name = board_info[ent->driver_data].name;
+ printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz "
+ "found at mem %lx, IRQ %d, ",
+ dev->name, bp->name,
+ ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
+ ((CHIP_ID(bp) & 0x0ff0) >> 4),
+ ((bp->flags & PCIX_FLAG) ? "-X" : ""),
+ ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
+ bp->bus_speed_mhz,
+ dev->base_addr,
+ bp->pdev->irq);
+
+ printk("node addr ");
+ for (i = 0; i < 6; i++)
+ printk("%2.2x", dev->dev_addr[i]);
+ printk("\n");
+
+ return 0;
+}
+
+static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct bnx2x *bp = netdev_priv(dev);
+
+ flush_scheduled_work();
+ tasklet_kill(&bp->sp_task);
+ unregister_netdev(dev);
+
+ if (bp->regview)
+ iounmap(bp->regview);
+
+ if (bp->doorbells)
+ iounmap(bp->doorbells);
+
+ free_netdev(dev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+}
+
+static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct bnx2x *bp = netdev_priv(dev);
+ int rc;
+
+ if (!netif_running(dev))
+ return 0;
+
+ rc = bnx2x_nic_unload(bp, 0);
+ if (!rc) {
+ return rc;
+ }
+
+ netif_device_detach(dev);
+ pci_save_state(pdev);
+ bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
+ return 0;
+}
+
+static int bnx2x_resume(struct pci_dev *pdev)
+{
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct bnx2x *bp = netdev_priv(dev);
+ int rc;
+
+ if (!netif_running(dev))
+ return 0;
+
+ pci_restore_state(pdev);
+ bnx2x_set_power_state(bp, PCI_D0);
+ netif_device_attach(dev);
+
+ rc = bnx2x_nic_load(bp, 0);
+ if (rc) {
+ return rc;
+ }
+ return 0;
+}
+
+static struct pci_driver bnx2x_pci_driver = {
+ .name = DRV_MODULE_NAME,
+ .id_table = bnx2x_pci_tbl,
+ .probe = bnx2x_init_one,
+ .remove = __devexit_p(bnx2x_remove_one),
+ .suspend = bnx2x_suspend,
+ .resume = bnx2x_resume,
+};
+
+static int __init bnx2x_init(void)
+{
+ return pci_register_driver(&bnx2x_pci_driver);
+}
+
+static void __exit bnx2x_cleanup(void)
+{
+ pci_unregister_driver(&bnx2x_pci_driver);
+}
+
+module_init(bnx2x_init);
+module_exit(bnx2x_cleanup);
+
--
1.4.2
^ permalink raw reply related
* [BNx2X][PATCH 3/8] bnx2x.h
From: Eliezer Tamir @ 2007-10-07 16:22 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x.h - main .h file
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x.h | 997
+++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 997 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
new file mode 100644
index 0000000..b7b2ceb
--- /dev/null
+++ b/drivers/net/bnx2x.h
@@ -0,0 +1,997 @@
+/* bnx2x.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Written by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
+ * Based on code from Michael Chan's bnx2 driver
+ */
+
+
+#ifndef BNX2X_H
+#define BNX2X_H
+
+/* error/debug prints */
+
+#define DRV_MODULE_NAME "bnx2x"
+#define PFX DRV_MODULE_NAME ": "
+
+/* for messages that are currently off */
+#define BNX2X_MSG_OFF 0
+#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */
+#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */
+#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */
+#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */
+
+#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
+
+/* regular debug print */
+#define DP(__mask, __fmt, __args...) do { \
+ if (bp->msglevel & (__mask)) \
+ printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+ __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
+ } while (0)
+
+/* for errors (never masked) */
+#define BNX2X_ERR(__fmt, __args...) do { \
+ printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \
+ __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \
+ } while (0)
+
+/* before we have a dev->name use dev_info() */
+#define BNX2X_DEV_INFO(__fmt, __args...) do { \
+ if (bp->msglevel & NETIF_MSG_PROBE) \
+ dev_info(&bp->pdev->dev, __fmt, ##__args); \
+ } while (0)
+
+
+#ifdef BNX2X_STOP_ON_ERROR
+#define bnx2x_panic() do { \
+ bp->panic = 1; \
+ BNX2X_ERR("driver assert\n"); \
+ bnx2x_disable_int(bp); \
+ bnx2x_panic_dump(bp); \
+ } while (0)
+#else
+#define bnx2x_panic()
+#endif
+
+
+#define U64_LO(x) (((u64)x) & 0xffffffff)
+#define U64_HI(x) (((u64)x) >> 32)
+#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)
+
+
+#define REG_ADDR(bp, block, offset) ((u8 *)bp->regview + block + offset)
+
+#define REG_RD(bp, block, offset) readl(REG_ADDR(bp, block, offset))
+#define REG_RD8(bp, block, offset) readb(REG_ADDR(bp, block, offset))
+#define REG_RD64(bp, block, offset) readq(REG_ADDR(bp, block, offset))
+
+#define REG_WR(bp, block, offset, val) \
+ writel((u32)val, REG_ADDR(bp, block, offset))
+#define REG_WR8(bp, block, offset, val) \
+ writeb((u8)val, REG_ADDR(bp, block, offset))
+#define REG_WR16(bp, block, offset, val) \
+ writew((u16)val, REG_ADDR(bp, block, offset))
+#define REG_WR32(bp, block, offset, val) REG_WR(bp, block, offset, val)
+
+#define REG_RD_IND(bp, block, offset) \
+ bnx2x_reg_rd_ind(bp, block + offset)
+#define REG_WR_IND(bp, block, offset, val) \
+ bnx2x_reg_wr_ind(bp, block + offset, val)
+
+#define REG_WR_DMAE(bp, block, offset, val, len32) \
+ do { \
+ memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
+ bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
+ block + offset, len32); \
+ } while (0)
+
+#define SHMEM_RD(bp, type) \
+ REG_RD(bp, bp->shmem_base, offsetof(struct shmem_region_t, type))
+#define SHMEM_WR(bp, type, val) \
+ REG_WR(bp, bp->shmem_base, offsetof(struct shmem_region_t, type), val)
+
+#define NIG_WR(reg, val) REG_WR(bp, GRCBASE_NIG, reg, val)
+#define EMAC_WR(reg, val) REG_WR(bp, emac_base, reg, val)
+#define BMAC_WR(reg, val) REG_WR(bp, GRCBASE_NIG, bmac_addr + reg, val)
+
+
+#define for_each_queue(bp, var) for (var = 0; var < bp->num_queues; var++)
+#ifdef BCM_MULTI
+#define for_each_nondefault_queue(bp, var) \
+ for (var = 1; var < bp->num_queues; var++)
+#define is_multi(bp) (bp->num_queues > 1)
+#endif
+
+
+struct regp {
+ u32 lo;
+ u32 hi;
+};
+
+struct bmac_stats {
+ struct regp tx_gtpkt;
+ struct regp tx_gtxpf;
+ struct regp tx_gtfcs;
+ struct regp tx_gtmca;
+ struct regp tx_gtgca;
+ struct regp tx_gtfrg;
+ struct regp tx_gtovr;
+ struct regp tx_gt64;
+ struct regp tx_gt127;
+ struct regp tx_gt255; /* 10 */
+ struct regp tx_gt511;
+ struct regp tx_gt1023;
+ struct regp tx_gt1518;
+ struct regp tx_gt2047;
+ struct regp tx_gt4095;
+ struct regp tx_gt9216;
+ struct regp tx_gt16383;
+ struct regp tx_gtmax;
+ struct regp tx_gtufl;
+ struct regp tx_gterr; /* 20 */
+ struct regp tx_gtbyt;
+
+ struct regp rx_gr64;
+ struct regp rx_gr127;
+ struct regp rx_gr255;
+ struct regp rx_gr511;
+ struct regp rx_gr1023;
+ struct regp rx_gr1518;
+ struct regp rx_gr2047;
+ struct regp rx_gr4095;
+ struct regp rx_gr9216; /* 30 */
+ struct regp rx_gr16383;
+ struct regp rx_grmax;
+ struct regp rx_grpkt;
+ struct regp rx_grfcs;
+ struct regp rx_grmca;
+ struct regp rx_grbca;
+ struct regp rx_grxcf;
+ struct regp rx_grxpf;
+ struct regp rx_grxuo;
+ struct regp rx_grjbr; /* 40 */
+ struct regp rx_grovr;
+ struct regp rx_grflr;
+ struct regp rx_grmeg;
+ struct regp rx_grmeb;
+ struct regp rx_grbyt;
+ struct regp rx_grund;
+ struct regp rx_grfrg;
+ struct regp rx_grerb;
+ struct regp rx_grfre;
+ struct regp rx_gripj; /* 50 */
+};
+
+struct emac_stats {
+ u32 rx_ifhcinoctets ;
+ u32 rx_ifhcinbadoctets ;
+ u32 rx_etherstatsfragments ;
+ u32 rx_ifhcinucastpkts ;
+ u32 rx_ifhcinmulticastpkts ;
+ u32 rx_ifhcinbroadcastpkts ;
+ u32 rx_dot3statsfcserrors ;
+ u32 rx_dot3statsalignmenterrors ;
+ u32 rx_dot3statscarriersenseerrors ;
+ u32 rx_xonpauseframesreceived ; /* 10 */
+ u32 rx_xoffpauseframesreceived ;
+ u32 rx_maccontrolframesreceived ;
+ u32 rx_xoffstateentered ;
+ u32 rx_dot3statsframestoolong ;
+ u32 rx_etherstatsjabbers ;
+ u32 rx_etherstatsundersizepkts ;
+ u32 rx_etherstatspkts64octets ;
+ u32 rx_etherstatspkts65octetsto127octets ;
+ u32 rx_etherstatspkts128octetsto255octets ;
+ u32 rx_etherstatspkts256octetsto511octets ; /* 20 */
+ u32 rx_etherstatspkts512octetsto1023octets ;
+ u32 rx_etherstatspkts1024octetsto1522octets;
+ u32 rx_etherstatspktsover1522octets ;
+
+ u32 rx_falsecarriererrors ;
+
+ u32 tx_ifhcoutoctets ;
+ u32 tx_ifhcoutbadoctets ;
+ u32 tx_etherstatscollisions ;
+ u32 tx_outxonsent ;
+ u32 tx_outxoffsent ;
+ u32 tx_flowcontroldone ; /* 30 */
+ u32 tx_dot3statssinglecollisionframes ;
+ u32 tx_dot3statsmultiplecollisionframes ;
+ u32 tx_dot3statsdeferredtransmissions ;
+ u32 tx_dot3statsexcessivecollisions ;
+ u32 tx_dot3statslatecollisions ;
+ u32 tx_ifhcoutucastpkts ;
+ u32 tx_ifhcoutmulticastpkts ;
+ u32 tx_ifhcoutbroadcastpkts ;
+ u32 tx_etherstatspkts64octets ;
+ u32 tx_etherstatspkts65octetsto127octets ; /* 40 */
+ u32 tx_etherstatspkts128octetsto255octets ;
+ u32 tx_etherstatspkts256octetsto511octets ;
+ u32 tx_etherstatspkts512octetsto1023octets ;
+ u32 tx_etherstatspkts1024octetsto1522octet ;
+ u32 tx_etherstatspktsover1522octets ;
+ u32 tx_dot3statsinternalmactransmiterrors ; /* 46 */
+};
+
+union mac_stats {
+ struct emac_stats emac;
+ struct bmac_stats bmac;
+};
+
+struct nig_stats {
+ u32 brb_discard;
+ u32 brb_packet;
+ u32 brb_truncate;
+ u32 flow_ctrl_discard;
+ u32 flow_ctrl_octets;
+ u32 flow_ctrl_packet;
+ u32 mng_discard;
+ u32 mng_octet_inp;
+ u32 mng_octet_out;
+ u32 mng_packet_inp;
+ u32 mng_packet_out;
+ u32 pbf_octets;
+ u32 pbf_packet;
+ u32 safc_inp;
+ u32 done;
+ u32 pad;
+};
+
+struct bnx2x_eth_stats {
+ u32 pad; /* to make long counters u64 aligned */
+ u32 mac_stx_start;
+ u32 total_bytes_received_hi;
+ u32 total_bytes_received_lo;
+ u32 total_bytes_transmitted_hi;
+ u32 total_bytes_transmitted_lo;
+ u32 total_unicast_packets_received_hi;
+ u32 total_unicast_packets_received_lo;
+ u32 total_multicast_packets_received_hi;
+ u32 total_multicast_packets_received_lo;
+ u32 total_broadcast_packets_received_hi;
+ u32 total_broadcast_packets_received_lo;
+ u32 total_unicast_packets_transmitted_hi;
+ u32 total_unicast_packets_transmitted_lo;
+ u32 total_multicast_packets_transmitted_hi;
+ u32 total_multicast_packets_transmitted_lo;
+ u32 total_broadcast_packets_transmitted_hi;
+ u32 total_broadcast_packets_transmitted_lo;
+ u32 crc_receive_errors;
+ u32 alignment_errors;
+ u32 false_carrier_detections;
+ u32 runt_packets_received;
+ u32 jabber_packets_received;
+ u32 pause_xon_frames_received;
+ u32 pause_xoff_frames_received;
+ u32 pause_xon_frames_transmitted;
+ u32 pause_xoff_frames_transmitted;
+ u32 single_collision_transmit_frames;
+ u32 multiple_collision_transmit_frames;
+ u32 late_collision_frames;
+ u32 excessive_collision_frames;
+ u32 control_frames_received;
+ u32 frames_received_64_bytes;
+ u32 frames_received_65_127_bytes;
+ u32 frames_received_128_255_bytes;
+ u32 frames_received_256_511_bytes;
+ u32 frames_received_512_1023_bytes;
+ u32 frames_received_1024_1522_bytes;
+ u32 frames_received_1523_9022_bytes;
+ u32 frames_transmitted_64_bytes;
+ u32 frames_transmitted_65_127_bytes;
+ u32 frames_transmitted_128_255_bytes;
+ u32 frames_transmitted_256_511_bytes;
+ u32 frames_transmitted_512_1023_bytes;
+ u32 frames_transmitted_1024_1522_bytes;
+ u32 frames_transmitted_1523_9022_bytes;
+ u32 valid_bytes_received_hi;
+ u32 valid_bytes_received_lo;
+ u32 error_runt_packets_received;
+ u32 error_jabber_packets_received;
+ u32 mac_stx_end;
+
+ u32 pad2;
+ u32 stat_IfHCInBadOctets_hi;
+ u32 stat_IfHCInBadOctets_lo;
+ u32 stat_IfHCOutBadOctets_hi;
+ u32 stat_IfHCOutBadOctets_lo;
+ u32 stat_Dot3statsinternalmactransmiterrors;
+ u32 stat_Dot3StatsCarrierSenseErrors;
+ u32 stat_Dot3StatsDeferredTransmissions;
+ u32 stat_FlowControlDone;
+ u32 stat_XoffStateEntered;
+
+ u32 x_total_sent_bytes_hi;
+ u32 x_total_sent_bytes_lo;
+ u32 x_total_sent_pkts;
+
+ u32 t_rcv_unicast_bytes_hi;
+ u32 t_rcv_unicast_bytes_lo;
+ u32 t_rcv_broadcast_bytes_hi;
+ u32 t_rcv_broadcast_bytes_lo;
+ u32 t_rcv_multicast_bytes_hi;
+ u32 t_rcv_multicast_bytes_lo;
+ u32 t_total_rcv_pkt;
+
+ u32 no_buff_discard;
+ u32 errors_discard;
+ u32 ttl0_discard;
+ u32 mac_filter_discard;
+ u32 xxoverflow_discard;
+
+ u32 brb_discard;
+ u32 brb_packet;
+ u32 brb_truncate;
+ u32 flow_ctrl_discard;
+ u32 flow_ctrl_octets;
+ u32 flow_ctrl_packet;
+ u32 mng_discard;
+ u32 mng_octet_inp;
+ u32 mng_octet_out;
+ u32 mng_packet_inp;
+ u32 mng_packet_out;
+ u32 pbf_octets;
+ u32 pbf_packet;
+ u32 safc_inp;
+ u32 driver_xoff;
+ u32 number_of_bugs_found_in_stats_spec; /* just kidding */
+};
+
+#ifdef BCM_MULTI
+#define MAX_CONTEXT 16
+#else
+#define MAX_CONTEXT 1
+#endif
+
+union cdu_context {
+ struct eth_context eth;
+ char pad[1024];
+};
+
+/* DMA memory not used in fastpath */
+struct bnx2x_slowpath {
+ union cdu_context context[MAX_CONTEXT];
+ struct eth_stats_query fw_stats;
+ struct mac_configuration_cmd mac_config;
+ struct mac_configuration_cmd mcast_config;
+
+ union mac_stats mac_stats;
+ struct nig_stats nig;
+ struct bnx2x_eth_stats eth_stats;
+
+ u32 wb_comp;
+#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
+ u32 wb_data[4];
+};
+
+#define bnx2x_sp(bp, var) (&bp->slowpath->var)
+#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : 0)
+#define bnx2x_sp_mapping(bp, var) \
+ (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
+
+
+struct sw_rx_bd {
+ struct sk_buff *skb;
+ DECLARE_PCI_UNMAP_ADDR(mapping)
+};
+
+struct sw_tx_bd {
+ struct sk_buff *skb;
+ u16 first_bd;
+};
+
+struct bnx2x_fastpath {
+
+ struct napi_struct napi;
+
+ struct host_status_block *status_blk;
+ dma_addr_t status_blk_mapping;
+
+ struct eth_tx_db_data *hw_tx_prods;
+ dma_addr_t tx_prods_mapping;
+
+ struct sw_tx_bd *tx_buf_ring;
+
+ struct eth_tx_bd *tx_desc_ring;
+ dma_addr_t tx_desc_mapping;
+
+ struct sw_rx_bd *rx_buf_ring;
+
+ struct eth_rx_bd *rx_desc_ring;
+ dma_addr_t rx_desc_mapping;
+
+ union eth_rx_cqe *rx_comp_ring;
+ dma_addr_t rx_comp_mapping;
+
+ int state;
+#define BNX2X_FP_STATE_CLOSED 0
+#define BNX2X_FP_STATE_IRQ 0x80000
+#define BNX2X_FP_STATE_OPENING 0x90000
+#define BNX2X_FP_STATE_OPEN 0xa0000
+#define BNX2X_FP_STATE_HALTING 0xb0000
+#define BNX2X_FP_STATE_HALTED 0xc0000
+#define BNX2X_FP_STATE_DELETED 0xd0000
+#define BNX2X_FP_STATE_CLOSE_IRQ 0xe0000
+
+ struct tasklet_struct fp_task;
+ int index;
+
+ u16 tx_pkt_prod;
+ u16 tx_pkt_cons;
+ u16 tx_bd_prod;
+ u16 tx_bd_cons;
+ u16 *tx_cons_sb;
+
+ u16 fp_c_idx;
+ u16 fp_u_idx;
+
+ u16 rx_bd_prod;
+ u16 rx_bd_cons;
+ u16 rx_comp_prod;
+ u16 rx_comp_cons;
+ u16 *rx_cons_sb;
+
+#ifdef BNX2X_STOP_ON_ERROR
+ u32 next_free,
+ last_alloc;
+#endif
+ unsigned long tx_pkt,
+ rx_pkt,
+ rx_calls;
+
+ struct bnx2x *bp; /* parent */
+};
+
+#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
+
+
+/* attn group wiring */
+#define MAX_DYNAMIC_ATTN_GRPS 8
+
+struct attn_route {
+ u32 sig[4];
+};
+
+struct bnx2x {
+ /* Fields used in the tx and intr/napi performance paths
+ * are grouped together in the beginning of the structure
+ */
+ void __iomem *regview;
+ void __iomem *doorbells;
+
+ struct net_device *dev;
+ struct pci_dev *pdev;
+
+ atomic_t intr_sem;
+
+ struct msix_entry msix_table[MAX_CONTEXT+1];
+
+ int tx_ring_size;
+
+#ifdef BCM_VLAN
+ struct vlan_group *vlgrp;
+#endif
+
+ u32 rx_csum;
+ u32 rx_offset;
+ u32 rx_buf_use_size; /* useable size */
+ u32 rx_buf_size; /* with alignment */
+
+ struct host_def_status_block *def_status_blk;
+ u16 def_c_idx;
+ u16 def_u_idx;
+ u16 def_t_idx;
+ u16 def_x_idx;
+ u16 def_att_idx;
+ u16 attn_state;
+ struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
+ u32 aeu_mask;
+ u32 nig_mask;
+
+ /* slow path ring */
+ struct eth_spe *spq;
+ dma_addr_t spq_mapping;
+ u16 spq_prod_idx;
+ u16 spq_con_idx;
+ u16 dsb_sp_prod_idx;
+ struct eth_spe *spq_prod_bd;
+ struct eth_spe *spq_last_bd;
+ u16 *spq_hw_con;
+ u16 *dsb_sp_prod;
+ u16 spq_left;
+ spinlock_t spq_lock; /* Used to serialize slowpath
+ events */
+ /* Flag for marking that there is either
+ * STAT_QUERY or CFC DELETE ramrod pending
+ */
+ u8 stat_pending;
+
+ /* End of fileds used in the performance code paths */
+
+ int panic;
+ int msglevel;
+
+ u32 flags;
+#define PCIX_FLAG 1
+#define PCI_32BIT_FLAG 2
+#define ONE_TDMA_FLAG 4 /* no longer used */
+#define NO_WOL_FLAG 8
+#define USING_DAC_FLAG 0x10
+#define USING_MSIX_FLAG 0x20
+#define ASF_ENABLE_FLAG 0x40
+
+ int port;
+
+ int pm_cap;
+ int pcie_cap;
+
+ /* Used to synchronize phy accesses */
+ spinlock_t phy_lock;
+
+ struct work_struct reset_task;
+ u16 in_reset_task;
+
+ struct tasklet_struct sp_task;
+ u16 sp_task_en;
+
+ struct timer_list timer;
+ int timer_interval;
+ int current_interval;
+
+ u32 shmem_base;
+
+ u32 chip_id;
+/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
+#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
+
+#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
+#define CHIP_NUM_5710 0x57100000
+
+#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
+#define CHIP_REV_Ax 0x00000000
+#define CHIP_REV_Bx 0x00001000
+#define CHIP_REV_Cx 0x00002000
+#define CHIP_REV_EMUL 0x0000e000
+#define CHIP_REV_FPGA 0x0000f000
+#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
+ (CHIP_REV(bp) == CHIP_REV_FPGA))
+
+#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
+#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
+
+ u16 fw_seq;
+ u16 fw_drv_pulse_wr_seq;
+ u32 fw_mb;
+
+ u32 hw_config;
+ u32 serdes_config;
+ u32 lane_config;
+ u32 ext_phy_config;
+#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
+ PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
+#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \
+ PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
+
+ u32 speed_cap_mask;
+ u32 link_config;
+#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
+#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
+#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
+#define SWITCH_CFG_ONE_TIME_DETECT \
+ PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
+
+ u8 ser_lane;
+ u8 rx_lane_swap;
+ u8 tx_lane_swap;
+
+ u8 link_up;
+
+ u32 supported;
+/* link settings - missing defines */
+#define SUPPORTED_2500baseT_Full (1 << 15)
+#define SUPPORTED_CX4 (1 << 16)
+
+ u32 phy_flags;
+/*#define PHY_SERDES_FLAG 0x1*/
+#define PHY_BMAC_FLAG 0x2
+#define PHY_EMAC_FLAG 0x4
+#define PHY_XGXS_FLAG 0x8
+#define PHY_SGMII_FLAG 0x10
+#define PHY_INT_MODE_MASK_FLAG 0x300
+#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
+#define PHY_INT_MODE_LINK_READY_FLAG 0x200
+
+ u32 phy_addr;
+ u32 phy_id;
+
+ u32 autoneg;
+#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
+#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
+#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
+#define AUTONEG_PARALLEL \
+ SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
+#define AUTONEG_SGMII_FIBER_AUTODET \
+ SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
+#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
+
+ u32 req_autoneg;
+#define AUTONEG_SPEED 0x1
+#define AUTONEG_FLOW_CTRL 0x2
+
+ u32 req_line_speed;
+/* link settings - missing defines */
+#define SPEED_12000 12000
+#define SPEED_12500 12500
+#define SPEED_13000 13000
+#define SPEED_15000 15000
+#define SPEED_16000 16000
+
+ u32 req_duplex;
+ u32 req_flow_ctrl;
+#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
+#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
+#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
+#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
+#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
+
+ u32 pause_mode;
+#define PAUSE_NONE 0
+#define PAUSE_SYMMETRIC 1
+#define PAUSE_ASYMMETRIC 2
+#define PAUSE_BOTH 3
+
+ u32 advertising;
+/* link settings - missing defines */
+#define ADVERTISED_2500baseT_Full (1 << 15)
+#define ADVERTISED_CX4 (1 << 16)
+
+ u32 link_status;
+ u32 line_speed;
+ u32 duplex;
+ u32 flow_ctrl;
+
+ u32 bc_ver;
+
+ int flash_size;
+#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
+#define NVRAM_TIMEOUT_COUNT 30000
+#define NVRAM_PAGE_SIZE 256
+
+ int rx_ring_size;
+
+ u16 tx_quick_cons_trip_int;
+ u16 tx_quick_cons_trip;
+ u16 tx_ticks_int;
+ u16 tx_ticks;
+
+ u16 rx_quick_cons_trip_int;
+ u16 rx_quick_cons_trip;
+ u16 rx_ticks_int;
+ u16 rx_ticks;
+
+ u32 stats_ticks;
+
+ int state;
+#define BNX2X_STATE_CLOSED 0x0
+#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
+#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
+#define BNX2X_STATE_OPEN 0x3000
+#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
+#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
+#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
+#define BNX2X_STATE_ERROR 0xF000
+
+ int num_queues;
+
+ u32 rx_mode;
+#define BNX2X_RX_MODE_NONE 0
+#define BNX2X_RX_MODE_NORMAL 1
+#define BNX2X_RX_MODE_ALLMULTI 2
+#define BNX2X_RX_MODE_PROMISC 3
+#define BNX2X_MAX_MULTICAST 64
+#define BNX2X_MAX_EMUL_MULTI 16
+
+ dma_addr_t def_status_blk_mapping;
+
+ struct bnx2x_slowpath *slowpath;
+ dma_addr_t slowpath_mapping;
+
+#ifdef BCM_ISCSI
+ void *t1;
+ dma_addr_t t1_mapping;
+ void *t2;
+ dma_addr_t t2_mapping;
+ void *timers;
+ dma_addr_t timers_mapping;
+ void *qm;
+ dma_addr_t qm_mapping;
+#endif
+
+ char *name;
+ u16 bus_speed_mhz;
+ u8 wol;
+ u8 pad;
+
+ /* used to synchronize stats collecting */
+ int stats_state;
+#define STATS_STATE_DISABLE 0
+#define STATS_STATE_ENABLE 1
+#define STATS_STATE_STOP 2 /* stop stats on next iteration */
+
+ u32 old_brb_discard;
+ struct bmac_stats old_bmac;
+ struct tstorm_per_client_stats old_tclient;
+ struct net_device_stats net_stats;
+ struct dmae_command dmae;
+
+ struct z_stream_s *strm;
+ void *gunzip_buf;
+ dma_addr_t gunzip_mapping;
+ int gunzip_outlen;
+#define FW_BUF_SIZE 0x8000
+ struct bnx2x_fastpath fp[1];
+};
+
+
+/* DMAE command defines */
+#define DMAE_CMD_SRC_PCI 0
+#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
+
+#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
+#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
+
+#define DMAE_CMD_C_DST_PCI 0
+#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
+
+#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
+
+#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
+#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
+
+#define DMAE_CMD_PORT_0 0
+#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
+
+#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
+#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
+
+#define DMAE_LEN_MAX 0x2000 /* BUG ??? (65532 / 4) */
+
+
+/* MC hsi */
+#define RX_COPY_THRESH 92
+#define BCM_PAGE_BITS 12
+#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
+
+#define NUM_TX_RINGS 32
+#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
+#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
+#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
+#define MAX_TX_BD (NUM_TX_BD - 1)
+#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
+#define NEXT_TX_IDX(x) ((((x) & (MAX_TX_DESC_CNT)) == \
+ (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
+#define TX_BD(x) ((x) & MAX_TX_BD)
+#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
+
+#define NUM_RX_RINGS 32
+#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
+#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
+#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
+#define MAX_RX_BD (NUM_RX_BD - 1)
+#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
+#define NEXT_RX_IDX(x) ((((x) & (MAX_RX_DESC_CNT)) == \
+ (MAX_RX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
+#define RX_BD(x) ((x) & MAX_RX_BD)
+
+
+/* used on a CID received from the HW */
+#define SW_CID(x) (x & (COMMON_RAMROD_ETH_RX_CQE_CID >> 1))
+
+#define BD_UNMAP_ADDR(bd) HILO_U64((bd)->addr_hi, (bd)->addr_lo)
+#define BD_UNMAP_LEN(bd) ((bd)->nbytes)
+
+
+#define MDIO_INDIRECT_REG_ADDR 0x1f
+#define MDIO_SET_REG_BANK(bp, reg_bank) \
+ bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
+
+#define MDIO_ACCESS_TIMEOUT 1000
+
+
+/* must be used on a CID before placing it on a HW ring */
+#define HW_CID(bp, x) (x | (bp->port << 23))
+
+#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
+#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
+
+#define ATTN_NIG_FOR_FUNC0 (1L << 8)
+#define ATTN_SW_TIMER_4_FUNC0 (1L << 9)
+#define GPIO_2_FUNC0 (1L << 10)
+#define GPIO_3_FUNC0 (1L << 11)
+#define GPIO_4_FUNC0 (1L << 12)
+#define ATTN_GENERAL_ATTN_1 (1L << 13)
+#define ATTN_GENERAL_ATTN_2 (1L << 14)
+#define ATTN_GENERAL_ATTN_3 (1L << 15)
+
+#define ATTN_NIG_FOR_FUNC1 (1L << 8)
+#define ATTN_SW_TIMER_4_FUNC1 (1L << 9)
+#define GPIO_2_FUNC1 (1L << 10)
+#define GPIO_3_FUNC1 (1L << 11)
+#define GPIO_4_FUNC1 (1L << 12)
+#define ATTN_GENERAL_ATTN_4 (1L << 13)
+#define ATTN_GENERAL_ATTN_5 (1L << 14)
+#define ATTN_GENERAL_ATTN_6 (1L << 15)
+
+#define ATTN_HARD_WIRED_MASK 0xff00
+#define ATTENTION_ID 4
+
+
+#define BNX2X_BTR 3
+#define MAX_SPQ_PENDING 8
+
+
+#define BNX2X_NUM_STATS 45
+#define BNX2X_NUM_TESTS 2
+
+
+#define DPM_TRIGER_TYPE 0x40
+#define DOORBELL(bp, cid, val) \
+ do{ \
+ writel((u32)val, (u8 *)(bp)->doorbells + \
+ ((BCM_PAGE_SIZE * cid) + DPM_TRIGER_TYPE)); \
+ } while (0)
+
+#define MIN_ETHERNET_PACKET_SIZE 60
+#define MAX_ETHERNET_PACKET_SIZE 1514
+#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9600
+
+
+/* stuff added to make the code fit 80Col */
+
+#define BNX2X_RX_SUM_OK(cqe) \
+ (!(cqe->fast_path_cqe.status_flags & \
+ (ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG | \
+ ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))
+
+
+#define MDIO_AN_CL73_OR_37_COMPLETE \
+ (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
+
+#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
+#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
+#define GP_STATUS_SPEED_MASK \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
+#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
+#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
+#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
+#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
+#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
+#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
+#define GP_STATUS_10G_HIG \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
+#define GP_STATUS_10G_CX4 \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
+#define GP_STATUS_12G_HIG \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
+#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
+#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
+#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
+#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
+#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
+#define GP_STATUS_10G_KX4 \
+ MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
+
+#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
+#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
+#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
+#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
+#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
+#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
+#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
+#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
+#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
+#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
+#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
+#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
+#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
+#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
+#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
+#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
+#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
+#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
+#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
+#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
+#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
+#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
+#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
+
+#define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \
+ NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G
+#define NIG_XGXS0_LINK_STATUS \
+ NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS
+#define NIG_XGXS0_LINK_STATUS_SIZE \
+ NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE
+#define NIG_SERDES0_LINK_STATUS \
+ NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS
+#define NIG_MASK_MI_INT \
+ NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT
+#define NIG_MASK_XGXS0_LINK10G \
+ NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G
+#define NIG_MASK_XGXS0_LINK_STATUS \
+ NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS
+#define NIG_MASK_SERDES0_LINK_STATUS \
+ NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS
+
+#define XGXS_RESET_BITS \
+ (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
+
+#define SERDES_RESET_BITS \
+ (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
+ MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
+
+
+#define BNX2X_MC_ASSERT_BITS \
+ (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+ GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+ GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
+ GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
+
+#define BNX2X_MCP_ASSERT \
+ GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
+
+#define BNX2X_DOORQ_ASSERT \
+ AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
+
+
+#ifdef __BIG_ENDIAN
+#define U_SB_ETH_RX_CQ_INDEX 0
+#define C_SB_ETH_TX_CQ_INDEX 0
+#define X_DEF_SB_SPQ_INDEX 1
+#define C_DEF_SB_SP_INDEX 2
+#else
+#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
+#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
+#define X_DEF_SB_SPQ_INDEX HC_INDEX_DEF_X_SPQ_CONS
+#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
+#endif
+
+#define BNX2X_RX_SB_INDEX \
+&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
+
+#define BNX2X_TX_SB_INDEX \
+&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]
+
+#define BNX2X_SPQ_SB_INDEX \
+&bp->def_status_blk->x_def_status_block.index_values[X_DEF_SB_SPQ_INDEX]
+
+#define BNX2X_SP_DSB_INDEX \
+&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
+
+
+#define CAM_IS_INVALID(x) \
+(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
+
+#define CAM_INVALIDATE(x) \
+x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE
+
+
+/* MISC_REGISTERS_RESET_REG - this is here for the hsi to work don't
touch */
+
+#endif /* bnx2x.h */
--
1.4.2
^ permalink raw reply related
* [BNX2X][PATCH 4/8] bnx2x_hsi.h
From: Eliezer Tamir @ 2007-10-07 16:23 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x_hsi.h - machine generated headers defining HW and Micorocode
constants.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x_hsi.h | 7086
+++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 7066 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
new file mode 100644
index 0000000..21eea48
--- /dev/null
+++ b/drivers/net/bnx2x_hsi.h
@@ -0,0 +1,7086 @@
+/* bnx2x_hsi.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ */
+
+/* Machine generated - do not edit */
+
+#define BRB1_REGISTERS_BRB1_INT_STS 0x11cUL
+#define BRB1_REGISTERS_BRB1_INT_STS_CLR 0x120UL
+#define BRB1_REGISTERS_BRB1_INT_STS_WR 0x124UL
+#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT 0x200UL
+#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT_SIZE 3
+#define BRB1_REGISTERS_LL_RAM 0x1000UL
+#define BRB1_REGISTERS_LL_RAM_SIZE 512
+#define BRB1_REGISTERS_NUM_OF_FULL_BLOCKS 0x90UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_0 0xc8UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_1 0xccUL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_2 0xd0UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_3 0xd4UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_4 0xd8UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_0 0xb8UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_1 0xbcUL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_2 0xc0UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_3 0xc4UL
+#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_0 0x78UL
+#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_1 0x7cUL
+#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_0 0x68UL
+#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_1 0x6cUL
+#define BRB1_REGISTERS_SOFT_RESET 0xdcUL
+#define CCM_REGISTERS_CAM_OCCUP 0x188UL
+#define CCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define CCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define CCM_REGISTERS_CCM_CFC_IFEN 0x3cUL
+#define CCM_REGISTERS_CCM_CQM_IFEN 0xcUL
+#define CCM_REGISTERS_CCM_CQM_USE_Q 0xc0UL
+#define CCM_REGISTERS_CCM_INT_STS 0x1d8UL
+#define CCM_REGISTERS_CCM_INT_STS_CLR 0x1dcUL
+#define CCM_REGISTERS_CCM_INT_STS_WR 0x1e0UL
+#define CCM_REGISTERS_CCM_REG0_SZ 0xc4UL
+#define CCM_REGISTERS_CCM_STORM0_IFEN 0x4UL
+#define CCM_REGISTERS_CCM_STORM1_IFEN 0x8UL
+#define CCM_REGISTERS_CDU_AG_RD_IFEN 0x30UL
+#define CCM_REGISTERS_CDU_AG_WR_IFEN 0x2cUL
+#define CCM_REGISTERS_CDU_SM_RD_IFEN 0x38UL
+#define CCM_REGISTERS_CDU_SM_WR_IFEN 0x34UL
+#define CCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define CCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_CNT_AUX1_Q 0xc8UL
+#define CCM_REGISTERS_CNT_AUX2_Q 0xccUL
+#define CCM_REGISTERS_CP_WEIGHT 0xb0UL
+#define CCM_REGISTERS_CQM_CCM_HDR_P 0x8cUL
+#define CCM_REGISTERS_CQM_CCM_HDR_S 0x90UL
+#define CCM_REGISTERS_CQM_CCM_IFEN 0x14UL
+#define CCM_REGISTERS_CQM_INIT_CRD 0x20cUL
+#define CCM_REGISTERS_CQM_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_CQM_P_WEIGHT 0xb8UL
+#define CCM_REGISTERS_CSDM_IFEN 0x18UL
+#define CCM_REGISTERS_CSDM_LENGTH_MIS 0x170UL
+#define CCM_REGISTERS_ERR_CCM_HDR 0x94UL
+#define CCM_REGISTERS_ERR_EVNT_ID 0x98UL
+#define CCM_REGISTERS_FIC0_INIT_CRD 0x210UL
+#define CCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_FIC1_INIT_CRD 0x214UL
+#define CCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_GR_ARB_TYPE 0x15cUL
+#define CCM_REGISTERS_GR_LD0_PR 0x164UL
+#define CCM_REGISTERS_GR_LD1_PR 0x168UL
+#define CCM_REGISTERS_INV_DONE_Q 0x108UL
+#define CCM_REGISTERS_N_SM_CTX_LD_0 0x4cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_1 0x50UL
+#define CCM_REGISTERS_N_SM_CTX_LD_10 0x74UL
+#define CCM_REGISTERS_N_SM_CTX_LD_11 0x78UL
+#define CCM_REGISTERS_N_SM_CTX_LD_12 0x7cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_13 0x80UL
+#define CCM_REGISTERS_N_SM_CTX_LD_14 0x84UL
+#define CCM_REGISTERS_N_SM_CTX_LD_15 0x88UL
+#define CCM_REGISTERS_N_SM_CTX_LD_2 0x54UL
+#define CCM_REGISTERS_N_SM_CTX_LD_3 0x58UL
+#define CCM_REGISTERS_N_SM_CTX_LD_4 0x5cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_5 0x60UL
+#define CCM_REGISTERS_N_SM_CTX_LD_6 0x64UL
+#define CCM_REGISTERS_N_SM_CTX_LD_7 0x68UL
+#define CCM_REGISTERS_PBF_IFEN 0x28UL
+#define CCM_REGISTERS_PBF_LENGTH_MIS 0x180UL
+#define CCM_REGISTERS_PBF_WEIGHT 0xacUL
+#define CCM_REGISTERS_PHYS_QNUM1_0 0x134UL
+#define CCM_REGISTERS_PHYS_QNUM1_1 0x138UL
+#define CCM_REGISTERS_PHYS_QNUM2_0 0x13cUL
+#define CCM_REGISTERS_PHYS_QNUM2_1 0x140UL
+#define CCM_REGISTERS_PHYS_QNUM3_0 0x144UL
+#define CCM_REGISTERS_PHYS_QNUM3_1 0x148UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM0_0 0x114UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM0_1 0x118UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM1_0 0x11cUL
+#define CCM_REGISTERS_QOS_PHYS_QNUM1_1 0x120UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM2_0 0x124UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM2_1 0x128UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM3_0 0x12cUL
+#define CCM_REGISTERS_QOS_PHYS_QNUM3_1 0x130UL
+#define CCM_REGISTERS_STORM_CCM_IFEN 0x10UL
+#define CCM_REGISTERS_STORM_LENGTH_MIS 0x16cUL
+#define CCM_REGISTERS_TSEM_IFEN 0x1cUL
+#define CCM_REGISTERS_TSEM_LENGTH_MIS 0x174UL
+#define CCM_REGISTERS_TSEM_WEIGHT 0xa0UL
+#define CCM_REGISTERS_USEM_IFEN 0x24UL
+#define CCM_REGISTERS_USEM_LENGTH_MIS 0x17cUL
+#define CCM_REGISTERS_USEM_WEIGHT 0xa8UL
+#define CCM_REGISTERS_XSEM_IFEN 0x20UL
+#define CCM_REGISTERS_XSEM_LENGTH_MIS 0x178UL
+#define CCM_REGISTERS_XSEM_WEIGHT 0xa4UL
+#define CCM_REGISTERS_XX_DESCR_TABLE 0x300UL
+#define CCM_REGISTERS_XX_DESCR_TABLE_SIZE 36
+#define CCM_REGISTERS_XX_INIT_CRD 0x220UL
+#define CCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_XX_MSG_NUM 0x224UL
+#define CCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define CCM_REGISTERS_XX_OVFL_EVNT_ID 0x44UL
+#define CCM_REGISTERS_XX_TABLE 0x280UL
+#define CCM_REGISTERS_XX_TABLE_SIZE 18
+#define CDU_REGISTERS_CDU_CHK_MASK0 0x0UL
+#define CDU_REGISTERS_CDU_CHK_MASK1 0x4UL
+#define CDU_REGISTERS_CDU_CONTROL0 0x8UL
+#define CDU_REGISTERS_CDU_GLOBAL_PARAMS 0x20UL
+#define CDU_REGISTERS_CDU_INT_STS 0x30UL
+#define CDU_REGISTERS_CDU_INT_STS_CLR 0x34UL
+#define CDU_REGISTERS_CDU_INT_STS_WR 0x38UL
+#define CDU_REGISTERS_ERROR_DATA 0x14UL
+#define CDU_REGISTERS_L1TT 0x800UL
+#define CDU_REGISTERS_L1TT_SIZE 512
+#define CDU_REGISTERS_MATT 0x100UL
+#define CDU_REGISTERS_MATT_SIZE 64
+#define CFC_REGISTERS_AC_INIT_DONE 0x78UL
+#define CFC_REGISTERS_ACTIVITY_COUNTER 0x400UL
+#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256
+#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256
+#define CFC_REGISTERS_CAM_INIT_DONE 0x7cUL
+#define CFC_REGISTERS_CFC_INT_STS 0xfcUL
+#define CFC_REGISTERS_CFC_INT_STS_CLR 0x100UL
+#define CFC_REGISTERS_CFC_INT_STS_WR 0x104UL
+#define CFC_REGISTERS_CONTROL0 0x28UL
+#define CFC_REGISTERS_DEBUG0 0x50UL
+#define CFC_REGISTERS_DISABLE_ON_ERROR 0x44UL
+#define CFC_REGISTERS_ERROR_VECTOR 0x3cUL
+#define CFC_REGISTERS_INIT_REG 0x4cUL
+#define CFC_REGISTERS_LCREQ_WEIGHTS 0x84UL
+#define CFC_REGISTERS_LL_INIT_DONE 0x74UL
+#define CFC_REGISTERS_NUM_LCIDS_ALLOC 0x20UL
+#define CFC_REGISTERS_NUM_LCIDS_ARRIVING 0x4UL
+#define CFC_REGISTERS_NUM_LCIDS_INSIDE 0x8UL
+#define CFC_REGISTERS_NUM_LCIDS_LEAVING 0x18UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define CSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define CSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define CSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define CSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define CSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define CSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define CSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define CSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define CSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define CSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define CSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define CSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define CSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define CSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define CSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define CSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define CSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define CSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define CSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define CSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define CSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define CSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define CSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define CSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define CSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define CSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define CSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define CSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define CSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define CSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define CSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define CSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define CSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define CSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define CSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define CSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define CSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define CSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define CSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define CSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define CSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define CSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define CSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define CSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define CSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define CSDM_REGISTERS_TIMER_TICK 0x0UL
+#define CSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define CSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define CSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define CSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define CSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define CSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define CSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define CSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define CSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define CSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define CSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define CSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define CSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define CSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define CSEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define CSEM_REGISTERS_INT_TABLE 0x400UL
+#define CSEM_REGISTERS_INT_TABLE_SIZE 256
+#define CSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define CSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define CSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define CSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define CSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define CSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define CSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define CSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define CSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define CSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define CSEM_REGISTERS_PRAM 0x40000UL
+#define CSEM_REGISTERS_PRAM_SIZE 65536
+#define CSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define CSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define CSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define CSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define CSEM_REGISTERS_TS_0_AS 0x38UL
+#define CSEM_REGISTERS_TS_10_AS 0x60UL
+#define CSEM_REGISTERS_TS_11_AS 0x64UL
+#define CSEM_REGISTERS_TS_12_AS 0x68UL
+#define CSEM_REGISTERS_TS_13_AS 0x6cUL
+#define CSEM_REGISTERS_TS_14_AS 0x70UL
+#define CSEM_REGISTERS_TS_15_AS 0x74UL
+#define CSEM_REGISTERS_TS_16_AS 0x78UL
+#define CSEM_REGISTERS_TS_17_AS 0x7cUL
+#define CSEM_REGISTERS_TS_18_AS 0x80UL
+#define CSEM_REGISTERS_TS_19_AS 0x84UL
+#define CSEM_REGISTERS_TS_1_AS 0x3cUL
+#define CSEM_REGISTERS_TS_2_AS 0x40UL
+#define CSEM_REGISTERS_TS_3_AS 0x44UL
+#define CSEM_REGISTERS_TS_4_AS 0x48UL
+#define CSEM_REGISTERS_TS_5_AS 0x4cUL
+#define CSEM_REGISTERS_TS_6_AS 0x50UL
+#define CSEM_REGISTERS_TS_7_AS 0x54UL
+#define CSEM_REGISTERS_TS_8_AS 0x58UL
+#define CSEM_REGISTERS_TS_9_AS 0x5cUL
+#define DMAE_REGISTERS_CMD_MEM 0x400UL
+#define DMAE_REGISTERS_CMD_MEM_SIZE 224
+#define DMAE_REGISTERS_CRC16C_INIT 0x1cUL
+#define DMAE_REGISTERS_CRC16T10_INIT 0x20UL
+#define DMAE_REGISTERS_GO_C0 0x80UL
+#define DMAE_REGISTERS_GO_C0_SIZE 1
+#define DMAE_REGISTERS_GO_C1 0x84UL
+#define DMAE_REGISTERS_GO_C1_SIZE 1
+#define DMAE_REGISTERS_GO_C10 0x88UL
+#define DMAE_REGISTERS_GO_C10_SIZE 1
+#define DMAE_REGISTERS_GO_C11 0x8cUL
+#define DMAE_REGISTERS_GO_C11_SIZE 1
+#define DMAE_REGISTERS_GO_C12 0x90UL
+#define DMAE_REGISTERS_GO_C12_SIZE 1
+#define DMAE_REGISTERS_GO_C13 0x94UL
+#define DMAE_REGISTERS_GO_C13_SIZE 1
+#define DMAE_REGISTERS_GO_C14 0x98UL
+#define DMAE_REGISTERS_GO_C14_SIZE 1
+#define DMAE_REGISTERS_GO_C15 0x9cUL
+#define DMAE_REGISTERS_GO_C15_SIZE 1
+#define DMAE_REGISTERS_GO_C10 0x88UL
+#define DMAE_REGISTERS_GO_C10_SIZE 1
+#define DMAE_REGISTERS_GO_C11 0x8cUL
+#define DMAE_REGISTERS_GO_C11_SIZE 1
+#define DMAE_REGISTERS_GO_C12 0x90UL
+#define DMAE_REGISTERS_GO_C12_SIZE 1
+#define DMAE_REGISTERS_GO_C13 0x94UL
+#define DMAE_REGISTERS_GO_C13_SIZE 1
+#define DMAE_REGISTERS_GO_C14 0x98UL
+#define DMAE_REGISTERS_GO_C14_SIZE 1
+#define DMAE_REGISTERS_GO_C15 0x9cUL
+#define DMAE_REGISTERS_GO_C15_SIZE 1
+#define DMAE_REGISTERS_GO_C2 0xa0UL
+#define DMAE_REGISTERS_GO_C2_SIZE 1
+#define DMAE_REGISTERS_GO_C3 0xa4UL
+#define DMAE_REGISTERS_GO_C3_SIZE 1
+#define DMAE_REGISTERS_GO_C4 0xa8UL
+#define DMAE_REGISTERS_GO_C4_SIZE 1
+#define DMAE_REGISTERS_GO_C5 0xacUL
+#define DMAE_REGISTERS_GO_C5_SIZE 1
+#define DMAE_REGISTERS_GO_C6 0xb0UL
+#define DMAE_REGISTERS_GO_C6_SIZE 1
+#define DMAE_REGISTERS_GO_C7 0xb4UL
+#define DMAE_REGISTERS_GO_C7_SIZE 1
+#define DMAE_REGISTERS_GO_C8 0xb8UL
+#define DMAE_REGISTERS_GO_C8_SIZE 1
+#define DMAE_REGISTERS_GO_C9 0xbcUL
+#define DMAE_REGISTERS_GO_C9_SIZE 1
+#define DMAE_REGISTERS_GRC_IFEN 0x8UL
+#define DMAE_REGISTERS_PCI_IFEN 0x4UL
+#define DMAE_REGISTERS_PXP_REQ_INIT_CRD 0xc0UL
+#define DMAE_REGISTERS_PXP_REQ_INIT_CRD_SIZE 1
+#define DORQ_REGISTERS_AGG_CMD0 0x60UL
+#define DORQ_REGISTERS_AGG_CMD1 0x64UL
+#define DORQ_REGISTERS_AGG_CMD2 0x68UL
+#define DORQ_REGISTERS_AGG_CMD3 0x6cUL
+#define DORQ_REGISTERS_CMHEAD_RX 0x50UL
+#define DORQ_REGISTERS_DORQ_INT_MASK 0x180UL
+#define DORQ_REGISTERS_DORQ_INT_STS 0x174UL
+#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL
+#define DORQ_REGISTERS_DORQ_INT_STS_WR 0x17cUL
+#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL
+#define DORQ_REGISTERS_DPM_CID_ADDR 0x44UL
+#define DORQ_REGISTERS_DPM_CID_OFST 0x30UL
+#define DORQ_REGISTERS_DQ_FIFO_AFULL_TH 0x7cUL
+#define DORQ_REGISTERS_DQ_FIFO_FULL_TH 0x78UL
+#define DORQ_REGISTERS_DQ_FILL_LVLF 0xa4UL
+#define DORQ_REGISTERS_DQ_FULL_ST 0xc0UL
+#define DORQ_REGISTERS_ERR_CMHEAD 0x58UL
+#define DORQ_REGISTERS_IF_EN 0x4UL
+#define DORQ_REGISTERS_MODE_ACT 0x8UL
+#define DORQ_REGISTERS_NORM_CID_OFST 0x2cUL
+#define DORQ_REGISTERS_NORM_CMHEAD_TX 0x4cUL
+#define DORQ_REGISTERS_OUTST_REQ 0x3cUL
+#define DORQ_REGISTERS_OUTST_REQ_CNT 0xa8UL
+#define DORQ_REGISTERS_REGN 0x38UL
+#define DORQ_REGISTERS_RSPA_CRD_CNT 0xacUL
+#define DORQ_REGISTERS_RSP_INIT_CRD 0x48UL
+#define DORQ_REGISTERS_SHRT_ACT_CNT 0x70UL
+#define DORQ_REGISTERS_SHRT_CMHEAD 0x54UL
+#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0 (0x1<<4)
+#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0_SIZE 4
+#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0 (0x1<<3)
+#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0_SIZE 3
+#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0 (0x1<<2)
+#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0_SIZE 2
+#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0 (0x1<<1)
+#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0_SIZE 1
+#define HC_REGISTERS_AGG_INT_0 0x50UL
+#define HC_REGISTERS_AGG_INT_1 0x54UL
+#define HC_REGISTERS_ATTN_BIT 0x120UL
+#define HC_REGISTERS_ATTN_BIT_SIZE 4
+#define HC_REGISTERS_ATTN_IDX 0x100UL
+#define HC_REGISTERS_ATTN_IDX_SIZE 2
+#define HC_REGISTERS_ATTN_MSG0_ADDR_L 0x18UL
+#define HC_REGISTERS_ATTN_MSG1_ADDR_L 0x20UL
+#define HC_REGISTERS_ATTN_NUM_P0 0x38UL
+#define HC_REGISTERS_ATTN_NUM_P1 0x3cUL
+#define HC_REGISTERS_CONFIG_0 0x0UL
+#define HC_REGISTERS_CONFIG_1 0x4UL
+#define HC_REGISTERS_CSTORM_ADDR_FOR_COALESCE 0x6cUL
+#define HC_REGISTERS_INT_MASK 0x108UL
+#define HC_REGISTERS_INT_MASK_SIZE 2
+#define HC_REGISTERS_LEADING_EDGE_0 0x40UL
+#define HC_REGISTERS_LEADING_EDGE_1 0x48UL
+#define HC_REGISTERS_P0_PROD_CONS 0x200UL
+#define HC_REGISTERS_P0_PROD_CONS_SIZE 74
+#define HC_REGISTERS_P1_PROD_CONS 0x400UL
+#define HC_REGISTERS_P1_PROD_CONS_SIZE 74
+#define HC_REGISTERS_PBA_COMMAND 0x140UL
+#define HC_REGISTERS_PBA_COMMAND_SIZE 4
+#define HC_REGISTERS_PCI_CONFIG_0 0x10UL
+#define HC_REGISTERS_PCI_CONFIG_1 0x14UL
+#define HC_REGISTERS_STATISTIC_COUNTERS 0x1000UL
+#define HC_REGISTERS_STATISTIC_COUNTERS_SIZE 516
+#define HC_REGISTERS_TRAILING_EDGE_0 0x44UL
+#define HC_REGISTERS_TRAILING_EDGE_1 0x4cUL
+#define HC_REGISTERS_TSTORM_ADDR_FOR_COALESCE 0x74UL
+#define HC_REGISTERS_UC_RAM_ADDR_0 0x28UL
+#define HC_REGISTERS_UC_RAM_ADDR_1 0x30UL
+#define HC_REGISTERS_USTORM_ADDR_FOR_COALESCE 0x68UL
+#define HC_REGISTERS_VQID_0 0x8UL
+#define HC_REGISTERS_VQID_1 0xcUL
+#define HC_REGISTERS_XSTORM_ADDR_FOR_COALESCE 0x70UL
+#define HC_REGISTERS_XT_RAM_ADDR_0 0x2cUL
+#define HC_REGISTERS_XT_RAM_ADDR_1 0x34UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0 0x42cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1 0x430UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP 0x434UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0 0x438UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1 0x43cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP 0x440UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0 0x444UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1 0x448UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP 0x44cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0 0x450UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1 0x454UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP 0x458UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL 0x45cUL
+#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL_SIZE 1
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_0 0x6cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_1 0x7cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_2 0x8cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_3 0x9cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_4 0xacUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_5 0xbcUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_6 0xccUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_7 0xdcUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_0 0x10cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_1 0x11cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_2 0x12cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_3 0x13cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_4 0x14cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_5 0x15cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_6 0x16cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_7 0x17cUL
+#define MISC_REGISTERS_AEU_ENABLE1_NIG_0 0xecUL
+#define MISC_REGISTERS_AEU_ENABLE1_NIG_1 0x18cUL
+#define MISC_REGISTERS_AEU_ENABLE1_PXP_0 0xfcUL
+#define MISC_REGISTERS_AEU_ENABLE1_PXP_1 0x19cUL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_0 0x70UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_1 0x80UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_2 0x90UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_3 0xa0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_4 0xb0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_5 0xc0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_6 0xd0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_7 0xe0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_0 0x110UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_1 0x120UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_2 0x130UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_3 0x140UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_4 0x150UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_5 0x160UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_6 0x170UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_7 0x180UL
+#define MISC_REGISTERS_AEU_ENABLE2_NIG_0 0xf0UL
+#define MISC_REGISTERS_AEU_ENABLE2_NIG_1 0x190UL
+#define MISC_REGISTERS_AEU_ENABLE2_PXP_0 0x100UL
+#define MISC_REGISTERS_AEU_ENABLE2_PXP_1 0x1a0UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_0 0x74UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_1 0x84UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_2 0x94UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_3 0xa4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_4 0xb4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_5 0xc4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_6 0xd4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_7 0xe4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_0 0x114UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_1 0x124UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_2 0x134UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_3 0x144UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_4 0x154UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_5 0x164UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_6 0x174UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_7 0x184UL
+#define MISC_REGISTERS_AEU_ENABLE3_NIG_0 0xf4UL
+#define MISC_REGISTERS_AEU_ENABLE3_NIG_1 0x194UL
+#define MISC_REGISTERS_AEU_ENABLE3_PXP_0 0x104UL
+#define MISC_REGISTERS_AEU_ENABLE3_PXP_1 0x1a4UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_0 0x78UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_1 0x88UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_2 0x98UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_3 0xa8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_4 0xb8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_5 0xc8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_6 0xd8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_7 0xe8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_0 0x118UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_1 0x128UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_2 0x138UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_3 0x148UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_4 0x158UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_5 0x168UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_6 0x178UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_7 0x188UL
+#define MISC_REGISTERS_AEU_ENABLE4_NIG_0 0xf8UL
+#define MISC_REGISTERS_AEU_ENABLE4_NIG_1 0x198UL
+#define MISC_REGISTERS_AEU_ENABLE4_PXP_0 0x108UL
+#define MISC_REGISTERS_AEU_ENABLE4_PXP_1 0x1a8UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_0 0x0UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_1 0x4UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_2 0x8UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_3 0xcUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_4 0x10UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_5 0x14UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_6 0x18UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_7 0x1cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_8 0x20UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_9 0x24UL
+#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_0 0x22cUL
+#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_1 0x23cUL
+#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_0 0x230UL
+#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_1 0x240UL
+#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_0 0x234UL
+#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_1 0x244UL
+#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_0 0x238UL
+#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_1 0x248UL
+#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0 0x60UL
+#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 0x64UL
+#define MISC_REGISTERS_BOND_ID 0x400UL
+#define MISC_REGISTERS_BOND_ID_SIZE 1
+#define MISC_REGISTERS_CHIP_METAL 0x404UL
+#define MISC_REGISTERS_CHIP_METAL_SIZE 1
+#define MISC_REGISTERS_CHIP_NUM 0x408UL
+#define MISC_REGISTERS_CHIP_NUM_SIZE 1
+#define MISC_REGISTERS_CHIP_REV 0x40cUL
+#define MISC_REGISTERS_CHIP_REV_SIZE 1
+#define MISC_REGISTERS_GRC_TIMEOUT_EN 0x280UL
+#define MISC_REGISTERS_LCPLL_CTRL_1 0x2a4UL
+#define MISC_REGISTERS_LCPLL_CTRL_REG_2 0x2a8UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_1 0x294UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_2 0x298UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_3 0x29cUL
+#define MISC_REGISTERS_PLL_STORM_CTRL_4 0x2a0UL
+#define MISC_REGISTERS_RESET_REG_1 0x580UL
+#define MISC_REGISTERS_RESET_REG_1_SIZE 3
+#define MISC_REGISTERS_RESET_REG_2 0x590UL
+#define MISC_REGISTERS_RESET_REG_2_SIZE 3
+#define MISC_REGISTERS_RESET_REG_3 0x5a0UL
+#define MISC_REGISTERS_RESET_REG_3_SIZE 3
+#define MISC_REGISTERS_RESET_REG_1 0x580UL
+#define MISC_REGISTERS_RESET_REG_1_SIZE 3
+#define MISC_REGISTERS_RESET_REG_2 0x590UL
+#define MISC_REGISTERS_RESET_REG_2_SIZE 3
+#define MISC_REGISTERS_SHARED_MEM_ADDR 0x2b4UL
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT (0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT_SIZE 0
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS
(0x1<<9)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS_SIZE 9
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G (0x1<<15)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G_SIZE 15
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS (0xf<<18)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS_SIZE 18
+#define NIG_REGISTERS_BMAC0_IN_EN 0xacUL
+#define NIG_REGISTERS_BMAC0_OUT_EN 0xe0UL
+#define NIG_REGISTERS_BMAC0_PAUSE_OUT_EN 0x110UL
+#define NIG_REGISTERS_BMAC0_REGS_OUT_EN 0xe8UL
+#define NIG_REGISTERS_BRB0_OUT_EN 0xf8UL
+#define NIG_REGISTERS_BRB0_PAUSE_IN_EN 0xc4UL
+#define NIG_REGISTERS_BRB1_OUT_EN 0xfcUL
+#define NIG_REGISTERS_BRB1_PAUSE_IN_EN 0xc8UL
+#define NIG_REGISTERS_BRB_LB_OUT_EN 0x100UL
+#define NIG_REGISTERS_DEBUG_PACKET_LB 0x800UL
+#define NIG_REGISTERS_DEBUG_PACKET_LB_SIZE 3
+#define NIG_REGISTERS_EGRESS_DEBUG_IN_EN 0xdcUL
+#define NIG_REGISTERS_EGRESS_DRAIN0_MODE 0x60UL
+#define NIG_REGISTERS_EGRESS_EMAC0_OUT_EN 0x120UL
+#define NIG_REGISTERS_EGRESS_EMAC0_PORT 0x58UL
+#define NIG_REGISTERS_EGRESS_PBF0_IN_EN 0xccUL
+#define NIG_REGISTERS_EGRESS_PBF1_IN_EN 0xd0UL
+#define NIG_REGISTERS_EMAC0_IN_EN 0xa4UL
+#define NIG_REGISTERS_EMAC0_PAUSE_OUT_EN 0x118UL
+#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT 0x494UL
+#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT_SIZE 1
+#define NIG_REGISTERS_INGRESS_BMAC0_MEM 0xc00UL
+#define NIG_REGISTERS_INGRESS_BMAC0_MEM_SIZE 256
+#define NIG_REGISTERS_INGRESS_BMAC1_MEM 0x1000UL
+#define NIG_REGISTERS_INGRESS_BMAC1_MEM_SIZE 256
+#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY 0x4e0UL
+#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY_SIZE 1
+#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO 0x4e4UL
+#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO_SIZE 1
+#define NIG_REGISTERS_LED_10G_P0 0x320UL
+#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_ENA_P0 0x318UL
+#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_P0 0x310UL
+#define NIG_REGISTERS_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x2f8UL
+#define NIG_REGISTERS_LED_MODE_P0 0x2f0UL
+#define NIG_REGISTERS_LLH0_BRB1_DRV_MASK 0x244UL
+#define NIG_REGISTERS_LLH0_BRB1_NOT_MCP 0x25cUL
+#define NIG_REGISTERS_LLH0_CM_HEADER 0x7cUL
+#define NIG_REGISTERS_LLH0_ERROR_MASK 0x8cUL
+#define NIG_REGISTERS_LLH0_EVENT_ID 0x84UL
+#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT 0x554UL
+#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT_SIZE 1
+#define NIG_REGISTERS_LLH0_XCM_MASK 0x130UL
+#define NIG_REGISTERS_LLH1_BRB1_NOT_MCP 0x2dcUL
+#define NIG_REGISTERS_LLH1_CM_HEADER 0x80UL
+#define NIG_REGISTERS_LLH1_ERROR_MASK 0x90UL
+#define NIG_REGISTERS_LLH1_EVENT_ID 0x88UL
+#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT 0x564UL
+#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT_SIZE 1
+#define NIG_REGISTERS_LLH1_XCM_MASK 0x134UL
+#define NIG_REGISTERS_MASK_INTERRUPT_PORT0 0x330UL
+#define NIG_REGISTERS_MASK_INTERRUPT_PORT1 0x334UL
+#define NIG_REGISTERS_NIG_EMAC0_EN 0x3cUL
+#define NIG_REGISTERS_NIG_INGRESS_EMAC0_NO_CRC 0x44UL
+#define NIG_REGISTERS_PBF_LB_IN_EN 0xb4UL
+#define NIG_REGISTERS_PRS_EOP_OUT_EN 0x104UL
+#define NIG_REGISTERS_PRS_REQ_IN_EN 0xb8UL
+#define NIG_REGISTERS_SERDES0_CTRL_PHY_ADDR 0x374UL
+#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS 0x578UL
+#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS_SIZE 1
+#define NIG_REGISTERS_STAT0_BRB_DISCARD 0x5f0UL
+#define NIG_REGISTERS_STAT0_BRB_DISCARD_SIZE 1
+#define NIG_REGISTERS_STAT1_BRB_DISCARD 0x628UL
+#define NIG_REGISTERS_STAT1_BRB_DISCARD_SIZE 1
+#define NIG_REGISTERS_STAT2_BRB_OCTET 0x7e0UL
+#define NIG_REGISTERS_STAT2_BRB_OCTET_SIZE 2
+#define NIG_REGISTERS_STATUS_INTERRUPT_PORT0 0x328UL
+#define NIG_REGISTERS_STATUS_INTERRUPT_PORT1 0x32cUL
+#define NIG_REGISTERS_XCM0_OUT_EN 0xf0UL
+#define NIG_REGISTERS_XCM1_OUT_EN 0xf4UL
+#define NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD 0x33cUL
+#define NIG_REGISTERS_XGXS0_CTRL_PHY_ADDR 0x340UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK10G 0x680UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK10G_SIZE 1
+#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS 0x684UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS_SIZE 1
+#define NIG_REGISTERS_XGXS_LANE_SEL_P0 0x2e8UL
+#define NIG_REGISTERS_XGXS_SERDES0_MODE_SEL 0x2e0UL
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS
(0x1<<9)
+#define
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS_SIZE 9
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G (0x1<<15)
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G_SIZE 15
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS
(0xf<<18)
+#define
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18
+#define
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0 0x5cUL
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P1 0x60UL
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P4 0x6cUL
+#define PBF_REGISTERS_IF_ENABLE_REG 0x44UL
+#define PBF_REGISTERS_INIT 0x0UL
+#define PBF_REGISTERS_INIT_P0 0x4UL
+#define PBF_REGISTERS_INIT_P1 0x8UL
+#define PBF_REGISTERS_INIT_P4 0xcUL
+#define PBF_REGISTERS_INIT_P0 0x4UL
+#define PBF_REGISTERS_INIT_P1 0x8UL
+#define PBF_REGISTERS_INIT_P4 0xcUL
+#define PBF_REGISTERS_MAC_IF0_ENABLE 0x30UL
+#define PBF_REGISTERS_MAC_IF1_ENABLE 0x34UL
+#define PBF_REGISTERS_MAC_LB_ENABLE 0x40UL
+#define PBF_REGISTERS_P0_ARB_THRSH 0xe4UL
+#define PBF_REGISTERS_P0_CREDIT 0x200UL
+#define PBF_REGISTERS_P0_CREDIT_SIZE 1
+#define PBF_REGISTERS_P0_INIT_CRD 0xd0UL
+#define PBF_REGISTERS_P0_PAUSE_ENABLE 0x14UL
+#define PBF_REGISTERS_P0_TASK_CNT 0x204UL
+#define PBF_REGISTERS_P0_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_P1_CREDIT 0x208UL
+#define PBF_REGISTERS_P1_CREDIT_SIZE 1
+#define PBF_REGISTERS_P1_INIT_CRD 0xd4UL
+#define PBF_REGISTERS_P1_TASK_CNT 0x20cUL
+#define PBF_REGISTERS_P1_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_P4_CREDIT 0x210UL
+#define PBF_REGISTERS_P4_CREDIT_SIZE 1
+#define PBF_REGISTERS_P4_INIT_CRD 0xe0UL
+#define PBF_REGISTERS_P4_TASK_CNT 0x214UL
+#define PBF_REGISTERS_P4_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_PBF_INT_STS 0x1c8UL
+#define PBF_REGISTERS_PBF_INT_STS_CLR 0x1ccUL
+#define PBF_REGISTERS_PBF_INT_STS_WR 0x1d0UL
+#define PB_REGISTERS_CONTROL 0x0UL
+#define PB_REGISTERS_PB_INT_STS 0x1cUL
+#define PB_REGISTERS_PB_INT_STS_CLR 0x20UL
+#define PB_REGISTERS_PB_INT_STS_WR 0x24UL
+#define PRS_REGISTERS_CFC_LD_CURRENT_CREDIT 0x164UL
+#define PRS_REGISTERS_CFC_SEARCH_CURRENT_CREDIT 0x168UL
+#define PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT 0x11cUL
+#define PRS_REGISTERS_CID_PORT_0 0xfcUL
+#define PRS_REGISTERS_CID_PORT_1 0x100UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_0 0xdcUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_1 0xe0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_2 0xe4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_3 0xe8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_4 0xecUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_5 0xf0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_6 0xf4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_7 0xf8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0xbcUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0xc0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0xc4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0xc8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0xccUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0xd0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_6 0xd4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_7 0xd8UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_0 0x98UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_1 0x9cUL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_2 0xa0UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_3 0xa4UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_4 0xa8UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_5 0xacUL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_6 0xb0UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_7 0xb4UL
+#define PRS_REGISTERS_CM_HDR_TYPE_0 0x78UL
+#define PRS_REGISTERS_CM_HDR_TYPE_1 0x7cUL
+#define PRS_REGISTERS_CM_HDR_TYPE_2 0x80UL
+#define PRS_REGISTERS_CM_HDR_TYPE_3 0x84UL
+#define PRS_REGISTERS_CM_HDR_TYPE_4 0x88UL
+#define PRS_REGISTERS_CM_HDR_TYPE_5 0x8cUL
+#define PRS_REGISTERS_CM_HDR_TYPE_6 0x90UL
+#define PRS_REGISTERS_CM_HDR_TYPE_7 0x94UL
+#define PRS_REGISTERS_CM_NO_MATCH_HDR 0xb8UL
+#define PRS_REGISTERS_EVENT_ID_1 0x54UL
+#define PRS_REGISTERS_EVENT_ID_2 0x58UL
+#define PRS_REGISTERS_EVENT_ID_3 0x5cUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_0 0x4UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_1 0x8UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_2 0xcUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_3 0x10UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_4 0x14UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_5 0x18UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_6 0x1cUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_7 0x20UL
+#define PRS_REGISTERS_INC_VALUE 0x48UL
+#define PRS_REGISTERS_NIC_MODE 0x138UL
+#define PRS_REGISTERS_NO_MATCH_EVENT_ID 0x70UL
+#define PRS_REGISTERS_NUM_OF_CFC_FLUSH_MESSAGES 0x128UL
+#define PRS_REGISTERS_NUM_OF_DEAD_CYCLES 0x130UL
+#define PRS_REGISTERS_NUM_OF_PACKETS 0x124UL
+#define PRS_REGISTERS_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x12cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_0 0x28UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_1 0x2cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_2 0x30UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_3 0x34UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_4 0x38UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_5 0x3cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_6 0x40UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_7 0x44UL
+#define PRS_REGISTERS_PENDING_BRB_CAC0_RQ 0x174UL
+#define PRS_REGISTERS_PENDING_BRB_CAC1_RQ 0x178UL
+#define PRS_REGISTERS_PENDING_BRB_CAC2_RQ 0x17cUL
+#define PRS_REGISTERS_PENDING_BRB_CAC3_RQ 0x180UL
+#define PRS_REGISTERS_PENDING_BRB_CAC4_RQ 0x184UL
+#define PRS_REGISTERS_PENDING_BRB_PRS_RQ 0x170UL
+#define PRS_REGISTERS_PRS_INT_STS 0x188UL
+#define PRS_REGISTERS_PRS_INT_STS_CLR 0x18cUL
+#define PRS_REGISTERS_PRS_INT_STS_WR 0x190UL
+#define PRS_REGISTERS_PURE_REGIONS 0x24UL
+#define PRS_REGISTERS_SERIAL_NUM_STATUS_LSB 0x154UL
+#define PRS_REGISTERS_SERIAL_NUM_STATUS_MSB 0x158UL
+#define PRS_REGISTERS_SRC_CURRENT_CREDIT 0x16cUL
+#define PRS_REGISTERS_TCM_CURRENT_CREDIT 0x160UL
+#define PRS_REGISTERS_TSDM_CURRENT_CREDIT 0x15cUL
+#define PXP2_REGISTERS_HST_DATA_FIFO_STATUS 0x47cUL
+#define PXP2_REGISTERS_HST_HEADER_FIFO_STATUS 0x478UL
+#define PXP2_REGISTERS_PGL_CONTROL0 0x490UL
+#define PXP2_REGISTERS_PGL_CONTROL1 0x514UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_0 0x4f4UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_1 0x4f8UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_2 0x4fcUL
+#define PXP2_REGISTERS_PGL_INT_CSDM_3 0x500UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_4 0x504UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_5 0x508UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_6 0x50cUL
+#define PXP2_REGISTERS_PGL_INT_CSDM_7 0x510UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_0 0x494UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_1 0x498UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_2 0x49cUL
+#define PXP2_REGISTERS_PGL_INT_TSDM_3 0x4a0UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_4 0x4a4UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_5 0x4a8UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_6 0x4acUL
+#define PXP2_REGISTERS_PGL_INT_TSDM_7 0x4b0UL
+#define PXP2_REGISTERS_PGL_INT_USDM_0 0x4b4UL
+#define PXP2_REGISTERS_PGL_INT_USDM_1 0x4b8UL
+#define PXP2_REGISTERS_PGL_INT_USDM_2 0x4bcUL
+#define PXP2_REGISTERS_PGL_INT_USDM_3 0x4c0UL
+#define PXP2_REGISTERS_PGL_INT_USDM_4 0x4c4UL
+#define PXP2_REGISTERS_PGL_INT_USDM_5 0x4c8UL
+#define PXP2_REGISTERS_PGL_INT_USDM_6 0x4ccUL
+#define PXP2_REGISTERS_PGL_INT_USDM_7 0x4d0UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_0 0x4d4UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_1 0x4d8UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_2 0x4dcUL
+#define PXP2_REGISTERS_PGL_INT_XSDM_3 0x4e0UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_4 0x4e4UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_5 0x4e8UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_6 0x4ecUL
+#define PXP2_REGISTERS_PGL_INT_XSDM_7 0x4f0UL
+#define PXP2_REGISTERS_PGL_READ_BLOCKED 0x568UL
+#define PXP2_REGISTERS_PGL_TXR_CDTS 0x528UL
+#define PXP2_REGISTERS_PGL_TXW_CDTS 0x52cUL
+#define PXP2_REGISTERS_PGL_WRITE_BLOCKED 0x564UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD1 0x1c0UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD2 0x1c4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD3 0x1c8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD6 0x1d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD7 0x1d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD8 0x1dcUL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD9 0x1e0UL
+#define PXP2_REGISTERS_PSWRQ_BW_CREDIT 0x32cUL
+#define PXP2_REGISTERS_PSWRQ_BW_L1 0x2b0UL
+#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L2 0x2b4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL
+#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL
+#define PXP2_REGISTERS_PSWRQ_BW_L3 0x2b8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L6 0x2c4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L7 0x2c8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L8 0x2ccUL
+#define PXP2_REGISTERS_PSWRQ_BW_L9 0x2d0UL
+#define PXP2_REGISTERS_PSWRQ_BW_RD 0x324UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB1 0x238UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB2 0x23cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB3 0x240UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB6 0x24cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB7 0x250UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB8 0x254UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB9 0x258UL
+#define PXP2_REGISTERS_PSWRQ_BW_WR 0x328UL
+#define PXP2_REGISTERS_PSWRQ_CDU0_L2P 0x0UL
+#define PXP2_REGISTERS_PSWRQ_CDU1_L2P 0x4UL
+#define PXP2_REGISTERS_PSWRQ_QM0_L2P 0x38UL
+#define PXP2_REGISTERS_PSWRQ_QM1_L2P 0x3cUL
+#define PXP2_REGISTERS_PSWRQ_SRC0_L2P 0x54UL
+#define PXP2_REGISTERS_PSWRQ_SRC1_L2P 0x58UL
+#define PXP2_REGISTERS_PSWRQ_TM0_L2P 0x1cUL
+#define PXP2_REGISTERS_PSWRQ_TM1_L2P 0x20UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_0 0x424UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_1 0x428UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_2 0x42cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_3 0x430UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_4 0x434UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_5 0x438UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_6 0x43cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_7 0x440UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_8 0x444UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_9 0x448UL
+#define PXP2_REGISTERS_RD_BLK_CNT 0x418UL
+#define PXP2_REGISTERS_RD_BLK_NUM_CFG 0x40cUL
+#define PXP2_REGISTERS_RD_CDURD_SWAP_MODE 0x404UL
+#define PXP2_REGISTERS_RD_DISABLE_INPUTS 0x374UL
+#define PXP2_REGISTERS_RD_INIT_DONE 0x370UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ10 0x3a0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ11 0x3a4UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ17 0x3bcUL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ18 0x3c0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ19 0x3c4UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ22 0x3d0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ6 0x390UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ9 0x39cUL
+#define PXP2_REGISTERS_RD_PBF_SWAP_MODE 0x3f4UL
+#define PXP2_REGISTERS_RD_PORT_IS_IDLE_0 0x41cUL
+#define PXP2_REGISTERS_RD_PORT_IS_IDLE_1 0x420UL
+#define PXP2_REGISTERS_RD_QM_SWAP_MODE 0x3f8UL
+#define PXP2_REGISTERS_RD_SR_CNT 0x414UL
+#define PXP2_REGISTERS_RD_SRC_SWAP_MODE 0x400UL
+#define PXP2_REGISTERS_RD_SR_NUM_CFG 0x408UL
+#define PXP2_REGISTERS_RD_START_INIT 0x36cUL
+#define PXP2_REGISTERS_RD_TM_SWAP_MODE 0x3fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD0 0x1bcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD12 0x1ecUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD13 0x1f0UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD14 0x1f4UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD15 0x1f8UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD16 0x1fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD17 0x200UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD18 0x204UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD19 0x208UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD20 0x20cUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD22 0x210UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD23 0x214UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD24 0x218UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD25 0x21cUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD26 0x220UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD27 0x224UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD4 0x1ccUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD5 0x1d0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L0 0x2acUL
+#define PXP2_REGISTERS_RQ_BW_RD_L12 0x2dcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L13 0x2e0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L14 0x2e4UL
+#define PXP2_REGISTERS_RQ_BW_RD_L15 0x2e8UL
+#define PXP2_REGISTERS_RQ_BW_RD_L16 0x2ecUL
+#define PXP2_REGISTERS_RQ_BW_RD_L17 0x2f0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L18 0x2f4UL
+#define PXP2_REGISTERS_RQ_BW_RD_L19 0x2f8UL
+#define PXP2_REGISTERS_RQ_BW_RD_L20 0x2fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L22 0x300UL
+#define PXP2_REGISTERS_RQ_BW_RD_L23 0x304UL
+#define PXP2_REGISTERS_RQ_BW_RD_L24 0x308UL
+#define PXP2_REGISTERS_RQ_BW_RD_L25 0x30cUL
+#define PXP2_REGISTERS_RQ_BW_RD_L26 0x310UL
+#define PXP2_REGISTERS_RQ_BW_RD_L27 0x314UL
+#define PXP2_REGISTERS_RQ_BW_RD_L4 0x2bcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L5 0x2c0UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND0 0x234UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND12 0x264UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND13 0x268UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND14 0x26cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND15 0x270UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND16 0x274UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND17 0x278UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND18 0x27cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND19 0x280UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND20 0x284UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND22 0x288UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND23 0x28cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND24 0x290UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND25 0x294UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND26 0x298UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND27 0x29cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND4 0x244UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND5 0x248UL
+#define PXP2_REGISTERS_RQ_BW_WR_ADD29 0x22cUL
+#define PXP2_REGISTERS_RQ_BW_WR_ADD30 0x230UL
+#define PXP2_REGISTERS_RQ_BW_WR_L29 0x31cUL
+#define PXP2_REGISTERS_RQ_BW_WR_L30 0x320UL
+#define PXP2_REGISTERS_RQ_BW_WR_UBOUND29 0x2a4UL
+#define PXP2_REGISTERS_RQ_BW_WR_UBOUND30 0x2a8UL
+#define PXP2_REGISTERS_RQ_CDU_ENDIAN_M 0x1a0UL
+#define PXP2_REGISTERS_RQ_CDU_P_SIZE 0x18UL
+#define PXP2_REGISTERS_RQ_CFG_DONE 0x1b4UL
+#define PXP2_REGISTERS_RQ_DBG_ENDIAN_M 0x1a4UL
+#define PXP2_REGISTERS_RQ_DISABLE_INPUTS 0x330UL
+#define PXP2_REGISTERS_RQ_HC_ENDIAN_M 0x1a8UL
+#define PXP2_REGISTERS_RQ_ONCHIP_AT 0x2000UL
+#define PXP2_REGISTERS_RQ_ONCHIP_AT_SIZE 2048
+#define PXP2_REGISTERS_RQ_QM_ENDIAN_M 0x194UL
+#define PXP2_REGISTERS_RQ_QM_P_SIZE 0x50UL
+#define PXP2_REGISTERS_RQ_RBC_DONE 0x1b0UL
+#define PXP2_REGISTERS_RQ_RD_MBS0 0x160UL
+#define PXP2_REGISTERS_RQ_SRC_ENDIAN_M 0x19cUL
+#define PXP2_REGISTERS_RQ_SRC_P_SIZE 0x6cUL
+#define PXP2_REGISTERS_RQ_TM_ENDIAN_M 0x198UL
+#define PXP2_REGISTERS_RQ_TM_P_SIZE 0x34UL
+#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY 0x80cUL
+#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT 0x810UL
+#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT 0x818UL
+#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT 0x820UL
+#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT 0x828UL
+#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT 0x830UL
+#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT 0x838UL
+#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT 0x840UL
+#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT 0x848UL
+#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT 0x850UL
+#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT 0x858UL
+#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT 0x860UL
+#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT 0x868UL
+#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT 0x870UL
+#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT 0x878UL
+#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT 0x880UL
+#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT 0x888UL
+#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT 0x890UL
+#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT 0x898UL
+#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT 0x8a0UL
+#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT 0x8a8UL
+#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT 0x8b0UL
+#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT 0x8b8UL
+#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT 0x8c0UL
+#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT 0x8c8UL
+#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT 0x8d0UL
+#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT 0x8d8UL
+#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT 0x8e0UL
+#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT 0x8e8UL
+#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT 0x8f0UL
+#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT 0x8f8UL
+#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT 0x900UL
+#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT 0x908UL
+#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_WR_MBS0 0x15cUL
+#define PXP_REGISTERS_HST_ARB_IS_IDLE 0x4UL
+#define PXP_REGISTERS_HST_CLIENTS_WAITING_TO_ARB 0x8UL
+#define PXP_REGISTERS_HST_INBOUND_INT 0x800UL
+#define PXP_REGISTERS_HST_INBOUND_INT_SIZE 512
+#define PXP_REGISTERS_PXP_INT_MASK_0 0x74UL
+#define PXP_REGISTERS_PXP_INT_STS_0 0x68UL
+#define PXP_REGISTERS_PXP_INT_STS_1 0x78UL
+#define PXP_REGISTERS_PXP_INT_STS_CLR_0 0x6cUL
+#define QM_REGISTERS_ACTCTRINITVAL_0 0x40UL
+#define QM_REGISTERS_ACTCTRINITVAL_1 0x44UL
+#define QM_REGISTERS_ACTCTRINITVAL_2 0x48UL
+#define QM_REGISTERS_ACTCTRINITVAL_3 0x4cUL
+#define QM_REGISTERS_BASEADDR 0x900UL
+#define QM_REGISTERS_BASEADDR_SIZE 64
+#define QM_REGISTERS_BYTECRDCOST 0x234UL
+#define QM_REGISTERS_BYTECRDINITVAL 0x238UL
+#define QM_REGISTERS_BYTECRDPORT_LSB 0x228UL
+#define QM_REGISTERS_BYTECRDPORT_MSB 0x224UL
+#define QM_REGISTERS_BYTECREDITAFULLTHR 0x94UL
+#define QM_REGISTERS_CMINITCRD_0 0xccUL
+#define QM_REGISTERS_CMINITCRD_1 0xd0UL
+#define QM_REGISTERS_CMINITCRD_2 0xd4UL
+#define QM_REGISTERS_CMINITCRD_3 0xd8UL
+#define QM_REGISTERS_CMINITCRD_4 0xdcUL
+#define QM_REGISTERS_CMINITCRD_5 0xe0UL
+#define QM_REGISTERS_CMINITCRD_6 0xe4UL
+#define QM_REGISTERS_CMINITCRD_7 0xe8UL
+#define QM_REGISTERS_CMINTEN 0xecUL
+#define QM_REGISTERS_CMINTVOQMASK_0 0x1f4UL
+#define QM_REGISTERS_CMINTVOQMASK_1 0x1f8UL
+#define QM_REGISTERS_CMINTVOQMASK_2 0x1fcUL
+#define QM_REGISTERS_CMINTVOQMASK_3 0x200UL
+#define QM_REGISTERS_CMINTVOQMASK_4 0x204UL
+#define QM_REGISTERS_CMINTVOQMASK_5 0x208UL
+#define QM_REGISTERS_CMINTVOQMASK_6 0x20cUL
+#define QM_REGISTERS_CMINTVOQMASK_7 0x210UL
+#define QM_REGISTERS_CONNNUM_0 0x20UL
+#define QM_REGISTERS_CONNNUM_1 0x24UL
+#define QM_REGISTERS_CTXREG_0 0x30UL
+#define QM_REGISTERS_CTXREG_1 0x34UL
+#define QM_REGISTERS_CTXREG_2 0x38UL
+#define QM_REGISTERS_CTXREG_3 0x3cUL
+#define QM_REGISTERS_ENBYPVOQMASK 0x23cUL
+#define QM_REGISTERS_ENBYTECRD_LSB 0x220UL
+#define QM_REGISTERS_ENBYTECRD_MSB 0x21cUL
+#define QM_REGISTERS_ENSEC 0xf0UL
+#define QM_REGISTERS_FUNCNUMSEL_LSB 0x230UL
+#define QM_REGISTERS_FUNCNUMSEL_MSB 0x22cUL
+#define QM_REGISTERS_HWAEMPTYMASK_LSB 0x218UL
+#define QM_REGISTERS_HWAEMPTYMASK_MSB 0x214UL
+#define QM_REGISTERS_OUTLDREQ 0x804UL
+#define QM_REGISTERS_OUTLDREQ_SIZE 1
+#define QM_REGISTERS_PCIREQAT 0x54UL
+#define QM_REGISTERS_PORT0BYTECRD 0x300UL
+#define QM_REGISTERS_PORT1BYTECRD 0x304UL
+#define QM_REGISTERS_PTRTBL 0xa00UL
+#define QM_REGISTERS_PTRTBL_SIZE 128
+#define QM_REGISTERS_QTASKCTR_0 0x308UL
+#define QM_REGISTERS_QVOQIDX_0 0xf4UL
+#define QM_REGISTERS_QVOQIDX_1 0xf8UL
+#define QM_REGISTERS_QVOQIDX_10 0x11cUL
+#define QM_REGISTERS_QVOQIDX_11 0x120UL
+#define QM_REGISTERS_QVOQIDX_12 0x124UL
+#define QM_REGISTERS_QVOQIDX_13 0x128UL
+#define QM_REGISTERS_QVOQIDX_14 0x12cUL
+#define QM_REGISTERS_QVOQIDX_15 0x130UL
+#define QM_REGISTERS_QVOQIDX_16 0x134UL
+#define QM_REGISTERS_QVOQIDX_17 0x138UL
+#define QM_REGISTERS_QVOQIDX_18 0x13cUL
+#define QM_REGISTERS_QVOQIDX_19 0x140UL
+#define QM_REGISTERS_QVOQIDX_10 0x11cUL
+#define QM_REGISTERS_QVOQIDX_11 0x120UL
+#define QM_REGISTERS_QVOQIDX_12 0x124UL
+#define QM_REGISTERS_QVOQIDX_13 0x128UL
+#define QM_REGISTERS_QVOQIDX_14 0x12cUL
+#define QM_REGISTERS_QVOQIDX_15 0x130UL
+#define QM_REGISTERS_QVOQIDX_16 0x134UL
+#define QM_REGISTERS_QVOQIDX_17 0x138UL
+#define QM_REGISTERS_QVOQIDX_18 0x13cUL
+#define QM_REGISTERS_QVOQIDX_19 0x140UL
+#define QM_REGISTERS_QVOQIDX_2 0xfcUL
+#define QM_REGISTERS_QVOQIDX_20 0x144UL
+#define QM_REGISTERS_QVOQIDX_21 0x148UL
+#define QM_REGISTERS_QVOQIDX_22 0x14cUL
+#define QM_REGISTERS_QVOQIDX_23 0x150UL
+#define QM_REGISTERS_QVOQIDX_24 0x154UL
+#define QM_REGISTERS_QVOQIDX_25 0x158UL
+#define QM_REGISTERS_QVOQIDX_26 0x15cUL
+#define QM_REGISTERS_QVOQIDX_27 0x160UL
+#define QM_REGISTERS_QVOQIDX_28 0x164UL
+#define QM_REGISTERS_QVOQIDX_29 0x168UL
+#define QM_REGISTERS_QVOQIDX_20 0x144UL
+#define QM_REGISTERS_QVOQIDX_21 0x148UL
+#define QM_REGISTERS_QVOQIDX_22 0x14cUL
+#define QM_REGISTERS_QVOQIDX_23 0x150UL
+#define QM_REGISTERS_QVOQIDX_24 0x154UL
+#define QM_REGISTERS_QVOQIDX_25 0x158UL
+#define QM_REGISTERS_QVOQIDX_26 0x15cUL
+#define QM_REGISTERS_QVOQIDX_27 0x160UL
+#define QM_REGISTERS_QVOQIDX_28 0x164UL
+#define QM_REGISTERS_QVOQIDX_29 0x168UL
+#define QM_REGISTERS_QVOQIDX_3 0x100UL
+#define QM_REGISTERS_QVOQIDX_30 0x16cUL
+#define QM_REGISTERS_QVOQIDX_31 0x170UL
+#define QM_REGISTERS_QVOQIDX_32 0x174UL
+#define QM_REGISTERS_QVOQIDX_33 0x178UL
+#define QM_REGISTERS_QVOQIDX_34 0x17cUL
+#define QM_REGISTERS_QVOQIDX_35 0x180UL
+#define QM_REGISTERS_QVOQIDX_36 0x184UL
+#define QM_REGISTERS_QVOQIDX_37 0x188UL
+#define QM_REGISTERS_QVOQIDX_38 0x18cUL
+#define QM_REGISTERS_QVOQIDX_39 0x190UL
+#define QM_REGISTERS_QVOQIDX_30 0x16cUL
+#define QM_REGISTERS_QVOQIDX_31 0x170UL
+#define QM_REGISTERS_QVOQIDX_32 0x174UL
+#define QM_REGISTERS_QVOQIDX_33 0x178UL
+#define QM_REGISTERS_QVOQIDX_34 0x17cUL
+#define QM_REGISTERS_QVOQIDX_35 0x180UL
+#define QM_REGISTERS_QVOQIDX_36 0x184UL
+#define QM_REGISTERS_QVOQIDX_37 0x188UL
+#define QM_REGISTERS_QVOQIDX_38 0x18cUL
+#define QM_REGISTERS_QVOQIDX_39 0x190UL
+#define QM_REGISTERS_QVOQIDX_4 0x104UL
+#define QM_REGISTERS_QVOQIDX_40 0x194UL
+#define QM_REGISTERS_QVOQIDX_41 0x198UL
+#define QM_REGISTERS_QVOQIDX_42 0x19cUL
+#define QM_REGISTERS_QVOQIDX_43 0x1a0UL
+#define QM_REGISTERS_QVOQIDX_44 0x1a4UL
+#define QM_REGISTERS_QVOQIDX_45 0x1a8UL
+#define QM_REGISTERS_QVOQIDX_46 0x1acUL
+#define QM_REGISTERS_QVOQIDX_47 0x1b0UL
+#define QM_REGISTERS_QVOQIDX_48 0x1b4UL
+#define QM_REGISTERS_QVOQIDX_49 0x1b8UL
+#define QM_REGISTERS_QVOQIDX_40 0x194UL
+#define QM_REGISTERS_QVOQIDX_41 0x198UL
+#define QM_REGISTERS_QVOQIDX_42 0x19cUL
+#define QM_REGISTERS_QVOQIDX_43 0x1a0UL
+#define QM_REGISTERS_QVOQIDX_44 0x1a4UL
+#define QM_REGISTERS_QVOQIDX_45 0x1a8UL
+#define QM_REGISTERS_QVOQIDX_46 0x1acUL
+#define QM_REGISTERS_QVOQIDX_47 0x1b0UL
+#define QM_REGISTERS_QVOQIDX_48 0x1b4UL
+#define QM_REGISTERS_QVOQIDX_49 0x1b8UL
+#define QM_REGISTERS_QVOQIDX_5 0x108UL
+#define QM_REGISTERS_QVOQIDX_50 0x1bcUL
+#define QM_REGISTERS_QVOQIDX_51 0x1c0UL
+#define QM_REGISTERS_QVOQIDX_52 0x1c4UL
+#define QM_REGISTERS_QVOQIDX_53 0x1c8UL
+#define QM_REGISTERS_QVOQIDX_54 0x1ccUL
+#define QM_REGISTERS_QVOQIDX_55 0x1d0UL
+#define QM_REGISTERS_QVOQIDX_56 0x1d4UL
+#define QM_REGISTERS_QVOQIDX_57 0x1d8UL
+#define QM_REGISTERS_QVOQIDX_58 0x1dcUL
+#define QM_REGISTERS_QVOQIDX_59 0x1e0UL
+#define QM_REGISTERS_QVOQIDX_50 0x1bcUL
+#define QM_REGISTERS_QVOQIDX_51 0x1c0UL
+#define QM_REGISTERS_QVOQIDX_52 0x1c4UL
+#define QM_REGISTERS_QVOQIDX_53 0x1c8UL
+#define QM_REGISTERS_QVOQIDX_54 0x1ccUL
+#define QM_REGISTERS_QVOQIDX_55 0x1d0UL
+#define QM_REGISTERS_QVOQIDX_56 0x1d4UL
+#define QM_REGISTERS_QVOQIDX_57 0x1d8UL
+#define QM_REGISTERS_QVOQIDX_58 0x1dcUL
+#define QM_REGISTERS_QVOQIDX_59 0x1e0UL
+#define QM_REGISTERS_QVOQIDX_6 0x10cUL
+#define QM_REGISTERS_QVOQIDX_60 0x1e4UL
+#define QM_REGISTERS_QVOQIDX_61 0x1e8UL
+#define QM_REGISTERS_QVOQIDX_62 0x1ecUL
+#define QM_REGISTERS_QVOQIDX_63 0x1f0UL
+#define QM_REGISTERS_QVOQIDX_60 0x1e4UL
+#define QM_REGISTERS_QVOQIDX_61 0x1e8UL
+#define QM_REGISTERS_QVOQIDX_62 0x1ecUL
+#define QM_REGISTERS_QVOQIDX_63 0x1f0UL
+#define QM_REGISTERS_QVOQIDX_7 0x110UL
+#define QM_REGISTERS_QVOQIDX_8 0x114UL
+#define QM_REGISTERS_QVOQIDX_9 0x118UL
+#define QM_REGISTERS_SOFT_RESET 0x428UL
+#define QM_REGISTERS_TASKCRDCOST_0 0x9cUL
+#define QM_REGISTERS_TASKCRDCOST_1 0xa0UL
+#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL
+#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL
+#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL
+#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL
+#define QM_REGISTERS_TASKCRDCOST_2 0xa4UL
+#define QM_REGISTERS_TASKCRDCOST_3 0xa8UL
+#define QM_REGISTERS_TASKCRDCOST_4 0xacUL
+#define QM_REGISTERS_TASKCRDCOST_5 0xb0UL
+#define QM_REGISTERS_TASKCRDCOST_6 0xb4UL
+#define QM_REGISTERS_TASKCRDCOST_7 0xb8UL
+#define QM_REGISTERS_TASKCRDCOST_8 0xbcUL
+#define QM_REGISTERS_TASKCRDCOST_9 0xc0UL
+#define QM_REGISTERS_VOQCRDERRREG 0x408UL
+#define QM_REGISTERS_VOQCREDIT_0 0x2d0UL
+#define QM_REGISTERS_VOQCREDIT_1 0x2d4UL
+#define QM_REGISTERS_VOQCREDIT_10 0x2f8UL
+#define QM_REGISTERS_VOQCREDIT_11 0x2fcUL
+#define QM_REGISTERS_VOQCREDIT_4 0x2e0UL
+#define QM_REGISTERS_VOQCREDITAFULLTHR 0x90UL
+#define QM_REGISTERS_VOQINITCREDIT_0 0x60UL
+#define QM_REGISTERS_VOQINITCREDIT_1 0x64UL
+#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL
+#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL
+#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL
+#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL
+#define QM_REGISTERS_VOQINITCREDIT_2 0x68UL
+#define QM_REGISTERS_VOQINITCREDIT_3 0x6cUL
+#define QM_REGISTERS_VOQINITCREDIT_4 0x70UL
+#define QM_REGISTERS_VOQINITCREDIT_5 0x74UL
+#define QM_REGISTERS_VOQINITCREDIT_6 0x78UL
+#define QM_REGISTERS_VOQINITCREDIT_7 0x7cUL
+#define QM_REGISTERS_VOQINITCREDIT_8 0x80UL
+#define QM_REGISTERS_VOQINITCREDIT_9 0x84UL
+#define QM_REGISTERS_VOQPORT_0 0x2a0UL
+#define QM_REGISTERS_VOQPORT_1 0x2a4UL
+#define QM_REGISTERS_VOQPORT_10 0x2c8UL
+#define QM_REGISTERS_VOQPORT_11 0x2ccUL
+#define QM_REGISTERS_VOQPORT_10 0x2c8UL
+#define QM_REGISTERS_VOQPORT_11 0x2ccUL
+#define QM_REGISTERS_VOQPORT_2 0x2a8UL
+#define QM_REGISTERS_VOQPORT_3 0x2acUL
+#define QM_REGISTERS_VOQPORT_4 0x2b0UL
+#define QM_REGISTERS_VOQPORT_5 0x2b4UL
+#define QM_REGISTERS_VOQPORT_6 0x2b8UL
+#define QM_REGISTERS_VOQPORT_7 0x2bcUL
+#define QM_REGISTERS_VOQPORT_8 0x2c0UL
+#define QM_REGISTERS_VOQPORT_9 0x2c4UL
+#define QM_REGISTERS_VOQQMASK_0_LSB 0x240UL
+#define QM_REGISTERS_VOQQMASK_0_MSB 0x244UL
+#define QM_REGISTERS_VOQQMASK_10_LSB 0x290UL
+#define QM_REGISTERS_VOQQMASK_10_MSB 0x294UL
+#define QM_REGISTERS_VOQQMASK_11_LSB 0x298UL
+#define QM_REGISTERS_VOQQMASK_11_MSB 0x29cUL
+#define QM_REGISTERS_VOQQMASK_1_LSB 0x248UL
+#define QM_REGISTERS_VOQQMASK_1_MSB 0x24cUL
+#define QM_REGISTERS_VOQQMASK_2_LSB 0x250UL
+#define QM_REGISTERS_VOQQMASK_2_MSB 0x254UL
+#define QM_REGISTERS_VOQQMASK_3_LSB 0x258UL
+#define QM_REGISTERS_VOQQMASK_3_MSB 0x25cUL
+#define QM_REGISTERS_VOQQMASK_4_LSB 0x260UL
+#define QM_REGISTERS_VOQQMASK_4_MSB 0x264UL
+#define QM_REGISTERS_VOQQMASK_5_LSB 0x268UL
+#define QM_REGISTERS_VOQQMASK_5_MSB 0x26cUL
+#define QM_REGISTERS_VOQQMASK_6_LSB 0x270UL
+#define QM_REGISTERS_VOQQMASK_6_MSB 0x274UL
+#define QM_REGISTERS_VOQQMASK_7_LSB 0x278UL
+#define QM_REGISTERS_VOQQMASK_7_MSB 0x27cUL
+#define QM_REGISTERS_VOQQMASK_8_LSB 0x280UL
+#define QM_REGISTERS_VOQQMASK_8_MSB 0x284UL
+#define QM_REGISTERS_VOQQMASK_9_LSB 0x288UL
+#define QM_REGISTERS_VOQQMASK_9_MSB 0x28cUL
+#define QM_REGISTERS_WRRWEIGHTS_0 0x80cUL
+#define QM_REGISTERS_WRRWEIGHTS_0_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_1 0x810UL
+#define QM_REGISTERS_WRRWEIGHTS_1_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL
+#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL
+#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL
+#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL
+#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL
+#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL
+#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL
+#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL
+#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL
+#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL
+#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL
+#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL
+#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_2 0x82cUL
+#define QM_REGISTERS_WRRWEIGHTS_2_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_3 0x830UL
+#define QM_REGISTERS_WRRWEIGHTS_3_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_4 0x834UL
+#define QM_REGISTERS_WRRWEIGHTS_4_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_5 0x838UL
+#define QM_REGISTERS_WRRWEIGHTS_5_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_6 0x83cUL
+#define QM_REGISTERS_WRRWEIGHTS_6_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_7 0x840UL
+#define QM_REGISTERS_WRRWEIGHTS_7_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_8 0x844UL
+#define QM_REGISTERS_WRRWEIGHTS_8_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_9 0x848UL
+#define QM_REGISTERS_WRRWEIGHTS_9_SIZE 1
+#define SRC_REGISTERS_COUNTFREE0 0x100UL
+#define SRC_REGISTERS_COUNTFREE0_SIZE 1
+#define SRC_REGISTERS_FIRSTFREE0 0x110UL
+#define SRC_REGISTERS_FIRSTFREE0_SIZE 2
+#define SRC_REGISTERS_KEYRSS0_0 0x8UL
+#define SRC_REGISTERS_KEYRSS1_9 0x54UL
+#define SRC_REGISTERS_LASTFREE0 0x130UL
+#define SRC_REGISTERS_LASTFREE0_SIZE 2
+#define SRC_REGISTERS_NUMBER_HASH_BITS0 0x0UL
+#define SRC_REGISTERS_SOFT_RST 0x9cUL
+#define SRC_REGISTERS_SRC_INT_STS 0xacUL
+#define SRC_REGISTERS_SRC_INT_STS_CLR 0xb0UL
+#define SRC_REGISTERS_SRC_INT_STS_WR 0xb4UL
+#define TCM_REGISTERS_CAM_OCCUP 0x17cUL
+#define TCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define TCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define TCM_REGISTERS_CDU_AG_RD_IFEN 0x34UL
+#define TCM_REGISTERS_CDU_AG_WR_IFEN 0x30UL
+#define TCM_REGISTERS_CDU_SM_RD_IFEN 0x3cUL
+#define TCM_REGISTERS_CDU_SM_WR_IFEN 0x38UL
+#define TCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define TCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_CP_WEIGHT 0xc0UL
+#define TCM_REGISTERS_CSEM_IFEN 0x2cUL
+#define TCM_REGISTERS_CSEM_LENGTH_MIS 0x174UL
+#define TCM_REGISTERS_ERR_EVNT_ID 0xa0UL
+#define TCM_REGISTERS_ERR_TCM_HDR 0x9cUL
+#define TCM_REGISTERS_EXPR_EVNT_ID 0xa4UL
+#define TCM_REGISTERS_FIC0_INIT_CRD 0x20cUL
+#define TCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_FIC1_INIT_CRD 0x210UL
+#define TCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_GR_ARB_TYPE 0x114UL
+#define TCM_REGISTERS_GR_LD0_PR 0x11cUL
+#define TCM_REGISTERS_GR_LD1_PR 0x120UL
+#define TCM_REGISTERS_N_SM_CTX_LD_0 0x50UL
+#define TCM_REGISTERS_N_SM_CTX_LD_1 0x54UL
+#define TCM_REGISTERS_N_SM_CTX_LD_10 0x78UL
+#define TCM_REGISTERS_N_SM_CTX_LD_11 0x7cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_12 0x80UL
+#define TCM_REGISTERS_N_SM_CTX_LD_13 0x84UL
+#define TCM_REGISTERS_N_SM_CTX_LD_14 0x88UL
+#define TCM_REGISTERS_N_SM_CTX_LD_15 0x8cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_2 0x58UL
+#define TCM_REGISTERS_N_SM_CTX_LD_3 0x5cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_4 0x60UL
+#define TCM_REGISTERS_N_SM_CTX_LD_5 0x64UL
+#define TCM_REGISTERS_N_SM_CTX_LD_6 0x68UL
+#define TCM_REGISTERS_N_SM_CTX_LD_7 0x6cUL
+#define TCM_REGISTERS_PBF_IFEN 0x24UL
+#define TCM_REGISTERS_PBF_LENGTH_MIS 0x16cUL
+#define TCM_REGISTERS_PBF_WEIGHT 0xb4UL
+#define TCM_REGISTERS_PHYS_QNUM0_0 0xe0UL
+#define TCM_REGISTERS_PHYS_QNUM0_1 0xe4UL
+#define TCM_REGISTERS_PHYS_QNUM1_0 0xe8UL
+#define TCM_REGISTERS_PHYS_QNUM1_1 0xecUL
+#define TCM_REGISTERS_PHYS_QNUM2_0 0xf0UL
+#define TCM_REGISTERS_PHYS_QNUM2_1 0xf4UL
+#define TCM_REGISTERS_PHYS_QNUM3_0 0xf8UL
+#define TCM_REGISTERS_PHYS_QNUM3_1 0xfcUL
+#define TCM_REGISTERS_PRS_IFEN 0x20UL
+#define TCM_REGISTERS_PRS_LENGTH_MIS 0x168UL
+#define TCM_REGISTERS_PRS_WEIGHT 0xb0UL
+#define TCM_REGISTERS_STOP_EVNT_ID 0xa8UL
+#define TCM_REGISTERS_STORM_LENGTH_MIS 0x160UL
+#define TCM_REGISTERS_STORM_TCM_IFEN 0x10UL
+#define TCM_REGISTERS_TCM_CFC_IFEN 0x40UL
+#define TCM_REGISTERS_TCM_INT_STS 0x1d0UL
+#define TCM_REGISTERS_TCM_INT_STS_CLR 0x1d4UL
+#define TCM_REGISTERS_TCM_INT_STS_WR 0x1d8UL
+#define TCM_REGISTERS_TCM_REG0_SZ 0xd8UL
+#define TCM_REGISTERS_TCM_STORM0_IFEN 0x4UL
+#define TCM_REGISTERS_TCM_STORM1_IFEN 0x8UL
+#define TCM_REGISTERS_TCM_TQM_IFEN 0xcUL
+#define TCM_REGISTERS_TCM_TQM_USE_Q 0xd4UL
+#define TCM_REGISTERS_TM_TCM_HDR 0x98UL
+#define TCM_REGISTERS_TM_TCM_IFEN 0x1cUL
+#define TCM_REGISTERS_TQM_INIT_CRD 0x21cUL
+#define TCM_REGISTERS_TQM_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_TQM_TCM_HDR_P 0x90UL
+#define TCM_REGISTERS_TQM_TCM_HDR_S 0x94UL
+#define TCM_REGISTERS_TQM_TCM_IFEN 0x14UL
+#define TCM_REGISTERS_TSDM_IFEN 0x18UL
+#define TCM_REGISTERS_TSDM_LENGTH_MIS 0x164UL
+#define TCM_REGISTERS_TSDM_WEIGHT 0xc4UL
+#define TCM_REGISTERS_USEM_IFEN 0x28UL
+#define TCM_REGISTERS_USEM_LENGTH_MIS 0x170UL
+#define TCM_REGISTERS_XX_DESCR_TABLE 0x280UL
+#define TCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define TCM_REGISTERS_XX_INIT_CRD 0x220UL
+#define TCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_XX_MAX_LL_SZ 0x44UL
+#define TCM_REGISTERS_XX_MSG_NUM 0x224UL
+#define TCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define TCM_REGISTERS_XX_OVFL_EVNT_ID 0x48UL
+#define TCM_REGISTERS_XX_TABLE 0x240UL
+#define TCM_REGISTERS_XX_TABLE_SIZE 10
+#define TM_REGISTERS_CFC_AC_CRDCNT_VAL 0x208UL
+#define TM_REGISTERS_CFC_AC_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL 0x210UL
+#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_CL0_CONT_REGION 0x30UL
+#define TM_REGISTERS_CL1_CONT_REGION 0x34UL
+#define TM_REGISTERS_CL2_CONT_REGION 0x38UL
+#define TM_REGISTERS_CLIN_PRIOR0_CLIENT 0x24UL
+#define TM_REGISTERS_CLIN_PRIOR1_CLIENT 0x28UL
+#define TM_REGISTERS_CLOUT_CRDCNT0_VAL 0x220UL
+#define TM_REGISTERS_CLOUT_CRDCNT0_VAL_SIZE 1
+#define TM_REGISTERS_CLOUT_CRDCNT1_VAL 0x228UL
+#define TM_REGISTERS_CLOUT_CRDCNT1_VAL_SIZE 1
+#define TM_REGISTERS_CLOUT_CRDCNT2_VAL 0x230UL
+#define TM_REGISTERS_CLOUT_CRDCNT2_VAL_SIZE 1
+#define TM_REGISTERS_EN_CL0_INPUT 0x8UL
+#define TM_REGISTERS_EN_CL1_INPUT 0xcUL
+#define TM_REGISTERS_EN_CL2_INPUT 0x10UL
+#define TM_REGISTERS_EN_LINEAR0_TIMER 0x14UL
+#define TM_REGISTERS_EN_LINEAR1_TIMER 0x18UL
+#define TM_REGISTERS_EN_REAL_TIME_CNT 0xd8UL
+#define TM_REGISTERS_EN_TIMERS 0x0UL
+#define TM_REGISTERS_EXP_CRDCNT_VAL 0x238UL
+#define TM_REGISTERS_EXP_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_LIN0_MAX_ACTIVE_CID 0x48UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_VALID 0x248UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_VALID_SIZE 1
+#define TM_REGISTERS_LIN0_PHY_ADDR 0x270UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_SIZE 2
+#define TM_REGISTERS_LIN0_SCAN_TIME 0x3cUL
+#define TM_REGISTERS_LIN1_PHY_ADDR_VALID 0x258UL
+#define TM_REGISTERS_LIN1_PHY_ADDR_VALID_SIZE 1
+#define TM_REGISTERS_LIN1_PHY_ADDR 0x280UL
+#define TM_REGISTERS_LIN1_PHY_ADDR_SIZE 2
+#define TM_REGISTERS_LIN_SETCLR_FIFO_ALFULL_THR 0x70UL
+#define TM_REGISTERS_PCIARB_CRDCNT_VAL 0x260UL
+#define TM_REGISTERS_PCIARB_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_TIMER_SOFT_RST 0x4UL
+#define TM_REGISTERS_TIMER_TICK_SIZE 0x1cUL
+#define TM_REGISTERS_TM_CONTEXT_REGION 0x44UL
+#define TM_REGISTERS_TM_INT_STS 0xf0UL
+#define TM_REGISTERS_TM_INT_STS_CLR 0xf4UL
+#define TM_REGISTERS_TM_INT_STS_WR 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define TSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define TSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define TSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define TSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define TSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define TSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define TSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define TSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define TSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define TSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define TSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define TSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define TSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define TSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define TSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define TSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define TSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define TSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define TSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define TSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define TSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define TSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define TSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define TSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define TSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define TSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define TSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define TSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define TSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define TSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define TSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define TSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define TSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define TSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define TSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define TSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define TSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define TSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define TSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define TSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define TSDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL
+#define TSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define TSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define TSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define TSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define TSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define TSDM_REGISTERS_TIMER_TICK 0x0UL
+#define TSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define TSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define TSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define TSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define TSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define TSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define TSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define TSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define TSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define TSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define TSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define TSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define TSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define TSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define TSEM_REGISTERS_INT_TABLE_TM 0xc4UL
+#define TSEM_REGISTERS_INT_TABLE 0x400UL
+#define TSEM_REGISTERS_INT_TABLE_SIZE 256
+#define TSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define TSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define TSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define TSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define TSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define TSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define TSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define TSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define TSEM_REGISTERS_PASSIVE_BUFFER 0x1000UL
+#define TSEM_REGISTERS_PASSIVE_BUFFER_SIZE 1024
+#define TSEM_REGISTERS_PRAM 0x40000UL
+#define TSEM_REGISTERS_PRAM_SIZE 65536
+#define TSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define TSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define TSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define TSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define TSEM_REGISTERS_TS_0_AS 0x38UL
+#define TSEM_REGISTERS_TS_10_AS 0x60UL
+#define TSEM_REGISTERS_TS_11_AS 0x64UL
+#define TSEM_REGISTERS_TS_12_AS 0x68UL
+#define TSEM_REGISTERS_TS_13_AS 0x6cUL
+#define TSEM_REGISTERS_TS_14_AS 0x70UL
+#define TSEM_REGISTERS_TS_15_AS 0x74UL
+#define TSEM_REGISTERS_TS_16_AS 0x78UL
+#define TSEM_REGISTERS_TS_17_AS 0x7cUL
+#define TSEM_REGISTERS_TS_18_AS 0x80UL
+#define TSEM_REGISTERS_TS_19_AS 0x84UL
+#define TSEM_REGISTERS_TS_1_AS 0x3cUL
+#define TSEM_REGISTERS_TS_2_AS 0x40UL
+#define TSEM_REGISTERS_TS_3_AS 0x44UL
+#define TSEM_REGISTERS_TS_4_AS 0x48UL
+#define TSEM_REGISTERS_TS_5_AS 0x4cUL
+#define TSEM_REGISTERS_TS_6_AS 0x50UL
+#define TSEM_REGISTERS_TS_7_AS 0x54UL
+#define TSEM_REGISTERS_TS_8_AS 0x58UL
+#define TSEM_REGISTERS_TS_9_AS 0x5cUL
+#define UCM_REGISTERS_CAM_OCCUP 0x170UL
+#define UCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define UCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define UCM_REGISTERS_CDU_AG_RD_IFEN 0x38UL
+#define UCM_REGISTERS_CDU_AG_WR_IFEN 0x34UL
+#define UCM_REGISTERS_CDU_SM_RD_IFEN 0x40UL
+#define UCM_REGISTERS_CDU_SM_WR_IFEN 0x3cUL
+#define UCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define UCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_CP_WEIGHT 0xc4UL
+#define UCM_REGISTERS_CSEM_IFEN 0x28UL
+#define UCM_REGISTERS_CSEM_LENGTH_MIS 0x160UL
+#define UCM_REGISTERS_CSEM_WEIGHT 0xb8UL
+#define UCM_REGISTERS_DORQ_IFEN 0x30UL
+#define UCM_REGISTERS_DORQ_LENGTH_MIS 0x168UL
+#define UCM_REGISTERS_ERR_EVNT_ID 0xa4UL
+#define UCM_REGISTERS_ERR_UCM_HDR 0xa0UL
+#define UCM_REGISTERS_EXPR_EVNT_ID 0xa8UL
+#define UCM_REGISTERS_FIC0_INIT_CRD 0x20cUL
+#define UCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_FIC1_INIT_CRD 0x210UL
+#define UCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_GR_ARB_TYPE 0x144UL
+#define UCM_REGISTERS_GR_LD0_PR 0x14cUL
+#define UCM_REGISTERS_GR_LD1_PR 0x150UL
+#define UCM_REGISTERS_INV_CFLG_Q 0xe4UL
+#define UCM_REGISTERS_N_SM_CTX_LD_0 0x54UL
+#define UCM_REGISTERS_N_SM_CTX_LD_1 0x58UL
+#define UCM_REGISTERS_N_SM_CTX_LD_10 0x7cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_11 0x80UL
+#define UCM_REGISTERS_N_SM_CTX_LD_12 0x84UL
+#define UCM_REGISTERS_N_SM_CTX_LD_13 0x88UL
+#define UCM_REGISTERS_N_SM_CTX_LD_14 0x8cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_15 0x90UL
+#define UCM_REGISTERS_N_SM_CTX_LD_2 0x5cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_3 0x60UL
+#define UCM_REGISTERS_N_SM_CTX_LD_4 0x64UL
+#define UCM_REGISTERS_N_SM_CTX_LD_5 0x68UL
+#define UCM_REGISTERS_N_SM_CTX_LD_6 0x6cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_7 0x70UL
+#define UCM_REGISTERS_PHYS_QNUM0_0 0x110UL
+#define UCM_REGISTERS_PHYS_QNUM0_1 0x114UL
+#define UCM_REGISTERS_PHYS_QNUM1_0 0x118UL
+#define UCM_REGISTERS_PHYS_QNUM1_1 0x11cUL
+#define UCM_REGISTERS_STOP_EVNT_ID 0xacUL
+#define UCM_REGISTERS_STORM_LENGTH_MIS 0x154UL
+#define UCM_REGISTERS_STORM_UCM_IFEN 0x10UL
+#define UCM_REGISTERS_TM_INIT_CRD 0x21cUL
+#define UCM_REGISTERS_TM_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_TM_UCM_HDR 0x9cUL
+#define UCM_REGISTERS_TM_UCM_IFEN 0x1cUL
+#define UCM_REGISTERS_TSEM_IFEN 0x24UL
+#define UCM_REGISTERS_TSEM_LENGTH_MIS 0x15cUL
+#define UCM_REGISTERS_TSEM_WEIGHT 0xb4UL
+#define UCM_REGISTERS_UCM_CFC_IFEN 0x44UL
+#define UCM_REGISTERS_UCM_INT_STS 0x1c8UL
+#define UCM_REGISTERS_UCM_INT_STS_CLR 0x1ccUL
+#define UCM_REGISTERS_UCM_INT_STS_WR 0x1d0UL
+#define UCM_REGISTERS_UCM_REG0_SZ 0xdcUL
+#define UCM_REGISTERS_UCM_STORM0_IFEN 0x4UL
+#define UCM_REGISTERS_UCM_STORM1_IFEN 0x8UL
+#define UCM_REGISTERS_UCM_TM_IFEN 0x20UL
+#define UCM_REGISTERS_UCM_UQM_IFEN 0xcUL
+#define UCM_REGISTERS_UCM_UQM_USE_Q 0xd8UL
+#define UCM_REGISTERS_UQM_INIT_CRD 0x220UL
+#define UCM_REGISTERS_UQM_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_UQM_P_WEIGHT 0xccUL
+#define UCM_REGISTERS_UQM_UCM_HDR_P 0x94UL
+#define UCM_REGISTERS_UQM_UCM_HDR_S 0x98UL
+#define UCM_REGISTERS_UQM_UCM_IFEN 0x14UL
+#define UCM_REGISTERS_USDM_IFEN 0x18UL
+#define UCM_REGISTERS_USDM_LENGTH_MIS 0x158UL
+#define UCM_REGISTERS_XSEM_IFEN 0x2cUL
+#define UCM_REGISTERS_XSEM_LENGTH_MIS 0x164UL
+#define UCM_REGISTERS_XX_DESCR_TABLE 0x280UL
+#define UCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define UCM_REGISTERS_XX_INIT_CRD 0x224UL
+#define UCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_XX_MSG_NUM 0x228UL
+#define UCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define UCM_REGISTERS_XX_OVFL_EVNT_ID 0x4cUL
+#define UCM_REGISTERS_XX_TABLE 0x300UL
+#define UCM_REGISTERS_XX_TABLE_SIZE 18
+#define USDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define USDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define USDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define USDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define USDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define USDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define USDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define USDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define USDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define USDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define USDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define USDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define USDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define USDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define USDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define USDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define USDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define USDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define USDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define USDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define USDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define USDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define USDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define USDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define USDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define USDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define USDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define USDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define USDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define USDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define USDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define USDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define USDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define USDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define USDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define USDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define USDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define USDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define USDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define USDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define USDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define USDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define USDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define USDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define USDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define USDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define USDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define USDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define USDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define USDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define USDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define USDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define USDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define USDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define USDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define USDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define USDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define USDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define USDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define USDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define USDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define USDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define USDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define USDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define USDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define USDM_REGISTERS_ENABLE_IN1 0x238UL
+#define USDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define USDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define USDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define USDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x280UL
+#define USDM_REGISTERS_NUM_OF_PKT_END_MSG 0x278UL
+#define USDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x27cUL
+#define USDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define USDM_REGISTERS_NUM_OF_Q10_CMD 0x270UL
+#define USDM_REGISTERS_NUM_OF_Q11_CMD 0x274UL
+#define USDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define USDM_REGISTERS_NUM_OF_Q2_CMD 0x250UL
+#define USDM_REGISTERS_NUM_OF_Q3_CMD 0x254UL
+#define USDM_REGISTERS_NUM_OF_Q4_CMD 0x258UL
+#define USDM_REGISTERS_NUM_OF_Q5_CMD 0x25cUL
+#define USDM_REGISTERS_NUM_OF_Q6_CMD 0x260UL
+#define USDM_REGISTERS_NUM_OF_Q7_CMD 0x264UL
+#define USDM_REGISTERS_NUM_OF_Q8_CMD 0x268UL
+#define USDM_REGISTERS_NUM_OF_Q9_CMD 0x26cUL
+#define USDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL
+#define USDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x550UL
+#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define USDM_REGISTERS_SYNC_PARSER_EMPTY 0x558UL
+#define USDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define USDM_REGISTERS_SYNC_SYNC_EMPTY 0x560UL
+#define USDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define USDM_REGISTERS_TIMER_TICK 0x0UL
+#define USEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define USEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define USEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define USEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define USEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define USEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define USEM_REGISTERS_ENABLE_IN 0xa4UL
+#define USEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define USEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define USEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define USEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define USEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define USEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define USEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define USEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define USEM_REGISTERS_INT_TABLE 0x400UL
+#define USEM_REGISTERS_INT_TABLE_SIZE 256
+#define USEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define USEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define USEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define USEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define USEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define USEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define USEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define USEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define USEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define USEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define USEM_REGISTERS_PRAM 0x40000UL
+#define USEM_REGISTERS_PRAM_SIZE 65536
+#define USEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define USEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define USEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define USEM_REGISTERS_THREADS_LIST_SIZE 1
+#define USEM_REGISTERS_TS_0_AS 0x38UL
+#define USEM_REGISTERS_TS_10_AS 0x60UL
+#define USEM_REGISTERS_TS_11_AS 0x64UL
+#define USEM_REGISTERS_TS_12_AS 0x68UL
+#define USEM_REGISTERS_TS_13_AS 0x6cUL
+#define USEM_REGISTERS_TS_14_AS 0x70UL
+#define USEM_REGISTERS_TS_15_AS 0x74UL
+#define USEM_REGISTERS_TS_16_AS 0x78UL
+#define USEM_REGISTERS_TS_17_AS 0x7cUL
+#define USEM_REGISTERS_TS_18_AS 0x80UL
+#define USEM_REGISTERS_TS_19_AS 0x84UL
+#define USEM_REGISTERS_TS_1_AS 0x3cUL
+#define USEM_REGISTERS_TS_2_AS 0x40UL
+#define USEM_REGISTERS_TS_3_AS 0x44UL
+#define USEM_REGISTERS_TS_4_AS 0x48UL
+#define USEM_REGISTERS_TS_5_AS 0x4cUL
+#define USEM_REGISTERS_TS_6_AS 0x50UL
+#define USEM_REGISTERS_TS_7_AS 0x54UL
+#define USEM_REGISTERS_TS_8_AS 0x58UL
+#define USEM_REGISTERS_TS_9_AS 0x5cUL
+#define XCM_REGISTERS_AUX1_Q 0x134UL
+#define XCM_REGISTERS_AUX_CNT_FLG_Q_19 0x1b0UL
+#define XCM_REGISTERS_CAM_OCCUP 0x244UL
+#define XCM_REGISTERS_CAM_OCCUP_ST 0x400UL
+#define XCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define XCM_REGISTERS_CDU_AG_RD_IFEN 0x44UL
+#define XCM_REGISTERS_CDU_AG_WR_IFEN 0x40UL
+#define XCM_REGISTERS_CDU_SM_RD_IFEN 0x4cUL
+#define XCM_REGISTERS_CDU_SM_WR_IFEN 0x48UL
+#define XCM_REGISTERS_CFC_INIT_CRD 0x404UL
+#define XCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_CP_WEIGHT 0xdcUL
+#define XCM_REGISTERS_CSEM_IFEN 0x28UL
+#define XCM_REGISTERS_CSEM_LENGTH_MIS 0x228UL
+#define XCM_REGISTERS_CSEM_WEIGHT 0xc4UL
+#define XCM_REGISTERS_DORQ_IFEN 0x30UL
+#define XCM_REGISTERS_DORQ_LENGTH_MIS 0x230UL
+#define XCM_REGISTERS_ERR_EVNT_ID 0xb0UL
+#define XCM_REGISTERS_ERR_XCM_HDR 0xacUL
+#define XCM_REGISTERS_EXPR_EVNT_ID 0xb4UL
+#define XCM_REGISTERS_FIC0_INIT_CRD 0x40cUL
+#define XCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_FIC1_INIT_CRD 0x410UL
+#define XCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_0 0x118UL
+#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_1 0x11cUL
+#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_0 0x108UL
+#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_1 0x10cUL
+#define XCM_REGISTERS_GR_ARB_TYPE 0x20cUL
+#define XCM_REGISTERS_GR_LD0_PR 0x214UL
+#define XCM_REGISTERS_GR_LD1_PR 0x218UL
+#define XCM_REGISTERS_NIG0_IFEN 0x38UL
+#define XCM_REGISTERS_NIG0_LENGTH_MIS 0x238UL
+#define XCM_REGISTERS_NIG1_IFEN 0x3cUL
+#define XCM_REGISTERS_NIG1_LENGTH_MIS 0x23cUL
+#define XCM_REGISTERS_NIG1_WEIGHT 0xd8UL
+#define XCM_REGISTERS_N_SM_CTX_LD_0 0x60UL
+#define XCM_REGISTERS_N_SM_CTX_LD_1 0x64UL
+#define XCM_REGISTERS_N_SM_CTX_LD_10 0x88UL
+#define XCM_REGISTERS_N_SM_CTX_LD_11 0x8cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_12 0x90UL
+#define XCM_REGISTERS_N_SM_CTX_LD_13 0x94UL
+#define XCM_REGISTERS_N_SM_CTX_LD_14 0x98UL
+#define XCM_REGISTERS_N_SM_CTX_LD_15 0x9cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_2 0x68UL
+#define XCM_REGISTERS_N_SM_CTX_LD_3 0x6cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_4 0x70UL
+#define XCM_REGISTERS_N_SM_CTX_LD_5 0x74UL
+#define XCM_REGISTERS_N_SM_CTX_LD_6 0x78UL
+#define XCM_REGISTERS_N_SM_CTX_LD_7 0x7cUL
+#define XCM_REGISTERS_PBF_IFEN 0x34UL
+#define XCM_REGISTERS_PBF_LENGTH_MIS 0x234UL
+#define XCM_REGISTERS_PBF_WEIGHT 0xd0UL
+#define XCM_REGISTERS_STOP_EVNT_ID 0xb8UL
+#define XCM_REGISTERS_STORM_LENGTH_MIS 0x21cUL
+#define XCM_REGISTERS_STORM_WEIGHT 0xbcUL
+#define XCM_REGISTERS_STORM_XCM_IFEN 0x10UL
+#define XCM_REGISTERS_TM_INIT_CRD 0x41cUL
+#define XCM_REGISTERS_TM_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_TM_XCM_HDR 0xa8UL
+#define XCM_REGISTERS_TM_XCM_IFEN 0x1cUL
+#define XCM_REGISTERS_TSEM_IFEN 0x24UL
+#define XCM_REGISTERS_TSEM_LENGTH_MIS 0x224UL
+#define XCM_REGISTERS_TSEM_WEIGHT 0xc0UL
+#define XCM_REGISTERS_UNA_GT_NXT_Q 0x120UL
+#define XCM_REGISTERS_USEM_IFEN 0x2cUL
+#define XCM_REGISTERS_USEM_LENGTH_MIS 0x22cUL
+#define XCM_REGISTERS_USEM_WEIGHT 0xc8UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD00 0x1d4UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD01 0x1d8UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD10 0x1dcUL
+#define XCM_REGISTERS_WU_DA_CNT_CMD11 0x1e0UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL00 0x1e4UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL01 0x1e8UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL10 0x1ecUL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL11 0x1f0UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD00 0x1c4UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD01 0x1c8UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD10 0x1ccUL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD11 0x1d0UL
+#define XCM_REGISTERS_XCM_CFC_IFEN 0x50UL
+#define XCM_REGISTERS_XCM_INT_STS 0x2a8UL
+#define XCM_REGISTERS_XCM_INT_STS_CLR 0x2acUL
+#define XCM_REGISTERS_XCM_INT_STS_WR 0x2b0UL
+#define XCM_REGISTERS_XCM_REG0_SZ 0xf4UL
+#define XCM_REGISTERS_XCM_STORM0_IFEN 0x4UL
+#define XCM_REGISTERS_XCM_STORM1_IFEN 0x8UL
+#define XCM_REGISTERS_XCM_TM_IFEN 0x20UL
+#define XCM_REGISTERS_XCM_XQM_IFEN 0xcUL
+#define XCM_REGISTERS_XCM_XQM_USE_Q 0xf0UL
+#define XCM_REGISTERS_XQM_BYP_ACT_UPD 0xfcUL
+#define XCM_REGISTERS_XQM_INIT_CRD 0x420UL
+#define XCM_REGISTERS_XQM_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_XQM_P_WEIGHT 0xe4UL
+#define XCM_REGISTERS_XQM_XCM_HDR_P 0xa0UL
+#define XCM_REGISTERS_XQM_XCM_HDR_S 0xa4UL
+#define XCM_REGISTERS_XQM_XCM_IFEN 0x14UL
+#define XCM_REGISTERS_XSDM_IFEN 0x18UL
+#define XCM_REGISTERS_XSDM_LENGTH_MIS 0x220UL
+#define XCM_REGISTERS_XSDM_WEIGHT 0xe0UL
+#define XCM_REGISTERS_XX_DESCR_TABLE 0x480UL
+#define XCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define XCM_REGISTERS_XX_INIT_CRD 0x424UL
+#define XCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_XX_MSG_NUM 0x428UL
+#define XCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define XCM_REGISTERS_XX_OVFL_EVNT_ID 0x58UL
+#define XCM_REGISTERS_XX_TABLE 0x500UL
+#define XCM_REGISTERS_XX_TABLE_SIZE 18
+#define XSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define XSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define XSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define XSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define XSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define XSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define XSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define XSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define XSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define XSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define XSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define XSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define XSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define XSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define XSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define XSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define XSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define XSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define XSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define XSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define XSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define XSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define XSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define XSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define XSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define XSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define XSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define XSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define XSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define XSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define XSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define XSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define XSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define XSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define XSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define XSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define XSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define XSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define XSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define XSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define XSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define XSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define XSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define XSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define XSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define XSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define XSDM_REGISTERS_TIMER_TICK 0x0UL
+#define XSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define XSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define XSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define XSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define XSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define XSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define XSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define XSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define XSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define XSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define XSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define XSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define XSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define XSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define XSEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define XSEM_REGISTERS_INT_TABLE 0x400UL
+#define XSEM_REGISTERS_INT_TABLE_SIZE 256
+#define XSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define XSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define XSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define XSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define XSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define XSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define XSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define XSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define XSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define XSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define XSEM_REGISTERS_PRAM 0x40000UL
+#define XSEM_REGISTERS_PRAM_SIZE 65536
+#define XSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define XSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define XSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define XSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define XSEM_REGISTERS_TS_0_AS 0x38UL
+#define XSEM_REGISTERS_TS_10_AS 0x60UL
+#define XSEM_REGISTERS_TS_11_AS 0x64UL
+#define XSEM_REGISTERS_TS_12_AS 0x68UL
+#define XSEM_REGISTERS_TS_13_AS 0x6cUL
+#define XSEM_REGISTERS_TS_14_AS 0x70UL
+#define XSEM_REGISTERS_TS_15_AS 0x74UL
+#define XSEM_REGISTERS_TS_16_AS 0x78UL
+#define XSEM_REGISTERS_TS_17_AS 0x7cUL
+#define XSEM_REGISTERS_TS_18_AS 0x80UL
+#define XSEM_REGISTERS_TS_19_AS 0x84UL
+#define XSEM_REGISTERS_TS_1_AS 0x3cUL
+#define XSEM_REGISTERS_TS_2_AS 0x40UL
+#define XSEM_REGISTERS_TS_3_AS 0x44UL
+#define XSEM_REGISTERS_TS_4_AS 0x48UL
+#define XSEM_REGISTERS_TS_5_AS 0x4cUL
+#define XSEM_REGISTERS_TS_6_AS 0x50UL
+#define XSEM_REGISTERS_TS_7_AS 0x54UL
+#define XSEM_REGISTERS_TS_8_AS 0x58UL
+#define XSEM_REGISTERS_TS_9_AS 0x5cUL
+#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
+#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
+#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
+#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
+#ifndef EMAC_REG_H
+#define EMAC_REG_H
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_MODE_RESET (1L<<0)
+#define EMAC_MODE_RESET_BITSHIFT 0
+#define EMAC_MODE_HALF_DUPLEX (1L<<1)
+#define EMAC_MODE_HALF_DUPLEX_BITSHIFT 1
+#define EMAC_MODE_PORT (0x3L<<2)
+#define EMAC_MODE_PORT_BITSHIFT 2
+#define EMAC_MODE_PORT_NONE (0L<<2)
+#define EMAC_MODE_PORT_NONE_BITSHIFT 2
+#define EMAC_MODE_PORT_MII (1L<<2)
+#define EMAC_MODE_PORT_MII_BITSHIFT 2
+#define EMAC_MODE_PORT_GMII (2L<<2)
+#define EMAC_MODE_PORT_GMII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_MAC_LOOP (1L<<4)
+#define EMAC_MODE_MAC_LOOP_BITSHIFT 4
+#define EMAC_MODE_25G_MODE (1L<<5)
+#define EMAC_MODE_25G_MODE_BITSHIFT 5
+#define EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
+#define EMAC_MODE_TAGGED_MAC_CTL_BITSHIFT 7
+#define EMAC_MODE_TX_BURST (1L<<8)
+#define EMAC_MODE_TX_BURST_BITSHIFT 8
+#define EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
+#define EMAC_MODE_MAX_DEFER_DROP_ENA_BITSHIFT 9
+#define EMAC_MODE_EXT_LINK_POL (1L<<10)
+#define EMAC_MODE_EXT_LINK_POL_BITSHIFT 10
+#define EMAC_MODE_FORCE_LINK (1L<<11)
+#define EMAC_MODE_FORCE_LINK_BITSHIFT 11
+#define EMAC_MODE_MPKT (1L<<18)
+#define EMAC_MODE_MPKT_BITSHIFT 18
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_ACPI_RCVD (1L<<20)
+#define EMAC_MODE_ACPI_RCVD_BITSHIFT 20
+#define EMAC_REG_EMAC_STATUS 0x4
+#define EMAC_STATUS_LINK (1L<<11)
+#define EMAC_STATUS_LINK_BITSHIFT 11
+#define EMAC_STATUS_LINK_CHANGE (1L<<12)
+#define EMAC_STATUS_LINK_CHANGE_BITSHIFT 12
+#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
+#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE_BITSHIFT 13
+#define EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
+#define EMAC_STATUS_SERDES_AUTONEG_CHANGE_BITSHIFT 14
+#define EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
+#define EMAC_STATUS_SERDES_NXT_PG_CHANGE_BITSHIFT 16
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_BITSHIFT 17
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
+#define EMAC_STATUS_MI_COMPLETE (1L<<22)
+#define EMAC_STATUS_MI_COMPLETE_BITSHIFT 22
+#define EMAC_STATUS_MI_INT (1L<<23)
+#define EMAC_STATUS_MI_INT_BITSHIFT 23
+#define EMAC_STATUS_AP_ERROR (1L<<24)
+#define EMAC_STATUS_AP_ERROR_BITSHIFT 24
+#define EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
+#define EMAC_STATUS_PARITY_ERROR_STATE_BITSHIFT 31
+#define EMAC_REG_EMAC_ATTENTION_ENA 0x8
+#define EMAC_ATTENTION_ENA_LINK (1L<<11)
+#define EMAC_ATTENTION_ENA_LINK_BITSHIFT 11
+#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
+#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE_BITSHIFT 14
+#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
+#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE_BITSHIFT 16
+#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
+#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
+#define EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
+#define EMAC_ATTENTION_ENA_MI_COMPLETE_BITSHIFT 22
+#define EMAC_ATTENTION_ENA_MI_INT (1L<<23)
+#define EMAC_ATTENTION_ENA_MI_INT_BITSHIFT 23
+#define EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
+#define EMAC_ATTENTION_ENA_AP_ERROR_BITSHIFT 24
+#define EMAC_REG_EMAC_LED 0xc
+#define EMAC_LED_OVERRIDE (1L<<0)
+#define EMAC_LED_OVERRIDE_BITSHIFT 0
+#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
+#define EMAC_LED_1000MB_OVERRIDE_BITSHIFT 1
+#define EMAC_LED_100MB_OVERRIDE (1L<<2)
+#define EMAC_LED_100MB_OVERRIDE_BITSHIFT 2
+#define EMAC_LED_10MB_OVERRIDE (1L<<3)
+#define EMAC_LED_10MB_OVERRIDE_BITSHIFT 3
+#define EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
+#define EMAC_LED_TRAFFIC_OVERRIDE_BITSHIFT 4
+#define EMAC_LED_BLNK_TRAFFIC (1L<<5)
+#define EMAC_LED_BLNK_TRAFFIC_BITSHIFT 5
+#define EMAC_LED_TRAFFIC (1L<<6)
+#define EMAC_LED_TRAFFIC_BITSHIFT 6
+#define EMAC_LED_1000MB (1L<<7)
+#define EMAC_LED_1000MB_BITSHIFT 7
+#define EMAC_LED_100MB (1L<<8)
+#define EMAC_LED_100MB_BITSHIFT 8
+#define EMAC_LED_10MB (1L<<9)
+#define EMAC_LED_10MB_BITSHIFT 9
+#define EMAC_LED_TRAFFIC_STAT (1L<<10)
+#define EMAC_LED_TRAFFIC_STAT_BITSHIFT 10
+#define EMAC_LED_2500MB (1L<<11)
+#define EMAC_LED_2500MB_BITSHIFT 11
+#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
+#define EMAC_LED_2500MB_OVERRIDE_BITSHIFT 12
+#define EMAC_LED_ACTIVITY_SEL (0x3L<<17)
+#define EMAC_LED_ACTIVITY_SEL_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
+#define EMAC_LED_ACTIVITY_SEL_0_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
+#define EMAC_LED_ACTIVITY_SEL_1_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
+#define EMAC_LED_ACTIVITY_SEL_2_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
+#define EMAC_LED_ACTIVITY_SEL_3_BITSHIFT 17
+#define EMAC_LED_BLNK_RATE (0xfffL<<19)
+#define EMAC_LED_BLNK_RATE_BITSHIFT 19
+#define EMAC_LED_BLNK_RATE_ENA (1L<<31)
+#define EMAC_LED_BLNK_RATE_ENA_BITSHIFT 31
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MAC_MATCH_COUNT 32
+#define EMAC_REG_EMAC_UNUSED1 0x90
+#define EMAC_REG_EMAC_UNUSED1_COUNT 2
+#define EMAC_REG_EMAC_BACKOFF_SEED 0x98
+#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
+#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED_BITSHIFT 0
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
+#define EMAC_RX_MTU_SIZE_MTU_SIZE_BITSHIFT 0
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED2 0xa0
+#define EMAC_REG_EMAC_UNUSED2_COUNT 3
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
+#define EMAC_MDIO_COMM_DATA_BITSHIFT 0
+#define EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
+#define EMAC_MDIO_COMM_REG_ADDR_BITSHIFT 16
+#define EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
+#define EMAC_MDIO_COMM_PHY_ADDR_BITSHIFT 21
+#define EMAC_MDIO_COMM_COMMAND (0x3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_INC_45 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_INC_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_FAIL (1L<<28)
+#define EMAC_MDIO_COMM_FAIL_BITSHIFT 28
+#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
+#define EMAC_MDIO_COMM_START_BUSY_BITSHIFT 29
+#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
+#define EMAC_MDIO_STATUS_LINK (1L<<0)
+#define EMAC_MDIO_STATUS_LINK_BITSHIFT 0
+#define EMAC_MDIO_STATUS_10MB (1L<<1)
+#define EMAC_MDIO_STATUS_10MB_BITSHIFT 1
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
+#define EMAC_MDIO_MODE_SHORT_PREAMBLE_BITSHIFT 1
+#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
+#define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT 4
+#define EMAC_MDIO_MODE_BIT_BANG (1L<<8)
+#define EMAC_MDIO_MODE_BIT_BANG_BITSHIFT 8
+#define EMAC_MDIO_MODE_MDIO (1L<<9)
+#define EMAC_MDIO_MODE_MDIO_BITSHIFT 9
+#define EMAC_MDIO_MODE_MDIO_OE (1L<<10)
+#define EMAC_MDIO_MODE_MDIO_OE_BITSHIFT 10
+#define EMAC_MDIO_MODE_MDC (1L<<11)
+#define EMAC_MDIO_MODE_MDC_BITSHIFT 11
+#define EMAC_MDIO_MODE_MDINT (1L<<12)
+#define EMAC_MDIO_MODE_MDINT_BITSHIFT 12
+#define EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
+#define EMAC_MDIO_MODE_EXT_MDINT_BITSHIFT 13
+#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
+#define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT 31
+#define EMAC_REG_EMAC_MDIO_AUTO_STATUS 0xb8
+#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
+#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR_BITSHIFT 0
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_TX_MODE_RESET (1L<<0)
+#define EMAC_TX_MODE_RESET_BITSHIFT 0
+#define EMAC_TX_MODE_CS16_TEST (1L<<2)
+#define EMAC_TX_MODE_CS16_TEST_BITSHIFT 2
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+#define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT 3
+#define EMAC_TX_MODE_FLOW_EN (1L<<4)
+#define EMAC_TX_MODE_FLOW_EN_BITSHIFT 4
+#define EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
+#define EMAC_TX_MODE_BIG_BACKOFF_BITSHIFT 5
+#define EMAC_TX_MODE_LONG_PAUSE (1L<<6)
+#define EMAC_TX_MODE_LONG_PAUSE_BITSHIFT 6
+#define EMAC_TX_MODE_LINK_AWARE (1L<<7)
+#define EMAC_TX_MODE_LINK_AWARE_BITSHIFT 7
+#define EMAC_REG_EMAC_TX_STATUS 0xc0
+#define EMAC_TX_STATUS_XOFFED (1L<<0)
+#define EMAC_TX_STATUS_XOFFED_BITSHIFT 0
+#define EMAC_TX_STATUS_XOFF_SENT (1L<<1)
+#define EMAC_TX_STATUS_XOFF_SENT_BITSHIFT 1
+#define EMAC_TX_STATUS_XON_SENT (1L<<2)
+#define EMAC_TX_STATUS_XON_SENT_BITSHIFT 2
+#define EMAC_TX_STATUS_LINK_UP (1L<<3)
+#define EMAC_TX_STATUS_LINK_UP_BITSHIFT 3
+#define EMAC_TX_STATUS_UNDERRUN (1L<<4)
+#define EMAC_TX_STATUS_UNDERRUN_BITSHIFT 4
+#define EMAC_TX_STATUS_CS16_ERROR (1L<<5)
+#define EMAC_TX_STATUS_CS16_ERROR_BITSHIFT 5
+#define EMAC_REG_EMAC_TX_LENGTHS 0xc4
+#define EMAC_TX_LENGTHS_SLOT (0xffL<<0)
+#define EMAC_TX_LENGTHS_SLOT_BITSHIFT 0
+#define EMAC_TX_LENGTHS_IPG (0xfL<<8)
+#define EMAC_TX_LENGTHS_IPG_BITSHIFT 8
+#define EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
+#define EMAC_TX_LENGTHS_IPG_CRS_BITSHIFT 12
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_RX_MODE_RESET (1L<<0)
+#define EMAC_RX_MODE_RESET_BITSHIFT 0
+#define EMAC_RX_MODE_FLOW_EN (1L<<2)
+#define EMAC_RX_MODE_FLOW_EN_BITSHIFT 2
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL_BITSHIFT 3
+#define EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
+#define EMAC_RX_MODE_KEEP_PAUSE_BITSHIFT 4
+#define EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
+#define EMAC_RX_MODE_ACCEPT_OVERSIZE_BITSHIFT 5
+#define EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
+#define EMAC_RX_MODE_ACCEPT_RUNTS_BITSHIFT 6
+#define EMAC_RX_MODE_LLC_CHK (1L<<7)
+#define EMAC_RX_MODE_LLC_CHK_BITSHIFT 7
+#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
+#define EMAC_RX_MODE_PROMISCUOUS_BITSHIFT 8
+#define EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
+#define EMAC_RX_MODE_NO_CRC_CHK_BITSHIFT 9
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG_BITSHIFT 10
+#define EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
+#define EMAC_RX_MODE_FILT_BROADCAST_BITSHIFT 11
+#define EMAC_RX_MODE_SORT_MODE (1L<<12)
+#define EMAC_RX_MODE_SORT_MODE_BITSHIFT 12
+#define EMAC_REG_EMAC_RX_STATUS 0xcc
+#define EMAC_RX_STATUS_FFED (1L<<0)
+#define EMAC_RX_STATUS_FFED_BITSHIFT 0
+#define EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
+#define EMAC_RX_STATUS_FF_RECEIVED_BITSHIFT 1
+#define EMAC_RX_STATUS_N_RECEIVED (1L<<2)
+#define EMAC_RX_STATUS_N_RECEIVED_BITSHIFT 2
+#define EMAC_REG_EMAC_MULTICAST_HASH 0xd0
+#define EMAC_REG_EMAC_MULTICAST_HASH_COUNT 8
+#define EMAC_REG_EMAC_CKSUM_ERROR_STATUS 0xf0
+#define EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
+#define EMAC_CKSUM_ERROR_STATUS_CALCULATED_BITSHIFT 0
+#define EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
+#define EMAC_CKSUM_ERROR_STATUS_EXPECTED_BITSHIFT 16
+#define EMAC_REG_EMAC_UNUSED3 0xf4
+#define EMAC_REG_EMAC_UNUSED3_COUNT 3
+#define EMAC_REG_EMAC_RX_STAT_IFHCINOCTETS 0x100
+#define EMAC_REG_EMAC_RX_STAT_IFHCINBADOCTETS 0x104
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x108
+#define EMAC_REG_EMAC_RX_STAT_IFHCINUCASTPKTS 0x10c
+#define EMAC_REG_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x110
+#define EMAC_REG_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x114
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x118
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x11c
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x120
+#define EMAC_REG_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x124
+#define EMAC_REG_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x128
+#define EMAC_REG_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x12c
+#define EMAC_REG_EMAC_RX_STAT_XOFFSTATEENTERED 0x130
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x134
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSJABBERS 0x138
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x13c
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x140
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x144
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x148
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x14c
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x150
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x154
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x158
+#define EMAC_REG_EMAC_RXMAC_DEBUG0 0x15c
+#define EMAC_REG_EMAC_RXMAC_DEBUG1 0x160
+#define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
+#define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
+#define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE_BITSHIFT 1
+#define EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
+#define EMAC_RXMAC_DEBUG1_BAD_CRC_BITSHIFT 2
+#define EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
+#define EMAC_RXMAC_DEBUG1_RX_ERROR_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
+#define EMAC_RXMAC_DEBUG1_ALIGN_ERROR_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
+#define EMAC_RXMAC_DEBUG1_LAST_DATA_BITSHIFT 5
+#define EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
+#define EMAC_RXMAC_DEBUG1_ODD_BYTE_START_BITSHIFT 6
+#define EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
+#define EMAC_RXMAC_DEBUG1_BYTE_COUNT_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
+#define EMAC_RXMAC_DEBUG1_SLOT_TIME_BITSHIFT 23
+#define EMAC_REG_EMAC_RXMAC_DEBUG2 0x164
+#define EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SFD (1L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SFD_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DATA (2L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DATA_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (3L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_EXT (4L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_EXT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DROP (5L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DROP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (6L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_FC (7L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_FC_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (1L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (2L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (3L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (4L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (5L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (6L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (7L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (8L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
+#define EMAC_RXMAC_DEBUG2_BYTE_IN_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
+#define EMAC_RXMAC_DEBUG2_FALSEC_BITSHIFT 15
+#define EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
+#define EMAC_RXMAC_DEBUG2_TAGGED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
+#define EMAC_RXMAC_DEBUG2_SE_COUNTER_BITSHIFT 19
+#define EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
+#define EMAC_RXMAC_DEBUG2_QUANTA_BITSHIFT 23
+#define EMAC_REG_EMAC_RXMAC_DEBUG3 0x168
+#define EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
+#define EMAC_RXMAC_DEBUG3_PAUSE_CTR_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
+#define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR_BITSHIFT 16
+#define EMAC_REG_EMAC_RXMAC_DEBUG4 0x16c
+#define EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
+#define EMAC_RXMAC_DEBUG4_TYPE_FIELD_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (1L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (2L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (3L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (5L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (6L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (7L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (7L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (8L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (9L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (10L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (14L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (15L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (16L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC (17L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (18L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (19L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (20L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (21L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (22L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (23L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC (24L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (25L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (26L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (27L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (28L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (29L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XON (30L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XON_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (31L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (32L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (33L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (34L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (35L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (36L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (37L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (38L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (39L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (40L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (41L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (42L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
+#define EMAC_RXMAC_DEBUG4_DROP_PKT_BITSHIFT 22
+#define EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
+#define EMAC_RXMAC_DEBUG4_SLOT_FILLED_BITSHIFT 23
+#define EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
+#define EMAC_RXMAC_DEBUG4_FALSE_CARRIER_BITSHIFT 24
+#define EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
+#define EMAC_RXMAC_DEBUG4_LAST_DATA_BITSHIFT 25
+#define EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
+#define EMAC_RXMAC_DEBUG4_SFD_FOUND_BITSHIFT 26
+#define EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
+#define EMAC_RXMAC_DEBUG4_ADVANCE_BITSHIFT 27
+#define EMAC_RXMAC_DEBUG4_START (1L<<28)
+#define EMAC_RXMAC_DEBUG4_START_BITSHIFT 28
+#define EMAC_REG_EMAC_RXMAC_DEBUG5 0x170
+#define EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (1L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (2L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (3L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (4L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (6L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (7L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
+#define EMAC_RXMAC_DEBUG5_EOF_DETECTED_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF0_BITSHIFT 8
+#define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
+#define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL_BITSHIFT 11
+#define EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
+#define EMAC_RXMAC_DEBUG5_LOAD_CCODE_BITSHIFT 12
+#define EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
+#define EMAC_RXMAC_DEBUG5_LOAD_DATA_BITSHIFT 13
+#define EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
+#define EMAC_RXMAC_DEBUG5_LOAD_STAT_BITSHIFT 14
+#define EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
+#define EMAC_RXMAC_DEBUG5_CLR_STAT_BITSHIFT 15
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT_BITSHIFT 19
+#define EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
+#define EMAC_RXMAC_DEBUG5_FMLEN_BITSHIFT 20
+#define EMAC_REG_EMAC_RX_STAT_FALSECARRIERERRORS 0x174
+#define EMAC_REG_EMAC_UNUSED4 0x178
+#define EMAC_REG_EMAC_UNUSED4_COUNT 2
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x1dc
+#define EMAC_REG_EMAC_UNUSED5 0x1e0
+#define EMAC_REG_EMAC_UNUSED5_COUNT 5
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_UNUSED9 0x1f8
+#define EMAC_REG_EMAC_UNUSED9_COUNT 2
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTOCTETS 0x200
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x204
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x208
+#define EMAC_REG_EMAC_TX_STAT_OUTXONSENT 0x20c
+#define EMAC_REG_EMAC_TX_STAT_OUTXOFFSENT 0x210
+#define EMAC_REG_EMAC_TX_STAT_FLOWCONTROLDONE 0x214
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x218
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x21c
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x220
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x224
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x228
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x22c
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x230
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x234
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x238
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x23c
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x240
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x244
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x248
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x24c
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x250
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x254
+#define EMAC_REG_EMAC_TXMAC_DEBUG0 0x258
+#define EMAC_REG_EMAC_TXMAC_DEBUG1 0x25c
+#define EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (1L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_START0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (4L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (5L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (6L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (7L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (8L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (9L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
+#define EMAC_TXMAC_DEBUG1_CRS_ENABLE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
+#define EMAC_TXMAC_DEBUG1_BAD_CRC_BITSHIFT 5
+#define EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
+#define EMAC_TXMAC_DEBUG1_SE_COUNTER_BITSHIFT 6
+#define EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
+#define EMAC_TXMAC_DEBUG1_SEND_PAUSE_BITSHIFT 10
+#define EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
+#define EMAC_TXMAC_DEBUG1_LATE_COLLISION_BITSHIFT 11
+#define EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
+#define EMAC_TXMAC_DEBUG1_MAX_DEFER_BITSHIFT 12
+#define EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
+#define EMAC_TXMAC_DEBUG1_DEFERRED_BITSHIFT 13
+#define EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
+#define EMAC_TXMAC_DEBUG1_ONE_BYTE_BITSHIFT 14
+#define EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
+#define EMAC_TXMAC_DEBUG1_IPG_TIME_BITSHIFT 15
+#define EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
+#define EMAC_TXMAC_DEBUG1_SLOT_TIME_BITSHIFT 19
+#define EMAC_REG_EMAC_TXMAC_DEBUG2 0x260
+#define EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
+#define EMAC_TXMAC_DEBUG2_BACK_OFF_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
+#define EMAC_TXMAC_DEBUG2_BYTE_COUNT_BITSHIFT 10
+#define EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
+#define EMAC_TXMAC_DEBUG2_COL_COUNT_BITSHIFT 26
+#define EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
+#define EMAC_TXMAC_DEBUG2_COL_BIT_BITSHIFT 31
+#define EMAC_REG_EMAC_TXMAC_DEBUG3 0x264
+#define EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (1L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (2L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SFD (3L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SFD_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_DATA (4L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_DATA_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (5L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (6L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EXT (7L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EXT_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATB (8L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATB_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATG (9L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATG_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_JAM (10L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_JAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (11L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (12L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (13L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (14L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (1L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (2L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_MC (3L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_MC_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (4L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (5L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC (6L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
+#define EMAC_TXMAC_DEBUG3_CRS_DONE_BITSHIFT 7
+#define EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
+#define EMAC_TXMAC_DEBUG3_XOFF_BITSHIFT 8
+#define EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
+#define EMAC_TXMAC_DEBUG3_SE_COUNTER_BITSHIFT 9
+#define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
+#define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER_BITSHIFT 13
+#define EMAC_REG_EMAC_TXMAC_DEBUG4 0x268
+#define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
+#define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (2L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (3L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (4L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (5L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (6L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (7L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (8L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (9L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (10L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (12L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (13L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (14L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
+#define EMAC_TXMAC_DEBUG4_STATS0_VALID_BITSHIFT 20
+#define EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
+#define EMAC_TXMAC_DEBUG4_APPEND_CRC_BITSHIFT 21
+#define EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
+#define EMAC_TXMAC_DEBUG4_SLOT_FILLED_BITSHIFT 22
+#define EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
+#define EMAC_TXMAC_DEBUG4_MAX_DEFER_BITSHIFT 23
+#define EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
+#define EMAC_TXMAC_DEBUG4_SEND_EXTEND_BITSHIFT 24
+#define EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
+#define EMAC_TXMAC_DEBUG4_SEND_PADDING_BITSHIFT 25
+#define EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
+#define EMAC_TXMAC_DEBUG4_EOF_LOC_BITSHIFT 26
+#define EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
+#define EMAC_TXMAC_DEBUG4_COLLIDING_BITSHIFT 27
+#define EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
+#define EMAC_TXMAC_DEBUG4_COL_IN_BITSHIFT 28
+#define EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
+#define EMAC_TXMAC_DEBUG4_BURSTING_BITSHIFT 29
+#define EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
+#define EMAC_TXMAC_DEBUG4_ADVANCE_BITSHIFT 30
+#define EMAC_TXMAC_DEBUG4_GO (1L<<31)
+#define EMAC_TXMAC_DEBUG4_GO_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED6 0x26c
+#define EMAC_REG_EMAC_UNUSED6_COUNT 5
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x2d8
+#define EMAC_REG_EMAC_UNUSED7 0x2dc
+#define EMAC_REG_EMAC_UNUSED7_COUNT 8
+#define EMAC_REG_EMAC_TX_RATE_LIMIT_CTRL 0x2fc
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC_BITSHIFT 0
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM_BITSHIFT 16
+#define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
+#define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED8 0x300
+#define EMAC_REG_EMAC_UNUSED8_COUNT 64
+#endif
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
+#define EMAC_MDIO_COMM_DATA_BITSHIFT 0
+#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
+#define EMAC_MDIO_COMM_START_BUSY_BITSHIFT 29
+#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
+#define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT 4
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
+#define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT 31
+#define EMAC_MODE_25G_MODE (1L<<5)
+#define EMAC_MODE_25G_MODE_BITSHIFT 5
+#define EMAC_MODE_ACPI_RCVD (1L<<20)
+#define EMAC_MODE_ACPI_RCVD_BITSHIFT 20
+#define EMAC_MODE_HALF_DUPLEX (1L<<1)
+#define EMAC_MODE_HALF_DUPLEX_BITSHIFT 1
+#define EMAC_MODE_MPKT (1L<<18)
+#define EMAC_MODE_MPKT_BITSHIFT 18
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_PORT_GMII (2L<<2)
+#define EMAC_MODE_PORT_GMII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII (1L<<2)
+#define EMAC_MODE_PORT_MII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_RESET (1L<<0)
+#define EMAC_MODE_RESET_BITSHIFT 0
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MAC_MATCH_COUNT 32
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_RX_MODE_FLOW_EN (1L<<2)
+#define EMAC_RX_MODE_FLOW_EN_BITSHIFT 2
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG_BITSHIFT 10
+#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
+#define EMAC_RX_MODE_PROMISCUOUS_BITSHIFT 8
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT 31
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+#define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT 3
+#define EMAC_TX_MODE_RESET (1L<<0)
+#define EMAC_TX_MODE_RESET_BITSHIFT 0
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x6424
+#define MCP_REG_MCPR_NVM_ADDR 0x640c
+#define MCP_REG_MCPR_NVM_CFG4 0x642c
+#define MCP_REG_MCPR_NVM_COMMAND 0x6400
+#define MCP_REG_MCPR_NVM_READ 0x6410
+#define MCP_REG_MCPR_NVM_SW_ARB 0x6420
+#define MCP_REG_MCPR_NVM_WRITE 0x6408
+#define MCP_REG_MCPR_NVM_WRITE1 0x6428
+#define MCP_REG_MCPR_SCRATCH 0x20000
+#define MCP_REG_MCPR_SCRATCH_COUNT 16384
+#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
+#define MCPR_NVM_ACCESS_ENABLE_EN_BITSHIFT 0
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN_BITSHIFT 1
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI (1L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO (2L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT_BITSHIFT 0
+#define MCPR_NVM_COMMAND_DOIT (1L<<4)
+#define MCPR_NVM_COMMAND_DOIT_BITSHIFT 4
+#define MCPR_NVM_COMMAND_DONE (1L<<3)
+#define MCPR_NVM_COMMAND_DONE_BITSHIFT 3
+#define MCPR_NVM_COMMAND_FIRST (1L<<7)
+#define MCPR_NVM_COMMAND_FIRST_BITSHIFT 7
+#define MCPR_NVM_COMMAND_LAST (1L<<8)
+#define MCPR_NVM_COMMAND_LAST_BITSHIFT 8
+#define MCPR_NVM_COMMAND_WR (1L<<5)
+#define MCPR_NVM_COMMAND_WR_BITSHIFT 5
+#define MCPR_NVM_COMMAND_WREN (1L<<16)
+#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
+#define MCPR_NVM_COMMAND_WRDI (1L<<17)
+#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
+#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
+#define MCPR_NVM_SW_ARB_ARB_ARB1_BITSHIFT 9
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1_BITSHIFT 5
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1_BITSHIFT 1
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_1_RST_USEM (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_1_RST_UPB (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_1_RST_CCM (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSEM (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSDM (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCU (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_1_RST_PBF (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_RST_TM (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_XCM (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSDM (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCT (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_1_RST_CDU (0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_RST_CFC (0x1<<25)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCP (0x1<<28)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_DMAE (0x1<<30)
+#define MISC_REGISTERS_RESET_REG_1_RST_SEMI_RTC (0x1<<31)
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBG (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBUE (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_3_SET MISC_REGISTERS_RESET_REG_3+4
+#define MISC_REGISTERS_RESET_REG_3_CLEAR MISC_REGISTERS_RESET_REG_3+8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB
(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_RSTB_HW (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_IDDQ (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN_SD (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_RSTB_HW (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_IDDQ (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN_SD (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_TXD_FIFO_RSTB
(0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_1_RST_USEM (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_1_RST_UPB (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_1_RST_CCM (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSEM (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSDM (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCU (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_1_RST_PBF (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_RST_TM (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_XCM (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSDM (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCT (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_1_RST_CDU (0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_RST_CFC (0x1<<25)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCP (0x1<<28)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_DMAE (0x1<<30)
+#define MISC_REGISTERS_RESET_REG_1_RST_SEMI_RTC (0x1<<31)
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBG (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBUE (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_3_CLEAR MISC_REGISTERS_RESET_REG_3+8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB
(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_SET MISC_REGISTERS_RESET_REG_3+4
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
+#ifndef __5710_INT_OFFSETS__
+#define __5710_INT_OFFSETS__
+
+#define TSTORM_PORT_COMMON_CONFIG_OFFSET(port) (0x1500 + (port * 0x28))
+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port) (0x1504 + (port * 0x28))
+#define TSTORM_RCQ_PROD_OFFSET(port, client_id) (0x15e0 + (port *
0x1b0) + \
+(client_id * 0x18))
+#define TSTORM_RCQ_PROD_SIZE 0x2
+#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) (0x15e8 + \
+(port * 0x1b0) + (client_id * 0x18))
+#define USTORM_BYTE_COUNTER_OFFSET(port, cpuID) (0x1d94 + \
+(port * 0x90) + (cpuID * 0x8))
+#define USTORM_BYTE_COUNTER_SIZE 0x4
+#define USTORM_DYNAMIC_HC_CONFIG_OFFSET(port) (0x1d80 + \
+(port * 0x90))
+#define USTORM_DYNAMIC_HC_CONFIG_SIZE 0x10
+#define USTORM_GRQ_CACHE_BD_LO_OFFSET(cpu_id, port, grq_bd_num) \
+(0x3000 + (cpu_id * 0x100) + (port * 0x80) + (grq_bd_num * 0x8))
+#define USTORM_GRQ_CACHE_BD_HI_OFFSET(cpu_id, port, grq_bd_num) \
+(0x3004 + (cpu_id * 0x100) + (port * 0x80) + (grq_bd_num * 0x8))
+#define COMMON_SB_HOST_SB_ADDR_SIZE 0x8
+#define COMMON_SB_HC_TIMEOUT_SIZE 0x1
+#define COMMON_SB_HC_DISABLE_SIZE 0x2
+#define COMMON_HC_BTR_SIZE 0x4
+#define COMMON_ASM_ASSERT_MSG_SIZE 0x10
+#define COMMON_ASM_ASSERT_INDEX_SIZE 0x8
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+#define XSTORM_SPQ_PAGE_BASE_OFFSET(port) (0x5328 + (port * 0x18))
+#define XSTORM_SPQ_PAGE_BASE_SIZE 0x8
+#define XSTORM_SPQ_PROD_OFFSET(port) (0x5330 + (port * 0x18))
+#define XSTORM_SPQ_PROD_SIZE 0x4
+#define XSTORM_VIRTUALIZATION_MODE_OFFSET 0x5120
+#define XSTORM_VIRTUALIZATION_MODE_SIZE 0x8
+#define XSTORM_JUMBO_SUPPORT_OFFSET(port) (0x5370 + (port * 0x4))
+#define XSTORM_JUMBO_SUPPORT_SIZE 0x1
+#define XSTORM_COMMON_IP_ID_MASK_OFFSET 0x5378
+#define XSTORM_COMMON_IP_ID_MASK_SIZE 0x2
+#define XSTORM_COMMON_RTC_PARAMS_OFFSET 0x5380
+#define XSTORM_COMMON_RTC_PARAMS_SIZE 0x8
+#define XSTORM_COMMON_RTC_RESOLUTION_OFFSET 0x5384
+#define XSTORM_COMMON_RTC_RESOLUTION_SIZE 0x2
+#define XSTORM_FW_VERSION_OFFSET 0x5428
+#define XSTORM_FW_VERSION_SIZE 0x8
+#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
+#define XSTORM_STATS_FLAGS_SIZE 0x8
+#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x5408 + (port * 0x8))
+#define XSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define XSTORM_CMNG_VARS_OFFSET(port) (0x5438 + (port * 0xc0))
+#define XSTORM_CMNG_VARS_SIZE 0xc0
+#define XSTORM_COS2PROTOCOL_OFFSET(port) (0x55b8 + (port * 0x10))
+#define XSTORM_COS2PROTOCOL_SIZE 0x10
+#define XSTORM_CON_NUMBER_OFFSET(port) (0x54f0 + (port * 0x438))
+#define XSTORM_CON_NUMBER_SIZE 0x4
+#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1400 + (port * 0x28))
+#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1408 + (port *
0x28))
+#define XSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define XSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1418 + (port * 0x28) + (index * 0x4))
+#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x141a + (port * 0x28) + (index * 0x4))
+#define XSTORM_HC_BTR_OFFSET(port) (0x1454 + (port * 0x18))
+#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define TSTORM_INDIRECTION_TABLE_OFFSET(port) (0x22c8 + (port * 0x80))
+#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+#define TSTORM_INDIRECTION_TABLE_ENTRY_SIZE 0x1
+#define TSTORM_STATISTICS_OFFSET(port) (0x4000 + (port * 0x540))
+#define TSTORM_STATISTICS_SIZE 0x540
+#define TSTORM_COMMON_RTC_PARAMS_OFFSET 0x26c8
+#define TSTORM_COMMON_RTC_PARAMS_SIZE 0x8
+#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4aa0 + (port * 0x8))
+#define TSTORM_STATS_FLAGS_SIZE 0x8
+#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x4a80 + (port * 0x8))
+#define TSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1400 + (port * 0x28))
+#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1408 + (port *
0x28))
+#define TSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define TSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1418 + (port * 0x28) + (index * 0x4))
+#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x141a + (port * 0x28) + (index * 0x4))
+#define TSTORM_HC_BTR_OFFSET(port) (0x1454 + (port * 0x18))
+#define TSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define TSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1900 + (port * 0x40))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1908 + (port *
0x40))
+#define CSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x18
+#define CSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1920 + (port * 0x40) + (index * 0x4))
+#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x1922 + (port * 0x40) + (index * 0x4))
+#define CSTORM_HC_BTR_OFFSET(port) (0x1984 + (port * 0xc0))
+#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
+(0x1400 + (port * 0x280) + (cpu_id * 0x28))
+#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
+(0x1408 + (port * 0x280) + (cpu_id * 0x28))
+#define CSTORM_SB_STATUS_BLOCK_SIZE 0x18
+#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
+(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
+(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define CSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
+#define CSTORM_STATS_FLAGS_SIZE 0x8
+#define CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x5118 + (port * 0x8))
+#define CSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define USTORM_INDIRECTION_TABLE_OFFSET(port) (0x5308 + (port * 0x80))
+#define USTORM_INDIRECTION_TABLE_SIZE 0x80
+#define USTORM_INDIRECTION_TABLE_ENTRY_SIZE 0x1
+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET 0x5408
+#define USTORM_MEM_WORKAROUND_ADDRESS_SIZE 0x8
+#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1900 + (port * 0x28))
+#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1908 + (port *
0x28))
+#define USTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define USTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1918 + (port * 0x28) + (index * 0x4))
+#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x191a + (port * 0x28) + (index * 0x4))
+#define USTORM_HC_BTR_OFFSET(port) (0x1954 + (port * 0xb8))
+#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
+(0x1400 + (port * 0x280) + (cpu_id * 0x28))
+#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
+(0x1408 + (port * 0x280) + (cpu_id * 0x28))
+#define USTORM_SB_STATUS_BLOCK_SIZE 0x10
+#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
+(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
+(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define USTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define USTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+
+#endif
+#ifndef __FW_DEFS_H__
+#define __FW_DEFS_H__
+
+#define BCM_5710_FW_MAJOR_VERSION 4
+#define BCM_5710_FW_MINOR_VERSION 0
+#define BCM_5710_FW_REVISION_VERSION 7
+#define BCM_5710_FW_COMPILE_FLAGS 1
+
+#endif
+/****************************************************************************
+* Copyright(c) 2001-2006 Broadcom Corporation, all rights reserved
+* Proprietary and Confidential Information.
+*
+* Name: mcp_shmem.h
+*
+* Description: MCP Sheared memory map
+*
+* Created: 05/03/2006 eilong
+*
+* $Date: 2007/10/02 $ $Revision: #44 $
+****************************************************************************/
+
+#ifndef MCP_SHMEM_H
+#define MCP_SHMEM_H
+
+
+#define FUNC_0 0
+#define FUNC_1 1
+#define FUNC_MAX 2
+
+
+/* This value (in milliseconds) determines the frequency of the driver
+* issuing the PULSE message code. The firmware monitors this periodic
+* pulse to determine when to switch to an OS-absent mode. */
+#define DRV_PULSE_PERIOD_MS 250
+
+/* This value (in milliseconds) determines how long the driver should
+* wait for an acknowledgement from the firmware before timing out. Once
+* the firmware has timed out, the driver will assume there is no firmware
+* running and there won't be any firmware-driver synchronization during a
+* driver reset. */
+#define FW_ACK_TIME_OUT_MS 5000
+
+#define FW_ACK_POLL_TIME_MS 1
+
+#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
+
+
+/****************************************************************************
+* Driver <-> FW Mailbox *
+****************************************************************************/
+struct drv_fw_mb_t
+{
+u32 drv_mb_header;
+#define DRV_MSG_CODE_MASK 0xffff0000
+#define DRV_MSG_CODE_LOAD_REQ 0x10000000
+#define DRV_MSG_CODE_LOAD_DONE 0x11000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
+#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
+#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
+#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
+#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
+#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
+#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
+#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
+#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
+
+#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
+
+u32 drv_mb_param;
+
+u32 fw_mb_header;
+#define FW_MSG_CODE_MASK 0xffff0000
+#define FW_MSG_CODE_DRV_LOAD_COMMON 0x11000000
+#define FW_MSG_CODE_DRV_LOAD_PORT 0x12000000
+#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x13000000
+#define FW_MSG_CODE_DRV_LOAD_DONE 0x14000000
+#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x21000000
+#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x22000000
+#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x23000000
+#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50000000
+#define FW_MSG_CODE_DIAG_REFUSE 0x51000000
+#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70000000
+#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x71000000
+#define FW_MSG_CODE_GET_KEY_DONE 0x80000000
+#define FW_MSG_CODE_NO_KEY 0x8f000000
+#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x8f800000
+#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90000000
+#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x91000000
+#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x92000000
+#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x93000000
+#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x94000000
+
+#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
+
+u32 fw_mb_param;
+
+u32 link_status;
+
+#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
+#define LINK_STATUS_LINK_UP 0x00000001
+
+#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
+#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
+
+#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
+#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
+
+#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
+#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
+#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
+
+#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
+#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
+#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
+#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
+#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
+#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
+#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
+
+#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
+#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
+
+#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
+#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
+
+#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
+#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
+#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
+#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
+#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
+
+#define LINK_STATUS_SERDES_LINK 0x00100000
+
+#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
+#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
+#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
+#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
+#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
+#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
+#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
+#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
+
+u32 drv_pulse_mb;
+#define DRV_PULSE_SEQ_MASK 0x00007fff
+#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
+/* The system time is in the format of
+* (year-2001)*12*32 + month*32 + day. */
+#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
+/* Indicate to the firmware not to go into the
+* OS-absent when it is not getting driver pulse.
+* This is used for debugging as well for PXE(MBA). */
+
+u32 mcp_pulse_mb;
+#define MCP_PULSE_SEQ_MASK 0x00007fff
+#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
+/* Indicates to the driver not to assert due to lack
+* of MCP response */
+#define MCP_EVENT_MASK 0xffff0000
+#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
+
+} drv_fw_mb_t;
+
+
+/****************************************************************************
+* Shared HW configuration *
+****************************************************************************/
+struct shared_hw_cfg_t
+{
+u8 part_num[16];
+
+u32 config;
+#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
+#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
+#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
+#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
+
+#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
+
+#define SHARED_HW_CFG_PORT_SWAP 0x00000004
+
+#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
+
+#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
+#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
+#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
+#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
+#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
+#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
+
+#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
+#define SHARED_HW_CFG_LED_MODE_SHIFT 16
+#define SHARED_HW_CFG_LED_MAC1 0x00000000
+#define SHARED_HW_CFG_LED_PHY1 0x00010000
+#define SHARED_HW_CFG_LED_PHY2 0x00020000
+#define SHARED_HW_CFG_LED_PHY3 0x00030000
+#define SHARED_HW_CFG_LED_MAC2 0x00040000
+#define SHARED_HW_CFG_LED_PHY4 0x00050000
+#define SHARED_HW_CFG_LED_PHY5 0x00060000
+#define SHARED_HW_CFG_LED_PHY6 0x00070000
+#define SHARED_HW_CFG_LED_MAC3 0x00080000
+#define SHARED_HW_CFG_LED_PHY7 0x00090000
+#define SHARED_HW_CFG_LED_PHY9 0x000a0000
+#define SHARED_HW_CFG_LED_PHY11 0x000b0000
+#define SHARED_HW_CFG_LED_MAC4 0x000c0000
+#define SHARED_HW_CFG_LED_PHY8 0x000d0000
+
+#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
+#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
+#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
+#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
+#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
+#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
+#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
+#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
+
+u32 config2;
+
+#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
+#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
+
+#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
+
+/* The default value for the core clock is 250MHz and it is
+achieved by setting the clock change to 4 */
+#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
+#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
+
+#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
+#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
+
+u32 power_dissipated;
+#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
+#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
+
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
+#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
+
+u32 ump_nc_si_config;
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
+
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
+
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
+
+u32 board;
+#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
+#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
+#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
+
+#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
+#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
+#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
+#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
+#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
+#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
+
+u32 reserved;
+
+};
+
+/****************************************************************************
+* Port HW configuration *
+****************************************************************************/
+struct port_hw_cfg_t
+{
+
+u32 pci_id;
+#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
+#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
+
+u32 pci_sub_id;
+#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
+#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
+
+u32 power_dissipated;
+#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
+#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
+#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
+#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
+#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
+#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
+#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
+#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
+
+u32 power_consumed;
+#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
+#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
+#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
+#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
+#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
+#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
+#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
+#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
+
+u32 mac_upper;
+#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
+#define PORT_HW_CFG_UPPERMAC_SHIFT 0
+u32 mac_lower;
+
+u32 iscsi_mac_upper;
+u32 iscsi_mac_lower;
+
+u32 rdma_mac_upper;
+u32 rdma_mac_lower;
+
+u32 serdes_config;
+
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
+
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
+
+u16 serdes_tx_driver_pre_emphasis[16];
+u16 serdes_rx_driver_equalizer[16];
+
+u32 xgxs_config_lane0;
+u32 xgxs_config_lane1;
+u32 xgxs_config_lane2;
+u32 xgxs_config_lane3;
+
+#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
+#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
+
+#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
+#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
+
+u16 xgxs_tx_driver_pre_emphasis_lane0[16];
+u16 xgxs_tx_driver_pre_emphasis_lane1[16];
+u16 xgxs_tx_driver_pre_emphasis_lane2[16];
+u16 xgxs_tx_driver_pre_emphasis_lane3[16];
+
+u16 xgxs_rx_driver_equalizer_lane0[16];
+u16 xgxs_rx_driver_equalizer_lane1[16];
+u16 xgxs_rx_driver_equalizer_lane2[16];
+u16 xgxs_rx_driver_equalizer_lane3[16];
+
+u32 lane_config;
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
+#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
+#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
+#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
+#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
+#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
+
+u32 external_phy_config;
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
+
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
+
+u32 speed_capability_mask;
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
+
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
+
+u32 reserved[2];
+
+};
+
+/****************************************************************************
+* Shared Feature configuration *
+****************************************************************************/
+struct shared_feat_cfg_t
+{
+u32 bmc_common;
+#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
+
+};
+
+
+/****************************************************************************
+* Port Feature configuration *
+****************************************************************************/
+struct port_feat_cfg_t
+{
+u32 config;
+#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
+#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
+#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
+#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
+#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
+#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
+#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
+#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
+#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
+#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
+#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
+#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
+#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
+#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
+#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
+#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
+#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
+#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
+#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
+#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
+#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
+#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
+#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
+#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
+#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
+#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
+#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
+#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
+#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
+#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
+#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
+#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
+#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
+#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
+#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
+#define PORT_FEATURE_EN_SIZE_SHIFT 24
+#define PORT_FEATURE_WOL_ENABLED 0x01000000
+#define PORT_FEATURE_MBA_ENABLED 0x02000000
+#define PORT_FEATURE_MFW_ENABLED 0x04000000
+
+u32 wol_config;
+
+#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
+#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
+#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
+#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
+#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
+#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
+#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
+
+u32 mba_config;
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
+#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
+#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
+#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
+#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
+#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
+#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
+#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
+#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
+#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
+
+u32 bmc_config;
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
+
+u32 mba_vlan_cfg;
+#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
+#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
+#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
+
+u32 resource_cfg;
+#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
+#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
+#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
+#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
+#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
+
+u32 smbus_config;
+#define PORT_FEATURE_SMBUS_EN 0x00000001
+#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
+#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
+
+u32 iscsib_boot_cfg;
+#define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT 0x00000001
+
+u32 link_config;
+#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
+#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
+#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
+#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
+#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
+#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
+
+#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
+#define PORT_FEATURE_LINK_SPEED_SHIFT 16
+#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
+#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
+#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
+#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
+#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
+#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
+#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
+#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
+#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
+#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
+#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
+#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
+#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
+#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
+#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
+
+#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
+#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
+#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
+#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
+#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
+#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
+#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
+
+
+u32 mfw_wol_link_cfg;
+
+u32 reserved[19];
+
+};
+
+
+/****************************************************************************
+* Device Information *
+****************************************************************************/
+struct dev_info_t
+{
+u32 bc_rev;
+
+struct shared_hw_cfg_t shared_hw_config;
+
+struct port_hw_cfg_t port_hw_config[FUNC_MAX];
+
+struct shared_feat_cfg_t shared_feature_config;
+
+struct port_feat_cfg_t port_feature_config[FUNC_MAX];
+
+};
+
+
+/****************************************************************************
+* Management firmware state *
+****************************************************************************/
+/* Allocate 320 bytes for management firmware: still not known exactly
+* how much IMD needs. */
+#define MGMTFW_STATE_WORD_SIZE 80
+
+struct mgmtfw_state_t
+{
+u32 opaque[MGMTFW_STATE_WORD_SIZE];
+
+};
+
+
+/****************************************************************************
+* Shared Memory Region *
+****************************************************************************/
+struct shmem_region_t
+{
+u32 validity_map[FUNC_MAX];
+#define SHR_MEM_VALIDITY_PCI_CFG 0x00000001
+#define SHR_MEM_VALIDITY_MB 0x00000002
+#define SHR_MEM_VALIDITY_DEV_INFO 0x00000004
+
+#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
+#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
+#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
+#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
+
+struct drv_fw_mb_t drv_fw_mb[FUNC_MAX];
+
+struct dev_info_t dev_info;
+
+#ifdef _LICENSE_H
+license_key_t drv_lic_key[FUNC_MAX];
+#else
+u8 reserved[64*FUNC_MAX];
+#endif
+
+
+u32 fw_info_fio_offset;
+struct mgmtfw_state_t mgmtfw_state;
+
+};
+
+
+#endif
+
+#ifndef __ETH_CONSTANTS_H_
+#define __ETH_CONSTANTS_H_
+
+/**
+* This file defines HSI constatnts for the ETH flow
+*/
+#ifdef _EVEREST_MICROCODE
+#include "microcode_constants.h"
+#include "eth_rx_bd.h"
+#include "eth_tx_bd.h"
+#include "eth_rx_cqe.h"
+#include "eth_rx_cqe_next_page.h"
+#endif
+
+
+#define DEFAULT_HASH_TYPE 0
+#define IPV4_HASH_TYPE 1
+#define TCP_IPV4_HASH_TYPE 2
+#define IPV6_HASH_TYPE 3
+#define TCP_IPV6_HASH_TYPE 4
+
+
+#define X_ETH_LOCAL_RING_SIZE 13
+#define FIRST_BD_IN_PKT 0
+#define PARSE_BD_INDEX 1
+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
+
+
+
+#define U_ETH_LOCAL_BD_RING_SIZE (8)
+
+#define U_ETH_BDS_PER_PAGE_MASK ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
+#define U_ETH_CQE_PER_PAGE_MASK ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
+#define TU_ETH_CQES_PER_PAGE
(PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+
+
+
+#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
+#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
+#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
+#define RAMROD_CMD_ID_ETH_UPDATE (100)
+#define RAMROD_CMD_ID_ETH_HALT (105)
+#define RAMROD_CMD_ID_ETH_SET_MAC (110)
+#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
+#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
+#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
+
+
+
+#define T_ETH_MAC_COMMAND_SET 0
+#define T_ETH_MAC_COMMAND_INVALIDATE 1
+
+#define T_ETH_INDIRECTION_TABLE_SIZE 128
+
+
+#define ETH_MAX_RX_CLIENTS (18)
+
+#endif
+
+#ifndef __MICROCODE_CONSTANTS_H_
+#define __MICROCODE_CONSTANTS_H_
+
+/**
+* This file defines HSI constatnts common to all microcode flows
+*/
+
+
+#define ETH_CONNECTION_TYPE 0
+#define TOE_CONNECTION_TYPE 1
+#define RDMA_CONNECTION_TYPE 2
+#define ISCSI_CONNECTION_TYPE 3
+#define RESERVED_CONNECTION_TYPE_0 4
+#define RESERVED_CONNECTION_TYPE_1 5
+#define RESERVED_CONNECTION_TYPE_2 6
+#define RESERVED_CONNECTION_TYPE_3 7
+#define NUM_OF_CONNECTION_TYPES 8
+
+
+
+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+
+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define ISCSI_STATE (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+
+#define MC_PAGE_SIZE (4096)
+
+
+
+
+
+#define IGU_PORT_BASE 0x0400
+
+#define IGU_ADDR_MSIX 0x0000
+#define IGU_ADDR_INT_ACK 0x0200
+#define IGU_ADDR_PROD_UPD 0x0201
+#define IGU_ADDR_ATTN_BITS_UPD 0x0202
+#define IGU_ADDR_ATTN_BITS_SET 0x0203
+#define IGU_ADDR_ATTN_BITS_CLR 0x0204
+#define IGU_ADDR_COALESCE_NOW 0x0205
+#define IGU_ADDR_SIMD_MASK 0x0206
+#define IGU_ADDR_SIMD_NOMASK 0x0207
+#define IGU_ADDR_MSI_CTL 0x0210
+#define IGU_ADDR_MSI_ADDR_LO 0x0211
+#define IGU_ADDR_MSI_ADDR_HI 0x0212
+#define IGU_ADDR_MSI_DATA 0x0213
+
+#define IGU_INT_ENABLE 0
+#define IGU_INT_DISABLE 1
+#define IGU_INT_NOP 2
+#define IGU_INT_NOP2 3
+
+
+#define HC_USTORM_DEF_SB_NUM_INDICES 4
+#define HC_CSTORM_DEF_SB_NUM_INDICES 8
+#define HC_XSTORM_DEF_SB_NUM_INDICES 4
+#define HC_TSTORM_DEF_SB_NUM_INDICES 4
+#define HC_USTORM_SB_NUM_INDICES 4
+#define HC_CSTORM_SB_NUM_INDICES 4
+
+
+
+
+#define HC_INDEX_U_TOE_RX_CQ_CONS 0
+#define HC_INDEX_U_ETH_RX_CQ_CONS 1
+
+
+#define HC_INDEX_C_TOE_TX_CQ_CONS 0
+#define HC_INDEX_C_ETH_TX_CQ_CONS 1
+#define HC_INDEX_C_ISCSI_EQ_CONS 2
+
+
+#define HC_INDEX_DEF_X_SPQ_CONS 0
+
+
+#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
+#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
+#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
+#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
+#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
+#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
+
+
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
+
+
+
+#define USTORM_ID 0
+#define CSTORM_ID 1
+#define XSTORM_ID 2
+#define TSTORM_ID 3
+#define ATTENTION_ID 4
+
+
+#define MAX_RAMRODS_PER_PORT (8)
+
+
+#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
+#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
+
+
+
+#define T_MAC_ADDRESS_LIST_SIZE (96)
+
+
+
+#define EMULATION_FREQUENCY_FACTOR (1600)
+#define FPGA_FREQUENCY_FACTOR (100)
+
+
+#define TIMERS_TICK_SIZE_CHIP 1e-3
+#define TIMERS_TICK_SIZE_EMUL \
+((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
+#define TIMERS_TICK_SIZE_FPGA \
+((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
+
+
+#define TSEMI_CLK1_RESUL_CHIP 1e-3
+#define TSEMI_CLK1_RESUL_EMUL \
+((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define TSEMI_CLK1_RESUL_FPGA \
+((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define USEMI_CLK1_RESUL_CHIP \
+(TIMERS_TICK_SIZE_CHIP)
+#define USEMI_CLK1_RESUL_EMUL \
+(TIMERS_TICK_SIZE_EMUL)
+#define USEMI_CLK1_RESUL_FPGA \
+(TIMERS_TICK_SIZE_FPGA)
+
+
+#define XSEMI_CLK1_RESUL_CHIP 1e-3
+#define XSEMI_CLK1_RESUL_EMUL \
+((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK1_RESUL_FPGA \
+((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define XSEMI_CLK2_RESUL_CHIP 1e-6
+#define XSEMI_CLK2_RESUL_EMUL \
+((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK2_RESUL_FPGA \
+((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
+#define SDM_TIMER_TICK_RESUL_EMUL \
+((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define SDM_TIMER_TICK_RESUL_FPGA \
+((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+
+#define XSTORM_IP_ID_ROLL_HALF 0x8000
+#define XSTORM_IP_ID_ROLL_ALL 0
+
+
+#define FW_LOG_LIST_SIZE (50)
+
+#define NUM_OF_PROTOCOLS 4
+#define MAX_COS_NUMBER 16
+#define MAX_T_STAT_COUNTER_ID 18
+
+
+#define T_FAIR 1
+#define FAIR_MEM 2
+#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
+
+#define UNKNOWN_ADDRESS 0
+#define UNICAST_ADDRESS 1
+#define MULTICAST_ADDRESS 2
+#define BROADCAST_ADDRESS 3
+
+#endif
+#ifndef __GENERAL_ATTEN_BITS_H
+#define __GENERAL_ATTEN_BITS_H
+
+
+
+#define RESERVED_GENERAL_ATTENTION_BIT_0 0
+
+
+#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
+
+#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
+
+
+#define RESERVED_GENERAL_ATTENTION_BIT_6 6
+#define RESERVED_GENERAL_ATTENTION_BIT_7 7
+#define RESERVED_GENERAL_ATTENTION_BIT_8 8
+#define RESERVED_GENERAL_ATTENTION_BIT_9 9
+#define RESERVED_GENERAL_ATTENTION_BIT_10 10
+#define RESERVED_GENERAL_ATTENTION_BIT_11 11
+#define RESERVED_GENERAL_ATTENTION_BIT_12 12
+#define RESERVED_GENERAL_ATTENTION_BIT_13 13
+#define RESERVED_GENERAL_ATTENTION_BIT_14 14
+#define RESERVED_GENERAL_ATTENTION_BIT_15 15
+#define RESERVED_GENERAL_ATTENTION_BIT_16 16
+#define RESERVED_GENERAL_ATTENTION_BIT_17 17
+#define RESERVED_GENERAL_ATTENTION_BIT_18 18
+#define RESERVED_GENERAL_ATTENTION_BIT_19 19
+#define RESERVED_GENERAL_ATTENTION_BIT_20 20
+#define RESERVED_GENERAL_ATTENTION_BIT_21 21
+
+
+#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
+#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
+#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
+#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
+
+
+#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
+
+
+#define LATCHED_ATTN_RBCR 23
+#define LATCHED_ATTN_RBCT 24
+#define LATCHED_ATTN_RBCN 25
+#define LATCHED_ATTN_RBCU 26
+#define LATCHED_ATTN_RBCP 27
+#define LATCHED_ATTN_TIMEOUT_GRC 28
+#define LATCHED_ATTN_RSVD_GRC 29
+#define LATCHED_ATTN_ROM_PARITY_MCP 30
+#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
+#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
+#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
+
+
+#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
+#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32 ))
+
+#endif
+#ifndef _GRC_ADDR_H
+#define _GRC_ADRR_H
+/*
+* This file defines GRC base address for every block.
+* This file is included by chipsim, asm microcode and cpp microcode.
+* These values are used in Design.xml on regBase attribute
+* Use the base with the generated offsets of specific registers.
+*/
+
+#define GRCBASE_PXPCS 0x000000
+#define GRCBASE_PCICONFIG 0x002000
+#define GRCBASE_PCIREG 0x002400
+#define GRCBASE_EMAC0 0x008000
+#define GRCBASE_EMAC1 0x008400
+#define GRCBASE_DBU 0x008800
+#define GRCBASE_MISC 0x00A000
+#define GRCBASE_DBG 0x00C000
+#define GRCBASE_NIG 0x010000
+#define GRCBASE_XCM 0x020000
+#define GRCBASE_PRS 0x040000
+#define GRCBASE_SRCH 0x040400
+#define GRCBASE_TSDM 0x042000
+#define GRCBASE_TCM 0x050000
+#define GRCBASE_BRB1 0x060000
+#define GRCBASE_MCP 0x080000
+#define GRCBASE_UPB 0x0C1000
+#define GRCBASE_CSDM 0x0C2000
+#define GRCBASE_USDM 0x0C4000
+#define GRCBASE_CCM 0x0D0000
+#define GRCBASE_UCM 0x0E0000
+#define GRCBASE_CDU 0x101000
+#define GRCBASE_DMAE 0x102000
+#define GRCBASE_PXP 0x103000
+#define GRCBASE_CFC 0x104000
+#define GRCBASE_HC 0x108000
+#define GRCBASE_PXP2 0x120000
+#define GRCBASE_PBF 0x140000
+#define GRCBASE_XPB 0x161000
+#define GRCBASE_TIMERS 0x164000
+#define GRCBASE_XSDM 0x166000
+#define GRCBASE_QM 0x168000
+#define GRCBASE_DQ 0x170000
+#define GRCBASE_TSEM 0x180000
+#define GRCBASE_CSEM 0x200000
+#define GRCBASE_XSEM 0x280000
+#define GRCBASE_USEM 0x300000
+#define GRCBASE_MISC_AEU GRCBASE_MISC
+
+#endif
+
+
+#define PCICFG_OFFSET 0x2000
+#define PCICFG_VENDOR_ID_OFFSET 0x00
+#define PCICFG_DEVICE_ID_OFFSET 0x02
+#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
+#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
+#define PCICFG_INT_LINE 0x3c
+#define PCICFG_INT_PIN 0x3d
+#define PCICFG_CACHE_LINE_SIZE 0x0c
+#define PCICFG_LATENCY_TIMER 0x0d
+#define PCICFG_REVESION_ID 0x08
+#define PCICFG_BAR_1_LOW 0x10
+#define PCICFG_BAR_1_HIGH 0x14
+#define PCICFG_BAR_2_LOW 0x18
+#define PCICFG_BAR_2_HIGH 0x1c
+#define PCICFG_GRC_ADDRESS 0x78
+#define PCICFG_GRC_DATA 0x80
+#define PCICFG_DEVICE_CONTROL 0xb4
+#define PCICFG_LINK_CONTROL 0xbc
+
+#define BAR_USTRORM_INTMEM 0x400000
+#define BAR_CSTRORM_INTMEM 0x410000
+#define BAR_XSTRORM_INTMEM 0x420000
+#define BAR_TSTRORM_INTMEM 0x430000
+
+
+#define BAR_IGU_INTMEM 0x440000
+
+#define BAR_DOORBELL_OFFSET 0x800000
+
+#define BAR_ME_REGISTER 0x450000
+
+
+#define GRC_CONFIG_2_SIZE_REG 0x408
+#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
+#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
+#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
+#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
+#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
+#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
+#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
+#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
+
+#define GRC_CONFIG_3_SIZE_REG (0x40c)
+#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
+#define PCI_CONFIG_3_FORCE_PME (1L<<24)
+#define PCI_CONFIG_3_PME_STATUS (1L<<25)
+#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
+#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
+#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
+#define PCI_CONFIG_3_PCI_POWER (1L<<31)
+
+#define GRC_CONFIG_2_SIZE_REG 0x408
+
+#define GRC_BAR2_CONFIG 0x4e0
+#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
+#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
+
+#define PCI_PM_DATA_A (0x410)
+#define PCI_PM_DATA_B (0x414)
+#define PCI_ID_VAL1 (0x434)
+#define PCI_ID_VAL2 (0x438)
+/****************************************************************************
+* Copyright(c) 2001-2006 Broadcom Corporation, all rights reserved
+* Proprietary and Confidential Information.
+*
+* This source file is the property of Broadcom Corporation, and
+* may not be copied or distributed in any isomorphic form without
+* the prior written consent of Broadcom Corporation.
+*
+* Name: phy_reg.h
+*
+* Description: This file contains partial list of the PHY registers.
+* It was manually created according to the excel data sheet
+* of the UNICORE (XGXS and SerDes). Only relevant registers
+* were added.
+* It is recommended to replace this file with automatically
+* generated version of the UNICORE registers
+*
+* Created: 01/14/2007 eilong
+*
+* $Date: 2007/07/23 $ $Revision: #14 $
+****************************************************************************/
+#ifndef PHY_REG_H
+#define PHY_REG_H
+
+#define MDIO_REG_BANK_CL73_IEEEB0 0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
+
+#define MDIO_REG_BANK_CL73_IEEEB1 0x10
+#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
+
+#define MDIO_REG_BANK_RX0 0x80b0
+#define MDIO_RX0_RX_EQ_BOOST 0x1c
+#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX1 0x80c0
+#define MDIO_RX1_RX_EQ_BOOST 0x1c
+#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX2 0x80d0
+#define MDIO_RX2_RX_EQ_BOOST 0x1c
+#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX3 0x80e0
+#define MDIO_RX3_RX_EQ_BOOST 0x1c
+#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX_ALL 0x80f0
+#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
+#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_TX0 0x8060
+#define MDIO_TX0_TX_DRIVER 0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+
+#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
+#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
+
+#define MDIO_REG_BANK_GP_STATUS 0x8120
+#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
+
+
+
+
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
+
+
+#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
+
+#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1 0x18
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
+
+#define MDIO_REG_BANK_OVER_1G 0x8320
+#define MDIO_OVER_1G_DIGCTL_3_4 0x14
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
+#define MDIO_OVER_1G_UP1 0x19
+#define MDIO_OVER_1G_UP1_2_5G 0x0001
+#define MDIO_OVER_1G_UP1_5G 0x0002
+#define MDIO_OVER_1G_UP1_6G 0x0004
+#define MDIO_OVER_1G_UP1_10G 0x0010
+#define MDIO_OVER_1G_UP1_10GH 0x0008
+
+
+#define MDIO_OVER_1G_UP1_12G 0x0020
+#define MDIO_OVER_1G_UP1_12_5G 0x0040
+#define MDIO_OVER_1G_UP1_13G 0x0080
+#define MDIO_OVER_1G_UP1_15G 0x0100
+#define MDIO_OVER_1G_UP1_16G 0x0200
+#define MDIO_OVER_1G_UP2 0x1A
+#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
+#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
+#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
+#define MDIO_OVER_1G_UP3 0x1B
+#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
+#define MDIO_OVER_1G_LP_UP1 0x1C
+#define MDIO_OVER_1G_LP_UP2 0x1D
+#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
+#define MDIO_OVER_1G_LP_UP3 0x1E
+
+#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
+
+#define MDIO_REG_BANK_CL73_USERB0 0x8370
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
+
+#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
+#define MDIO_AER_BLOCK_AER_REG 0x1E
+
+#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
+#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
+#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
+#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
+#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
+#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
+#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
+#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_SYMMETRIC
0x0080
+#define
MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_ASYMMETRIC 0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
+
+
+
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
+
+
+
+#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
+#define EXT_PHY_OPT_WIS_DEVAD 0x2
+#define EXT_PHY_OPT_PCS_DEVAD 0x3
+#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
+#define EXT_PHY_OPT_CNTL 0x0
+#define EXT_PHY_OPT_PMD_RX_SD 0xa
+#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
+#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
+#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
+#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
+#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
+#define EXT_PHY_OPT_LASI_CNTL 0x9002
+#define EXT_PHY_OPT_RX_ALARM 0x9003
+#define EXT_PHY_OPT_LASI_STATUS 0x9005
+#define EXT_PHY_OPT_PCS_STATUS 0x0020
+#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
+
+#endif
+#ifndef __5710_HSI_L2_LE__
+#define __5710_HSI_L2_LE__
+#pragma pack(push, 1)
+/*
+* attention bits
+*/
+struct atten_def_status_block {
+u32 attn_bits;
+u32 attn_bits_ack;
+#if defined(__BIG_ENDIAN)
+u16 attn_bits_index;
+u8 reserved0;
+u8 status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 attn_bits_index;
+#endif
+u32 reserved1;
+};
+
+
+/*
+* common data for all protocols
+*/
+struct doorbell_hdr {
+u8 header;
+#define DOORBELL_HDR_RX (0x1<<0)
+#define DOORBELL_HDR_RX_SHIFT 0
+#define DOORBELL_HDR_DB_TYPE (0x1<<1)
+#define DOORBELL_HDR_DB_TYPE_SHIFT 1
+#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
+#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
+#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
+#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
+};
+
+/*
+* doorbell message send to the chip
+*/
+struct doorbell {
+#if defined(__BIG_ENDIAN)
+u16 zero_fill2;
+u8 zero_fill1;
+struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+struct doorbell_hdr header;
+u8 zero_fill1;
+u16 zero_fill2;
+#endif
+};
+
+
+
+/*
+* IGU driver acknowlegement register
+*/
+struct igu_ack_register {
+#if defined(__BIG_ENDIAN)
+u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+#endif
+};
+
+
+/*
+* Parser parsing flags field
+*/
+struct parsing_flags {
+u16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
+#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
+#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
+#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
+#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
+#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
+#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
+#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
+#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
+#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
+#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
+#define PARSING_FLAGS_RESERVED0 (0x3<<14)
+#define PARSING_FLAGS_RESERVED0_SHIFT 14
+};
+
+
+/*
+* dmae command structure
+*/
+struct dmae_command {
+u32 opcode;
+#define DMAE_COMMAND_SRC (0x1<<0)
+#define DMAE_COMMAND_SRC_SHIFT 0
+#define DMAE_COMMAND_DST (0x3<<1)
+#define DMAE_COMMAND_DST_SHIFT 1
+#define DMAE_COMMAND_C_DST (0x1<<3)
+#define DMAE_COMMAND_C_DST_SHIFT 3
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
+#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
+#define DMAE_COMMAND_ENDIANITY (0x3<<9)
+#define DMAE_COMMAND_ENDIANITY_SHIFT 9
+#define DMAE_COMMAND_PORT (0x1<<11)
+#define DMAE_COMMAND_PORT_SHIFT 11
+#define DMAE_COMMAND_CRC_RESET (0x1<<12)
+#define DMAE_COMMAND_CRC_RESET_SHIFT 12
+#define DMAE_COMMAND_SRC_RESET (0x1<<13)
+#define DMAE_COMMAND_SRC_RESET_SHIFT 13
+#define DMAE_COMMAND_DST_RESET (0x1<<14)
+#define DMAE_COMMAND_DST_RESET_SHIFT 14
+#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15)
+#define DMAE_COMMAND_RESERVED0_SHIFT 15
+u32 src_addr_lo;
+u32 src_addr_hi;
+u32 dst_addr_lo;
+u32 dst_addr_hi;
+#if defined(__BIG_ENDIAN)
+u16 reserved1;
+u16 len;
+#elif defined(__LITTLE_ENDIAN)
+u16 len;
+u16 reserved1;
+#endif
+u32 comp_addr_lo;
+u32 comp_addr_hi;
+u32 comp_val;
+u32 crc32;
+u32 crc32_c;
+#if defined(__BIG_ENDIAN)
+u16 crc16_c;
+u16 crc16;
+#elif defined(__LITTLE_ENDIAN)
+u16 crc16;
+u16 crc16_c;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 reserved2;
+u16 crc_t10;
+#elif defined(__LITTLE_ENDIAN)
+u16 crc_t10;
+u16 reserved2;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 xsum8;
+u16 xsum16;
+#elif defined(__LITTLE_ENDIAN)
+u16 xsum16;
+u16 xsum8;
+#endif
+};
+
+
+struct double_regpair {
+u32 regpair0_lo;
+u32 regpair0_hi;
+u32 regpair1_lo;
+u32 regpair1_hi;
+};
+
+
+/*
+* The eth Rx Buffer Descriptor
+*/
+struct eth_rx_bd {
+u32 addr_lo;
+u32 addr_hi;
+u32 len;
+u32 reserved;
+};
+
+/*
+* The eth storm context of Ustorm
+*/
+struct ustorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+u8 sb_index_number;
+u8 status_block_id;
+u8 __local_rx_bd_cons;
+u8 __local_rx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+u8 __local_rx_bd_prod;
+u8 __local_rx_bd_cons;
+u8 status_block_id;
+u8 sb_index_number;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 rcq_cons;
+u16 rx_bd_cons;
+#elif defined(__LITTLE_ENDIAN)
+u16 rx_bd_cons;
+u16 rcq_cons;
+#endif
+u32 rx_bd_page_base_lo;
+u32 rx_bd_page_base_hi;
+u32 rcq_base_address_lo;
+u32 rcq_base_address_hi;
+#if defined(__BIG_ENDIAN)
+u8 __reserved1;
+u8 __current_dynamic_hc_timeout;
+u16 flags;
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x3FFF<<2)
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+u16 flags;
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x3FFF<<2)
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 2
+u8 __current_dynamic_hc_timeout;
+u8 __reserved1;
+#endif
+u32 mc_alignment_size;
+struct eth_rx_bd __local_bd_ring[8];
+};
+
+/*
+* The eth storm context of Tstorm
+*/
+struct tstorm_eth_st_context {
+u32 __reserved0[28];
+};
+
+/*
+* The eth aggregative context section of Xstorm
+*/
+struct xstorm_eth_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars1;
+u8 __reserved50;
+u16 __mss;
+#elif defined(__LITTLE_ENDIAN)
+u16 __mss;
+u8 __reserved50;
+u8 __tcp_agg_vars1;
+#endif
+u32 __snd_nxt;
+u32 __tx_wnd;
+u32 __snd_una;
+u32 __reserved53;
+#if defined(__BIG_ENDIAN)
+u8 __agg_val8_th;
+u8 __agg_val8;
+u16 __tcp_agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __tcp_agg_vars2;
+u8 __agg_val8;
+u8 __agg_val8_th;
+#endif
+u32 __reserved58;
+u32 __reserved59;
+u32 __reserved60;
+u32 __reserved61;
+#if defined(__BIG_ENDIAN)
+u16 __agg_val7_th;
+u16 __agg_val7;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val7;
+u16 __agg_val7_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars4;
+u16 __tcp_agg_vars3;
+u8 __reserved62;
+#elif defined(__LITTLE_ENDIAN)
+u8 __reserved62;
+u16 __tcp_agg_vars3;
+u8 __tcp_agg_vars4;
+#endif
+u32 __tcp_agg_vars5;
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc6;
+u16 __tcp_agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+u16 __tcp_agg_vars6;
+u16 __agg_misc6;
+#endif
+u32 __agg_val10;
+u32 __agg_val10_th;
+#if defined(__BIG_ENDIAN)
+u16 __reserved3;
+u8 __reserved2;
+u8 __agg_misc7;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_misc7;
+u8 __reserved2;
+u16 __reserved3;
+#endif
+};
+
+/*
+* The eth aggregative context of Xstorm
+*/
+struct xstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u16 __bd_prod;
+u8 __agg_vars1;
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u8 __agg_vars1;
+u16 __bd_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 cdu_reserved;
+u16 __agg_vars3;
+u8 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_vars2;
+u16 __agg_vars3;
+u8 cdu_reserved;
+#endif
+u32 __more_packets_to_send;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars4;
+u16 __agg_val4_th;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val4_th;
+u16 __agg_vars4;
+#endif
+struct xstorm_eth_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars7;
+u8 __agg_val3_th;
+u8 __agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_vars6;
+u8 __agg_val3_th;
+u16 __agg_vars7;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val11_th;
+u16 __agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val11;
+u16 __agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __reserved1;
+u8 __agg_val6_th;
+u16 __agg_val9;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val9;
+u8 __agg_val6_th;
+u8 __reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val2_th;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u16 __agg_val2_th;
+#endif
+u32 __agg_vars5;
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc0;
+u16 __agg_val4;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val4;
+u16 __agg_misc0;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __agg_val3;
+u8 __agg_val6;
+u8 __agg_val5_th;
+u8 __agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_val5;
+u8 __agg_val5_th;
+u8 __agg_val6;
+u8 __agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc1;
+u16 __bd_ind_max_val;
+#elif defined(__LITTLE_ENDIAN)
+u16 __bd_ind_max_val;
+u16 __agg_misc1;
+#endif
+u32 __reserved57;
+u32 __agg_misc4;
+u32 __agg_misc5;
+};
+
+/*
+* The eth aggregative context section of Tstorm
+*/
+struct tstorm_eth_extra_ag_context_section {
+u32 __agg_val1;
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars2;
+u8 __agg_val3;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u8 __agg_val3;
+u8 __tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val5;
+u8 __agg_val6;
+u8 __tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+u8 __tcp_agg_vars3;
+u8 __agg_val6;
+u16 __agg_val5;
+#endif
+u32 __reserved63;
+u32 __reserved64;
+u32 __reserved65;
+u32 __reserved66;
+u32 __reserved67;
+u32 __tcp_agg_vars1;
+u32 __reserved61;
+u32 __reserved62;
+u32 __reserved2;
+};
+
+/*
+* The eth aggregative context of Tstorm
+*/
+struct tstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u16 __reserved54;
+u8 agg_vars1;
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50 (0x1<<0)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50_SHIFT 0
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51 (0x1<<1)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51_SHIFT 1
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52 (0x1<<2)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52_SHIFT 2
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53 (0x1<<3)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53_SHIFT 3
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF (0x3<<4)
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF_SHIFT 4
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u8 agg_vars1;
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50 (0x1<<0)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50_SHIFT 0
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51 (0x1<<1)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51_SHIFT 1
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52 (0x1<<2)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52_SHIFT 2
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53 (0x1<<3)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53_SHIFT 3
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF (0x3<<4)
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF_SHIFT 4
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+u16 __reserved54;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val4;
+u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_vars2;
+u16 __agg_val4;
+#endif
+struct tstorm_eth_extra_ag_context_section __extra_section;
+};
+
+/*
+* The eth aggregative context of Cstorm
+*/
+struct cstorm_eth_ag_context {
+u32 __agg_vars1;
+#if defined(__BIG_ENDIAN)
+u8 __aux1_th;
+u8 __aux1_val;
+u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_vars2;
+u8 __aux1_val;
+u8 __aux1_th;
+#endif
+u32 __num_of_treated_packet;
+u32 __last_packet_treated;
+#if defined(__BIG_ENDIAN)
+u16 __reserved58;
+u16 __reserved57;
+#elif defined(__LITTLE_ENDIAN)
+u16 __reserved57;
+u16 __reserved58;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __reserved62;
+u8 __reserved61;
+u8 __reserved60;
+u8 __reserved59;
+#elif defined(__LITTLE_ENDIAN)
+u8 __reserved59;
+u8 __reserved60;
+u8 __reserved61;
+u8 __reserved62;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __reserved64;
+u16 __reserved63;
+#elif defined(__LITTLE_ENDIAN)
+u16 __reserved63;
+u16 __reserved64;
+#endif
+u32 __reserved65;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars3;
+u16 __rq_inv_cnt;
+#elif defined(__LITTLE_ENDIAN)
+u16 __rq_inv_cnt;
+u16 __agg_vars3;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __packet_index_th;
+u16 __packet_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 __packet_index;
+u16 __packet_index_th;
+#endif
+};
+
+/*
+* The eth aggregative context of Ustorm
+*/
+struct ustorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u8 __aux_counter_flags;
+u16 __agg_vars;
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u16 __agg_vars;
+u8 __aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 cdu_usage;
+u8 __agg_misc2;
+u16 __agg_misc1;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_misc1;
+u8 __agg_misc2;
+u8 cdu_usage;
+#endif
+u32 __agg_misc4;
+#if defined(__BIG_ENDIAN)
+u8 __agg_val3_th;
+u8 __agg_val3;
+u16 __agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_misc3;
+u8 __agg_val3;
+u8 __agg_val3_th;
+#endif
+u32 __agg_val1;
+u32 __agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+u16 __agg_val2_th;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u16 __agg_val2_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __reserved2;
+u8 __decision_rules;
+u8 __decision_rule_enable_bits;
+#elif defined(__LITTLE_ENDIAN)
+u8 __decision_rule_enable_bits;
+u8 __decision_rules;
+u16 __reserved2;
+#endif
+};
+
+/*
+* Timers connection context
+*/
+struct timers_block_context {
+u32 __reserved_0;
+u32 __reserved_1;
+u32 __reserved_2;
+u32 reserved_flags;
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_0 (0x3<<0)
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_0_SHIFT 0
+#define TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_1 (0x1<<2)
+#define TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_1_SHIFT 2
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_2 (0x1FFFFFFF<<3)
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_2_SHIFT 3
+};
+
+/*
+* structure for easy accessability to assembler
+*/
+struct eth_tx_bd_flags {
+u8 as_bitfield;
+#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
+#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
+#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
+#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
+#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
+#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
+#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
+#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
+#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
+#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
+#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
+#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
+#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
+#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
+};
+
+/*
+* The eth Tx Buffer Descriptor
+*/
+struct eth_tx_bd {
+u32 addr_lo;
+u32 addr_hi;
+#if defined(__BIG_ENDIAN)
+u16 nbytes;
+u16 nbd;
+#elif defined(__LITTLE_ENDIAN)
+u16 nbd;
+u16 nbytes;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 general_data;
+#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
+struct eth_tx_bd_flags bd_flags;
+u16 vlan;
+#elif defined(__LITTLE_ENDIAN)
+u16 vlan;
+struct eth_tx_bd_flags bd_flags;
+u8 general_data;
+#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
+#endif
+};
+
+/*
+* Tx parsing BD structure for ETH, Relevant in START
+*/
+struct eth_tx_parse_bd {
+#if defined(__BIG_ENDIAN)
+u16 total_hlen;
+u8 ip_hlen;
+s8 cs_offset;
+u8 tcp_flags;
+#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
+#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
+#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
+#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
+#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
+#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
+#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
+u8 global_data;
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
+#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
+#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+u8 global_data;
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
+#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
+#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
+u8 tcp_flags;
+#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
+#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
+#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
+#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
+#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
+#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
+#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
+u8 ip_hlen;
+s8 cs_offset;
+u16 total_hlen;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 tcp_pseudo_csum;
+u16 lso_mss;
+#elif defined(__LITTLE_ENDIAN)
+u16 lso_mss;
+u16 tcp_pseudo_csum;
+#endif
+#if defined(__BIG_ENDIAN)
+u32 tcp_send_seq;
+u16 ip_id;
+#elif defined(__LITTLE_ENDIAN)
+u16 ip_id;
+u32 tcp_send_seq;
+#endif
+};
+
+/*
+* The last BD in the BD memory will hold a pointer to the next BD memory
+*/
+struct eth_tx_next_bd {
+u32 addr_lo;
+u32 addr_hi;
+u8 reserved[8];
+};
+
+/*
+* union for 3 Bd types
+*/
+union eth_tx_bd_types {
+struct eth_tx_bd reg_bd;
+struct eth_tx_parse_bd parse_bd;
+struct eth_tx_next_bd next_bd;
+};
+
+/*
+* The eth storm context of Xstorm
+*/
+struct xstorm_eth_st_context {
+u32 tx_bd_page_base_lo;
+u32 tx_bd_page_base_hi;
+#if defined(__BIG_ENDIAN)
+u16 tx_bd_cons;
+u8 __reserved0;
+u8 __local_tx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+u8 __local_tx_bd_prod;
+u8 __reserved0;
+u16 tx_bd_cons;
+#endif
+u32 db_data_addr_lo;
+u32 db_data_addr_hi;
+u32 __pkt_cons;
+u32 __gso_next;
+u32 is_eth_conn_1b;
+union eth_tx_bd_types __bds[13];
+};
+
+/*
+* The eth storm context of Cstorm
+*/
+struct cstorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+u16 __reserved0;
+u8 sb_index_number;
+u8 status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+u8 status_block_id;
+u8 sb_index_number;
+u16 __reserved0;
+#endif
+u32 __reserved1[3];
+};
+
+/*
+* Ethernet connection context
+*/
+struct eth_context {
+struct ustorm_eth_st_context ustorm_st_context;
+struct tstorm_eth_st_context tstorm_st_context;
+struct xstorm_eth_ag_context xstorm_ag_context;
+struct tstorm_eth_ag_context tstorm_ag_context;
+struct cstorm_eth_ag_context cstorm_ag_context;
+struct ustorm_eth_ag_context ustorm_ag_context;
+struct timers_block_context timers_context;
+struct xstorm_eth_st_context xstorm_st_context;
+struct cstorm_eth_st_context cstorm_st_context;
+};
+
+
+/*
+* ethernet doorbell
+*/
+struct eth_tx_doorbell {
+#if defined(__BIG_ENDIAN)
+u16 npackets;
+u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+struct doorbell_hdr hdr;
+#elif defined(__LITTLE_ENDIAN)
+struct doorbell_hdr hdr;
+u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+u16 npackets;
+#endif
+};
+
+
+/*
+* ustorm status block
+*/
+struct ustorm_def_status_block {
+u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* cstorm status block
+*/
+struct cstorm_def_status_block {
+u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* xstorm status block
+*/
+struct xstorm_def_status_block {
+u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* tstorm status block
+*/
+struct tstorm_def_status_block {
+u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* host status block
+*/
+struct host_def_status_block {
+struct atten_def_status_block atten_status_block;
+struct ustorm_def_status_block u_def_status_block;
+struct cstorm_def_status_block c_def_status_block;
+struct xstorm_def_status_block x_def_status_block;
+struct tstorm_def_status_block t_def_status_block;
+};
+
+
+/*
+* ustorm status block
+*/
+struct ustorm_status_block {
+u16 index_values[HC_USTORM_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* cstorm status block
+*/
+struct cstorm_status_block {
+u16 index_values[HC_CSTORM_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* host status block
+*/
+struct host_status_block {
+struct ustorm_status_block u_status_block;
+struct cstorm_status_block c_status_block;
+};
+
+
+
+
+/*
+* The data for RSS setup ramrod
+*/
+struct eth_client_setup_ramrod_data {
+u32 client_id_5b;
+#if defined(__BIG_ENDIAN)
+u16 reserved1;
+u8 reserved0;
+u8 is_rdma_1b;
+#elif defined(__LITTLE_ENDIAN)
+u8 is_rdma_1b;
+u8 reserved0;
+u16 reserved1;
+#endif
+};
+
+
+/*
+* L2 dynamic host coalescing init parameters
+*/
+struct eth_dynamic_hc_config {
+u32 threshold[3];
+u8 hc_timeout[4];
+};
+
+
+/*
+* regular eth FP CQE parameters struct
+*/
+struct eth_fast_path_rx_cqe {
+#if defined(__BIG_ENDIAN)
+u8 placement_offset;
+u8 status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+u8 error_flags;
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1F<<3)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 3
+u8 type;
+#elif defined(__LITTLE_ENDIAN)
+u8 type;
+u8 error_flags;
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1F<<3)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 3
+u8 status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+u8 placement_offset;
+#endif
+u32 rss_hash_result;
+#if defined(__BIG_ENDIAN)
+u16 pkt_len;
+u16 vlan_tag;
+#elif defined(__LITTLE_ENDIAN)
+u16 vlan_tag;
+u16 pkt_len;
+#endif
+#if defined(__BIG_ENDIAN)
+struct parsing_flags pars_flags;
+u16 l4_csum;
+#elif defined(__LITTLE_ENDIAN)
+u16 l4_csum;
+struct parsing_flags pars_flags;
+#endif
+};
+
+
+/*
+* The data for RSS setup ramrod
+*/
+struct eth_halt_ramrod_data {
+u32 client_id_5b;
+u32 reserved0;
+};
+
+
+/*
+* Place holder for ramrods protocol specific data
+*/
+struct ramrod_data {
+u32 data_lo;
+u32 data_hi;
+};
+
+/*
+* union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
+*/
+union eth_ramrod_data {
+struct ramrod_data general;
+};
+
+
+
+/*
+* Eth Rx Cqe structure- general structure for ramrods
+*/
+struct common_ramrod_eth_rx_cqe {
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u8 conn_type_3b;
+u8 type;
+#elif defined(__LITTLE_ENDIAN)
+u8 type;
+u8 conn_type_3b;
+u16 reserved;
+#endif
+u32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
+#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
+struct ramrod_data protocol_data;
+};
+
+/*
+* Rx Last CQE in page (in ETH)
+*/
+struct eth_rx_cqe_next_page {
+u32 addr_lo;
+u32 addr_hi;
+u32 reserved0;
+u32 reserved1;
+};
+
+/*
+* union for all eth rx cqe types (fix their sizes)
+*/
+union eth_rx_cqe {
+struct eth_fast_path_rx_cqe fast_path_cqe;
+struct common_ramrod_eth_rx_cqe ramrod_cqe;
+struct eth_rx_cqe_next_page next_page_cqe;
+};
+
+
+
+/*
+* common data for all protocols
+*/
+struct spe_hdr {
+u32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF<<0)
+#define SPE_HDR_CID_SHIFT 0
+#define SPE_HDR_CMD_ID (0xFF<<24)
+#define SPE_HDR_CMD_ID_SHIFT 24
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
+#define SPE_HDR_COMMON_RAMROD_SHIFT 8
+#elif defined(__LITTLE_ENDIAN)
+u16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
+#define SPE_HDR_COMMON_RAMROD_SHIFT 8
+u16 reserved;
+#endif
+};
+
+struct regpair {
+u32 lo;
+u32 hi;
+};
+
+/*
+* ethernet slow path element
+*/
+union eth_specific_data {
+u8 protocol_data[8];
+struct regpair mac_config_addr;
+struct eth_client_setup_ramrod_data client_setup_ramrod_data;
+struct eth_halt_ramrod_data halt_ramrod_data;
+struct regpair leading_cqe_addr;
+struct regpair update_data_addr;
+};
+
+/*
+* ethernet slow path element
+*/
+struct eth_spe {
+struct spe_hdr hdr;
+union eth_specific_data data;
+};
+
+
+
+
+
+
+/*
+* doorbell data in host memory
+*/
+struct eth_tx_db_data {
+u32 packets_prod;
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u16 bds_prod;
+#elif defined(__LITTLE_ENDIAN)
+u16 bds_prod;
+u16 reserved;
+#endif
+};
+
+
+
+
+/*
+* Common configuration parameters per port in Tstorm
+*/
+struct tstorm_eth_port_common_config {
+#if defined(__BIG_ENDIAN)
+u8 reserved;
+u8 leading_client_id;
+u8 rss_result_mask;
+u8 config_flags;
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0 (0x3<<6)
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0_SHIFT 6
+#elif defined(__LITTLE_ENDIAN)
+u8 config_flags;
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0 (0x3<<6)
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0_SHIFT 6
+u8 rss_result_mask;
+u8 leading_client_id;
+u8 reserved;
+#endif
+};
+
+/*
+* parameters for eth update ramrod
+*/
+struct eth_update_ramrod_data {
+struct tstorm_eth_port_common_config port_config;
+u8 indirectionTable[128];
+u32 reserved0;
+};
+
+
+/*
+* MAC filtering configuration command header
+*/
+struct mac_configuration_hdr {
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 offset;
+u8 length_6b;
+#elif defined(__LITTLE_ENDIAN)
+u8 length_6b;
+u8 offset;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+/*
+* MAC address in list for ramrod
+*/
+struct tstorm_cam_entry {
+#if defined(__BIG_ENDIAN)
+u16 middle_mac_addr;
+u16 lsb_mac_addr;
+#elif defined(__LITTLE_ENDIAN)
+u16 lsb_mac_addr;
+u16 middle_mac_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 flags;
+#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
+#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
+#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
+#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
+#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
+#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
+u16 msb_mac_addr;
+#elif defined(__LITTLE_ENDIAN)
+u16 msb_mac_addr;
+u16 flags;
+#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
+#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
+#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
+#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
+#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
+#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
+#endif
+};
+
+/*
+* MAC filtering: CAM target table entry
+*/
+struct tstorm_cam_target_table_entry {
+#if defined(__BIG_ENDIAN)
+u16 vlan_id;
+u8 client_id;
+u8 flags;
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
+#elif defined(__LITTLE_ENDIAN)
+u8 flags;
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
+u8 client_id;
+u16 vlan_id;
+#endif
+};
+
+/*
+* MAC address in list for ramrod
+*/
+struct mac_configuration_entry {
+struct tstorm_cam_entry cam_entry;
+struct tstorm_cam_target_table_entry target_table_entry;
+};
+
+/*
+* MAC filtering configuration command
+*/
+struct mac_configuration_cmd {
+struct mac_configuration_hdr hdr;
+struct mac_configuration_entry config_table[64];
+};
+
+
+
+
+/*
+* Configuration parameters per client in Tstorm
+*/
+struct tstorm_eth_client_config {
+#if defined(__BIG_ENDIAN)
+u16 statistics_counter_id;
+u16 max_buffer_size;
+#elif defined(__LITTLE_ENDIAN)
+u16 max_buffer_size;
+u16 statistics_counter_id;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
+u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
+u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
+#endif
+};
+
+
+/*
+* MAC filtering configuration parameters per port in Tstorm
+*/
+struct tstorm_eth_mac_filter_config {
+u32 ucast_drop_all;
+u32 ucast_accept_all;
+u32 mcast_drop_all;
+u32 mcast_accept_all;
+u32 bcast_drop_all;
+u32 bcast_accept_all;
+u32 strict_vlan;
+};
+
+
+
+
+
+
+struct rate_shaping_per_protocol {
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u16 protocol_rate;
+#elif defined(__LITTLE_ENDIAN)
+u16 protocol_rate;
+u16 reserved0;
+#endif
+u32 protocol_quota;
+s32 current_credit;
+u32 reserved;
+};
+
+struct rate_shaping_vars {
+struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
+u32 pause_mask;
+u32 periodic_stop;
+u32 rs_periodic_timeout;
+u32 rs_threshold;
+u32 last_periodic_time;
+u32 reserved;
+};
+
+struct fairness_per_protocol {
+u32 credit_delta;
+s32 fair_credit;
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 state;
+u8 weight;
+#elif defined(__LITTLE_ENDIAN)
+u8 weight;
+u8 state;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+struct fairness_vars {
+struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
+u32 upper_bound;
+u32 port_rate;
+u32 pause_mask;
+u32 fair_threshold;
+};
+
+struct safc_struct {
+u32 cur_pause_mask;
+u32 expire_time;
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 cur_cos_types;
+u8 safc_timeout_usec;
+#elif defined(__LITTLE_ENDIAN)
+u8 safc_timeout_usec;
+u8 cur_cos_types;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+struct demo_struct {
+u8 con_number[NUM_OF_PROTOCOLS];
+#if defined(__BIG_ENDIAN)
+u8 reserved1;
+u8 fairness_enable;
+u8 rate_shaping_enable;
+u8 cmng_enable;
+#elif defined(__LITTLE_ENDIAN)
+u8 cmng_enable;
+u8 rate_shaping_enable;
+u8 fairness_enable;
+u8 reserved1;
+#endif
+};
+
+struct cmng_struct {
+struct rate_shaping_vars rs_vars;
+struct fairness_vars fair_vars;
+struct safc_struct safc_vars;
+struct demo_struct demo_vars;
+};
+
+
+
+struct cos_to_protocol {
+u8 mask[MAX_COS_NUMBER];
+};
+
+
+
+
+
+
+/*
+* Common statistics collected by the Xstorm (per port)
+*/
+struct xstorm_common_stats {
+struct regpair total_sent_bytes;
+u32 total_sent_pkts;
+u32 unicast_pkts_sent;
+struct regpair unicast_bytes_sent;
+struct regpair multicast_bytes_sent;
+u32 multicast_pkts_sent;
+u32 broadcast_pkts_sent;
+struct regpair broadcast_bytes_sent;
+struct regpair done;
+};
+
+/*
+* Protocol-common statistics collected by the Tstorm (per client)
+*/
+struct tstorm_per_client_stats {
+struct regpair total_rcv_bytes;
+struct regpair rcv_unicast_bytes;
+struct regpair rcv_broadcast_bytes;
+struct regpair rcv_multicast_bytes;
+struct regpair rcv_error_bytes;
+u32 total_rcv_pkts;
+u32 rcv_unicast_pkts;
+u32 rcv_broadcast_pkts;
+u32 rcv_multicast_pkts;
+u32 no_buff_discard;
+u32 errors_discard;
+u32 ttl0_discard;
+u32 reserved;
+};
+
+/*
+* Protocol-common statistics collected by the Tstorm (per port)
+*/
+struct tstorm_common_stats {
+struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
+u32 mac_filter_discard;
+u32 xxoverflow_discard;
+u32 brb_truncate_discard;
+u32 pkts_till_64B;
+u32 pkts_65_to_127B;
+u32 pkts_128_to_255B;
+u32 pkts_256_to_511B;
+u32 pkts_512_to_1023B;
+u32 pkts_1024_to_1522B;
+u32 pkts_1523_to_9022B;
+struct regpair done;
+};
+
+/*
+* Eth statistics query sturcture for the eth_stats_quesry ramrod
+*/
+struct eth_stats_query {
+struct xstorm_common_stats xstorm_common;
+struct tstorm_common_stats tstorm_common;
+};
+
+
+
+
+/*
+* FW version stored in the Xstorm RAM
+*/
+struct fw_version {
+#if defined(__BIG_ENDIAN)
+u16 patch;
+u8 primary;
+u8 client;
+#elif defined(__LITTLE_ENDIAN)
+u8 client;
+u8 primary;
+u16 patch;
+#endif
+u32 flags;
+#define FW_VERSION_OPTIMIZED (0x1<<0)
+#define FW_VERSION_OPTIMIZED_SHIFT 0
+#define __FW_VERSION_RESERVED (0x7FFFFFFF<<1)
+#define __FW_VERSION_RESERVED_SHIFT 1
+};
+
+
+/*
+* FW version stored in first line of pram
+*/
+struct pram_fw_version {
+#if defined(__BIG_ENDIAN)
+u16 patch;
+u8 primary;
+u8 client;
+#elif defined(__LITTLE_ENDIAN)
+u8 client;
+u8 primary;
+u16 patch;
+#endif
+u8 flags;
+#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
+#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
+#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
+#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
+#define __PRAM_FW_VERSION_RESERVED0 (0x1F<<3)
+#define __PRAM_FW_VERSION_RESERVED0_SHIFT 3
+};
+
+/*
+* The send queue element
+*/
+struct slow_path_element {
+struct spe_hdr hdr;
+u8 protocol_data[8];
+};
+
+/*
+* eth/toe flags that indicate if to query
+*/
+struct stats_indication_flags {
+u32 collect_eth;
+u32 collect_toe;
+};
+
+#pragma pack(pop)
+
+#endif
--
1.4.2
^ permalink raw reply related
* [BNX2X][PATCH 5/8] bnx2x_init.h
From: Eliezer Tamir @ 2007-10-07 16:23 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x_init.h - Various bits of init code.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x_init.h | 555
++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 555 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
new file mode 100644
index 0000000..c46f064
--- /dev/null
+++ b/drivers/net/bnx2x_init.h
@@ -0,0 +1,555 @@
+/* bnx2x_init.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ * Written by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
+ */
+#ifndef EVEREST_INIT_FUNCTIONS_H
+#define EVEREST_INIT_FUNCTIONS_H
+
+#define COMMON 0x1
+#define PORT0 0x2
+#define PORT1 0x4
+
+#define INIT_EMULATION 0x1
+#define INIT_FPGA 0x2
+#define INIT_ASIC 0x4
+#define INIT_HARDWARE 0x7
+
+#define BLCNUM_PRS 0
+#define BLCNUM_SRCH 1
+#define BLCNUM_TSDM 2
+#define BLCNUM_TCM 3
+#define BLCNUM_BRB1 4
+#define BLCNUM_TSEM 5
+#define BLCNUM_PXPCS 6
+#define BLCNUM_EMAC0 7
+#define BLCNUM_EMAC1 8
+#define BLCNUM_DBU 9
+#define BLCNUM_MISC 10
+#define BLCNUM_DBG 11
+#define BLCNUM_NIG 12
+#define BLCNUM_MCP 13
+#define BLCNUM_UPB 14
+#define BLCNUM_CSDM 15
+#define BLCNUM_USDM 16
+#define BLCNUM_CCM 17
+#define BLCNUM_UCM 18
+#define BLCNUM_USEM 19
+#define BLCNUM_CSEM 20
+#define BLCNUM_XPB 21
+#define BLCNUM_DQ 22
+#define BLCNUM_TIMERS 23
+#define BLCNUM_XSDM 24
+#define BLCNUM_QM 25
+#define BLCNUM_PBF 26
+#define BLCNUM_XCM 27
+#define BLCNUM_XSEM 28
+#define BLCNUM_CDU 29
+#define BLCNUM_DMAE 30
+#define BLCNUM_PXP 31
+#define BLCNUM_CFC 32
+#define BLCNUM_HC 33
+#define BLCNUM_PXP2 34
+#define BLCNUM_MISC_AEU 35
+
+
+static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
+
+static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
+ u32 wb_addr, u32 wb_len);
+
+static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
+
+
+#define MEM_WR(block_addr, reg, value, len32) \
+do { \
+ int __i; \
+ for (__i = 0; __i < len32; __i++) { \
+ REG_WR(bp, block_addr, reg + __i*4, (((u32 *)(value))[__i])); \
+ if (!(__i % 10000)) { \
+ touch_softlockup_watchdog(); \
+ cpu_relax(); \
+ } \
+ } \
+} while (0)
+
+#define MEM_IND(block_addr, reg, value, len32) \
+do { \
+ int __i; \
+ for (__i = 0; __i < len32; __i++) { \
+ REG_WR_IND(bp, block_addr, reg + __i*4, \
+ (((u32 *)(value))[__i])); \
+ if (!(__i % 10000)) { \
+ touch_softlockup_watchdog(); \
+ cpu_relax(); \
+ } \
+ } \
+} while (0)
+
+#define _DMAE_WR(block_addr, reg, len32) \
+do { \
+ int __len32 = len32, offset = 0; \
+ while (__len32 > DMAE_LEN_MAX) { \
+/* DP(NETIF_MSG_DMAE, "DMAE_WR: offset %d len32 %d\n", \
+ offset, __len32); */ \
+ bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, \
+ block_addr + reg + offset, DMAE_LEN_MAX); \
+ offset += DMAE_LEN_MAX * 4; \
+ __len32 -= DMAE_LEN_MAX; \
+ } \
+/* DP(NETIF_MSG_DMAE, "DMAE_WR: offset %d len32 %d\n", offset, \
+ __len32); */ \
+ bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, \
+ block_addr + reg + offset, __len32); \
+} while (0)
+
+#define DMAE_WR(block_addr, reg, value, len32) \
+do { \
+/* DP(NETIF_MSG_DMAE, "DMAE_WR: block 0x%x reg 0x%lx len32 %d\n", \
+ block_addr, reg, len32); */ \
+ memcpy(bp->gunzip_buf, value, (len32) * 4); \
+ _DMAE_WR(block_addr, reg, len32); \
+} while (0)
+
+#define DMAE_CLR(bp, block_addr, reg, len32) \
+do { \
+/* DP(NETIF_MSG_DMAE, "DMAE_CLR: block 0x%x reg 0x%lx len32 %d\n", \
+ block_addr, reg, len32); */ \
+ memset(bp->gunzip_buf, 0, (len32) * 4); \
+ _DMAE_WR(block_addr, reg, len32); \
+} while (0)
+
+#define GUNZIP_DMAE_WR(block_addr, reg, value, len8) \
+do { \
+/* DP(NETIF_MSG_DMAE, "GUNZIP_DMAE_WR: block 0x%x reg 0x%lx len8 %d\n", \
+ block_addr, reg, len8); */ \
+ bnx2x_gunzip(bp, (u8 *)(value), len8); \
+/* DP(NETIF_MSG_DMAE, " ==> outlen %d\n", bp->gunzip_outlen); */ \
+ _DMAE_WR(block_addr, reg, bp->gunzip_outlen); \
+} while (0)
+
+
+#define INIT_INTERNAL0_MEM_WR(block_bar, block, reg, \
+ part, hw, value, off, len) \
+ INIT_MEM_WR(block, reg, part, hw, value, off, len);
+
+#define INIT_REG_WR(block, reg, value, part, hw) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ REG_WR(bp, GRCBASE_##block, reg, value); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_REG_RD(block, reg, value, part, hw) \
+do { \
+ u32 val; \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ val = REG_RD(bp, GRCBASE_##block, reg); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_MEM_WR(block, reg, part, hw, value, off, len) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ MEM_WR(GRCBASE_##block, reg + (off<<2), value, len); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_MEM_IND(block, reg, part, hw, value, off, len) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ MEM_IND(GRCBASE_##block, reg + (off<<2), value, len); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_MEM_WB(block, reg, part, hw, value, off, len) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ DMAE_WR(GRCBASE_##block, reg + (off<<2), value, len); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_MEM_CLR(block, reg, part, hw, off, len) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ DMAE_CLR(bp, GRCBASE_##block, reg + (off<<2), len); \
+ usage++; \
+ } \
+} while (0)
+
+#define INIT_GUNZIP_DMAE(block, reg, part, hw, value, off, len) \
+do { \
+ if ((_block == BLCNUM_##block) && (_part == part) && (_hw & hw)) { \
+ GUNZIP_DMAE_WR(GRCBASE_##block, reg + (off<<2), value, len); \
+ usage++; \
+ } \
+} while (0)
+
+
+static void bnx2x_init_stage(struct bnx2x *bp, int _block, int _part)
+{
+ int _hw;
+ int usage = 0;
+
+ switch (CHIP_REV(bp)) {
+ case CHIP_REV_EMUL:
+ _hw = INIT_EMULATION;
+ break;
+ case CHIP_REV_FPGA:
+ _hw = INIT_FPGA;
+ break;
+ default:
+ _hw = INIT_ASIC;
+ }
+
+ touch_softlockup_watchdog();
+
+#define STORAGE_CLASS static const u32
+#ifdef __BIG_ENDIAN
+#include "bnx2x_asm_be.h"
+#else
+#include "bnx2x_asm.h"
+#endif
+#include "bnx2x_init_values.h"
+
+ DP(NETIF_MSG_HW, "Block %d, Part %d, hw %d - usage %d\n",
+ _block, _part, _hw, usage);
+}
+
+#undef INIT_INTERNAL0_MEM_WR
+#undef INIT_REG_WR
+#undef INIT_REG_RD
+#undef INIT_MEM_WR
+#undef INIT_MEM_IND
+#undef INIT_MEM_WB
+#undef INIT_MEM_CLR
+#undef INIT_GUNZIP_DMAE
+
+
+static void bnx2x_zero_intmem(struct bnx2x *bp)
+{
+#define STORM_INTMEM_SIZE 22528
+
+ u32 storms[4] = {0x1a0000, /*T*/
+ 0x220000, /*C*/
+ 0x2a0000, /*X*/
+ 0x320000};/*U*/
+ u32 i;
+
+ for (i = 0; i < 4; i++) {
+ DMAE_CLR(bp, storms[i], 0UL, STORM_INTMEM_SIZE / 4);
+ }
+}
+
+
+/****************************************************************************
+* PXP
+****************************************************************************/
+
+#define NUM_WR_Q 13
+#define NUM_RD_Q 29
+#define MAX_RD_ORD 3
+#define MAX_WR_ORD 2
+
+struct arb_line {
+ int l;
+ int add;
+ int ubound;
+};
+
+static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
+ {{ 8 , 64 , 25}, { 16 , 64 , 25}, { 32 , 64 , 25}, { 64 , 64 , 41}},
+ {{ 4 , 8 , 4}, { 4 , 8 , 4}, { 4 , 8 , 4}, { 4 , 8 , 4}},
+ {{ 4 , 3 , 3}, { 4 , 3 , 3}, { 4 , 3 , 3}, { 4 , 3 , 3}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 16 , 3 , 11}, { 16 , 3 , 11}},
+ {{ 8 , 64 , 25}, { 16 , 64 , 25}, { 32 , 64 , 25}, { 64 , 64 , 41}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 64 , 3 , 41}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 64 , 3 , 41}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 64 , 3 , 41}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 64 , 3 , 41}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 3 , 6}, { 16 , 3 , 11}, { 32 , 3 , 21}, { 32 , 3 , 21}},
+ {{ 8 , 64 , 25}, { 16 , 64 , 41}, { 32 , 64 , 81}, { 64 , 64 , 120}}};
+
+static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
+ {{ 4 , 6 , 3}, { 4 , 6 , 3}, { 4 , 6 , 3}},
+ {{ 4 , 2 , 3}, { 4 , 2 , 3}, { 4 , 2 , 3}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 16 , 2 , 11}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 32 , 2 , 21}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 32 , 2 , 21}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 32 , 2 , 21}},
+ {{ 8 , 64 , 25}, { 16 , 64 , 25}, { 32 , 64 , 25}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 16 , 2 , 11}},
+ {{ 8 , 2 , 6}, { 16 , 2 , 11}, { 16 , 2 , 11}},
+ {{ 8 , 9 , 6}, { 16 , 9 , 11}, { 32 , 9 , 21}},
+ {{ 8 , 47 , 19}, { 16 , 47 , 19}, { 32 , 47 , 21}},
+ {{ 8 , 9 , 6}, { 16 , 9 , 11}, { 16 , 9 , 11}},
+ {{ 8 , 64 , 25}, { 16 , 64 , 41}, { 32 , 64 , 81}}};
+
+static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
+ {PXP2_REGISTERS_RQ_BW_RD_L0, PXP2_REGISTERS_RQ_BW_RD_ADD0 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND0},
+ {PXP2_REGISTERS_PSWRQ_BW_L1, PXP2_REGISTERS_PSWRQ_BW_ADD1 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB1},
+ {PXP2_REGISTERS_PSWRQ_BW_L2, PXP2_REGISTERS_PSWRQ_BW_ADD2 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB2},
+ {PXP2_REGISTERS_PSWRQ_BW_L3, PXP2_REGISTERS_PSWRQ_BW_ADD3 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB3},
+ {PXP2_REGISTERS_RQ_BW_RD_L4, PXP2_REGISTERS_RQ_BW_RD_ADD4 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND4},
+ {PXP2_REGISTERS_RQ_BW_RD_L5, PXP2_REGISTERS_RQ_BW_RD_ADD5 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND5},
+ {PXP2_REGISTERS_PSWRQ_BW_L6, PXP2_REGISTERS_PSWRQ_BW_ADD6 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB6},
+ {PXP2_REGISTERS_PSWRQ_BW_L7, PXP2_REGISTERS_PSWRQ_BW_ADD7 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB7},
+ {PXP2_REGISTERS_PSWRQ_BW_L8, PXP2_REGISTERS_PSWRQ_BW_ADD8 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB8},
+ {PXP2_REGISTERS_PSWRQ_BW_L9, PXP2_REGISTERS_PSWRQ_BW_ADD9 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB9},
+ {PXP2_REGISTERS_PSWRQ_BW_L10, PXP2_REGISTERS_PSWRQ_BW_ADD10 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB10},
+ {PXP2_REGISTERS_PSWRQ_BW_L11, PXP2_REGISTERS_PSWRQ_BW_ADD11 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB11},
+ {PXP2_REGISTERS_RQ_BW_RD_L12, PXP2_REGISTERS_RQ_BW_RD_ADD12 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND12},
+ {PXP2_REGISTERS_RQ_BW_RD_L13, PXP2_REGISTERS_RQ_BW_RD_ADD13 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND13},
+ {PXP2_REGISTERS_RQ_BW_RD_L14, PXP2_REGISTERS_RQ_BW_RD_ADD14 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND14},
+ {PXP2_REGISTERS_RQ_BW_RD_L15, PXP2_REGISTERS_RQ_BW_RD_ADD15 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND15},
+ {PXP2_REGISTERS_RQ_BW_RD_L16, PXP2_REGISTERS_RQ_BW_RD_ADD16 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND16},
+ {PXP2_REGISTERS_RQ_BW_RD_L17, PXP2_REGISTERS_RQ_BW_RD_ADD17 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND17},
+ {PXP2_REGISTERS_RQ_BW_RD_L18, PXP2_REGISTERS_RQ_BW_RD_ADD18 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND18},
+ {PXP2_REGISTERS_RQ_BW_RD_L19, PXP2_REGISTERS_RQ_BW_RD_ADD19 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND19},
+ {PXP2_REGISTERS_RQ_BW_RD_L20, PXP2_REGISTERS_RQ_BW_RD_ADD20 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND20},
+ {PXP2_REGISTERS_RQ_BW_RD_L22, PXP2_REGISTERS_RQ_BW_RD_ADD22 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND22},
+ {PXP2_REGISTERS_RQ_BW_RD_L23, PXP2_REGISTERS_RQ_BW_RD_ADD23 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND23},
+ {PXP2_REGISTERS_RQ_BW_RD_L24, PXP2_REGISTERS_RQ_BW_RD_ADD24 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND24},
+ {PXP2_REGISTERS_RQ_BW_RD_L25, PXP2_REGISTERS_RQ_BW_RD_ADD25 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND25},
+ {PXP2_REGISTERS_RQ_BW_RD_L26, PXP2_REGISTERS_RQ_BW_RD_ADD26 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND26},
+ {PXP2_REGISTERS_RQ_BW_RD_L27, PXP2_REGISTERS_RQ_BW_RD_ADD27 ,
+ PXP2_REGISTERS_RQ_BW_RD_UBOUND27},
+ {PXP2_REGISTERS_PSWRQ_BW_L28, PXP2_REGISTERS_PSWRQ_BW_ADD28 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB28}};
+
+static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
+ {PXP2_REGISTERS_PSWRQ_BW_L1, PXP2_REGISTERS_PSWRQ_BW_ADD1 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB1},
+ {PXP2_REGISTERS_PSWRQ_BW_L2, PXP2_REGISTERS_PSWRQ_BW_ADD2 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB2},
+ {PXP2_REGISTERS_PSWRQ_BW_L3, PXP2_REGISTERS_PSWRQ_BW_ADD3 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB3},
+ {PXP2_REGISTERS_PSWRQ_BW_L6, PXP2_REGISTERS_PSWRQ_BW_ADD6 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB6},
+ {PXP2_REGISTERS_PSWRQ_BW_L7, PXP2_REGISTERS_PSWRQ_BW_ADD7 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB7},
+ {PXP2_REGISTERS_PSWRQ_BW_L8, PXP2_REGISTERS_PSWRQ_BW_ADD8 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB8},
+ {PXP2_REGISTERS_PSWRQ_BW_L9, PXP2_REGISTERS_PSWRQ_BW_ADD9 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB9},
+ {PXP2_REGISTERS_PSWRQ_BW_L10, PXP2_REGISTERS_PSWRQ_BW_ADD10 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB10},
+ {PXP2_REGISTERS_PSWRQ_BW_L11, PXP2_REGISTERS_PSWRQ_BW_ADD11 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB11},
+ {PXP2_REGISTERS_PSWRQ_BW_L28, PXP2_REGISTERS_PSWRQ_BW_ADD28 ,
+ PXP2_REGISTERS_PSWRQ_BW_UB28},
+ {PXP2_REGISTERS_RQ_BW_WR_L29, PXP2_REGISTERS_RQ_BW_WR_ADD29 ,
+ PXP2_REGISTERS_RQ_BW_WR_UBOUND29},
+ {PXP2_REGISTERS_RQ_BW_WR_L30, PXP2_REGISTERS_RQ_BW_WR_ADD30 ,
+ PXP2_REGISTERS_RQ_BW_WR_UBOUND30}};
+
+static void bnx2x_init_pxp(struct bnx2x *bp, int r_order, int w_order)
+{
+ int i, val;
+
+ if (r_order > MAX_RD_ORD) {
+ DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
+ r_order, MAX_RD_ORD);
+ r_order = MAX_RD_ORD;
+ }
+
+ if (w_order > MAX_WR_ORD) {
+ DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
+ w_order, MAX_WR_ORD);
+ w_order = MAX_WR_ORD;
+ }
+
+ DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
+
+ for (i = 0; i < NUM_RD_Q-1; i++) {
+ REG_WR(bp, GRCBASE_PXP2, read_arb_addr[i].l,
+ read_arb_data[i][r_order].l);
+ REG_WR(bp, GRCBASE_PXP2, read_arb_addr[i].add,
+ read_arb_data[i][r_order].add);
+ REG_WR(bp, GRCBASE_PXP2, read_arb_addr[i].ubound,
+ read_arb_data[i][r_order].ubound);
+ }
+
+ for (i = 0; i < NUM_WR_Q-1; i++) {
+ if ((write_arb_addr[i].l == PXP2_REGISTERS_RQ_BW_WR_L29) ||
+ (write_arb_addr[i].l == PXP2_REGISTERS_RQ_BW_WR_L30)) {
+
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].l,
+ write_arb_data[i][w_order].l);
+
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].add,
+ write_arb_data[i][w_order].add);
+
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].ubound,
+ write_arb_data[i][w_order].ubound);
+ } else {
+
+ val = REG_RD(bp, GRCBASE_PXP2, write_arb_addr[i].l);
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].l,
+ val | (write_arb_data[i][w_order].l << 10));
+
+ val = REG_RD(bp, GRCBASE_PXP2, write_arb_addr[i].add);
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].add,
+ val | (write_arb_data[i][w_order].add << 10));
+
+ val = REG_RD(bp, GRCBASE_PXP2,
+ write_arb_addr[i].ubound);
+ REG_WR(bp, GRCBASE_PXP2, write_arb_addr[i].ubound,
+ val | (write_arb_data[i][w_order].ubound << 7));
+ }
+ }
+
+ val = write_arb_data[NUM_WR_Q-1][w_order].add;
+ val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
+ val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_PSWRQ_BW_RD, val);
+
+ val = read_arb_data[NUM_RD_Q-1][r_order].add;
+ val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
+ val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_PSWRQ_BW_WR, val);
+
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_WR_MBS0, w_order);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_WR_MBS0 + 8, w_order);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_RD_MBS0, r_order);
+ REG_WR(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_RD_MBS0 + 8, r_order);
+}
+
+
+/****************************************************************************
+* CDU
+****************************************************************************/
+
+#define CDU_REGION_NUMBER_XCM_AG 2
+#define CDU_REGION_NUMBER_UCM_AG 4
+
+/**
+ * String-to-compress [31:8] = CID (all 24 bits)
+ * String-to-compress [7:4] = Region
+ * String-to-compress [3:0] = Type
+ */
+#define CDU_VALID_DATA(_cid, _region, _type) \
+ (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
+#define CDU_CRC8(_cid, _region, _type) \
+ calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
+#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
+ (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
+#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
+ (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
+#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
+
+/*****************************************************************************
+ * Description:
+ * Calculates crc 8 on a word value: polynomial 0-1-2-8
+ * Code was translated from Verilog.
+
****************************************************************************/
+static u8 calc_crc8(u32 data, u8 crc)
+{
+ u8 D[32];
+ u8 NewCRC[8];
+ u8 C[8];
+ u8 crc_res;
+ u8 i;
+
+ /* split the data into 31 bits */
+ for (i = 0; i < 32; i++) {
+ D[i] = data & 1;
+ data = data >> 1;
+ }
+
+ /* split the crc into 8 bits */
+ for (i = 0; i < 8; i++ ) {
+ C[i] = crc & 1;
+ crc = crc >> 1;
+ }
+
+ NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
+ D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
+ C[6] ^ C[7];
+ NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
+ D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
+ D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
+ NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
+ D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
+ C[0] ^ C[1] ^ C[4] ^ C[5];
+ NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
+ D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
+ C[1] ^ C[2] ^ C[5] ^ C[6];
+ NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
+ D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
+ C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
+ NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
+ D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
+ C[3] ^ C[4] ^ C[7];
+ NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
+ D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
+ C[5];
+ NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
+ D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
+ C[6];
+
+ crc_res = 0;
+ for (i = 0; i < 8; i++) {
+ crc_res |= (NewCRC[i] << i);
+ }
+
+ return crc_res;
+}
+
+
+#endif /* EVEREST_INIT_FUNCTIONS_H */
+
--
1.4.2
^ permalink raw reply related
* [BNx2X][PATCH 6/8] bnx2x_init_values.h
From: Eliezer Tamir @ 2007-10-07 16:23 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x_init_values.h -HW init code machine generated from HW definitions.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x_init_values.h | 7789
+++++++++++++++++++++++++++++++++++++++
1 files changed, 7789 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x_init_values.h
b/drivers/net/bnx2x_init_values.h
new file mode 100644
index 0000000..0d626e3
--- /dev/null
+++ b/drivers/net/bnx2x_init_values.h
@@ -0,0 +1,7789 @@
+/* bnx2x_init_values.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ */
+
+/* machine generated - don't change */
+
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FIC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FIC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FOC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FOC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FOC2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSEM, TSEM_REGISTERS_MSG_NUM_FOC3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_ELEMENT0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_ELEMENT1, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_ELEMENT2, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_ELEMENT3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_ELEMENT4, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ARB_CYCLE_SIZE, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_0_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_1_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_2_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_3_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_4_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_5_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_6_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_7_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_8_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_9_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_10_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_11_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_12_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_13_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_14_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_15_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_16_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_17_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_18_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_TS_19_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ENABLE_IN, 0X3FFF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_ENABLE_OUT, 0X3FF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_FIC0_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_FIC1_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_PAS_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSEM, TSEM_REGISTERS_THREADS_LIST, 0XFF, COMMON,
INIT_HARDWARE);
+
+INIT_MEM_CLR(TSEM, TSEM_REGISTERS_PASSIVE_BUFFER, COMMON,
INIT_HARDWARE, 0X0,
+2048);
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION[] = {
+0x1};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1[] = {
+0x34};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2[] = {
+0x18};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3[] = {
+0xc};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4[] = {
+0x20};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5[] = {
+0x138};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6[] = {
+0x1f4};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x1};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7,
+0X800, 436);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8,
+0X408, 200);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9,
+0X400, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_10,
+0X1000, 336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_11,
+0X1150, 336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_12,
+0X500, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_13,
+0X50A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_14,
+0X514, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_15,
+0X51A, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_16,
+0X540, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_17,
+0X54A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_18,
+0X554, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_19,
+0X566, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_20,
+0X578, 108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_21,
+0X5E4, 108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_22[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_22,
+0X200, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_23[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_23,
+0X202, 2);
+}
+
+
+{
+static const u32
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_24[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_24,
+0X200, 2);
+}
+
+
+{
+static const u32
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_25[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_25,
+0X202, 2);
+}
+
+
+{
+static const u32
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_26[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_26,
+0X204, 4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_27,
+0X208, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_28,
+0X21A, 18);
+}
+
+
+{
+static const u32
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_29[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_29,
+0X7E4, 4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30,
+0XA42, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_31,
+0XA4C, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA[] = {
+0x1};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1[] = {
+0x34};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2[] = {
+0x18};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3[] = {
+0xc};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4[] = {
+0x20};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5[] = {
+0x1388};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6[] = {
+0x1f4};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x1};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7, 0X800,
+436);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9,
0X400, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_10, 0X1000,
+336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_11, 0X1150,
+336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_12,
0X500, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_13,
0X50A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_14,
0X514, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_15,
0X51A, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_16,
0X540, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_17,
0X54A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_18,
0X554, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_19,
0X566, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_20, 0X578,
+108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_21, 0X5E4,
+108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_22[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_22,
0X200, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_23[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_23,
0X202, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_24[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_24, 0X200,
+2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_25[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_25, 0X202,
+2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_26[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_26, 0X204,
+4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_27,
0X208, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_28,
0X21A, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_29[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_29, 0X7E4,
+4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30,
0XA42, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_31,
0XA4C, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC[] = {
+0x1};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1[] = {
+0x34};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2[] = {
+0x18};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3[] = {
+0xc};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4[] = {
+0x20};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5[] = {
+0x7a120};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6[] = {
+0x1f4};
+INIT_MEM_WR(TSEM, TSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x1};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7, 0X800,
+436);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9,
0X400, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_10, 0X1000,
+336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_11, 0X1150,
+336);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_12,
0X500, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_13,
0X50A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_14,
0X514, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_15,
0X51A, 6);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_16,
0X540, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_17,
0X54A, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_18,
0X554, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_19,
0X566, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_20, 0X578,
+108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_21, 0X5E4,
+108);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_22[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_22,
0X200, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_23[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_23,
0X202, 2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_24[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_24, 0X200,
+2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_25[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_25, 0X202,
+2);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_26[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_26, 0X204,
+4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_27,
0X208, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_28,
0X21A, 18);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_29[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_TSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_29, 0X7E4,
+4);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30,
0XA42, 10);
+}
+
+
+{
+static const u32 EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_TSTRORM_INTMEM, TSEM, TSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_TSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_31,
0XA4C, 10);
+}
+
+INIT_REG_WR(CDU, CDU_REGISTERS_CDU_CONTROL0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CDU, CDU_REGISTERS_CDU_CHK_MASK0, 0X3D000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CDU, CDU_REGISTERS_CDU_CHK_MASK1, 0X3D, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_CDU_L1TT_COMMON_MEMORY_INIT_HARDWARE[] = {
+0xfffffff3, 0x314fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xfffffff1, 0x30efffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xfffffff6, 0x305fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0xc30c305, 0xc30c30c3, 0xcf300014,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xfffffff2, 0x304fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xfffffff7, 0x31efffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xfffffff5, 0x302fffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf300, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xfffffff3, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xfffffff6, 0x305fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0xc30c305, 0xc30c30c3, 0xcf300014,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xfffffff2, 0x304fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xfffffff7, 0x30efffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf300, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xfffffff3, 0x31efffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xfffffff6, 0x305fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0xc30c305, 0xc30c30c3, 0xcf300014,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xfffffff2, 0x304fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffff97, 0x56fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
0x20cf3c,
+0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xfffffff3, 0x320fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xfffffff6, 0x305fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0xc30c305, 0xc30c30c3, 0xcf300014,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xfffffff2, 0x304fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xffffff8a, 0x42fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cc000,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffff97, 0x5cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3,
0x20cf3c,
+0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf300,
+0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf3cc, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf3cc, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf3cc, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0xcf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x1cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x2cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x4cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
0x8cf3c,
+0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc,
+0xf3cf3cf3, 0x10cf3c, 0xcdcdcdcd,
+0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3,
+0x20cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0xc30c30c, 0xc30c30c3,
+0xcf3cf3cc, 0xf3cf3cf3, 0x40cf3c, 0xcdcdcdcd};
+INIT_MEM_WB(CDU, CDU_REGISTERS_L1TT, COMMON, INIT_HARDWARE,
+EVST_CDU_L1TT_COMMON_MEMORY_INIT_HARDWARE, 0X0, 512);
+}
+
+
+{
+static const u32 EVST_CDU_MATT_COMMON_MEMORY_INIT_HARDWARE[] = {
+0xa0000, 0x700a0, 0x28110, 0xb8138, 0x201f0, 0x10210, 0xf0220, 0x10310,
+0x80000, 0x80080, 0x28100, 0xb8128, 0x201e0, 0x10200, 0x70210, 0x20280,
+0xf0000, 0x800f0, 0x28170, 0xb8198, 0x20250, 0x10270, 0xb8280, 0x80338,
+0x100000, 0x80100, 0x28180, 0xb81a8, 0x20260, 0x18280, 0xe8298, 0x80380,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_MEM_WB(CDU, CDU_REGISTERS_MATT, COMMON, INIT_HARDWARE,
+EVST_CDU_MATT_COMMON_MEMORY_INIT_HARDWARE, 0X0, 64);
+}
+
+INIT_REG_WR(CFC, CFC_REGISTERS_CONTROL0, 0X10, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CFC, CFC_REGISTERS_DISABLE_ON_ERROR, 0X3FFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CFC, CFC_REGISTERS_LCREQ_WEIGHTS, 0X84924A, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_INC_VALUE, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_EVENT_ID_1, 0X45, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_EVENT_ID_2, 0X84, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_EVENT_ID_3, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_NO_MATCH_EVENT_ID, 0X4, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_1, 0X12170000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_2, 0X22170000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_3, 0X32170000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_TYPE_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_0, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_1, 0X12150000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_2, 0X22150000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_3, 0X32150000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_5, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_6, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_7, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_NO_MATCH_HDR, 0X2100000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0X100000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0X10100000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0X20100000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0X30100000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_6, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_7, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_0, 0X100000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_1, 0X12140000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_2, 0X22140000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_3, 0X32140000,
COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_5, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_6, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_7, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CID_PORT_0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_CID_PORT_1, 0X800000, PORT1, INIT_HARDWARE);
+INIT_REG_RD(PRS, PRS_REGISTERS_NUM_OF_PACKETS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(PRS, PRS_REGISTERS_NUM_OF_CFC_FLUSH_MESSAGES, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(PRS, PRS_REGISTERS_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0X0,
COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(PRS, PRS_REGISTERS_NUM_OF_DEAD_CYCLES, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_0, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_1, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_2, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_3, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_4, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_5, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_6, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_FLUSH_REGIONS_TYPE_7, 0XFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PURE_REGIONS, 0X3E, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_0, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_1, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_2, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_3, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_5, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_6, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PRS, PRS_REGISTERS_PACKET_REGIONS_TYPE_7, 0X3F, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CFC_RSP_START_ADDR, 0X411, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CMP_COUNTER_START_ADDR, 0X400, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_Q_COUNTER_START_ADDR, 0X404, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_PCK_END_MSG_START_ADDR, 0X419, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CMP_COUNTER_MAX0, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CMP_COUNTER_MAX1, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CMP_COUNTER_MAX2, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_CMP_COUNTER_MAX3, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_EVENT_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_12, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_13, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_14, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_15, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_16, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_17, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_18, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_19, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_20, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_21, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_22, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_23, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_24, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_25, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_26, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_27, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_28, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_29, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_30, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_T_31, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_FIC_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_AGG_INT_MODE_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_ENABLE_IN1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_ENABLE_IN2, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_ENABLE_OUT1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_ENABLE_OUT2, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q0_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q1_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q3_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q4_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q5_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q6_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q7_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q8_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q9_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q10_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_Q11_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_PKT_END_MSG, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(TSDM, TSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_TIMER_TICK, 0X1, COMMON, INIT_EMULATION);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_TIMER_TICK, 0XA, COMMON, INIT_FPGA);
+INIT_REG_WR(TSDM, TSDM_REGISTERS_TIMER_TICK, 0X3E8, COMMON, INIT_ASIC);
+INIT_REG_WR(TCM, TCM_REGISTERS_XX_MAX_LL_SZ, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_XX_OVFL_EVNT_ID, 0X32, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TQM_TCM_HDR_P, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TQM_TCM_HDR_S, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TM_TCM_HDR, 0X30, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_ERR_TCM_HDR, 0X8100000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_ERR_EVNT_ID, 0X33, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_EXPR_EVNT_ID, 0X30, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_STOP_EVNT_ID, 0X31, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PRS_WEIGHT, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PBF_WEIGHT, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CP_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TSDM_WEIGHT, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_TQM_USE_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_GR_ARB_TYPE, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_GR_LD0_PR, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_GR_LD1_PR, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CFC_INIT_CRD, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_FIC0_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_FIC1_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TQM_INIT_CRD, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_XX_INIT_CRD, 0X13, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_XX_MSG_NUM, 0X20, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_TCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(TCM, TCM_REGISTERS_XX_TABLE, COMMON, INIT_HARDWARE,
+EVST_TCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 10);
+}
+
+
+{
+static const u32 EVST_TCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x10000, 0x204c0, 0x30980, 0x40e40, 0x51300, 0x617c0, 0x71c80, 0x82140,
+0x92600, 0xa2ac0, 0xb2f80, 0xc3440, 0xd3900, 0xe3dc0, 0xf4280, 0x104740,
+0x114c00, 0x1250c0, 0x135580, 0x145a40, 0x155f00, 0x1663c0, 0x176880,
0x186d40,
+0x197200, 0x1a76c0, 0x1b7b80, 0x1c8040, 0x1d8500, 0x1e89c0, 0x1f8e80,
+0x209340};
+INIT_MEM_WR(TCM, TCM_REGISTERS_XX_DESCR_TABLE, COMMON, INIT_HARDWARE,
+EVST_TCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 32);
+}
+
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_0, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_1, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_2, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_3, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_N_SM_CTX_LD_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_REG0_SZ, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM0_0, 0X1D, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM0_1, 0X3D, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM1_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM1_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM2_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM2_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM3_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PHYS_QNUM3_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_STORM0_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_STORM1_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_TQM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_STORM_TCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TQM_TCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TSDM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TM_TCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PRS_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_PBF_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_USEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CDU_AG_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CDU_AG_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CDU_SM_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_CDU_SM_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TCM, TCM_REGISTERS_TCM_CFC_IFEN, 0X1, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_BRB1_LL_RAM_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x2000, 0x4000, 0x6000, 0x8000, 0xa000, 0xc000, 0xe000, 0x10000, 0x12000,
+0x14000, 0x16000, 0x18000, 0x1a000, 0x1c000, 0x1e000, 0x20000,
+0x22000, 0x24000, 0x26000, 0x28000, 0x2a000, 0x2c000, 0x2e000, 0x30000,
+0x32000, 0x34000, 0x36000, 0x38000, 0x3a000, 0x3c000, 0x3e000, 0x40000,
+0x42000, 0x44000, 0x46000, 0x48000, 0x4a000, 0x4c000, 0x4e000, 0x50000,
+0x52000, 0x54000, 0x56000, 0x58000, 0x5a000, 0x5c000, 0x5e000, 0x60000,
+0x62000, 0x64000, 0x66000, 0x68000, 0x6a000, 0x6c000, 0x6e000, 0x70000,
+0x72000, 0x74000, 0x76000, 0x78000, 0x7a000, 0x7c000, 0x7e000, 0x80000,
+0x82000, 0x84000, 0x86000, 0x88000, 0x8a000, 0x8c000, 0x8e000, 0x90000,
+0x92000, 0x94000, 0x96000, 0x98000, 0x9a000, 0x9c000, 0x9e000, 0xa0000,
+0xa2000, 0xa4000, 0xa6000, 0xa8000, 0xaa000, 0xac000, 0xae000, 0xb0000,
+0xb2000, 0xb4000, 0xb6000, 0xb8000, 0xba000, 0xbc000, 0xbe000, 0xc0000,
+0xc2000, 0xc4000, 0xc6000, 0xc8000, 0xca000, 0xcc000, 0xce000, 0xd0000,
+0xd2000, 0xd4000, 0xd6000, 0xd8000, 0xda000, 0xdc000, 0xde000, 0xe0000,
+0xe2000, 0xe4000, 0xe6000, 0xe8000, 0xea000, 0xec000, 0xee000, 0xf0000,
+0xf2000, 0xf4000, 0xf6000, 0xf8000, 0xfa000, 0xfc000, 0xfe000, 0x100000,
+0x102000, 0x104000, 0x106000, 0x108000, 0x10a000, 0x10c000, 0x10e000,
0x110000,
+0x112000, 0x114000, 0x116000, 0x118000, 0x11a000, 0x11c000, 0x11e000,
0x120000,
+0x122000, 0x124000, 0x126000, 0x128000, 0x12a000, 0x12c000, 0x12e000,
0x130000,
+0x132000, 0x134000, 0x136000, 0x138000, 0x13a000, 0x13c000, 0x13e000,
0x140000,
+0x142000, 0x144000, 0x146000, 0x148000, 0x14a000, 0x14c000, 0x14e000,
0x150000,
+0x152000, 0x154000, 0x156000, 0x158000, 0x15a000, 0x15c000, 0x15e000,
0x160000,
+0x162000, 0x164000, 0x166000, 0x168000, 0x16a000, 0x16c000, 0x16e000,
0x170000,
+0x172000, 0x174000, 0x176000, 0x178000, 0x17a000, 0x17c000, 0x17e000,
0x180000,
+0x182000, 0x184000, 0x186000, 0x188000, 0x18a000, 0x18c000, 0x18e000,
0x190000,
+0x192000, 0x194000, 0x196000, 0x198000, 0x19a000, 0x19c000, 0x19e000,
0x1a0000,
+0x1a2000, 0x1a4000, 0x1a6000, 0x1a8000, 0x1aa000, 0x1ac000, 0x1ae000,
0x1b0000,
+0x1b2000, 0x1b4000, 0x1b6000, 0x1b8000, 0x1ba000, 0x1bc000, 0x1be000,
0x1c0000,
+0x1c2000, 0x1c4000, 0x1c6000, 0x1c8000, 0x1ca000, 0x1cc000, 0x1ce000,
0x1d0000,
+0x1d2000, 0x1d4000, 0x1d6000, 0x1d8000, 0x1da000, 0x1dc000, 0x1de000,
0x1e0000,
+0x1e2000, 0x1e4000, 0x1e6000, 0x1e8000, 0x1ea000, 0x1ec000, 0x1ee000,
0x1f0000,
+0x1f2000, 0x1f4000, 0x1f6000, 0x1f8000, 0x1fa000, 0x1fc000, 0x1fe000,
0x200000,
+0x202000, 0x204000, 0x206000, 0x208000, 0x20a000, 0x20c000, 0x20e000,
0x210000,
+0x212000, 0x214000, 0x216000, 0x218000, 0x21a000, 0x21c000, 0x21e000,
0x220000,
+0x222000, 0x224000, 0x226000, 0x228000, 0x22a000, 0x22c000, 0x22e000,
0x230000,
+0x232000, 0x234000, 0x236000, 0x238000, 0x23a000, 0x23c000, 0x23e000,
0x240000,
+0x242000, 0x244000, 0x246000, 0x248000, 0x24a000, 0x24c000, 0x24e000,
0x250000,
+0x252000, 0x254000, 0x256000, 0x258000, 0x25a000, 0x25c000, 0x25e000,
0x260000,
+0x262000, 0x264000, 0x266000, 0x268000, 0x26a000, 0x26c000, 0x26e000,
0x270000,
+0x272000, 0x274000, 0x276000, 0x278000, 0x27a000, 0x27c000, 0x27e000,
0x280000,
+0x282000, 0x284000, 0x286000, 0x288000, 0x28a000, 0x28c000, 0x28e000,
0x290000,
+0x292000, 0x294000, 0x296000, 0x298000, 0x29a000, 0x29c000, 0x29e000,
0x2a0000,
+0x2a2000, 0x2a4000, 0x2a6000, 0x2a8000, 0x2aa000, 0x2ac000, 0x2ae000,
0x2b0000,
+0x2b2000, 0x2b4000, 0x2b6000, 0x2b8000, 0x2ba000, 0x2bc000, 0x2be000,
0x2c0000,
+0x2c2000, 0x2c4000, 0x2c6000, 0x2c8000, 0x2ca000, 0x2cc000, 0x2ce000,
0x2d0000,
+0x2d2000, 0x2d4000, 0x2d6000, 0x2d8000, 0x2da000, 0x2dc000, 0x2de000,
0x2e0000,
+0x2e2000, 0x2e4000, 0x2e6000, 0x2e8000, 0x2ea000, 0x2ec000, 0x2ee000,
0x2f0000,
+0x2f2000, 0x2f4000, 0x2f6000, 0x2f8000, 0x2fa000, 0x2fc000, 0x2fe000,
0x300000,
+0x302000, 0x304000, 0x306000, 0x308000, 0x30a000, 0x30c000, 0x30e000,
0x310000,
+0x312000, 0x314000, 0x316000, 0x318000, 0x31a000, 0x31c000, 0x31e000,
0x320000,
+0x322000, 0x324000, 0x326000, 0x328000, 0x32a000, 0x32c000, 0x32e000,
0x330000,
+0x332000, 0x334000, 0x336000, 0x338000, 0x33a000, 0x33c000, 0x33e000,
0x340000,
+0x342000, 0x344000, 0x346000, 0x348000, 0x34a000, 0x34c000, 0x34e000,
0x350000,
+0x352000, 0x354000, 0x356000, 0x358000, 0x35a000, 0x35c000, 0x35e000,
0x360000,
+0x362000, 0x364000, 0x366000, 0x368000, 0x36a000, 0x36c000, 0x36e000,
0x370000,
+0x372000, 0x374000, 0x376000, 0x378000, 0x37a000, 0x37c000, 0x37e000,
0x380000,
+0x382000, 0x384000, 0x386000, 0x388000, 0x38a000, 0x38c000, 0x38e000,
0x390000,
+0x392000, 0x394000, 0x396000, 0x398000, 0x39a000, 0x39c000, 0x39e000,
0x3a0000,
+0x3a2000, 0x3a4000, 0x3a6000, 0x3a8000, 0x3aa000, 0x3ac000, 0x3ae000,
0x3b0000,
+0x3b2000, 0x3b4000, 0x3b6000, 0x3b8000, 0x3ba000, 0x3bc000, 0x3be000,
0x3c0000,
+0x3c2000, 0x3c4000, 0x3c6000, 0x3c8000, 0x3ca000, 0x3cc000, 0x3ce000,
0x3d0000,
+0x3d2000, 0x3d4000, 0x3d6000, 0x3d8000, 0x3da000, 0x3dc000, 0x3de000,
0x3e0000,
+0x3e2000, 0x3e4000, 0x3e6000, 0x3e8000, 0x3ea000, 0x3ec000, 0x3ee000,
0x3f0000,
+0x3f2000, 0x3f4000, 0x3f6000, 0x3f8000, 0x3fa000, 0x3fc000, 0x3fe000,
+0x3fe001};
+INIT_MEM_WR(BRB1, BRB1_REGISTERS_LL_RAM, COMMON, INIT_HARDWARE,
+EVST_BRB1_LL_RAM_COMMON_MEMORY_INIT_HARDWARE, 0X0, 512);
+}
+
+INIT_REG_WR(BRB1, BRB1_REGISTERS_SOFT_RESET, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_0, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_1, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_2, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_3, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_FULL_CYCLES_0, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_FULL_CYCLES_1, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_FULL_CYCLES_2, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_FULL_CYCLES_3, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(BRB1, BRB1_REGISTERS_NUM_OF_FULL_CYCLES_4, 0X0, COMMON,
+INIT_HARDWARE);
+
+{
+static const u32
EVST_BRB1_FREE_LIST_PRS_CRDT_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x1ff, 0x200};
+INIT_MEM_WR(BRB1, BRB1_REGISTERS_FREE_LIST_PRS_CRDT, COMMON, INIT_HARDWARE,
+EVST_BRB1_FREE_LIST_PRS_CRDT_COMMON_MEMORY_INIT_HARDWARE, 0X0, 3);
+}
+
+INIT_REG_WR(BRB1, BRB1_REGISTERS_SOFT_RESET, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_0, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_1, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_2, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_3, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_5, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_6, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_7, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_8, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_9, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_10, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_11, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_12, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_13, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_14, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_15, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_16, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_17, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_18, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_19, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_20, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_GENERAL_ATTN_21, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_0, 0XBF5C0000,
+PORT0, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_0, 0XFFF51FEF,
+PORT0, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_0, 0XFFFF,
PORT0,
+INIT_HARDWARE);
+/* MANUAL CHANGE, ASSAFG */
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_0, 0X500003E0,
+PORT0, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_1, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_1, 0XA000,
PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_1, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_1, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_2, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_2, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_2, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_2, 0XFE00000,
+PORT0, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_3, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_3, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_3, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_3, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_4, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_4, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_4, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_4, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_5, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_5, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_5, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_5, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_6, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_6, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_6, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_6, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_7, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_7, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_7, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_7, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_NIG_0, 0X55540000, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_NIG_0, 0X55555555, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_NIG_0, 0X5555, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_NIG_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_PXP_0, 0X55540000, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_PXP_0, 0X55555555, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_PXP_0, 0X5555, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_PXP_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_0, 0XBF5C0000,
+PORT1, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_0, 0XFFF51FEF,
+PORT1, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_0, 0XFFFF,
PORT1,
+INIT_HARDWARE);
+/* MANUAL CHANGE, ASSAFG */
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_0, 0X500003E0,
+PORT1, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_1, 0XA000,
PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_2, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_2, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_2, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_2, 0XFE00000,
+PORT1, INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_3, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_3, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_3, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_3, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_4, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_4, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_4, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_4, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_5, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_5, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_5, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_5, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_6, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_6, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_6, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_6, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_7, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_7, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_7, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_7, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_NIG_1, 0X55540000, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_NIG_1, 0X55555555, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_NIG_1, 0X5555, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_NIG_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE1_PXP_1, 0X55540000, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE2_PXP_1, 0X55555555, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE3_PXP_1, 0X5555, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_ENABLE4_PXP_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_1_FUNC_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_2_FUNC_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_3_FUNC_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_4_FUNC_0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_1_FUNC_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_2_FUNC_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_3_FUNC_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_INVERTER_4_FUNC_1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_GRC_TIMEOUT_EN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_PLL_STORM_CTRL_1, 0X71D2911, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_PLL_STORM_CTRL_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_PLL_STORM_CTRL_3, 0X9C0424, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_PLL_STORM_CTRL_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(MISC, MISC_REGISTERS_LCPLL_CTRL_1, 0X209, COMMON,
INIT_HARDWARE);
+/* MANUAL CHANGE, ASSAFG */
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0, 0X7, PORT0,
+INIT_HARDWARE);
+/* MANUAL CHANGE, ASSAFG */
+INIT_REG_WR(MISC_AEU, MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1, 0X7, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_CM_HEADER, 0X300000, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_CM_HEADER, 0X300000, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_EVENT_ID, 0X26, PORT0, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_EVENT_ID, 0X26, PORT1, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_ERROR_MASK, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_ERROR_MASK, 0X0, PORT1, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_XCM_MASK, 0X4, PORT0, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_XCM_MASK, 0X4, PORT1, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_BRB1_NOT_MCP, 0X1, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_BRB1_NOT_MCP, 0X1, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_STATUS_INTERRUPT_PORT0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_STATUS_INTERRUPT_PORT1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH0_XCM_INIT_CREDIT, 0X30, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_LLH1_XCM_INIT_CREDIT, 0X30, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_PBF_LB_IN_EN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_PRS_REQ_IN_EN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_BRB0_PAUSE_IN_EN, 0X1, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_BRB1_PAUSE_IN_EN, 0X1, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_EGRESS_PBF0_IN_EN, 0X1, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_EGRESS_PBF1_IN_EN, 0X1, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_EGRESS_DEBUG_IN_EN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_BRB0_OUT_EN, 0X1, PORT0, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_BRB1_OUT_EN, 0X1, PORT1, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_BRB_LB_OUT_EN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_PRS_EOP_OUT_EN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_XCM0_OUT_EN, 0X1, PORT0, INIT_HARDWARE);
+INIT_REG_WR(NIG, NIG_REGISTERS_XCM1_OUT_EN, 0X1, PORT1, INIT_HARDWARE);
+INIT_REG_WR(UPB, PB_REGISTERS_CONTROL, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XPB, PB_REGISTERS_CONTROL, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CFC_RSP_START_ADDR, 0XA11, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CMP_COUNTER_START_ADDR, 0XA00, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_Q_COUNTER_START_ADDR, 0XA04, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CMP_COUNTER_MAX0, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CMP_COUNTER_MAX1, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CMP_COUNTER_MAX2, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_CMP_COUNTER_MAX3, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_EVENT_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_12, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_13, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_14, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_15, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_16, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_17, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_18, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_19, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_20, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_21, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_22, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_23, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_24, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_25, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_26, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_27, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_28, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_29, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_30, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_T_31, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_FIC_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_AGG_INT_MODE_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_ENABLE_IN1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_ENABLE_IN2, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_ENABLE_OUT1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_ENABLE_OUT2, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q0_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q1_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q3_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q4_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q5_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q6_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q7_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q8_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q9_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q10_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_Q11_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_PKT_END_MSG, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(CSDM, CSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_TIMER_TICK, 0X1, COMMON, INIT_EMULATION);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_TIMER_TICK, 0XA, COMMON, INIT_FPGA);
+INIT_REG_WR(CSDM, CSDM_REGISTERS_TIMER_TICK, 0X3E8, COMMON, INIT_ASIC);
+INIT_REG_WR(USDM, USDM_REGISTERS_CFC_RSP_START_ADDR, 0XA11, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_CMP_COUNTER_START_ADDR, 0XA00, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_Q_COUNTER_START_ADDR, 0XA04, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_PCK_END_MSG_START_ADDR, 0XA21, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_CMP_COUNTER_MAX0, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_CMP_COUNTER_MAX1, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_CMP_COUNTER_MAX2, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_CMP_COUNTER_MAX3, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_0, 0X46, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_EVENT_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_12, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_13, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_14, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_15, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_16, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_17, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_18, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_19, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_20, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_21, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_22, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_23, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_24, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_25, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_26, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_27, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_28, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_29, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_30, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_T_31, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_FIC_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_0, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_AGG_INT_MODE_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_ENABLE_IN1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_ENABLE_IN2, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_ENABLE_OUT1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_ENABLE_OUT2, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q0_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q1_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q2_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q3_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q4_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q5_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q6_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q7_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q8_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q9_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q10_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_Q11_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_PKT_END_MSG, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(USDM, USDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(USDM, USDM_REGISTERS_TIMER_TICK, 0X1, COMMON, INIT_EMULATION);
+INIT_REG_WR(USDM, USDM_REGISTERS_TIMER_TICK, 0XA, COMMON, INIT_FPGA);
+INIT_REG_WR(USDM, USDM_REGISTERS_TIMER_TICK, 0X3E8, COMMON, INIT_ASIC);
+INIT_REG_WR(CCM, CCM_REGISTERS_XX_OVFL_EVNT_ID, 0X32, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CQM_CCM_HDR_P, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CQM_CCM_HDR_S, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_ERR_CCM_HDR, 0X8100000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_ERR_EVNT_ID, 0X33, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_TSEM_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_XSEM_WEIGHT, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_USEM_WEIGHT, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PBF_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CP_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CQM_P_WEIGHT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_CQM_USE_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CNT_AUX1_Q, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CNT_AUX2_Q, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_INV_DONE_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_GR_ARB_TYPE, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_GR_LD0_PR, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_GR_LD1_PR, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CFC_INIT_CRD, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CQM_INIT_CRD, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_FIC0_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_FIC1_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_XX_INIT_CRD, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_XX_MSG_NUM, 0X18, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_CCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_MEM_WR(CCM, CCM_REGISTERS_XX_TABLE, COMMON, INIT_HARDWARE,
+EVST_CCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 18);
+}
+
+
+{
+static const u32 EVST_CCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x2000, 0x40c0, 0x6180, 0x8240, 0xa300, 0xc3c0, 0xe480, 0x10540, 0x12600,
+0x146c0, 0x16780, 0x18840, 0x1a900, 0x1c9c0, 0x1ea80, 0x20b40,
+0x22c00, 0x24cc0, 0x26d80, 0x28e40, 0x2af00, 0x2cfc0, 0x2f080, 0x31140,
+0x33200, 0x352c0, 0x37380, 0x39440, 0x3b500, 0x3d5c0, 0x3f680, 0x41740,
+0x43800, 0x458c0, 0x47980, 0x49a40};
+INIT_MEM_WR(CCM, CCM_REGISTERS_XX_DESCR_TABLE, COMMON, INIT_HARDWARE,
+EVST_CCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 36);
+}
+
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_1, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_2, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_3, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_N_SM_CTX_LD_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_REG0_SZ, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM0_0, 0X18, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM0_1, 0X38, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM1_0, 0X19, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM1_1, 0X39, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM2_0, 0X1A, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM2_1, 0X3A, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM3_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_QOS_PHYS_QNUM3_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM1_0, 0X1C, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM1_1, 0X3C, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM2_0, 0X1B, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM2_1, 0X3B, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM3_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PHYS_QNUM3_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_STORM0_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_STORM1_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_CQM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_STORM_CCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CQM_CCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CSDM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_TSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_XSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_USEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_PBF_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CDU_AG_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CDU_AG_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CDU_SM_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CDU_SM_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CCM, CCM_REGISTERS_CCM_CFC_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_XX_OVFL_EVNT_ID, 0X32, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UQM_UCM_HDR_P, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UQM_UCM_HDR_S, 0X2150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_TM_UCM_HDR, 0X30, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_ERR_UCM_HDR, 0X8100000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_ERR_EVNT_ID, 0X33, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_EXPR_EVNT_ID, 0X30, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_STOP_EVNT_ID, 0X31, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_TSEM_WEIGHT, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CSEM_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CP_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UQM_P_WEIGHT, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_UQM_USE_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_INV_CFLG_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_GR_ARB_TYPE, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_GR_LD0_PR, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_GR_LD1_PR, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CFC_INIT_CRD, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_FIC0_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_FIC1_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_TM_INIT_CRD, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UQM_INIT_CRD, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_XX_INIT_CRD, 0XC, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_XX_MSG_NUM, 0X20, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_UCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_MEM_WR(UCM, UCM_REGISTERS_XX_TABLE, COMMON, INIT_HARDWARE,
+EVST_UCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 18);
+}
+
+
+{
+static const u32 EVST_UCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x8000, 0x10300, 0x18600, 0x20900, 0x28c00, 0x30f00, 0x39200, 0x41500,
0x49800,
+0x51b00, 0x59e00, 0x62100, 0x6a400, 0x72700, 0x7aa00, 0x82d00,
+0x8b000, 0x93300, 0x9b600, 0xa3900, 0xabc00, 0xb3f00, 0xbc200, 0xc4500,
+0xcc800, 0xd4b00, 0xdce00, 0xe5100, 0xed400, 0xf5700, 0xfda00, 0x105d00};
+INIT_MEM_WR(UCM, UCM_REGISTERS_XX_DESCR_TABLE, COMMON, INIT_HARDWARE,
+EVST_UCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 32);
+}
+
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_0, 0XA, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_1, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_2, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_3, 0X10, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_N_SM_CTX_LD_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_REG0_SZ, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_PHYS_QNUM0_0, 0X1F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_PHYS_QNUM0_1, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_PHYS_QNUM1_0, 0X1E, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_PHYS_QNUM1_1, 0X3E, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_STORM0_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_STORM1_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_UQM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_STORM_UCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UQM_UCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_USDM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_TM_UCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_TM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_TSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_XSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_DORQ_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CDU_AG_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CDU_AG_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CDU_SM_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_CDU_SM_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(UCM, UCM_REGISTERS_UCM_CFC_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FIC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FIC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FOC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FOC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FOC2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(USEM, USEM_REGISTERS_MSG_NUM_FOC3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_ELEMENT0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_ELEMENT1, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_ELEMENT2, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_ELEMENT3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_ELEMENT4, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ARB_CYCLE_SIZE, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_0_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_1_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_2_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_3_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_4_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_5_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_6_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_7_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_8_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_9_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_10_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_11_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_12_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_13_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_14_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_15_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_16_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_17_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_18_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_TS_19_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ENABLE_IN, 0X3FFF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_ENABLE_OUT, 0X3FF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_FIC0_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_FIC1_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_PAS_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(USEM, USEM_REGISTERS_THREADS_LIST, 0XFFFF, COMMON,
INIT_HARDWARE);
+
+INIT_MEM_CLR(USEM, USEM_REGISTERS_PASSIVE_BUFFER, COMMON,
INIT_HARDWARE, 0X0,
+2048);
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION[] = {
+0x1};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1[] = {
+0x1a};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2[] = {
+0x4e};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3[] = {
+0x10};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4[] = {
+0x20};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5[] = {
+0x138};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6[] = {
+0x1f4};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7[] = {
+0x4c4b4};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8,
+0X1400, 258);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9,
+0X408, 200);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_10[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_10,
+0X400, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_11,
+0X500, 160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_12,
+0X5A0, 160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_13,
+0X640, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_14,
+0X64A, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_15,
+0X654, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_16,
+0X682, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_17,
+0X760, 36);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_18,
+0X784, 36);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_19,
+0X7A8, 32);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_20,
+0XC00, 1024);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_21,
+0XC00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_22,
+0XC40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_23[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_23,
+0XC80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_24[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_24,
+0XCC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_25[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_25,
+0XD00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_26[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_26,
+0XD40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_27,
+0XD80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_28,
+0XDC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_29[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_29,
+0XE00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30,
+0XE40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_31,
+0XE80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_32[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_32,
+0XEC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_33[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_33,
+0XF00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_34[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_34,
+0XF40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_35[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_35,
+0XF80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_36[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_36,
+0XFC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_37[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_37,
+0XC20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_38,
+0XC60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_39,
+0XCA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_40[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_40,
+0XCE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_41[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_41,
+0XD20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_42[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_42,
+0XD60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_43[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_43,
+0XDA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_44[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_44,
+0XDE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_45[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_45,
+0XE20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_46[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_46,
+0XE60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_47[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_47,
+0XEA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_48[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_48,
+0XEE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_49[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_49,
+0XF20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_50,
+0XF60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_51,
+0XFA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_52[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_52,
+0XFE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_53[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_53,
+0X900, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_54[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_54,
+0X902, 2);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_55[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_55,
+0X900, 2);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_56[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_56,
+0X902, 2);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_57[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x28, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_57,
+0X904, 8);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_58[] = {
+0x0, 0x0, 0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_58,
+0X12DA, 4);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_59[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_59,
+0X12C4, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_60[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_60,
+0X12DE, 82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_61[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_61,
+0X1330, 82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_62[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_62,
+0X1382, 12);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_63[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_63,
+0X138E, 12);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_64[] = {
+0x1000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_64, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_65[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_65, 0X4300, 16);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_66[] = {
+0x0};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_66, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_67[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_67, 0X4310, 16);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA[] = {
+0x1};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1[] = {
+0x1a};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2[] = {
+0x4e};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3[] = {
+0x10};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4[] = {
+0x20};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5[] = {
+0x1388};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6[] = {
+0x1f4};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7[] = {
+0x4c4b40};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8, 0X1400,
+258);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_10[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_10, 0X400,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_11, 0X500,
+160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_12, 0X5A0,
+160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_13,
0X640, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_14,
0X64A, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_15,
0X654, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_16,
0X682, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_17,
0X760, 36);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_18,
0X784, 36);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_19, 0X7A8,
+32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_20, 0XC00,
+1024);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_21,
0XC00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_22,
0XC40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_23[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_23,
0XC80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_24[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_24,
0XCC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_25[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_25,
0XD00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_26[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_26,
0XD40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_27,
0XD80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_28,
0XDC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_29[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_29,
0XE00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30,
0XE40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_31,
0XE80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_32[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_32,
0XEC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_33[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_33,
0XF00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_34[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_34,
0XF40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_35[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_35,
0XF80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_36[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_36,
0XFC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_37[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_37,
0XC20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_38,
0XC60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_39,
0XCA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_40[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_40,
0XCE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_41[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_41,
0XD20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_42[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_42,
0XD60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_43[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_43,
0XDA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_44[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_44,
0XDE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_45[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_45,
0XE20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_46[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_46,
0XE60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_47[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_47,
0XEA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_48[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_48,
0XEE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_49[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_49,
0XF20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_50,
0XF60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_51,
0XFA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_52[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_52,
0XFE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_53[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_53,
0X900, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_54[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_54,
0X902, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_55[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_55, 0X900,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_56[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_56, 0X902,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_57[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x28, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_57, 0X904,
+8);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_58[] = {
+0x0, 0x0, 0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_58,
0X12DA,
+4);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_59[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_59,
0X12C4,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_60[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_60, 0X12DE,
+82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_61[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_61, 0X1330,
+82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_62[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_62, 0X1382,
+12);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_63[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_63, 0X138E,
+12);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_64[] = {
+0x1000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_64, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_65[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_65, 0X4300, 16);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_66[] = {
+0x0};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_66, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_67[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_67, 0X4310, 16);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC[] = {
+0x1};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1[] = {
+0x1a};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2[] = {
+0x4e};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3[] = {
+0x10};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4[] = {
+0x20};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5[] = {
+0x7a120};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6[] = {
+0x1f4};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7[] = {
+0x1dcd6500};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8, 0X1400,
+258);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_10[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_10, 0X400,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_11, 0X500,
+160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_12, 0X5A0,
+160);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_13,
0X640, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_14,
0X64A, 10);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_15,
0X654, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_16[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_16,
0X682, 46);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_17,
0X760, 36);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_18,
0X784, 36);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_19, 0X7A8,
+32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
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0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_20, 0XC00,
+1024);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_21,
0XC00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_22,
0XC40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_23[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_23,
0XC80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_24[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_24,
0XCC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_25[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_25,
0XD00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_26[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_26,
0XD40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_27[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_27,
0XD80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_28[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_28,
0XDC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_29[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_29,
0XE00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30,
0XE40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_31[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_31,
0XE80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_32[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_32,
0XEC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_33[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_33,
0XF00, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_34[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_34,
0XF40, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_35[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_35,
0XF80, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_36[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_36,
0XFC0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_37[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_37,
0XC20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_38,
0XC60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_39,
0XCA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_40[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_40,
0XCE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_41[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_41,
0XD20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_42[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_42,
0XD60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_43[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_43,
0XDA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_44[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_44,
0XDE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_45[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_45,
0XE20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_46[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_46,
0XE60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_47[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_47,
0XEA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_48[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_48,
0XEE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_49[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_49,
0XF20, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_50,
0XF60, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_51,
0XFA0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_52[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_52,
0XFE0, 32);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_53[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_53,
0X900, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_54[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_54,
0X902, 2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_55[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_55, 0X900,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_56[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_56, 0X902,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_57[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x28, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_57, 0X904,
+8);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_58[] = {
+0x0, 0x0, 0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_58,
0X12DA,
+4);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_59[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_59,
0X12C4,
+2);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_60[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_60, 0X12DE,
+82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_61[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_61, 0X1330,
+82);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_62[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_62, 0X1382,
+12);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_63[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_USTRORM_INTMEM, USEM, USEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_USEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_63, 0X138E,
+12);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_64[] = {
+0x1000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_64, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_65[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_65, 0X4300, 16);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_66[] = {
+0x0};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_66, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_67[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(USEM, USEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_USEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_67, 0X4310, 16);
+}
+
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FIC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FIC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FOC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FOC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FOC2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(CSEM, CSEM_REGISTERS_MSG_NUM_FOC3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_ELEMENT0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_ELEMENT1, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_ELEMENT2, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_ELEMENT3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_ELEMENT4, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ARB_CYCLE_SIZE, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_0_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_1_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_2_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_3_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_4_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_5_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_6_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_7_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_8_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_9_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_10_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_11_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_12_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_13_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_14_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_15_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_16_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_17_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_18_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_TS_19_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ENABLE_IN, 0X3FFF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_ENABLE_OUT, 0X3FF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_FIC0_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_FIC1_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_PAS_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(CSEM, CSEM_REGISTERS_THREADS_LIST, 0XFFFF, COMMON,
INIT_HARDWARE);
+
+INIT_MEM_CLR(CSEM, CSEM_REGISTERS_PASSIVE_BUFFER, COMMON,
INIT_HARDWARE, 0X0,
+2048);
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x1};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_1[] = {
+0x10};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_2[] = {
+0x12};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_3[] = {
+0x30};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_4[] = {
+0xe};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_5[] = {
+0x1f4};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_5, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_6[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_6,
+0X1400, 66);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_7[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_7,
+0X408, 200);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_8[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_8,
+0X400, 2);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_9[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_9,
+0X500, 160);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_10,
+0X5A0, 160);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_11,
+0X640, 16);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_12[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_12,
+0X650, 16);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_13,
+0X660, 48);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_14[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_14,
+0X690, 48);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_15[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE,
EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_15,
+0X800, 192);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_16[] = {
+0x0, 0x0, 0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_16,
+0X8C0, 4);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_17[] = {
+0x0, 0x0, 0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_17,
+0X8C4, 4);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE,
EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_18,
+0XC1C, 128);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_19,
+0XC10, 6);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_20,
+0XC16, 6);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_21[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE,
EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_21,
+0X10A0, 4);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT0_MEMORY_INIT_HARDWARE_22,
+0X904, 48);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_23[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_HARDWARE, EVST_CSEM_FAST_MEMORY_PORT1_MEMORY_INIT_HARDWARE_23,
+0X934, 48);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_24[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_CSTRORM_INTMEM, CSEM, CSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_HARDWARE,
EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_24,
+0X970, 576);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_25[] = {
+0x13fffff};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_25, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_26[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_26, 0X4300, 16);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_27[] = {
+0x0};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_27, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_28[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(CSEM, CSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_HARDWARE,
+EVST_CSEM_FAST_MEMORY_COMMON_MEMORY_INIT_HARDWARE_28, 0X4310, 16);
+}
+
+INIT_REG_WR(DQ, DORQ_REGISTERS_MODE_ACT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_NORM_CID_OFST, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_OUTST_REQ, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_DPM_CID_ADDR, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_RSP_INIT_CRD, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_NORM_CMHEAD_TX, 0X90, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_CMHEAD_RX, 0X90, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_SHRT_CMHEAD, 0X800090, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_ERR_CMHEAD, 0X8140000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_AGG_CMD0, 0X8A, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_AGG_CMD1, 0X80, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_AGG_CMD2, 0X90, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_AGG_CMD3, 0X80, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_SHRT_ACT_CNT, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_DQ_FIFO_FULL_TH, 0X7D0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_DQ_FIFO_AFULL_TH, 0X76C, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_REGN, 0X7C1004, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DQ, DORQ_REGISTERS_IF_EN, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CLIN_PRIOR0_CLIENT, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CLIN_PRIOR1_CLIENT, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_LIN_SETCLR_FIFO_ALFULL_THR, 0X1C, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CFC_AC_CRDCNT_VAL, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CFC_CLD_CRDCNT_VAL, 0X1, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CLOUT_CRDCNT0_VAL, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CLOUT_CRDCNT1_VAL, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CLOUT_CRDCNT2_VAL, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EXP_CRDCNT_VAL, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_PCIARB_CRDCNT_VAL, 0X2, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_TIMER_TICK_SIZE, 0X9C, COMMON,
INIT_EMULATION);
+INIT_REG_WR(TIMERS, TM_REGISTERS_TIMER_TICK_SIZE, 0X9C4, COMMON,
INIT_FPGA);
+INIT_REG_WR(TIMERS, TM_REGISTERS_TIMER_TICK_SIZE, 0X3D090, COMMON,
INIT_ASIC);
+
+{
+static const u32 EVST_TIMERS_LIN0_PHY_ADDR_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0};
+INIT_MEM_WB(TIMERS, TM_REGISTERS_LIN0_PHY_ADDR, PORT0, INIT_HARDWARE,
+EVST_TIMERS_LIN0_PHY_ADDR_PORT0_MEMORY_INIT_HARDWARE, 0X0, 2);
+}
+
+
+{
+static const u32 EVST_TIMERS_LIN1_PHY_ADDR_PORT1_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0};
+INIT_MEM_WB(TIMERS, TM_REGISTERS_LIN1_PHY_ADDR, PORT1, INIT_HARDWARE,
+EVST_TIMERS_LIN1_PHY_ADDR_PORT1_MEMORY_INIT_HARDWARE, 0X0, 2);
+}
+
+INIT_REG_WR(TIMERS, TM_REGISTERS_CL0_CONT_REGION, 0X8, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CL1_CONT_REGION, 0XC, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_CL2_CONT_REGION, 0X10, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_TM_CONTEXT_REGION, 0X20, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_TIMERS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_LINEAR0_TIMER, 0X1, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_LINEAR1_TIMER, 0X1, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_REAL_TIME_CNT, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_CL0_INPUT, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_CL1_INPUT, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(TIMERS, TM_REGISTERS_EN_CL2_INPUT, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CFC_RSP_START_ADDR, 0XA14, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CMP_COUNTER_START_ADDR, 0XA00, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_Q_COUNTER_START_ADDR, 0XA04, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CMP_COUNTER_MAX0, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CMP_COUNTER_MAX1, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CMP_COUNTER_MAX2, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_CMP_COUNTER_MAX3, 0XFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_0, 0X20, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_1, 0X20, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_EVENT_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_12, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_13, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_14, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_15, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_16, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_17, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_18, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_19, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_20, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_21, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_22, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_23, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_24, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_25, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_26, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_27, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_28, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_29, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_30, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_T_31, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_0, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_FIC_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_0, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_1, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_2, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_3, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_4, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_5, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_6, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_7, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_8, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_9, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_10, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_11, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_12, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_13, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_14, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_15, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_16, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_17, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_18, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_19, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_20, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_21, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_23, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_24, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_25, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_26, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_27, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_28, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_29, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_30, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_AGG_INT_MODE_31, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_ENABLE_IN1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_ENABLE_IN2, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_ENABLE_OUT1, 0X7FFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_ENABLE_OUT2, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q0_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q1_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q3_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q4_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q5_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q6_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q7_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q8_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q9_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q10_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_Q11_CMD, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_PKT_END_MSG, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_RD(XSDM, XSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_TIMER_TICK, 0X1, COMMON, INIT_EMULATION);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_TIMER_TICK, 0XA, COMMON, INIT_FPGA);
+INIT_REG_WR(XSDM, XSDM_REGISTERS_TIMER_TICK, 0X3E8, COMMON, INIT_ASIC);
+INIT_REG_WR(QM, QM_REGISTERS_ACTCTRINITVAL_0, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ACTCTRINITVAL_1, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ACTCTRINITVAL_2, 0XA, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ACTCTRINITVAL_3, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_PCIREQAT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_0, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_1, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_2, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_3, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_4, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_5, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_6, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINITCRD_7, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_OUTLDREQ, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CTXREG_0, 0X7C, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CTXREG_1, 0X3D, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CTXREG_2, 0X3F, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CTXREG_3, 0X9C, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ENSEC, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_0, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_1, 0X1808004, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_12, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_2, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_13, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_14, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_15, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_16, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_3, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_17, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_18, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_19, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_20, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_4, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_21, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_22, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_23, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_24, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_5, 0X1080120, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_25, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_26, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_27, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_28, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_6, 0X20010810, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_29, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_30, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_31, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_32, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_7, 0X1010120, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_33, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_34, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_35, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_36, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_8, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_37, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_38, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_39, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_40, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_9, 0X1808004, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_41, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_42, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_43, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_44, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_10, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_45, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_46, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_47, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_48, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_11, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_49, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_50, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_51, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_52, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_12, 0X1010101, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_53, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_54, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_55, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_56, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_13, 0X1080120, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_57, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_58, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_59, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_60, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_14, 0X20010810, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_61, 0X8, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_62, 0X6, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_QVOQIDX_63, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_WRRWEIGHTS_15, 0X1010120, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_0_LSB, 0X1FFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_0_MSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_1_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_1_MSB, 0X1FFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_2_LSB, 0X800000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_2_MSB, 0X800000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_3_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_3_MSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_4_LSB, 0X600000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_4_MSB, 0X600000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_5_LSB, 0X1F000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_5_MSB, 0X1F000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_6_LSB, 0X40000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_6_MSB, 0X40000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_7_LSB, 0X80000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_7_MSB, 0X80000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_8_LSB, 0X20000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_8_MSB, 0X20000000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_9_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_9_MSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_10_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_10_MSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_11_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQQMASK_11_MSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_1, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQPORT_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_0, 0XC08, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_1, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_2, 0X100, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_3, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_4, 0X17, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_5, 0X80, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_6, 0X200, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTVOQMASK_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_HWAEMPTYMASK_LSB, 0XFFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_HWAEMPTYMASK_MSB, 0XFFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ENBYPVOQMASK, 0X13, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQCREDITAFULLTHR, 0X13F, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_0, 0X140, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_1, 0X140, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_4, 0XC0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_VOQINITCREDIT_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_0, 0X48, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_1, 0X48, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_4, 0X48, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_8, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_9, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_10, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_TASKCRDCOST_11, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_BYTECRDINITVAL, 0X8000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_BYTECRDCOST, 0X2400, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_BYTECREDITAFULLTHR, 0X7FFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ENBYTECRD_LSB, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_ENBYTECRD_MSB, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_BYTECRDPORT_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_BYTECRDPORT_MSB, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_FUNCNUMSEL_LSB, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_FUNCNUMSEL_MSB, 0XFFFFFFFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(QM, QM_REGISTERS_CMINTEN, 0XFF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P0, 0X1, PORT0, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P1, 0X1, PORT1, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P4, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_MAC_IF0_ENABLE, 0X1, PORT0, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_MAC_IF1_ENABLE, 0X1, PORT1, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_MAC_LB_ENABLE, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_IF_ENABLE_REG, 0X7FFF, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P1, 0X0, PORT1, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT_P4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_INIT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P1, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(PBF, PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P4, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XX_OVFL_EVNT_ID, 0X32, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_XCM_HDR_P, 0X3150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_XCM_HDR_S, 0X3150020, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_TM_XCM_HDR, 0X1000030, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_ERR_XCM_HDR, 0X8100000, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_ERR_EVNT_ID, 0X33, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_EXPR_EVNT_ID, 0X30, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_STOP_EVNT_ID, 0X31, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_STORM_WEIGHT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_TSEM_WEIGHT, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CSEM_WEIGHT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_USEM_WEIGHT, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_PBF_WEIGHT, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_NIG1_WEIGHT, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CP_WEIGHT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XSDM_WEIGHT, 0X5, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_P_WEIGHT, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_XQM_USE_Q, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_BYP_ACT_UPD, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_0, 0XC8, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_1, 0XC8, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_0, 0X2, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_1, 0X2, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_UNA_GT_NXT_Q, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_AUX1_Q, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_AUX_CNT_FLG_Q_19, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD00, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD01, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD10, 0X0, PORT0,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD11, 0X0, PORT1,
+INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_CMD00, 0X2, PORT0, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_CMD01, 0X2, PORT1, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_CMD10, 0X2, PORT0, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_CMD11, 0X2, PORT1, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_UPD_VAL00, 0XFF, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_UPD_VAL01, 0XFF, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_UPD_VAL10, 0XFF, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_WU_DA_CNT_UPD_VAL11, 0XFF, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GR_ARB_TYPE, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GR_LD0_PR, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_GR_LD1_PR, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CFC_INIT_CRD, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_FIC0_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_FIC1_INIT_CRD, 0X40, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_TM_INIT_CRD, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_INIT_CRD, 0X20, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XX_INIT_CRD, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XX_MSG_NUM, 0X1F, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_XCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_MEM_WR(XCM, XCM_REGISTERS_XX_TABLE, COMMON, INIT_HARDWARE,
+EVST_XCM_XX_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 18);
+}
+
+
+{
+static const u32 EVST_XCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+0x1000, 0x2080, 0x3100, 0x4180, 0x5200, 0x6280, 0x7300, 0x8380, 0x9400,
0xa480,
+0xb500, 0xc580, 0xd600, 0xe680, 0xf700, 0x10780,
+0x11800, 0x12880, 0x13900, 0x14980, 0x15a00, 0x16a80, 0x17b00, 0x18b80,
+0x19c00, 0x1ac80, 0x1bd00, 0x1cd80, 0x1de00, 0x1ee80, 0x1ff00};
+INIT_MEM_WR(XCM, XCM_REGISTERS_XX_DESCR_TABLE, COMMON, INIT_HARDWARE,
+EVST_XCM_XX_DESCR_TABLE_COMMON_MEMORY_INIT_HARDWARE, 0X0, 31);
+}
+
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_0, 0XF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_1, 0X7, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_2, 0XB, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_3, 0XE, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_4, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_5, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_6, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_N_SM_CTX_LD_7, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_REG0_SZ, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_STORM0_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_STORM1_IFEN, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_XQM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_STORM_XCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XQM_XCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XSDM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_TM_XCM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_TM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_TSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CSEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_USEM_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_DORQ_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_PBF_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_NIG0_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_NIG1_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CDU_AG_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CDU_AG_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CDU_SM_WR_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_CDU_SM_RD_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XCM, XCM_REGISTERS_XCM_CFC_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FIC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FIC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FOC0, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FOC1, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FOC2, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_RD(XSEM, XSEM_REGISTERS_MSG_NUM_FOC3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_ELEMENT0, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_ELEMENT1, 0X2, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_ELEMENT2, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_ELEMENT3, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_ELEMENT4, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ARB_CYCLE_SIZE, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_0_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_1_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_2_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_3_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_4_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_5_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_6_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_7_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_8_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_9_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_10_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_11_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_12_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_13_AS, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_14_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_15_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_16_AS, 0X4, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_17_AS, 0X3, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_18_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_TS_19_AS, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ENABLE_IN, 0X3FFF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_ENABLE_OUT, 0X3FF, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_FIC0_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_FIC1_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_PAS_DISABLE, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(XSEM, XSEM_REGISTERS_THREADS_LIST, 0XFFFF, COMMON,
INIT_HARDWARE);
+
+INIT_MEM_CLR(XSEM, XSEM_REGISTERS_PASSIVE_BUFFER, COMMON,
INIT_HARDWARE, 0X0,
+2048);
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION[] = {
+0x1};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2[] = {
+0x18};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3[] = {
+0xc};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4[] = {
+0x66};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5[] = {
+0x138};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6[] = {
+0x1f4};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_7, 0X60D0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8[] = {
+0x4c4b4};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_8, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_9,
+0X1576, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_10,
+0X1400, 72);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_11,
+0X408, 200);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_12[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_12,
+0X400, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_13,
+0X144A, 146);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_14[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_14,
+0X14DE, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_15[] = {
+0x0, 0x10001};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_15,
+0X14E0, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_16[] = {
+0x150004, 0xcccccccd, 0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_16,
+0X150A, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_17,
+0X500, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_18,
+0X50A, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_19,
+0X514, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_20,
+0X51A, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_21,
+0X14E2, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_22,
+0X14F0, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_23[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_23,
+0X540, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_24[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_24,
+0X541, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_25[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_25,
+0X542, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_26[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_26,
+0X543, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_27[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_27,
+0X546, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_28[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_28,
+0XC08, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_29[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_29,
+0XC0A, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_30,
+0XC0C, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_31[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_31,
+0XC0E, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_32[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_32,
+0XC00, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_33[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_33,
+0XC02, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_34[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_34,
+0XC04, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_35[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_35,
+0XC06, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_36[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_36,
+0XC10, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_37[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_37,
+0XC11, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_38,
+0XC12, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_39,
+0XC20, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_40[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_40,
+0XC2E, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_41[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_41,
+0XC2F, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_42[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_42,
+0X60C, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_43[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_43,
+0X60E, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_44[] = {
+0xcccc0201, 0xcccccccc};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_44,
+0X608, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_45[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_45,
+0X12B0, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_46[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_46,
+0X12B2, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_47[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_47,
+0X12B4, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_48[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_48,
+0X12B6, 2);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_49[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_49,
+0X12C2, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_50,
+0X12C6, 66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_51,
+0X1308, 66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_52[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_EMULATION_52,
+0X134A, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_53[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_EMULATION,
EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_EMULATION_53,
+0X134E, 4);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_54[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_54, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_55[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_55, 0X4300, 16);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_56[] = {
+0x1000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_56, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_57[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_57, 0X4310, 8);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_58[] = {
+0x2000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_58, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_59[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_59, 0X4318, 8);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_60[] = {
+0x3000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_60, 0X4200, 1);
+}
+
+
+{
+static const u32
EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_61[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_EMULATION,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_EMULATION_61, 0X4320, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA[] = {
+0x1};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2[] = {
+0x18};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3[] = {
+0xc};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4[] = {
+0x66};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5[] = {
+0x1388};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6[] = {
+0x1f4};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7[] = {
+0x5};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_7, 0X60D0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8[] = {
+0x4c4b40};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_8, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_9, 0X1576,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_10,
0X1400,
+72);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_11, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_12[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_12, 0X400,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_13,
0X144A,
+146);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_14[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_14,
0X14DE,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_15[] = {
+0x0, 0x10001};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_15,
0X14E0,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_16[] = {
+0x150004, 0xcccccccd, 0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_16,
0X150A,
+4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_17,
0X500, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_18,
0X50A, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_19,
0X514, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_20,
0X51A, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_21, 0X14E2,
+14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_22, 0X14F0,
+14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_23[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_23,
0X540, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_24[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_24,
0X541, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_25[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_25,
0X542, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_26[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_26,
0X543, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_27[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_27, 0X546,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_28[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_28,
0XC08, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_29[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_29,
0XC0A, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_30,
0XC0C, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_31[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_31,
0XC0E, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_32[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_32,
0XC00, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_33[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_33,
0XC02, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_34[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_34,
0XC04, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_35[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_35,
0XC06, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_36[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_36,
0XC10, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_37[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_37,
0XC11, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_38,
0XC12, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_39,
0XC20, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_40[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_40,
0XC2E, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_41[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_41,
0XC2F, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_42[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_42, 0X60C,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_43[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_43, 0X60E,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_44[] = {
+0xcccc0201, 0xcccccccc};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_44, 0X608,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_45[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_45,
0X12B0,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_46[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_46,
0X12B2, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_47[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_47,
0X12B4, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_48[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_48,
0X12B6,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_49[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_FPGA, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_49,
0X12C2,
+4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_50, 0X12C6,
+66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_51, 0X1308,
+66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_52[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_FPGA_52,
0X134A, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_53[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_FPGA, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_FPGA_53,
0X134E, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_54[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_54, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_55[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_55, 0X4300, 16);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_56[] = {
+0x1000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_56, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_57[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_57, 0X4310, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_58[] = {
+0x2000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_58, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_59[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_59, 0X4318, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_60[] = {
+0x3000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_60, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_61[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_FPGA,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_FPGA_61, 0X4320, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC[] = {
+0x1};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC, 0X62F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_1, 0X6000, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2[] = {
+0x18};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_2, 0X6010, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3[] = {
+0xc};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_3, 0X6020, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4[] = {
+0x66};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_4, 0X6030, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5[] = {
+0x7a120};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_5, 0X60C0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6[] = {
+0x1f4};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_6, 0X60F0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7[] = {
+0x1f4};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_7, 0X60D0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8[] = {
+0x1dcd6500};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_8, 0X60E0, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_9, 0X1576,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_10[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_10,
0X1400,
+72);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_11[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_11, 0X408,
+200);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_12[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_12, 0X400,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_13[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_13,
0X144A,
+146);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_14[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_14,
0X14DE,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_15[] = {
+0x0, 0x10001};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_15,
0X14E0,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_16[] = {
+0x150004, 0xcccccccd, 0xffffffff, 0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_16,
0X150A,
+4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_17[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_17,
0X500, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_18[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_18,
0X50A, 10);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_19[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_19,
0X514, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_20[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_20,
0X51A, 6);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_21[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_21, 0X14E2,
+14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_22[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_22, 0X14F0,
+14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_23[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_23,
0X540, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_24[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_24,
0X541, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_25[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_25,
0X542, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_26[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_26,
0X543, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_27[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_27, 0X546,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_28[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_28,
0XC08, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_29[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_29,
0XC0A, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_30,
0XC0C, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_31[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_31,
0XC0E, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_32[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_32,
0XC00, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_33[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_33,
0XC02, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_34[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_34,
0XC04, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_35[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_35,
0XC06, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_36[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_36,
0XC10, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_37[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_37,
0XC11, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_38[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_38,
0XC12, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_39[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffff,
+0xffffffff};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_39,
0XC20, 14);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_40[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_40,
0XC2E, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_41[] = {
+0x1};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_41,
0XC2F, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_42[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_42, 0X60C,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_43[] = {
+0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_43, 0X60E,
+1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_44[] = {
+0xcccc0201, 0xcccccccc};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_44, 0X608,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_45[] = {
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_45,
0X12B0,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_46[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_46,
0X12B2, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_47[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_47,
0X12B4, 2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_48[] = {
+0x100000, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_48,
0X12B6,
+2);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_49[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+COMMON, INIT_ASIC, EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_49,
0X12C2,
+4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_50[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_50, 0X12C6,
+66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_51[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_51, 0X1308,
+66);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_52[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT0, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT0_MEMORY_INIT_ASIC_52,
0X134A, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_53[] = {
+0x0, 0x0, 0x0, 0x0};
+INIT_INTERNAL0_MEM_WR(BAR_XSTRORM_INTMEM, XSEM, XSEM_REGISTERS_FAST_MEMORY,
+PORT1, INIT_ASIC, EVST_XSEM_FAST_MEMORY_PORT1_MEMORY_INIT_ASIC_53,
0X134E, 4);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_54[] = {
+0x0};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_54, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_55[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000, 0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_55, 0X4300, 16);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_56[] = {
+0x1000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_56, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_57[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_57, 0X4310, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_58[] = {
+0x2000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_58, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_59[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_59, 0X4318, 8);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_60[] = {
+0x3000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_60, 0X4200, 1);
+}
+
+
+{
+static const u32 EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_61[] = {
+0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
+0x40000000, 0x40000000};
+INIT_MEM_WR(XSEM, XSEM_REGISTERS_FAST_MEMORY, COMMON, INIT_ASIC,
+EVST_XSEM_FAST_MEMORY_COMMON_MEMORY_INIT_ASIC_61, 0X4320, 8);
+}
+
+INIT_REG_WR(DMAE, DMAE_REGISTERS_CRC16C_INIT, 0X0, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DMAE, DMAE_REGISTERS_CRC16T10_INIT, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DMAE, DMAE_REGISTERS_PXP_REQ_INIT_CRD, 0X2, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(DMAE, DMAE_REGISTERS_PCI_IFEN, 0X1, COMMON, INIT_HARDWARE);
+INIT_REG_WR(DMAE, DMAE_REGISTERS_GRC_IFEN, 0X1, COMMON, INIT_HARDWARE);
+
+{
+static const u32 EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE[] = {
+0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x2000};
+INIT_MEM_IND(PXP, PXP_REGISTERS_HST_INBOUND_INT, COMMON, INIT_HARDWARE,
+EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE, 0X100, 5);
+}
+
+
+{
+static const u32
EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE_1[] = {
+0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x2000};
+INIT_MEM_IND(PXP, PXP_REGISTERS_HST_INBOUND_INT, COMMON, INIT_HARDWARE,
+EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE_1, 0X108, 5);
+}
+
+
+{
+static const u32
EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE_2[] = {
+0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x2000};
+INIT_MEM_IND(PXP, PXP_REGISTERS_HST_INBOUND_INT, COMMON, INIT_HARDWARE,
+EVST_PXP_HST_INBOUND_INT_COMMON_MEMORY_INIT_HARDWARE_2, 0X0, 5);
+}
+
+INIT_REG_WR(HC, HC_REGISTERS_CONFIG_0, 0X1080, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_CONFIG_1, 0X1080, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_UC_RAM_ADDR_0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_XT_RAM_ADDR_0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_UC_RAM_ADDR_1, 0X0, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_XT_RAM_ADDR_1, 0X0, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_ATTN_NUM_P0, 0X10, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_ATTN_NUM_P1, 0X10, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_LEADING_EDGE_0, 0XFFFF, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_TRAILING_EDGE_0, 0XFFFF, PORT0,
INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_LEADING_EDGE_1, 0XFFFF, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_TRAILING_EDGE_1, 0XFFFF, PORT1,
INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_AGG_INT_0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_AGG_INT_1, 0X0, PORT1, INIT_HARDWARE);
+
+{
+static const u32 EVST_HC_ATTN_IDX_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_ATTN_IDX, PORT0, INIT_HARDWARE,
+EVST_HC_ATTN_IDX_PORT0_MEMORY_INIT_HARDWARE, 0X0, 1);
+}
+
+
+{
+static const u32 EVST_HC_ATTN_IDX_PORT1_MEMORY_INIT_HARDWARE_1[] = {
+0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_ATTN_IDX, PORT1, INIT_HARDWARE,
+EVST_HC_ATTN_IDX_PORT1_MEMORY_INIT_HARDWARE_1, 0X1, 1);
+}
+
+
+{
+static const u32 EVST_HC_ATTN_BIT_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_ATTN_BIT, PORT0, INIT_HARDWARE,
+EVST_HC_ATTN_BIT_PORT0_MEMORY_INIT_HARDWARE, 0X0, 2);
+}
+
+
+{
+static const u32 EVST_HC_ATTN_BIT_PORT1_MEMORY_INIT_HARDWARE_1[] = {
+0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_ATTN_BIT, PORT1, INIT_HARDWARE,
+EVST_HC_ATTN_BIT_PORT1_MEMORY_INIT_HARDWARE_1, 0X2, 2);
+}
+
+INIT_REG_WR(HC, HC_REGISTERS_VQID_0, 0X2B5, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_VQID_1, 0X2B5, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_PCI_CONFIG_0, 0X0, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_PCI_CONFIG_1, 0X0, PORT1, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_USTORM_ADDR_FOR_COALESCE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_CSTORM_ADDR_FOR_COALESCE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_XSTORM_ADDR_FOR_COALESCE, 0X0, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_TSTORM_ADDR_FOR_COALESCE, 0X0, COMMON,
+INIT_HARDWARE);
+
+{
+static const u32 EVST_HC_P0_PROD_CONS_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_P0_PROD_CONS, PORT0, INIT_HARDWARE,
+EVST_HC_P0_PROD_CONS_PORT0_MEMORY_INIT_HARDWARE, 0X0, 74);
+}
+
+/* MANUAL CHANGE, Gertner */
+{
+static const u32 EVST_HC_PBA_COMMAND_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_PBA_COMMAND, PORT0, INIT_HARDWARE,
+EVST_HC_PBA_COMMAND_PORT0_MEMORY_INIT_HARDWARE, 0X0, 2);
+}
+
+
+{
+static const u32 EVST_HC_P1_PROD_CONS_PORT1_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_P1_PROD_CONS, PORT1, INIT_HARDWARE,
+EVST_HC_P1_PROD_CONS_PORT1_MEMORY_INIT_HARDWARE, 0X0, 74);
+}
+
+/* MANUAL CHANGE, Gertner */
+{
+static const u32 EVST_HC_PBA_COMMAND_PORT1_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_PBA_COMMAND, PORT1, INIT_HARDWARE,
+EVST_HC_PBA_COMMAND_PORT1_MEMORY_INIT_HARDWARE, 0X2, 2);
+}
+
+
+{
+static const u32 EVST_HC_INT_MASK_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x1ffff};
+INIT_MEM_WR(HC, HC_REGISTERS_INT_MASK, PORT0, INIT_HARDWARE,
+EVST_HC_INT_MASK_PORT0_MEMORY_INIT_HARDWARE, 0X0, 1);
+}
+
+
+{
+static const u32 EVST_HC_INT_MASK_PORT1_MEMORY_INIT_HARDWARE_1[] = {
+0x1ffff};
+INIT_MEM_WR(HC, HC_REGISTERS_INT_MASK, PORT1, INIT_HARDWARE,
+EVST_HC_INT_MASK_PORT1_MEMORY_INIT_HARDWARE_1, 0X1, 1);
+}
+
+INIT_REG_WR(HC, HC_REGISTERS_CONFIG_0, 0X1A82, PORT0, INIT_HARDWARE);
+INIT_REG_WR(HC, HC_REGISTERS_CONFIG_1, 0X1A82, PORT1, INIT_HARDWARE);
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT0, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE, 0X0, 36);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_1[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT1, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_1, 0X24, 36);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_2[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT0, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_2, 0X48, 74);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_3[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT1, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_3, 0X92, 74);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_4[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT0, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_4, 0XDC, 74);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_5[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT1, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_5, 0X126, 74);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_6[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT0, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT0_MEMORY_INIT_HARDWARE_6, 0X170, 74);
+}
+
+
+{
+static const u32
EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_7[] = {
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0,
+0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+INIT_MEM_WR(HC, HC_REGISTERS_STATISTIC_COUNTERS, PORT1, INIT_HARDWARE,
+EVST_HC_STATISTIC_COUNTERS_PORT1_MEMORY_INIT_HARDWARE_7, 0X1BA, 74);
+}
+
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_CONTROL0, 0XE38324, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_CONTROL1, 0X3C10, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_0, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_1, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_2, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_3, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_4, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_5, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_6, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_TSDM_7, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_1, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_2, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_3, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_4, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_5, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_6, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_7, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_2, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_3, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_4, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_5, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_6, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_7, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_0, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_1, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_2, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_3, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_4, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_5, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_6, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_CSDM_7, 0XFFFFFFFF, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_0, 0XFFFF5330, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_XSDM_1, 0XFFFF5348, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PGL_INT_USDM_0, 0XF0003000, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ6, 0X8, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ9, 0X8, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ10, 0X8, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ11, 0X2, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ17, 0X4, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ18, 0X5, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ19, 0X4, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_MAX_BLKS_VQ22, 0X0, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RD_START_INIT, 0X1, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD0, 0X40, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD1, 0X1808, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD2, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD3, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD4, 0X40, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD5, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD6, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD7, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD8, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD9, 0X10003, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD10, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD11, 0X803, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD12, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD13, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD14, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD15, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD16, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD17, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD18, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD19, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD20, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD22, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD23, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD24, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD25, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD26, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_ADD27, 0X3, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_ADD28, 0X2403, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_WR_ADD29, 0X2F, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_WR_ADD30, 0X9, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND0, 0X19, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB1, 0X184, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB2, 0X183, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB3, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND4, 0X19, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND5, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB6, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB7, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB8, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB9, 0XC86, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB10, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB11, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND12, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND13, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND14, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND15, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND16, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND17, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND18, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND19, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND20, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND22, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND23, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND24, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND25, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND26, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_RD_UBOUND27, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_UB28, 0X306, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_WR_UBOUND29, 0X13, COMMON,
+INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_BW_WR_UBOUND30, 0X6, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_L1, 0X1004, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_L2, 0X1004, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_RD, 0X106440, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_PSWRQ_BW_WR, 0X106440, COMMON,
INIT_HARDWARE);
+INIT_REG_WR(PXP2, PXP2_REGISTERS_RQ_RBC_DONE, 0X1, COMMON, INIT_HARDWARE);
--
1.4.2
^ permalink raw reply related
* [BNX2X][PATCH 8/8] bnx2x_asm.h
From: Eliezer Tamir @ 2007-10-07 16:24 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
This is the microcode for the BCM57710 chip.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x_asm.h | 4900
+++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 4900 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x_asm.h b/drivers/net/bnx2x_asm.h
new file mode 100644
index 0000000..5604c2d
--- /dev/null
+++ b/drivers/net/bnx2x_asm.h
@@ -0,0 +1,4900 @@
+/* bnx2x_asm.h: Broadcom Everest network driver
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, except as noted below.
+ *
+ * This file contains asm code derived from proprietary unpublished
+ * source code, Copyright (c) 2007 Broadcom Corporation.
+ *
+ * Permission is hereby granted for the distribution of this firmware data
+ * in hexadecimal or equivalent format, provided this copyright notice is
+ * accompanying it.
+ */
+
+{
+static const u32 EVST_TSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x4c5, 0x53a, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x249, 0x24a, 0x24b, 0x286, 0xe3, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x1025, 0x7ff8,
+ 0x7ff8, 0xd22, 0xd50, 0xc0f, 0xe1e, 0x7ff8,
+ 0x7ff8, 0x1083, 0xe87, 0xe47, 0x7ff8, 0xec8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x153e, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x12c0, 0x7ff8, 0x7ff8, 0x153e, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x153e, 0x7ff8, 0x7ff8, 0x7ff8, 0x1336, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x153e, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x18b1, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x18b1, 0x7ff8, 0x1632, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8};
+ INIT_MEM_WR(TSEM, TSEM_REGISTERS_INT_TABLE, COMMON,
+ INIT_HARDWARE, EVST_TSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE,
+ 0X0, 256);
+}
+
+
+{
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0[] = {
+ 0x00088b1f, 0x00000000, 0x7ded0300, 0xc594780b, 0xbb7cf0b9, 0xdd925edf,
+ 0x212b9b24, 0x1024d840, 0xb72e0351, 0x09b08a80, 0xbad2a310, 0xa8b4445c,
+ 0xc810840b, 0x6c1ea455, 0x5722c9ed, 0x52836d2f, 0x0dd20f41, 0xa723d2a2,
+ 0xd06c1a0d, 0xc445cba8, 0x3968dad6, 0xaffa2b16, 0x4810a88a, 0x73c1eb04,
+ 0xf7dff96c, 0xefdd999d, 0x209bb2fb, 0x7d39e7da, 0x769f1ffe, 0xdedcdf32,
+ 0xf333ef79, 0x6ccaacce, 0xb1893acc, 0xd20ff873, 0xd8c61477, 0x9f5a68d8,
+ 0xc618e90c, 0x8399776a, 0x3631e4f7, 0x34259779, 0xcdf20329, 0x7906d04a,
+ 0x54094bd3, 0xcf336a7e, 0x7e3b9bd7, 0xb3942576, 0x13d99adf, 0x8961b090,
+ 0xd8c59626, 0xffe33b31, 0x98be40c6, 0x9e04cab1, 0x73de6dad, 0x55fa832b,
+ 0x0096366d, 0x9ab58fed, 0xfa5f98bd, 0x00641284, 0xb5eeed43, 0x7fe81cd6,
+ 0x49695051, 0x09fe4370, 0x8be508f8, 0xac41cd5b, 0x91dc95df, 0x763273e5,
+ 0xdcced1bc, 0x3fef8456, 0x8c45c2b3, 0x2cee092d, 0x4b7a81cb, 0x131e2876,
+ 0xb364b38c, 0x06349a12, 0x33412bbf, 0xddbd5174, 0x38c3dcc1, 0x8d18e70c,
+ 0xfa58f34b, 0xfd0b8c18, 0xeac9b532, 0xd6f1c24b, 0x5149dd5b, 0x746f1cfc,
+ 0x5f3238d1, 0x07182bfb, 0x5afdd5da, 0xeb14e0f1, 0x02dfcc4c, 0x9dda9fe3,
+ 0x2771e730, 0xb5856fce, 0x8f3b4930, 0x3ce1cf79, 0xad9b0496, 0xab844e65,
+ 0x14595ad9, 0x7b7aafed, 0x4dae1eba, 0x9afcfd05, 0xbc7a6372, 0x61773191,
+ 0x3184bf34, 0xe1138b6f, 0x0fa75a0f, 0x9d7f7e8f, 0xab3d12a5, 0xdb999bb7,
+ 0xb19fed1e, 0x8c996300, 0x84279999, 0x49ed6578, 0x4edd2d1e, 0x5b74f4bb,
+ 0xc6da2a9a, 0x82e7e781, 0x9e05eb0e, 0x41f08a7e, 0xad75e29a, 0x29fe6150,
+ 0xe94b9853, 0x0b7afda5, 0x6312d39b, 0x332237be, 0x667efc00, 0x98eb7822,
+ 0xbb4c66ff, 0x00550d4c, 0x650bfc3c, 0x6bbe60fb, 0x7afede15, 0x6bfaa6e6,
+ 0x48bd5907, 0x14d7f5d7, 0x13ce6e3f, 0x7cc0c973, 0x41f793e5, 0x5ee56997,
+ 0x1155f886, 0x1858456f, 0x3ca1980e, 0xa8ea4769, 0xfc5adcfb, 0x7f625695,
+ 0x3a4c63c9, 0x2426b8fa, 0x5369f2ea, 0x75f80cd2, 0x2a5d8eba, 0xcda700f2,
+ 0x2d423dd4, 0xd724ac60, 0x6776fc4e, 0xe6e495ae, 0xae1c89ce, 0xc19d733b,
+ 0xc7efe400, 0xde439706, 0x15ccbfea, 0xb2301f03, 0xea636589, 0x3df1b137,
+ 0x1e21d7cb, 0x074a0f81, 0x01f85d7f, 0xeea6f5a4, 0x974854c2, 0x9c01252b,
+ 0x23c46ac7, 0x6b330ea4, 0x6c3b79c0, 0x6eb4f08c, 0x01e3f168, 0xcdee9e0d,
+ 0x45e53c03, 0x02d7bdfb, 0x6d9073df, 0x275e02ca, 0x59e79be1, 0xfd0bd799,
+ 0x6203cdac, 0x6774015f, 0x10c0a165, 0xceef2fe8, 0xddafc46c, 0x85a1720a,
+ 0x14f00ac7, 0x220f3c11, 0xc0e31b1c, 0xaf1c2f63, 0xbf212783, 0x024f074a,
+ 0xb1e3870c, 0x7806f5c0, 0xd8f017ae, 0x764bff29, 0xcf63c13d, 0xacf04e5f,
+ 0x1d2ab2b3, 0x7811893c, 0xbf1c21b6, 0x03d67c12, 0xe857853f, 0x44bf93f1,
+ 0xc4ab1f8f, 0x3c031ccf, 0x893c0473, 0x364eef04, 0xff27e387, 0x363f1c47,
+ 0x4f0b4718, 0xcf5e8472, 0xc42f3c21, 0xd17ec781, 0x0a7e3d04, 0xb1f8f46a,
+ 0x19e67849, 0xe02799e0, 0xfb3c1271, 0x9f8e3cd8, 0x1e09bb82, 0xe3c1ad9b,
+ 0xe0db2282, 0xca2086c4, 0xebfe1b85, 0x1810e907, 0x45a41c77, 0x67f58c69,
+ 0x9f2c87ec, 0xd133bae0, 0xffd6117f, 0xd5f81132, 0x152bd519, 0x7f59e63b,
+ 0x7058550a, 0xa3fa828d, 0x4546c84e, 0x0cb7d71b, 0x8050f1f4, 0x99db54f7,
+ 0xf805df2f, 0xf48db62b, 0xcf24dd98, 0x142feb0c, 0x7337ab53, 0xcbe630fc,
+ 0xfa849e9d, 0x633b97cd, 0x51791538, 0x04622d4f, 0x58390f63, 0x163964d8,
+ 0xa2e7c8d6, 0xe2fcfa4d, 0xe12f3ea0, 0x013fc12e, 0x8f40c7ef, 0x1fafd031,
+ 0xf4c31e82, 0x0dbb0b13, 0xd051cded, 0x95aacc73, 0xbebc15c7, 0x6c70e9ca,
+ 0xf8e48393, 0x5bb7f5cb, 0xe1c20159, 0xc66ae400, 0x4543b009, 0x62d9bf30,
+ 0x212ca77e, 0xc431e90b, 0x3bea3173, 0x585b9f3e, 0xf4367570, 0x9d81e0b3,
+ 0xeccba416, 0x2c69daf6, 0xae91e719, 0x07798fef, 0xb01f4898, 0x07d02601,
+ 0x5bd75a73, 0xc6e64006, 0xc30f9639, 0xf9377a9a, 0x541ff9f5, 0x2ca7f3e9,
+ 0xed098b41, 0x358562f9, 0x34b7b8c3, 0x38e5cbe8, 0x08d2c3ff, 0xd9bc724f,
+ 0x69fe8340, 0xa24caf38, 0xe1c5df9b, 0x6ca07f07, 0x0595da00, 0x9c09e78a,
+ 0x851bd60f, 0xc5683bf4, 0x4c2eb7ef, 0xd907dcf5, 0xcfcb55f7, 0xc27a572e,
+ 0x0c1854cb, 0xec2fbcda, 0x8725f84e, 0xefa234d7, 0x5cc6dc79, 0xfc237784,
+ 0xe7d72db7, 0xf38c05e7, 0x6faff4e3, 0xaa3f492b, 0x72db5ef9, 0x0d51fa4d,
+ 0x9f6f549f, 0x0e2fcbae, 0xbfaba4de, 0x5d3cd368, 0xc5a6c2f9, 0xeb05f2ba,
+ 0xe7e5d76e, 0xd5d2ee05, 0x0af96dbf, 0x0d2df95d, 0x7fcaeaf7, 0x975eb550,
+ 0x88ffc9bf, 0x738dfeae, 0xcae5759a, 0xa3078b4b, 0xf56f545f, 0x780fee0f,
+ 0x8d8ef93f, 0x7ca2556d, 0xd3fcf92c, 0x8f4a6cc6, 0x5d29ba37, 0x720a7281,
+ 0xd3cdda6f, 0x06f3adfa, 0xbe4b7ca3, 0x90d2c4ff, 0xc9ece0db, 0xec3946df,
+ 0x006cafc9, 0x7e78afda, 0x7cc28d40, 0x0a5def28, 0xfbf263b7, 0x1907a151,
+ 0xade487bb, 0xb1e5cac6, 0xa5fe99e6, 0xd6351728, 0x33836150, 0x45acbf7e,
+ 0x0e2c79a1, 0xe8e87482, 0x8f806059, 0xc7b9dff7, 0xa1d7e34c, 0xfd1cbcde,
+ 0x82955f04, 0xe5f687e3, 0xf08e1cce, 0x502b1778, 0x9265b58f, 0x2c6cec3e,
+ 0x22aa3f4f, 0x7e947cfe, 0xd28738da, 0x4a7e8d63, 0x5156368f, 0x036361fa,
+ 0xe5c6e1a5, 0x18dfbe94, 0xe348f4a0, 0xd2ff4a3a, 0xe1e944d8, 0xbe944dc6,
+ 0xf4a418dd, 0xd297a354, 0xbada9f08, 0x64afd10b, 0xba18daef, 0xf8432cc6,
+ 0x66dfd26d, 0xf854bf3c, 0x62f0f1db, 0xfc5c7ba4, 0x37a980b1, 0x722625ba,
+ 0xe5a8c07a, 0xbefce40c, 0xccf39f8b, 0x551579e7, 0xa3c01006, 0xfd234bf5,
+ 0x83ce2d22, 0xded1472e, 0xcfb09fa0, 0x8590764c, 0x4cccf59e, 0x6803e2d2,
+ 0x65e6fa84, 0xd009f047, 0x9b8a055f, 0x781f4bf3, 0xf1f07d39, 0x4bafd464,
+ 0xa3ae4db3, 0xafcfe3a3, 0xe5cf25b6, 0xdf53c0d4, 0x6e9fcfa6, 0x1fb9ca52,
+ 0x35994ee9, 0xe5c1f91c, 0xe9043a3a, 0xeca94d96, 0xd5b66967, 0xeb1d3475,
+ 0x6c3e6905, 0x17f12a47, 0xdea863ac, 0xbc470d77, 0xb470a27e, 0x3da08fb2,
+ 0xf105e6f9, 0x0be5c7eb, 0xfa2b0bf5, 0xf2ddacdf, 0x1b53da25, 0x2e1ceffc,
+ 0x794a98bc, 0x8b7d6fd9, 0x0cbb6039, 0x8dd0efbf, 0x72dced07, 0xbf2e788d,
+ 0xd953fe37, 0xa01fc931, 0x07630e92, 0x0927c899, 0x4ebebd2e, 0xdbebe5d5,
+ 0xfa74bbfa, 0x7900ff1b, 0x1515e365, 0x7046a0f9, 0x6c3dad45, 0x3ccb03f5,
+ 0x4ba6f82b, 0x0053ae75, 0xd7857ade, 0x72badd3f, 0xac6e95f6, 0x35f344d9,
+ 0xf1bc77c2, 0xe3555ba0, 0x3e6d5fc3, 0x862fa77d, 0x4537ff3f, 0x4c6af1a1,
+ 0xf6664fdc, 0x09ca3240, 0xcf240ecb, 0xce66fe20, 0xbd687e08, 0xf268e303,
+ 0x67f01fb2, 0xb3d963ba, 0x77f7134e, 0x9b26e38d, 0x5fc2f394, 0xcb378edd,
+ 0x3c46de70, 0x6e7db5d6, 0x137ad3f5, 0xe28e2bfe, 0x59f7e251, 0x026c97c5,
+ 0xfdb25efe, 0xd7ca2b03, 0xe14096a7, 0xe3e2f38f, 0xcefc27a7, 0xe88e63ec,
+ 0x4aee973c, 0xe96aff22, 0x0f4eb17a, 0x771c0eb0, 0xf03178fe, 0x034b50d7,
+ 0x662e5807, 0x9102fc82, 0x8fe5eb93, 0xfe8ac059, 0xa6e667d6, 0xe613f462,
+ 0x5f9356b7, 0xd9a5a4b5, 0x49f17e8a, 0x7c472a66, 0x256f649d, 0x6bd0d68f,
+ 0xf84ac9b4, 0xef4eb05a, 0xa99f8037, 0xa99f83cb, 0x19b257cb, 0xadfeb859,
+ 0x970160dc, 0x2ba9e697, 0xa8b9302f, 0x61ac45df, 0x8fd7da0d, 0xbecf475a,
+ 0xdbf0e912, 0xbf118ac7, 0x4078a1f3, 0x4df1e21a, 0xe35f63c2, 0xa3fac62f,
+ 0x1c61c27a, 0x86b7ca37, 0x8781047d, 0x378aedda, 0xbc6f8318, 0x7f246f82,
+ 0x875945ad, 0x4e9121f4, 0xf12a2937, 0x899999ab, 0xe7afcd5f, 0xba4e3ce2,
+ 0x0a5301ec, 0x77c543d8, 0xec932983, 0x43a408f5, 0x257af2a7, 0x8a63f6aa,
+ 0x7acbbe9f, 0xc08d0d4c, 0x01b0187d, 0x41565fc4, 0x0b8e1b47, 0xad9c12ed,
+ 0xa3d5db0c, 0x5b7d429c, 0x5f9baab6, 0xf681fe3d, 0x7b231860, 0x97d6e090,
+ 0x907d813b, 0xfa618efe, 0x7d1e49ef, 0xdf323abe, 0x6e17f110, 0x9b7fa18b,
+ 0xcc86776c, 0xf1b28fe0, 0x1d64676a, 0x9ceb8f91, 0xf48c11e4, 0x4df69b9c,
+ 0xb87f0996, 0x2c33ec4e, 0x97ed2e6b, 0x4ebecbd6, 0x259759fd, 0xf5ffd1a8,
+ 0xf915b76a, 0x866cfea2, 0x2dfe9825, 0xa61b9df4, 0xcd77d1ac, 0xca257f8a,
+ 0x127bd4a7, 0x3b7d518f, 0xbf95a5d0, 0x5efa0a5f, 0x4c19f8f0, 0x559f6fa7,
+ 0xbd210ffc, 0x705fe38d, 0xfa3dd9ff, 0xda77e5ff, 0xfd1e90ff, 0x7f0b1d3f,
+ 0xe2df50a7, 0xc650e03e, 0xfa3f483a, 0xf7e41852, 0xdc3ef89b, 0xa06e3b5f,
+ 0x7ffa3c7c, 0x2a18f20a, 0x1861ff44, 0xfef9590b, 0x3ae5e626, 0x5f7daab8,
+ 0xab9fae19, 0x03759fc0, 0x4d662f5f, 0x10be37a4, 0x9a0e2ffd, 0xff034859,
+ 0x513ff692, 0xbcad25fd, 0xa16b357e, 0x1a0fb8fa, 0x52e1e1d2, 0xa43abb5d,
+ 0xb0afee37, 0x0fa825c5, 0x62cdbaba, 0x376c00ff, 0xffb115e5, 0x412958b2,
+ 0x5e0bfd7f, 0xd4f7cfff, 0xdf302b2a, 0xb3da2299, 0xb6f98280, 0x53fed47e,
+ 0x013dd2d3, 0xf2a36f6a, 0x6572d34e, 0x012bf905, 0xb3daafe2, 0xe973e26e,
+ 0x1daad51f, 0x67b5ffc4, 0xd45c9087, 0xb4a6cd9e, 0x6a40f967, 0x3f367b57,
+ 0x9521794e, 0x535faf9f, 0xa713d67b, 0x9c62319f, 0x2ce07151, 0x125e7016,
+ 0x28847ca7, 0xffa7161f, 0x25d76a22, 0xd9cd76ec, 0x81a42c11, 0xfdf3355b,
+ 0x892ff050, 0x1af7e42f, 0xcf6c0be4, 0xb5be883a, 0xfa3ae92d, 0x4a35e746,
+ 0x937edfd7, 0x0a3de39b, 0xc68d0b3f, 0xff89b3fe, 0x403ff7e2, 0xbc1a2fc7,
+ 0xfdf8fb51, 0x8ff1a18f, 0x3334bea9, 0xe57fa3cc, 0x670fb259, 0x6bcd1754,
+ 0x1fd4d293, 0x89b672f5, 0x7b0079d1, 0xf46feb92, 0xca2fc967, 0xe8cca770,
+ 0x2f75afc5, 0xbdaa6537, 0xcdbbcff8, 0x371c02fe, 0x64bb24f8, 0x717ff43b,
+ 0x4b83d585, 0x0f978b81, 0x69d354c9, 0x553fbe5c, 0x342ae307, 0x7afb923d,
+ 0x2a6033f4, 0xebc5365d, 0x6aaef285, 0xcb007357, 0x09690ca7, 0xc1a73e41,
+ 0x5d19fb4d, 0x77da850e, 0x883b8bfd, 0x01dc72e5, 0x04a129ed, 0xaa031e30,
+ 0xd0d62fc0, 0x3e835065, 0x73bc63df, 0xf630b6ee, 0x13cb8777, 0xefb4e5e0,
+ 0xa1e84035, 0x173f332e, 0x600de391, 0x97683d81, 0xc9bc77ce, 0xd20ca4e6,
+ 0x44e64ef3, 0x99740f3d, 0xd28cce6a, 0x90ded2a5, 0x8976768b, 0xb70ca5af,
+ 0xfc5b0780, 0x6afe22d7, 0xb01c74e6, 0x850d2f50, 0xfa4b0fe8, 0x1fd03531,
+ 0x7e8476ed, 0xc784292f, 0x978e76ac, 0x66e683fa, 0x1961bf3c, 0x281615fe,
+ 0x48515d3f, 0xaf478b78, 0x75bb978b, 0xddfa04f4, 0xdc5df08c, 0xf084debe,
+ 0x146dba49, 0xc2d905fb, 0x17f5968f, 0x16fda59a, 0x1e5d05e3, 0x8befdfdc,
+ 0x2f2d868f, 0x1f017ea4, 0x47c0fa8b, 0x85f7960d, 0x33dd8f8f, 0xbf01f2b2,
+ 0xe1276665, 0xe613f161, 0xeb400da0, 0x05fd2e9a, 0x40feb4ef, 0xe9c60ad7,
+ 0xc36c78be, 0xf177841e, 0x00278a63, 0x45f68af9, 0xb5d018d3, 0xaff80e72,
+ 0x3efd3df9, 0x8be40b64, 0xe8ded16a, 0xd3c701ff, 0x3d9aa5ba, 0xb939b9f0,
+ 0xbd583fa7, 0x135f9f5d, 0xe4418be5, 0x39c405c7, 0x9ff79d90, 0x5de7e56d,
+ 0xb88f01a7, 0x6cf32d5f, 0x8bd52a5b, 0xa4551f9c, 0x728fceea, 0x895282ce,
+ 0x61039f21, 0x3f3da401, 0xa8965dc9, 0xd6efbbcb, 0xafe4af9f, 0xbf9dd1ca,
+ 0x5f20790c, 0x70dc2f97, 0x6c3f2e89, 0xfe5d28f3, 0xe8576d92, 0x51da2bfa,
+ 0xd11f2baa, 0xef2ead7a, 0xaba19f69, 0xcdff6a3f, 0xd798fcba, 0xc5f2ebe7,
+ 0xf2e89687, 0xd52c8fe3, 0xfa38afe5, 0x31ff5d23, 0xbdb7eaf8, 0x4b26d5f1,
+ 0x024f23d3, 0x24923cff, 0x0a770cfd, 0x32ffc18b, 0xe7e663dd, 0x5fe5a62c,
+ 0x7b4b5f12, 0x64fe5a6b, 0x3474753f, 0x368e8d9f, 0xccefedca, 0xaf4f77a4,
+ 0xf4e5fae2, 0x5fa469dd, 0xfd9ccf80, 0xe02b858b, 0x7a727946, 0x5e0dff50,
+ 0x653e24ed, 0x59dba76e, 0x924fd51c, 0x3e84f32f, 0xd157f1cb, 0xdcd06b7a,
+ 0x179c0ad0, 0xdf1d27e8, 0xadc2e2e5, 0xee94f480, 0xfae5e0fb, 0x9f405e7c,
+ 0x63d0623f, 0x9ed1e771, 0x3471e7ca, 0x97abf695, 0x88dcff0a, 0xbd1b47af,
+ 0xacbd9dfd, 0xdb2595e7, 0x7ae0d79b, 0xb1e2b774, 0xa2cdfb41, 0x874c16fe,
+ 0x7c89b480, 0xcaab72ed, 0x726ed052, 0xcfd8dfff, 0x0ce4b560, 0x6ab1d3ea,
+ 0x77a419e9, 0xb2afdfc4, 0x257f5cc6, 0x9e0326e1, 0x52aeaa83, 0x7ddf8c3b,
+ 0x856cf317, 0x74b52c29, 0x3c21b1ef, 0x4ec9bbb7, 0x32e103b8, 0x36a0ef9c,
+ 0x76359985, 0xb1e03ce8, 0x8f0499a8, 0xe38b1d45, 0xd8ff9374, 0xb6c2a2fd,
+ 0xbc38e1e6, 0xf3bba5df, 0xc4739e18, 0xd9b8f383, 0xe0c67042, 0x863534eb,
+ 0x8bd888fd, 0x776156f9, 0x3fbd9dbf, 0xdf89baa3, 0xcf783e65, 0xfd71fda3,
+ 0xe4ada83c, 0xe8f41533, 0x94f86020, 0x8c67c851, 0xbfb7a87d, 0x3ecd43ec,
+ 0xfb71bc53, 0x7f8f514a, 0xf8fe22a8, 0x7cb1a8be, 0x31e5cab4, 0x051bf977,
+ 0x97f23443, 0x82f5fcbb, 0xa4f91a21, 0x2f04c57f, 0x756177ad, 0x7a92f8a0,
+ 0x776837f6, 0x393541c9, 0xe8ff3c3e, 0x1fd3c679, 0xaec3f9de, 0xe3b9fe47,
+ 0x5362b335, 0x7d00d284, 0xddc850b0, 0x5919e6c2, 0x7c3e1aa9, 0xad7831b4,
+ 0x272d1f76, 0x502e9f0e, 0xb9bc1fb9, 0xc56d7031, 0x65d7ec10, 0xc0f3cad2,
+ 0xe50f2070, 0xe1d5b2b3, 0x425ea209, 0xbd70b2e0, 0x659ce7c6, 0x3e402ff2,
+ 0x07597f9f, 0xc20d03ed, 0xd22297fd, 0xfa58de5b, 0xcf189973, 0x4acedf3b,
+ 0x6c5f3e60, 0xcefd90b0, 0xd871f2b6, 0x9f8a0e73, 0xbeeb0858, 0xb85f2834,
+ 0x4be85d2b, 0x1a5b5c3d, 0xa55dae9b, 0x3805c746, 0xb91c2196, 0x8e197f61,
+ 0x03ec583f, 0xbb9b90c5, 0x81ecded4, 0xeb8e6fd1, 0xa403b977, 0x91e53707,
+ 0x1289f41f, 0x2e305ab4, 0x8d685666, 0x73b5f205, 0xa8f10a1b, 0xc177e8c5,
+ 0xc2aaf7f8, 0x9bf5c2ef, 0xf6b4bbf4, 0x14c9fb08, 0x33d9fde7, 0xecd1afc0,
+ 0x7e09b427, 0x195977af, 0x51eb93ae, 0xf5d0622e, 0x6bfb9569, 0x577d8ed2,
+ 0xb9307f7e, 0x7ee49d87, 0xb71b16fe, 0x8abd870f, 0xb7a7f205, 0x331d91e7,
+ 0xffe603e2, 0x4fa3552b, 0x369f972a, 0x76ffbfce, 0x2fec5be5, 0x51f7e854,
+ 0xbf7cce4f, 0xfb4615f8, 0x0f481b0c, 0x15a5f0df, 0xf02538e1, 0xcce3c177,
+ 0x38dd7662, 0x17b323be, 0x9f9c69ba, 0x66a738e3, 0x61c69dfe, 0x7a8c5c2c,
+ 0xe05311e6, 0xce9a2f4d, 0xd0f39b99, 0xe44ecdff, 0x64c66afe, 0xf767feb1,
+ 0x417c6095, 0xfcc97fc6, 0xc82fda3a, 0x9fe651b8, 0x1417f9e4, 0x01f08f11,
+ 0xdc94ffaf, 0x94aab83f, 0xe5121fca, 0xfebcb7ec, 0xa9fd651f, 0x5923fcbc,
+ 0x79abe45f, 0x86ab2ffe, 0x5e3f2296, 0x807c3e30, 0xcebefd0f, 0xc483c431,
+ 0x9bbd9d4b, 0x671cedfc, 0x6f1e4efb, 0xbfd02d04, 0x20ccfe11, 0x1e056853,
+ 0xe2f63c66, 0x6f11539f, 0x0b956c29, 0xcfe029cf, 0xe17ae731, 0x4679e347,
+ 0xfd8bdf44, 0x4554afd2, 0x9624f2a5, 0x5d27e584, 0x32e980ce, 0x1bfd3fda,
+ 0xfb9ecfd9, 0xd65df4a7, 0x4a9fee33, 0xed560d7f, 0xe73be90a, 0x3bb60a17,
+ 0x936bff5f, 0x604bcb85, 0xf78f5f35, 0xfd198fe5, 0x931641d2, 0x1f4fae4e,
+ 0xf5a4a776, 0x9f5b5e72, 0xe793addd, 0x193bb52e, 0xd7d762f5, 0x7a8add1f,
+ 0x31a9f303, 0xfdb447f4, 0xd5cfc217, 0x573263ef, 0xae43e106, 0xf69e90b3,
+ 0xc9bc68ac, 0xf1402522, 0x079cf203, 0x4f44f816, 0x3e635025, 0xa737e977,
+ 0x175dcae7, 0x7bf9e0a5, 0x3c0f88ad, 0xabcd9cf9, 0x713d67dd, 0x0abe60ee,
+ 0xe344ebf6, 0x9e980535, 0x3efbe34c, 0x771b9f27, 0xc9e7f500, 0x6c59bf5f,
+ 0x7c9e5c01, 0x5562cde6, 0x276bf763, 0x9cfb1475, 0x7a2271d1, 0x5edb1ed5,
+ 0x4498b34e, 0xca05e01c, 0x3f419549, 0x462fde39, 0x99790726, 0x347f4166,
+ 0x3f4eace9, 0xf5c0983d, 0x661683ff, 0xf4df2276, 0x70be3c67, 0x791d7ebb,
+ 0x91fb887a, 0xbebbd40a, 0xf87ebe4c, 0xc4d5a01a, 0x1eca1cc7, 0xf812bdf3,
+ 0x3dffb33e, 0xfe6e9c01, 0x1fad1326, 0xe73b06df, 0xab6c634a, 0x1fcf05ea,
+ 0xfc8c61d2, 0xf72a59de, 0x739fa0eb, 0x1b9fa0e7, 0xfaed13b0, 0xfce1d855,
+ 0x00a8e04d, 0xa69acc7f, 0xd9a2fce8, 0x5fa894b3, 0x1c73ff04, 0xa092050a,
+ 0x3091d27e, 0x1ca7fded, 0x21922b65, 0xe0d9da9f, 0xf09a4275, 0x79c147ba,
+ 0xbad322ff, 0x999be706, 0xea19fa65, 0x779334c7, 0x0bd004fd, 0xa7e5d75b,
+ 0xe5d9dfa2, 0x292c0536, 0x4fe7f9f1, 0x6947e08d, 0x4ccf89ce, 0x0a6a0253,
+ 0x276e17da, 0x9a3ebc57, 0xf7c368f8, 0x6ff63714, 0xf971bf6c, 0x00a60aef,
+ 0x75ddfa5e, 0xcc0a60b0, 0x0fd8836b, 0xc1413f01, 0x4507a9b8, 0x4cd2e57c,
+ 0x8d54bf77, 0xed7d2ddc, 0x26bf5486, 0xe3c8dadf, 0xf1139f36, 0xcf186d9c,
+ 0xf3d8c859, 0xb694d98d, 0xfbe9ba37, 0x880f1906, 0xf6fd080c, 0xbd97c48b,
+ 0x7dfa8a51, 0xe90cf235, 0xbd4ad7ff, 0x73fe6103, 0xb46fca55, 0x801a51bc,
+ 0xf0575b3f, 0x5fab2df2, 0xe50027bf, 0xdeeef6fd, 0x4a7e8c97, 0xfb82d29b,
+ 0xf8d05b71, 0xb7a6bf02, 0xbe10548f, 0x0a91b6f4, 0x22d7bbf6, 0xb79855f6,
+ 0xaca7ca3f, 0x2bf7bad7, 0xb4787bab, 0x7e433f7e, 0x71e385b5, 0xefde9e63,
+ 0xfee76fe8, 0xee16cbc6, 0xe8d4bddf, 0xaf3dac1b, 0xffc7189f, 0xe56df5dc,
+ 0x79c7a6a9, 0x2d51c902, 0x9db95b0b, 0x33fd26e9, 0xc515f421, 0x72124f21,
+ 0x99f30f5d, 0xe499f307, 0xce2a7ee4, 0x9f7c1e6f, 0x5638caa4, 0x5e981f1e,
+ 0x9f7cdd9e, 0x57b7dd66, 0xa1ec6fcc, 0xe05fab6e, 0xfa68ed05, 0xa7e10f61,
+ 0xe78f2f75, 0x83d9f7ae, 0xb5b55009, 0x0067b3c4, 0x2b76fbae, 0xd65f5c6e,
+ 0xb9f0f019, 0x0fa64fe8, 0xfb30f35e, 0x3f87c629, 0xf8237367, 0x10fc90bf,
+ 0xfaf64b38, 0x7c864917, 0x800fe482, 0x46fc88b7, 0x46b53f1d, 0x0f7affca,
+ 0x85ab4ff2, 0x7cb73fe7, 0xcc62fc41, 0xe9115eaf, 0xfa6bea9f, 0x535bfea3,
+ 0xbcd3fd65, 0xffec9e7d, 0x50dfef0c, 0xebe2dc3e, 0xa7307a44, 0x68ed0f37,
+ 0xfc82ef24, 0x355e4d70, 0x2f3cede4, 0xdf76b1f9, 0x8f100757, 0xaf9ced75,
+ 0x7e077823, 0x5ff0bd46, 0x1de76116, 0xdb8e71cc, 0xc137f273, 0x458fff9e,
+ 0xc0ca1e7b, 0xa5ef0f9e, 0x6cfbd85c, 0x3df644d6, 0x209e0307, 0x283ac81d,
+ 0x94dd65cd, 0xeea7b7ba, 0x99a4b445, 0xa2a7d37c, 0x0b3bfbff, 0xe98ce5e9,
+ 0x9e105243, 0xf39d0374, 0x87cf9cec, 0x369c4bd8, 0xaf4473a4, 0x1acdf3f0,
+ 0x37594fa1, 0x14e9ab8f, 0x60227fbc, 0x4f41580a, 0xcdef34d5, 0x764ef3c2,
+ 0x35e541d0, 0x84e6ee22, 0x5ac79597, 0xd559e567, 0xe8ce776f, 0xc995cbd7,
+ 0xe6e741de, 0x56795f20, 0x72ac7f5c, 0x10eabe12, 0xa7d3483e, 0xf25ca985,
+ 0xfadb5d77, 0xf1e000dc, 0x10ef3db3, 0xe6b13efd, 0xd699f3f1, 0xf87ead37,
+ 0x81fad75e, 0x67d0f515, 0xbce0dfe8, 0xe79d0f54, 0x49efeead, 0xe5e512b9,
+ 0x55b6660f, 0x9641ff33, 0xdc6d548e, 0xabd05edc, 0x10cde05e, 0xf74c59e8,
+ 0x74c57e83, 0x19a7e81f, 0x1709cfd0, 0xfa12369b, 0xa87db139, 0xb5e0056b,
+ 0x75f254b9, 0xd3e44afe, 0xd7c97ce6, 0x4ef4ad17, 0xf4f3e180, 0x3eab66f9,
+ 0x8e723ebf, 0x8464d177, 0x9e5d84fb, 0xcfb45de3, 0x325ea80b, 0x84bf5a35,
+ 0xf9f281e3, 0x8c98ee6b, 0xced97706, 0xe2df64b1, 0xb3aaadd9, 0xb573ba39,
+ 0xa26eac4f, 0xa01a955f, 0xb3aaac7d, 0x55ce74b9, 0xf50f391a, 0xefd463f6,
+ 0xb7887ed4, 0xee407ce8, 0x0be66bc7, 0xe0367b79, 0x1fc04d25, 0x14e572b8,
+ 0x2c2fff98, 0xd761bd1a, 0x30059fce, 0x245f7464, 0xf54bdc2e, 0xfefaad9b,
+ 0x05417ab5, 0x2897d9fe, 0xe566bbfb, 0xea310994, 0x97ea1a27, 0xc7a7feca,
+ 0xd7ab4784, 0xfd5f50ec, 0x3eda2d9b, 0xd10f4b5b, 0xdfccbe5f, 0xe845fd4c,
+ 0xa3af9813, 0x7ab5be4f, 0xeeab9e25, 0x6094f04b, 0xf7f76cfc, 0xe465e918,
+ 0x5e468f2f, 0x9edcadf3, 0xcf1d9d55, 0xefc974b4, 0x0c099741, 0xfda172e9,
+ 0xd089fb19, 0xa083fc1f, 0xd170dce6, 0x90ca3b8e, 0x59f191ce, 0xaa37f680,
+ 0xa0b01736, 0x3fff7e46, 0x470a171c, 0x28bc6ea9, 0xf83a651c, 0xc7c1dffe,
+ 0x31f07115, 0x87c13bf1, 0xf4ca3ed1, 0x188fb432, 0x5aaa9837, 0xc32e9cf1,
+ 0xd3e7b014, 0xec89b239, 0x6c9796eb, 0x6c405c5e, 0x62f26b49, 0xa596fd9c,
+ 0x374acf6e, 0x795f0fea, 0x702bcc1e, 0xe4e28997, 0x3a7be4b7, 0xcb797cf0,
+ 0x567be6bf, 0x0ccea0e2, 0xc43c67b2, 0x3adfbe1f, 0x841e5afb, 0x68add7c4,
+ 0x9f5d68f2, 0x7f75a76a, 0x17b38cc6, 0x32db3da3, 0x59ce92a3, 0xa029fa34,
+ 0x4cd6b3f7, 0xea443f46, 0xcd6d8737, 0x2fd680e4, 0x495eac0b, 0xafc47c7e,
+ 0xa4f64d5a, 0x4a5bf6af, 0x1c6317c3, 0x6fb056f6, 0x9d35b418, 0xc37ee9b9,
+ 0x96476ae3, 0x5be60ed6, 0x5cbe7ac4, 0x66fde315, 0xdabbea32, 0xde31546b,
+ 0x134f9423, 0xfb5bf7f0, 0xcbf44ae0, 0x349e2c0a, 0x5576976c, 0x63ffdd37,
+ 0xad08786a, 0x039dcdd3, 0x85911e29, 0x520fd033, 0xdd2bfc5e, 0xab082c07,
+ 0xedd3b444, 0xbb8d7b43, 0x64d9fef9, 0xb04e575a, 0xdee83339, 0xd0b98b96,
+ 0x8dc7fb1f, 0xc67aa4e7, 0x19aed2f1, 0xeefd4893, 0xff416feb, 0x2494c663,
+ 0xfc95978a, 0x60a7ec67, 0x9fb31a93, 0x3f4ae378, 0x2186f32f, 0x4a17ef31,
+ 0x9f6bc5ba, 0xe327096f, 0x72a9f53e, 0xa3183cb5, 0xcb8d857d, 0x05fbf1a1,
+ 0xf47373fb, 0x5e0f0efb, 0xc22e76f3, 0x0a47cccd, 0xb23bfe39, 0x3f8f1e90,
+ 0xe63261f0, 0x30fbaeb7, 0x7bfcd30b, 0x6eb8a0bf, 0x485918d0, 0x6f15679f,
+ 0xc4a7ca05, 0x49f9bc6f, 0x55fcca7c, 0xabbd6167, 0x5fe927d1, 0x647c5374,
+ 0xe74634fd, 0xd31eb85e, 0x36c7f1e2, 0x8faa1ebe, 0x7a008e73, 0x3a36c7e2,
+ 0x4548e9d7, 0x67fe22b8, 0x00d69bdb, 0xef4217ae, 0xe8cf7ad0, 0xd23f4a6f,
+ 0xe9930eb8, 0xd3f71b52, 0x76a7e9e3, 0xff889741, 0xa3f5fc2e, 0xfa461f62,
+ 0x220915e7, 0x945f886f, 0xc25d8b71, 0x15baee6f, 0x3cc2772f, 0xe414f1fb,
+ 0x1bf690a2, 0x21d69859, 0x3fbc9b4f, 0x3d3ad1b5, 0x5014e74c, 0xf497eb4e,
+ 0x1b8a7e69, 0xa9f814ae, 0x859254dc, 0x9ec576fe, 0x0bde689b, 0xf5a74c37,
+ 0x7986e569, 0x77096784, 0x3edfc185, 0xf69a34d3, 0x51d1e315, 0xdfd2d7fa,
+ 0xbc767e96, 0xcd5c53fa, 0xfb10c744, 0x4fe90253, 0x4519473c, 0x7e7418fb,
+ 0x2df3fd27, 0x61bf7e56, 0x47df0263, 0x1df782d8, 0x457d47c0, 0x3e9139f5,
+ 0xa66d7caf, 0x6def98fa, 0xa6ea727f, 0x474de60c, 0x2ffbc6bb, 0xf398f84d,
+ 0x646fdcb5, 0xec9be566, 0x2a6d3e37, 0x6abe426d, 0x8a07fc12, 0xe1e9c2c0,
+ 0x7dca54a6, 0xfa4dc5be, 0xd9ef00ac, 0x532f80c4, 0x59a487ec, 0xe72859c2,
+ 0x8af7a875, 0x9c7dbf50, 0x7dd2761c, 0xd3ab923d, 0xe2bd056d, 0x7ee28fff,
+ 0xf625bd51, 0x827be7f9, 0xfb17af5f, 0x14f2c6a2, 0x37479cbb, 0xddbadbe9,
+ 0x516e4963, 0xffdda31f, 0x8fd01ee3, 0xa7081f28, 0x693d6fb3, 0xe2717d4c,
+ 0xb2e3a224, 0xe33788a1, 0xb87b1db8, 0xe3a6fe5e, 0x983826fa, 0x4edfa35d,
+ 0x7fb261a9, 0xbf8606a7, 0xfa41f88f, 0x7c0f3bcc, 0xc7376a9e, 0x0a6fbbd4,
+ 0x5fbf1a7c, 0xab9ddeb0, 0xf447475f, 0xf2e0eb2e, 0x377afe7c, 0xf0899ed9,
+ 0xc42be231, 0x8f5ef683, 0xf378cbe4, 0xd267582e, 0xee320bdd, 0xfb146fe7,
+ 0xed1f977a, 0xe24fceb6, 0x68a52bfb, 0x28f53f5a, 0xb8fbe1f3, 0xbceb6123,
+ 0x05bf7ce1, 0x61e9b7d7, 0xed9fed0f, 0x7698b0b5, 0x34e029ca, 0x37a93fea,
+ 0x4edf8efb, 0xa387add3, 0x3c59dbf1, 0xefdb33de, 0xa595bc44, 0x069d7dca,
+ 0x127dd635, 0x6d9d5e99, 0xce2117b8, 0x8718ca73, 0xf6586aeb, 0x1d757fa2,
+ 0xbfb8aa0b, 0xbf738d73, 0x3aefcfca, 0xaf685fa8, 0xc6b9973b, 0x375fcfad,
+ 0x9eff9f4c, 0xc8bdf627, 0xe5b1c9cc, 0xcd7fde58, 0xe7ea48bb, 0xf3f51590,
+ 0xfd259db2, 0x350fd37a, 0xd8d05eb8, 0x87681ad5, 0xf5c1aa78, 0xfeec7a42,
+ 0xf6da45dc, 0x8f48162e, 0x05833ed5, 0xc514f134, 0x434ec173, 0x3c09e2bb,
+ 0x6f087695, 0x7f3973aa, 0x9b8dea80, 0x2bf9edc2, 0x1d876c89, 0x36f5fbf4,
+ 0xf71e3456, 0x11e1ec1e, 0x7a3d203f, 0xe41fa8bf, 0xf69f8669, 0xb70658f9,
+ 0xdc99df77, 0xe9c7d06d, 0x07c3dad7, 0xf8bb8b70, 0xcdd93770, 0xdcbbc566,
+ 0xe5ce431e, 0xb1c07b7c, 0x788577fc, 0xf6496c9f, 0x1c334a41, 0xf92c5e5c,
+ 0x15ae7a7a, 0x48896f7a, 0x10b4c7ab, 0xe7667fde, 0x47d5edfb, 0x7f88c943,
+ 0xa3c73967, 0xc5d308f3, 0x39f118fd, 0x67edc6d5, 0x076818f5, 0x9bb73af5,
+ 0xe7fc8859, 0x05f23250, 0x28521d0b, 0xa4e0515e, 0x6bd70773, 0x4bec7627,
+ 0xf3a1a05e, 0xfe5b99f1, 0xff9863f5, 0x40775c54, 0x392b197f, 0x566619fc,
+ 0xb3be40ae, 0x7889f1e5, 0x7b29f0cf, 0xa2bf8d1a, 0x1f89a1e5, 0xb3f8fe42,
+ 0x4a41e5e6, 0x680b5a57, 0x0b5b9ffc, 0xa9e7bd21, 0xa7e8ad97, 0xac2b829b,
+ 0xfb3ecf68, 0x0889facd, 0xaf8f67df, 0x5df3889f, 0xf4cbf4f9, 0x4acb657d,
+ 0xa6ff8f4a, 0x3f8fca99, 0x7be54cde, 0xb523fa9f, 0x1eecfe3f, 0x3bc3cfc2,
+ 0x213ed0f7, 0x8ccafc0b, 0xd04eb9f3, 0x8516baed, 0xb2d354f0, 0xc1a05d53,
+ 0xfced75d3, 0x4efb7d7b, 0x7f7c2175, 0xfeeef158, 0x57ca256f, 0xdb753d9f,
+ 0x8ad7e4e5, 0x58afa57b, 0x08a3b080, 0xfd05019f, 0xe00b2b0c, 0x76e7cb54,
+ 0x9739418f, 0x077a8474, 0x70f8deb1, 0x98f88a93, 0x0126e60a, 0xdcac07f2,
+ 0xf711a93f, 0x60495e07, 0x8f9d026a, 0xb8a2299d, 0x99bf210a, 0x024fd10e,
+ 0xeed4c76f, 0x8cff7e22, 0xaffd05c3, 0xba437c43, 0x7df9530a, 0x1d67809d,
+ 0x201303ac, 0x0ce2513d, 0x29427c50, 0xe2710fbf, 0x20e6123f, 0x61acea1d,
+ 0xa6a1677a, 0x41cdf388, 0x7e0f3f3b, 0x68b0f41b, 0x870cfd4f, 0xf3f38ae9,
+ 0x8e48e76d, 0xc7efcd7f, 0xa96edcb5, 0xf1bd5273, 0x9a7b1f04, 0xd4508bbf,
+ 0x1276a960, 0xbdf8451c, 0x4fe71978, 0xed841ca3, 0x5c9fc14e, 0x211e604e,
+ 0x2b4e479c, 0x554e47a7, 0x58f7c550, 0xd59b5b6a, 0xf9d14505, 0xa0ee1f15,
+ 0x3fe791f3, 0x76889a5d, 0x5bf8ef2a, 0xe571ef44, 0x7ef21e7c, 0x3fa71cb0,
+ 0xbb435d06, 0x27bdd89f, 0x31e431ed, 0xbe822f22, 0x5643cae3, 0x1a9cafe4,
+ 0x96c0dfde, 0xc3598a3d, 0xf8ab032f, 0x5bb6be7c, 0x0f4df275, 0x7f38c060,
+ 0x7be9bbb7, 0x8a6de6ce, 0x290ee099, 0xa7362f78, 0x392159a5, 0x3962f113,
+ 0xb0ffde41, 0xf9c15060, 0x7e91b849, 0xfd30af92, 0x4d6fddbd, 0x33768b18,
+ 0x79c6fa44, 0xb23f63a4, 0xaf76bbc1, 0x0a33212d, 0xcaecdbb7, 0x4753fba1,
+ 0x694d7c38, 0xd3007f9c, 0xbead3eb9, 0x38f3fa74, 0xf1956d1f, 0xcf98f96c,
+ 0xc2bf0334, 0xf2695978, 0xe3d423de, 0x60e43aef, 0x04ebe50a, 0x4f5f13df,
+ 0xc1777e15, 0x6fe22103, 0x37e7c749, 0xc563ca9b, 0x7024161f, 0xe770063d,
+ 0xdc247ce2, 0xe321e971, 0x4b3d442f, 0xcef6ef62, 0xc662ce51, 0xa4c6823d,
+ 0x2b8b66f2, 0x46d1ed07, 0xa8654bc7, 0x3f973a47, 0xdbef1838, 0xe8f5dcd6,
+ 0xdefded60, 0xc256559a, 0xdf95b35f, 0xc3f68a1b, 0x2497a1ef, 0x4ca93970,
+ 0xfc478df1, 0x27adb5d7, 0xc6de2cba, 0xc5f655ef, 0x57ce7d5f, 0x56f9d3f5,
+ 0xfa21f22a, 0x487b2df9, 0xd63c95ef, 0x0ecd694a, 0xf4100f7e, 0xe5015298,
+ 0x2a763bd5, 0xaeff090b, 0x837fb41c, 0x707b828b, 0x48a2eccb, 0xd7b707bc,
+ 0xaf80ff92, 0x71c82f48, 0x5c3f513b, 0x9425a906, 0x7579f88b, 0x9507d5e7,
+ 0x0c53d264, 0x91f801f9, 0x19e932e4, 0x27be885b, 0xf520bd70, 0x29f0197f,
+ 0x769ac7f6, 0x7df708aa, 0xfac5e616, 0xf14baa69, 0xda56e468, 0x8d8db71f,
+ 0x19c671c2, 0x6eee35e8, 0x50abb7ce, 0x8e5f395e, 0x121afec2, 0x167da892,
+ 0xf53c7da0, 0xefd8621b, 0xe3870b01, 0xe6e5c619, 0x3177bb13, 0xfe41d5f1,
+ 0x796a4a1e, 0xf571c90b, 0xff9a56e6, 0x09378100, 0x668ef54f, 0x3501bb92,
+ 0xccf50541, 0x788fac38, 0x9dbcef82, 0xc810f5ca, 0x7fc1aab1, 0x9fae0ece,
+ 0x5ec2fdb0, 0xa9ca56e4, 0x76f7f384, 0xe56abfdf, 0x044f6238, 0xd75e243d,
+ 0x61fd7026, 0x2b94bfc4, 0x02198394, 0xea33932e, 0xcfa6b03f, 0x12a728ad,
+ 0x4bd89f9e, 0xa1884fef, 0x8cbea4ef, 0x67497747, 0xb487d390, 0x48f52a72,
+ 0x9005be5c, 0x21ca5cb0, 0x48cf5c63, 0x3889f43d, 0xe7fa94b7, 0x0f3c09d7,
+ 0x79c5e47c, 0x6bf11ea2, 0xddaef9f0, 0x97c70db7, 0x32384af0, 0x05e3eb26,
+ 0xdd9d2e10, 0x49e3e74c, 0x65fe057d, 0x4d77d72e, 0xfaf0dec2, 0xa19e053b,
+ 0x81ea885e, 0x91f9441e, 0xc8ed1af0, 0x1d7c095b, 0x3f3f431e, 0xea36788f,
+ 0xa4b70967, 0xd0b3d49b, 0x03b620ee, 0xd5acbefc, 0x878e12df, 0x737ff815,
+ 0xdef6be54, 0xddf106f8, 0xb8dfe106, 0xfb43d99f, 0xdfea1732, 0xfa957948,
+ 0x4b3fe234, 0xc5f0463c, 0xd04fe9fd, 0x7f24cc1f, 0x7f0bec5d, 0x0874bfb9,
+ 0x1e64fd63, 0xd9500019, 0xfcc7318a, 0xb7642d5c, 0xb91feb47, 0xab29cbf7,
+ 0xc0ad7ea0, 0xa1fbf4a7, 0x49d9b7bd, 0x2277caed, 0x993a37dc, 0xb38f134b,
+ 0x51f25ecb, 0xee2dfe2c, 0x3d456bd8, 0xef413356, 0x8e56b057, 0x39132fc7,
+ 0xe44cbe9d, 0xec394df4, 0xb75ca075, 0x4be4f7fe, 0xd35a6f91, 0x9b91db62,
+ 0x24bde513, 0x5d6227c1, 0x3259d722, 0x353bb46f, 0x7465f586, 0x97d623dd,
+ 0x1afa3e42, 0x03d055b7, 0xeceb3bd6, 0xc31bdfdc, 0x8720f0e9, 0x983dd60b,
+ 0x3ae0fd97, 0x7ea6ab6a, 0x617e044a, 0xd17b65d7, 0x2b39d24e, 0x29423c2d,
+ 0xdb077ae0, 0xe0b9e119, 0x1ea6d275, 0xba42a4eb, 0x9c387e0f, 0x5beb6985,
+ 0x02bf69c7, 0x89b94bd6, 0xf5e37d99, 0xaf5faf9b, 0x30e9b160, 0x7db5d691,
+ 0xe2735faf, 0x63735fac, 0x6e115fae, 0x73269bf2, 0x44fdfc7d, 0xfffb3efd,
+ 0xa46479f6, 0x4ef78ec7, 0xfe09e473, 0xbdf7a0e9, 0xdfb65432, 0xdddf869a,
+ 0xca4bae3c, 0x6875ea91, 0x622bfbed, 0x2dbd70bd, 0x5fd46bfc, 0x61cb2f32,
+ 0x1bf64efd, 0x1de911f9, 0xb1b9e391, 0x852707d7, 0x30efd01f, 0xb6b6af5f,
+ 0xfa60764c, 0xe3872279, 0xc947cb54, 0xd736e714, 0xa33bf66f, 0x8fd9e974,
+ 0x180fa749, 0x1e283af3, 0xcd2f2de8, 0x1aa5ea43, 0x29d82f11, 0xa9700bdf,
+ 0x4cbeffb4, 0x3277c7ec, 0xc5f31f1e, 0xc9c52f10, 0xfdf024d6, 0xde5c2fda,
+ 0x83c25494, 0xd64a7f7e, 0x3b53fb97, 0x903e3fa5, 0x96564df3, 0xfc279fb8,
+ 0x1e1d964a, 0x7163b3a1, 0x27d677f6, 0x98ef422a, 0x4ad9d0e2, 0x3fdf9674,
+ 0x80b3b46c, 0xfcf25ee6, 0xbdd0874f, 0x43cc05e1, 0xd60ba9e7, 0x23405839,
+ 0xf30fadcf, 0xd1ef5b71, 0xe0a8ff8f, 0x3ac45bef, 0xf7bc55b1, 0xa6907c84,
+ 0x5f88abd1, 0xb7fa9f9c, 0xb3afbf57, 0xca5e42d3, 0xfe17fb44, 0x0b7ee66e,
+ 0x149e9f7c, 0x136fef9d, 0x1c91df4d, 0xa391c695, 0xa394f3b2, 0x8acfdbf3,
+ 0xf82273bc, 0xf85bdfe4, 0x1fbfc9be, 0x8d6f9534, 0x04678fc1, 0xa9925e3f,
+ 0xa5deb0fa, 0xe3076e21, 0x31eb93d5, 0xdde91e2d, 0x8c97813d, 0xadc72e02,
+ 0x38cf6fc0, 0xf23be27b, 0x7f29573e, 0x1ac6a73f, 0x85b9442a, 0xf383d734,
+ 0x442a1899, 0x155e77bc, 0x54b4a5ca, 0x24cf85f8, 0xd2dfa154, 0x6aad8cf9,
+ 0x9d27b3ab, 0xfbf5133a, 0xf5dbffdb, 0x753f98dd, 0x27a6f726, 0xebe44d6e,
+ 0x85fe788c, 0x38250f4c, 0xfb35de39, 0x33ffa876, 0x6a7d7a6c, 0xcd397071,
+ 0xed3b3330, 0x5fb9f903, 0x2298726c, 0x452dc0fe, 0xf0ea7798, 0x33f0b5f8,
+ 0x2c8f9c25, 0xa51f652f, 0x80523ee3, 0xff5b4ae2, 0x422a7402, 0xfbf63dff,
+ 0x8fc84cac, 0x96353fdc, 0xe0e898df, 0x5b1adc7a, 0xed158cbf, 0x3f489f91,
+ 0x325eb939, 0xcfe239d2, 0xf68d3809, 0xf3838464, 0xcd2243c7, 0x72fc295c,
+ 0xa696d7e8, 0xdfef4fed, 0x1b019fc0, 0xbefce3f9, 0x52c7714b, 0xe3c26fb1,
+ 0x7dd9776f, 0xb9323917, 0xee2b18bf, 0x5a81fa5a, 0xda8a34fd, 0xc8e17df3,
+ 0x8959b9fe, 0x92331ff8, 0x7970f0b4, 0xda89f391, 0x54bf6135, 0xb8e00b80,
+ 0x59abcc49, 0x94610bbc, 0x9fe39f0f, 0xec7a3e4b, 0x7a0dd877, 0x49fa1f06,
+ 0x9f37fdc3, 0x8bb8fd09, 0xdc503f84, 0xe384df31, 0x4ddb9d0e, 0x3f296deb,
+ 0xbd622d85, 0xd5ccfd0d, 0x3877d1f8, 0xfca9fe92, 0x2cc3c2a4, 0x345b8f32,
+ 0xc8407df4, 0xbccaa66d, 0x867fb4b6, 0xcd7df079, 0x5a1296d6, 0xf96a9d0f,
+ 0x0bfdf680, 0x49ff7137, 0xe910b3d2, 0xcf49ece9, 0x0f1c0d9a, 0x505acfa0,
+ 0x75850d9f, 0x1fe41155, 0x6584f413, 0xe645c91f, 0x8c64f0ac, 0xf765dab7,
+ 0x7eca9c93, 0x2b0d1cea, 0x5ca89412, 0xf2e7fb47, 0xf65ae52d, 0x8fb22e33,
+ 0x9077dfa0, 0xe2591ae7, 0xdc4b3a9c, 0xe44acc6f, 0xbce227e9, 0xdfb156e4,
+ 0x59a449b8, 0xb5cfb1c9, 0xfb7d0a77, 0x9dd2628e, 0xa1c31dab, 0xd3e4f7fa,
+ 0x0e996745, 0x06d48bdf, 0xb3a2f7c2, 0xb6fbe12a, 0xce95fc9f, 0x1871235b,
+ 0xddfc9bac, 0xfc9db5bc, 0x65c656bc, 0xd3cf7588, 0xa1c86f26, 0x3ef813d5,
+ 0xf9f1e5e7, 0x88f3d245, 0xe3ae4f80, 0x9d98503f, 0xae6573de, 0x7e343311,
+ 0x08c29b24, 0xee47619f, 0x3dc91b73, 0x76ef7463, 0x7cfb9b9e, 0x2fc0581f,
+ 0xd6fb5700, 0xdd24cf37, 0xde39eee2, 0xb8e580bc, 0x3fde5df6, 0xfebdc43b,
+ 0xda65d8cb, 0xc0d626b8, 0xaef5bee1, 0xfc7e74a9, 0xac9eee7f, 0x7092678b,
+ 0x39f959d7, 0x3a161804, 0xc8b3f6cf, 0x9b9f8a3f, 0x1c017f87, 0xfb5edaf3,
+ 0xea3e014a, 0xf746d17a, 0x3ddbe6ef, 0xd1ff6714, 0xbdd1378b, 0xc9e60aa6,
+ 0x6432f7e2, 0x05d1467c, 0xcd9b07dd, 0xfde9abbc, 0x0b84bc3a, 0x310cdc7e,
+ 0xc2cbc33e, 0x80299f90, 0xeafed99b, 0xf9c50a57, 0xe47be9f9, 0x5db9979f,
+ 0x44fdfc59, 0x3d60a76c, 0x850c877c, 0x904fbe15, 0x153fa0f5, 0x7a8957f2,
+ 0x6b7a8957, 0xf77a0694, 0x0efb8ecc, 0x78a7de90, 0xbee99936, 0xedcdc79b,
+ 0x4fba7755, 0xca9f7eb3, 0xfcbe74fc, 0x895e12aa, 0x094dcf70, 0x90b8c58d,
+ 0x79fe1cf7, 0x98f7a44e, 0x1ce973cf, 0xf1375874, 0x25b03559, 0xedeaa7ea,
+ 0x1cf6a096, 0x16ca00f9, 0xf5e989ca, 0xef3eb8b1, 0xb0d2f872, 0x3d92577d,
+ 0xa238c660, 0xe6065f44, 0xba612a4f, 0xedaa78d7, 0x8748494f, 0x3bbfcf53,
+ 0xcb7ae91c, 0xf96f270b, 0xf4fdc331, 0x24c2dbe4, 0x1c14eea7, 0x9dddb4ef,
+ 0x7c79dbd2, 0x5764dd9d, 0x4a73f235, 0x14c7ed89, 0x465cb93b, 0xd7375ff5,
+ 0xaef62f7f, 0xfa0deb4f, 0x6fde7a34, 0xfed1a7d4, 0xdeb4fab4, 0xeda34fa0,
+ 0x4ffd3eb9, 0xf5c02b9c, 0x2f6f499e, 0x53bf7a65, 0xcb193fef, 0x4ebcc49b,
+ 0xce3fb859, 0x1ca32e02, 0x6b17b2cc, 0x1df380e5, 0x7c01fff0, 0xe763e3c3,
+ 0x6f246494, 0x66670fc5, 0xb2541ca1, 0xe5780386, 0x525972a7, 0xa991df08,
+ 0x802bb284, 0x40ae95de, 0x56f904c8, 0xdf091e71, 0x1fa009d5, 0x9f66552a,
+ 0x9b95a690, 0x8e73e609, 0xc91b97f3, 0x7d38ef6f, 0xd4df8873, 0xf7da70d0,
+ 0x778bc675, 0xfbddf3d1, 0xc07de871, 0xfec36a51, 0x15fc3ab6, 0x9b03b44e,
+ 0x3eefd0ce, 0x24e3bdcc, 0x3dd615c5, 0xe258daff, 0xefed38bf, 0x4f33e314,
+ 0xd77ff137, 0x45cb7fed, 0x62bfd2ba, 0xf0835f7a, 0xeafedb59, 0x5abb9461,
+ 0xab605ef9, 0xe05ef745, 0x9977874e, 0x023cc633, 0x52a4276b, 0xf83f673c,
+ 0xf7ca2936, 0x1ffe1c07, 0x90d81e11, 0xf2571c14, 0xd055bd7f, 0xef526077,
+ 0x35fdae7a, 0xe92f5f41, 0x1f5e05b5, 0x789577dd, 0xb6fd50be, 0x7bf7c858,
+ 0x8defd8d6, 0x8d3e0936, 0xe70e73f0, 0x5972f7e7, 0x669833d5, 0xdffbf9e9,
+ 0x3e8edc9c, 0xc07cf02d, 0x7488dde1, 0x7f9fe8d2, 0x140c3c23, 0x774c67fa,
+ 0x7ec948a1, 0x003d285f, 0xc27f34af, 0xb4712f7b, 0x615ff9c6, 0x3e07f3e1,
+ 0x1f4e0ffd, 0x678053e0, 0xca5f80bf, 0x7a897bef, 0xe622dcfc, 0x5bd44bb9,
+ 0x81efe4ec, 0x2f7abe4a, 0xe73e362d, 0x3cf2f145, 0xf83665e2, 0xc66fb885,
+ 0xc20d3586, 0xfc679076, 0x96343f1c, 0xce19afee, 0x5c7835d5, 0xf52ffc4c,
+ 0xe3c71178, 0xcf714eab, 0xf413e052, 0xa6ff2f3b, 0xc8c61cf8, 0xf850acae,
+ 0x998af13b, 0xf1f1f5fb, 0x6eff813a, 0x2bc70246, 0xcecff3e0, 0x8d3e28cc,
+ 0x423f4970, 0x3a1f27fa, 0x1ea3fbc5, 0xb7f6c1e6, 0x5cb5e8fe, 0xefcc271e,
+ 0xfc531dcf, 0x119d929f, 0x588ee6f7, 0x1a4d8543, 0x747bcafc, 0xfabc5db2,
+ 0xedb8ffd2, 0xe7ba6657, 0x8e43f465, 0x89da7588, 0xd4ebf53b, 0x21bd4bbf,
+ 0x9ca4b8e2, 0xb55bc3ce, 0xee87bc66, 0xe05c7925, 0x30ef10ac, 0x325e9034,
+ 0x4dff57be, 0xee35a1df, 0xd4a89df3, 0x9333c7af, 0xe9fed42e, 0xf6a2b8e3,
+ 0xa5c718cb, 0x92fd7fb7, 0x61b49c44, 0xdef34bdf, 0x893fd929, 0xf73dc8bf,
+ 0xfdbad9b3, 0x81fd68c6, 0x7eb18fd4, 0xc7d33e7c, 0x86e2fe11, 0x389f392f,
+ 0xcdef7493, 0x9edef132, 0xcdbbf04d, 0xf50cfa19, 0x14dedda7, 0x11247f42,
+ 0x5ef42796, 0xfc893380, 0x5da1a72f, 0x24976892, 0xbbdb25da, 0x7f0b9da9,
+ 0x8dda070e, 0x6afc124f, 0x7bfd7667, 0x07bdf2b9, 0x6e24c4ff, 0x65dc44f7,
+ 0xd17e7f48, 0x3bc37d57, 0xf0116910, 0x9217143c, 0xbc7b7cc1, 0xfceea879,
+ 0x3fbc8f04, 0x2f4ffb2a, 0x90ebbfd7, 0xfbe7d3e9, 0xfbe7d1cd, 0x3b79f5fb,
+ 0xacf2423b, 0xe7d97c84, 0x2d9e7434, 0x599911de, 0x4f8a9dee, 0xc450dd35,
+ 0x7485e0fe, 0x6d7f41ce, 0x8b6fa40d, 0x5f1be2f3, 0x9043c367, 0xdf0dfd9f,
+ 0xe7119983, 0x4ab7983d, 0x75bfdf38, 0xdac5bbed, 0x96e1db78, 0x6f110bf9,
+ 0x877e6fb3, 0x4dd67fec, 0x54fd6887, 0xc77fa29b, 0x7eb7f662, 0x43ef82bf,
+ 0x15fbef9f, 0x7cbe3a17, 0x4c93e69f, 0x8cf11dbb, 0x04d0d7bf, 0xb03c8de3,
+ 0xdc77e69c, 0x73f912f1, 0x02f07e4b, 0xb60d9b9d, 0xe12757f8, 0x20eb173e,
+ 0xf84273fd, 0xf853238b, 0xfc8cceef, 0x86786b39, 0x0975d8e4, 0x83a47fe2,
+ 0xbc8d93c7, 0x5d13be1f, 0xc73f3be0, 0x22bd7ded, 0x65ea00e4, 0x95127b0b,
+ 0x8304852f, 0x88458b79, 0x40cd1bb0, 0xf00edb30, 0xdaef1cac, 0xea7c0193,
+ 0xb8f48ff0, 0xb17aee00, 0x7f17194f, 0xd426dceb, 0x4d15f533, 0x7819a60a,
+ 0x5d3f8dde, 0x7c610302, 0x97d73c83, 0x8e3c44ef, 0xf9a399e3, 0xe02f986d,
+ 0xe2c549f9, 0xd4fc693d, 0x1f7bc8ae, 0x18e78c26, 0x2eef3912, 0x3839e131,
+ 0xc07ae0cb, 0x3cefea23, 0xb72c64b0, 0x1b0fdc3f, 0x5235e629, 0xbb41ed0d,
+ 0x59eeca39, 0xd5e18bb9, 0xc6999f7b, 0x7b502573, 0xdda90a0d, 0x9c6ed138,
+ 0xdede3768, 0x8a832fb4, 0x0aefbaf9, 0xfbac5b59, 0xaff514ae, 0x52aff514,
+ 0xbbf9037c, 0x285b8026, 0x99ca2c9f, 0x8a746f78, 0x87b26e68, 0x95e67f68,
+ 0x883eae9b, 0x75bf24ed, 0x7aa5f889, 0x7334bf11, 0x88b79896, 0x4f78925f,
+ 0x5e92764e, 0xf654933f, 0x7121e906, 0xdfcb2fae, 0x186efa96, 0xaefa861b,
+ 0x46f7f4a3, 0x37a475fd, 0x7d67d77d, 0xac8bbe83, 0x82c799af, 0xcf98b3e5,
+ 0x7f0f2632, 0x416fc767, 0x4d61cc7c, 0x9bbead16, 0x9bb7ae59, 0xf9f4f837,
+ 0x07577ebe, 0x94f88851, 0x7e90cee3, 0x2fdeb951, 0x5f2ffb9a, 0xe9fd92a7,
+ 0xb9ed64f7, 0x83ff5ac1, 0x9acd63c7, 0x57ed39f6, 0x8b9fed29, 0x94a3ac78,
+ 0xfe49b7d6, 0x7558f1e3, 0xac78866d, 0xd07bcd59, 0xb1e34576, 0x69cdddb8,
+ 0xfb58f1e7, 0xdbcffc44, 0x9720ff16, 0x45fbce86, 0xfe2447fc, 0x971e66ea,
+ 0x51c45933, 0x99ab38c9, 0xb26ace22, 0xe3053fa8, 0x6ccfd03b, 0x7a72af5a,
+ 0xfbfe8905, 0x1348be31, 0xc6db357f, 0xe3c608f5, 0x7ff1e74c, 0x831e51fb,
+ 0x86f57d62, 0x0e303ff0, 0x57cbc7d0, 0xaf20ff61, 0xc01eb0eb, 0x593bf241,
+ 0xe518efc4, 0x972146f2, 0x566dce37, 0x363c9217, 0xec4e15ab, 0xcb7f7197,
+ 0x26872760, 0xef143e0b, 0x5d1f002e, 0x9f199c9a, 0x59d862ef, 0x77c17d7d,
+ 0x999e7ca3, 0xcc7b6578, 0xf00fcf1c, 0x694b28fd, 0xc457bd37, 0x50033c2a,
+ 0x892aae6f, 0x8d7ed1e6, 0x17b90936, 0xcf7f2afc, 0x91358aaa, 0x2d61ae1e,
+ 0x1e712e94, 0xfff7f2b2, 0x560fe4c2, 0xd3be066d, 0xd92d93ec, 0xecd7cfa6,
+ 0x5d65f3d0, 0x381cbeab, 0x012c75d0, 0x7493ee55, 0xe10d88cf, 0x5bd48f7e,
+ 0x88e5e84c, 0xbb7a12be, 0x28bca92b, 0xec34f244, 0x20a5f6bc, 0x4975c01f,
+ 0x3b277d8c, 0x3b8c5bcd, 0x5ca72226, 0xdd158ddf, 0x60fb158e, 0xd73af163,
+ 0x2a034a28, 0x1bd80b9e, 0x3e02b7ee, 0xb326b3c6, 0xbe477e56, 0xeb9d2cb2,
+ 0xa6bfbe5b, 0x8f988bd5, 0xbec8c5e8, 0xf88cd859, 0xa40f7a94, 0x25ebce86,
+ 0x7caa279d, 0x972a89dc, 0x30f1929b, 0x9275a426, 0x3e59f27f, 0xb4fecff2,
+ 0xc2f5cbdf, 0x48f8deb2, 0xd1f0d3d6, 0x647c58b2, 0x72a65a4e, 0x9ba25478,
+ 0xe3893009, 0x44f22d5c, 0x3968bcc7, 0xf2b1cde5, 0xbd8bce8c, 0xa95ede62,
+ 0x1f5e988f, 0xf9afb1e5, 0x03deebba, 0xddedec3f, 0x8903bab2, 0x7e862145,
+ 0x1fe4a7c4, 0xfee45975, 0x7e57bfaa, 0xd678a358, 0xdf9acd99, 0x8ebb006f,
+ 0xd732f2a9, 0xe5c5cc3f, 0xfbe18d9e, 0xd43e1a17, 0x97b04dd9, 0xd4eef405,
+ 0xfccdabee, 0xe93c8127, 0xb291ff48, 0x08f7411f, 0x89db8128, 0x826ed2be,
+ 0x9e2331c6, 0x1980f64d, 0x15e997e1, 0x857cfd62, 0xd55f3758, 0x5bfb4096,
+ 0xfbc5923b, 0x60d9832c, 0xd4c867c4, 0xf4cf7e83, 0xeb3eef46, 0xa495ec1b,
+ 0x60840613, 0xecf32979, 0x2a7cff47, 0x9efdd2f3, 0x6aa0d632, 0xe984bdf9,
+ 0x5db27ce5, 0xd2ea9f9f, 0x81f78de7, 0xce3d17f0, 0x23063f87, 0x057b487f,
+ 0xfbcdc07e, 0xa13b565b, 0x3bd7dcfe, 0x763279f0, 0xd5eea1eb, 0x1ff79049,
+ 0x7df15971, 0x3d47f9ac, 0xe8ad306b, 0x5175e1f4, 0x11feb3b0, 0x4f866021,
+ 0xf017bf70, 0x3d80e8b0, 0xf8579f91, 0x7ce0bce9, 0xdfb228f9, 0xe763de3d,
+ 0xa47ee6f8, 0x5fa4af91, 0x53e25134, 0x449345f8, 0xf33693b7, 0xa6944a7e,
+ 0x837ebc81, 0x95015fb0, 0xf8a307f3, 0xdd099dd0, 0x47afa865, 0x1a5961ff,
+ 0x4cef9dc6, 0x1d31f9e5, 0xf3e5131e, 0x21ec7e78, 0x9bef09af, 0xf207bc8d,
+ 0xcff9fdf0, 0x795097ac, 0x3e2f2f09, 0x2bebc4dc, 0xf19f29a7, 0xeee5b5d1,
+ 0x8abf1e64, 0x14a61b71, 0x78c61ebe, 0xdc45e9d0, 0xf1ae9d3f, 0x7c294def,
+ 0xebd640df, 0x6afe6e2b, 0xbfaf8f1b, 0x28ffdc5a, 0x22ac2078, 0x4c8da17c,
+ 0x5385bd41, 0x9d06fe16, 0x773c8d8f, 0xf9d62ca6, 0xb70a427c, 0x7a369fcb,
+ 0x779a47d9, 0x7982ab59, 0x4efafef4, 0xfba0a3dc, 0x4abff7fa, 0x128ef179,
+ 0xeca7ef13, 0x7ef9e3cc, 0x76bb5f3f, 0x078040dd, 0xf004cce4, 0x9f3e1f7d,
+ 0x10f9451d, 0x7078d7ea, 0xb8c9322d, 0x363f3e25, 0xc9c92861, 0x709c88ac,
+ 0xa08370fd, 0xae820deb, 0x82dfbb26, 0xfc28dcf0, 0x4229a1bb, 0xd1b3478e,
+ 0xed1fef64, 0xa6979721, 0xf677e2f4, 0xc720df59, 0xc5be0255, 0x1984caf8,
+ 0x6442cbf7, 0x479dabc7, 0x8f0ebec5, 0x1debe82f, 0x7d16daf6, 0x20cdbebe,
+ 0xbf6245bf, 0x62da91f3, 0x1ca77eed, 0x1fd36abf, 0x4aae7f68, 0xb8d075ca,
+ 0x973779df, 0xd0978deb, 0xc6066f7e, 0x195fa029, 0x5f5f9270, 0xb02ceb8b,
+ 0x3e09d707, 0xf53172c8, 0x6bf73a0a, 0x149f7196, 0x65553bc7, 0xd7be13aa,
+ 0xb8a0ebae, 0x226ddaf6, 0x9dded16e, 0xada77fcb, 0xc6b6773b, 0x9c7e843f,
+ 0xed006e78, 0xfa34ce9c, 0x9cda5add, 0x0773c688, 0xf502dc46, 0x149fe38f,
+ 0x1cfb1e0f, 0xe817d716, 0x94a6564f, 0x8cc94bcc, 0xd67cf2a6, 0x8a8fcfc8,
+ 0xbc5257f2, 0xdb7e88f3, 0xf3fcefcf, 0x4039c361, 0xb4dfb89d, 0x9c4f2531,
+ 0xce298633, 0x98626ea9, 0x894e9be2, 0x7bf8507b, 0x50af74d0, 0x7b3361c4,
+ 0x70e71740, 0xe8db63d1, 0x3ee479de, 0xee9366d2, 0x9b53d23e, 0xa47dd2b7,
+ 0x5f30f2d4, 0x207db40f, 0x288703d6, 0x97f713ad, 0xeb801d70, 0xbe56da81,
+ 0x1078781e, 0xb0faafbf, 0xcf1fdfc5, 0xddf1a207, 0xdafee8a7, 0xe03e1786,
+ 0x7f76d7f7, 0x9afefb10, 0xbf406758, 0x4f77c6bd, 0xe40fac35, 0xff390c3d,
+ 0x960f1293, 0xefbdfa0e, 0xe46cbb53, 0x1bef198a, 0xdb9bbabc, 0x60e7a4ef,
+ 0xca2231dd, 0xc0fd7227, 0xe3c900d4, 0x6a87a109, 0x793ef852, 0x87ae0ef5,
+ 0x53f41a4e, 0xcfbf056d, 0xf9a06242, 0x9f79045d, 0xab06c325, 0xb23c4d21,
+ 0xa65fce31, 0x8dbe85bb, 0xab6ba747, 0xe01ea858, 0x29b376bd, 0xf4446934,
+ 0x1f6c803e, 0x07ba30b4, 0x498a52f4, 0x880c8bde, 0xd7bc8d75, 0x791aeb47,
+ 0x7bce412f, 0x9fbf1348, 0xf2807280, 0x3b8a4afd, 0xf381fde6, 0x915c1f6d,
+ 0x11e48738, 0x47922cfc, 0x97046067, 0x3c7887cb, 0x713995ad, 0x811bf6bd,
+ 0x059c08d7, 0x6d533e7c, 0xfd915e9c, 0x4c9f3125, 0x561bbe31, 0x894f3827,
+ 0xbf147fa7, 0xac43f569, 0x97293138, 0xc87aff92, 0x18f21f65, 0x612d9f97,
+ 0x9712b7ba, 0xc38f9f6f, 0x52ff02b7, 0xeedefd8f, 0xa7fa8d3f, 0xb467eb6a,
+ 0x2e56970f, 0x3d08e7ee, 0xbdfcf754, 0x1e9e3df4, 0xabb77e32, 0x03bc1e1c,
+ 0x3a2a3491, 0xce03e43e, 0x23f1d151, 0xffc882fe, 0xa1bbdb5f, 0x008000a9,
+ 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1[] = {
+ 0x00088b1f, 0x00000000, 0x5ced0300, 0xd554780b, 0x5e675eb5, 0xc927bc99,
+ 0x11e12664, 0x24188106, 0x86022124, 0x41084e97, 0x0209d55e, 0x7906bc82,
+ 0xa8983c85, 0x36af6ab4, 0x2f440543, 0xad5b4ded, 0x05f8af78, 0x29a916a5,
+ 0x6bc48301, 0xe14041c0, 0x29784b6a, 0x51136d54, 0x08921512, 0x8bdcab97,
+ 0xbdad7ba6, 0xc99cccf7, 0xfa3e090c, 0x8ceefd7d, 0x6759fe9f, 0xdece73ef,
+ 0xded7b5eb, 0x3b3b1d6b, 0x8016efd9, 0x400af1cb, 0x24f44032, 0x00c757b0,
+ 0x42c22554, 0x1c4b4307, 0xb4327738, 0x2300349a, 0xf789bb58, 0xa80409b3,
+ 0x8d36eba6, 0xecb419b3, 0x903c1692, 0x028beecb, 0xafbb2d67, 0xa25f3c53,
+ 0xc892cfbc, 0xece8c1db, 0x3e287d3f, 0xb2217a07, 0xfde3d7fb, 0x88701185,
+ 0x109300d0, 0xe8f06c07, 0xe0fec6ee, 0xe78bf7e6, 0x17fb3803, 0x0f9efac5,
+ 0x83c69ab0, 0xe4cdaee3, 0x0cca28f3, 0x1f6aafdd, 0xffa6679b, 0x11567775,
+ 0x78f4c71b, 0x78b6df3e, 0xd1bc3420, 0x83ba5fa5, 0xf025b3f5, 0xced1ed7e,
+ 0x3ea2134c, 0xeec2bd66, 0xcb8c8d69, 0x45006c82, 0x913bd007, 0xaecc0ad1,
+ 0x88cc71a5, 0x7183e7c7, 0xd8f4fc46, 0xb891fcae, 0x0381a8d2, 0x36e8fa37,
+ 0xbf607f71, 0xf64fc8d1, 0x404dfbde, 0xde26f97c, 0x01c71631, 0x1c1a2f1b,
+ 0x06adf9ec, 0xb53e4628, 0x638c0946, 0x51339ec8, 0x717ee1c8, 0x6e829dff,
+ 0xc0f6f0d5, 0x1f7ec8f7, 0x181c0255, 0xa571f008, 0xfce80e11, 0x4454fae4,
+ 0xcc0dea05, 0x3e4348eb, 0x70193403, 0xf94ccb9e, 0x0a78e3f7, 0x9bb71de2,
+ 0x5497f3d8, 0xec9c1b35, 0x9f38edf9, 0x9f17e418, 0x47247b57, 0xa6659ef9,
+ 0x7fb1fba2, 0x03269cfb, 0x1e9795ea, 0x71f6e9c5, 0x75e0070c, 0xe3975d3b,
+ 0x414cb450, 0x0321bf18, 0x071a0e6c, 0x5002c068, 0x18d97f8e, 0xda3c631a,
+ 0x9d77f62c, 0x06535cfe, 0x75e743b5, 0xa6b1dff8, 0x441843b3, 0x5a1b5a32,
+ 0x93032e2e, 0xf42b932f, 0x73e1d589, 0xe7f781e7, 0xbe7a3230, 0x86fccf78,
+ 0x389597c3, 0x58460580, 0x0bd19bd7, 0x3606ac1b, 0x738e2812, 0x0f489ba7,
+ 0xb2ce9826, 0x68ee2bf7, 0xe874676d, 0xe0e801f7, 0xd6a71cac, 0xa7d0ffa7,
+ 0xd7e70d23, 0x9a72f9be, 0x608c532d, 0x1b3cdfa4, 0x64a53ade, 0xfbaf9e85,
+ 0x3409b1d1, 0x83a32b5f, 0x4a95f7bc, 0x88199c3b, 0xd51aedbd, 0x6f3c4373,
+ 0x052a92e4, 0xf42751c7, 0x199b50be, 0xe3e994df, 0x7e26bdff, 0x0787bdff,
+ 0xbf5d8158, 0xe478b600, 0x30b830c3, 0x20f4c4d1, 0x21d69a17, 0x60343b26,
+ 0xe2e78a33, 0x814766f0, 0xa747c32d, 0x7455133a, 0xaa5ee2ef, 0xae2b7dfe,
+ 0x7bf7b553, 0x7b5506e0, 0x8aae777f, 0xb47eb01e, 0xaaa0ffaa, 0xfafa2af1,
+ 0xfd54538d, 0x574f5707, 0xdeb643d1, 0xb43feaa5, 0x7b556ef6, 0xaa897d76,
+ 0xc6f6dc1d, 0x25cfc64c, 0xbf8c9f82, 0x1529fc80, 0xfc540974, 0x01332c76,
+ 0x851e28f0, 0x442a5bf5, 0xe22a0cbb, 0xd457ef50, 0x37b37eaf, 0x8c36d05e,
+ 0xd25a3b44, 0x301a6cb8, 0xa55a5b3d, 0xefc9a8ff, 0xaa37cbbd, 0x6ad515e9,
+ 0x9aab74ba, 0x358a6fde, 0x087a659f, 0xbf97a0bd, 0x8e5cf7fe, 0x511133ff,
+ 0x452231ca, 0x9b48c72d, 0x19d18e5a, 0xe6c6396a, 0x9f18e5a8, 0x826396a7,
+ 0xa4c72d5d, 0xf6396a49, 0xec4daf98, 0x5f207f9f, 0xf5f042db, 0x47f603c6,
+ 0x72b8d862, 0x902d0e8d, 0xc61981ff, 0x3e47c891, 0xcf3a61de, 0x75dfb43e,
+ 0x9fa0054a, 0x8f6b1fa3, 0xd38fcef0, 0x42474146, 0x03ce0a75, 0xb88c72f2,
+ 0xf999812e, 0x239ed627, 0x9df682ba, 0xcb932734, 0x5b8c5379, 0x9753ecc3,
+ 0xafc8e8a0, 0x559d7188, 0xb809519c, 0xb43ce86e, 0xcc0531ae, 0xa1faf442,
+ 0xf4bbfb80, 0xe4feb1d7, 0x5c68336f, 0x8d9d9fde, 0x412ed18e, 0x278a0d2a,
+ 0x1187fd16, 0x5e527c68, 0x7e49c14b, 0xc9b8057d, 0xd98f2faf, 0xa97ce062,
+ 0xbbec75a5, 0x3417a1ca, 0xeceeff48, 0xd9575bf4, 0xf89e9500, 0x3dfe1037,
+ 0xae2c3e50, 0x935f32e8, 0x7d7ceba5, 0x5e91b472, 0x1e951c92, 0xb0cfb1c8,
+ 0xb50cc21c, 0x398d733c, 0x27ad855a, 0x0fe981c3, 0xd0add73e, 0xcf126e73,
+ 0xaf8c49b9, 0x9d315c1f, 0x59aecc1d, 0x4cef285f, 0xf53346c2, 0xced90ef3,
+ 0xd188cdde, 0xc233dc82, 0x67f408fd, 0xf35dd87c, 0xb7bd9b8a, 0x7193fb64,
+ 0xa9fff8c0, 0xc392caae, 0x77eca2ec, 0x0cece36b, 0x38ee755b, 0xab4ff3b4,
+ 0x83aa93b5, 0x92ff0bc4, 0xcf89e3c0, 0x73f695b6, 0xc7b0ff92, 0x295b3fa0,
+ 0x6eb2b7c6, 0xe36034c5, 0xf08d6d73, 0x3611c444, 0x7bacae23, 0xbfe40bf4,
+ 0xbf2d5eab, 0x7b3f7c56, 0x9fefc95f, 0xcf48d8b4, 0x2935bddc, 0xc0de9e88,
+ 0x4f96e570, 0xf20c4226, 0x4ffc83bd, 0xdef8fde0, 0xe05c58af, 0x322ed5aa,
+ 0xc76d77c4, 0xafeb8578, 0xe523e49d, 0xd7fbaae7, 0x5d71b42f, 0xeca317fb,
+ 0x24f1b146, 0xbd46fb30, 0xf26e09ba, 0xfe906fb7, 0x0be7c8d2, 0xa9198cd5,
+ 0x77697e3e, 0x666aca6f, 0xdbcb6e78, 0xe7f10a71, 0x5cf714e7, 0x8f101da8,
+ 0x2df2557e, 0x2c6daf90, 0xbf7482fe, 0xa15eabb8, 0x041a1c35, 0x4ca0f88a,
+ 0x1f20b1ef, 0x0eb46aca, 0xcd595f7c, 0x4640cb7e, 0xfaecd697, 0xe5f5c92d,
+ 0xd2c7c483, 0xc02d071d, 0xe88602e8, 0xadb64be7, 0x1882f210, 0x5e4412c5,
+ 0x7207efec, 0x18943e39, 0xe45d5e5a, 0xf9757b53, 0x629a3f20, 0x5fb03f38,
+ 0x7ec2f277, 0x7291ee3c, 0x9dd476e3, 0x0025a6dc, 0xaf9027f1, 0xf17fbbe5,
+ 0xf8a5f202, 0x21c5f78f, 0x15745a3f, 0xad37df5c, 0x78d9d8b5, 0xe26ef58a,
+ 0xb14b94a7, 0x3f17b79e, 0xe3e263fb, 0xb63fa3f2, 0x54f3d700, 0x3fcd1e4d,
+ 0xf4bde715, 0xf1139999, 0xd27032fa, 0x31378bbc, 0xa4bc3079, 0x823b4983,
+ 0x12fff7c8, 0xf2dbfc78, 0xb810f31c, 0x687b80f7, 0x73163f5e, 0x3cf11168,
+ 0x7eba2cd3, 0x9897ea49, 0xbf412aff, 0x9f25f62d, 0x715bb5f5, 0x2d1ed65d,
+ 0x0b7f22b4, 0x8d7cb910, 0xf2df3d2a, 0x11c92368, 0x2fc16e74, 0x27fb93a5,
+ 0x95f24e9b, 0xa35741f9, 0xeea91ede, 0x7dfd9d07, 0x67ef91e3, 0x38c28fe3,
+ 0x7c12c5b9, 0x9138313f, 0x1afd93cf, 0x059e9821, 0x8f2d85fa, 0xf7fd9e91,
+ 0x6c3f6e09, 0x5e2b1e1c, 0x849a2eaf, 0xdefef1fd, 0x9bef48b9, 0x463e90a1,
+ 0xfd982780, 0x7d0bd16f, 0x7b2fb752, 0x71fed182, 0x057a775a, 0xc2e75f7c,
+ 0x7d75c5f7, 0x0ebf9b1e, 0x5e5281f7, 0x6e7ae35d, 0x97d781ef, 0x2972bf0b,
+ 0x86795f94, 0xfbd091fb, 0xfd807705, 0x1ffd85eb, 0xfcfffb24, 0x497f97a5,
+ 0xdb93be7a, 0xa1b5e7ff, 0xbf843fec, 0xf630fdb6, 0x67fb7dff, 0xc4b4c7c9,
+ 0x1cf1f3ab, 0xefceb7f3, 0x165f6fe0, 0x0fe4a4fe, 0x9e6fd2e5, 0x73ac9e80,
+ 0xeb439f42, 0x19f9d5ef, 0xe38cded8, 0x8294f6e0, 0x6f6b82f1, 0xc78c4da4,
+ 0x71137c44, 0xa5c62289, 0x9975bc34, 0xde9e2fc7, 0x3ff5ffd4, 0x3dfde00d,
+ 0xc59fd449, 0x7fd63a13, 0xce3fe89c, 0x17d6dfdb, 0xbd5edbdb, 0xfc93907e,
+ 0xe2992d90, 0xdc7f1113, 0x0772e421, 0xc5f38ff6, 0x22a8463d, 0x39c95c7c,
+ 0x8bf91af5, 0xef3fb11c, 0x8215f7a0, 0xcf718753, 0xc5134a5b, 0xd9fd801f,
+ 0x7d81667c, 0x1db9a72d, 0xf6caf8fa, 0x442f14b7, 0x50fe507a, 0xcad78eaf,
+ 0xf032ed77, 0xc23ee8f9, 0x73361aeb, 0xd2297f94, 0xdbc5bf2a, 0xa106d689,
+ 0x6ac239c5, 0x44d4bd36, 0x8085f3bf, 0x6d4282f3, 0xaff4389f, 0x438a60cd,
+ 0x7011fb7f, 0xc63e6bfd, 0x9ed2c3f7, 0xcca988e6, 0x7a4a5359, 0xd9939771,
+ 0x87c72253, 0x30e7fc98, 0x4b9cded9, 0x38f3d17c, 0x53bbeb9c, 0x0d84e7dc,
+ 0xd60b37a4, 0x79e3d71e, 0x588bb302, 0x83ef37ec, 0xcec8b5da, 0x7de896bb,
+ 0xceff67e3, 0xc9eb532b, 0x76ea5582, 0x7a6a43e7, 0x5c97b48d, 0x97b7f5c8,
+ 0xac0335e6, 0x6243ecc1, 0x8193b32b, 0x9547663a, 0x9573c246, 0x13a7c226,
+ 0x644cbf1d, 0xea6bcc72, 0x9cbea030, 0xededc0d9, 0xafe744c5, 0xe73cf113,
+ 0xae0fe328, 0xb10eba73, 0x27f670ef, 0xf6449f5c, 0x6397e679, 0x88bef072,
+ 0x8c61a608, 0xb27fd74f, 0xf52dc48a, 0x48d1e983, 0xc3fe6fec, 0xbf7093ad,
+ 0xd46dbd56, 0xd5d8bd1b, 0x0d7cdab2, 0x87fc97de, 0x79f23b68, 0x4d6add70,
+ 0xae37a62f, 0xf7c14506, 0xb267ae3f, 0xb0d37f44, 0x7adfb00f, 0xabbe7f03,
+ 0x59a20be1, 0xca639d3b, 0xd82398f1, 0x6ae88146, 0xa3326f7a, 0x96c8ddb1,
+ 0x07d248e9, 0x14adef1e, 0xcf50bebc, 0xdf18b8e2, 0xb305d739, 0xc8313e2d,
+ 0x63f1203a, 0x32ce67e1, 0x32b621fe, 0xf90181fe, 0xae784299, 0x43f2a6d2,
+ 0xc3f70037, 0x1e2ad437, 0x0df79b3d, 0xa78d763b, 0xd615ebfd, 0xfe8cf4ce,
+ 0xf65dfa66, 0x2b8e7e73, 0x3d7e6dc7, 0xf58dbc75, 0x02616b37, 0xbec071e9,
+ 0xb144adee, 0x7d03ec2f, 0x4ff0bec4, 0xd86ba728, 0x8bfbaa17, 0xb636a17d,
+ 0x1ecc1b4e, 0x3da35cc7, 0x001827b6, 0x64f6d5d7, 0xcee1f9df, 0x4ccd7c20,
+ 0x0e5f90d2, 0x0f8c3ff4, 0x1d1e7c29, 0x23c38869, 0x6439b834, 0xc64e9fbf,
+ 0xe8f0cd7d, 0x81cf1a00, 0xb3f47369, 0x0e0718c9, 0xfdda0ab7, 0x5bdede33,
+ 0xba7257b6, 0x5ddfb89f, 0x910ffbc9, 0x1d9d05fd, 0xf43c8ed0, 0xf500c7a7,
+ 0xe575fcef, 0xe90c7764, 0xa49ca019, 0x243d31be, 0xa77a95bd, 0x1e40d02d,
+ 0x8d9265ea, 0x44ed2be4, 0x7465efce, 0x234223f8, 0xb0457f9b, 0x49322cf8,
+ 0x9f8bec23, 0xcb4851ff, 0xf727915e, 0x953a4dc7, 0xf3df6dbf, 0xa3fa3a65,
+ 0x5ba338f6, 0x4963e4cb, 0xb125c672, 0x57d135fb, 0xb47ea246, 0xd75b1f25,
+ 0x314f8b44, 0x53f933f9, 0x29ffdcec, 0x63cc1336, 0x3dce50f3, 0x063b40ee,
+ 0x4affd8bb, 0x0f318b3f, 0xee7fdf93, 0x7df17cde, 0xde398e46, 0xd1e30030,
+ 0x1e781f71, 0xdaf7bf41, 0xff9fdd9e, 0xdef7da07, 0x5a4ee9cb, 0x7ce86257,
+ 0xfaee3bd6, 0xb66e3e08, 0x8cf9c78f, 0xd51fef12, 0xe87df4f0, 0xbc35461f,
+ 0x28d5eb4d, 0x362337dc, 0xd40a5e0c, 0x42d39c5f, 0xe439d28b, 0x2569cfda,
+ 0x313fda3f, 0xf8cf3c50, 0xe2f90c32, 0x0cb2be8a, 0x4be3e5f9, 0x139d131f,
+ 0x9fcfd5c1, 0xda71e7bd, 0xf3044687, 0xd83ae3c7, 0xf9fcfc48, 0x41195f2d,
+ 0xf3ffe7e7, 0x17454121, 0xfd555318, 0x55fd4d0b, 0x0ca6b7ed, 0xb64fb556,
+ 0x53d1530d, 0xfaa94633, 0x5f2728ff, 0x379edf45, 0xc8bfd559, 0x87a2a45e,
+ 0xfd556a79, 0xaf543c6f, 0x3469cf6a, 0x7338a015, 0x47ece54f, 0x28e4de1c,
+ 0xd918f540, 0x311fb15a, 0x00aaa3af, 0x5fd18f97, 0x6c47eed5, 0x0efce58f,
+ 0xf1d0b3d4, 0x1bf5264f, 0x8885fb2b, 0x31c4827b, 0x27f23a29, 0x5c638f57,
+ 0x12574e51, 0x455383d3, 0xb8d91f4c, 0x594d2bce, 0x70b85ed8, 0x0bc63c68,
+ 0x1e2fd5ef, 0xf2bc7a81, 0xfa8787b5, 0xc75c73cb, 0x6e5f156c, 0xe2a9caf9,
+ 0x08ac3e4b, 0x2a3de390, 0xa0f4d0ba, 0x29adffaa, 0x93ed55ab, 0xc8058f6d,
+ 0xfa2a57f1, 0x074f3947, 0x807371c8, 0xb5545f1c, 0xb03771cb, 0xd6c74c75,
+ 0x1d6cbdfd, 0x75b0f443, 0xb60df10c, 0x601e218e, 0x206e98eb, 0x19959bc0,
+ 0x732a8784, 0x557ffae8, 0x53be11e6, 0x73fc2769, 0xc6c224e5, 0x7ca1074a,
+ 0x1dadcdfe, 0x4db1f724, 0xa307a48d, 0x5e92d54f, 0x915635e4, 0x543c8c9e,
+ 0xbb971fb1, 0x01471ee1, 0x2d656d62, 0x656767bd, 0x9929e13d, 0xfbb9d387,
+ 0xeee2ff72, 0x7347798b, 0x21efcf12, 0x36ab798d, 0x2fc8ad8c, 0xbd7e47bf,
+ 0x8fc200cd, 0xdd3f249f, 0x78682516, 0xf1c7b797, 0xcdfc7ffe, 0xffb7e4bb,
+ 0xffb20662, 0x9d8e64b4, 0xccc3bb66, 0xa7126f70, 0x56b09e65, 0xf6739f23,
+ 0x398e7c31, 0xce17bc49, 0x01f7b64e, 0x4bdabb58, 0xa2b4463f, 0x089ce8a8,
+ 0x2e0d7b75, 0xf77da3ad, 0xf6f247b7, 0x696749bd, 0xa2fe815c, 0xe9a46b74,
+ 0x96393f63, 0x68a826d7, 0xe9aa7d57, 0xd3b93f63, 0xc5f33a79, 0x79d0a290,
+ 0x9b309964, 0x81936372, 0x061da3c7, 0xdfd8eebe, 0xd3573f41, 0xb1b58b6a,
+ 0x72bb1ef7, 0xf7f22c7d, 0xe424c018, 0xe9861dbf, 0xd7cc3117, 0xcddfd30d,
+ 0xaf9e94f0, 0x3be381e7, 0xc49fe4ad, 0xc831dce7, 0xc6fb8c96, 0xc6fa6ce9,
+ 0xd05be25c, 0xb369f57d, 0x4a1add77, 0x0fb3a976, 0x8fd93ca2, 0x3714dc22,
+ 0x9d8e5228, 0x1fc93724, 0xe52b1d2f, 0x13a70df1, 0x9d057f24, 0x1a9ed01c,
+ 0xff79eb40, 0x4f5f4973, 0xcff10776, 0xffbf203f, 0x98a4f917, 0x1efe7c4d,
+ 0x14d3ed3b, 0x0ed38db3, 0x0c7e334e, 0xdbb7bd25, 0xfe33fe85, 0xed811c70,
+ 0x74111cc7, 0x8dfac2be, 0xe717e998, 0x49eb306d, 0xbc18676f, 0x8758f779,
+ 0xcebafe5f, 0x9c01eb2c, 0x97a67cf4, 0x98274f64, 0x67c5829c, 0x3e9c8527,
+ 0x69f1e28f, 0x52bbfb60, 0x681ba68e, 0xbc0bbf1d, 0xcc93ca3f, 0xd4d8bfc5,
+ 0xee738ae6, 0x0fc6c679, 0xddfa3177, 0x7da7debb, 0x7de9fce9, 0x7dfae3c7,
+ 0xc90fc2e7, 0xe3bf8eaf, 0x375c38eb, 0xc65f1ddb, 0x6f6fcba1, 0xc673a0ed,
+ 0xb133869a, 0xd7f88e78, 0x9fa42d2b, 0x148c93f3, 0xd5882ec7, 0xb8797059,
+ 0x3060975b, 0x892ee7b1, 0x530eb619, 0x45cccb5f, 0x17460486, 0x1d67b9f7,
+ 0x5fc0c962, 0x96191219, 0xc758ee65, 0x748d01b7, 0xef34d14e, 0x899fd8a2,
+ 0x7a5ec1f8, 0x695e794d, 0x3e44270f, 0x1d39f91e, 0x67c10bd7, 0x667bdf79,
+ 0xb9dee71e, 0x87144ff0, 0x7e22cddb, 0xf1430a1f, 0x6c4de739, 0x9714f13e,
+ 0x7c93344f, 0xeb4e5c58, 0x978e3a95, 0x2fec87f7, 0xadd2f8e2, 0xfdff6afa,
+ 0xe086bbe4, 0xc4a77be7, 0xf3884f38, 0x67d9acaf, 0xecc30a34, 0x1a3517d9,
+ 0x73b31fd4, 0xae5fbe04, 0xdff78183, 0x34e1f0b9, 0x1df7db94, 0xa9d6f81f,
+ 0xec1eb4d9, 0x7a1274ad, 0x3ac58b2a, 0x81f44155, 0x7e8807ca, 0x784dd2b3,
+ 0x58bd72a8, 0xfda8aaa7, 0x628dca9d, 0xeb16aa9d, 0x3eba56d4, 0x74f9ee6b,
+ 0x987cdfa7, 0x2857a83f, 0x9779e11e, 0x436f42e9, 0xf3c8979d, 0x1da2e78e,
+ 0x9bfe213f, 0x779d57ae, 0x7d74dc1d, 0x0c497e50, 0x8720ef5c, 0x5fda03ef,
+ 0x027576fd, 0x8feda23b, 0x539c839a, 0x3007eb7a, 0x7a17ef2e, 0x41f0c73c,
+ 0xa68b1fe4, 0x863c7fa0, 0x76fe4446, 0x475c14c6, 0x5d24d98f, 0xd91ce9c4,
+ 0xeda7267f, 0xf3a61da2, 0xdda21dfb, 0x4ed3933d, 0xfde74f49, 0x59ff642b,
+ 0xfa4b769c, 0xc9574e0e, 0xfdf8b3fe, 0x69de9cd5, 0xfd053d9e, 0x07283e75,
+ 0x8c0bded0, 0xeba027fd, 0x1fe5342f, 0x35bf3b40, 0xb404d165, 0xd3fa0373,
+ 0x569f8c64, 0x6a7a401f, 0x6e1d66c6, 0xc331ecbd, 0xe37de0d6, 0xbc3a45cd,
+ 0x7b9f426f, 0x137de0d6, 0xe74afe07, 0xcca4df7f, 0x9e906b1d, 0x8759b396,
+ 0x7f406dfa, 0x8e7bec9d, 0x77bb65a4, 0x327512dd, 0x5a0e0dd9, 0x1deab337,
+ 0x3e4a6eb4, 0xb4519f8f, 0xf5c664d6, 0x38293143, 0x378a198e, 0x483587a9,
+ 0x6f30af2b, 0xefb0f8c0, 0xab51e589, 0xe91cfcf1, 0xbe3f44d1, 0x171b1ffa,
+ 0x7ebd411c, 0x8c35f84f, 0xafd08abb, 0x13b13f31, 0x28b0d5c7, 0x5f589176,
+ 0xc28b2e30, 0x9fe98a38, 0x6653c449, 0xf4144f41, 0x15a78134, 0x53d469fb,
+ 0xd19ac7e9, 0xbb78e20f, 0xf316c1fa, 0x41dcf255, 0xbfbaa0fc, 0xca9f83f0,
+ 0xaf387675, 0xbb56b9c3, 0x62eff992, 0x54057fd1, 0x1cbbfe53, 0x2eff943c,
+ 0xc558f98d, 0xdbf2eeb7, 0xba6ab5e5, 0xd8b1f9eb, 0xf5f14747, 0x1f38b665,
+ 0x488df397, 0xd8afc90e, 0x97e36be4, 0x0bacbfba, 0xf6f3f270, 0xc5bcfc7f,
+ 0xcb8ea139, 0xfde1c589, 0x5fbb9392, 0xffaf0277, 0xd785eb50, 0xfaf9cf3f,
+ 0x31e7fadb, 0x9fe0d7c9, 0x591d255d, 0x9d1d6fb8, 0xec9f1ce8, 0x65710fb7,
+ 0x98502d37, 0x3f03141c, 0xde26fee7, 0x65db1139, 0x77aca11d, 0x8beef56c,
+ 0x6cff91b6, 0xb683eef5, 0xfb957f91, 0x6e4f69a0, 0x105a7f23, 0xf48db8ef,
+ 0x6fe78321, 0xcdfdd542, 0xc0f9e64c, 0x6fdf08ae, 0xeb375bbd, 0x0e7be615,
+ 0xf5bc1e30, 0xd406f3d2, 0x76dbf38f, 0x58fcc48c, 0xea89ae9b, 0x8a5eda1d,
+ 0xc7c50f05, 0x96196f4c, 0x3ced69d4, 0xbc8cf65e, 0xfa5f5543, 0x74bb8d08,
+ 0x6e0bcd7b, 0x95e4bd76, 0x9cf45933, 0xadfc8b9f, 0x0eeb29bb, 0x7f244f6e,
+ 0x3a66c357, 0xa9d12f1f, 0xfe254ceb, 0x79c79934, 0x9e8d5ee7, 0x73e3f98d,
+ 0x325a4f7a, 0x66eb6543, 0xef0c27c3, 0xdaabd64d, 0x67543c71, 0xe5c9c6ca,
+ 0x8bec5ab7, 0xbef82c9a, 0x366e2f73, 0x84affe60, 0xf7c4efdd, 0x80c2fd6f,
+ 0x6bd574f2, 0xfd9f80e1, 0x9e47fe7c, 0x5ed82b17, 0xae8df943, 0xaa72c179,
+ 0xd56d7293, 0xcf28227a, 0x5c466da5, 0x2f3c1b59, 0xab1e5dd7, 0x579efb74,
+ 0x2fa55f90, 0xc70e3eff, 0xefe359f7, 0xe6f75e28, 0x635eb707, 0xb1f6b07e,
+ 0x0cf8e3a0, 0x973c2eb8, 0xb83f221c, 0x63fc8935, 0x33dd38d7, 0x701b9c52,
+ 0x7a5cd6f9, 0xe7a9f316, 0x2cfe7e76, 0xd5fdbb8e, 0x3f51d32f, 0x524edb5d,
+ 0x37d9411d, 0xd075a0da, 0xb77e857b, 0x8692d8bd, 0x3db690fb, 0x6dd7a42d,
+ 0x6c5b2e3b, 0xd8797d43, 0xa90a7b55, 0xaed56ece, 0x255c2b02, 0xadbd43ee,
+ 0xc85d41ee, 0x83cb1db9, 0xcb6b77e7, 0x5f77e783, 0xdddf9e0a, 0x8e3c775f,
+ 0xe40411d7, 0x50ceeb79, 0x79b743bd, 0x8e4c13de, 0x1e759f6c, 0x835d461b,
+ 0x79e25f3c, 0x8e274bd3, 0x9e419c5b, 0x790841ff, 0x199aef96, 0xf325f64f,
+ 0xaa4975db, 0xcff23a3c, 0xc9fe03d3, 0xc9ad9fba, 0x6bf256f6, 0xca47aea2,
+ 0x52e6adbf, 0xb54bd61a, 0xb0d23beb, 0xcf64a43e, 0x6d57647b, 0x501a8ebb,
+ 0xde5be5ae, 0x5b1ca037, 0xc32f32f5, 0xc0da6ceb, 0x10f5e3fb, 0x8e4c36a2,
+ 0x8e47ca47, 0x98c6f31f, 0x896d71c7, 0x2de579e5, 0x5caf3cb1, 0xbbbdf5cd,
+ 0x8b20f27c, 0x7dd7ec46, 0x50f253f2, 0xcd57cd7e, 0x98be4bd3, 0xf9372f90,
+ 0x677455d7, 0xa3aea097, 0x52ec7210, 0xb1e8c147, 0x41ef2b44, 0xdb6dbb10,
+ 0xda2aebcc, 0x85179c42, 0x67e8abaa, 0xd5e76109, 0xe8a7ab3d, 0x8ddf9e7e,
+ 0x5678318f, 0xbe7fec9d, 0xea0fae7f, 0x46496deb, 0x41f1868f, 0x899ad71b,
+ 0x7399de74, 0x1afe5103, 0xd691e823, 0x11639ac6, 0x3cca448f, 0xfd198773,
+ 0x3cf7ffd3, 0xa89fe300, 0x0f26e84f, 0xcf76f790, 0xdfa200f2, 0xb003cdb7,
+ 0x3bce9800, 0x0a8e515c, 0x1e5f08cb, 0x78feada0, 0xbcf3ca14, 0x698e973c,
+ 0x4f7dc2ca, 0x53074fe1, 0xe8e0ba7c, 0xb6f9d8c5, 0xcde97a20, 0xfbb8f2bb,
+ 0xee711667, 0x8b061833, 0x4b1aedbc, 0xdeb6f28f, 0x5fdd5db8, 0x1c72edc4,
+ 0xbad45f0b, 0xfe7f5fd1, 0x389f1e13, 0xf74c3e0a, 0x9c4a7fdf, 0xd89d7899,
+ 0xe1a63517, 0x27472df7, 0x3f60b71c, 0xd4fa79df, 0xca2714a9, 0x707874f3,
+ 0x9d3cfaaa, 0xe2fa67b5, 0xab2d27c8, 0xf5b9e2a6, 0x11adb42c, 0xcb67fc3e,
+ 0xd8afcc8f, 0xf85f6aa7, 0xca7fe1c0, 0xd7cac9fc, 0x7a881ebe, 0xd7ee6b33,
+ 0x66b7a899, 0xea30fdab, 0xd751c1f3, 0xe50adf93, 0xfb6fbf47, 0xe973723e,
+ 0x07c71c08, 0xdf9a1e95, 0x110f2b5f, 0xb4fb50fe, 0x52160f05, 0x1edfcadd,
+ 0x983aa02a, 0x6b5fc28b, 0xb818b763, 0x35d7519f, 0x2dd7f894, 0x41aea0f4,
+ 0xa2666f3e, 0x7380f3d0, 0x0fcf6ec4, 0x3c0edef3, 0xe506fc3f, 0xe3ce7802,
+ 0xce06eeb7, 0x7db93ba3, 0x8e89e7ff, 0xe79b2b04, 0x252f87c2, 0x43b3effb,
+ 0xe5d6cfed, 0xf77e836b, 0x3f0a7cf6, 0x3bafae5f, 0x18e38896, 0x2274ea3a,
+ 0xa0bbf0ba, 0x757e8f4a, 0xe8f4782e, 0x1343e79f, 0x8ab10bd1, 0xb022e186,
+ 0xbb062e11, 0x3883d781, 0x0d819ce8, 0x9e2c1ed5, 0xa7e6b728, 0xa71f195b,
+ 0xa23e7958, 0x1474ef26, 0x913b27be, 0x46dbc1fb, 0x05e7483f, 0x73a0aba0,
+ 0xc652fbf2, 0x6df9c10f, 0xe519e6f7, 0x058750f9, 0x414a6c71, 0x64dfb60e,
+ 0x8186f2e5, 0x29dd6973, 0x4e5e0932, 0x923c59e8, 0xe7427a8d, 0x1e42ec9a,
+ 0xc9e88fbd, 0xba9a6d4f, 0x61a7c706, 0x97fc59d7, 0x4d79106d, 0xa38d054f,
+ 0x2d22a125, 0xe9c71331, 0xf8a56f1c, 0x7fdd22af, 0xfccd385d, 0xbd1bd60f,
+ 0x0c48758f, 0x4875143f, 0x4875137f, 0xc48758cd, 0x3ff30cf0, 0x62bf4b88,
+ 0xe011b92f, 0x053ed5b0, 0xa75594f9, 0xb347efa3, 0x96e29bea, 0x9673f1f9,
+ 0x1bfc40d5, 0x38e3ebba, 0x793107aa, 0xd8576fc7, 0xeb136ea3, 0x5ea7acc3,
+ 0x9577f1a4, 0xac8bb737, 0x921a33fa, 0x13c7abf7, 0x7d71feb9, 0x68bfab6c,
+ 0x4d8c3941, 0x71c5cfb1, 0x0d6be284, 0x2e316f5b, 0xa3a5f1f3, 0x7b65f217,
+ 0xe42f4742, 0x1c0550cb, 0xbe4ae3c1, 0xa23dbe7f, 0x73c63863, 0x836a77b7,
+ 0x7ec8cdd6, 0xf620adfd, 0x455e5cdb, 0x0100df62, 0x1c1c05df, 0xa3ed25f5,
+ 0xbaf0342e, 0x1d3afaff, 0x7ea4dfe5, 0x693ee7c9, 0xc4baf1e5, 0x540c7ba1,
+ 0xcf7dbe47, 0x624b81d9, 0x9703af88, 0xad6bfeb2, 0x999f3883, 0x75de603d,
+ 0xbdcba8fb, 0xe6c0e710, 0x9e9f3c42, 0x1077dc6b, 0xd4df3259, 0xd3e7885c,
+ 0x3794530b, 0xfad91711, 0x6973c44f, 0x38b62759, 0x544dff23, 0x453969b1,
+ 0xbf18dfe4, 0x1f31eea8, 0x6fcfc78d, 0xc5a31817, 0x5d722bc7, 0xb7d1524d,
+ 0xf556f4a6, 0xa01b6c9f, 0x9bef976a, 0xd544319a, 0xf46e720f, 0xe6f9d7d1,
+ 0x04f1c6cb, 0x57ce438e, 0x90fdbfce, 0x0f2e3016, 0xece8379c, 0x9fe654ba,
+ 0xb4ff0b96, 0x3a72ec7c, 0xf46db8af, 0x0c87a463, 0x29f91f69, 0xce1c4f54,
+ 0xd762b464, 0x0962ef1b, 0xe8782956, 0xffb930bb, 0xf393eef4, 0x1782fd1e,
+ 0x5f3cf220, 0xfaea33f1, 0x6a2d92c9, 0x80a5ecba, 0xba9d6ffd, 0x7835a77d,
+ 0x7a7765bd, 0x484fca12, 0x3fa813bf, 0xf1245f72, 0xfbfc63b6, 0xbbda9ee8,
+ 0xfbb49394, 0x21cabe4f, 0xefd40fbb, 0x7bf8ebec, 0xdfabc7b3, 0xede8447f,
+ 0xbd1c29f3, 0x15ea27f6, 0x8fe8bf89, 0xdb5e6c97, 0xeed1387b, 0x16eaf658,
+ 0x972bc8ab, 0xdbdb5bed, 0xab0ebbec, 0xe0fd559a, 0x8a9d6521, 0x4d5fd35e,
+ 0xe75fc86f, 0xff287f7f, 0xd9beb2ba, 0x2b63f580, 0x8fc8509f, 0x7c43f575,
+ 0x50b473fc, 0xc84fcc11, 0x785ad3f6, 0x4cf9ce80, 0x4e9fe48d, 0x307db3c7,
+ 0xf9892fa3, 0x68f57f9c, 0xf9e7ea1a, 0x3d8fbe04, 0xea9dbcbd, 0x5aeab355,
+ 0x1d9a3f28, 0x6593f9c5, 0x5fa0d26a, 0x768e2f6a, 0x6b90fd63, 0xa7e52c45,
+ 0xc08731b3, 0x3b06e7fd, 0x7eb8b4db, 0x767e2201, 0xfa78c06c, 0x6a8d1a2f,
+ 0x118f687d, 0xf27637fd, 0xebc0c1f5, 0xff201708, 0x66061f85, 0xbcc7aeca,
+ 0x9da3b5cf, 0x7a72d69e, 0x9df68a4c, 0x7b1f7027, 0xb499db98, 0x839ed70f,
+ 0x149e7916, 0xd942cecc, 0x929fb491, 0x18865503, 0xf1b2bb7f, 0x7e6505ef,
+ 0x57dabbe0, 0xed8f4a5a, 0x6bedc2cb, 0x2857d910, 0x67ad70fd, 0xd1f24d7c,
+ 0xeff3afd9, 0x27c543de, 0xf54e9390, 0xd9bbf293, 0xe2dce223, 0x9acdbd5e,
+ 0x6c7bcdd0, 0x23b2becc, 0xbd71723a, 0xdf2ef691, 0x2edfc727, 0xd7ecb7d6,
+ 0x67e6e52f, 0xe99d5c72, 0xc9484bb3, 0x6f09faa0, 0x27ea28dc, 0x8746e302,
+ 0x728f5f3d, 0x3ac7b93c, 0xf65dce9e, 0xecf8a4cc, 0x0cee02a4, 0x50767baa,
+ 0xdd4d4d1d, 0xfd78b1dd, 0xc9c584e8, 0x7a15ee5c, 0x94201f91, 0x2fbb27eb,
+ 0x49f4fd06, 0x8f10e83d, 0x4cc8eaf4, 0x7acb71a0, 0xd5be1b88, 0x1ad7ef77,
+ 0xbbc606af, 0xcebc57df, 0x7c9eda7e, 0x5de2ca37, 0xc435ca57, 0xc1b95ebb,
+ 0xfa46f5d5, 0xb37a2edb, 0x9f8de991, 0xbc37b67e, 0xcedbeb4c, 0x9d91cf43,
+ 0xd6f7191e, 0x796e484f, 0xab3fa4e9, 0xf557f3c4, 0x49135bb7, 0xe3debc9e,
+ 0xc4dfa1c2, 0xe23af971, 0x53c03ce9, 0x9f07e745, 0x166dfdee, 0x9f4fadfa,
+ 0xfa508a7d, 0xab134ff1, 0xe5fef0b2, 0xb4aebe1a, 0x246a7a6c, 0xfa5bfbee,
+ 0xb9448d56, 0x69bf7f6b, 0x02c33364, 0x3eee7a44, 0x2d70bdf1, 0xdd338f8f,
+ 0x8f3fdef4, 0x1efb4dda, 0xae9ab8d8, 0xa48a6eb7, 0x53e87dfa, 0xdc6dfbcd,
+ 0x26cefd4c, 0x253dff3b, 0xb49f39c8, 0xadf62093, 0x9f053f5e, 0xc0eff943,
+ 0x1f3adfeb, 0xfb215c3e, 0x56f6132b, 0x5ffffc0e, 0x7f0f97e1, 0xb023f51e,
+ 0x453ebe8e, 0x42fb63e4, 0xb39e715f, 0x792ae537, 0xf87520d8, 0x3adefeea,
+ 0xeb4113fc, 0x40fdc7f0, 0xa929f875, 0x3c34df7c, 0xf99d7829, 0xaf591485,
+ 0xf1c46397, 0x1fd7aa85, 0x9df4b50d, 0x246858f3, 0x083a19bc, 0x21d260ed,
+ 0xc21c878e, 0x9c20e009, 0x93841508, 0x0a708aa0, 0x834e12d4, 0x97594246,
+ 0x4843290d, 0x67fbf23e, 0x8c71fe10, 0x0d31ebb0, 0x8c6fdcfc, 0x18d333a8,
+ 0x3fee5a3d, 0x7ddf5432, 0x01d8eafb, 0x982151e6, 0x1b8aab5d, 0x0fa87fa5,
+ 0x21fcaefc, 0x793df75e, 0x61fd06b9, 0xdc15efe8, 0xfbe7bf54, 0x69e1e13e,
+ 0xf880bdf4, 0x7532213e, 0xb7cc34f5, 0xc0bdfb76, 0x31e42d00, 0x05b5498c,
+ 0x9fc02f7c, 0x19d122bf, 0x30f28a91, 0x16fcd3a6, 0x7741fb0b, 0x7b18b447,
+ 0x7faf2a4c, 0xbf6ffc58, 0x34fa8be8, 0xffad953a, 0xd4e6ec41, 0x2f492fa2,
+ 0x75fbfd65, 0x7c04cea9, 0x4afa2bbe, 0xb73dd63a, 0xaebe3b0d, 0x5bcdf509,
+ 0xd57c5fef, 0xbf0203ef, 0xafac0807, 0x4befcf67, 0x2c76d7cf, 0x84d5f3a3,
+ 0xd7f386e3, 0xb0df5f50, 0x5f7d1f7b, 0x07f8ee30, 0x2dc17df4, 0xf7d1341f,
+ 0xbcf67b05, 0x02fbf417, 0xf1a337a9, 0x61fe02fb, 0xe05f7d12, 0xefa79fd3,
+ 0x5034f5c3, 0xf7e0c68f, 0xae5fd405, 0xab7e5f87, 0xfb020bef, 0xe9336a15,
+ 0x157bdefb, 0xdbf77d1b, 0x57dfe462, 0xc5234195, 0x3e1ef761, 0xcbfae169,
+ 0x9c5f35e3, 0x4bf298b5, 0xde605fb2, 0x4a71e64d, 0x875ea83f, 0xef8977d3,
+ 0xdc30d8d0, 0xa215df38, 0xd7ad77d7, 0xe22a9198, 0x02f7e135, 0xafc205e7,
+ 0xdcf7172f, 0xe50069bb, 0x09672145, 0x67875ff8, 0xea4f7e78, 0xf97bd4b7,
+ 0x81eb15bc, 0xffb949d6, 0xf663e40f, 0x9476110b, 0x560bf64f, 0x3ae47f5a,
+ 0xf009cf27, 0x9f851e33, 0xc4ef88af, 0x1023cb82, 0x32f62b4f, 0x8630cfd4,
+ 0x0c618c31, 0x18c31863, 0x318630c6, 0x630c618c, 0xc618c318, 0x8c318630,
+ 0x18630c61, 0x30c618c3, 0x618c3186, 0xc318630c, 0x8630c618, 0x0c618c31,
+ 0x18c31863, 0x318630c6, 0x630c618c, 0xc618c318, 0x8c318630, 0xff0eec61,
+ 0xa39b150e, 0x008000cb, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+static const u32 EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x13f84186,
+ 0x21b4c2c8, 0x7367db88, 0xc64addfa, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0x8fedb6db, 0xf654c65f, 0x008000f9, 0x00
+ };
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0,
+ 0, 12265);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1,
+ 8192, 7065);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2,
+ 16384, 93);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3,
+ 24576, 93);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4,
+ 32768, 93);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5,
+ 40960, 93);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6,
+ 49152, 93);
+ INIT_GUNZIP_DMAE(TSEM, TSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_TSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7,
+ 57344, 93);
+}
+
+
+{
+static const u32 EVST_USEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+ 0x7ff8, 0x7ff8, 0x7ff8, 0xe6f, 0xe19, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x419, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x3e5, 0x3e6, 0x3e7, 0x3e8, 0x1e2, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xd49, 0x7ff8,
+ 0x7ff8, 0x9dc, 0xd49, 0x9b0, 0xb3e, 0xd30,
+ 0xd49, 0x9ed, 0xa07, 0xa12, 0xc97, 0xa26,
+ 0xa3d, 0xa2b, 0xd49, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xd49, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0xc16, 0x7ff8, 0x7ff8, 0x7ff8, 0xc40, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0xb29, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xc76, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0xc7b, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x13f5, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x1446, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x221e, 0x7ff8,
+ 0x22af, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x221e, 0x7ff8, 0x1ef4, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8};
+ INIT_MEM_WR(USEM, USEM_REGISTERS_INT_TABLE, COMMON,
+ INIT_HARDWARE, EVST_USEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE,
+ 0X0, 256);
+}
+
+
+{
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0[] = {
+ 0x00088b1f, 0x00000000, 0x7ded0300, 0x4554780b, 0xdbdd7096, 0x9ddfb7dd,
+ 0x90f093ce, 0x1bc884dc, 0x0108486c, 0xc0427683, 0xc8b63820, 0x362a0e3a,
+ 0x91e1210f, 0x59718604, 0x00eedd9d, 0x8d186046, 0xf8338a82, 0xa0cc20db,
+ 0x0804cecb, 0x0da09063, 0xa8830e09, 0x71919951, 0xf2023758, 0xe0c48170,
+ 0x7cc38eb0, 0x55539d6c, 0xba6f7ddd, 0xf7ee8321, 0xf983ff7f, 0xaadd4ac6,
+ 0x79d4f75b, 0x4e73a9d5, 0x99891b55, 0xb909db90, 0xf968ff0a, 0x24210323,
+ 0xdf865a3d, 0x9269ebfc, 0x0685c846, 0x26ce6a93, 0x536efc64, 0x5f5a76f8,
+ 0x410a49b4, 0x4ad37e5d, 0x17213e48, 0x957ab237, 0x5ba9f5a1, 0xdd793b69,
+ 0x82d2b640, 0xa4c8736c, 0x16d39080, 0x9d19fec2, 0x6420c932, 0x175595ae,
+ 0x033fda6d, 0x346f2fc6, 0xff7d2b13, 0x0bc18374, 0xa55b25f5, 0xfb689110,
+ 0x5e95279e, 0x2179fc74, 0xd2aadea9, 0x1467d6fa, 0xf2c849d5, 0x117aff37,
+ 0xfae02bbe, 0xaa216022, 0x3efdf002, 0x21286da3, 0x263b43f3, 0xcce3a2f6,
+ 0x64792edf, 0x1bf99dfa, 0xf9edf0a5, 0x190a5cf0, 0xb60bb8e8, 0x903a89d9,
+ 0xe09570c1, 0x4b1e7177, 0xcddfa25e, 0x14eb3806, 0x3dfa339f, 0x022f9f81,
+ 0x1fed4475, 0x957a2fad, 0x57be877e, 0x03c92bf9, 0x8994ac53, 0xff7e9ebf,
+ 0xfdeb1ee2, 0x7e6038af, 0x677f4a35, 0xfe663cec, 0x3f31e606, 0xe89949b4,
+ 0x2936b800, 0xc7468773, 0x1d6db05b, 0x70312d51, 0xc3d7e86d, 0x2faed31f,
+ 0x0d1008bf, 0xf109f33c, 0xfe003bd6, 0xb0cf7290, 0xa477f3e8, 0xc1464264,
+ 0xf8cd06f8, 0xce910484, 0x0309e206, 0xd39349de, 0x4eb74b13, 0x4b6e96b7,
+ 0x09bbf992, 0xd39a79e0, 0x1b8099e1, 0x4c8175cb, 0xa80b9f2c, 0x810be708,
+ 0x18be5881, 0x9ff3e0f0, 0x7cb10a07, 0xf2c5e029, 0x961940e5, 0xec3e029b,
+ 0x7ee04af7, 0xfc06b72c, 0x8197fcf8, 0x0d5f2c72, 0x7ff3e354, 0xf2c32c0d,
+ 0x7c4102df, 0x2ac0ebfe, 0x9d00772c, 0xb02bb968, 0x81ddcb01, 0x3d7bf610,
+ 0x3dcb0db0, 0xfe7c7a81, 0x2d1fc053, 0x1aeebc93, 0x524fa523, 0xf6537129,
+ 0x5f3ea920, 0x53d6898d, 0x0f7ab1a7, 0x428d5d7f, 0x0e63d3f1, 0xf5fa53ad,
+ 0x31ad6eae, 0x4bdef6d3, 0xd0567b59, 0xdb42dcbd, 0xf6b256b3, 0xe5be757e,
+ 0x6fdeda56, 0x101f6b3d, 0xa36e5baa, 0xb0b603ed, 0xadf521f6, 0x7db4edcb,
+ 0xbf6b0348, 0xe15eec25, 0x5a5bf5a0, 0xd5af3d58, 0xeb49c2b7, 0x7d594779,
+ 0x0add5b74, 0xf47f7d17, 0xc0bef629, 0x6d130ef7, 0xb9140b1c, 0x74a5ebcb,
+ 0x42e7411f, 0xef59017a, 0x450efac1, 0xdac7dfb4, 0x9c1ebccd, 0xbe52f5ee,
+ 0xfde265da, 0x9ed8c3c9, 0x6707fa27, 0x1e3176b3, 0x9e7ac729, 0x10bf8c59,
+ 0xef23bbeb, 0x47f7c62f, 0x11ffde45, 0xde4777d6, 0x8ffb0c7f, 0x2fffbc8a,
+ 0x023d7f58, 0x8fac0aff, 0x24ffc08e, 0xbfc08f6b, 0xe047b596, 0x1efac3af,
+ 0xe93cfdfe, 0xd6906f39, 0x97fe4917, 0xe5db9f80, 0x3a0272ea, 0x04ce18cc,
+ 0x22527e39, 0xfe5c83f7, 0xdf915123, 0xf149bc9f, 0xf8efbc82, 0x862bc15d,
+ 0x69e3ce6c, 0x8bfb9f50, 0xf38e1235, 0x7697900b, 0xefd38e85, 0x388ce3fa,
+ 0x6719a85c, 0x3172e1c4, 0x1c71afce, 0xd9c6f75b, 0x16ac7871, 0xc5f3c39e,
+ 0x8e388d38, 0x1af37bab, 0x16914ef1, 0x8a16779e, 0x7e23f671, 0xcf07ba52,
+ 0x7e280fae, 0xbb38e8a4, 0xc9f8a03e, 0x230e71c6, 0x83dd193c, 0x42c3ef27,
+ 0x1f7938cd, 0x3e718b96, 0x757a7842, 0x1f5d9c6f, 0xf3c2d58e, 0xce317ce1,
+ 0x6fa71c71, 0xf795e6f7, 0x9e169151, 0x718a168f, 0x7271c73e, 0xeece37ba,
+ 0x67f96a3f, 0xfc231ff7, 0xd3f11173, 0x1af37bbf, 0x7f9689f5, 0xe1127d46,
+ 0x7842ff9f, 0x9c6f7706, 0xf9689fdd, 0x1127f767, 0x8c1221fe, 0xf37bbc33,
+ 0x2d27f51a, 0x53fa8cff, 0x38ac7f84, 0xc1eec8ce, 0x5a67faf3, 0x59febcfc,
+ 0x38293f04, 0xe0f7414e, 0x8b427d19, 0x2227d19f, 0xe38de9f8, 0x38deed8c,
+ 0xe2d09faf, 0x1113f5e7, 0x38e2e4fc, 0x5e6f75b7, 0xf16a4fa3, 0x0464fa33,
+ 0x9c70c33f, 0xa10f0e12, 0x3c4b0ce3, 0x5a739ece, 0xc739ecfc, 0xd5b233f0,
+ 0x76d1706f, 0x00f12653, 0xfacf6338, 0x376d1282, 0x0abad1a6, 0xa9f897a5,
+ 0x7ac2357e, 0x6e5e143f, 0xbb681a0b, 0xc8f27b73, 0xbaec6a35, 0xa24e325f,
+ 0x97cae87c, 0xbb8ef635, 0xa7a9a6c8, 0xec68a694, 0xbd29b482, 0x698cf534,
+ 0xe67a9a39, 0xef358383, 0x52339af7, 0x70b3ef53, 0x77dea6ac, 0x7de68969,
+ 0x6a77c7f5, 0x4e5673da, 0xd773d4d5, 0xfbd4d74e, 0xa9a59faf, 0x5f38dc0f,
+ 0x2de0de33, 0xa1f5344b, 0xd4d31fdb, 0xd72c3787, 0x6b4d3dd4, 0x2d91f534,
+ 0xcfc66acf, 0x4d33f23f, 0x66e8e0bd, 0xf8f0bd4d, 0xc7f79a6b, 0xb3a9da9e,
+ 0xd3ee1cab, 0x00dd7843, 0xed1db476, 0x055f734b, 0xbee2e4ed, 0xda3fac16,
+ 0x47f581d7, 0x700ff36f, 0x04fe3a53, 0xeb43185e, 0x7716ff8a, 0x528fbb1c,
+ 0x5099264e, 0xd85265fa, 0x89957db5, 0x8be519f2, 0xfd2bac92, 0x9565a33f,
+ 0x993fd1dc, 0x1721ff96, 0x560f8007, 0x81da324a, 0x06a90376, 0x099bb1be,
+ 0x9baae1f2, 0xc6095e0b, 0x6ceae1f0, 0xb8c5e7a6, 0xfceb23ab, 0xd75841db,
+ 0x3d78949f, 0xe1d71078, 0x5c15b327, 0x1cd6d797, 0xe973070c, 0x668fd978,
+ 0x516add82, 0x0b1c3da8, 0x19e1428f, 0x033cf08a, 0x009f3cf0, 0x42ff4b1e,
+ 0x9cd63c0d, 0xd63c0d72, 0xbef05d88, 0xd0f79e0e, 0xdb3278ee, 0x55fff582,
+ 0x48385ef3, 0xb392c485, 0xa559e10c, 0x3c0d7290, 0xaf3c08b6, 0x036edc80,
+ 0xe0e3d278, 0x2d58ffa7, 0x6be6727e, 0x73b113f1, 0xf9e0e98e, 0x86c7e398,
+ 0x7cd7d6f0, 0xf393f0cc, 0x998fc318, 0x1e16277e, 0xbb5e8457, 0x246f3f01,
+ 0xa032c780, 0x7e9f8b48, 0x11f8b50b, 0x4cf91676, 0xc71b4f07, 0x39e1038f,
+ 0xf0c6d350, 0x08c7efd3, 0xed5cd98f, 0x7326d371, 0x043aad96, 0xed9a857a,
+ 0x240807a4, 0x1068eefd, 0x7a4214ac, 0xca54b212, 0xb51eb841, 0xfda5be51,
+ 0xbf28db2f, 0xef83bec2, 0x9f6ce627, 0x7694fca9, 0x095aa121, 0x5c9511f6,
+ 0xb234e636, 0xfba1167d, 0xbc299bb0, 0x5d2f1b17, 0x7f8513fe, 0xa81196ce,
+ 0x10a4a8d7, 0x9f08ffe8, 0xe181955a, 0xdf5f1087, 0x263ea87b, 0xa9df5f46,
+ 0x0bc9b0c3, 0x047991fb, 0x0722ec61, 0x4e99d48f, 0xebc8c5b7, 0x7ada0dbc,
+ 0x175b4845, 0x9fc31770, 0xe9a7ef14, 0x7dd085fe, 0x3fba09c2, 0x898cf280,
+ 0x70a3ec3c, 0x1bfba29c, 0x63cac4a2, 0x546feb0d, 0x3ce9336b, 0x1e4b974e,
+ 0x6079123a, 0x04e1cced, 0xef419e36, 0x9c2973ef, 0x2ff111f7, 0x77e7e70d,
+ 0x0cabb833, 0x597911ec, 0x00956d0a, 0x6227aa6e, 0xf61fc8f4, 0x5c429a2d,
+ 0xef0bd7d8, 0x97cf9f7d, 0xdef82d18, 0x21c9998c, 0x6de62f58, 0xf7bcd548,
+ 0x9776d203, 0xaa43d70f, 0x3ff7e82c, 0xefb6fbe5, 0xd53a6fdf, 0x6dafd316,
+ 0x5089b343, 0x69bdb53a, 0xe9c3caf7, 0x3b6d7e7b, 0xefd23345, 0x07ddfe21,
+ 0x0fedb5ca, 0xeb02b713, 0xbad543dc, 0xe3f4cbe7, 0x1c28f050, 0x54fc04b3,
+ 0xb35c0191, 0xa0ccdb79, 0x55ecffb6, 0x3e86a0a6, 0x02950f94, 0xa9073fde,
+ 0xf1c2f38f, 0x4fed75fa, 0xd1d41fe9, 0xde8f183f, 0xffce9fff, 0xaab9d06f,
+ 0x54f538b1, 0xd51777cc, 0x153d4a4f, 0xb6c16fd3, 0x8af5347b, 0xfd340fd0,
+ 0xa9986de7, 0xaea47f69, 0x7b3ed342, 0x7d4d62d5, 0x349ff066, 0x565e1ffd,
+ 0xa87f69a3, 0xfda6b57a, 0x3467f281, 0x5ff81ff5, 0xfefff4d4, 0xed349bfd,
+ 0x59159bd2, 0x52aae7e0, 0xc13d59fc, 0x3347f73f, 0xf9452cd9, 0xd9f5f056,
+ 0x5f962640, 0x6b2c5404, 0x7d52ff40, 0x6561ef2e, 0x5999e6d5, 0x9f05b7a0,
+ 0xf755319f, 0xe57476ad, 0xd57ebd4f, 0xd7fd21f3, 0x4492ec1b, 0x1285a17e,
+ 0x6f1e81f1, 0x227d9897, 0xebe49f9e, 0x51cb211b, 0x4c2a16be, 0xecee16fe,
+ 0xb0f20259, 0xaff70950, 0x971e2476, 0x8f384bd4, 0x6a6f508a, 0xb3d2c614,
+ 0x363e0e9f, 0x06fdf9fe, 0xac257efc, 0x7ec06387, 0xe1966df6, 0xbee6e1fb,
+ 0x78030ef7, 0xb4c8afbc, 0xc74c691f, 0xa07cee75, 0x1194f52c, 0xf2c3e7f0,
+ 0x2c7ee06c, 0x58fc074f, 0x63940a9e, 0x8d502279, 0x19605b65, 0x82069f96,
+ 0xac0f1e58, 0x4093f2c2, 0x02c7961d, 0x43fcb01b, 0xc5e58420, 0xc14b1780,
+ 0xd0b7ffa7, 0xb7ff9555, 0x91dff5d3, 0xaaae9c8e, 0x70f066ec, 0xc1d5aeba,
+ 0x380b4a2b, 0x557be805, 0x116f6666, 0x9efd1daf, 0x4d7fc29d, 0xca0fcc6c,
+ 0xf4edd7fd, 0x67e856ef, 0xe8481fac, 0xbf439d78, 0xe77e0fe9, 0x00d463ce,
+ 0x3f3c4ecb, 0xe212fd3d, 0x6be50481, 0x6366dfe1, 0x9550a578, 0xac849191,
+ 0xcf1bf419, 0x9237562c, 0xdebf7814, 0x8e07eb13, 0xed380b8c, 0x39557e06,
+ 0xcde7d987, 0xf08f8606, 0xcebdcf2e, 0x9956bf28, 0x5f83fa3b, 0x4cc9fc9b,
+ 0xeb235d60, 0xe058dfb9, 0x02eac82b, 0xe3a7ff5f, 0x6d74a4e3, 0xd097b47c,
+ 0x7d9c45fd, 0xe61be8db, 0xc0bed6ab, 0x7f813b57, 0x0d9dfbe9, 0xd0c89203,
+ 0xc90f38e8, 0xebebe32a, 0xd0f3bde0, 0xefb02e2b, 0xeeca6497, 0xf1897953,
+ 0xdb3ea8b7, 0x6f9988ed, 0xdeb6a355, 0x31952759, 0x349a837f, 0x47e8186d,
+ 0x2e54fbb7, 0x2c4cb1e8, 0x324b38c5, 0x54a9f715, 0xb84217e8, 0x9464f6c9,
+ 0x16022fcb, 0xc35df7ec, 0x289c6891, 0x24e40d1c, 0xf4581f7d, 0xfdc4bf6a,
+ 0xf19df213, 0x38fc052b, 0x1974c9a4, 0xfd0b0bec, 0xfbb055ff, 0x62eb1188,
+ 0x437aaadc, 0x3c0b7cd0, 0x1ef9aedf, 0x31154f7d, 0xd739abb0, 0x39236fe2,
+ 0xaa8ff82d, 0x3760a5f2, 0xeac6dc62, 0xc92fdad6, 0x63557a9a, 0x9ec6b74f,
+ 0x9ea83f81, 0x11928523, 0x67216af8, 0x3696458b, 0xe6594fc5, 0x816cd86e,
+ 0x58e8d27f, 0xab785125, 0xb3bfd624, 0xb77dc561, 0x0eb3d0aa, 0x8f87abe7,
+ 0xa31eefd2, 0x0bfc3131, 0xfa8f9d0c, 0x8bfff0e2, 0x4f94ffc0, 0x1fccca17,
+ 0x17412c40, 0x0cc921c8, 0xfca2a6ba, 0x3f044710, 0xbf426730, 0xe3175313,
+ 0x875b7dd0, 0x7264ded6, 0xfb665e77, 0x5f77fd7a, 0x1ebddfe3, 0x7fb72afe,
+ 0xade61130, 0xe36563c7, 0xe31f8a97, 0x057ff469, 0xfc0a3c51, 0xbdf06dde,
+ 0xcfe3a066, 0x0299f6df, 0x14d675f2, 0x35f8ffec, 0xf8577ef4, 0xeda7991d,
+ 0xd92e79d1, 0x7f7b44ed, 0x0e3c33c9, 0xf0ad2419, 0xfc8559dd, 0xaf6857c3,
+ 0x8ae83818, 0xa882e44f, 0x81e22d7d, 0x02a0939f, 0x8673cc7e, 0x9bb002ba,
+ 0xc02c3567, 0xfafcc5fd, 0x23f80a4d, 0x0cb9102e, 0x7c8175f0, 0xa18bcae8,
+ 0x0506fbd7, 0xd9da82f9, 0xa4e16227, 0x4ea6b676, 0x7d4d6ced, 0x019a992e,
+ 0xebb9b3f1, 0x8f6b744d, 0xbfb4d4f3, 0x6bfa6065, 0x05aea91e, 0x4364e4bb,
+ 0x02b77dde, 0xa97f5e1d, 0x8b3bf000, 0x014ef736, 0x78807e3c, 0x2bf7debc,
+ 0xaec8ffa0, 0x1bbfe870, 0x9c5d5be5, 0xd161e394, 0x8a1bc936, 0xb9c737c3,
+ 0x75fc16be, 0xffc3c78e, 0x3251e5cc, 0xcbc9d2b2, 0x34cf961b, 0xbbcf91a2,
+ 0x033ffe0d, 0xad39093f, 0xfa4cf902, 0x7667e316, 0x7e325f19, 0xd1f7e397,
+ 0xdf1d05ca, 0x9f8e9df9, 0x9efe05db, 0x135fc6f1, 0x75834cb0, 0x55692d65,
+ 0xd21ddf81, 0x7f283ad1, 0xf411b52a, 0xa57dd3e7, 0x04938e91, 0xdbfd5083,
+ 0x870d756e, 0x5250f24a, 0xe9dc6a03, 0x8df66a31, 0xdd468549, 0xcd1c923e,
+ 0x7074f3a5, 0x462fd038, 0x37f64eeb, 0x43cd3471, 0x68e3a2f9, 0xa449b7f6,
+ 0x74adf70d, 0x64f3cd3c, 0x4a9eb6af, 0xa5fa0954, 0x4f9f6996, 0x5fd03834,
+ 0x0e413c96, 0xe55e3199, 0x4673729d, 0x41b01c0c, 0x19f780ce, 0xc4e9c91c,
+ 0x77fe8613, 0x5a413c39, 0x8c1beca7, 0xd0d26707, 0xb79f20b6, 0x1cdc5e46,
+ 0x09ef0a0e, 0x3a9abc1d, 0x9f535385, 0xa1a6746c, 0x127aa31e, 0xd2c398f4,
+ 0xd2bef0ca, 0x7e983998, 0x0fbfc5df, 0x380b1900, 0x3bf7d81d, 0x86ecf163,
+ 0xbefb3770, 0x7efd39e6, 0x7d1e96a7, 0xf37ab1dc, 0x67f76e16, 0x1a0f7c99,
+ 0x64163ca9, 0xfbe01b55, 0x2e6a9945, 0x694dffae, 0xcb394fc8, 0x5a49c84a,
+ 0xe208ea97, 0x412d7735, 0x876e7bff, 0x2b92fccc, 0xe99ba16d, 0x090b6658,
+ 0xd022475a, 0xbb8865cb, 0x963ca2ac, 0x341f728d, 0x1d4de7d1, 0x3123f225,
+ 0xf87acefe, 0x03ff8e93, 0x7c0177a3, 0xc21ef6bf, 0x96e3d4e3, 0x3ad0fb7b,
+ 0x9c5ef2e8, 0x9f0eb460, 0x57c7f687, 0xd2081d16, 0xb452ea71, 0xa888d3fd,
+ 0x3d001d17, 0x7013fa25, 0xd43c5290, 0x97ef22d9, 0xfaa22aac, 0x1c7be2c9,
+ 0xdc5882e4, 0x456e2183, 0x8f8829c2, 0x168676c4, 0xda5b81ee, 0x41f2da26,
+ 0x2fcc250e, 0xb119d9b8, 0xb660153f, 0x0f510ead, 0xfa7f602b, 0x60503e1a,
+ 0xfea8ba9f, 0xa1976c03, 0x54accb4e, 0x04afa701, 0x20d951e6, 0x62f2fa89,
+ 0x50559f2a, 0x0ef83c47, 0xf0637378, 0xfd869c12, 0x769b78a3, 0xbabdbc4d,
+ 0x8801ea72, 0x36f147f7, 0xa9b7874d, 0x9dcfc007, 0xfdf46f08, 0xba7d5592,
+ 0x57ca278f, 0x93bf00db, 0xc630e58b, 0x42398eff, 0x5bbff312, 0xe3e42ed1,
+ 0x87604a6c, 0x1d21ff08, 0x11c61ea7, 0x13de29fc, 0xb88fd97c, 0x5fff0307,
+ 0x5c04ff8f, 0x7bbd1b9f, 0x8c37bc60, 0x3a4ae9de, 0xe2ed17ce, 0xa7bf7ec9,
+ 0x172a2f34, 0x03cfe1c4, 0x34cb2b3b, 0xa7f000eb, 0xf1726b80, 0x850e4312,
+ 0xb1d619b7, 0xd27ce8f4, 0xfdad0597, 0xbdd33ce9, 0x36e407b2, 0x043fe4cb,
+ 0xdfdd71df, 0xd0508611, 0x93cfe268, 0x12b9510c, 0xc7ddabdf, 0x33b5fbfc,
+ 0xd472d0e5, 0x8c126d57, 0x36a7e517, 0x30753f1d, 0x0cfc6a7e, 0xe9b2a9f9,
+ 0x8d4fc633, 0x8fc02535, 0xdb924d95, 0x71d2c6ac, 0x43c80971, 0x2316cf94,
+ 0x05d964df, 0x4eb12bdd, 0xe6f918f9, 0x03cacac4, 0x78a0df10, 0x3f4b8b6f,
+ 0x7798bf0e, 0x1dd7fa22, 0x50c9f9ca, 0x447835da, 0x46acdcf6, 0x99fa2af1,
+ 0x7bf60a4d, 0x805ff155, 0xb61554ef, 0xd9e80dbd, 0x1743e879, 0x23ae37d8,
+ 0xfbc3f753, 0xa29469ae, 0xcb239f30, 0xa81f204b, 0xd10fce8e, 0x2248e1c4,
+ 0x8fb0411d, 0xc98be312, 0x0d5f0463, 0x64fe219f, 0xafe7d3a8, 0x9d16f8f1,
+ 0x1435da3f, 0x261fb82f, 0x498fe626, 0xc9781935, 0x23f49bec, 0xfb0a8a9d,
+ 0xf63295c9, 0x6872874f, 0x6257fcec, 0x519354bf, 0x7a090f63, 0x9aa37e0b,
+ 0x99f10edb, 0x69df9b1a, 0xafe58f4a, 0x0c4e7b14, 0x20153e3f, 0xee54399e,
+ 0xfaccb747, 0x94c3ac21, 0xc630beaf, 0xb2661ff6, 0x7f44be02, 0x7478dbe0,
+ 0x32f5efa1, 0xabe3628d, 0x968effb4, 0x1bb00625, 0x02cf4bbb, 0xb02e7fbe,
+ 0xf49dea93, 0x5a2482fd, 0xd7953d42, 0x6f7af07b, 0xee3bf656, 0x7cfa2591,
+ 0xf7f6c293, 0x6e2c4d23, 0xc1ee8c49, 0xc91a8f10, 0x399459f1, 0x211bd718,
+ 0x4a57b0cf, 0x7d38c14a, 0x8e9cca10, 0x25e8191c, 0x21d8d8e4, 0x71749d87,
+ 0xb2aa31cc, 0x1c3f3e87, 0xc6bef3a0, 0x41ceeafe, 0x7b3c5f06, 0xe7872275,
+ 0xe3aced86, 0x89b8ec5d, 0x676a5f80, 0xd695353d, 0x525d072b, 0xedcb5e80,
+ 0xcbc6b795, 0x7dc3d447, 0x1719caf8, 0x7e2f03ec, 0xe78b2e6d, 0xc711f90f,
+ 0xfdc0a1d7, 0xcfb09ef8, 0x08394490, 0xb75bda02, 0xff840aa1, 0xcd8c7b50,
+ 0x066aba43, 0x298d05fa, 0x25db5eb0, 0x2dbc57cc, 0x190a7f3c, 0xfa47ef0e,
+ 0xbe54ab91, 0x98fd1b0f, 0xb0987747, 0xbd814d78, 0xc4ea19ba, 0x0ad9ed9c,
+ 0xeccd7ee3, 0x1ffd0b2d, 0x920bcbec, 0x60534aea, 0xc6ca4911, 0x36898b71,
+ 0x1a90515e, 0x263e8234, 0xdfd1b2fd, 0x6ba2de35, 0xb3e2c1ef, 0x8c60c064,
+ 0x4fb850f3, 0x2a16ec45, 0x8380d67a, 0x33f1a9b8, 0x4f4ce079, 0x12ef7f29,
+ 0x03ceb7fe, 0xfa9279fa, 0x9c694f03, 0x7f3bc5f8, 0xeb1ca033, 0x08dbf8f1,
+ 0xd29e7d1e, 0x2c78aedc, 0xce95a551, 0xe3d3f838, 0x816f8f49, 0x8a7e3d4f,
+ 0x534a7b8f, 0xd178aed4, 0xfc30e1e3, 0x6a1f780d, 0xa025050e, 0x61dbc303,
+ 0xe3065e6a, 0xb9d845e0, 0x61069de3, 0x3b5da2e7, 0xc7a3c381, 0x793c5757,
+ 0x88c84ca7, 0xe036ffc2, 0xe27c08c3, 0x3d00aa39, 0x2b644c92, 0x3b7c33cc,
+ 0x052ae5c6, 0xbc59795f, 0x143676ed, 0x9fb403e8, 0x1a618f49, 0xcfa3babe,
+ 0xd3bd95cc, 0x0112de60, 0x5fedc9d7, 0x02dfed6b, 0x2f816830, 0x7748d9ec,
+ 0x7b6d1f8a, 0x4907c32a, 0x5f14ed65, 0x37c5ae27, 0x76dadc13, 0x79fa37c1,
+ 0x18fe1aff, 0x3d1fe513, 0x5134de9e, 0x50f21cbb, 0x803e917a, 0xf27be1e7,
+ 0xd19fd093, 0x7af8e2c4, 0xcc7d1a7e, 0xc61f7917, 0x523f8897, 0xf28bf777,
+ 0x99eb0de3, 0xc57aba06, 0x067199e8, 0xf4f147ff, 0x38ffa08c, 0x2471a74e,
+ 0x8ae0dfb8, 0x311c77ce, 0x1fe1157e, 0x893fd74a, 0xbd26f679, 0x98779e61,
+ 0x3f538454, 0x505f915f, 0x645fbfc4, 0x5c618471, 0x02a0f28a, 0x6adf64b6,
+ 0xd8b6f2c2, 0x1fbc4df7, 0x8f9e30e9, 0x7be103d0, 0x287bf310, 0x7b55c87e,
+ 0x930eae14, 0x163f4464, 0x74bce387, 0x4dea3864, 0x582bff83, 0xb36c2f17,
+ 0x1fe00d04, 0xc3fb8634, 0xb1a974fa, 0x9db632a5, 0xf50b9ff6, 0xf70e3f48,
+ 0x5047f002, 0x67d8eafe, 0xe38e6d0e, 0x25f6125f, 0xe3d45315, 0x876e0e42,
+ 0xa7ce87a5, 0x11a471b8, 0x6df3d5c6, 0xc11af109, 0xebf3d50e, 0x0331d204,
+ 0x54f9eb9e, 0xca3797cf, 0x8a7ec20f, 0xe51345f0, 0x129fad0b, 0x47f281f9,
+ 0xdb6bb00f, 0x1e7f3ff3, 0xf377decc, 0x5bc4652f, 0xd77da87f, 0xabb1895b,
+ 0x46d3d913, 0x8a81af3e, 0x1519473f, 0x0673875d, 0x5be432aa, 0xfb78a7dd,
+ 0x476173c1, 0x405f6f5c, 0x9786e85a, 0xe3833dc2, 0x0da65ebb, 0x4b838e54,
+ 0x9be810a4, 0xf0472887, 0xff66b9b8, 0xf1dac33a, 0xdfb4e3e9, 0xb8019a8c,
+ 0xfbc1f92e, 0x91f7c06f, 0x965ac1ce, 0x76064027, 0xdcfd87f4, 0xba4ccbc3,
+ 0xf20a6ffd, 0x9f9e0cf1, 0xdbed29ff, 0x6dc60533, 0x8a194f4b, 0x7f4d7671,
+ 0x3cc5f7fd, 0xdfeae3f4, 0x5afee2ab, 0xc4f2dbc8, 0x6154bde0, 0xde0464f6,
+ 0x2f0606c3, 0xe74cb3c5, 0x2834d9d5, 0x9f0e26b4, 0x916fd28a, 0xd1a98d73,
+ 0xf33edb7a, 0x7438a1fd, 0xf811df15, 0x0ab4907e, 0x8f137e7c, 0x6cfc8b0f,
+ 0x0faf2fbf, 0x1fac7da3, 0x14a3b72f, 0x7adcafed, 0x85dced09, 0x6cf2c5f5,
+ 0xf6cdbd8d, 0xedec5db7, 0xde38fdfa, 0xccfd86c2, 0x41afaede, 0x03617dfb,
+ 0x8a6c9fdb, 0x40517fe4, 0x2e1da286, 0x885e9df6, 0x17aa2d1f, 0x36125efb,
+ 0x803e70aa, 0xeb5b5ff5, 0xc5ceac35, 0x3fef237d, 0x6fec0571, 0xa860fb22,
+ 0xbc1f635f, 0xacd09956, 0xfef307d9, 0x99307d91, 0x7dad7cd0, 0x3c7f7d30,
+ 0xfca983ec, 0x5d4650ac, 0x2b167e5f, 0xfc47a72a, 0x8b39e97d, 0xe312ad6f,
+ 0x47f3d087, 0x024d45a7, 0xf7cd5cfe, 0x9b2e77c9, 0x75be7685, 0xb3be95c0,
+ 0x9417f3e8, 0xce474664, 0xfe0d831f, 0xf6ae0017, 0x43fa5703, 0xf3554d9e,
+ 0x1e814f17, 0xdbf1e268, 0xb4728123, 0x377d047b, 0xbe0ecc2b, 0x0bb35073,
+ 0x8d7705f6, 0xfb05c8fa, 0x16460b9b, 0xa85f3a2f, 0xab51ec68, 0x8c336132,
+ 0x1e8a4a2f, 0xa2e5e803, 0x926396fc, 0x243eba2b, 0x095effd6, 0xf2b93ff4,
+ 0xb7cc0641, 0x0ba0e1aa, 0xf61e7df0, 0x6f5fe045, 0xf880ce68, 0x1f1da2e3,
+ 0xb41f60b9, 0xdaf6614b, 0x0bab6305, 0x770b79f6, 0xf71e7b53, 0x078ce14f,
+ 0x37ce9e28, 0xc3582ecc, 0x5d89633e, 0xc6bfe0ff, 0x375da882, 0x010c12ce,
+ 0x1837b75c, 0xae1756bc, 0x295fc287, 0xdaba955d, 0xe50e1777, 0x74029bac,
+ 0xcdcf2620, 0x5a48d0f0, 0x8893ded0, 0xf902d7f8, 0xcaf26f4b, 0xee970d5b,
+ 0xc59915bd, 0x048872bd, 0x0d3f9076, 0x4d25789c, 0x26f65623, 0xec688eb8,
+ 0xbd44f3bd, 0x7bd056f7, 0xec048c87, 0x87d9ebea, 0xd9fa1b3b, 0xcc779c55,
+ 0x5ff001f3, 0xcabd8eb6, 0xe1aaacf9, 0xa79044d2, 0x0fbe124a, 0x365595ce,
+ 0x7261dc18, 0xf2bcbd2d, 0xd5e7381d, 0x815264de, 0x0e9bdb2f, 0xbd43865a,
+ 0xad7e80d1, 0x868b77aa, 0x6c5d1f00, 0xde019532, 0xee7df6ab, 0xeb17f902,
+ 0x0326c5f7, 0x3a6f6f3e, 0xb8c5cf89, 0x87531b17, 0x43b3bac0, 0x96bffb66,
+ 0x83b1bfb7, 0x4aeb783e, 0x3bee2a67, 0xec71dc39, 0xaa5d8d58, 0xffc76bb7,
+ 0xe39bd994, 0x0eb89dd3, 0xf8b37b08, 0x24e95938, 0xafaf5fdd, 0x555f4eb7,
+ 0x13747db8, 0xc8f10919, 0x0ba92bc6, 0x9bdb2e40, 0xe8e5eeec, 0x46766107,
+ 0xcf17cb7b, 0x47e7864e, 0x69f7e80c, 0x3e4062bf, 0x82e6f03e, 0x2c4736ac,
+ 0x3e916b9e, 0x797e7b97, 0x7fed2f71, 0xf98da0f9, 0x219e8d9b, 0xba3c673e,
+ 0x98c97b84, 0x25ec1cb7, 0xf82b2c63, 0xa3c8eced, 0x7d02e25d, 0xe81718cc,
+ 0xb26a0898, 0x14cfc6ff, 0x1557ff90, 0xea335f5f, 0xc83b7aab, 0xf4949075,
+ 0x72e9bc86, 0x7e01291b, 0xee21a8ea, 0xf775b4cd, 0x50b65921, 0xcd6fe43a,
+ 0x5ed900f6, 0x15d479e3, 0x764a75f5, 0xe0a8be8c, 0x9aceebe7, 0x62537d82,
+ 0xb3316f9e, 0x83d9e338, 0x7d465ff3, 0xb93347f7, 0xb7face39, 0xd3f4ccd2,
+ 0x7938252e, 0x213bf43b, 0x96c939e3, 0x1b78dfb7, 0x8e2a28f2, 0x3d6023a9,
+ 0xfc666199, 0xb5e478df, 0x6927c85a, 0xc0464e3c, 0xccb60a2c, 0xbbf4c834,
+ 0xfcca897b, 0x76654751, 0x53788f5e, 0xaec27e61, 0xb3c3807a, 0x165c90f7,
+ 0xcbd82feb, 0x98a623f3, 0x8947084d, 0x7683f999, 0x05492a1e, 0xe2aafbfd,
+ 0x3c86609f, 0xb56d5385, 0xbfea352e, 0x98d0f612, 0x0f273ba3, 0x398e7fa3,
+ 0xdc81bb2f, 0x06cdd1ea, 0x967aaf98, 0xaba96490, 0xbbc7447d, 0xbdbc763b,
+ 0x1478d9e7, 0x9720038e, 0x8574ff02, 0x5a50c9fd, 0x4c6adbdf, 0x020bf381,
+ 0xe21e62ff, 0xf13d6afb, 0xe8a0726e, 0xc35e7778, 0x04910acf, 0xb73c8fe0,
+ 0xf2373b90, 0xf78ac7e5, 0x63f33361, 0xd9fa85f5, 0x3bb43683, 0x88f5f176,
+ 0x02ccce64, 0x053a0a3c, 0x10fecccd, 0xfefa24f0, 0xd7a666e3, 0xf2f7f945,
+ 0x35266bf5, 0x5bb37c88, 0x1a84bf42, 0xa5fa5b0c, 0x987ebf41, 0x378d1d17,
+ 0xf8471ffb, 0x9afeb55b, 0xb65936c6, 0x27dc7e83, 0xbcf86325, 0x846bf69b,
+ 0xc8f58ccf, 0x08c78d7f, 0x6dfcf1ca, 0x8d3f998b, 0x79737b84, 0x0bf20ded,
+ 0x38e4c3f2, 0xe5a253dc, 0x2b4da698, 0xc37e237a, 0x28ab902e, 0x40dca89e,
+ 0x00a75d59, 0x652c56bf, 0x5e7e3ce5, 0x1f8362a5, 0xc6ee73e5, 0xbec11399,
+ 0x30820e7a, 0xfce23fb0, 0x2f5b644a, 0x7371f3c8, 0xfbb80bfc, 0xd73dbe70,
+ 0xbe19aeb0, 0xe7ebf94b, 0x8db18f80, 0xe00f3ccf, 0xb73d7e0a, 0x94e384c5,
+ 0xc8c7bf03, 0x75d38869, 0xefc651f7, 0x4a98b663, 0x8f79d3a6, 0xf8371209,
+ 0xd96ef765, 0xbdfd006a, 0x9b39f817, 0xd3ac39c9, 0xb1ae0f67, 0xdbeb063f,
+ 0xff013267, 0x94852eef, 0x8b9188ef, 0x6baf4d96, 0xb6fe77e4, 0x67e8c99a,
+ 0x60914b6e, 0x56e426eb, 0xe2977de0, 0xfff28499, 0x97fc9d3d, 0xc0fff7b2,
+ 0xcb8eb2e9, 0x2a32baff, 0xf251f4ff, 0x1e496496, 0xcf1fbeca, 0x735bf6af,
+ 0x121df2f7, 0x5d43d5ea, 0x65bf80fc, 0xd5cdb57a, 0xf2bf7e8f, 0x9fdc4eae,
+ 0x7ce3e047, 0xf054aeb3, 0x67e4b64d, 0x0b9ca6f6, 0x0578a2f8, 0x137b467e,
+ 0x4e716df4, 0x8f14b368, 0xb973971f, 0xadcae355, 0x2b1f6bd0, 0xbd023ffe,
+ 0x57ab4a0b, 0x3a9d1d80, 0x7a7c8825, 0xa567f24e, 0x1ced75d0, 0xbd1c73c8,
+ 0xcb973af0, 0x26bf26cb, 0x1c2bb22f, 0x75f017a4, 0x6191dd39, 0xc946db5e,
+ 0xed11f40d, 0x6fb646ea, 0x13c7ccb8, 0xa0df2fcf, 0x7ef047dc, 0x767acbac,
+ 0x917e8cd9, 0xe742c50e, 0xd6c43fd9, 0xa0952233, 0xcef9105c, 0x156f205e,
+ 0x1e9b1d74, 0x339d8eb3, 0x0abf21d5, 0xe30b103c, 0x6cc9cbf7, 0x70e6bfde,
+ 0x43e70a7e, 0xd43de262, 0x4c4a3780, 0x93120dae, 0x7f8c0377, 0x49d8e0ee,
+ 0xc577f7c8, 0xdb05fbe7, 0x267f2137, 0x8047b997, 0xf46759de, 0x76879358,
+ 0x5b2dc7d5, 0x13fdc05f, 0x5e0b2ff0, 0xca0e5b5f, 0x1c480e41, 0xfe510ffe,
+ 0xe09fa18f, 0x7d17ca03, 0xd0f4312c, 0xb38885f3, 0xd2ecbc09, 0x72e6e9c5,
+ 0x985be53c, 0x9eb951be, 0xdcbeb44a, 0xbb5b9d30, 0x659e57c8, 0x2cbe5694,
+ 0x993f146a, 0x58951950, 0x261602ce, 0xfb644f87, 0x78a38d8f, 0xa2a7a27a,
+ 0xeb7aa0ae, 0xf7664a09, 0x467c68c8, 0x3cc579c4, 0x3e30b0ee, 0xc9671448,
+ 0x5a27f932, 0x259c7134, 0x33af6606, 0x9841d97e, 0x98b7073c, 0xaddb9fb9,
+ 0x5aa6fbb1, 0x6e037dd8, 0x29583523, 0xcf672fea, 0xb850716c, 0x4e0d68ee,
+ 0xb9c2a619, 0xbbb4e0f4, 0x6e5e61b2, 0xf38698c9, 0xa5f0d772, 0x47a0fd1e,
+ 0xc93fe86c, 0x8219e7eb, 0x93d538fe, 0xc43fe307, 0x99e823e9, 0x75fade68,
+ 0x033d112e, 0x74d1f616, 0x1fd7aede, 0xcdddbc85, 0xd1fcbd4b, 0x26e5717f,
+ 0x6823cb7d, 0xf1639207, 0x2d47c0ed, 0x874b1d6c, 0x4bf687f5, 0xfe73b20f,
+ 0x527a710f, 0x3c00cdca, 0x13316dd4, 0xe421f738, 0x97cd35d7, 0x5715fe09,
+ 0xe951e29a, 0x3234eab8, 0x5029ee09, 0x6fee32bd, 0x1d7dff6a, 0xbb51a7de,
+ 0xc7964cd5, 0xd38923e0, 0x091a692b, 0x72c4a585, 0xae95b2dd, 0xf2316963,
+ 0x22d50c67, 0x0ef951df, 0x345fc8c6, 0xa9577afe, 0xee4f6e26, 0x7f2d795a,
+ 0x4d56cfc5, 0x3be4d16e, 0xb8d1fef0, 0x6b96e4fd, 0xf7d03be5, 0xe1df214b,
+ 0x8377b31d, 0x7fe5c585, 0xd053f206, 0x6240daa3, 0x767afce4, 0x6fca8dcf,
+ 0x908bf715, 0x9b1fad46, 0x6d8cefca, 0xff2bfa2a, 0xecaae00d, 0x1879fa75,
+ 0xe589aaae, 0x2382260f, 0x1c85d38d, 0x69472827, 0xf8036abe, 0xee5c840b,
+ 0x75f0a4b1, 0x7f812bd1, 0xc829f05f, 0x229fd835, 0x19fe0f7e, 0x3e544a67,
+ 0x93149ea1, 0x8a76b027, 0xbfcf165c, 0xf1c5bef6, 0x9d05eced, 0x8c7a133e,
+ 0x81f7b5ea, 0x9ca6eb2e, 0x87fb60c8, 0x31e6febf, 0x3a0aafda, 0x304a81a1,
+ 0xfc87f9df, 0xf72f2f1b, 0xf4003fbc, 0xdeec7bc9, 0x25661198, 0x945d7908,
+ 0x0677547b, 0xafc40f7f, 0xe93b0a49, 0x1beab8fe, 0xfdd0f1d8, 0x963237e9,
+ 0xaf8bff2f, 0xdfec1b2c, 0x2d43d946, 0x401bc809, 0x22c9e23d, 0xc5e50b21,
+ 0xf7cb1b7a, 0x78766e2a, 0x25da5e41, 0x90fde60b, 0xdbbe8ec2, 0x13457d69,
+ 0xaece3395, 0xf6ff7eb1, 0x80453a62, 0xbcc1e8df, 0xaeefe1eb, 0xbde7881b,
+ 0x5f1e758c, 0x2277de4c, 0x38a2573f, 0x1b32d170, 0xdf84b7fa, 0x03a3a8ac,
+ 0x29a724f9, 0xd1f5865b, 0xe229e7c8, 0x9d7cfac2, 0x1a76875d, 0x282bdd60,
+ 0xfb015bad, 0xff66d183, 0xb1bbe015, 0x28bb5a45, 0x766eaa5f, 0x224d7f02,
+ 0xe5c9de2c, 0xec8db523, 0xf256b707, 0xec2f36b1, 0xf59ec6cb, 0x57fd87ee,
+ 0xec488f92, 0x5f24661c, 0xfe056cc5, 0x774af34b, 0xfe0a71d1, 0xf13c3083,
+ 0x2a1d7671, 0x492ec091, 0xd4952d6b, 0x7bf95da1, 0xf353ec03, 0xd004de59,
+ 0xb29fec55, 0x297075fe, 0xff4493f8, 0x1eb656fe, 0x8ff7eadd, 0x9d29d707,
+ 0xbe95864f, 0x50fee63f, 0x46728433, 0xc19b0797, 0x4f991425, 0x7af1c105,
+ 0x1e7105b7, 0x8bf98f3d, 0xb0ae9ca1, 0xd9ec6775, 0xf45be630, 0xa69826a8,
+ 0x51eb5372, 0xaa6e3bb4, 0x8e80956e, 0x401d0ebb, 0xb6b4fb78, 0xd5cb92b0,
+ 0x0a5ebe4e, 0xff73a6b8, 0xe98574f3, 0xb30bdaff, 0x313f6133, 0x7cc7ead8,
+ 0xda8f311b, 0x9c267f62, 0x7900d967, 0xf389f922, 0x1558c644, 0x8ff2dfee,
+ 0xdd55f984, 0xf036f6df, 0x9d9f7e9a, 0xd204e471, 0x33196323, 0x591c3783,
+ 0x6d7f0122, 0x3efe3078, 0x0d8be85b, 0x9318efdc, 0x35bb718f, 0x3c9a2ec6,
+ 0x139ec533, 0x8f9e5fa3, 0xe2ec63e6, 0x68b718f9, 0xc27b0ffa, 0xc994768a,
+ 0x15e0113b, 0xe35e7ce7, 0xfd8819f7, 0x3ad3c09e, 0x60d3c32b, 0xc1d33deb,
+ 0x71f80a9f, 0xcd7e3e53, 0xcdbcff1a, 0x6f615693, 0xad213e31, 0xb6e19fc2,
+ 0x0b23dac7, 0xfd787f04, 0x3f8c8de3, 0x639c03a6, 0xc8cd430a, 0x66c165ff,
+ 0x089bfbe0, 0xc6328fe7, 0x7f3e7a1f, 0xf9c29adc, 0x4fef03a3, 0x4bf387c8,
+ 0xa562f471, 0x6983d995, 0x37c825ad, 0xc1e60e54, 0x577a0af7, 0x8a184c1b,
+ 0xf5864f73, 0x4555b966, 0xbd0af3f8, 0x6e67c0cd, 0xe300cfaf, 0xbe591a36,
+ 0xefb66d73, 0x6bc9f818, 0x0acf15d3, 0x0c59c709, 0x53cbd478, 0xd0d1c803,
+ 0x71a51ca8, 0x1f9e933f, 0x5af8e11f, 0xf89cf1ce, 0x1580fe3b, 0x70bd97e1,
+ 0x3be4046f, 0xf4739041, 0x824eba52, 0x072a12bc, 0x7294e014, 0x5bc83177,
+ 0x091e85ef, 0xd186fce8, 0xe9f00b5f, 0x4aeb13c7, 0x748bc591, 0x62f5e1bd,
+ 0xc76bf33b, 0xacebbfd8, 0xd4f97f6c, 0xafdbd04c, 0xbf40565e, 0x0f1e42aa,
+ 0x8acfb48d, 0x7ced9be1, 0xf07c31de, 0x3a13d473, 0x3debd03e, 0xf5441f3d,
+ 0x51ef5684, 0xf4656dbc, 0x5a70f661, 0xd30352eb, 0x973d5a17, 0xf45d3e88,
+ 0x9f8f0e85, 0xb6bfbd1b, 0xefc13b62, 0x0f975a27, 0xd6c7ff58, 0x6bd603e5,
+ 0xa5b2cbac, 0xc51277e3, 0x8326a2c7, 0x3c8b7e0a, 0xe2bb3f9e, 0x9f9829c7,
+ 0xe4bd72f0, 0x58bfad81, 0x68359197, 0xa4eee2fd, 0x5a16e4e1, 0x979007d2,
+ 0xa0a9ec13, 0x065a4efd, 0x8ab29c61, 0x2b264b9f, 0xdafae107, 0xd315ee2e,
+ 0x08a9d9c7, 0xd83fb449, 0x8af8309e, 0x9487e242, 0x9626e6b5, 0xad72f857,
+ 0x5dedd70d, 0xf77f3a47, 0xfee7ad00, 0x42734658, 0x5fbfdfaa, 0x29e324c2,
+ 0xe22c1798, 0x6fdd6232, 0xa2436039, 0xd03b0a5d, 0xae5abf2f, 0xa5f906ab,
+ 0x72893ef4, 0xc6316ebd, 0x391d2ebd, 0x70720299, 0x19abf1a9, 0xdc68d407,
+ 0x37c0fea9, 0x9c76b105, 0x360d5b88, 0x1ad3fff8, 0x3c3a4fb3, 0xe3d324f0,
+ 0x0164fcba, 0xdc1f0447, 0x967061bf, 0xf6cf9012, 0x5af104e3, 0xf98e78af,
+ 0x389f7f01, 0xf8e41e98, 0xb427f712, 0x2ad9fd37, 0xc678850d, 0xe1d82b25,
+ 0x7ffc5bef, 0x370df805, 0x55be6075, 0x41a5d373, 0x7aa6cfb0, 0xfcf06fe6,
+ 0xb263e606, 0x223e6375, 0x07cf5eef, 0xdd9a7a7a, 0x862963fe, 0xba651d28,
+ 0xa47801bf, 0x917ffda6, 0x1748bf20, 0xf167db47, 0xebf7c2a6, 0x2874be2d,
+ 0xe7385c61, 0x03d3e741, 0x9ddfc3ea, 0x6ea9079d, 0xb27cc77f, 0xcde2a36c,
+ 0x58748c27, 0x045ee1c4, 0xa7803e71, 0x123e74c1, 0xe7138eff, 0x1be2df7b,
+ 0x24147008, 0xdf87c1fd, 0x4306f8b5, 0xc4ce149d, 0x4cb27e7b, 0xbe7f8c5e,
+ 0x0331d356, 0x25a3b1e8, 0x6bfa06c5, 0x81efc59f, 0xcee5837e, 0xcf7fe019,
+ 0xb3c9f56f, 0xe7f15d70, 0x325d79f1, 0x0daaf7e2, 0x1dfe5760, 0xfe35bbf3,
+ 0xf5e0bafc, 0x51338436, 0x9d918bfe, 0x9c6eb9bf, 0xdfa1b493, 0x339eff7c,
+ 0x541e21fd, 0xdc19e6f9, 0x61be566f, 0xbe956246, 0xf8092831, 0xfc7162ef,
+ 0xa07cfef5, 0xf6a463da, 0x76361dc6, 0x6921728e, 0x16057bc5, 0x18f62fd5,
+ 0xb09af463, 0x5a988e6b, 0x47f8c0a7, 0x0d481946, 0x9e4bfb95, 0x1c483dd1,
+ 0x536ed97d, 0xf7b8fe35, 0x5e31aec0, 0x1f49df3f, 0x3ed2ee3f, 0x80fe8ac2,
+ 0x613b3a29, 0xf7e98d99, 0x976636d5, 0x8597b810, 0x37e179c2, 0xbb77cc4e,
+ 0x2ef7f230, 0xa1717438, 0xe0bca3e1, 0xd5673830, 0x938843fa, 0xe072bf05,
+ 0x88ca66fe, 0x38d5e7df, 0x8e32f2a3, 0xf71aef9f, 0x952ebbfa, 0xa3b29ff6,
+ 0x83182d39, 0xd3be7d3f, 0x030fd86a, 0x986d8d3d, 0x9ef6421f, 0x2a7b80cb,
+ 0x9839eca7, 0xf115f306, 0xa67cfd4c, 0xbe44ab2c, 0xc916d079, 0xf205eb0b,
+ 0xe83c5ddc, 0x1c3c0b9f, 0x2fae7119, 0x13178bac, 0xf1cf79d8, 0x633c977e,
+ 0x31fd807a, 0x5ee70945, 0xe02b0fcb, 0xbd707c14, 0x0ac9d8bc, 0xff5377bb,
+ 0x77c8a9fc, 0xf54824ad, 0x99370fea, 0xbbdd5cf0, 0x969e3e57, 0x6671e947,
+ 0x9cbdc9a3, 0x4bf94eb2, 0x81d67dcd, 0x198471df, 0xd46728fd, 0xe5f02e70,
+ 0xbe5897bc, 0x3f8d99ed, 0xf07880cc, 0x5abe527f, 0xb798e148, 0xcbcf84c9,
+ 0x9f08fd37, 0x36fce39f, 0x8c74a5ef, 0xb2dbbf13, 0x59e60326, 0xef27b7fe,
+ 0xa1df7903, 0xa08c87b8, 0x92edc2e5, 0xfe6ebf26, 0x2ea6ab16, 0xf991cbe2,
+ 0x3bfcd14b, 0x6cd3c295, 0x5d9dbf93, 0xff8badb0, 0xecc6d9b1, 0x4bddefaf,
+ 0xea395de7, 0xcd5fda12, 0xf2f5b36f, 0xd701872d, 0xff88f0db, 0x5a16e77a,
+ 0xa337ff1f, 0x7066d707, 0xdf801582, 0xf1cfe994, 0xb8918c7b, 0x245b9e37,
+ 0x8284c75e, 0x30ef71c4, 0x6fc003d5, 0x44345fe3, 0x5cf0dfe2, 0x9c45bfc4,
+ 0x86ff1f5b, 0xb3d00834, 0x0b7f8bd7, 0xc1c7d7fe, 0x9cfc6cdb, 0xe6fbe712,
+ 0x7bbc59b7, 0xb30311ee, 0x27a3ae6b, 0x8db803de, 0x0fc3df40, 0x5dfadf82,
+ 0xaf778d8e, 0xf709599c, 0x94299c35, 0xce419220, 0xc597315c, 0x36698393,
+ 0x4080dc6d, 0x28c0e57e, 0x54f2ef7d, 0x7cd0ea44, 0x4d62e177, 0xf5f767be,
+ 0xf1e5b5d6, 0xaf3b1b25, 0x7a6bd7a0, 0xd29ff9b9, 0x1c46536b, 0x62741bec,
+ 0xcf280bf9, 0x85fa60ef, 0x17e88f5a, 0x23edca5a, 0x7013debd, 0x7d173809,
+ 0x7942439d, 0xd8ab70b1, 0xaad8c8be, 0xf4597e80, 0x4a127f75, 0x2bf74efd,
+ 0xf671ec83, 0x1f7d742b, 0xa69dcf0a, 0xffe001f0, 0x76b9c991, 0x74738310,
+ 0x87cf0d3f, 0x4193af6c, 0x417f082f, 0xd26d1f64, 0xfec5a7ee, 0xf8cec0a1,
+ 0xdb3b26e4, 0xcfce7e87, 0x527f08f7, 0xe761316d, 0x0849926c, 0x3f22defc,
+ 0xf493f84b, 0xdf9109fe, 0x6a660648, 0x00c16efc, 0x937385c9, 0x2c1603cb,
+ 0x58dc0657, 0xb13206d6, 0xb150155c, 0x8818135c, 0xe400dae5, 0x0e39c1e4,
+ 0x0175960b, 0x06cf9637, 0x1f5cb132, 0x7f694950, 0xc40c2bf0, 0x86e5d052,
+ 0xf9d61ff1, 0xab9b4959, 0xeb3f4254, 0x4bc53b74, 0x195394fb, 0x67ec2ab9,
+ 0x142f313a, 0x1f81cb73, 0x41f8b3f7, 0x9c31d4bb, 0x8648e7dd, 0x50fbdec4,
+ 0x2b3fe3cf, 0xc677fe29, 0x7635ffe1, 0xf2c87791, 0xe24aab2f, 0xbb412faf,
+ 0xf61bdd91, 0x82fa5fe6, 0xffbed3dd, 0x41afbc1b, 0xfc8437ef, 0xddeb78c9,
+ 0xea4fae7a, 0x2cf6faf8, 0xba31b5c8, 0x2f7f04bf, 0xf2d7e5f8, 0xe0a7fefc,
+ 0x1f2d04bc, 0xf978b3b1, 0xd86581f3, 0x392ef53f, 0x74be9739, 0x7180c1b1,
+ 0x19168b84, 0xaa17a5f7, 0x400d651d, 0xf0c76377, 0xcf89887f, 0xe767623c,
+ 0xabcd1279, 0xa07fcf96, 0xa3b5abe2, 0x2fa3b9ff, 0x37815de8, 0xd8673e3d,
+ 0x27b65c99, 0x34f6ff38, 0xf14fbf6f, 0xbc476d3e, 0x7c47ef6a, 0xd67decc7,
+ 0xebf9fcce, 0x3e7f04a1, 0x2ba659f8, 0x6a16defc, 0xdafb327f, 0x8e3da2f7,
+ 0xfed1323f, 0x48c70f5c, 0xfd279307, 0x62945dbe, 0xd605bedf, 0x946fda08,
+ 0x057fbe3d, 0xf6f198fc, 0xe983b2ed, 0xd7af4cd5, 0xf2a35760, 0xbd58519a,
+ 0xf7b0d81f, 0xf062ba94, 0x73fbe45b, 0x45ee206a, 0xe3e609ca, 0x5b5f26d5,
+ 0x0606739e, 0xc8cfe0ad, 0x1019cbf1, 0xf568c987, 0x7e742b17, 0x7e066b0e,
+ 0xaea907af, 0xf7cafe01, 0xfcf938cb, 0x12485b16, 0x3c4d329b, 0x7965683d,
+ 0x8003fe30, 0xd53982c7, 0xdaafc02b, 0x5bb0617b, 0xec8ff471, 0xfe5838da,
+ 0x21e21316, 0x1873cb7f, 0x72dfcaaf, 0x898a5187, 0x79dbb577, 0xf9c1c6be,
+ 0x4857e059, 0x86751794, 0x72dfbbeb, 0x6fca27bc, 0xceff6938, 0x724e1bf3,
+ 0xafe2ce7d, 0x9f513a8b, 0xeb6765bf, 0xee21cfc8, 0xf3f9f14a, 0xbaee2239,
+ 0xbb64fd09, 0x1049fa94, 0xca560837, 0x8918ef98, 0xf961cf5b, 0x21f7911b,
+ 0xff9f4d7e, 0xafc59cbc, 0xc19e867b, 0x2b65d9f8, 0xde5def8b, 0xf710266a,
+ 0x1ea0f8ac, 0x161b71e3, 0xbb5244ca, 0xc97e9bce, 0x4c6ef3c4, 0xf4038f90,
+ 0xe8233d07, 0x0145194e, 0xdbe2447a, 0x871e78fa, 0x95fdc1cb, 0x98edb7f3,
+ 0x6bd27c04, 0xf7048a61, 0xbeb80acf, 0x1df2faed, 0x8e19b3ae, 0xd9d77151,
+ 0xbf5cf09e, 0xd7d7eace, 0x1f6f2673, 0xd7f5fa47, 0x7e725fd9, 0x7e7439b2,
+ 0xc4578868, 0x7b16c3a1, 0x10e3ff17, 0xf43f1c47, 0xcf8ffcf5, 0x1c7053db,
+ 0x9c51ffbd, 0x214bacdf, 0x8713df0f, 0xdfe19fff, 0x6077d797, 0x935a453e,
+ 0x4d0f5714, 0xbf111457, 0xe311cdb9, 0x53ebd6b7, 0x80eea9a7, 0x5af11b2d,
+ 0xea1af80a, 0x298b5350, 0x39dd2b1c, 0x32a3cc76, 0xf0682779, 0x7fefc098,
+ 0xfc8c52d9, 0x0efcfc20, 0x9b4ed6ab, 0xbcfd10ef, 0x3778c377, 0xdfcfd025,
+ 0xee024877, 0xda5fa0fb, 0x5ff1a252, 0x5a75bf0b, 0x73825075, 0xc25e695d,
+ 0xfaa727ce, 0x07904c6b, 0x36788633, 0x83d27ad3, 0x6bd062ee, 0xfd9ee529,
+ 0xbdad6ae0, 0x2f25cfc0, 0x392e7826, 0xe7f57712, 0xf8009da0, 0x275f3d8e,
+ 0x3f3101d6, 0x75cd3eba, 0x1ca9f5b0, 0x7d6099f1, 0xfff90efa, 0x1ffc78d1,
+ 0xa0c7af43, 0x09af4f5d, 0xba53df70, 0x5e205fa6, 0x60d74a3f, 0x2bfae877,
+ 0x6ee9771e, 0x28d1a73c, 0x98fcbb7d, 0x217878ae, 0xf9121e1e, 0x38755fcd,
+ 0x9cfcd3be, 0xabf9bf18, 0x8d1baf80, 0x2ffcbf67, 0x03f80a6d, 0xc0581f85,
+ 0x8b638fab, 0x524d95e7, 0x8ab3ec1e, 0xd35caf9b, 0xf3c09cae, 0xb2373bcd,
+ 0x6380ba7d, 0x132ff089, 0x0a2285f5, 0x1321d547, 0x277ad109, 0x1bfe80f4,
+ 0x1fdc10a4, 0x3c6879dc, 0x91ede7d6, 0x1fbc2a48, 0x39c2b6f4, 0xbd843980,
+ 0x6b28549f, 0xf64eb5ee, 0x4f0def6a, 0xd4d14b2d, 0x7bda7dd3, 0x9fdc7bc3,
+ 0xe9ef69a3, 0xef69ac1f, 0x53523e5d, 0x7b5aa9bf, 0x5d16786f, 0xd9eb628f,
+ 0xfd353bc1, 0xaa9aadfb, 0xa75cdfa9, 0xec5c37bd, 0xf9f01743, 0x4b30d80c,
+ 0x58774f7b, 0xf7314b0a, 0xfee1cf0d, 0xb5860587, 0x8739c36f, 0x9af9a141,
+ 0x43dcbaf1, 0xf909b8d4, 0x10f77af1, 0xdef77f0d, 0xc06f2c21, 0x0b4c7987,
+ 0x2fdb69b6, 0xb8feb439, 0x3835d2eb, 0xd5d15be0, 0xaba5a99c, 0x135db555,
+ 0x5a81f66f, 0x657b8b3a, 0xe9cde112, 0x8dc1f2d1, 0xa78f4de2, 0x7fd6a74c,
+ 0xf7f26593, 0xa39c4276, 0xcf01a971, 0xb8b1968d, 0x3fe1dfdd, 0x138ce7ef,
+ 0xa2f710ef, 0x661be3e9, 0xe29862ba, 0xf42d0f9d, 0x52bbe058, 0x585ff353,
+ 0xf741ea1c, 0x6fd46b69, 0xa253d7ae, 0x0f39faa4, 0xf6ed1fe0, 0x6bc3f25f,
+ 0xcfb756c6, 0xc4238d19, 0x9743c7bb, 0xc02b77a7, 0x20f7a37f, 0xba127c88,
+ 0xd93895be, 0x8cea5bba, 0x9e44df59, 0x12df5887, 0x31e7438d, 0x3a70e005,
+ 0x45265da9, 0xec17b2ed, 0x8ec3e42e, 0x034219df, 0x3179a3b2, 0x1fa0de22,
+ 0x2e7748af, 0x4f7749b0, 0xb648ed67, 0xc9c0ff4e, 0xf94f99d6, 0xbc1516bd,
+ 0x84b3f22e, 0x8ab55abd, 0xdee0d3ed, 0xf598a686, 0xc4e9c2a2, 0xe2c615fe,
+ 0x26ef980a, 0xd46fdb1b, 0x83ae124a, 0x7e12d9b5, 0x094b65f7, 0xc59d7bb6,
+ 0xf3e650e5, 0x5c7c02b2, 0x4fdf78e9, 0x315bcc05, 0x5f9f3fc4, 0x2df064e9,
+ 0xbfdef1e6, 0x22d07cfb, 0x45a709e2, 0xcfe907cf, 0xa97f0bab, 0x05bba077,
+ 0x9e8dcbd4, 0x817c0217, 0x41f82a49, 0x327d37ef, 0x8e78772a, 0xedbb36bc,
+ 0xd740c9d9, 0xc81e0d77, 0x078f563b, 0x20d3c3ed, 0xc0f6534d, 0x9236633b,
+ 0x9f5a56e5, 0x9fd15417, 0x06fba26e, 0xb0c7a527, 0x70cb6163, 0xcce4df5a,
+ 0x3e8c7c46, 0x7e0fdbee, 0x08d3fed3, 0xee630984, 0x0f1ba915, 0xdc1477bf,
+ 0x4896f3c8, 0xacf7e6b5, 0x512f1726, 0x9df06272, 0xe63171be, 0x6cfc8b47,
+ 0x7806cffa, 0x47c3f712, 0x92bcb39f, 0x26e94b22, 0x87289ba0, 0xe7efe285,
+ 0x303b7317, 0x12fdf468, 0xa1ac3ee8, 0x9ba7ef0d, 0x1cc3f427, 0xdeffcf19,
+ 0xef71e9cb, 0xbcd71e46, 0xa1aaf572, 0x46b79a20, 0x3f7027c7, 0x4e69bcde,
+ 0x5e6677bc, 0x139e3653, 0xf7093e26, 0x1f4d55ff, 0xe75f50f8, 0x3f61bbe7,
+ 0x4884fde6, 0xe0240f70, 0x1a59c984, 0x46a7dbfa, 0x3b5ad0f5, 0xef69f7e6,
+ 0xedcc5c8b, 0x6b1b79d1, 0xe3a4f40e, 0x8215fefd, 0x992415f7, 0x61bcf03a,
+ 0xdf4b95fb, 0xe33f778b, 0xf224a779, 0x6efef1c1, 0x7e10ff61, 0x9388b77f,
+ 0xee0906c2, 0x4175c6e7, 0xe70aec66, 0x9d43e712, 0x6fe93f7e, 0x9e61fb79,
+ 0x0f25ebed, 0xd51655c4, 0xa6e3ef6b, 0xbdee3cfa, 0xb1fe7e6a, 0xfd461d71,
+ 0xefc8e07d, 0x5bf7f933, 0xe2000f20, 0xefd96be5, 0xd89bf9cd, 0xef94e9bd,
+ 0x97b5ef35, 0x39b39411, 0x2a90a4ab, 0xfc77bd75, 0x47d28e11, 0xce197ae8,
+ 0x7506fbc6, 0xf87798f7, 0x915e7da0, 0xe96ff311, 0xa769a5fa, 0xdefe96eb,
+ 0x95fddd73, 0x41e7c441, 0x8f1fbbfe, 0x9de5c73c, 0x4b313fdf, 0x1d7893e0,
+ 0xf9d119c5, 0x7c17f90b, 0x224488fb, 0x736f83ef, 0xf1079956, 0xe4ad6b3b,
+ 0x351f5951, 0x1f023f16, 0x8c9adef3, 0xf36634e7, 0x93aece79, 0xe297ef30,
+ 0xfad72341, 0xbcc5167b, 0xb3bcc2e7, 0xa3ef7faf, 0xaa4afefe, 0x5f80546e,
+ 0x2aff7ee2, 0x2abf8333, 0x05bde095, 0x903c9d94, 0xec226790, 0x1774859e,
+ 0xde91c3cb, 0xbef17b30, 0xc58f4a91, 0x7113f884, 0x157490e7, 0x443ea2ec,
+ 0x40d5f5c5, 0xdb129b11, 0x17fbc7ee, 0xf84a4e0a, 0x0b05113b, 0x87afbc24,
+ 0x9b77d918, 0x1cddccbe, 0xa27d0e7b, 0xbef9f18b, 0xebba7d3f, 0x60a5da5d,
+ 0x8cf3c4bc, 0x7380ee33, 0xd7df05bb, 0x3c4af7d5, 0x7fd7998f, 0xa75f6ba9,
+ 0xd59f7f6b, 0xdc65716f, 0x3c8e7101, 0xf9d3ecd8, 0xec6dc915, 0x81d22fbe,
+ 0x736f8be7, 0xdbdf3828, 0x1f78991c, 0x97a7d176, 0xeba17ed1, 0x9d2cf040,
+ 0xdf8ba15f, 0xb2459123, 0x9cfbaf00, 0xac1712fe, 0x479e766f, 0x9c32b862,
+ 0x76b5f9c5, 0x311bb521, 0x64ded69e, 0x92d4c8c7, 0x5e30fd7d, 0xd88bde2e,
+ 0x513c7c1d, 0xf040367f, 0xb1f6cc7e, 0x59a2fcdf, 0xbee8bb45, 0x2c5defd8,
+ 0xc82faafa, 0xb8b3c0bb, 0x5782313f, 0x2e9df15b, 0x9bb867f0, 0x33fbb176,
+ 0xf2f80f88, 0x91ff1156, 0x2ec02bc3, 0xe3c7f7d8, 0x164e30a9, 0xfcc289dd,
+ 0xaf4b9fe8, 0x47d576a6, 0xab42fb51, 0x18bd28df, 0xe9cfbf9d, 0x979821ec,
+ 0xc7a7bed4, 0x573a58a6, 0x003d98b8, 0xe8cf50fc, 0xda75eec4, 0x74524acb,
+ 0x297ef79d, 0x211ddff1, 0x77ed0341, 0x47eb1f71, 0x5878c1c1, 0xc801ded5,
+ 0xf3173657, 0x1d258f27, 0xc7bcc28f, 0xcf16fd36, 0xe7158f8d, 0xf36acfc6,
+ 0x8cf06c29, 0x7635c9e2, 0x444bde2e, 0xbff50579, 0xef1078f9, 0xaa9eb448,
+ 0xd5e2fcc7, 0x014bc549, 0x831326ff, 0xa0730c93, 0x9f8f429f, 0xfe4a92af,
+ 0x2caef009, 0xec767067, 0x2b393031, 0xbf81736c, 0x418f72ba, 0xb32b3806,
+ 0x7e543c99, 0x07f71439, 0x1d993db5, 0x1cb65b75, 0xcb6f2054, 0xbb02e6dd,
+ 0x979f96ac, 0x7272e5ab, 0x065b725b, 0xdb6e5ff8, 0xf904b373, 0x5d488717,
+ 0x32e3e01f, 0x9851e369, 0x5aaf45ef, 0xcc16fc0f, 0x3d3ae2b5, 0x197fedcf,
+ 0xec64b7e4, 0xa7800cd9, 0x0dc1837d, 0xbef2fa7a, 0x87c059d9, 0xfe9d5493,
+ 0xe50def07, 0xc20649df, 0x1eb013d6, 0x4efcdf28, 0x27017562, 0xe81535c0,
+ 0xb6bcf941, 0xfbcfbe00, 0xb656fd73, 0xe7235931, 0xcfc3be5d, 0x12624fcf,
+ 0x606d2643, 0x6571e6e7, 0x6938f2a7, 0x847f8ee3, 0x7bce3b75, 0xa3fcecc9,
+ 0x75ce1937, 0x8af937ac, 0x24dd9ed1, 0xa5cf01b9, 0x6f1467a1, 0xc0d21d8c,
+ 0xcb7d27f9, 0x548f6833, 0x468af6f0, 0x98af27e6, 0x6298a756, 0xe7c6d0ed,
+ 0xd2b5fef0, 0x087ffb2d, 0x0ed2da7e, 0x370fde07, 0xba56f881, 0xcf059c59,
+ 0x93097be9, 0x0b8b76ef, 0x37f6ecf3, 0x807faea6, 0x69e77d80, 0x0c9fa6c9,
+ 0x7a8d9bef, 0x0d9f4a3f, 0xcfa53269, 0xbc42db24, 0xe77ae5f7, 0x716109f1,
+ 0x4a383bb6, 0x69a7fda9, 0x164bedbf, 0x5323be27, 0xaf8f5cfb, 0xa7e52ad3,
+ 0x3ef8aea4, 0xe7f77fcd, 0x816d2ab4, 0xaec7c4b8, 0x08afe45c, 0xaefc3a1d,
+ 0x8ff2707f, 0xa4a17d03, 0x7afe9caf, 0x50dfde0e, 0x7d60fd06, 0x73c368e8,
+ 0xd8bc7ace, 0xe0eb6dcd, 0x366204fe, 0x2f3d79e1, 0xc8ca72fc, 0xb98cf478,
+ 0x8310c117, 0xdadc08cf, 0xf4c6d2f6, 0x41af70b5, 0xe780d1a9, 0xf59e0543,
+ 0x75100efd, 0x40d9adfd, 0xd943eab7, 0x8704ffb4, 0xf9c709e4, 0x7aeaf5de,
+ 0x8941d93a, 0x4b7abcc3, 0x8df778a1, 0x876e8f5d, 0xbd478332, 0x33a8cfb8,
+ 0x4f52bec2, 0xdb12433f, 0x693c509f, 0xcf6ea5ee, 0x16e51aa4, 0xf9b707d8,
+ 0x429b3ef1, 0xa677de0b, 0x49193fd7, 0x63c50dca, 0xf8fbec2e, 0xe22ed034,
+ 0xded6ab77, 0xe0ce33ff, 0xbf0248cf, 0x14274ddf, 0x781de726, 0xaf51791f,
+ 0x6eb0255e, 0x3ebd86ae, 0x050e97e8, 0x4c915df5, 0x375d2ac2, 0x09789757,
+ 0xbfda99c4, 0xa4bee372, 0xf385de08, 0x90e78a15, 0xf458f14a, 0x05678e4d,
+ 0x5f5363a5, 0x74f4179b, 0x38b1af53, 0xe9af535e, 0x9dfac132, 0x4b6bd432,
+ 0x8e80abfc, 0xb2337fed, 0x2e0ffa71, 0x4fe6fd65, 0xa96f7e84, 0xd30f0d5f,
+ 0x69278671, 0x5eb169d7, 0x30b5f5d2, 0xb27dd709, 0xd4dfbe0a, 0x6889b1eb,
+ 0x7af8dcdf, 0xd7e9e38d, 0xa656f5eb, 0x417623af, 0xfdeec5d8, 0xff3979e7,
+ 0xb8f4c49c, 0xf0ad1df8, 0x834fc1d8, 0x90e678fd, 0xd0c73641, 0x49e2d3b3,
+ 0xa5cdf882, 0xe049798d, 0xc7443c67, 0x391bdf87, 0xa41dfbac, 0x37b9f423,
+ 0xebe53ea6, 0x73e62316, 0xffa0ad7d, 0x4cfe4a72, 0x573bae76, 0x2387dc8a,
+ 0x3b9f5151, 0x7c9f5b50, 0xb43dfb2f, 0xe77a7e7f, 0x687bf093, 0xf5154cef,
+ 0xbee127fa, 0xb0aab9ce, 0x687f78b3, 0xbfed05ef, 0xee77f6c2, 0xe3b7fd11,
+ 0x2a4915fb, 0x8ca9f3ce, 0x704be3fa, 0xd4f3655f, 0x785e28aa, 0xfb4c4f7f,
+ 0xddaf67a9, 0xb5e77e7e, 0x30fabfdb, 0x77f47b4e, 0xdfda6cca, 0xf3bfe075,
+ 0x41877e20, 0x2ec7f5ba, 0xccbae7f0, 0xb0c7b7c1, 0xbc408475, 0x9d9433a2,
+ 0x51af2f14, 0xefc1ef94, 0xc57e4063, 0x6d073bd4, 0xdefc7ca5, 0x61231eb8,
+ 0xffa8975f, 0xdfda85dd, 0xd289f8b1, 0xfa15edb6, 0xb4de4fde, 0xb410567b,
+ 0x012796ef, 0xff3d8c5f, 0xe51578de, 0x4ffbe30b, 0xfc60b18d, 0xafa289f0,
+ 0x45ef705c, 0x20ca4abb, 0x9265f88e, 0x5a5bc9ac, 0x25fa549d, 0xc097e3f0,
+ 0xdfd0e973, 0x4267b9a8, 0x7d262f94, 0xa5b57ccb, 0xbf45ce5d, 0x485f7008,
+ 0xe30ff0fb, 0x7745e409, 0x89e73ee0, 0xc68769a2, 0xd1b0bec3, 0x7ce236e4,
+ 0x80bc06e8, 0xf01b4de7, 0x85e217fe, 0x287281f6, 0xa78bea87, 0x0fbc9caf,
+ 0x8f6daaf4, 0x41e20529, 0xb16e066b, 0x69aedf00, 0x54c2f764, 0x996ad9ee,
+ 0x358f431d, 0x54e7bf2a, 0x8dee590d, 0xe1ac43f1, 0xf3f46de7, 0xf86493de,
+ 0xe62de74e, 0x07bfe74b, 0x69655ef0, 0xf8bd00cb, 0xf409d174, 0x320e9657,
+ 0x76da39e2, 0xa47a848b, 0x97cbe784, 0xff7019a4, 0xe2a67e0b, 0x65b2f598,
+ 0xf4314a60, 0x7cb2762f, 0x4e0eb17e, 0xe699f434, 0x64cbf583, 0x7ac471c0,
+ 0xbb186137, 0x4dc266a7, 0x0bcf764e, 0x51dea7df, 0xd803c6c8, 0x66e5afd0,
+ 0xf9ebccfb, 0x154ee89b, 0x9fbd23d7, 0x25fefc49, 0xcf34a75d, 0xfee24e3f,
+ 0x85e91b71, 0x7fc1a7bf, 0x6836d087, 0x981caaf3, 0x7e82a177, 0x15f276a7,
+ 0xec4583d6, 0xc04ff93c, 0x3f7c06ef, 0xec7182d6, 0x09e2bee8, 0x8181cfa4,
+ 0x76f11072, 0x73fb8ccc, 0xde26a761, 0x8b23108f, 0x108d7bc3, 0xd4ca7f6f,
+ 0xf3e70996, 0x7f15635c, 0xead1ff3c, 0x6f734924, 0x8bf3e12e, 0x0dab5fee,
+ 0xb9b5bfb0, 0x85099e58, 0xaafded17, 0x3f9eecbd, 0x0adf99d9, 0x993677f0,
+ 0xf59c7355, 0x02179457, 0x5790bea1, 0x867a0edd, 0xe78259e9, 0x76efc404,
+ 0x60cb19d6, 0x360eda3f, 0x299bd516, 0xffac4e75, 0xcc157037, 0x0080005f,
+ 0x00
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1[] = {
+ 0x00088b1f, 0x00000000, 0x7de50300, 0xd554780b, 0xf33ef0b5, 0x9324849e,
+ 0x32484277, 0x01288081, 0x95100486, 0xd024275e, 0x3bc20408, 0xaf090248,
+ 0x01324804, 0x54b63fc1, 0xd4180806, 0x8bd1782a, 0x583b43fd, 0x8350b450,
+ 0xe8350d44, 0x55b15784, 0x6a22aa1c, 0xa14786e1, 0xb4010954, 0xb96bfb17,
+ 0x77bdad6b, 0x44c9ce66, 0x77dfa2d4, 0xf57e9bff, 0x9c7ecfb0, 0x7b5ad7b5,
+ 0x73def73d, 0x0d856151, 0x63198c19, 0x98364e0d, 0xe257cab1, 0xc615e8b7,
+ 0xdddfe3ae, 0xfaf93650, 0xdd3ea038, 0x086c6766, 0x04ac7594, 0x0c5fd3db,
+ 0xf7fb1763, 0x6861e678, 0xcac7517f, 0x9abce355, 0x169f45b4, 0x37d98e30,
+ 0x9e8e3554, 0x19c6ab55, 0xd369c7c0, 0x3bf553c0, 0xa6553c35, 0x553c1556,
+ 0x04da781a, 0x781a6d3c, 0xc3535eaa, 0x556e6553, 0x81a553c1, 0x23c04da7,
+ 0x559f6bdb, 0x0c525b8d, 0x3afcde16, 0x58cdd7fd, 0xe77bce2c, 0x8cfeee2b,
+ 0xc9f17c2d, 0xd8c61670, 0x38fac305, 0xb6c54efc, 0x784ee135, 0x0ee0d5fe,
+ 0xf78375b7, 0x279e7d1e, 0xb3b8f3a3, 0xf38d0a6d, 0x191e17b7, 0x7dff7087,
+ 0xf386d19b, 0x4dd9cc67, 0xc5df0a19, 0xaec8027f, 0x39af66ed, 0x3058e11c,
+ 0xf2a00d96, 0xe87e5e29, 0x0bca1eb2, 0xce327b9f, 0x3577df0e, 0xaab74f19,
+ 0x25d24ce1, 0xc49bd3e0, 0xf5b559e0, 0xc018a32f, 0x6bed62e3, 0x7b6d2e11,
+ 0x28b5defc, 0x2fa0df78, 0x1b044535, 0x1c58c9cf, 0xad7f97f6, 0x6efc02a6,
+ 0xf59723e3, 0xc2394f00, 0x7ee7477e, 0x31616c13, 0x3fc1fae7, 0x5fb7676e,
+ 0xc1f1fbd7, 0x44f9303c, 0x6eaff4c6, 0xd38a701e, 0x2fe38743, 0x7f79f0b1,
+ 0xe18ff5ba, 0x455fbd0a, 0xf0d2bb74, 0x0efedfeb, 0xb8e575e8, 0x776341d9,
+ 0x15b6af41, 0x5fc7d950, 0x600137b6, 0x59aef0f1, 0x2afd053c, 0x7f679e8c,
+ 0x7c55e301, 0xe1b87668, 0xf53b157b, 0xa2d70805, 0xdd8f079d, 0xb458f409,
+ 0x963318cb, 0x129ba34f, 0xf80f4017, 0x9fa64d7f, 0x1f770b1e, 0xf787f8e4,
+ 0x74fca3cb, 0x60ebb459, 0x19dfeb1c, 0xbef0391f, 0x7d082335, 0xf47d381a,
+ 0x42657eaf, 0xbaf0b87e, 0x3ad3e2c2, 0x10bc47f7, 0x3a9d051d, 0xe769a6e8,
+ 0x5eb0fa02, 0x3f60fa7e, 0x76e7467b, 0xf9263659, 0xfe5bf099, 0xf381d991,
+ 0x7dedff2e, 0x79ff08e1, 0xebe73543, 0x9ce26bcd, 0xa372ddf0, 0x4f46ce3b,
+ 0x97fcbefe, 0x65fe68cb, 0x31c59747, 0x5133979a, 0x97e68c37, 0x579af388,
+ 0xbe14653f, 0x884acf9f, 0x0337caef, 0xb9f9e19e, 0x0aede581, 0x898e2eb2,
+ 0x19fe7175, 0xbf306333, 0x4ebe26f3, 0x7bd27fdd, 0x58fad1b6, 0x8fac18cc,
+ 0x87c91665, 0xb9fca84b, 0x369d9be0, 0x3f87f51d, 0xfebf204b, 0x6f19d92d,
+ 0x7d6ff9c3, 0xd1f487c8, 0xdf191d1f, 0xe0c1eb4a, 0xae50f816, 0xf839f8c3,
+ 0xdda3f39e, 0xeff45430, 0xd19f4f09, 0xffe01d69, 0xbdf152de, 0x7aecfe80,
+ 0xa21dc11a, 0x1c67840c, 0xf9da4b97, 0xe21522e9, 0xb1f3f867, 0x580abe00,
+ 0x6fbd7cdf, 0xf47c475d, 0xbd7c7bd9, 0xcf7bac74, 0xe76a3c84, 0xc3e37a33,
+ 0xe424ff79, 0x64cb4f47, 0x9937df05, 0xbad83799, 0xeb146ade, 0xf92f5d5a,
+ 0x2836e004, 0x017e7e11, 0x743797bc, 0x824ff3e3, 0x4237f3fe, 0xfd01bebf,
+ 0x9de17bf0, 0xb5eb93c7, 0xa383c84c, 0xfd43feb8, 0xf3d59feb, 0xfad5df75,
+ 0x1a7d7aed, 0xb27e7d69, 0x7bb1ff63, 0xd27c7d61, 0x46a7d720, 0x67d66a5e,
+ 0xd7c14bf9, 0xdf0d27e7, 0x5f7e7d6d, 0x0bacb3f2, 0x0685f9f9, 0xe61a577f,
+ 0xf677eafc, 0x95a8f1ae, 0xbd094f7f, 0xb20e59d7, 0xced0d8f7, 0x6ef927fc,
+ 0x532a6fe1, 0xf802324b, 0xe0a5f24d, 0x4a3f3f37, 0xfd7afbbe, 0x2fdfada3,
+ 0x7d71cee4, 0xf30650fb, 0x1fe2029a, 0x198536e9, 0x2f3c1158, 0x37669ded,
+ 0xc6d7fd00, 0x17a81c5a, 0xd64bea4f, 0x09ff5a30, 0x0b26feb4, 0xbda199b8,
+ 0xf4c3e50a, 0xc3db50e6, 0xffdcfeb0, 0xf839ca60, 0xce1ab20e, 0x9bf34a7f,
+ 0xc77c205f, 0x896dcc8d, 0x02d7f3f2, 0xb398c94b, 0xfa2420d1, 0xc65f242a,
+ 0x98f7aa3f, 0x0c969fe1, 0x57f00ff8, 0xc7a330c1, 0x45fde30c, 0x8df04057,
+ 0xeabdbacd, 0x897d0427, 0x86f800a9, 0xfafd797d, 0x5ca38070, 0x00a081c2,
+ 0x80b0177d, 0xc32fa83f, 0x7f390c27, 0x410de2b8, 0xd8526f3a, 0x2c3c00e9,
+ 0xf8cba8f0, 0xfe716ff7, 0xbed46f71, 0xb37475ab, 0x7c09ff9f, 0xb19d3a75,
+ 0xf034f853, 0xf3f206e9, 0x478e66ac, 0xe9e28557, 0x1af27449, 0xffb24f11,
+ 0xfef72146, 0xd0d67973, 0xd93f5812, 0x408ff78f, 0x19960bf9, 0x90977de9,
+ 0xf6dc57a7, 0x572bd408, 0xa0457b9a, 0x3872b8de, 0x6bdb1c27, 0xf82a39e1,
+ 0x1615ddfc, 0x55ca5e7a, 0xdd61ebd6, 0x64ed625d, 0xad73b94f, 0xbb105b6c,
+ 0x8764696e, 0xa1fa607e, 0x5fe497a8, 0x0ec7ad35, 0x7f9a3d3a, 0x33a030c1,
+ 0xb4eff1fe, 0x7ffa8394, 0x9eb8af1d, 0xad479f10, 0x820aa3ad, 0xc0ad73cc,
+ 0x5f7dd8db, 0x4d8e5098, 0x22334e6c, 0xeae6263e, 0xc075c351, 0xb0a460f5,
+ 0x1658b2b3, 0xdf7635c2, 0x2077e13d, 0x1deb0e3d, 0xababc056, 0xa4a9b2f9,
+ 0x88f18dff, 0x7afda3e3, 0x8f98e8c6, 0x73f33c78, 0x3ac3732b, 0xf5c75b78,
+ 0x51395401, 0x4e50c1af, 0x238fdfd4, 0x33be013e, 0x4e7a3691, 0x8c6d9b1a,
+ 0x3466ef85, 0xe1e906da, 0xfb45ddbb, 0xaa769133, 0x64fd124f, 0xbc15eebb,
+ 0xad9329dd, 0xa3fcd82a, 0xe7fcf9a2, 0x099f743c, 0xba274444, 0xb5753a49,
+ 0x7a2fbebe, 0xe61e3f65, 0x68f6811d, 0xa37242ae, 0x5a331f33, 0x14f2570f,
+ 0xe434cacf, 0x8f2f3d67, 0x0f283c55, 0x7af1d6de, 0xec8544f7, 0x5ae7c91a,
+ 0xf826befc, 0x63ff7e55, 0x7246f651, 0x57e2493b, 0xaf0b55e2, 0xeaf20f6c,
+ 0x3f7940ee, 0x6fd069be, 0x557ef815, 0xc1d362b3, 0x56865550, 0xc3ec8393,
+ 0x67f4460d, 0xb8f9dba6, 0x603050cc, 0x9cdf0072, 0x3d103489, 0x35de67f6,
+ 0xeae3f913, 0xf38666a3, 0x1cbdce77, 0x6df37a8e, 0xbb9de39d, 0xd11dfd70,
+ 0x235f6db3, 0x615e3e9f, 0x086b9d1b, 0xe08d371c, 0x6d91549c, 0xa334f544,
+ 0x1f18c5a2, 0x226747c0, 0xbe5ea8a3, 0xcf615eef, 0x3df0f7c4, 0x98fdc382,
+ 0x21836d99, 0x237c1a32, 0x467ea142, 0xbfe72475, 0x131686f2, 0xbda8d395,
+ 0x8efc9efc, 0xc9cd1d76, 0x7881ed69, 0x54363c98, 0xd9ac7ef5, 0x8411d4bb,
+ 0x14a36b3f, 0xa3be4f21, 0xdf02705e, 0xff339106, 0xa585e9df, 0x1ab42f52,
+ 0xfecace51, 0x017f02f9, 0x983e217a, 0xd2b2585e, 0x59748f1e, 0x3c57b7b2,
+ 0x6f25922e, 0xa60b8c8e, 0x3807de17, 0x3ec720ec, 0xcf867900, 0x2f41934b,
+ 0x0bd00c0c, 0x27c4ad93, 0x47b77eda, 0x1e5da4e9, 0x3a482f5c, 0xe17ac0fd,
+ 0x410bd47d, 0x28e8f5d6, 0xda985eb5, 0x617a4a5c, 0xb33d64ea, 0xd9e9d807,
+ 0x0bd23751, 0xa9d371d9, 0x0684746c, 0x27c41be1, 0xe27c7133, 0xfa83bf13,
+ 0x97144561, 0xd13d5af7, 0xf94f1c95, 0x8bbc72a6, 0xe17df0f5, 0x25f1ca57,
+ 0xf7b21453, 0x231df33a, 0x1d325dfe, 0xfc82b8e4, 0x92f8e5c7, 0x69e39062,
+ 0x2d5c93ac, 0x383ab940, 0xfef2ae50, 0x0f5c2555, 0xfed29ab8, 0xefea08a3,
+ 0x58746f5d, 0x7ebdfda0, 0x50343b39, 0xea88aece, 0x7396ce42, 0x39b57b39,
+ 0xaea3ec8b, 0xc84277e6, 0xe9679057, 0x517c208e, 0xecca1458, 0x333df801,
+ 0xbb19f7e8, 0xadbc7d71, 0xa3b6f477, 0xfdf5cbdd, 0x3f7e835b, 0x0f80fd18,
+ 0x09cf3c05, 0x633f03be, 0xfbac2e74, 0x5edcb99c, 0x27a1dcae, 0xf23555fc,
+ 0x5db55ef5, 0x3ca1d8f1, 0x130bf32a, 0xe5ed1796, 0xc1980cf1, 0xba00ecd8,
+ 0x75bb7a2f, 0x6fd6126d, 0x8e6e1c51, 0x7c877b43, 0x3be63804, 0x325f9116,
+ 0x087edcd6, 0x4e7d8ddb, 0x7e416c71, 0xbfdc14d9, 0x16fd14aa, 0x5ef5b478,
+ 0x8e95cf92, 0x2d6fe475, 0xafaeaeda, 0x0f97506c, 0x4f34b909, 0x0dd8cdef,
+ 0xe8ef65df, 0x99f4c11d, 0x8f81d76c, 0x1f117ff2, 0x831f0147, 0x058f8c6f,
+ 0x8c262dcd, 0x3c5b7c4b, 0x1ff9d37c, 0x677e128e, 0xeb8c1b26, 0x273a2fed,
+ 0x1ff70dc9, 0xee300f00, 0xe3bd0ddc, 0xeff8024b, 0xb78be098, 0x136b2575,
+ 0x42955db1, 0xc1eacaed, 0x517286a1, 0x27a41b03, 0x6af5a9ba, 0xb46f3e87,
+ 0xaa2ebe93, 0xcecca5de, 0x6ab3bc40, 0xcf72bfe4, 0xa1dd5186, 0xf406b8be,
+ 0x939fb437, 0xf8c12e69, 0x3b6b51d1, 0x9fc945c9, 0x9fce68fa, 0xc7a7344a,
+ 0xb9edee99, 0x149a77a4, 0xaf3bad1b, 0xa021eb95, 0xfbca158b, 0x51aff8ef,
+ 0x33360e82, 0x374e4bad, 0xd709d017, 0x5166a8ed, 0xddf6e06e, 0xdccbe68c,
+ 0x316e6fff, 0x6872bf62, 0x2408ad1f, 0x677afcab, 0x00b8ecb7, 0xc53dee7a,
+ 0x429b7bf9, 0x81e64b71, 0xe7a105ff, 0xed28e88d, 0x4f4aef8f, 0xb47d1789,
+ 0xad47ae9a, 0x0059b1be, 0xc55efb5f, 0x3ebc0cf1, 0xd117bebb, 0x52473595,
+ 0xfa26c17c, 0xbfa33a49, 0xcbf93760, 0xf4501013, 0xecacf3ab, 0x4f5efc8c,
+ 0xca05576e, 0xcb77e91b, 0x56eda2e7, 0xbc1559db, 0xabb2aa91, 0x3676d129,
+ 0x7cc4de30, 0x845aa714, 0xf1ae002f, 0x914d92fa, 0x0aedafa8, 0x1d151bd9,
+ 0x75a76ff8, 0x9fc6137e, 0xe335f510, 0x0e9b04b3, 0x4d9f78e9, 0xbd11b7be,
+ 0xfef28b66, 0x141fa1e4, 0xd6af5e01, 0xa0661de9, 0xfd9d34df, 0x239470d8,
+ 0xae191b0f, 0x196fab8b, 0x87ae5c9d, 0x7d291e92, 0xf5118cfb, 0x1b7c2962,
+ 0x67f4abf9, 0x119c5f5c, 0xfa047cf0, 0x50b189d7, 0x026430d6, 0xa3b27f7c,
+ 0xf81da465, 0xa3e0ca61, 0x3bae306b, 0xec76c729, 0x9d71d218, 0x4f1d219e,
+ 0x7f90e5d7, 0x8562df75, 0xa071d5d6, 0x329ff61b, 0x31d8ed39, 0x5d716ef8,
+ 0x8a48c52c, 0x0b53b19c, 0x96f45ca1, 0x768761de, 0x7587c673, 0x316bb8c3,
+ 0x38c1adf3, 0x7abe98d7, 0xa7801256, 0x53c5eaa2, 0xd072ee10, 0x2967986f,
+ 0x323a3e6f, 0x0af5cb1e, 0x4bb977f5, 0x32c0f14c, 0x4d974dbe, 0xf3fbe183,
+ 0xdda21da1, 0xb9dbcf55, 0x580e2ab6, 0x037ef089, 0x5bf9c1c9, 0x5f218615,
+ 0x16afd81f, 0x02c7ae3e, 0xa1eafae3, 0xb0cb943f, 0x35bb8e3f, 0xae216a72,
+ 0xfa93805f, 0x08795b0f, 0xe87ce4e5, 0xb7ccd507, 0xb78d3175, 0x09615ea0,
+ 0xb0f95e30, 0xe186c7b4, 0x1d196f78, 0xcb41ff58, 0x9f5714d3, 0x844bdf09,
+ 0x5be8e7f1, 0xf67b6247, 0xf686c553, 0x8e3c9b20, 0xac4977e8, 0x4f9e9637,
+ 0x614bba76, 0x04378ed2, 0x47b76bc6, 0x337924f7, 0x5ae566bf, 0x3bab579c,
+ 0x7c474d36, 0x7a84d975, 0xc7898cf9, 0xde02cf7f, 0xdd0ec04b, 0x42633eef,
+ 0xba307dbd, 0xdb9bf517, 0x64f24d94, 0x78a02b1e, 0x6e4ac962, 0x635a9c57,
+ 0x476828f5, 0xf8296d19, 0x331aff7e, 0xe4ed53cf, 0xb92da4fa, 0x6dfa24f5,
+ 0xcc8debe7, 0xaeadb00d, 0xd214f5ef, 0x230efcef, 0xb37e99f1, 0xd956e491,
+ 0xdacf1e4e, 0x3dc7cf5f, 0xb1cb9dbf, 0x4653cd9c, 0x032e7ca1, 0x79a66479,
+ 0x7cd5e5a9, 0x371e42fb, 0x3be5bf5d, 0x3d0e97e9, 0xcf2d63db, 0x2e40dc83,
+ 0x293758b9, 0x7e31328f, 0x3c995a5e, 0x6df21373, 0xf8da95b1, 0x7f3e7bbc,
+ 0x4567f512, 0x5537c318, 0x0a53db06, 0xeb8603e7, 0xd779a8a3, 0xe5f7c8e7,
+ 0xe2075645, 0x1be21cff, 0xd1a3c9d7, 0xef9d4f14, 0x973c2529, 0x73c26ab1,
+ 0x3f3526d9, 0x33d12f4f, 0x2a3ea067, 0x20ce650f, 0x9f83eb72, 0x77c27f01,
+ 0x1e293566, 0x53e582ab, 0xa60d9687, 0xaae08db2, 0xd1fe7a11, 0x0fdfe230,
+ 0x06bcb81e, 0x72e673f9, 0xcd9da185, 0x516b25dc, 0x526d55cf, 0xb9430fec,
+ 0x5fef396c, 0xee11fd06, 0x7ce69e0f, 0x476cfc04, 0xdfaaaf7e, 0x6fda8870,
+ 0xfe38ec55, 0xc94a5b07, 0xeb77282e, 0x3d6fd519, 0xe83f7645, 0xecbbca21,
+ 0x90e3eb77, 0xcd6aabdf, 0x0e98e036, 0x77fc91fe, 0x510ac8ca, 0x638b329f,
+ 0xb7e824c0, 0x941eda34, 0x4a85f50f, 0x7e449e87, 0x7f39b971, 0x7469da9d,
+ 0x31b852e0, 0xff89ea3f, 0x91e9bf24, 0xf9fb06df, 0x8e7d7f6d, 0xbceff909,
+ 0xf90cca07, 0x95e348d1, 0x28e32f3d, 0x3da05bac, 0x12b1f924, 0xb3e50af8,
+ 0xfcb51f96, 0x04df89d7, 0x0ef96a1f, 0x08a9ff6c, 0xac6b7de7, 0xdace7704,
+ 0xf86b533d, 0x6708623a, 0x2807dace, 0xc0df300f, 0x8f12dde3, 0x0f9e0695,
+ 0xa571b059, 0xb7f54509, 0xc7034786, 0x9c7d7e93, 0xb578fa89, 0x3f25e1c9,
+ 0xf642a875, 0x7b5b38e6, 0xea45a22e, 0xb862bbdb, 0x5f1ab59d, 0xcb159da2,
+ 0xf4bf283c, 0x3bc23a49, 0x9953b54b, 0x04a7b7a5, 0x62535fc6, 0xd7d3dc64,
+ 0x87e7df03, 0x2c4ef942, 0xbcc68c87, 0x5359be5e, 0x7051d08e, 0xd1d0b189,
+ 0xc7e5efe8, 0x943bb28b, 0xfac927d7, 0x2a9cbc6e, 0xf1bbbbfa, 0x7d64fdf6,
+ 0x940f2f18, 0xfdbc61f5, 0x93ea8c5d, 0xbb47c263, 0x9b3e1033, 0xa8f1be0a,
+ 0xfbbf629c, 0x91d66f53, 0xd7b5a8fd, 0xf191896f, 0xe9f1461a, 0x1fdfe682,
+ 0x81563cc7, 0xed179ba5, 0x7e34e628, 0xc7601ada, 0x7902ac30, 0x23f04637,
+ 0xa037098b, 0xff8d185e, 0x59d13e06, 0x97b406bc, 0x2dbc18c6, 0xac2dce38,
+ 0x2fae76d6, 0xc6d9b326, 0xfb5d59eb, 0xce4ea867, 0x8ab3f805, 0xb41ab193,
+ 0x161c6aa3, 0x7740378c, 0x4ff2b392, 0x2f28dbb1, 0x86cf1202, 0x9cc2bcfe,
+ 0x1ca1ebba, 0xc247843e, 0x12e8e127, 0x2180a04e, 0xa7ace10a, 0xf382ba71,
+ 0x1bb320d2, 0x909798f3, 0x0f6e88cf, 0x5dba458c, 0x07c132b2, 0xeb261ca2,
+ 0xbe74467f, 0x45eb2914, 0x9f535639, 0x791b29a8, 0xfd3129fb, 0xbc61bb46,
+ 0x94e77a65, 0x47efe018, 0x68dc4b62, 0x3b9f0117, 0xc9e7c8bc, 0xcc27f226,
+ 0x98756ea6, 0x090baca7, 0xbe00c01f, 0x338ac1dc, 0x2cc57f70, 0x6267e7c1,
+ 0xa4673c78, 0x51f57d79, 0x0fc03bb4, 0x5dfd095b, 0x61355e5f, 0xf9bf227c,
+ 0xafe10994, 0x8a39046a, 0xbe632c4f, 0xf4e4deab, 0x4b9be104, 0x37c97a31,
+ 0x8d829f7c, 0x7260f5e3, 0x2831359f, 0x7972e7a7, 0xe44f64b6, 0x292f2c48,
+ 0xbdfef6e5, 0xc48d77c3, 0x2d05c56e, 0x8b39f06b, 0x16441eb5, 0xd763bd44,
+ 0x7b409de8, 0x5a3ab8b9, 0x1eb59e55, 0x6c7209a8, 0xaa924d56, 0xee79131f,
+ 0xa1567ee9, 0xa0a16378, 0x4784f4fb, 0xbd3ddf29, 0x0d6ee8c4, 0x79bf2f18,
+ 0xe10a21a5, 0x6f4856ae, 0x63b39a82, 0x867c19bf, 0xdbf834f0, 0x36461d03,
+ 0xc156fd09, 0xf0917ee5, 0xc1ca8a97, 0x0f1055af, 0x2dfc2626, 0x36a7f70f,
+ 0xa60d46e4, 0xe1039fb8, 0x351f3570, 0xcb19fb62, 0x7ee26fc0, 0x2cf7f12f,
+ 0xe9dbb409, 0x1b800f4b, 0xff2371e0, 0x4acd79ca, 0x7b44673d, 0x41f510a4,
+ 0x6ce7cd38, 0xea7f0aab, 0xbab57172, 0x5d46ab3c, 0xe4231ade, 0x0fd63f6e,
+ 0xc9a7dfd7, 0xe1788ec7, 0x28c7cfbb, 0xca1fcc06, 0x05f4abf7, 0x2b1f903b,
+ 0x8c01de4c, 0x965425ca, 0x157de1ed, 0x46d5a5ea, 0xe51b2da7, 0x7bf72576,
+ 0x5ba70a81, 0xb4280e49, 0x396067be, 0xac809f60, 0x73beb2a7, 0x539094f9,
+ 0x4b05adab, 0x9f801f49, 0x5c82798a, 0x9510d383, 0x30a2eb41, 0x2d3b7c98,
+ 0x0308fff8, 0xf57005ed, 0xba04a641, 0xe11499f4, 0x9f5cf8c1, 0x18dd4a37,
+ 0x0593ea9f, 0x3ca3b774, 0x3ed779e0, 0xd24286fa, 0x644d031f, 0x79118f0f,
+ 0xefa071d8, 0x787724ac, 0x13ca55de, 0x3ceaf3e7, 0x672f7a6b, 0x17f406e6,
+ 0x02fe1c7a, 0x4db8cfe5, 0xfa5f928f, 0xff7f9588, 0x9fdc3d91, 0x4438caa9,
+ 0x29de36f2, 0x5c09f4f2, 0x7ca3c6ee, 0x04d7f943, 0x81e257f2, 0xf1396fe4,
+ 0x6ef89c49, 0xf829f312, 0x5b825351, 0x1b2778c1, 0x2570419b, 0x983edc0a,
+ 0xc7f9a764, 0xcf90380b, 0xde2ace50, 0x20ebba11, 0x9b41deef, 0xf9ff887f,
+ 0xe944fd6d, 0x6a1eb21f, 0xc5fc10bf, 0x8fb83159, 0xec95a126, 0x87eaefe6,
+ 0x0bf8cd7e, 0xd30f8d82, 0xca543f23, 0x2ffa91a3, 0xe3283e29, 0x1fe95de4,
+ 0x92a745bd, 0x885b4623, 0xe98cde4a, 0xf93f96ab, 0x19dcb50e, 0xaa97ac3f,
+ 0x9fb3827e, 0x5e527eaa, 0xa53caa96, 0xfb552ee0, 0xaa398569, 0xb46139b2,
+ 0x3ed5bdaa, 0xed0e5551, 0xfdbaaf7b, 0x2a172f9b, 0xc7308780, 0x933b556c,
+ 0x025addc5, 0xb583a878, 0xdb0a2c32, 0x32f04b2d, 0x44b0debf, 0x4364b0ec,
+ 0x678a37f9, 0xfa368604, 0x9f685b85, 0x95964851, 0xd88b5efc, 0xc8375867,
+ 0xa9fe45ec, 0x067a0eeb, 0x9cb6dfde, 0xafccf4a9, 0x933af812, 0x25b181cf,
+ 0x3f01c577, 0x27b76c65, 0xefb6f8f1, 0x258fa436, 0xecbb7184, 0x65d90b15,
+ 0xde9f5103, 0x9dc71fe1, 0x16383d94, 0x772c67fa, 0x68fe43de, 0x86f5b313,
+ 0x8098cf76, 0x5ef7a8b2, 0x8cbf5131, 0x339d56a6, 0x637bbd60, 0x64f81db9,
+ 0x987b88c1, 0xbea33788, 0xda74daac, 0xaa80f184, 0x87da16e6, 0xb4e0a038,
+ 0xff7bed09, 0x0ce7a17b, 0x1fb821ed, 0xe086c5ea, 0xc71713fb, 0x875e689a,
+ 0x5e2f5c84, 0x39f617a6, 0x394a578f, 0xddabbc5d, 0x4278c7ab, 0x295e3aa5,
+ 0xd794b6e5, 0x52f30ef7, 0x76e4037c, 0xea527f50, 0x9ae39001, 0x9a2f9e7a,
+ 0x387c7685, 0x1ad3f5c9, 0xc72eaeb9, 0x8cf5c876, 0x8eff20eb, 0xce82e817,
+ 0x3c0937ef, 0x24bc785e, 0x24fef087, 0xc41433c6, 0x1c5f16a7, 0xd3c2378f,
+ 0x15cf994e, 0x7bb6d2f4, 0xf3cb8135, 0xedc85d9d, 0xcf9e8243, 0x944cbe28,
+ 0x1082ae6f, 0xb819cbe2, 0xe90b254f, 0xe8b5f7f0, 0xacbf1567, 0x1fafd430,
+ 0xfb49bcb7, 0x5fb84c9a, 0x6292e309, 0xd185533f, 0xcdf712be, 0x56383f00,
+ 0x9aaa7d02, 0x657f04bc, 0xbe0b5643, 0xf1e26caf, 0x8f235717, 0x56b15667,
+ 0xe99efbf2, 0xc79fae02, 0x536a3b72, 0x77e09dac, 0x5137c095, 0x3d9a37cf,
+ 0xdfe9051e, 0xe297714a, 0x0f5b0a3d, 0x59d667e5, 0x4fd9830a, 0xd0df11fb,
+ 0x133ac0ff, 0x54bf0033, 0xc79c7f40, 0x2643e4a1, 0xef14fb8c, 0xe1bf2852,
+ 0x053a386a, 0xa5aeb7f3, 0x85768646, 0xb262ef84, 0x0fccfc8f, 0x733f0ae7,
+ 0x7c6b8f2e, 0x23db94b8, 0xa17f79fa, 0x4af4eb38, 0xbdce67e1, 0x0fa1f14a,
+ 0x399f85cb, 0xa645c78f, 0x1e79962f, 0x3e4b1f35, 0x96a3f2d5, 0xfe55ff5f,
+ 0xf22b1ddc, 0x00d8fd71, 0xef40f3d4, 0xbbe7e891, 0xefe4601f, 0xdfb97e15,
+ 0x9e807188, 0x558e6d6b, 0xf7afee50, 0x39f8c1ac, 0x07ebcfdb, 0xb8516c55,
+ 0x8bdfb17c, 0x33aa49f3, 0x7cbfdc31, 0x10e9d048, 0x7bf709d2, 0x142576b1,
+ 0xd7c1abd7, 0x1a50e513, 0x3c0013ee, 0x856464be, 0xc4df28bb, 0x57ff4be5,
+ 0x1c3cb613, 0xc7f7afc0, 0x72953e72, 0x95899fb0, 0x6b3d42ec, 0x718ee868,
+ 0xbe469dc7, 0x8c453b6f, 0xfb57bbd7, 0x3cf009a8, 0x8befbe2f, 0x9650f2e5,
+ 0x3f7c163f, 0x845bc6ba, 0x394d8f70, 0xabfa8156, 0xb1c96467, 0xebafa858,
+ 0x8a0c87f9, 0x234e1737, 0xf22f9e3d, 0x38effb6e, 0xcc1f7f5f, 0x086b7acf,
+ 0x925e0fd1, 0x7671939e, 0x360ddeeb, 0xef6b5fe4, 0xf2c1f1c1, 0xbae9f2c0,
+ 0xb0256766, 0xf5aeaa7e, 0x4f2ca7a4, 0xd4c177d8, 0xe5ff764a, 0xae3eb451,
+ 0xd97bd025, 0x77011def, 0x77d8937f, 0x7a431cde, 0x61b2e419, 0x5f806658,
+ 0xf720f02d, 0x6f7b5a3d, 0xb7dd7a25, 0x663be798, 0x4a551c54, 0x495b3fb1,
+ 0x4e8cd3f5, 0xf7c03763, 0x31c288b1, 0xfb19d367, 0xbc2b8883, 0x7142c2b5,
+ 0x6c2b23ab, 0x48adf654, 0xd16df2a0, 0xfd40ff25, 0x7615a7f0, 0x50394f2a,
+ 0xb8f11bdd, 0x02a9f93f, 0x7a5e5bcc, 0x23f028cb, 0xd782d1e2, 0x29eb36ae,
+ 0x91b5755e, 0xf09137ef, 0x9dd6bccf, 0x78f34495, 0x6a33c532, 0xe73925de,
+ 0x0a3cbf28, 0x1541a0fd, 0x3ed2d6a7, 0x69cf9ae1, 0xd049eedf, 0x69079417,
+ 0xcad571e2, 0x3b26a3a6, 0xb5d141f0, 0xa7671a28, 0xae147dae, 0x0aebf733,
+ 0xd938f7ed, 0xcf14d974, 0x79a511f5, 0xf9dc45ea, 0x2e48b8ce, 0xe9079a3f,
+ 0xcf22de88, 0xb77bf72a, 0x708ff6dc, 0xc6a587a4, 0xaa47fb4e, 0x0e29eb0e,
+ 0xf688f0f3, 0xb9105b70, 0xdc6cf18b, 0xd891f4af, 0x2fada4b7, 0xe37bb934,
+ 0xc142817e, 0xa1fadac7, 0x3f7cfe71, 0x622eefee, 0xeb47cff2, 0xda1bfc19,
+ 0x9cdc544f, 0xeb40c173, 0x47c987fa, 0x87fa32cb, 0x41dec02c, 0xbea990ff,
+ 0x9a7c26ef, 0x7955d393, 0xdffc4eb8, 0x81d99dda, 0x8075554e, 0xf3e42ce6,
+ 0xb6d9e8db, 0xae3b21e7, 0xfb484b1b, 0x5817a853, 0x17f91d1f, 0x9db56e95,
+ 0xeb813bd3, 0x1c09dea5, 0x84f7e05f, 0x07e463ef, 0x677b404d, 0x4bf81c5c,
+ 0xbf87597d, 0x5127e014, 0xfd2f6cbd, 0x27ae0b24, 0xa03f6ef8, 0xe0414bcb,
+ 0x6230941e, 0x614bf62a, 0x19bf89eb, 0x95f237f0, 0x71a59e76, 0xf5ca7d7c,
+ 0x73d71d3c, 0x69dfc506, 0x1dc76b3d, 0x8a5d909e, 0x2c63aee3, 0xcb9e982f,
+ 0xdcacf314, 0xae5f08c4, 0xa784514d, 0xc1536c8b, 0x8bc7e008, 0xc033c700,
+ 0x0a0a978f, 0xee312342, 0x1a105251, 0xfebfcdd5, 0x508536ab, 0x13e975bf,
+ 0x7ca14ba3, 0xe63bf23f, 0x2c729bc9, 0x9b99e788, 0xdf93baf8, 0x1e9de93b,
+ 0x8868eb8d, 0x7984ddb1, 0xa7cd1ebd, 0x1bbed1c2, 0x345267b2, 0xe0aebfae,
+ 0xe7cf1f9c, 0x84b3595d, 0x56baaff6, 0xf112ffb5, 0x9fb87f8a, 0x67d09162,
+ 0x5133c7c0, 0x193457be, 0xbcb43f49, 0xae1571f2, 0x50e6b6e3, 0xdc5e77ca,
+ 0xac38c9fb, 0xbd3bf4bf, 0x45e5074d, 0xddf88c35, 0x4f27faf5, 0xbd73fae1,
+ 0x8e4b4662, 0xe87e6a2d, 0xad9fee32, 0xf687be68, 0xf8ec5467, 0x6541d761,
+ 0xff64fdcd, 0x2b27f2c8, 0x3728052c, 0x2e5c0cdb, 0x4dda6a2c, 0x2fa2ecf6,
+ 0x7cc00eaf, 0xffbdc5f0, 0x31ca286f, 0x87571bd7, 0xbd72fca2, 0xd6287576,
+ 0xad0d5ebb, 0x9c97660e, 0x9d13d04f, 0x7b4c7ea4, 0xff8aa0cf, 0x207a124c,
+ 0x5e7d76ad, 0x90d7c04f, 0x811d93a3, 0xf486c8fb, 0x8679d1d6, 0x46e7ef21,
+ 0x57e80bcf, 0xe1e433eb, 0x7347c1fb, 0xf006e743, 0x51825e63, 0x14ef9dca,
+ 0x5ce261b7, 0xacd38c82, 0xaec819f3, 0x1e2b9771, 0xf8661bf4, 0x014e7474,
+ 0x3f6d14ec, 0x2d2e97b2, 0x4c3cf688, 0x98c14176, 0xdcb183fe, 0x08f981db,
+ 0x4c1cb6e6, 0xa687b00f, 0xdfb474fb, 0xecd9b0bb, 0xe668bb45, 0x6961f3e5,
+ 0x19f2b718, 0xb4b7df68, 0xfdf46697, 0xd39448d3, 0x8f4c78da, 0x1f2e9b6a,
+ 0xcb5457be, 0x6d2f886c, 0xc2fe067c, 0xced21e70, 0xec6bc6d2, 0xec168dbe,
+ 0xd9d74f6f, 0xfc6d1e10, 0x4899da46, 0xeb20c6b7, 0x5f3c667d, 0xd51d72cf,
+ 0x8f4474fa, 0x4b08df5a, 0x89a73c3a, 0x9b5046fa, 0x6d43c06e, 0x986da4f3,
+ 0x72fdab77, 0xf87f685a, 0x137bed6e, 0xef5c2ad9, 0xde9611b6, 0x1fcbefd8,
+ 0xf864a65b, 0xbdfb44f9, 0x3e5cf13e, 0xe081edfa, 0xac5e2dfa, 0xcf4a1fdf,
+ 0xcfffc745, 0x57e073d6, 0x258f8f77, 0x8f067abf, 0x5abf707b, 0xdca41fab,
+ 0x118ee395, 0x772cee78, 0x02fd902f, 0xddc92ffe, 0x6a76f131, 0x4279a3d7,
+ 0xefc5f934, 0x77b68e4d, 0x2f7e3ceb, 0x95174383, 0x697c79d1, 0xcedcb9a7,
+ 0x5ff41683, 0xe5ff3c9c, 0x1478ac9a, 0xb9d76fc5, 0xb7b2140a, 0x0f46455d,
+ 0xf97093b6, 0xea38f326, 0xf291a714, 0x93fed28a, 0xbd4761f6, 0xa51de783,
+ 0x41ed28bd, 0xcb8f015f, 0xebcc1e4e, 0x111c5ec1, 0xc9e7043f, 0xb90cbbf7,
+ 0xac67bf83, 0x47fa20e0, 0x8c2aa6d3, 0x17b0bbd6, 0xed6a7f25, 0xbeffb949,
+ 0x0bd63a2b, 0x2beb94be, 0xa42eb345, 0xe85fba9e, 0xd3d42ae9, 0xbfa7a8d1,
+ 0xdaddd950, 0x4f4f4171, 0xc7eff845, 0x073c1f80, 0x08286fbf, 0x105f77e6,
+ 0xf497cee3, 0x46c81df3, 0x6f999378, 0x5d8bfa25, 0x6142cfe9, 0x7f5574c7,
+ 0x5ff71c7f, 0xd78eb46e, 0xf8ebc0ff, 0xebe1ffd1, 0x33eec3b8, 0xa0df9f05,
+ 0x7127ec84, 0xabe8879d, 0xeeb8d97d, 0x38a468fe, 0x5cddb6ba, 0xff81a761,
+ 0x83dfe2aa, 0xfa1d26c9, 0xee72ae3b, 0xda45d7ff, 0xe4bf21df, 0xb7ed3d4d,
+ 0x1dfe0459, 0xaf0b67da, 0x8159e8d9, 0x673c3076, 0x794a3f6c, 0x6ae51985,
+ 0x0630ebf8, 0xa717fd8b, 0x62fcfed1, 0xa2714b96, 0xdb48e6e2, 0x7502506a,
+ 0x1fb40db1, 0x6f4dbdd1, 0x7ed816df, 0xe16f6c81, 0x449ab371, 0xd79e6acf,
+ 0xe2fbe956, 0xaf3dad6a, 0x8977ffd6, 0x76574fb8, 0x562d6bc0, 0xeb0e4f2e,
+ 0x61577d69, 0x632068bc, 0xbadfb926, 0xaa39c786, 0xf9d2579a, 0xff514ae4,
+ 0xe28f8357, 0x830f9448, 0x379a17a6, 0x643ae1c4, 0xa7fe754e, 0x24fbeb72,
+ 0xa079b527, 0x8f2e46a8, 0x917a155c, 0xd0aa19f7, 0x7126c77e, 0x1f6ed55e,
+ 0xb807788f, 0xe78ec798, 0xff90ce1a, 0x37cf6338, 0xe138fbcc, 0xcfbcaa7f,
+ 0xd21883a1, 0x53ef2aef, 0x88d474d5, 0xcdb7c17e, 0xef8d9cff, 0x9c50c388,
+ 0xe3c0d530, 0x8acda9af, 0xa94be30d, 0xeddfff62, 0x7ef842eb, 0xa37313c0,
+ 0xba4bdd71, 0xf8e04db4, 0xb3f0fb6c, 0xf437ec6c, 0xfb86c184, 0x70fb5f0a,
+ 0xbc49bbe9, 0x4638fb4c, 0x8a1a589d, 0x89db497e, 0xcf88a125, 0xf489e0d7,
+ 0x21b8f578, 0x81713c68, 0x05fc9e3f, 0xe58cc1ca, 0x006c9e22, 0x8fe617bd,
+ 0xadfb68cb, 0x0ead7215, 0x97c8aff3, 0x80bef87b, 0xd192c4ba, 0x27ba7e54,
+ 0x3862879d, 0x6ed7984f, 0xfb8c63e0, 0x62c983f4, 0x21b7f9de, 0x3cf316ac,
+ 0x7f25b175, 0xb4f375a0, 0x06eb8ece, 0xc8be53fa, 0x7a4ecbbd, 0x79865110,
+ 0x7ba0019a, 0x8a17942c, 0x6dcdb8a1, 0xe0897e82, 0x085e6297, 0x798c99a0,
+ 0x258c47e5, 0xf98adf0f, 0x6383169f, 0x23b93125, 0xa3cc027a, 0x0ccfc89f,
+ 0xfc066108, 0x244f36ae, 0x5f32e1f3, 0x32dff324, 0x7f60a45f, 0x29db8f3c,
+ 0x9559345f, 0xbb323737, 0xccb0f51b, 0x561ead0b, 0x24bfb8cd, 0xa9cc42f2,
+ 0x27fd1e60, 0xed3bec49, 0x7c9afc4b, 0x41713dcd, 0xe35335f2, 0xee1e77f8,
+ 0xc79192fb, 0x3cb5fe41, 0xc43c7ae1, 0x58f35372, 0x6b07ee76, 0x791c1ee0,
+ 0xaafc8e25, 0xee8bfeaf, 0x7cd75835, 0xa5e0f495, 0x51f33376, 0xc795b13c,
+ 0x148d9bcd, 0xfe04b83f, 0x7e806c59, 0x8f8e297d, 0x8739afbb, 0x2fa343d6,
+ 0x7fdb1437, 0xb2e9c714, 0x93c9bdee, 0xfb77ded0, 0x04de8e0c, 0x1ab7f709,
+ 0x6821867d, 0xba44dcaf, 0x320f8ecc, 0xd7084b3f, 0x1575da4f, 0x4c63d623,
+ 0xce73c702, 0x72dfdc87, 0x10f9e52d, 0x5c27dc9b, 0x87e0f3cd, 0x1130c192,
+ 0x60f8f0f1, 0x7c3d92f9, 0x02f17b1f, 0x7735ce85, 0xd1992f95, 0xe53bea74,
+ 0x1c69be4b, 0xc84136ba, 0x0e3cfebf, 0xbe78f7fd, 0x7aaa26ff, 0x94b23650,
+ 0xc44def9c, 0x1062567b, 0xf1c4dfbc, 0x7eff7527, 0xfd88cfc7, 0x73bbf37e,
+ 0xf85fbf62, 0xe3cf7f17, 0xf19ef86f, 0x867bfe73, 0xc33df7df, 0x3e9835bf,
+ 0xbf9adff8, 0xe7e7e7f7, 0x43ddf1b9, 0x5eeda3ca, 0x0fa79016, 0xd150a57f,
+ 0x1befce75, 0x505ab722, 0xbd7cca6f, 0xbd8fd3cc, 0xd6b3e783, 0x5b3c5ae5,
+ 0x5ede7f14, 0x89372be2, 0x8cb66bfb, 0xfadc6ecb, 0xe5f4e29a, 0xebfc6346,
+ 0xeefe460e, 0x6bcf2b25, 0x112d8331, 0x32d05cf3, 0x29d82271, 0x79e0d675,
+ 0xdceef6d1, 0x6f4ae90f, 0x07b293b8, 0xa9d2c626, 0x7b306700, 0x571121ed,
+ 0x8a3135b4, 0x3d833237, 0xd77d2271, 0x51f6889e, 0x3efe01c4, 0x5b9ccbdc,
+ 0xda7b2e08, 0x6817da44, 0x9ef8434f, 0xa8daf910, 0x30d27dd1, 0x76051cbe,
+ 0x36f5e621, 0xfc8f7e60, 0x93b51b56, 0xc897dbdf, 0x9184f7bf, 0x757f9829,
+ 0x29f7cadf, 0x9ef465bd, 0xdcf0552d, 0x99e3378e, 0x8dcbca34, 0xfacd3946,
+ 0xe3e553ce, 0xce862fe8, 0xf0be52e3, 0xf5cf1dc8, 0x2237fda5, 0x41cf272f,
+ 0x18ff47ec, 0x6f6fb8e0, 0x8ceff116, 0x39d0777d, 0x81ba5708, 0x8fc9dcf0,
+ 0xe3817114, 0xe321ae22, 0xf53f3202, 0x290f1167, 0xedfbe44f, 0x05bc624f,
+ 0xff18adca, 0x6fa3f008, 0x4f2d3ae2, 0x9f4eb20c, 0xc83c7850, 0x078f36fd,
+ 0xbd1c9965, 0xbee803aa, 0xd4b7e04c, 0x3211f3cb, 0x9882f3be, 0x47a700d7,
+ 0xd64ea687, 0xf226feda, 0xd2eee663, 0x1eb2fe21, 0x03cd7bd0, 0x08727df0,
+ 0x063a47be, 0x8915a7e3, 0x77590edc, 0x74f29db8, 0xfaf935bb, 0xc226897d,
+ 0x9c49edcf, 0xdce1f72f, 0x6f5f79e0, 0x1b346ac3, 0xf4db8623, 0xc544f2c1,
+ 0x9c230fe0, 0x6e1c75a5, 0xaf62f789, 0x73bf073d, 0x5afb60ea, 0xa796667c,
+ 0xbd3c50e5, 0x3a5af2e2, 0xd5e5f507, 0x7c537743, 0xbf4764cc, 0x3aab6662,
+ 0x893536ce, 0xa377d5c7, 0xbb788d81, 0x717e40c7, 0xe2063dd6, 0x2b62a8a3,
+ 0x4651adf9, 0xe586efa6, 0xca1edc09, 0xc1c98bcc, 0x491c9b32, 0x61e66076,
+ 0x0cbce47b, 0xea2bdc7f, 0x88b1a59e, 0x97c9afb7, 0xf203127a, 0xf68e32a5,
+ 0x95a5f36d, 0xfb47bd6f, 0x24bce542, 0xb3de645e, 0xdca97cab, 0xfbcae0af,
+ 0xc2bfb54c, 0x851f6865, 0xbdacc6f1, 0x5cf24ca7, 0x3f9a425a, 0xe7b59a9f,
+ 0x6551e532, 0x7d55d4de, 0xe869ec99, 0x59fec267, 0x9044fe40, 0x782b8d97,
+ 0x7115f53e, 0xe609a81e, 0x7eb804ef, 0x67c7f307, 0xdf1bcc33, 0x2fa2bebf,
+ 0x1c2bbd3d, 0x62b7dcf4, 0xcd5d3d18, 0x2aff2997, 0x4fbf72f3, 0xf1dfb4ec,
+ 0x0abf880f, 0xca8f1e7f, 0x3e9e3cda, 0xf069c784, 0x379e30dc, 0x2165bd72,
+ 0x5cdd9db9, 0xc17e8a9a, 0xa4968fdf, 0x9855dc22, 0x8be00b47, 0x1ac3a736,
+ 0x8170fe89, 0xb3f98ac3, 0x740b96ac, 0xe0caa18e, 0x3a07fba3, 0xbc698bee,
+ 0x36e7f7cc, 0xbf115b67, 0xd5df3d37, 0xdf33bff4, 0xef893b35, 0x23f29663,
+ 0xdce740b3, 0x4ec3cf82, 0xf900bceb, 0xe780aeb0, 0xf7a5d64b, 0xb1b7f5a4,
+ 0xdce467a0, 0xf36af180, 0xea22fc78, 0xe06b749e, 0x8c9397fb, 0x58508fdc,
+ 0x96393041, 0xb3775dd2, 0x60948afd, 0xdbdb7f76, 0x81038fc0, 0xa594f60f,
+ 0x54bcfb8a, 0x7975b7f1, 0x50c35373, 0xb3371d2e, 0xa73e3cde, 0x4d31bf8a,
+ 0xe1c64d9e, 0xd414fc60, 0x74f233cf, 0x90786b4e, 0x3da19cfc, 0xb8906265,
+ 0x715aac19, 0x893b921f, 0x9a68fde1, 0xcc47db7c, 0xb43a7ef3, 0x23a79e9b,
+ 0x6799907d, 0x2f802b60, 0x1e8c6b33, 0x3cc9bbcc, 0x332dad5c, 0xe4f8f909,
+ 0x345b265b, 0xc29c37b5, 0x746fd2f6, 0xebad6de4, 0x151cfd09, 0xd37b9d0a,
+ 0x9b8acbc6, 0x2862465a, 0x5f5b1064, 0x06ed0b97, 0xa06ceba5, 0x9f986eb2,
+ 0x8c7614cb, 0x7c86ae36, 0x36877684, 0xaf8da6be, 0x9f74124f, 0x7fa6ec24,
+ 0x1ca5fe17, 0xe5a38e57, 0xb9dded97, 0x5e2aed5e, 0xd7d449bf, 0x4bae65e6,
+ 0xd58e7a47, 0xb51bd431, 0xe92c2379, 0xefcde301, 0x3dfbf7ce, 0x98bef981,
+ 0xcf1f7cc0, 0x7cf369eb, 0xb5659e52, 0x84e7417c, 0x465c8237, 0xe04ae57d,
+ 0xd7ac8179, 0x9ca30fb3, 0xf5c9c3f0, 0x979846f3, 0x4739ec8f, 0xa2f3e324,
+ 0xbdee8d73, 0x32e3c50a, 0x2fb67ec7, 0x20acca14, 0xbbd9ce92, 0xdd5f4ade,
+ 0x58cfe50d, 0x4ec510c3, 0xfc8ea279, 0x2689e611, 0x1a3e53bd, 0x4d67fdf7,
+ 0xe9147419, 0x48c8a535, 0xbd26f7fb, 0xbf8a3853, 0x042ab2df, 0xe855f7df,
+ 0xefa9073e, 0x62f0ecc6, 0x23e59c84, 0x7d2f2054, 0xe0359d6f, 0x309ac8fa,
+ 0x9340f281, 0x6973f327, 0xe2d72fa0, 0x4ef499fa, 0xfc4608de, 0x80bbdd5d,
+ 0xfd2abfdb, 0xeff93fb8, 0xf791ef14, 0xbee3440e, 0x5ebf0c85, 0xfa0bdaca,
+ 0xafafcc2a, 0xda9eabbe, 0x784eddde, 0x206afa94, 0x83d42be8, 0x9e781351,
+ 0xf9ff4b5d, 0xd2ba9f82, 0x5dc95d3f, 0x9ee233d4, 0xa12524c2, 0x63b6beb3,
+ 0xb476e75c, 0x2fba15cf, 0x3bfe2bad, 0x3af9c89e, 0xedbb0bb2, 0xcbaf80b8,
+ 0x3f4d4efd, 0xbde8fe4c, 0xf3c3ffee, 0x92cfc247, 0x97e92479, 0xaef6120d,
+ 0xe78a667c, 0xa0ee7ebf, 0x2e9ffc88, 0x92a01dcf, 0x0ee746fd, 0xc1dce8a2,
+ 0xdecb1341, 0x3c89f685, 0x2029e487, 0x2fe0e8bb, 0x7cfb5a3e, 0x8113dd0c,
+ 0x0f41a0c7, 0x5efd251e, 0xd910f609, 0xf09fcd4f, 0xdf036ab8, 0xa4d95db7,
+ 0x81d4ef3e, 0x73d7a14f, 0x8f947e61, 0x4762fb11, 0xfc27fb89, 0x0dfbc9f1,
+ 0x9749f181, 0xf72b17dd, 0x9eb87adb, 0xb52bc552, 0xd62ac9f1, 0xab6afb4e,
+ 0xea0715ca, 0x5e2a1f8d, 0xbd493dd9, 0x225fbbaf, 0xb0a67fbf, 0x9ed05144,
+ 0x2a0ae8b5, 0xebfcff68, 0x16b73cfc, 0x2e248e3f, 0xf7159f9f, 0xa77b3e89,
+ 0xc661e742, 0xb3c7fc88, 0x3173f3af, 0x73ca66cf, 0x21cf3c31, 0xdcf21bf3,
+ 0xfcfeadcb, 0xdf9e46c6, 0x75c04868, 0x4cc9cf27, 0x45e214d8, 0x074c613b,
+ 0xf755b81f, 0xb3c49c1e, 0x34e79871, 0xb5887bf3, 0xca48f670, 0xf8f2893e,
+ 0x93b7cde4, 0xd8829272, 0x72260f49, 0x7f7da478, 0x3f7a924f, 0x6303f81f,
+ 0x00fed493, 0xc0feb595, 0x7c67cacd, 0xb9b9f888, 0x983c7ef3, 0xc7137f3f,
+ 0x7eff75d7, 0xd82affc7, 0xbc45abf8, 0x5e3fcb4a, 0x8182e711, 0x0342e76c,
+ 0xb73dacf1, 0x9d79f5c8, 0xee80ff62, 0xdf937b6b, 0x6ae5214b, 0xff1f185d,
+ 0xe54f2171, 0x7e3105f3, 0x5c78319d, 0x6ed165ec, 0x18f9de99, 0xedbf5bf2,
+ 0xff6538ea, 0x729c7506, 0xaa945360, 0x5ddbc83c, 0x70eb3ed5, 0x10fd554f,
+ 0xfaaa6ddf, 0xaa678fdb, 0xdeb477ca, 0xd77f6aa9, 0xcaa8475f, 0xc7576a3f,
+ 0xa6beef29, 0x0366538e, 0xcfb606c7, 0x9cd1ccb1, 0xfcd374b7, 0xf3d5ca93,
+ 0xcf56ae4a, 0x3d46b52b, 0x7ab734af, 0x7aeabd5e, 0x251fbd06, 0x196cf30a,
+ 0x16cf3ddf, 0xe6a7ed2e, 0xf7ec565e, 0x15ba5e44, 0x2e7935ed, 0x3d87ef1a,
+ 0xf7f03200, 0xfb4d7e3b, 0x70be2e70, 0x45e2fc8a, 0xde19e9af, 0x23b6d05b,
+ 0x3be9798c, 0x62c7ba1e, 0xbe9ea361, 0xa1de0cc3, 0x6dee0293, 0xf9e40e03,
+ 0x48c317d2, 0xc97c2e44, 0xfd0b19ec, 0x6672be17, 0x69439e00, 0x5cf3c55b,
+ 0x39f817ee, 0x1d6ee676, 0x4bef0930, 0xc159b037, 0x28fb33ee, 0xde2fec49,
+ 0xfafb4a13, 0xe42ded94, 0x986c2fcf, 0x9b3cc466, 0xc934776c, 0xf3f1db28,
+ 0x1e2bcf51, 0xbe00dff2, 0xdca778c0, 0xf3e9ff6f, 0x6c2dff5c, 0x3fbdd232,
+ 0x6aefb70b, 0x17ae7bc3, 0x7dd3371e, 0x97edae67, 0xbce6af49, 0xecf093b8,
+ 0x03b3d26a, 0xb9a5fd6a, 0xebc79d8f, 0x492b1aaa, 0xfc9941ef, 0x7e06aaaf,
+ 0xbdb7ef8f, 0x8bd17707, 0x03715f7b, 0x7eed170a, 0x20e31c2e, 0x0b6df37f,
+ 0xfb7e3f27, 0xddefdfd7, 0x0dc27de5, 0xbfa03efc, 0xcec4abe1, 0x343df4fd,
+ 0xe76f31f7, 0x7c0064f7, 0x0bef0343, 0xf391e3f0, 0x9f9da2e5, 0xbbef12ff,
+ 0x4fa5f4ff, 0x56f0897e, 0x2feaf3fc, 0xd6fa4a7f, 0xe1b9436a, 0xba7de17a,
+ 0x4bf65c2f, 0x40e5c1ee, 0x3dcff3db, 0xc38c0bfb, 0x6defc87c, 0x3e7bdb6f,
+ 0x6dbbf905, 0x187117d7, 0x77ba5af7, 0x9789c524, 0xcf139cbe, 0x475ec6be,
+ 0x837cf5be, 0x37f7dd7b, 0xb8414fee, 0xcd7d022e, 0x1767e8c1, 0x25435ff6,
+ 0x2edb6fbf, 0xc1de85ee, 0xe1be85ef, 0x938dfa3d, 0xed08ffc6, 0xaf7e469f,
+ 0x83ef0dcc, 0x38e80f7e, 0x6fd05bf0, 0xf97fbf07, 0x720abe22, 0x3d5df41f,
+ 0x7fe9f7d4, 0x57ef38de, 0xc6cac0bf, 0x83ef2ee8, 0xbc037ef6, 0x2dfbfbc9,
+ 0x7aa39c3d, 0xe97f7ea0, 0x36ff7437, 0x1dac6dd2, 0x3cf8fbef, 0xbfbbfd05,
+ 0x3ee9db1a, 0x66bdf6ba, 0x67d033db, 0x680fdee1, 0xccbdb4fd, 0xdc4c98e3,
+ 0x31d6df97, 0xb9cf712f, 0xb6b8b188, 0xa47bf186, 0x7ef1fe05, 0xbd387b69,
+ 0x7349f717, 0x4cf795fe, 0xe5a5fbcb, 0x6e5405ef, 0x45c798fd, 0x59f97835,
+ 0xf8dfe90f, 0xa30ca5e9, 0x7b5ffdf3, 0x87c4b76f, 0x1d7bf84d, 0xfc1adb74,
+ 0x7b8eef1e, 0xe49d05f5, 0xf71de8fd, 0x387943a1, 0x580f9595, 0xb6d07910,
+ 0xdeb3df85, 0x94fe85d6, 0xb46a88e7, 0xbfcc54eb, 0xe921f5ab, 0xbff82378,
+ 0xf4167e2d, 0x0feeabb0, 0xcfca7897, 0x8f7ee261, 0xc39ce3d1, 0x5c7ddec1,
+ 0x438cc796, 0xac3a987e, 0x2731fea3, 0x611e23c6, 0x60117ee2, 0xa75e0b7c,
+ 0xf64fcbc7, 0x16a47d18, 0xdb6888e3, 0x0dc277c0, 0xc8e10cad, 0x32313bc7,
+ 0x1dcaf3fd, 0x24547d7e, 0xf82e5df0, 0xdef6f849, 0x3f4897e1, 0x9ee1c075,
+ 0x83d9ce36, 0xf945cfc7, 0xdef77e08, 0x63f28ec6, 0x17de034e, 0x9faaa111,
+ 0xeaa99c36, 0xf8097d27, 0x619453bc, 0xf274fadd, 0xc7c2931e, 0x533e9e70,
+ 0x5ef87b40, 0xce4f7e2e, 0x7f1feecb, 0x71b4fd57, 0xbcff0675, 0xf280daa0,
+ 0x7050c235, 0xabac2ae0, 0x46c51888, 0xdd243ffb, 0x628fac0a, 0x9f3fd2be,
+ 0x9f1f34d9, 0x83436fbc, 0xedcfac37, 0xd51ae426, 0xf10c79cf, 0x68eba05e,
+ 0x23f6c6ef, 0x7fa03e25, 0x291d035f, 0xea87fea5, 0xf7863f67, 0x53f9c86d,
+ 0x5e103d39, 0x96cb970e, 0xc029207d, 0xaba0ed3f, 0xe5f09abb, 0x4650111b,
+ 0xca6a7b78, 0x07f00121, 0x1d5dcbe2, 0x80086d9e, 0xfc03db17, 0xf5149bd3,
+ 0xfebc51f8, 0x63f57d74, 0x32fee1ee, 0x3f098b63, 0xfc25f301, 0x77a0ef4c,
+ 0xd0b9b8f5, 0xcfc0a47f, 0xc78b1ea9, 0xc46f7ce1, 0x369bb367, 0x45bdf9d0,
+ 0x363a15db, 0x83c7a7e7, 0x6c8be7c4, 0x1e0fff12, 0xf4fd7841, 0x0d89e5e0,
+ 0x120ffbf2, 0x94684fdf, 0x3f65e5f3, 0x4078c17f, 0xea75698c, 0xd56b7bfa,
+ 0x8eb3a7fd, 0x3e61c7f1, 0xff077a64, 0x7e60f7c2, 0xff3e050b, 0x11e0ff59,
+ 0x95bf0077, 0x39248dce, 0x5fe5e729, 0xdc696b8f, 0x81a1b80e, 0xfcc6ed02,
+ 0x31c78d51, 0x8fda3bab, 0x1a79a3cb, 0xbc961ca8, 0x51e208f6, 0x3f2587d6,
+ 0xf2af1414, 0xff89ffbb, 0x9275b904, 0xdffad531, 0x5b9757af, 0x1bcf12f4,
+ 0x20cd2c8f, 0xe3cb28ed, 0xe632de30, 0xe5f0d43f, 0x89f96599, 0x023db971,
+ 0x037b8fe4, 0xfc3f1fc9, 0xafa8fdbc, 0xf7c28a40, 0x186f257a, 0x8bea15b7,
+ 0x637b7846, 0x8a28b6fe, 0x5097d93f, 0x454be78f, 0x5ed46e7c, 0x45307bfe,
+ 0x4bdede21, 0x69f3fc32, 0xdfdf29f9, 0xcfcd5eef, 0x6de294db, 0x0e6af088,
+ 0x2f412b46, 0xd44444b4, 0xf7ed0b3c, 0x835f54ff, 0x9ac9ec76, 0x78a7ba68,
+ 0xcfcf3261, 0x8d488fee, 0x254273c3, 0xfa248f0f, 0x4f15adcc, 0xf9e98ff7,
+ 0xbd7f3fc6, 0xaff81c3a, 0xe742b37d, 0x19f47ecd, 0x78c1dcc8, 0x1e2dd4cf,
+ 0xf4ef6fbc, 0x182951a7, 0xf4fb287c, 0xf10323ec, 0xb89e9d7d, 0x6acbecb7,
+ 0xdce6d7ba, 0xe323b4e6, 0x75b9fde0, 0xa5af5a7a, 0xa82161e1, 0x657dce6f,
+ 0xf076823f, 0x6d8acdb9, 0x6e738c15, 0x37ba02cd, 0xe9229cec, 0xade12cf0,
+ 0xe059936c, 0x52f0d9ed, 0x5d5293e0, 0x18bc9d07, 0xc91f9b9f, 0x6f3763cb,
+ 0xbf0db71b, 0x742df4f7, 0xb253796f, 0xf0193f33, 0x39c530b3, 0xfc6f9f0e,
+ 0x071ff773, 0xe69e3ce0, 0xbf5ee6e7, 0x766e3b36, 0x7f9bbe80, 0x7febef91,
+ 0x8a5f64c3, 0x9211bd70, 0x46c9b8ac, 0xa1fda068, 0x005e4573, 0x7766a4f8,
+ 0x48617f10, 0xfb2fcf32, 0x5a25e4f9, 0xbcd1f97f, 0x8bf36f3c, 0x9ace2f24,
+ 0x7499d86b, 0xae393f7f, 0x9ea8bc76, 0x96c43e3c, 0x84f87b73, 0xd21844fb,
+ 0xe3fb84e3, 0x54bb40b0, 0x785941f2, 0x9f7e9b98, 0xf48c2c26, 0x8ac349f9,
+ 0x3cc00f73, 0x92366fe6, 0x39bf98dc, 0xc63b7976, 0xf918d7f9, 0x5fc1467e,
+ 0xc49f6265, 0x02c6cda8, 0x9217c3e4, 0xf9233fb9, 0xe29cf80c, 0x5897c842,
+ 0x66121b2e, 0xc0c67dc0, 0x9cf0b3ef, 0x07cd88f5, 0xaa9c637b, 0x1335b16c,
+ 0xcdb2a2fd, 0x6b63c266, 0x06db9858, 0xc3c24aed, 0x5cf0910c, 0xf3e7cc95,
+ 0x3d3b64eb, 0x80ccf473, 0x59e175fb, 0x7a19036b, 0x0d10f005, 0xff350be5,
+ 0x73a814fe, 0x533c17f0, 0xb8be076f, 0x79850882, 0x53d4695c, 0x9c198c7c,
+ 0xff38fc86, 0x6f95e3bd, 0xc36536ee, 0xcbabcb3f, 0x9ab43df8, 0x842acefb,
+ 0x6fb5a47d, 0xb9a0f7b5, 0xef41a3d8, 0x1fdad365, 0x7b0b274f, 0x768fdc57,
+ 0x87d8daa5, 0x185bbff8, 0x4e4ecefd, 0xcaeff73d, 0x33bc786a, 0x23399a27,
+ 0x3736bee9, 0x338d57dd, 0x6cbabb40, 0xfa1362e3, 0xb77f3027, 0x5c7fea0d,
+ 0xc3ee98bf, 0x253cc52a, 0x2f9b6fae, 0x9429f70c, 0xc48e8b2e, 0x88992dfd,
+ 0xd9c38c37, 0x7df10198, 0x882a4592, 0x4756338f, 0xa40ce2ca, 0x5ef095af,
+ 0xc705cbf6, 0xd6fa869e, 0x8131f995, 0x277702e7, 0x19de251b, 0x1c88eefe,
+ 0x9fcafcef, 0xf393ff91, 0xd1725bab, 0x648b2dae, 0x869e9dbf, 0xa14c4c74,
+ 0x5da2167d, 0xf69faad9, 0x94acede1, 0xc75d2bf7, 0x2f603bef, 0xdbbfb99b,
+ 0xf102d997, 0x4df6b73b, 0xff832993, 0x4f7016db, 0xa8f2cba5, 0xd3e9ed0f,
+ 0xf187af50, 0xee5f6167, 0x96f2aa17, 0x506f22a5, 0x4d6653a4, 0x4dda71a4,
+ 0x264f0eb8, 0xfbcf78f3, 0x2b9fdcc9, 0x5f90714d, 0xd998f95e, 0xf78d2ab1,
+ 0xf973cbd7, 0xe377f13d, 0x2ffff37c, 0x998af9c2, 0xad577efc, 0x15a4f295,
+ 0xde7810c0, 0x066065d7, 0xcb8e1453, 0xdc42b2f9, 0x8fef0d7f, 0x9564bde3,
+ 0x555e5c61, 0x31fcf246, 0xa86e9232, 0x17b397b8, 0x80712f1f, 0xf7c77fbf,
+ 0xadfd7f15, 0xd15f1003, 0xdb285f74, 0x89fb17a9, 0x430d8fed, 0x9f53bebd,
+ 0x4b89fb85, 0x851fedd7, 0xda2e4cf7, 0xc9cb8835, 0x871bbedf, 0xe0917ceb,
+ 0x1f915687, 0xdc650d9f, 0x3259f54f, 0x7d242ff7, 0x98f8133f, 0x87df92bd,
+ 0xba70d6c8, 0x3f7bae54, 0x5f2010ce, 0x107e572a, 0x1f900c67, 0x5be825ff,
+ 0x438be619, 0xb2f95d79, 0x4fca0071, 0x0536397f, 0xda93f2f9, 0x1f91c357,
+ 0xdede613e, 0x54738c36, 0xd7181d5b, 0xdfb1d8ae, 0x209bb3d4, 0x57e150fa,
+ 0x53c3de01, 0x77173c38, 0xf6829bbe, 0xdc0be55a, 0xf14caae1, 0x4b78c1f5,
+ 0x9d3d0ed5, 0x7c6aad0b, 0xdf20fff5, 0xe924e969, 0x81f48553, 0xd050b1f5,
+ 0x92e90aa5, 0xe3cf7c89, 0x35ae5036, 0x4c8a9d02, 0x22380650, 0xe01d3852,
+ 0x2f7f2e7d, 0x67f4a9f4, 0x15d67c35, 0x70a6fb7e, 0xa4f80579, 0x14df5f3c,
+ 0x2bad77ce, 0x32fd255f, 0xe1cbdd7b, 0xe675ba73, 0xef1d8ab7, 0x6bdfc49e,
+ 0x32b468ab, 0xedf34ec5, 0xe42aff98, 0xfa379c3f, 0xf0ef3861, 0xf92de7ae,
+ 0x4e14d6f2, 0xbe1a859f, 0x0aeb88ec, 0xd4a24bf8, 0x2909b679, 0x89863f9c,
+ 0x8435b327, 0x5e91fce3, 0x602f9276, 0x0438c820, 0x6bb8b934, 0x922ff90b,
+ 0x737bf21e, 0x6e413e04, 0x2f27f138, 0xc55bfe24, 0xbd5aec7d, 0xfdd05a35,
+ 0x94f89ad4, 0x27c3c026, 0x454d29db, 0x010d0f1b, 0x71d8abdf, 0xf309ac26,
+ 0x2edc354f, 0x84cdf9c8, 0xc90f88d1, 0x29771717, 0xc85fac06, 0xe1257fb8,
+ 0xf968f092, 0xcfdc44a1, 0x78bab39d, 0xe71820f4, 0x5862fba4, 0x03c40caf,
+ 0x0a4e6787, 0xc4ee4fdf, 0xe5c01160, 0x21e7e26c, 0x7ddf894f, 0xd5e6b53c,
+ 0x5be7bc70, 0x8a6973f2, 0x7df293cc, 0x24f09d18, 0x4380ece0, 0x91e127c0,
+ 0xd0f398fc, 0x7081d1b4, 0xe252f96b, 0x5b27f255, 0x2ce32b1e, 0xf5753e2a,
+ 0x53bf4538, 0xf52f7da0, 0xcbf419ff, 0x47b20e30, 0x841c60f1, 0xe903b2d5,
+ 0xca527a01, 0x16ebf859, 0xdfc96f78, 0x1b298358, 0x94f2f1d6, 0xfdfe5c9e,
+ 0xdc2a37d5, 0x6fa7d7ee, 0xf34f53fc, 0x5e67d1f8, 0x0be5047d, 0x525bbfd5,
+ 0xf155e62b, 0x6fda01e9, 0xe47cc956, 0xe2f7b3b7, 0x3ffaf954, 0xae5a7b8b,
+ 0x91111c1a, 0xf91dec41, 0xa30574fc, 0xbae97c7c, 0xc76ff377, 0x91bcf175,
+ 0xae9425f6, 0xb4f74919, 0x6736d82e, 0xe9d3f228, 0x5093ddba, 0x74f85e9e,
+ 0x39e109b0, 0xd1f5c75d, 0x9e433582, 0xee937bc5, 0xea33975a, 0xb5df284e,
+ 0x0ff11061, 0xb2eb878e, 0xad165974, 0xf55b93cb, 0x1e9277b9, 0xca123f05,
+ 0x590dcf2d, 0x06e3bf8e, 0xa59532f6, 0xf312765d, 0x9f7819ec, 0x3b37971e,
+ 0x2ad85c84, 0xc156d5d6, 0x57ab3927, 0xfe21d1f7, 0xb81d58b7, 0xba05d56f,
+ 0xaae8013e, 0x2573fd0b, 0x165af3ed, 0x1753f74a, 0x91fdf99b, 0x65846fc5,
+ 0xfcef86ae, 0x5076e155, 0x125989b9, 0x059fa933, 0xc5382ff7, 0x547ec1f7,
+ 0xf7e5a7c5, 0xa4790877, 0x5ff4c7ed, 0x3e3e450e, 0x50bde023, 0xd454fcfb,
+ 0xf7b6172b, 0x383e428e, 0xfb4ad7bf, 0xe26bce90, 0xa937603d, 0x7d80cbf6,
+ 0x5d832aa4, 0x17635674, 0xf0e7f669, 0x14ded138, 0xf9247db5, 0xef7168b9,
+ 0x3dfb6088, 0xa129e23b, 0xa1f6ed5f, 0x6cdebabd, 0x67077dc3, 0xfddcbe45,
+ 0x1fdf9eb2, 0x7dfce16b, 0x0f2ce5f6, 0xfff343da, 0x1bf3cbcc, 0xc0f91e78,
+ 0xd8f48786, 0xcf3d5e7e, 0x93d87723, 0x454c371b, 0x28e2bfb6, 0xfef78b59,
+ 0xee2ed95e, 0x6ece6305, 0x50f23b1a, 0x3b6bbda2, 0x4a3f6b52, 0xda9bf2bb,
+ 0xd4efd291, 0x526793da, 0xc1cd5c44, 0x892f881c, 0xbff76927, 0xbc0ee401,
+ 0x456da7df, 0x9f91d939, 0xe7a128ae, 0x63d4e525, 0xbf6b2f98, 0x8f7da3a8,
+ 0x77fb5ffb, 0xab1d1e3d, 0x47a2dc6c, 0xa2b6d53d, 0x7c67f686, 0x9e9aa2ba,
+ 0x6a3f4e92, 0x6d76a16c, 0x77cd594d, 0xef5ede01, 0xb4e5c116, 0xf31147a0,
+ 0x46bec519, 0x91913ed5, 0xf7c1b468, 0xf7e01e8a, 0xbe62cf23, 0xb234b4b0,
+ 0xa5da1983, 0xe942cb45, 0xd94bf8fe, 0xd81d6e61, 0xf2b67f4d, 0x5e72ef7d,
+ 0x6bee3bab, 0x8c71e47d, 0xd6cdac97, 0xc7cff28b, 0xf67e553b, 0xf8c1dfcf,
+ 0x4f8c64c2, 0xf8f7ff90, 0x5d7f8c78, 0xa1eb283a, 0xd697f50c, 0x6e0fe130,
+ 0x9e97fea0, 0xf04ff594, 0x7eb275fa, 0xb9ffaf23, 0x0de597a8, 0x9a95fa9a,
+ 0x3979a7fa, 0x78e3753e, 0x3f482b8c, 0x9daa5fbd, 0x84ab49fb, 0x47dbaedf,
+ 0x05a925cf, 0xbdf152fd, 0x0273e1c9, 0xa27e8b5e, 0xffeba077, 0x2fd9dd82,
+ 0x47faf015, 0xcf8ed3bb, 0x0276c87f, 0x17bef02f, 0xf3b37fbe, 0xfef83efb,
+ 0xf7a77b6e, 0x1afbe2b7, 0x11a2fbcd, 0x83ee1b4e, 0xee2bdf6d, 0x51330987,
+ 0x5f9e4d90, 0x261fdd74, 0x64f56e82, 0x233fc9af, 0x7f10e7e3, 0xf4469a9c,
+ 0xfbe2613f, 0xf7844ec4, 0x9199dfa4, 0xc4ff1de7, 0x5db1fdec, 0x3ebe4f51,
+ 0x3c234bdb, 0xe3c6ef28, 0xf8519dbd, 0x853ed034, 0xd6e60689, 0x375d67f1,
+ 0xbefc6fd2, 0x7be271ce, 0x88dd8b3a, 0x9e416476, 0x71728992, 0x8de630ca,
+ 0x7dedbd00, 0xef982993, 0x4e78f797, 0xb7bceaf3, 0x8f1a7ac0, 0x400f08f7,
+ 0x7abd737c, 0x9febe4c2, 0xa6bf2019, 0x5c3972a6, 0x8451f184, 0x07ae01eb,
+ 0x8a7ee067, 0xb26fbe4c, 0xe87ce028, 0x418e02bd, 0x8d13fdfe, 0xcdc961d7,
+ 0x1803b034, 0xbc59d0c1, 0x3345fbf4, 0x092f77c4, 0x80cf10fb, 0x8c4befe0,
+ 0x54cacf17, 0x3a5d872e, 0xefd88f2e, 0xaababef8, 0xfda47fa5, 0x8f78553d,
+ 0x227fde33, 0xf5f76bda, 0xf2e54a2c, 0x9b77b5dc, 0x505f9f89, 0x185857ef,
+ 0x1be11fb8, 0xdff057ec, 0xfb425cc7, 0xfb53147c, 0xf2b29c5c, 0x9e07566f,
+ 0x6a619efb, 0xbab0f610, 0x6f914cdd, 0x2e764889, 0x7a927e45, 0x7faf2b4f,
+ 0x2fbbe622, 0xb600f9c5, 0x09952fbb, 0x04edc7fd, 0x5367fb6d, 0xc09e2275,
+ 0xb59fd682, 0xe385588f, 0xbdb518b0, 0x25641870, 0x93b72fcf, 0x79b5741f,
+ 0xa3f3ed08, 0x7f14303d, 0xc638fc3c, 0xdc65f33f, 0x72a3edcd, 0xb7397197,
+ 0xe5c63c6f, 0xa7a57f0e, 0xfea44ffe, 0xcf5c71e1, 0x6e734a3f, 0xa7d7efc1,
+ 0xba13d015, 0xac3b400d, 0x1efab860, 0xa1b989fe, 0xb1e4f2aa, 0xf97baad1,
+ 0x524e4ea7, 0x7a8b0b95, 0x9be7daa9, 0xef11837d, 0xa7edcef7, 0xe6bfcfbe,
+ 0x5c51e59b, 0x70be3c61, 0x63f3f9a2, 0x2ecf8033, 0x143bd56d, 0xf60bdf58,
+ 0x57863b6e, 0x077d4b97, 0xef023a42, 0x61dbfacf, 0xc73bed3d, 0x50fe7f38,
+ 0xc8bb9ebf, 0x570d4f7c, 0x916e7afc, 0x95d900ed, 0x5a77d237, 0x59d4073d,
+ 0x2f2ff746, 0x77e0730d, 0xa4fc69be, 0x1f6d5525, 0xc8176574, 0x1b9aeba7,
+ 0x3d8c2b7f, 0xc76de428, 0x86c5e6fb, 0x46f67bc0, 0x11dc504d, 0x1b5fa7e8,
+ 0xe3ac18cd, 0xea4e7545, 0x474d7557, 0xeb034ae5, 0x987e88df, 0x7ff48c3d,
+ 0x2af1527e, 0x3554638c, 0xf96bfdf2, 0x7e98fe2f, 0xbd62b657, 0xebe7da93,
+ 0xe31834ff, 0xe5af232a, 0x7af938d1, 0xde015876, 0xf5c3931b, 0x89b5c45a,
+ 0x8d75def4, 0x1ec6fb51, 0x7f902725, 0xcf4f77b2, 0xc4969fc5, 0xf7ae3e38,
+ 0x9e70f7df, 0x3ed57ce4, 0x77b5fd1c, 0xd706acf4, 0xdf773bd5, 0xe5a1fa4d,
+ 0x815959a7, 0x5495f4f6, 0xdad7f093, 0xb77da4bf, 0x11da87af, 0xe44714bf,
+ 0xb7924e79, 0xbdd19ef0, 0x9f9baf09, 0x15c63f41, 0x215debce, 0x838c1e11,
+ 0x3561bcb4, 0x36717ae0, 0x7eb80d9b, 0x7ab0de72, 0x664e7e71, 0x39c2fda0,
+ 0x8b92dc6f, 0xd2c9c9f2, 0xa0656787, 0x455e72de, 0x2c76c27d, 0x94cfba27,
+ 0x0df323bf, 0xbefb53f9, 0xb1e38ea4, 0xd243d054, 0xc7a0b667, 0xdfc1037f,
+ 0x800003c7, 0x0000
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2[] = {
+ 0x00088b1f, 0x00000000, 0x58ed0300, 0xe7146c7b, 0xbdbd9f11, 0xf6c73bbd,
+ 0xb3ec19dd, 0x3bd93609, 0x38292130, 0x87905f8b, 0x6a2cf2c4, 0x94699c31,
+ 0xb584eb47, 0x1db2f15d, 0xa40f263b, 0x0ec17922, 0x5d49c822, 0xea908aa9,
+ 0x9a138bb6, 0x69824da4, 0x242da1a0, 0xab879467, 0x49b4c6a0, 0x988854d3,
+ 0x627121c6, 0xc7f34382, 0x6772a2b5, 0x1ee5bdbe, 0x554d0d36, 0x59cc7fa9,
+ 0xeedf4ff2, 0x3337cdf7, 0xe6f999bf, 0x0747a35b, 0xef500e98, 0xf3870586,
+ 0xb9a83601, 0x3402a99a, 0x2b7490ec, 0xe666a007, 0x8fc0bb3d, 0xeee6bb28,
+ 0x96f444ab, 0x70009d68, 0x6eff84af, 0x2830e7a6, 0xe6f8034d, 0x15d35cf2,
+ 0xfb8e6800, 0x5a002a00, 0xef0245e2, 0xb0235f8b, 0x9f620e35, 0x3c8d8b0f,
+ 0xc7e500b5, 0x4d79e223, 0x9357d7e7, 0x589c86fc, 0x6fe50ba9, 0x76d2cb68,
+ 0x3b8beca1, 0xc700abc2, 0x20e28fed, 0xbf41300c, 0xeef19325, 0x28a81978,
+ 0x39f15be7, 0xa3544702, 0x7b42ad44, 0xfc856be2, 0xb15cf886, 0x740569ef,
+ 0x77ccfb40, 0xca00eb64, 0x0bbe5f03, 0x401e01aa, 0x05ed0175, 0x600871c0,
+ 0xefc4105b, 0x2776b70b, 0xc9c5ffed, 0xf9c4c902, 0xe5bd931f, 0xf9ba5500,
+ 0x6f5e7a13, 0xf8fdb579, 0x052c5aac, 0x5af29e30, 0xdc6e3803, 0xf71302e7,
+ 0x81a22efb, 0x6602b1f8, 0xd2d3fd10, 0x3719eefe, 0xee65bc9a, 0xe50c5950,
+ 0x158d2dd5, 0xc6eb89dc, 0xbf84529e, 0x50fe079b, 0x9ff7c41d, 0x410b4b48,
+ 0xdebad806, 0x6c41417a, 0xff45ec7a, 0x2bbef8cd, 0x764cdc68, 0x7a079c7d,
+ 0x7461ea1e, 0xb679cbe1, 0x6ff413ae, 0x06753a3b, 0x563bbf40, 0xfdb946ea,
+ 0xf51347e8, 0x5796efe9, 0xcbf88f13, 0x60405dae, 0xf64c1402, 0xb5f8d6e3,
+ 0x6aab5fc2, 0x20103325, 0xfc21befe, 0x4f47b4d6, 0xe312e8f0, 0xb49c4496,
+ 0x32409c50, 0xbc3bee3e, 0xf05bf1ff, 0xb5b98c39, 0xe6b7d452, 0x865af220,
+ 0xabe22576, 0xe17bee46, 0xd93f1437, 0x8cacfc76, 0xcff9b6af, 0x3a979f88,
+ 0x400f0090, 0x2d3ebe20, 0xa2fc966e, 0x2847f2a4, 0x71b15f77, 0xcacfc537,
+ 0x31b75afc, 0xc007ac5f, 0xb0bdabf5, 0xb27f3a21, 0x2f146f5d, 0xf6fc87bb,
+ 0xfbdb0c96, 0x4b5bfdf1, 0xa8e90c96, 0x2af7c0e7, 0x3935642a, 0x4dc54daf,
+ 0xee0d5e71, 0x1f8efc45, 0x147d5af7, 0x848ea827, 0xbf1c2ff3, 0xfe8bdac1,
+ 0x97e3033c, 0xcb1d1c44, 0x5a8e2956, 0xf316ce5f, 0x5809af5b, 0xf56fbe12,
+ 0xa28dcf8f, 0x92bf97bf, 0x07fb2315, 0x0372c95e, 0x56627bee, 0xbde91b63,
+ 0x57eb95fc, 0xfd2fe848, 0x380dd798, 0xfd3afdaf, 0xcf0e7a7e, 0xbf8a00ed,
+ 0xe7f1137b, 0xb8a579f0, 0xd1e17fff, 0xd1e1cde1, 0x77e1cfe1, 0x7df1b16f,
+ 0x9fc3bff2, 0xf197d7c3, 0xe7bff7d1, 0x7c0aefa3, 0xf0dff93c, 0xc1727581,
+ 0xeccff261, 0x4d53ad5c, 0x03e1c7fa, 0x42438c4a, 0xa32b043e, 0x1fdeae0b,
+ 0x80fe1227, 0x295bda20, 0xfec954ec, 0xfd90ff4c, 0x97d69fe4, 0xfdb67dbd,
+ 0xbb1fd970, 0x30fd93c2, 0xabe8fed9, 0xb7e37eb6, 0xd55f7e91, 0xb315a70f,
+ 0x35f71db8, 0x0769650f, 0xdbafa8a6, 0xe0e58814, 0x0a876dfb, 0xceafaa2d,
+ 0xfd15b279, 0xec89b9e4, 0xa0e7d44c, 0xc33f9f5d, 0xe52c0d3d, 0x07670717,
+ 0xbe8dbea8, 0x6b8c832d, 0x54f59746, 0x6387d087, 0x0fd513ae, 0x1ad3f8e3,
+ 0x367b9cf3, 0x7babbbc6, 0x74f58496, 0x3ef1b145, 0x4ff5b3d9, 0x8adc4ffd,
+ 0x7b1c2fef, 0x7b999672, 0x507c76f5, 0x5017bb95, 0xb8140f9f, 0x9f79f88b,
+ 0x0baca55e, 0xf79b2584, 0x920f0ee5, 0x6f00a71d, 0x37fd41cf, 0x137fad83,
+ 0xaea8790c, 0x07b0c337, 0xe851bf50, 0x0f3a8909, 0x0ffc62fd, 0xb4e42235,
+ 0x32e7f742, 0x6db9b3f2, 0xa9e21ad3, 0xf389282a, 0xc919f9a5, 0x496e50b2,
+ 0xc0f31558, 0x7f287f8d, 0x6a96824b, 0x441dda18, 0x9cc390fd, 0x2c5be7d4,
+ 0xbec3afe5, 0xcd1139e4, 0x8c33de7e, 0xeb0caaf3, 0x5cb6b5f5, 0x4de7c2cd,
+ 0xabcfa4cf, 0x3c8ae886, 0x3ef80faa, 0xf4b65b86, 0xd2afbfa7, 0x68c98f3e,
+ 0xb873f36f, 0xaa36155e, 0x1eb6fba9, 0x125f9f4d, 0x1dbd0a0e, 0xdb4cab3d,
+ 0xd98f1b5f, 0xa6d87d76, 0xa6202780, 0x2509cd0f, 0xf87a86fd, 0xfd379e29,
+ 0x373a0650, 0xf84b03ef, 0x2ff1fa0b, 0x214fbf65, 0xc5067bb6, 0x0eec7cbf,
+ 0xff1d2f3a, 0xe53dea6d, 0x0ea273a1, 0x216e0c73, 0xf47a7b5a, 0xb11c70db,
+ 0xefee37c7, 0x278b31e9, 0x1fd329fb, 0xda67f699, 0x66cbc4e7, 0x61b4f4d3,
+ 0x03766d1e, 0x59369ccc, 0x2f3d2b6e, 0xe1df2c9f, 0x59f6cbfd, 0x3fcdce1c,
+ 0x340e2587, 0x76a826d0, 0xf22e98ec, 0xd2feeea6, 0xf9c53180, 0xc4e5e8e7,
+ 0xaa386f6d, 0xe8fc4587, 0x2bdf9465, 0x3e7225bd, 0x5bbeb7fa, 0x7fa97a0a,
+ 0x8ab85ae9, 0xe83940ea, 0xa23983bb, 0xae794d9e, 0x84bb0c6e, 0xbccb86dc,
+ 0xca171ea9, 0x8247bf39, 0xf5fe22bd, 0x1e149a9c, 0xe53d1e5b, 0x38e4d707,
+ 0xc66a7871, 0xb6fe203c, 0x20780f76, 0x286fd932, 0xd6a1d44f, 0xff4cbac4,
+ 0x3455e601, 0x58fdeaf7, 0xc9c7e19f, 0xb828187e, 0x71b3e313, 0xbc28d650,
+ 0x4fe07f1d, 0x44f6b1d4, 0xcf295a5d, 0x5d3e500f, 0x500d2c1c, 0xaaa8bd3d,
+ 0x296f3485, 0xc70864fa, 0x0458db92, 0x58694fa2, 0xe3f941e4, 0x1f42e5ef,
+ 0xe78b3fca, 0xdbb54ab0, 0x6f48b307, 0x5166d73c, 0xb7f8e67f, 0xf286095e,
+ 0xed7b13e6, 0xec58b045, 0xbfb54beb, 0x243dd7d5, 0x36ec69fb, 0x13497613,
+ 0xaecbe092, 0x3ac6bf43, 0xed51f544, 0xdaa76d09, 0x8731547a, 0xdf1091e7,
+ 0x6ff409ce, 0xcc4511f4, 0xcf2e786b, 0x1bdfa2f2, 0x667b96ba, 0x9e70f8d0,
+ 0x980ee746, 0x3afd5a7a, 0x7af155db, 0xd0dfea11, 0x14e4d61f, 0x91a790de,
+ 0xdd6ebf54, 0x37f05673, 0x57235f05, 0x0c91f788, 0x4fc6d29e, 0x9b5f4f10,
+ 0x2b5fde2a, 0x173ea1f5, 0xa795cfb1, 0x71381fb8, 0x7121f90f, 0xc84b6c8e,
+ 0xf3619c1c, 0x442d6e02, 0xeeb7fe71, 0x265bc12a, 0x6cff835f, 0xf3a1e45c,
+ 0x403af90b, 0x72fec57e, 0x20dfce3d, 0x3ffd5a41, 0x6fffa898, 0x78c5a075,
+ 0xf0ea9f44, 0xd4e78e81, 0xa20fb11f, 0x451d3bf1, 0x876efc62, 0x8ebdf02a,
+ 0x3c470279, 0x253fb9b0, 0x440030bf, 0xbca11efc, 0xec9422aa, 0x281e1ef3,
+ 0x47d22282, 0xd3afd44e, 0x4239a5d1, 0xf56c001f, 0x3a7fdcde, 0x5b3d626a,
+ 0x07dfa7a7, 0xa2c2bbea, 0x7b75ddee, 0xf97e9136, 0x7a744379, 0x8481bdfa,
+ 0xc451ef38, 0xa7666bdd, 0x6e03bfbd, 0x3f47be4c, 0xc2ab0c9f, 0x15d5dade,
+ 0x5dbf7269, 0xb8da6b77, 0xfd11ee3e, 0xb9c4e9df, 0xb7de9ff9, 0xfc70f932,
+ 0x5d0fb8dd, 0x5fbc9150, 0xfda8d43d, 0x7bae317e, 0xfa22a0e8, 0x179e91d8,
+ 0xdfe506fd, 0x88306a41, 0x7887a0e7, 0xf3b5de5e, 0xe9473a5e, 0x5df946de,
+ 0xe3de2aff, 0x12556312, 0x1f3b3b57, 0x98ad96de, 0x8bd1f824, 0x679fff88,
+ 0x73bfc459, 0x3acd1b8f, 0xd461f73d, 0xcf4d7cff, 0x439d1746, 0x5102c9f2,
+ 0xfd897ef7, 0xeeebdd08, 0xb3927457, 0xbf791de5, 0xbb1bdf6c, 0xe5481d68,
+ 0x251e1d33, 0xd7acfb92, 0xa94687be, 0x3cbf4413, 0x7ea3edeb, 0x8d02444e,
+ 0xa8b02c8f, 0xee24d68e, 0x0fbdce35, 0x3f3d0905, 0x7fb05539, 0xac9f9a6f,
+ 0x2bb3b232, 0xf544bd18, 0x568d93fd, 0x3b57a899, 0x64be440a, 0x63c473fa,
+ 0x17fdf1d8, 0x2a87be27, 0xe64adce9, 0x7f112ecf, 0xa115dd03, 0xa8de7c61,
+ 0x67922168, 0xaa0ce542, 0xcadd2347, 0x91e44b6a, 0x4af717ee, 0x5388a2e9,
+ 0xb711bf67, 0x39e90776, 0x740a5dd2, 0x4c7c6d0f, 0x50f7da8e, 0xffe6242d,
+ 0x11603640, 0x0c56ebca, 0x6be64c28, 0xc15933d3, 0x3773b491, 0x7adc6d2f,
+ 0x24704674, 0xc09b3e25, 0x94a847ce, 0xcd4f14dc, 0x27582bf6, 0x2822d31b,
+ 0x2dfa85af, 0xee301baa, 0xd3aef3a1, 0x2f48c5a3, 0xfa249573, 0x6d41f5d2,
+ 0xb1ddb925, 0xe76229bb, 0x406d029d, 0x6970c67d, 0x36b084b0, 0x055225db,
+ 0x1d5afccc, 0xb80daeed, 0x47963e44, 0xe526b542, 0x31bf4463, 0x222aeb82,
+ 0x7a339f76, 0xdc44b0a0, 0x02fa234f, 0x9e7a63d2, 0x905e11a1, 0x53b6cbc6,
+ 0xd9c9e29f, 0x9c94dd23, 0xee78ea7f, 0x3ea2df99, 0x0af4440f, 0xf000d79a,
+ 0x68f77d08, 0xb3f8df30, 0xba4c2654, 0xb3f987dd, 0x69fcec0e, 0xa8c4e5f0,
+ 0x1016827e, 0xec75af76, 0xc406c776, 0xd8ca3dfc, 0xac27e3b0, 0x646037c7,
+ 0xe1d1f39c, 0xd313bd05, 0xebdf5dff, 0x3ace7386, 0x0505dbf4, 0x91d8c4f5,
+ 0x31996c74, 0x0835258e, 0xa6871475, 0x03f713e6, 0x047c4de8, 0xb1d27fb1,
+ 0xeb6efe37, 0xbaa4175b, 0x9ae1812d, 0xf6c96c40, 0xad1f5197, 0xcb1b94bf,
+ 0x7f697cc1, 0x3ca2db3e, 0xa7a892dc, 0xf38befd8, 0x21f7e9c2, 0xe1f51218,
+ 0x1ff704c1, 0x39bcc075, 0x879d3bd8, 0x51b99f13, 0xc69981af, 0xcddfc877,
+ 0xdab393ae, 0xbd47fe71, 0xb7ba7e9d, 0xd6417f9e, 0x057ce0d6, 0x35de51d7,
+ 0xefa051cb, 0x9a63184a, 0xeca7b7c8, 0x565054f8, 0x7831da0e, 0xb9515368,
+ 0x374d8c4b, 0xfd0975d9, 0x435cf680, 0x31c9ca9b, 0xefa20ab5, 0xc50aabc4,
+ 0x6f4ee8cf, 0x4bd7c89e, 0x73ebc59d, 0x7972796d, 0x66458e32, 0x9975f0a7,
+ 0x5cbe0c97, 0x5ea8503e, 0xffb13ce1, 0xa41bd00d, 0x69e1c4be, 0xf2239ca5,
+ 0x2c88fdbd, 0xda76e9ce, 0x3aa63133, 0xfd0f91f9, 0x8caffa2a, 0xaf77eb7e,
+ 0x65bf4479, 0xbf6a5fe2, 0xce28dbd5, 0xcb7ca6ed, 0xacbea243, 0x2bee72cf,
+ 0x7d5fb55f, 0xbf38923c, 0xd142c217, 0xaa75c967, 0xf02ff49b, 0x890c3a89,
+ 0x62536a7e, 0x678ffb4d, 0x831d5217, 0x5c447b93, 0x77a1cf39, 0xdd9388ba,
+ 0x53161961, 0x44147d5f, 0xf47354ff, 0x6fddf15a, 0x0269d1cd, 0xf122f1fd,
+ 0x6f67f47c, 0x7bfc8a56, 0xf89970ba, 0xf5f4f97e, 0xc67e1d02, 0xebf9f65c,
+ 0x07f8e4f0, 0x1c7e6df2, 0xd0cb2a3f, 0x72afa8dd, 0x4ebedced, 0x8a16f7f4,
+ 0x86a93f6f, 0xf04f34f9, 0x71513434, 0xece4f9f5, 0x5f854cdf, 0x4015e64e,
+ 0xf3bbf0b1, 0xcefb5493, 0x7cd8a632, 0x2c911d8f, 0x424c7fda, 0xbc4e3082,
+ 0xd3951460, 0x76b041f7, 0x73189d53, 0xb3fdaac5, 0x7ba35f49, 0xf281e621,
+ 0x7f7c492b, 0x88c469f8, 0xe58c9e51, 0x39231681, 0x77c4b3c7, 0x53af271b,
+ 0x302614f2, 0xf5941eee, 0x187f5413, 0x19191919, 0x19191919, 0x19191919,
+ 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919,
+ 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919,
+ 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919,
+ 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x19191919, 0x017fc6a7,
+ 0x9b8bc43f, 0x00008000
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x92300408, 0x94019869,
+ 0x4e0cea60, 0x7ed64219, 0x6faf339a, 0xb6db6c55, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb805f8fe, 0x0061ff64, 0x000080
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x92300408, 0x94019869,
+ 0x4e0cea60, 0x7ed64219, 0x6faf339a, 0xb6db6c55, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb805f8fe, 0x0061ff64, 0x000080
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x92300408, 0x94019869,
+ 0x4e0cea60, 0x7ed64219, 0x6faf339a, 0xb6db6c55, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb805f8fe, 0x0061ff64, 0x000080
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x92300408, 0x94019869,
+ 0x4e0cea60, 0x7ed64219, 0x6faf339a, 0xb6db6c55, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb805f8fe, 0x0061ff64, 0x000080
+ };
+static const u32 EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x92300408, 0x94019869,
+ 0x4e0cea60, 0x7ed64219, 0x6faf339a, 0xb6db6c55, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb805f8fe, 0x0061ff64, 0x000080
+ };
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0,
+ 0, 12745);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1,
+ 8192, 13014);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2,
+ 16384, 2912);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3,
+ 24576, 95);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4,
+ 32768, 95);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5,
+ 40960, 95);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6,
+ 49152, 95);
+ INIT_GUNZIP_DMAE(USEM, USEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_USEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7,
+ 57344, 95);
+}
+
+
+{
+static const u32 EVST_CSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+ 0x649, 0x7ff8, 0x7ff8, 0x600, 0x61b, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x357, 0x7ff8, 0x3d6, 0x3d7, 0x1e6, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x480, 0x7ff8,
+ 0x7ff8, 0x41c, 0x408, 0x41e, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x9ce, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xa27, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xed4, 0xf3d,
+ 0x7ff8, 0x7ff8, 0xf87, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0xed4, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8};
+ INIT_MEM_WR(CSEM, CSEM_REGISTERS_INT_TABLE, COMMON,
+ INIT_HARDWARE, EVST_CSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE,
+ 0X0, 256);
+}
+
+
+{
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0[] = {
+ 0x00088b1f, 0x00000000, 0x7dd50300, 0xc5547c0b, 0x3d9cf8b9, 0x9b3bece7,
+ 0x081083cd, 0xf2200d86, 0x3c204966, 0x31024dc5, 0x5044c45a, 0x90583eb1,
+ 0xa06c8067, 0xedbd5edc, 0x50f2effd, 0x9f1b6a91, 0x11758b45, 0x1641a8a8,
+ 0x86e09209, 0xadc8822e, 0x6a5a36f4, 0xc406ad41, 0x08490880, 0xcb4af168,
+ 0x999bef9d, 0x1b273ddd, 0xfdfd1f12, 0xfcfe377f, 0xf5e6730d, 0x6f9af7cd,
+ 0x5666f9be, 0xe8622621, 0xf865c84d, 0xa7908ebb, 0xa8c84265, 0xf3d91a58,
+ 0x2749134d, 0xea8d6ce4, 0x5210e532, 0x5c8d53b4, 0x364bf347, 0x1bc84148,
+ 0x190858f6, 0x7af34849, 0x0dc9f796, 0xcb4f1cbf, 0x6c992ec9, 0xd88909a6,
+ 0x9083240d, 0x7f613326, 0xcfcc24ae, 0x92ecb0b3, 0x81ef7b0d, 0x9ad417fe,
+ 0x6fb68588, 0x903d91aa, 0x0a59b65f, 0xd7968912, 0x49ec643d, 0x941f9ffb,
+ 0xcd171642, 0xe8cc7e6f, 0xe564224a, 0x619a6f9e, 0x69d7015c, 0x8cb899bf,
+ 0x325fdf00, 0x5210871a, 0xdc5edc1e, 0x5e53f693, 0x740db92d, 0x52f5f29c,
+ 0xf091bae4, 0xb4ca0a5d, 0x6c5b45df, 0xc18035c4, 0xb8e09970, 0xcf658f38,
+ 0x7f6971d1, 0x9632a944, 0x13c6c526, 0x5fed39f8, 0xfc88e387, 0x38e89792,
+ 0xabc55db4, 0x58a61b92, 0x10de2061, 0xceb9bf1d, 0x1da36332, 0xd8c2b7e6,
+ 0x1e7e293f, 0x79875eb3, 0x18370794, 0xd700ed8b, 0x21bce306, 0x6d16feb1,
+ 0xae168df9, 0x7bbb7d75, 0xe9f5cae3, 0x69453f69, 0x9cbe58ff, 0x0ec84f10,
+ 0x658d07f0, 0xffdf6343, 0xd210a524, 0x8997fa0d, 0x9feb1ccb, 0x977e0090,
+ 0x78023b89, 0x7724e127, 0x9cdadd3c, 0x4b2dba5a, 0x803b6de1, 0x0e9c57e7,
+ 0x989df98f, 0xc4cfe13e, 0x0bbf29f4, 0x7fb5fce1, 0xf8cfa600, 0x37fdf8dd,
+ 0x3e9831fe, 0xfa60f7e7, 0xd304bfbc, 0xac52fe0d, 0x033fd1b7, 0x2f7ecdd3,
+ 0xbfd17f7e, 0xfc97d300, 0x15fdf895, 0x6e987dff, 0xfbf007f5, 0x4c1aff36,
+ 0x30abfbb7, 0xb5e9c1dd, 0x7ac41fd3, 0x305bfcbb, 0xf087f3ad, 0x5afe1bfb,
+ 0x3c051f4c, 0xe3d934d2, 0x3a50a15c, 0x4e224f25, 0xad2426ca, 0x4a8574b4,
+ 0x59d369f3, 0x6ab7bbbe, 0xa9e29185, 0xa79a1cfb, 0x6caacc74, 0xe5a26158,
+ 0x7959cb59, 0xa57380ef, 0x5ef79699, 0x56fbcacd, 0xd0b4ae95, 0xb24fbef2,
+ 0x55826bf2, 0xfcb4ad2b, 0x7cac4d9a, 0xa561a870, 0xae0f968d, 0x23c3e561,
+ 0x9a7655ce, 0xe59fbe1f, 0x574a1af3, 0xde7cd125, 0xdd1f9661, 0x41cab558,
+ 0xc13e8fdb, 0x0d6f8fda, 0xfe38aec9, 0x4ad2a1d8, 0x5342813d, 0x07ca1e3d,
+ 0x644e7479, 0x16f9901c, 0x8a30efcc, 0x1e3ddbf2, 0xc4cf2eda, 0xb13b81f3,
+ 0xbdb4677c, 0xa2a3f317, 0xf2b0e7ed, 0xac85fb68, 0x097eda3c, 0xbca977e6,
+ 0xf986593e, 0xe07ea2d1, 0xf45caca7, 0xcac67e47, 0x3f7fa24d, 0xe3a2ebe6,
+ 0xd8fcc6af, 0x106bf8e8, 0xf8e8bade, 0xe8f2b28f, 0xfe618ff8, 0x28fe3e0d,
+ 0x804f69e9, 0x792a5fd6, 0x6efe079f, 0x202e5431, 0x4894d3a0, 0x43f5c826,
+ 0x72019912, 0xa1713f7a, 0x2ae87b9e, 0x7fe407a3, 0x1bf9bbc7, 0x5fe03f41,
+ 0xfde7e43a, 0xf60e6d6e, 0xb5ea05b3, 0x7d3f6918, 0xef27ef3b, 0x7e9a31bd,
+ 0x205bdef2, 0xf08ed9fa, 0xcfd6bb58, 0x69c6f78e, 0x5caf79e1, 0xe11bb3f4,
+ 0x5e6d7471, 0xa09e7f79, 0x8bcfe785, 0x10fb3f45, 0xc1aed49e, 0xc528f3b3,
+ 0x9fac4e4f, 0x7e29479d, 0x10e7ec24, 0x35d193f6, 0x307d4678, 0xa8cfd346,
+ 0x7e88160f, 0xeaf382fe, 0x767eb5d9, 0x0b4e307e, 0xa2e507cf, 0x9e118f9f,
+ 0x6bcdaeec, 0xb41387d4, 0x58b87cf0, 0xfb1273f4, 0x7eb5d3e9, 0xe2d31d76,
+ 0x28b1d767, 0x9fb15a7e, 0xd79b5dfe, 0xfc5ae3e8, 0xc51e3e8c, 0xcfd8d7cf,
+ 0xb3f5aea0, 0x3f16b8eb, 0xf1478ebb, 0x9fa09063, 0xd79b5d61, 0xf8b54fe8,
+ 0x1469fd19, 0x27ec363f, 0xd4f06bb7, 0x4fc5ae7d, 0xfc51e7dd, 0xf7404ba4,
+ 0x33c1aefc, 0x3f16b4f6, 0xf1474f63, 0x33f61573, 0xd4fd6bae, 0xa7e2d69d,
+ 0x3f1474ee, 0x135e71fd, 0xb1af36bb, 0x33f1685f, 0x7e288bf6, 0x853f6386,
+ 0x1e105b95, 0xda19fb42, 0x9c6f3f71, 0x379fead3, 0x33fd31ce, 0xf50048f2,
+ 0xdc499abe, 0xd684ce00, 0xf34480d2, 0xbbcd3a4a, 0x2f10f520, 0xac0a7fd5,
+ 0x71a043ff, 0xe5a64063, 0xb929d549, 0x76f15d6b, 0x8075e140, 0x8348c71f,
+ 0x4e70cec6, 0xa9f26ab0, 0x76355293, 0x9e94fa42, 0xf4c67c9a, 0xe67c9a3e,
+ 0xed34835d, 0xd5c9ce7b, 0x1e2d7be4, 0x2f67c9a7, 0x77b4d42f, 0x4d46fcfd,
+ 0xb7d59f79, 0x1efdf268, 0xdf26b1f9, 0x9ad9c9ff, 0xe5f580fc, 0x6d06fe9a,
+ 0x0fc9a65a, 0x4d0ffea9, 0x4acd587e, 0x5e1dde4d, 0xeee7c9ab, 0xffd35c7f,
+ 0x6acf43c8, 0x5f87f9f2, 0x7cc7e4d0, 0xfda6b2f4, 0x69af13b8, 0xecce13f2,
+ 0x765dd9d6, 0x9e60d367, 0xb6cec197, 0xca69fda1, 0x5d1da236, 0xfcc66d90,
+ 0x98edb34f, 0xef44e9ff, 0xd74a4e35, 0xb183405f, 0x0ef46f34, 0x0bb02677,
+ 0x240d2529, 0x81af5213, 0xbe5f698c, 0x477ca546, 0xf7b0a4f9, 0x68c7fea5,
+ 0xf6b433ea, 0x79e9a14f, 0xe02ac143, 0x019235d3, 0x9326d1f9, 0x9b23e04a,
+ 0xae5f2089, 0x637f3ab9, 0x1fbf8e20, 0x297c61ce, 0xba387dfa, 0xc00c1f6e,
+ 0xc490fd3a, 0x71b781f3, 0xc7287e5d, 0xd572eb88, 0x8123b78a, 0x9cbfb47e,
+ 0x5d82669f, 0x7b52366b, 0x231e1e39, 0xc2086785, 0xe9f014f3, 0x63c01db3,
+ 0x03463fee, 0x02cfa58f, 0xa8963c0d, 0x006ef19d, 0xd3c28fc7, 0x6331e1c0,
+ 0x0d1585fe, 0x1a150091, 0x10fb9f73, 0xb246359e, 0x358f0340, 0x808bcf0a,
+ 0xf08eea9f, 0x169c7fd3, 0xb5ca7d3f, 0x2dda89f8, 0x73f0e81f, 0x4563c394,
+ 0x1c566b78, 0xf3e9f865, 0x263f0c1f, 0x3c3c4e3a, 0xeabd288e, 0x1d3d9e00,
+ 0x099ae7e1, 0x5df4fc5a, 0xb08fc5ac, 0x3aa7c89b, 0x9da38e78, 0x1d8e50f5,
+ 0xe2b039e1, 0xdf4fc338, 0x263c239f, 0x49dba553, 0xadbd4c8b, 0x33d04195,
+ 0xdd27acd4, 0xb8e94041, 0x52d041a3, 0xc841e909, 0xdc1f527d, 0x4ad4fc57,
+ 0xffd696f9, 0x15f94aca, 0xbf7c25f6, 0x967aa731, 0x855a51f1, 0x48941f04,
+ 0x7137dd3e, 0xcb5398d9, 0xee8461f6, 0xf0a6aed3, 0xff9ed736, 0xff0a43ea,
+ 0x50234d9c, 0x214951cf, 0x9f2e7f50, 0xf8664f9a, 0xbb34a421, 0xa267ea8c,
+ 0x32df6694, 0xb03c8b14, 0x104f995f, 0x307276c6, 0x6a6d4ab7, 0xf9df938c,
+ 0x85f9b4eb, 0xc05e6d41, 0xa4ff005d, 0xf74e3ef8, 0x23ee8435, 0x06fba23e,
+ 0xa9fb6942, 0x5296664a, 0xf74c7c7c, 0xa46f903f, 0x27281ffb, 0x4fab0564,
+ 0x3af30871, 0x0416c6be, 0xff757cba, 0x2bac2308, 0x72a3ef33, 0x0217af1f,
+ 0x852670e4, 0x6fcf94bb, 0x534d2056, 0xaaf16cde, 0xde011eb8, 0xf8ca1e29,
+ 0x1e276efc, 0xf7ed3bb5, 0x2a65e5ee, 0xe1a503ac, 0x83885325, 0x64d77b90,
+ 0x3f18e551, 0x01964f0f, 0x32c903f5, 0x4b70fd50, 0xd69508cd, 0xf51e6520,
+ 0x38dc6378, 0xf9b44ad3, 0xf9b54b5b, 0x1aa3d566, 0xcb9a5d28, 0xf281b224,
+ 0xb433edce, 0x0c71d1e5, 0x313788a9, 0x5b9d295e, 0x2798548f, 0xfdff4c6d,
+ 0xdf832763, 0x67143727, 0x47f3fec1, 0xcc337b92, 0x02e5ea07, 0xe11a0f3d,
+ 0x529b8cfb, 0xf6696bdc, 0xd1f9b288, 0xe1ed3931, 0xf6264a25, 0x4fef8477,
+ 0xf363d83f, 0x3e758618, 0x48483b8f, 0x0f597585, 0x6d5e1dff, 0xfa05cefe,
+ 0x687e31f9, 0x0e3e74e2, 0x93d3407c, 0xff1407c0, 0xc41f3827, 0x83e332f4,
+ 0x7483e026, 0x3e33d7d8, 0x6a024f98, 0x31f8090f, 0xc6dc1f31, 0xfbd040f9,
+ 0xdbef4e76, 0xafe77d38, 0xbb47f2d3, 0xe1b93c79, 0x82574c81, 0x57b23cf9,
+ 0xf3f68625, 0x3e0cc9f2, 0x7052eff2, 0xeeeb8533, 0x6df96d4a, 0x3979fa3a,
+ 0xf66288fd, 0xbefe5294, 0x20b4fee7, 0x39bb99e8, 0x7bac66fd, 0x711eadec,
+ 0xd398f9f4, 0xd3670f47, 0x81aa8dba, 0x205c6fb6, 0x1a7fb011, 0xa33afd39,
+ 0x34e24cc3, 0x70f4fd02, 0x9b4fbcce, 0x4c48159f, 0x416d5f3f, 0xefb889da,
+ 0xa437424b, 0x9793889d, 0x34ca5b45, 0x3bc185f9, 0xafe7f534, 0x9f29a59b,
+ 0x5350b55b, 0xa59aef7e, 0xc0acfc9a, 0x33fa9afd, 0x29a15bef, 0x61f2bbbf,
+ 0x0b9df94d, 0xefe4d31e, 0xa9a33ef0, 0x0d8cfb7f, 0x4b5bf29a, 0x4f94d25f,
+ 0xc9aed92b, 0x34ea7997, 0x0b3da5f5, 0xccbf837b, 0xdf3ef467, 0x477cfc1d,
+ 0xa905e44d, 0xfa131ebd, 0x85df84ee, 0x03fc9bdf, 0x77e53d30, 0xfed3f7e3,
+ 0x00ae9831, 0x03d74dfd, 0x7d4b1d43, 0x0deacf8f, 0xc1c85f7a, 0xbb3baaa7,
+ 0xef5eded2, 0xa89cf5e9, 0x917f5edf, 0x3a6fb02c, 0x962d3ff2, 0x07ac2948,
+ 0x73b3122d, 0x7c93f7c4, 0x2564249d, 0x4c8d8ba6, 0xd6bf174e, 0x68e410a3,
+ 0xbfd231b1, 0xbf71ded2, 0x7ce12424, 0xd5f556e6, 0xdd7f39c0, 0x0b7c0d60,
+ 0xfc9a7983, 0xb5e32da2, 0x3fc7cd72, 0xf84657b3, 0x1ddd602a, 0xe97b760b,
+ 0xc9e8030e, 0x69ecbec8, 0x4f5e0143, 0xbb6be60d, 0xc67a7ae1, 0x4276925f,
+ 0x62973c01, 0x033fca7a, 0x17bf26d3, 0x05fe13d3, 0x57f71e98, 0xbfe8da62,
+ 0xfd8fd30f, 0xf23f4c01, 0x03f4c1af, 0x47a6157f, 0x7d30ebfc, 0xf4c41fdf,
+ 0xa60b7fb0, 0x9843f9ef, 0x316bf836, 0x307bf66d, 0xc712f215, 0xc47bbd2f,
+ 0x77d08bf1, 0xe29e1f42, 0xf81a72fc, 0xbc5f1125, 0x938be5a0, 0x85f2256a,
+ 0xe9ea0f5e, 0xdf77d7a0, 0x18061f95, 0x587e187e, 0xd1d2cc18, 0xe9576fbb,
+ 0xde9e2e7d, 0x064e0c03, 0x23f7a70f, 0xda45783a, 0xad23940b, 0x7b3133e7,
+ 0xcc6c788f, 0xebfc2b4f, 0xb4fccac4, 0x42debfdc, 0xf500ddff, 0x4200d094,
+ 0xf21b6bfb, 0x2fc1fd3f, 0x1a8476de, 0xcf1d3980, 0x0ebf4f4f, 0x860240f1,
+ 0x6adfe12b, 0x50a57865, 0x1eba1095, 0xbaf81dac, 0x2bcb367b, 0x1211d604,
+ 0xa9fbc772, 0x4e02fda3, 0x01df80bb, 0xda676606, 0x1f0cc9f6, 0x69ee1d91,
+ 0xf57e3149, 0xf7fb5a99, 0x43f27b00, 0x8cf58113, 0x7c5aed04, 0x3f3e6805,
+ 0xe68eaf86, 0xfbde99d1, 0xef9f85ff, 0x4a4e8fab, 0x4b5fc657, 0x250fdd21,
+ 0x7d9667d8, 0xc86c3e67, 0xc03c3e06, 0xe6adbdf9, 0x2432649a, 0xe0d78fd6,
+ 0x09d07262, 0xe0c97c9d, 0xe7ff07ac, 0xcd20a6c5, 0x77bd924f, 0x9c9db4c9,
+ 0xf601c67c, 0xd1924b6f, 0x4d438640, 0xedbb3eed, 0xec0746e0, 0x1a659663,
+ 0x3af2279c, 0x5092cba6, 0x6f1ed38e, 0xf36ad517, 0x0952556d, 0x92b8b3f3,
+ 0xfd050fa7, 0xe89e74ec, 0x1332fa07, 0xb2cfd153, 0x44f3a34c, 0xb20bd41a,
+ 0xa0a75579, 0x9bf69ffc, 0x0d0fdeb1, 0xc4fd4747, 0x9f21a8e0, 0x0a20f6d2,
+ 0x5c76fb97, 0x567e43bf, 0x7fc1182e, 0x57eac245, 0xd0b23fb0, 0x3ec32fff,
+ 0x1798288e, 0x7242fafd, 0xaff884c0, 0xdb478cd6, 0x2059c4b9, 0x6e58ebb4,
+ 0xf824d214, 0x29edd296, 0x68b91e7e, 0xb5a9c58b, 0x793452d7, 0xa70f6d5f,
+ 0x7f837ec6, 0x463a0180, 0x169f8052, 0x625a7673, 0x297a346e, 0x8cca55ab,
+ 0xfb145adf, 0xebc2891a, 0x65fd5893, 0x0ed0933b, 0x3f18f65e, 0x06900c0f,
+ 0x63d9bfe0, 0x28970778, 0xfeb1f954, 0x0c46cae8, 0xcf2f7f34, 0xcfb97389,
+ 0x79f70048, 0xf955cb9f, 0xaecea760, 0x7b768459, 0x11836879, 0x8967d9f6,
+ 0xfcf404a1, 0x239ef259, 0x22ce4e2f, 0xbae111b2, 0x6ed68d77, 0x4d56fba5,
+ 0x355bee9e, 0x96e479f9, 0x9abf380c, 0xb74aa4f7, 0xd58fb8d0, 0x26648794,
+ 0xe549f377, 0x7efeb083, 0xdb77935a, 0xaec7c078, 0x6e41f2e7, 0x2ce2d366,
+ 0xb7ca77aa, 0x39046bbc, 0x85fc6ce9, 0x3db73f50, 0xc571fa1c, 0x579ddabc,
+ 0xd92c3c72, 0x09827922, 0x723fbbd6, 0x51f4233d, 0x4b83e72b, 0xd21f97df,
+ 0x2a1f8689, 0xb909ef65, 0x7c2f8c5b, 0xdfc90fc0, 0x76ccffa3, 0xa0feb7fd,
+ 0xfda2f7fd, 0xbffa6be7, 0xdff683f4, 0x66fc1daf, 0x8bff4125, 0xb0070dcd,
+ 0x4123d382, 0x47cb857d, 0xfa2774c1, 0x25aa5aa1, 0x27d689b7, 0x6672e21e,
+ 0xfb003d30, 0x92d796c5, 0x567e8187, 0xcbee4e69, 0xb96878da, 0x283f978d,
+ 0xf44b308d, 0x739a92fb, 0xed06fdff, 0x099612c7, 0xbd54aa88, 0xf744af77,
+ 0xc41dab85, 0xb4f94293, 0x034cf285, 0x4f147ff8, 0x362bac0a, 0x7bea08f2,
+ 0x8cbff338, 0xffab4efa, 0xf476cb27, 0x97adb4c3, 0xa04aafd1, 0x7c53ac2a,
+ 0x41932b1f, 0xe5409ebf, 0xca9077de, 0x41b7cd0f, 0x4ebfa80d, 0xdb7afdc2,
+ 0xcfcc22c1, 0x1a4893af, 0x38b3afcd, 0x943ac186, 0xfc6831e2, 0x5a2569bb,
+ 0x78093a7f, 0x3f3f601a, 0x100fcf87, 0xe22ee302, 0xa9a56ef9, 0xbff4faba,
+ 0x1cd73f38, 0x8429bcef, 0xfc917bce, 0xd7f001c8, 0xf5a19f74, 0xcb93b7c7,
+ 0x40460dda, 0xb9726742, 0x7f368b68, 0xde9492bd, 0x46d01034, 0x8eaf80ec,
+ 0x78a773f4, 0xebffec6c, 0x8ebb2309, 0x4c7e3d47, 0x5a7c5a99, 0xda7c5a5c,
+ 0xa5f0e806, 0x5b9267c3, 0xfcba1f8b, 0xcf84af06, 0x347d31e4, 0xf850fdfd,
+ 0x0e7c00ac, 0xfe93e18e, 0x98339a95, 0x3d9c0188, 0x73f20894, 0x81223d96,
+ 0x1e955c6c, 0xa3a7c15c, 0xc81b1791, 0x2777b409, 0xf267dca1, 0x8dc42879,
+ 0x431e0272, 0x39a59758, 0xf91b3fac, 0x0164d9c8, 0x2e4a7ca2, 0x8e98ee0f,
+ 0x7fdb293f, 0xbd6d366c, 0x3878f81e, 0xac084bee, 0x65ccbf53, 0x2bb16af4,
+ 0x85dfd841, 0x1cd766fc, 0x088607dc, 0xeabd839c, 0xd439ae27, 0xefcd797e,
+ 0xb91434c4, 0xff02e190, 0xdfba5cf4, 0x90fcfaa2, 0x2d7d406a, 0xaa7ff9c6,
+ 0x49f1eb91, 0x43f105ff, 0x000ed42d, 0x784b513f, 0xc86af9b3, 0xcf18cad7,
+ 0x1aa94be0, 0x8737e308, 0x303f1c55, 0x607e8cc7, 0xeb8abd5f, 0x099cf371,
+ 0xfa23bf18, 0x25cb0e6d, 0x096e87e0, 0x37b8ea7f, 0xae68fd6e, 0xac20627d,
+ 0x1218cf5f, 0x8ad5afdb, 0x1fadfbe1, 0xc7e9dbeb, 0xea14656a, 0xa1f65fc7,
+ 0x6b28a8f3, 0x3fd97e43, 0xef9c46ef, 0x32e4b0ce, 0xe58bb851, 0x14347ebb,
+ 0xa2ff0bce, 0x3c48bd30, 0x30656653, 0x0bd33797, 0xe1967f55, 0xba6e925c,
+ 0xbe314ad7, 0x27cbcf1e, 0x01492585, 0x608474fd, 0xf39591fb, 0x2f189ed0,
+ 0xc808bcff, 0x10961f93, 0x048df94f, 0x3546a7e3, 0x1c7e1a28, 0xf9d1447d,
+ 0xf03282c1, 0xed46d8cd, 0xb4a7f1f7, 0x1f05b7f9, 0xf006483b, 0x649793f1,
+ 0x968cec09, 0x495ee256, 0xd39968e1, 0x6ae000b3, 0xd0dc40b9, 0x5c92e5a6,
+ 0x7aff6892, 0x5f223144, 0xe764633c, 0xb3cccf14, 0xfa505707, 0x1caf39be,
+ 0xdd5f0afd, 0xe89dedef, 0x17662b5c, 0xae036492, 0x38649e31, 0xd949fadf,
+ 0x3d95096a, 0x9a51eaa9, 0xe0bebed4, 0x82bfc153, 0xb3cc7b5f, 0xc609837a,
+ 0xc212aaf1, 0x806f3857, 0xb6b88464, 0xa381123d, 0x5e95e692, 0x9f42bf8d,
+ 0x2ccac806, 0x7b57c780, 0x90eb08de, 0x9ed89c39, 0x20715af9, 0x0caf35df,
+ 0xb93880ac, 0x0be1529f, 0xefd4aeb8, 0xf8dfe893, 0x5c217144, 0x59aae6cd,
+ 0xb9d6df40, 0xe802f266, 0xc7aaa54d, 0xefc0492d, 0x483c3745, 0xd4b67de1,
+ 0x33e4eb80, 0x0fe11baa, 0x0e2c212c, 0xc4e4894f, 0x16a0c7e3, 0x07385438,
+ 0x983d9956, 0x004b75e6, 0x7f1ffbb7, 0x4639c077, 0xd21345cb, 0x57f727af,
+ 0x55037688, 0xaabd8f66, 0xf82acc7a, 0xa3a4162f, 0x0ebdb83c, 0xdeba1cd7,
+ 0xf8a5af0e, 0x09f7604e, 0x4bd52dfb, 0x2b851475, 0xfe406ed5, 0xcb8f1e24,
+ 0x8f99f549, 0xf200bf88, 0x221e547b, 0x63f25112, 0x017532fa, 0x679c1f9d,
+ 0x97b63311, 0x892452c2, 0x6691bbea, 0xbb06447b, 0xb4cbfc00, 0x4a63f57c,
+ 0x473b1570, 0x04be8377, 0x7ee84f1d, 0x68d2bd63, 0xcf7e9ab9, 0x150ab8f1,
+ 0x385eb794, 0xa9a7d09e, 0x83002b8a, 0xb880b55f, 0x9fa62403, 0x26728349,
+ 0xfb441e7a, 0x2e7df5b1, 0x50676a25, 0x4ff11ce1, 0x7af1f719, 0xfce5cdfa,
+ 0x1deaaaf4, 0x761ef801, 0x304df5b0, 0x0616dc57, 0x332dfba7, 0x7cc587ae,
+ 0x99fb1d3d, 0x827a0821, 0x73c3ae44, 0xe8599f2e, 0x189ead05, 0xc6236d7b,
+ 0xca3d8d8d, 0x0e1d1ce0, 0xa85c45e5, 0x6ed03c2e, 0x5c9f1454, 0x2cbb707f,
+ 0xcfb79c37, 0xfdcdc74e, 0xd0a9c988, 0x0307f91f, 0x87e7e032, 0x3e7a17d2,
+ 0xf2a11118, 0x8437f1c7, 0xd07799c2, 0xf943cd19, 0x5fab5534, 0x7646cbd2,
+ 0xe088fd87, 0x855e3d2f, 0x3be5eb1c, 0x3ef73ef7, 0xff7d5790, 0xef8d8a44,
+ 0xc7e31bea, 0x921de667, 0x156f4193, 0xb8507c50, 0x9672e1be, 0x03782172,
+ 0xf0c9e3e0, 0x8b9016f5, 0x6c4ebcef, 0xd6e3ada2, 0xef647b89, 0xd1d99552,
+ 0xc543c00e, 0xa6460bde, 0xef4822bf, 0xb953df28, 0x2e427680, 0xa2af7f04,
+ 0xb1be86a5, 0x42965a75, 0xe546b460, 0x26a7cf40, 0x64d9deb2, 0x0387b38b,
+ 0x5947e829, 0xf5b4edce, 0xb9650e3c, 0xf53dd3c5, 0x77d77a0a, 0x718240d1,
+ 0xd29f0a7e, 0xe87d046a, 0xc12468bb, 0x9f81efb4, 0xbe4fc520, 0x254f3f06,
+ 0x8852cfc2, 0x7ff5182f, 0xeaadfe02, 0x0ffc2d28, 0xbff062b9, 0x83c8ab6e,
+ 0x9c3bfd3c, 0x31ef4719, 0x8cfb95b5, 0x78aedfec, 0xa9f215f9, 0xe1b1cb97,
+ 0x69780ca0, 0x1a649f2f, 0x11f195e8, 0xe5e83f66, 0x56b48d34, 0x5cdf54a8,
+ 0x0cfbf0e0, 0xd1f3f9ad, 0xc0346f7e, 0x1d4b5bf9, 0xbdee76c1, 0xa68fd027,
+ 0xb249eb97, 0x1f986de7, 0xacd34869, 0xe9d7ed0b, 0xe5f73b00, 0xcf82bdfa,
+ 0xed939573, 0xaf017af7, 0x082be4c2, 0xb54a339e, 0x3ce97f94, 0xf1620d7b,
+ 0xb1c6bdd3, 0x5c5390b8, 0x69e59e7f, 0x7e565caf, 0x78c5e79e, 0xa2285ea2,
+ 0x0bbac094, 0x12fc142a, 0x5e69fca2, 0x7cf5517e, 0x5065fc02, 0xaa418f4b,
+ 0xca60242a, 0x427f2f6d, 0x7de9dade, 0xf1893c9d, 0x8fd7f3f4, 0x0763ed47,
+ 0x732dc7d8, 0x7b224948, 0xb1c7d854, 0xf7ee57fa, 0x9a27e013, 0xb83c4b9a,
+ 0x8939669e, 0xcc74a25b, 0x9b924252, 0xd8ba9ff6, 0xd679eb85, 0xf0015714,
+ 0x91d51643, 0xd5a2c7e8, 0xbbfce34a, 0xe1b749cd, 0x94bf9a64, 0xc29dbd98,
+ 0xe34e81e8, 0x6bfb127c, 0x87711fb7, 0x283cef40, 0x3c60d7b9, 0xd4342502,
+ 0x0f797857, 0xff2bf323, 0x4335694a, 0x4603ccfc, 0x7ee858a2, 0x6e1397fd,
+ 0xc8b42b71, 0x30db6d71, 0x4f35ebd8, 0x1abfeb68, 0x6e9bcaf9, 0x8db27f04,
+ 0x85a9a7ed, 0x467e8d93, 0x0f4191e2, 0x10a9fe0a, 0x3555a974, 0xbec0b174,
+ 0xcd2e8e3f, 0xdeb8c549, 0xf3e42f37, 0x95e746ea, 0x0a5e6893, 0x5798a7f2,
+ 0xf98731ae, 0x179d09c3, 0xbe16d3e5, 0xc17017bf, 0xbdd838f9, 0xec36f7e4,
+ 0x735ed7ef, 0x76abf00f, 0x03d2559f, 0x473eb8fc, 0xe049366b, 0x73f3a557,
+ 0xabbafcc3, 0x77a02995, 0xe4cddfba, 0x38b70f4b, 0x383fc2a7, 0xb69439a7,
+ 0x79da2d61, 0x7df2c3c4, 0x253cc05f, 0x2e65e014, 0x2d7383d7, 0xfaf119a5,
+ 0xb9bf49ef, 0xf962514c, 0xc0b8d16e, 0xfe389a01, 0xcb03fda7, 0x577ad126,
+ 0x975d991b, 0xfe3eda41, 0x5e671d19, 0xfb0dcd8d, 0xb7b28df6, 0xeb3ee004,
+ 0x212ebd71, 0x80252b9d, 0x12f3c963, 0xda073679, 0xd04e7e11, 0x197ddff4,
+ 0xa78a6f1d, 0x62f0afa3, 0x45ae4c36, 0x7252b525, 0xa3d2ce4c, 0xf068f7f8,
+ 0x75f40e9f, 0x22147f00, 0x064ab0fd, 0x4ff089fa, 0xd19285d0, 0x852c7c05,
+ 0xed1afedf, 0xa72a52b3, 0x0b657e71, 0x1f9c69c8, 0xaffea5a8, 0x3f280557,
+ 0xcf3fedfd, 0xb0249127, 0x40935ba7, 0xfcfd4e4e, 0x7f1049cf, 0xb39fb7f5,
+ 0x596fa47d, 0x0f7dc232, 0x1a977bb7, 0x8d85bc99, 0x5e61f3a5, 0x40fffd33,
+ 0x8fb9293f, 0xa42dd39d, 0x7cfe386a, 0x083d23a5, 0x66884df7, 0x639ed17d,
+ 0xbdd8512e, 0x0dfb7d0d, 0x5d4fb646, 0x98c1bd58, 0xbc3802e5, 0x9c7001ff,
+ 0xa744f1e2, 0x453f986a, 0x7abb35c0, 0xdd6c1184, 0x1226c24f, 0x2a2de761,
+ 0xf8f0b79e, 0xc94fb9c2, 0x1e24becc, 0xeef144bb, 0xcfd578e5, 0xeb1d1663,
+ 0x73af2a3e, 0x218a72eb, 0xc3ee602e, 0xbc53ee12, 0x6fcc85e1, 0xd40f9ba2,
+ 0xa3d539ff, 0x3a1efbde, 0xcfd3f407, 0x85fc7daf, 0x67c7c487, 0x8c5e21cd,
+ 0x9bfbd0e3, 0x817f87e7, 0xf7e675fd, 0xda918dfe, 0xcc3ce08f, 0x9ce1a327,
+ 0x873f0ce1, 0xec417b86, 0x3a609a3c, 0xe762e8df, 0x2ddfcbbd, 0xabb8e606,
+ 0xb9fa3b72, 0xeffaf3bf, 0xddf6f496, 0x92cfa056, 0x1f8e63ca, 0x362aa1d3,
+ 0x9f60fdd0, 0xe4ef7cd8, 0x8386a5f3, 0x4eedfa0a, 0x173bbf3e, 0xe3e217a8,
+ 0xf98a76cd, 0x91f3a68c, 0xf311f363, 0x59e5c258, 0x8bf04fcc, 0x9cf9d7e0,
+ 0x9fd5566f, 0xfa646ecc, 0xa38930e4, 0xa0afa0b7, 0xdbdffce7, 0x6ee6ee50,
+ 0xe9ee2829, 0xca847382, 0xa3d7a089, 0x7a3f0d74, 0x092ef50e, 0xb1f8b264,
+ 0xc3ec2648, 0x6cc6d59b, 0x7d3d2390, 0xf65db99b, 0xea2fcf6d, 0x746fcc8d,
+ 0xf03aa94a, 0x4defe033, 0x1c84ef8c, 0xf5b5d92d, 0xf2e39075, 0x40394f6d,
+ 0xaa573f8e, 0xc5fc6032, 0xc0701f9b, 0x2529c239, 0xfafd00e0, 0xb3c99079,
+ 0x261c9e5e, 0x2fd39f86, 0xc82a62ff, 0x559b57c3, 0x0f271ca7, 0x6df19d62,
+ 0x144c4531, 0x0c35151f, 0x8c7f343f, 0x3c421fe5, 0x54f8bf94, 0xf30bdc06,
+ 0x2b8bb6d5, 0x1175f1e2, 0x6c57b7dc, 0xe418acfa, 0xf15a47cf, 0x1f5f45bc,
+ 0x8a98bbc6, 0x8cb365e7, 0x63fa89c9, 0x1fdb137c, 0x34bde237, 0x9be30d5f,
+ 0xe94f5c05, 0xc743fddb, 0x241f023f, 0xbc96f4c8, 0xc761b9eb, 0x7ee03d70,
+ 0x3ccfbe5b, 0x871de9b3, 0xdc59df84, 0xe3685b42, 0xbc59bbab, 0x3b17ee00,
+ 0x399af7b2, 0xabbc8a5f, 0x9047c596, 0xfd394f30, 0xdfc1ab16, 0x5bfb4b3d,
+ 0x06e4d47c, 0x2ade2eba, 0x8b5c0297, 0xfef5beb6, 0x458f4a38, 0x29f4d5db,
+ 0x29761a6c, 0x01f7dd6e, 0xe8c6e6bf, 0x2de3be51, 0xcfe07f86, 0x165d18d4,
+ 0x832b7f6d, 0x8f8f6d0c, 0x71bdfa22, 0x84fa0248, 0x5de47d18, 0x3f0230ff,
+ 0x2247be7c, 0x6fa94710, 0x3a41780f, 0xe9453a72, 0xa3e7aba6, 0x263d01f4,
+ 0xe0ed03e8, 0xdebe967e, 0xa4dd7c27, 0x5df88cfc, 0x0dc981f0, 0xeaf05ef3,
+ 0xff001c4f, 0xf192a549, 0x640f73f5, 0x40b4fac0, 0x3138640d, 0xfc17df65,
+ 0xfe70dff6, 0xb7fddff3, 0xf2f3820c, 0xb17e60f4, 0xd7980f40, 0x16b7f5dc,
+ 0xc479f7c3, 0xe0b77c8b, 0x9a678a39, 0x9290a97e, 0x62e409ed, 0xffad89a5,
+ 0xe1305f27, 0x8049fab9, 0x7815c28f, 0xe0f6e64f, 0xffb75c52, 0xbfbe7a2d,
+ 0x725ff30c, 0x24c3b9be, 0xd6a869e2, 0xd3d7e38f, 0x83ba7957, 0xe9b7cf3f,
+ 0x8fa006a1, 0xeee4eefc, 0x4a0f288d, 0xba43e380, 0x822ffb4c, 0x5d1f8cef,
+ 0x5107f08a, 0x506be9bd, 0xb161963d, 0xf1f396f1, 0xcb93dae2, 0x15b70839,
+ 0x664f6fce, 0xbef7f624, 0xfe9ee5ca, 0xc9ec6835, 0x79337c98, 0xf230f4df,
+ 0xdcc385d1, 0x1f72101e, 0x7ac12b2c, 0xbba46a0d, 0xfd87b583, 0xef704545,
+ 0x7c3fb074, 0x4dbd74b5, 0x549bd724, 0x72dad72e, 0x6e1427c1, 0xc122ec05,
+ 0xfc79272f, 0xce1fcc39, 0x493de761, 0x0badc5db, 0xd1cf183e, 0xaf213fbe,
+ 0xf83eb9f3, 0xfe56934f, 0x096efac9, 0x3b7a28fd, 0xaa7cbda5, 0x545f9f28,
+ 0xc7ff7bef, 0x08be3e54, 0xe9d4f909, 0x2e7c9d4b, 0x7cb12d78, 0x6efa117e,
+ 0xd2aff9f2, 0xd03bf39f, 0xf8759b9f, 0xfbdd0b6b, 0xc7576efc, 0xbfebd478,
+ 0x8fce7042, 0xd907a44a, 0x3fe7ac3a, 0xafe577c1, 0xf60de92c, 0x04df9448,
+ 0x8b7e725f, 0xbbe0a3f1, 0xed3faf2b, 0xc73813f4, 0xaf303ec0, 0x15fb089b,
+ 0x179d9bb3, 0xf986735c, 0xd923cd1d, 0x3ac0697e, 0x1aeff305, 0x0ec0a39c,
+ 0xd77e3a98, 0x8e93f717, 0x4e87e7f9, 0xcc59f977, 0xfda41d7c, 0x9e257c10,
+ 0x0cc3a38e, 0x1221df4e, 0x3afb83ec, 0xdfef1c8f, 0xbc9999b6, 0xb5e8faef,
+ 0x4167c03c, 0xc66490cb, 0xdeb8d95f, 0x5b6abf09, 0xfa0c95c0, 0x17dc2db4,
+ 0x0eda90e3, 0xee8949ca, 0xe9c4bf5b, 0xb7b70afb, 0x2a91365a, 0x488fe219,
+ 0x8111da2b, 0x2f8c664d, 0x8afbb7d3, 0x8befc5eb, 0xe03fa00f, 0x634b25e3,
+ 0xb33f2271, 0xea77cf99, 0x5d1b5f9b, 0x8506be54, 0x3f601837, 0x41936830,
+ 0xe6688f1b, 0x724b9d7c, 0xbea7af81, 0x891a4969, 0xdbb2b4e7, 0x3e1c7202,
+ 0x8826f467, 0x1fcfd223, 0x6b7b07fa, 0x1f9d9994, 0xee86a1bc, 0x676bfbc5,
+ 0x23f604cd, 0x45aac675, 0xb6cce089, 0x4eeb3830, 0x50fcba30, 0xb1682978,
+ 0x7ce10a47, 0xfbe11379, 0x099d3d1b, 0x216f4fdb, 0x16d4de78, 0x9abe5996,
+ 0x5051939d, 0xed009d1e, 0xe35ed12e, 0xda9af3e4, 0x3dc0afed, 0xe4b08abb,
+ 0x9e704834, 0xe37468db, 0x83229e7a, 0x12e11b1e, 0x439dedf7, 0xdff1c7a7,
+ 0x7882b328, 0x8dee37d9, 0xe72f013b, 0x9c0918cf, 0xb7f67b93, 0x3bfd603a,
+ 0x7e43ce1f, 0x9467cfd3, 0x97e1a5d9, 0x71327e1d, 0x5e3edc52, 0x45f1cf4f,
+ 0xcf009ede, 0xe6ab6a90, 0xe35354fb, 0xfc027772, 0x1fa598d7, 0x9abb1f84,
+ 0x0f8e5976, 0xe2f6390b, 0xff6882f9, 0xee397b40, 0x978e489e, 0x077570ad,
+ 0xefab2c3c, 0xbaf01ddb, 0x6ed4bfec, 0xab6bf889, 0x6d1fc59f, 0x400a7783,
+ 0x1ca86b8e, 0xe3938f0f, 0x39c72a1a, 0xccf9dbed, 0x6f1cac3f, 0x644e3905,
+ 0x08fa7187, 0x3e161e39, 0xac3c7286, 0xf35f7b46, 0x2f3f337e, 0xa58e50e9,
+ 0x1c59d36e, 0x4096db8b, 0x881e036f, 0x5201e191, 0x79e40718, 0xe794b7db,
+ 0xef061641, 0x979e4abf, 0xbe3c24ed, 0x266f4f44, 0xa8eacbcf, 0x77404b3c,
+ 0xeacbcf26, 0xd3d78b09, 0x7680f1c9, 0x57dacc72, 0x5f7b5844, 0xefafce6d,
+ 0x7ae5e3a2, 0x60883754, 0x47ae4c6e, 0xb6f5cbc5, 0xe0fae48e, 0xa45ae595,
+ 0x533cb93b, 0x4ee3edb9, 0x58775740, 0xc6f2e71b, 0x3bd593d8, 0x28ff2f80,
+ 0xc176afbb, 0xdbeccc7a, 0x727b1eff, 0x29c5f024, 0x381fcf0e, 0x03fb34df,
+ 0xb8f17fd8, 0x2a9ed067, 0x34f55fda, 0xd92df79c, 0x8bd012a4, 0xd0c73515,
+ 0xc3efd29e, 0xdfa57d85, 0xd23d0b8f, 0xdfcb9c59, 0x7265f8f8, 0xfe4bc223,
+ 0x223be324, 0xadfff9fa, 0x560f3823, 0x5eef0fbd, 0xf33b3808, 0xe8798813,
+ 0xd0f312e1, 0x9089f7c3, 0x0f241197, 0x8f1443fc, 0x3f812f28, 0xacdf78c8,
+ 0xcd6ae0b4, 0x719f2b3b, 0x555793bd, 0x9e6e0450, 0x72bf7e32, 0x07a5bade,
+ 0xa8c3dee0, 0x305cae23, 0x338fc7ab, 0xf55f6179, 0xe515a592, 0xd325d059,
+ 0x12fbb0a2, 0xe8de3e5c, 0xfc085959, 0x9c95abe6, 0x22f8feb0, 0x32bbe35f,
+ 0xaaf99efb, 0x6168f818, 0x2134e4bd, 0xc2339e1f, 0xae98af7e, 0x794fc0c3,
+ 0x8fb873e1, 0x205f585b, 0x7585fb43, 0xa2043e12, 0xd3a08fc7, 0xca4f8db7,
+ 0x056df0e0, 0x6700edf8, 0x38df5b2b, 0xa7dca27c, 0x17f03404, 0xc1f17b3d,
+ 0x0bb7062c, 0xef015d4c, 0xb3bc28a8, 0x07579c64, 0x14e1eaf0, 0xde0cef78,
+ 0x8e968b4c, 0xde709a7f, 0x70d8fe88, 0x37f6974a, 0xe7cfd6df, 0x4fb80d23,
+ 0x4abefe13, 0x866c9bd9, 0x1b4bae7d, 0x2b484c4f, 0x00ff45c6, 0xee6c3ffd,
+ 0x51ff71d6, 0xf1d83abf, 0xa8ef6720, 0x965f3fb8, 0xf70eeae4, 0xaa82ef82,
+ 0xbcd33f74, 0x7a8014dd, 0x7e4dfe62, 0xde1fbb8f, 0xf4c12a1b, 0xddd4bfb4,
+ 0x7d4e2e2f, 0xd9e733de, 0x8200d4f9, 0x49cd1f71, 0xca277fcc, 0x88c8b06f,
+ 0x3f381bbf, 0xfe1a562c, 0x4bd821f9, 0x01f21a9b, 0x3c4ba6ae, 0x2992e46e,
+ 0x6cd6f9e1, 0x6bdc4ede, 0xa4e007bc, 0x7d7b337c, 0xfb16714a, 0xce7b9e37,
+ 0x07bdb3e4, 0xfdd237ee, 0xc234378d, 0xfd48fe08, 0xc4b9be7d, 0xfbd37883,
+ 0x4792e71d, 0xf7a51f70, 0x9529363b, 0xdaafb846, 0x81225eb4, 0x36f8fc04,
+ 0x7f0063c4, 0xdf87e074, 0x8424316a, 0xdbb823bf, 0x91ac3fdd, 0x87af2fd0,
+ 0x15a6fe77, 0xebb5c20f, 0x3cd9ebd9, 0xf94bf9db, 0xf4bcc53c, 0xebc69370,
+ 0xb8bafc48, 0x4feecc30, 0xb3223c57, 0x8dc79075, 0x7c057808, 0xb462f2c5,
+ 0xc9d65a77, 0xcddb6fa8, 0x107c1023, 0xb3dd09ee, 0xa2af725a, 0x676a2aed,
+ 0xf7f9054d, 0x2fe0fad2, 0xe088f96d, 0x46b2d9fa, 0xf53e020a, 0x6efb15f3,
+ 0x6f796f11, 0x1a663e58, 0x801ce896, 0xa50e65d1, 0x773b9c0b, 0xfaf6bf44,
+ 0x2fddc0a3, 0x8483be3e, 0x30bf5f70, 0x9fbb8378, 0x69947f46, 0x3fa141f2,
+ 0x674139f8, 0x132a44f2, 0x3f2115eb, 0x7c849e42, 0x17c60dbd, 0xc12a15c4,
+ 0x80395903, 0x3f50c7b7, 0x437b23dd, 0x781f1e16, 0x99f3e007, 0x83ee3cf3,
+ 0xa30c69e3, 0x0a795ccf, 0x8f48ef7e, 0xce683c51, 0xb45b7609, 0x3bef8a7e,
+ 0x210f311f, 0x7a7e6207, 0xbfe3d039, 0xdf47bc33, 0xc06eeb19, 0x32ce5475,
+ 0x7e06be54, 0x1d34ded7, 0x5b966602, 0xaad3459e, 0x6cf289a2, 0xa654869a,
+ 0xe606427f, 0x7fe3130f, 0x6917c7c4, 0x03f4b596, 0xfc07c40b, 0x86df21a9,
+ 0xf0bd2ce7, 0xa5c7153c, 0x792558f8, 0x817dd808, 0xf3ae08b7, 0x1f64e9b9,
+ 0x3c46d9e0, 0x54ae4063, 0x5bf72a6b, 0xfa59f8b2, 0x1ba90597, 0xeef8edf6,
+ 0x824cffd4, 0x136dd8f5, 0x81266ff9, 0x364eec9d, 0xfe12f7f0, 0x79ddf2c9,
+ 0xf9665c9e, 0x997e512c, 0xdbcdefb5, 0xf3193213, 0xcd394583, 0xa2e1fd43,
+ 0x0879625c, 0xcae5a4f8, 0xbc32695a, 0x9d5aa563, 0xed597fcc, 0xae7c0c19,
+ 0x49bed818, 0x7188d379, 0x5e1e226e, 0xdeb0bab5, 0x5f0a2b83, 0x509c41b1,
+ 0xf705c7a1, 0x58c12b18, 0xd3ddf6e9, 0xb21e9c55, 0x2def80cd, 0xb3740a40,
+ 0x8d79d95b, 0xf1a927a0, 0x6afb860c, 0x0c19e424, 0x56598971, 0xe295b26f,
+ 0xc350ef37, 0x9a839044, 0x07c83ef7, 0x0ee80b3b, 0x821de4fd, 0xfd2868b7,
+ 0x21b55d76, 0xcb37ae3e, 0xed0e905a, 0x9cf0f928, 0x66dc788a, 0xe6af1f46,
+ 0x39725efc, 0xe0b95dc9, 0xf79ed35a, 0x5d2140d6, 0xa52df307, 0xe90fd0d9,
+ 0xd0fd4115, 0xcbf8d852, 0x4e7839b1, 0x7f1ac7dd, 0xe7606d4e, 0xb521a4f6,
+ 0x7184764b, 0x2f187dd8, 0x7b559a97, 0x03c63664, 0x973ed098, 0x83f41e3c,
+ 0xacdb88da, 0x89b6fed0, 0x926e7c7b, 0xf1e0c819, 0x7b060611, 0x5cec7e7a,
+ 0x329c4ddb, 0xcf0b9f8c, 0xd205f4fb, 0x4f9a6296, 0xc5483682, 0x77ea5b3c,
+ 0xa31c3be1, 0x9b5e2c6d, 0xee093ff6, 0x616e3e0d, 0xb7984fef, 0xb9fc4f10,
+ 0xb32b4cd7, 0x54dad763, 0x1aab73e4, 0xb6f405ba, 0x82711cf5, 0xf782a6de,
+ 0x3c438c23, 0x57102060, 0x741aa2f0, 0xeb5c3c42, 0x02f5c540, 0xce796e2d,
+ 0x2d38c0a8, 0xbfa2fe9c, 0x81ae8dc7, 0x2bf1d710, 0x58bfcb1b, 0x5a13e2c0,
+ 0x2106373f, 0xcb35352e, 0xbf1f195c, 0xd6cac332, 0x85491dff, 0xfd6958b7,
+ 0x2d73aa57, 0x7aa10fc0, 0x47fe812b, 0x448ca1ef, 0x726a90e9, 0x527e852e,
+ 0x72f853cf, 0x14807e70, 0x446ba70a, 0xb8f3c532, 0x782eed1b, 0xf77e88cf,
+ 0xb45f5e00, 0x39046e84, 0xc06add68, 0x8cdbc87b, 0x6fc832ee, 0x5739736b,
+ 0x42727cc1, 0x56cf9c56, 0x9b67ce03, 0x32d075b5, 0x01daf70a, 0x3146be2c,
+ 0x8296ba14, 0xc511b1fe, 0x6f9bfb4c, 0x31457a65, 0xacdca014, 0xbe7d32b3,
+ 0xebe4c0da, 0x9b8e8971, 0xd0ffbb1b, 0xa7f6cad2, 0xc837a6dd, 0x996b1740,
+ 0x91128fb8, 0x009e0ec1, 0xf1d0790f, 0xa0d5d827, 0xce339f8b, 0x489f74a2,
+ 0x76073f08, 0xfb4f1e1f, 0x095767d9, 0x47e26bcc, 0x4bde318b, 0xc75e71c4,
+ 0xd25ae3f9, 0xbd699b28, 0x77122f6b, 0xad9bf604, 0x4e1049ce, 0x6d45dd71,
+ 0xf121567c, 0x071e3c28, 0x7cc995d7, 0x5da2029c, 0x3ac3273f, 0x3229c74b,
+ 0xb53bbeeb, 0x7cad07f9, 0xd926c97d, 0x90ccfeec, 0x2fdd7067, 0xefe3ba31,
+ 0xbc78887d, 0x5fcf76ed, 0xd039ae21, 0xfb4492a0, 0xcefe913f, 0xfee2d74f,
+ 0xd17e5f74, 0x8377f18a, 0xe00555d6, 0xfd41c49d, 0xef943f58, 0x93bf78ec,
+ 0x95e81df2, 0x4f4b9e6b, 0x2c61f583, 0x152237d7, 0xe47c067c, 0xe47c664c,
+ 0xbb931e1c, 0xa41cd68d, 0xb41bf01f, 0x5bb2f217, 0xc899de0d, 0x73f9419f,
+ 0xed85e823, 0xf5a71676, 0x19e61e8b, 0x9c624f20, 0xf5ff9c13, 0x962b83e9,
+ 0xde6155ed, 0x6675b25f, 0xc68bcf52, 0x543938c6, 0x7caf8c1d, 0x5369aaae,
+ 0x57634fc1, 0x83257cf1, 0x7f04bffb, 0xb66abe08, 0x7a34e2c7, 0x514bf1c4,
+ 0x5f719fdd, 0x2125f455, 0x7e389cce, 0xe09bf6e1, 0x08818997, 0x244eb5c6,
+ 0xb82b7ecc, 0xef4052e0, 0x33a5f9e8, 0x2900813e, 0xe55dbbd0, 0x6e564397,
+ 0xe5f9455f, 0xeb9f8392, 0x7964f869, 0x2bf7517d, 0x396a49f9, 0x3e54747f,
+ 0x5df4c6d6, 0x9e2b33e8, 0xb26e8e57, 0x1cbefbb2, 0x982775cf, 0x30aed97e,
+ 0x6c3db27d, 0xddb27d42, 0xb9e2f5ee, 0xf3f32666, 0x08dbc511, 0x9eee4ef1,
+ 0x38dad766, 0xf5c4dd7e, 0xd08d4840, 0xffad3d1d, 0x63ae8c5f, 0x9b85ca6e,
+ 0x1cc7a499, 0x4f23d726, 0xbbc03719, 0x0ad84f6f, 0xe6bd00be, 0x82b95904,
+ 0x8277d09f, 0x38ae5bdd, 0xb77d4461, 0xc5bbcf6b, 0xf0540f60, 0xbbd18e78,
+ 0x1c2e2ddf, 0xbe30fd02, 0x97f38afa, 0x4c058fc8, 0xda2bfbe2, 0x12c68277,
+ 0x276e97a6, 0x6711d52e, 0x81f78bcf, 0x864f814a, 0xf463d7c5, 0xcfeef76c,
+ 0x2007d289, 0x61fa703c, 0xd30fbe2f, 0x4b39fbd9, 0x6005715e, 0x9df6719f,
+ 0xe2ae1188, 0x06eed913, 0x77dfebbc, 0x1c78b7c9, 0x346b8836, 0xfa660e56,
+ 0xf02fb2a9, 0xfc339095, 0xfd0cf8a3, 0x6b0bc06d, 0xdb80ece3, 0x711fbcf9,
+ 0xba3cec2b, 0xf88418d1, 0x6b0947fd, 0x21c4ec27, 0xb9e72636, 0x13bd5fcb,
+ 0xe05bcee0, 0xe7da78c1, 0xfefc6492, 0xf731122b, 0x15ba3a05, 0x54854bf4,
+ 0x2949d157, 0xa5288f56, 0xb4ffc003, 0x0f359bbb, 0xe6c27fc6, 0x12f00e1d,
+ 0xb420f5a5, 0x372e3d1b, 0x7db3f40f, 0xe434eac4, 0x85370e2b, 0x3db364ab,
+ 0xab808706, 0xa7e98d97, 0x86b36c27, 0x76b146db, 0x8f6a7fa0, 0x09bd9935,
+ 0x3f9e8ef4, 0x18e7f542, 0x09f1c45f, 0x4f8c45f0, 0x179099a4, 0xd3cf19f8,
+ 0xf3efffdb, 0x57c034c9, 0x05e69d9c, 0xb93ef83a, 0x51c59fd4, 0xd1d0b8b1,
+ 0x187dbe32, 0xce6cc38d, 0x79c3742c, 0x1f8f4566, 0xecf94a63, 0xde811ffc,
+ 0xc67bd87b, 0x7813bec2, 0x6017249e, 0xc1236ebf, 0x8f641efb, 0xf969fb05,
+ 0x21f6535b, 0xa1dfcfa8, 0xef8d89fb, 0x6829bc0f, 0xefe0ee77, 0x48888f21,
+ 0xa08e9768, 0xa95dcccb, 0xd2466f60, 0xec8efbd8, 0xe39b893e, 0xc4db35fb,
+ 0xd73b802c, 0xe02fa136, 0xcb01f5e9, 0xee2581df, 0x760b9ef5, 0x26f8a26c,
+ 0xf704924d, 0x2e2441dc, 0x4cfed167, 0xae702253, 0x012dec2b, 0xfb9fd087,
+ 0x6d2bbf78, 0xe75d3f4c, 0xa0eee761, 0xaa0e01f7, 0x528dc3c7, 0x6eb10e0c,
+ 0x0d4895ec, 0x06050dd8, 0x5b117a4f, 0xbd7ef057, 0x70ddb914, 0xebacea99,
+ 0xe74a5c60, 0x05116e96, 0xbfeb5ee3, 0xd07f06ce, 0x47dbf094, 0x22299e00,
+ 0x8dadd6ee, 0xdddbd5bb, 0xfb126ec2, 0x293f6111, 0x5f608274, 0xef85bd81,
+ 0x8a7df0ff, 0x3757bf93, 0x3f466221, 0xae6de3fc, 0x0fae1e81, 0x14ff0a14,
+ 0x74b93f0e, 0x8a04f2f9, 0xfc44a9ff, 0x8e2c2ab5, 0x6e5d2099, 0x6fce9482,
+ 0xb11241ca, 0x726f3852, 0x1c78e44b, 0x463cdd5f, 0x89bf879b, 0x3afeb119,
+ 0xd397afab, 0x62b912f1, 0x4db7fbfc, 0xf9d9fa0f, 0xecfc1fd8, 0x1f5c63fc,
+ 0x8180a039, 0x3b07a637, 0xe6ebe0f7, 0xf75b2341, 0xceffedf4, 0xa19c7ee5,
+ 0x81f81871, 0x06feeef7, 0x7737ddd7, 0xd83ef37f, 0x573f6397, 0xc769f808,
+ 0x19323e7d, 0x3263a5fd, 0xe8851ef1, 0x8d59f7d7, 0xc8efb08d, 0xbe3de237,
+ 0x0f1e1403, 0xe67d93bc, 0x9fa027f1, 0x7998270b, 0xc66fd079, 0x62fc62ef,
+ 0xf81fb7a3, 0x7bf98bdd, 0x6624078e, 0x03f28967, 0x46b45dfc, 0xcfe117ae,
+ 0xd25f4f14, 0x94467680, 0x3e4aa77e, 0x11d01257, 0xfe0b8efe, 0xe4fdc2bb,
+ 0xce7152ce, 0x46f1c6d4, 0xf3c51df6, 0x966bebb6, 0x5fc7602a, 0x4f13299f,
+ 0xb837b8dc, 0xe713c46c, 0xa6dcf8ef, 0xbec873b5, 0x0a989e97, 0x3243f1fe,
+ 0x85f2ed5e, 0x0c33bfb7, 0xc2720df2, 0x578137f3, 0xc3ebc781, 0xfbe0154b,
+ 0x17267669, 0x6e3f8d9d, 0xe18fe510, 0xecc26f40, 0xe5097cc5, 0x37d74f47,
+ 0x8d26ff77, 0x7c1a5fdb, 0x816f4477, 0x37874177, 0x032614ce, 0x83a33a3e,
+ 0xd0f74f9e, 0xbce805f9, 0x017e7422, 0xe9bdc76a, 0xbf7e6277, 0x82f3133f,
+ 0x1bf57d3f, 0x140ec0d3, 0x8d39397c, 0xbad8c9f1, 0x3d88d227, 0xf681a746,
+ 0x1e8bc41c, 0x1b3ed36f, 0x27ca8499, 0x3ee01a40, 0x60e7588d, 0xe546437d,
+ 0xebf5e8f7, 0x5df2eddb, 0xd4796193, 0x5dd36baf, 0x9eb4bab3, 0x92add7e9,
+ 0xa80a5543, 0xb96562a3, 0x6601d6c2, 0xfe780bb7, 0x9d6f4a42, 0x6ba7b52a,
+ 0xe9e9f047, 0x8e5fad3d, 0xe25e109a, 0x4878f955, 0xa03ef147, 0x8eb17e1e,
+ 0x498f3677, 0x9f5f2d76, 0x4fe9353f, 0x6ff012c3, 0x2fac7c47, 0x18a0fa17,
+ 0x34c5c806, 0x34c97600, 0xb3d2067b, 0x7891a2f8, 0x2f5a5ee0, 0x6e34f90b,
+ 0x7a53215d, 0x84fd3f23, 0xf11db7af, 0x0345c553, 0xf8c5a6f1, 0xcc7dad4a,
+ 0xa7557c06, 0x1ce0d954, 0xd97b5aeb, 0x8f8a64aa, 0x4e159f49, 0x46abf3c7,
+ 0xd9d70103, 0x7db9f0e4, 0xf7104fe0, 0x7bc30ba8, 0xf70f808b, 0xbfb80d2b,
+ 0xc840b96a, 0x68767163, 0x0d95786d, 0x74dab1ec, 0x0706fd19, 0xbee68852,
+ 0xe99dab67, 0x6d13da91, 0xca093d53, 0x9a4927fb, 0x9d224afb, 0xc3e93c46,
+ 0x2dde9fc0, 0xc520fd09, 0x8f880c6b, 0xadfb9249, 0xee4bb074, 0xb661ef60,
+ 0x2b7e8fd4, 0x7cdfc29d, 0x93ea0a77, 0x2d0fb5c9, 0x84c25275, 0xdf8791fe,
+ 0xee49675b, 0x62bd6817, 0xc5f31b97, 0xdf707273, 0x699ffa37, 0xf940a6d3,
+ 0xfc1baa0d, 0xc5e5931f, 0x395fdc0a, 0xc2e5299b, 0xd4b772fe, 0x7604c2b8,
+ 0x871b1975, 0xb0690338, 0x4a6f7d3f, 0xc8b588da, 0x757f224b, 0x0a465aee,
+ 0xe76e3eed, 0xfbf0bdf9, 0x956fcb07, 0x64e4fef0, 0xc4091667, 0x1af153f1,
+ 0x8f6a5f4a, 0x5eee12dd, 0x4e3df048, 0xf8e30499, 0x07bf00fa, 0xe2af5adb,
+ 0x96b7033b, 0x2b5048da, 0x37d7281f, 0x35a6be72, 0xa875836f, 0x25fccc2c,
+ 0xd348cfb7, 0xcc252fd4, 0xf572117e, 0x7f7f2e23, 0x9293ad24, 0x5b53ff69,
+ 0x0c430e1b, 0xdf7c8dfe, 0xdd8934bc, 0xaf722253, 0xeee7a051, 0xe06966f0,
+ 0xad00d1fb, 0xd6e4dc7c, 0xa31e6fe6, 0x93e5ebcd, 0xf2357be2, 0x06e4a653,
+ 0xb70adf7c, 0x467f98af, 0x7af41fa3, 0xf3fad6e1, 0x7eff60fb, 0xaf0c4deb,
+ 0xede82f42, 0x289ebd75, 0x02ae340d, 0xa12d2ebe, 0xf004fefb, 0x017d5f7c,
+ 0x2630dfbf, 0x78debdb7, 0x44fdcec7, 0xd8ab9157, 0x09fabfbe, 0xba169be0,
+ 0xf0129a1e, 0x8457588d, 0xca98a01f, 0x3909f031, 0xd7fe8e93, 0x3ca917c9,
+ 0x00fcc5a7, 0xed423d51, 0xfb02770c, 0xafbda4e7, 0x7aa2be46, 0xf9a9fe85,
+ 0x98cedfdf, 0x037550ac, 0xbd8bbf7e, 0xf50f2048, 0x8b1ffa18, 0x2e5342e1,
+ 0x0e7a6f3c, 0x853e3dfd, 0xbd716bee, 0x2f7688dd, 0x35293de8, 0x54840726,
+ 0xaeb177e1, 0x76624ccd, 0x389fd47c, 0x7df8d55d, 0x03147f04, 0xa7ae40de,
+ 0xefefe8cb, 0x71887f2a, 0xa17cd5ff, 0x24a487e7, 0x23f48ebe, 0x0fc2bafd,
+ 0x5f040f82, 0x3f95d7e8, 0x1d41fce8, 0x49d92bad, 0x1def0c19, 0x0d6f2bac,
+ 0xeb7f5150, 0x839b13d7, 0x76f40ff9, 0x9d9db94a, 0xf038dcbb, 0x27d83b56,
+ 0xe0be8533, 0x7f8093eb, 0x17c63af2, 0x56ce356f, 0x07c9bce0, 0x4f139ef2,
+ 0x15f7e677, 0x86b1587c, 0xf293dfa0, 0xd74013c3, 0x78a92777, 0x9f5cd9fe,
+ 0xeb09c932, 0x7bf604d2, 0x9eb85342, 0x55ef0a2a, 0x73ebffc0, 0x9d057eb3,
+ 0xe1fce26f, 0xa9c47ee1, 0x88fd091e, 0xfc14f4ed, 0x5cdf9683, 0x39230522,
+ 0xe34f3a31, 0x6c7af5ed, 0xed873f1a, 0x1be85dec, 0x937b9d05, 0x7b4affde,
+ 0xe84e8ee1, 0xe9ebda2a, 0x74f6015a, 0x7d92ba02, 0xec05be2c, 0xf5eba06e,
+ 0x77ec1517, 0xfed6924e, 0xf72670b9, 0xe447b857, 0xb1f1f5f5, 0x6674f9fa,
+ 0xec25def7, 0x8bef6e7b, 0x58546f71, 0xeb677fbc, 0xd7af194d, 0x9ff3bad9,
+ 0xbdbf5a49, 0xafd08ba0, 0xf5cef0ed, 0xeb74476f, 0xd7b6ff4c, 0xfba2abbb,
+ 0xff421fbc, 0xbac5fe8a, 0x5eabf420, 0x16778b2f, 0x07bcfbf5, 0x9fd01837,
+ 0x3fdf2d72, 0xe9656b5f, 0x5cec49cb, 0xf8493aaa, 0x5639d97b, 0xf99daf60,
+ 0xa334be83, 0x4901f95f, 0x03c53f46, 0x7fa80ca3, 0x1d18d887, 0x0f251ee9,
+ 0x0f6db3e6, 0x42946fb3, 0xb9c00642, 0x2e764f6c, 0x4a44ad5b, 0x15bbaf51,
+ 0xd7537102, 0x3e3f18d8, 0x4ee066f0, 0xe381e718, 0xd0ab0dfd, 0x00691d0f,
+ 0xae7466bb, 0x295be782, 0xadfa1726, 0x184deb9b, 0xf752d56f, 0x77e17bef,
+ 0x24be5aa8, 0xfb667bf8, 0x73d14deb, 0x1b9e1325, 0x8e21921c, 0x6095a5a2,
+ 0x1984e23c, 0x3fd82291, 0x561a4b5d, 0x9c7cbec1, 0xd79bdd91, 0x926cebd3,
+ 0x3ba3b7b8, 0x7167a867, 0x2c494524, 0x73e3a48e, 0x3c228686, 0xbad85067,
+ 0xd7fd69e2, 0x838c339c, 0xfb47b135, 0x740f86f3, 0xf3a3a7fa, 0x76466d86,
+ 0xaefad52e, 0x264ec04a, 0xfa13d2a7, 0x773b3a6f, 0xf563dba8, 0x8e701cb8,
+ 0xbafbecc8, 0xae3d3d3d, 0x1fd71d61, 0x085ad8d6, 0x6d56db68, 0x09618d58,
+ 0x3d1b1fdc, 0x93e3d3ff, 0xbf8f59e3, 0x127bb082, 0x5b0a63ec, 0xdfbf114b,
+ 0x9c469cf7, 0xb26b6f63, 0xdd6f807a, 0xb03be726, 0x7ee09ffe, 0x6d13bab9,
+ 0xdb8bd056, 0x007a7a9a, 0x8b5f3d1e, 0xb88fdb73, 0xdf9c4f7f, 0x73b30b6e,
+ 0xb30fb817, 0xb7bdea9f, 0x5c6237ab, 0x8f97d9e0, 0xa2d0fc61, 0x06626437,
+ 0x12756d7f, 0x341c9fbf, 0x5e5fbac2, 0x35b9e323, 0x69fc8395, 0x42b6f171,
+ 0xc6da2c8f, 0x7f2ce3de, 0x429c14cd, 0xfebf97db, 0xbf8830e9, 0x7ad95e6f,
+ 0x201f7e00, 0x7ec4b2f0, 0x38d02eb7, 0x2e53de0c, 0xc9fb1257, 0xa1f3f1fa,
+ 0x19b67533, 0x16c44ef8, 0xe583fbf6, 0x5355dba1, 0xcb2f7edc, 0xb4b8e2a1,
+ 0x2f07d31e, 0x00ee7849, 0xc7bfc5f0, 0x3ff5de2b, 0xe0c492f3, 0xf08355ab,
+ 0x5be5863b, 0xbdc337b6, 0x2623f2be, 0xb6f9afdc, 0x2e77c39c, 0xc56db68b,
+ 0xad5f6138, 0xe96bf64c, 0x2a7fbba7, 0xaa5e2047, 0xf3bd86a2, 0x3f18f34f,
+ 0xf7621155, 0xbdedbe96, 0xeadb459f, 0x14500f5f, 0xa2f1da2e, 0xd3b1d603,
+ 0xf81d9b0d, 0x2b96eeee, 0xf0ec67df, 0x61e854fe, 0x6134e384, 0x776fa972,
+ 0xff774393, 0x3f1a4b6c, 0xc7e48894, 0xf0c7f7c7, 0xd171f8c8, 0x0b7f2fd6,
+ 0xbccf7bf7, 0x016fc5f6, 0x3cffc5de, 0x9f385bff, 0x4e2c7b23, 0x5efa9fd8,
+ 0x8fde0bfe, 0x3be6ed14, 0xf9babed8, 0xf77f17a5, 0x8ec1f82c, 0xcdaa7bb2,
+ 0xe1b327f5, 0xf6f365de, 0xafc033af, 0x327ebcb7, 0x77cb97da, 0x0af33b52,
+ 0x3acd2fe7, 0x1ee8eff9, 0x7d9abeeb, 0x59d700d9, 0x22535f4a, 0x7df8b9fa,
+ 0xb78b10b8, 0xab83de8b, 0x3ae0f766, 0x335c37bd, 0x216be6ed, 0x7546af8e,
+ 0xf4e89a83, 0x4a61dbfe, 0x82dfe1c7, 0xbeecd57e, 0x94f859d9, 0x03dbfee0,
+ 0x3957ae0e, 0x99acbefd, 0x50b3fcfb, 0xe1d69358, 0x1748b7fd, 0x2bee26f0,
+ 0x54f0e2df, 0x5e6e4039, 0x1bef057b, 0xd0a6dd02, 0xfd6f3689, 0x75ee1b32,
+ 0xef5b529f, 0xba0eb8c1, 0xa05f81fe, 0x28affebc, 0xdf3bcd3f, 0xe12d3f45,
+ 0xa39b83f7, 0x3af7e2f3, 0x6df19625, 0xe6f7624a, 0x3ee1fe38, 0xfa6de81d,
+ 0x639fdf9d, 0xc7bfabfc, 0x2f47ee29, 0xbe21f4d9, 0xcbc7a6e3, 0xbfe10edb,
+ 0x1a4bd18e, 0xef478b13, 0x1f024e88, 0xe8c7c04e, 0x89a1fbf8, 0xef462def,
+ 0x893a7311, 0xfbd1a0fb, 0x013f349f, 0x495fd2f3, 0xbcd07d02, 0x6d2bdd81,
+ 0x23bf1356, 0xbe8bee2f, 0x98b3a3a9, 0x21f2477f, 0xfc19d8e8, 0x3b3f16df,
+ 0x57ec2e1c, 0xc655a78f, 0x6d79f7c4, 0x1b6eccc9, 0x491574e1, 0x1edba9b4,
+ 0xd5a843c2, 0xa61e2972, 0xa3be8aad, 0x5bdfc6e2, 0x55efc58b, 0xbf1f1f5e,
+ 0xfcbc9197, 0xc59d80fa, 0xc7a6e5d3, 0x7e7137d6, 0x65c38175, 0x05809133,
+ 0xb8f209df, 0x2ab67fc0, 0xfd86ecc5, 0x7476bb5a, 0xc6e730d9, 0xd4768bda,
+ 0xf5822bac, 0xe08fd4c1, 0x6fd11a7d, 0x3287bf2e, 0x77c46ec4, 0x4f42943c,
+ 0xa3e7bc26, 0x60dd1aa4, 0xbb8bb617, 0x6e54364b, 0x9c37e9a7, 0x3f412f0f,
+ 0xb2b5bf68, 0xb6723fdf, 0x623fdff2, 0x9cb2a4e7, 0x39011adb, 0xfd0923ba,
+ 0xeb57a47f, 0xc2aef0c7, 0xbb0633fb, 0xbc167fd1, 0x57d001e5, 0x255ec965,
+ 0x5473f699, 0xfa357f5a, 0x24deedd3, 0x6bbee758, 0x71fb5dfc, 0xddda1989,
+ 0x8bb59636, 0xb93d371b, 0xecb8fc5b, 0xe2fbf8fe, 0x3c5d6d9d, 0x24fc17a7,
+ 0xefe6bfb0, 0xdd7be1e4, 0x271d9c74, 0xdc87180c, 0x7171656c, 0x2e0dbf62,
+ 0xec671854, 0xfcca571f, 0x79a0209c, 0xbd96ab5f, 0xa0fa3dc7, 0x8ab708b7,
+ 0x56ed890d, 0x18e6fef1, 0x3cb8c412, 0xe35bbbfd, 0xd9d5ddb9, 0x64ee78bb,
+ 0x493d6f2e, 0xac1efe4f, 0xb685fde6, 0xfef07d43, 0x23ddbc10, 0x5d1bbc53,
+ 0x1a931932, 0xaa1afbe3, 0xe5fee167, 0xe61efceb, 0x7bcec3d0, 0x785afe01,
+ 0xe318c41f, 0xfbf0ddab, 0x2728460d, 0xa5ff4133, 0xd47ad878, 0x9b77b2a2,
+ 0xa0356853, 0x33d9aa5b, 0x234ba096, 0x8fff3124, 0xe4ebe70b, 0xcfcd5cff,
+ 0x9de052ed, 0x2fce3a1d, 0x5f8d060d, 0x872e66fb, 0xbb332737, 0x4c7437ea,
+ 0xcd5bf7e0, 0x18455755, 0xbe066f7d, 0x55e0c3ba, 0x352a7de1, 0xff0552bd,
+ 0x5f8c724e, 0xbee9975c, 0xec6de8ed, 0xc6a3e83d, 0x8f4fb9aa, 0x79cbdd8c,
+ 0x9e00e00f, 0xb9e2a731, 0xcb8e0cd6, 0x392b9736, 0xb42f4e25, 0x9ddc45d9,
+ 0xe77f192b, 0xd317dbc2, 0xa1363f23, 0xa8c47a9d, 0xef16238d, 0x53f788a8,
+ 0xa22afbc4, 0x5586c17c, 0x1c3f6049, 0xaf7da019, 0x9f993cab, 0x45142a17,
+ 0x19e3cfc0, 0xfbce8e9e, 0xe3bf0a99, 0xe93f67fc, 0x7ffaef07, 0x6cb9c775,
+ 0xcb6fa503, 0x792fbfbc, 0x6ddf969a, 0x1e0256f4, 0x5e356666, 0xbe78a465,
+ 0x0839fa6b, 0xdf37684f, 0x394f3f6f, 0xc358f780, 0xf9a7dc16, 0x01537fe6,
+ 0xeff909e3, 0x6493be68, 0x27804aef, 0xf04caefa, 0x8a8f7c53, 0xdf5e2494,
+ 0xbc5ffaf5, 0x44f824e3, 0x453abdc4, 0x4f4e809c, 0x6d0af788, 0xc0339a84,
+ 0xfe371ef7, 0x1fd0a69e, 0xc572fb74, 0x272102b8, 0x5e272e6e, 0xdc41e7d8,
+ 0x81b6584d, 0xf94038bc, 0x4b02e4f6, 0x8e438775, 0xcc7b5bc6, 0xdc201454,
+ 0x4f9fca1a, 0xd5faf0fe, 0x55236fb0, 0x93684369, 0x8be81ded, 0x1990123a,
+ 0x8a47929c, 0xcbfb17d7, 0xef58be99, 0x1747055d, 0xf17d6aff, 0xa3b7327a,
+ 0x0dd8beb9, 0x53f0409b, 0xc246ae00, 0x20d6713b, 0xf43f9dff, 0x11fb9843,
+ 0xfc56777c, 0x124d413e, 0x641c8383, 0x63c6d57c, 0x1d3a6626, 0xfd977dec,
+ 0x5f78ae83, 0x01a36471, 0x5b240d1e, 0x8a7ed953, 0xbe8d0c6a, 0x4ac07bda,
+ 0x96d99de0, 0xf006d31a, 0xd385b43b, 0x3f035516, 0xe04658d6, 0xfdfd741c,
+ 0x8d1f724f, 0xe075e67f, 0xce33aa4b, 0x36dd0e1a, 0x45f7f698, 0x43d3cd43,
+ 0xd1befa69, 0xe7f03efb, 0xb6437912, 0x7cafe293, 0xb355f065, 0x83edf30c,
+ 0x0aa1e1fe, 0xedb92809, 0xa3adf7fb, 0x4f27e11f, 0xee11531a, 0xf9bce1a1,
+ 0xd8477f68, 0x245e063c, 0xddaede58, 0x027bebef, 0x8dd2bfff, 0x5f2f0dd9,
+ 0xe8f5841c, 0xbc1c0a38, 0xc29c917e, 0x80682099, 0xbe15f5f5, 0x345f372e,
+ 0x5a1bfa68, 0x78c3205b, 0x6f552243, 0x862eefe2, 0x8fa42e4d, 0xe7d3bd93,
+ 0x3768254b, 0xbdffd4b4, 0x6cd7c43f, 0xcc7eb6b5, 0xd8175ced, 0x156716b9,
+ 0xb6dc7781, 0x40d53f72, 0xff1050ca, 0x718bbe2a, 0x1f193a66, 0x945b7a08,
+ 0xf62d722a, 0x7dc03117, 0x09abd6cf, 0xdb4c0fbe, 0x71ae3871, 0xfb48fac1,
+ 0xad10fbc5, 0x6f3c16f5, 0x32015ffb, 0x80008ac4, 0x0000
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1[] = {
+ 0x00088b1f, 0x00000000, 0x98ed0300, 0xd554707b, 0xfbbfc019, 0x24bbbbd8,
+ 0x245ddcd9, 0x06e1b1a0, 0xe8928092, 0x80c4208e, 0x04206ae4, 0x6768c665,
+ 0x267198fa, 0x9e47911b, 0x76a5b16b, 0x81378cec, 0x274eb55a, 0x2c61db55,
+ 0xcea85ed3, 0x4b389ad8, 0x4982c0dd, 0xa94889ba, 0x061276d3, 0x363a605b,
+ 0x041d8a32, 0x8d1d8976, 0xbefd0e0e, 0xbb25ee73, 0xfd3a809b, 0x6fc0c0f7,
+ 0xfb8f3dcf, 0xbe75ef9d, 0xf4826f73, 0x032f8fbb, 0xf49b8180, 0x55000d97,
+ 0xdb0901ef, 0x3bc8196a, 0x41548024, 0x1f31a4ba, 0x8e016fa0, 0x59ff01b9,
+ 0x46f306be, 0xe3779f80, 0x82801aef, 0xc2c1b51e, 0x4a3d8ab6, 0xc749a008,
+ 0xc8076e45, 0x082ac153, 0xcc80e7f1, 0x7ced39f3, 0xd5ec2e3e, 0x6529eef3,
+ 0xdb1f21cf, 0xc032e970, 0xfc4e8072, 0xe2c4b809, 0x28181283, 0xc7a0eb47,
+ 0xfde9a596, 0xcfdd93d1, 0xf2875f15, 0x1f0c941d, 0xebfc0fb6, 0xc7da11f4,
+ 0xa06f6c59, 0xd80f9c7e, 0xb1ea39df, 0xea9ef8fd, 0xc5ac9484, 0x6fcc7576,
+ 0xee75d81b, 0x95858d17, 0x7b647944, 0xd47ff62f, 0x6248ab1c, 0x523d05fb,
+ 0x6dfca3ae, 0x0456f727, 0xa03b8064, 0xfb8e8767, 0x2443225f, 0xc3cd8c86,
+ 0x267be3f7, 0xedec578e, 0xe997f1c2, 0x7ac02d4f, 0xb0731b1d, 0xdf991d2f,
+ 0x7cea8058, 0x006b7f02, 0x18f84f43, 0xbbbf87fb, 0x7a42a8d0, 0x72b1a9a0,
+ 0x8c175e6a, 0x40354314, 0x74661c37, 0xb56ca79f, 0x2df7c6c1, 0x64d7c77e,
+ 0xd7af8c66, 0x7a9ef665, 0xf4077de7, 0xd91d4ac8, 0x0b5a7c36, 0x8fdfbed0,
+ 0x890e0095, 0xc92146a9, 0x65cbceed, 0x2d071274, 0x69ab68cd, 0xff47c68d,
+ 0x495da603, 0xfad831fb, 0x7123feaf, 0xb33e7373, 0xb442cee7, 0xdf639553,
+ 0x4ef852fe, 0xd3f692ac, 0xfaf34c58, 0x43de8d66, 0xcbf7497a, 0xf34517b0,
+ 0xa4233deb, 0x22c0ff7f, 0x1f76c2c3, 0x76c240ea, 0x536fd07a, 0x7e394dff,
+ 0x7293d7e7, 0x198f8d3e, 0xaa8fc6c0, 0x92b7cd26, 0x52f2ecb3, 0x97b9af6a,
+ 0x77a37dda, 0x65b512eb, 0x00dbabf4, 0x77e9657c, 0x35e3ad81, 0xa01c5c68,
+ 0xafa19621, 0xe4c03d26, 0x217d226d, 0x46042adf, 0xd8b63fb7, 0xfed30c28,
+ 0x37fb8514, 0x21da2bf9, 0xbfccc8a0, 0x1829b4af, 0x9ef9ffb0, 0x80bd4fa5,
+ 0x21a30efe, 0x9b71fc99, 0x4e11fdce, 0xe008bb60, 0x039b1f51, 0xb9aadedb,
+ 0xdae517af, 0xf58537f6, 0x21fc77ef, 0xa1c3f8e1, 0x05627027, 0xd63cc9f9,
+ 0x064bb65e, 0x3b71ed03, 0xdd3d9cd2, 0xf591f15e, 0x2f5c544b, 0x7e0bd275,
+ 0x2a7e2514, 0xb01feefd, 0x6bc87dbd, 0x3c7d3058, 0x09fccd8a, 0xf018b1a0,
+ 0xc7892915, 0x1a6b582b, 0xc5f86bcc, 0x3532b885, 0x07e30cae, 0x4fda961d,
+ 0x160d75ea, 0x9142f3b6, 0xa2dfc9a7, 0x7d251363, 0xf8ffac38, 0xf5045144,
+ 0x25ccd71d, 0x05f107e4, 0xc33635b0, 0x1eea8ffa, 0x23d477a6, 0x0a8f7ff3,
+ 0xbf68bd47, 0x79e450aa, 0x9955ef5a, 0xc07cc3cf, 0xd263ecfc, 0xbbef3e2b,
+ 0xfa5bc79b, 0x79bf703c, 0x0066f625, 0xb7a6a0fd, 0xabbb4c34, 0x4d7f7951,
+ 0xbf26d4a2, 0xee56d501, 0x36ab38c7, 0x92bd3aad, 0x9f1e61f6, 0xeada7687,
+ 0xf1d00de4, 0xb85bb62f, 0xe1eb6099, 0xa0100dd6, 0xd077b738, 0x22bc77ba,
+ 0xbcf89385, 0x1e9cf6c5, 0x99796c77, 0xd9026ffd, 0x6bccea37, 0xc7ad1f1f,
+ 0x4af6d069, 0x3c28b8f6, 0x05b9517b, 0xfd9623a0, 0xe3f48ffc, 0xe44fec0e,
+ 0xae0bd73c, 0x3f87933b, 0x32e4a04a, 0xe28e1eaa, 0xbabfafe6, 0x491dc87d,
+ 0x30791f2f, 0xd6a7f2fe, 0x398ffb75, 0xe289de7e, 0xdbb4bc52, 0x5c636d8a,
+ 0x00ac956c, 0xf9b5ec28, 0x8d8fb8cd, 0x27503ece, 0x61e3e906, 0x9f02af37,
+ 0xb25bb1d7, 0x236f3893, 0xb3f707e9, 0x5f5cd629, 0x3f0ffd8c, 0x2b7f2d9b,
+ 0x42c1a23c, 0x37293f5c, 0x6c02b76b, 0x17fb017e, 0x47adea67, 0x71a2ac6b,
+ 0x775b2f5c, 0xbeb7f767, 0x8ceedd94, 0xdb915748, 0xfe5e6fcc, 0xa98ee5f5,
+ 0x89ce8d49, 0x614a5fb6, 0x8e6dc70b, 0x05834f7f, 0xdae1f7d3, 0x8bf5d5b7,
+ 0x56b34f5e, 0xe7effff8, 0x72df6b82, 0xf63aff28, 0x2bcf229d, 0x9f7c7cdb,
+ 0x271e34fb, 0x83df9813, 0xefedd395, 0x11e63572, 0xbb523cc0, 0x27cf180b,
+ 0x38180e3e, 0x113a352f, 0x81b94600, 0xcbb53cf2, 0x5755e332, 0x5c00ff99,
+ 0xacfb4d9c, 0x36626cfd, 0x525c2f20, 0x2ff6f8d9, 0x6595170e, 0x504f57e4,
+ 0xeed67265, 0x47edd4db, 0x2f7f473d, 0x530c2985, 0xa1183f03, 0x852bd5b6,
+ 0x23ee51cb, 0x5f7f13a3, 0x5499f649, 0x4e297b97, 0xbd983f06, 0xabbde331,
+ 0xfb48d083, 0x6542fdaa, 0xcfb9c7f5, 0xc06ddfd5, 0x3dcd5a85, 0xce5794f5,
+ 0xa35d7a1d, 0x49f54f38, 0x0f9f0f30, 0x66bc8e4d, 0xf6e75ca1, 0x5f24698f,
+ 0x1b4c7c5d, 0x3b5e46bf, 0x12432a3f, 0xd1ed41fb, 0xec6fe500, 0x471b40ff,
+ 0x9ef4be76, 0x4d68fa46, 0xb48f2c48, 0x7d5856ee, 0x01e0e6f0, 0xbd0fd58d,
+ 0xcd2dcc12, 0x7eb0f7ec, 0xcf262cf4, 0xa2ffd887, 0x0f9fe534, 0xfae8fe39,
+ 0x0fafeba7, 0x33667939, 0x80de4f98, 0x36f537e3, 0x6f4e746b, 0x3f666a7c,
+ 0x16d3f374, 0xf536ae27, 0x34b38ee4, 0x1c5a33aa, 0x2bb2dc3f, 0x7f373fbb,
+ 0x0fd106d5, 0xe1f94c97, 0xf9a1f244, 0x27c1c62a, 0xa1f3ad63, 0x8ebeba72,
+ 0xc15579d0, 0x91cec3de, 0x2d45c4ce, 0x25c1f542, 0xff19b4d5, 0x41fa65ab,
+ 0x4dfb907d, 0x6645c0fd, 0xe681fa87, 0x3aeeb435, 0xe926ff18, 0x4780dd69,
+ 0x37acb8a7, 0x0c369c79, 0x244b7c60, 0xfed26c87, 0x4ecf41d6, 0x41d1d7ca,
+ 0x41c3f585, 0x7a672ec9, 0x8b6af9e5, 0x8e2dd7a3, 0xa0a8b71e, 0xd1f9e316,
+ 0x0fa9ec62, 0xa2175419, 0xa779f01e, 0x2ffdbcf3, 0xbf48066f, 0xd6edc00d,
+ 0x5befe310, 0x7b60eb4f, 0x13cf2f7d, 0xf3dc9dae, 0xb2a93521, 0xf65bf47e,
+ 0x6f8b2ffe, 0xcb1f749c, 0x7815473b, 0xf7b7c706, 0xa53deb66, 0x507303a6,
+ 0xecf19d1f, 0x3d040f79, 0xe5b66e2c, 0x11bea5d8, 0x5e492af2, 0x1b36c250,
+ 0xeb4a88fd, 0xcfd02b27, 0x2c24de50, 0x60cc8c2c, 0x9d87972f, 0xaf6dc33a,
+ 0x7aa28745, 0xf9eba628, 0x4a798cc1, 0xad91d788, 0xfd22c541, 0x9e4a5f7f,
+ 0x5d5855a9, 0x86785f7c, 0x4081f8ba, 0x8e20e9e4, 0xd3a5d3ff, 0xe515bb3f,
+ 0x09e7db39, 0xbe0d9d53, 0x87e4153d, 0x6d0c9d3f, 0xf7fc5308, 0x835ec27a,
+ 0x5bae1ef2, 0xb0257548, 0xebda2e3a, 0x8e5ea9b5, 0xa8d63e26, 0xf5bac59e,
+ 0xdd6f5a79, 0x9d4ee940, 0x985213fa, 0x3e5d42f2, 0x9561b3f7, 0xdcf313ef,
+ 0x58ea99dc, 0x9ced7eb7, 0xfb9375e4, 0x671d53bc, 0x80e76c75, 0x3e34fcc4,
+ 0x294959f2, 0xfc1a97ca, 0x7919a4b4, 0xddf7c824, 0x50166c75, 0x94e1753d,
+ 0x5ca2f6d7, 0xe37c1c9f, 0x9fa3d534, 0x23c8f9f4, 0xa59f9eae, 0x3c1e3c9d,
+ 0x1ef445e3, 0x5c768838, 0x4b988c81, 0x61fcd376, 0x5c0cf1af, 0x74177e7d,
+ 0x1bac7ab3, 0x7d523276, 0xd9b7fe42, 0x7bac778d, 0x6223c31e, 0x757e73b3,
+ 0xf249f928, 0x742f376b, 0xfb8d4f54, 0x66f9fa31, 0xc535635c, 0xae4f5801,
+ 0x81e7a694, 0x5a3db2b6, 0x807c8668, 0xb1cec49e, 0xb725fadc, 0xd942516e,
+ 0x1ff789fe, 0xffba06eb, 0x967b409c, 0x7f5b1e92, 0xbc75c6fb, 0xc5fb252e,
+ 0x33f3fc47, 0x1d672bef, 0x75473c7f, 0x2e93e62f, 0x92fa615d, 0x1e389c83,
+ 0xdad75e34, 0x1d76d754, 0x10ecc43b, 0xfcc7cd7d, 0x6116ec88, 0x8cf8e272,
+ 0xe87579f8, 0x9ef4cdc0, 0xae1e188e, 0x124af219, 0x12c94fbf, 0xabf54fbf,
+ 0xefaa01e3, 0x469507a3, 0x39b8867b, 0x3b70fe43, 0x69f98393, 0x9e6fb9da,
+ 0x79ec1a0d, 0xafb700d7, 0xf519c83c, 0x87473b70, 0xdb9ddd79, 0xffde260f,
+ 0x3fe5aeaa, 0x51eecc23, 0x4ff99a4f, 0x72664c74, 0x945d3d61, 0xb45b0e79,
+ 0xbf965cee, 0x07ca02ac, 0x1eacfc27, 0x81b5fcc2, 0x458f5ce4, 0x6ae5c511,
+ 0x5fc3eda9, 0xe93cbe53, 0x7f4d1347, 0x2f2776df, 0x1e63e903, 0x7fdc1555,
+ 0x2f8fa6af, 0xd625fb9c, 0x99085af9, 0x08bcfb1a, 0xfe7583b7, 0xe5c500e9,
+ 0x865fad57, 0xbe2cbd07, 0x0d7c6ea2, 0x0673b0b6, 0x9116444e, 0xb912207e,
+ 0xf6c6f295, 0xec4596a1, 0x759dd4b9, 0x07a2bdff, 0x7dc98078, 0x914ef13e,
+ 0x7c1ef641, 0x3d1808a7, 0x676a7e4c, 0x4373439e, 0x0d491ebc, 0x59bdd9fb,
+ 0x1fdc0582, 0xfd6b2ca0, 0xec5bf8f6, 0x284f6fdc, 0xdc1ea666, 0xfc9c8b79,
+ 0x170e84b8, 0xc93117ca, 0xc7de7664, 0x9d789ed9, 0x89e6d3c9, 0xf5763b31,
+ 0x1f7f787a, 0x8b2105a7, 0x8fa3b7c5, 0xf4ccb61d, 0xee7e81d1, 0x1c75652d,
+ 0xfca75b6b, 0x8e2ccbf6, 0xfbb1154e, 0xa247bf5d, 0xee77187e, 0x37dd4e97,
+ 0xdbc9ff11, 0xc44d1754, 0x7f6006fd, 0x0f96fedd, 0xe773a71f, 0x4e281f94,
+ 0xff23ba3a, 0xf29c36a6, 0x8714cbc2, 0xea91b992, 0xce570be6, 0xe9297371,
+ 0x58d0e3bb, 0xc68aa789, 0x432c568f, 0xc6863bb9, 0x922ad44a, 0x4825fb92,
+ 0x529e98c7, 0x9e069e03, 0xd0564f3f, 0xfd8e8b77, 0x7ba0acff, 0xdfe21da3,
+ 0x7be83a1d, 0x997fee08, 0xb88bbfc6, 0x884dfbfa, 0xc38753c7, 0xaeecc061,
+ 0xaccd4110, 0xf93957e3, 0x94c94c0e, 0x73a77db0, 0xf272aefe, 0xf1eeed5e,
+ 0x747c7e1d, 0xcacd5a67, 0x3d517747, 0x0f953854, 0x78799ceb, 0xe329dbb1,
+ 0xd2554dfe, 0x9dae1ce9, 0x9df27354, 0xd5df92a1, 0x5dc27539, 0xeae79d90,
+ 0x4dedd97c, 0x862bde6e, 0xe8f79662, 0x6feb8a3e, 0x73b1f31b, 0x0a33e62c,
+ 0x4fc433c3, 0xb06df502, 0xd18fbdfb, 0x1f77f7bd, 0xf015659b, 0x1fecc93c,
+ 0xa2f6859f, 0xcde62d7b, 0x3fcb06bd, 0xf2f7994d, 0xf7fe3a1f, 0x43cf10a3,
+ 0xd9847492, 0x328e9647, 0xdbd248fb, 0x8caffb4e, 0x0f45ce57, 0x1764d1d6,
+ 0x9434b9af, 0xce5ddf21, 0x7f89717a, 0xfb95c9b7, 0x37bf1099, 0x573beae6,
+ 0xb7a65f8f, 0x6fefccb8, 0xb6c0cfa9, 0x03159f70, 0xad4f565e, 0x29b604b9,
+ 0xf59773f1, 0x179625fb, 0xc4ba42d6, 0x27b5ed8b, 0x2df940bc, 0xf1b01ef5,
+ 0xfc8503db, 0x71c16f3e, 0x2febb3b2, 0x7cfcaa77, 0xcea4fd74, 0x3d4d1f39,
+ 0x530826b8, 0x7471a47a, 0xce72ae3e, 0xc78a2ec7, 0x900f5e6a, 0xd706a73f,
+ 0xb17d5315, 0x423c216c, 0x9afa4bfe, 0x2fa99f93, 0x6ae2bdfe, 0x713b8afa,
+ 0x43df0ab0, 0xe997e6f5, 0x85c68ead, 0x72fe82be, 0x3a9faefc, 0x5f8a9fae,
+ 0xa0f8fe57, 0xefa669b7, 0x2e474938, 0x8c2d133a, 0x7a396fab, 0x9230bfbb,
+ 0x6dfe7ca4, 0x246fb9fb, 0x5ec73de9, 0xfed6bf2c, 0x7d7887f7, 0x3343c70a,
+ 0xf3732fde, 0x2c86de3d, 0xc86ebdf6, 0xca59f2cb, 0xacc92e93, 0xfc77df37,
+ 0x5a1e056f, 0x2d25b18f, 0xac1bbe85, 0x0ae32484, 0xd20f0f4c, 0x2a921573,
+ 0x23702c15, 0x8ee5ef8b, 0xca3035fc, 0x3486adc6, 0x517809a3, 0x610dde45,
+ 0xf25f6ac6, 0x655b525e, 0xbed0a62c, 0x61c9a856, 0x9eb616e9, 0xf546dea5,
+ 0x833c1ab3, 0x3414a13a, 0xf6a63ed3, 0xb719c2a3, 0x3be850ce, 0x72a7ea35,
+ 0xb92e7efa, 0x3fb931fb, 0xa1e474ae, 0xdbc1e012, 0x0d5fcba6, 0x1aee4c3d,
+ 0xf942afda, 0x96b19c6e, 0x8fb1985e, 0xae2f2495, 0x4870efb7, 0xddd6f3a5,
+ 0x4e904607, 0x0ac94972, 0x57de72f9, 0x84553f97, 0x9bae2047, 0x84b4fa1a,
+ 0xe07d2bce, 0x3d6827cf, 0x437187dd, 0xb9ea9aeb, 0x0592f72b, 0xd6ec7254,
+ 0x6a64ffc9, 0x95f806cf, 0xe7b3aa62, 0x0a0a0a08, 0x0a0a0a0a, 0x0a0a0a0a,
+ 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a,
+ 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a,
+ 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a,
+ 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x0a0a0a0a, 0x660a0a0a, 0xc5357ff2,
+ 0x80006faa, 0x0000
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+static const u32 EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x30000d41, 0x4bb00408, 0x3f040736,
+ 0x845e8953, 0xce74fdac, 0xd8c9d5bb, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db,
+ 0xb6db6db6, 0x6db6db6d, 0xf1fdb6db, 0xbdb1600b, 0x008000cb, 0x00
+ };
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0,
+ 0, 12810);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1,
+ 8192, 3198);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2,
+ 16384, 93);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3,
+ 24576, 93);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4,
+ 32768, 93);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5,
+ 40960, 93);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6,
+ 49152, 93);
+ INIT_GUNZIP_DMAE(CSEM, CSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_CSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7,
+ 57344, 93);
+}
+
+
+{
+static const u32 EVST_XSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE[] = {
+ 0x12ba, 0x7ff8, 0x7ff8, 0x7ff8, 0x1208, 0x584,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x270, 0x2cb, 0x2f9, 0x55d,
+ 0x389, 0x3ca, 0x461, 0x4a8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x355, 0x356, 0x357, 0x358, 0xe3, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0xabc, 0xe14,
+ 0x7ff8, 0x7ff8, 0x1034, 0xebc, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x1e0b, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x24fd, 0x26a4,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x26a4, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x26a4, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x26a4, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x26a4, 0x7ff8, 0x7ff8, 0x7ff8, 0x26a4,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x2de8, 0x7ff8, 0x7ff8, 0x7ff8, 0x2b2e, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x2c36, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x2b2e, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8};
+ INIT_MEM_WR(XSEM, XSEM_REGISTERS_INT_TABLE, COMMON,
+ INIT_HARDWARE, EVST_XSEM_INT_TABLE_COMMON_MEMORY_INIT_HARDWARE,
+ 0X0, 256);
+}
+
+
+{
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0[] = {
+ 0x00088b1f, 0x00000000, 0x7dd50300, 0x4554780b, 0xdbdd7096, 0x7edf6fb7,
+ 0xe2f213a6, 0x04787495, 0x420ec050, 0x26867444, 0x70671660, 0x1047c06c,
+ 0xbccf0ec5, 0x1b0cb23b, 0xc1bb6647, 0x09190128, 0x01604463, 0x6718083b,
+ 0x120a09d1, 0x2c0b4034, 0xece3fcc3, 0xd99dd997, 0x1fcb31f5, 0x98c44185,
+ 0xe30ca8b4, 0x4e75baea, 0xdefba555, 0xc6743c24, 0x9f33fbff, 0x75bdd453,
+ 0x3a9d4eab, 0xad55de75, 0xb2510b10, 0xfe1af909, 0xb6f21326, 0x10990844,
+ 0x5a2e832f, 0x72a4278e, 0x2ab229bf, 0xfba99087, 0xa9c9d1cd, 0x4528deb4,
+ 0x1f2eb42c, 0xcefbe2b6, 0x341eacad, 0x0b793db5, 0x980e4f7d, 0x905a2ec8,
+ 0xa4993691, 0x23567213, 0xad3c6fec, 0xd8b213e7, 0x8d95aaca, 0xb423cc6f,
+ 0x858b497d, 0x67f7e958, 0x507c99f7, 0x8a4bba5f, 0xe5430a10, 0x00ead5c1,
+ 0x8892ffda, 0xd0f56cd4, 0x90fa2efa, 0x67dd2fbe, 0x2efb408a, 0xdfba5b57,
+ 0x90f9c841, 0xc02a3c46, 0xf6f487f7, 0x459484d1, 0xa00e16f6, 0x48f6caed,
+ 0x538e995e, 0x4e8a55b6, 0xa5cf0f1e, 0x51768988, 0x9e2764de, 0xaf860c91,
+ 0xf38b8e09, 0x8e8dba58, 0x4a25fb4b, 0xc277eabd, 0x8f541b78, 0xf39f8e33,
+ 0x238e3721, 0xd02f95ea, 0x5577e871, 0x985e492f, 0x024c9562, 0xcefc74cd,
+ 0xe7a2d683, 0x95bf301c, 0x7133ae6a, 0xc2afc51e, 0x8d22ca3c, 0xe003a16a,
+ 0x8f17546a, 0xde57f78e, 0xd70f4fd4, 0x8119a1a6, 0xf2c6f784, 0x4f10887c,
+ 0x465ebc6e, 0x01d9af88, 0x99d447f0, 0xdfcfe263, 0x9eb8c924, 0xe2264de5,
+ 0x13fde2d1, 0x8d242612, 0x46f11310, 0xd5a4af01, 0xb75c4de9, 0xbafd6e0b,
+ 0xdfe64d2d, 0x7acf01f6, 0x381b0ebe, 0xf0067e9e, 0xe7c932d1, 0xf9d0a95e,
+ 0x6e234d27, 0x6fdf32e9, 0xe6a29330, 0x2f7be65e, 0x3f850310, 0xb7846440,
+ 0x83ee048a, 0x2eae4bb2, 0xbfd3c0a1, 0xce9fa668, 0xbec4b577, 0xb07893bf,
+ 0xaac1eafd, 0xc375d60f, 0x99cff9ed, 0x525cf872, 0xf778bea1, 0xca65da5a,
+ 0xfc011f74, 0xd1b7802a, 0x6c3db2f0, 0x7b9defa2, 0xf5adc792, 0x60afe224,
+ 0x1ae7f431, 0xc7d6eb2f, 0x574dab7d, 0x6296994f, 0x7dc3afc0, 0xa75e7af6,
+ 0xd8e45a70, 0x21286558, 0xa434b253, 0x2a59e5b7, 0xdfe59bee, 0xcf2d7067,
+ 0xb4c24472, 0x707c04fe, 0x81abad33, 0xe0bddc1b, 0x932c8e83, 0x3203284c,
+ 0x7df3d899, 0xd291e01d, 0x97f64141, 0x32d1efb9, 0x9372c728, 0x4d235969,
+ 0x1e3cc309, 0xd2d23c03, 0x30d5226e, 0x2085bb6f, 0xe786ea9e, 0xc04e173f,
+ 0x8a1c9ad3, 0xbf789ca7, 0xf9f4cc6b, 0xc29b2000, 0xf881cfb0, 0xe8527566,
+ 0x567ed1f3, 0x9ec5d0e7, 0x149dd744, 0x68c3c346, 0x33cb397f, 0x4a9abf01,
+ 0x3c2245f7, 0x3467852a, 0x8073f3c2, 0xe03e99e3, 0xea2772d1, 0x290eb1e0,
+ 0xa563c1d1, 0x2478c1c3, 0x9e01a77c, 0x1a3c393b, 0x77259fd6, 0x90da3c22,
+ 0x4ea7841a, 0x783a2525, 0xecf0dd6c, 0xe05e3804, 0x3f03d674, 0xf8f493b9,
+ 0xc7a65219, 0x53f02a8f, 0x88a78064, 0x784363c3, 0x862292f7, 0x613f219f,
+ 0x71d0b1f8, 0x7571e112, 0x00abd7af, 0xc07debcf, 0x55b88da3, 0x15a19f8f,
+ 0x0458fc7a, 0x7806c53c, 0x0e3c398a, 0x2918e784, 0xba19f866, 0x58b1e102,
+ 0xfa6ebdaa, 0xab6d92ca, 0xf0bec08e, 0xd065ffd0, 0xf71d1872, 0x4e8e5a26,
+ 0x213fa421, 0x1043263f, 0xc0b6e5ae, 0xd17f6808, 0x11d5e946, 0xf70b2be7,
+ 0xa33fab14, 0x71e4484d, 0x1547f809, 0x5b0b1bdf, 0x9425bf18, 0xf0a70f1f,
+ 0x7a7cb676, 0xff0a5df1, 0x5e799dc2, 0x33f70793, 0xf88bf681, 0x862682d4,
+ 0x59fc421f, 0xdfc09d33, 0xc6b359fc, 0xf01f2be0, 0x610425a9, 0x160fb1ec,
+ 0xb6cf9bd5, 0x25cfec27, 0xd2f5f49b, 0xe02ebe88, 0xa4ff029e, 0xf94b3f78,
+ 0xf5fca118, 0xa0c7ca7d, 0x1e4cc0fc, 0x86737904, 0x26a239f2, 0xac95c7ee,
+ 0xe1d6c2bd, 0xee3b26ec, 0x1e1b8be3, 0x8050c952, 0x9b914ec3, 0xfc984e30,
+ 0xfb85247e, 0x4ebf3e1e, 0x7c8cd473, 0x0f9cf00c, 0xe7cd8efc, 0x2c791201,
+ 0x60b3f693, 0xac335edd, 0x95ad3dcb, 0xe60b8833, 0x1fdf4fd1, 0x91940df1,
+ 0x3281901f, 0xfb4507e5, 0xd2079836, 0xe645bdca, 0xda13dbf7, 0xebe809cd,
+ 0xf5f44b73, 0x2cc4734e, 0x952f3c83, 0xf71d2348, 0x7bfd6a81, 0x937fce31,
+ 0x1893c414, 0x973a1eef, 0xa55029fe, 0x03bfe90f, 0xd53f066e, 0x82070a07,
+ 0x7920595c, 0xa07cc177, 0xbf5838dd, 0x9f3c2a93, 0xbbd928b7, 0x294f5696,
+ 0x966f27e6, 0x944bc27a, 0x14efec4c, 0x87ed3b97, 0xec793eed, 0x20f1e795,
+ 0x8dde2371, 0xa3583ff0, 0x8d8717af, 0x1feb63f3, 0xefd2996c, 0xcaf3c24c,
+ 0x9dfbdbe6, 0xf293a049, 0x7aba99a6, 0xae8e6469, 0xc54d92fd, 0xea8bf7ba,
+ 0x17ef754b, 0xaba43dd4, 0xd61f8717, 0x66b07fb5, 0x03fdeea5, 0xef746bd5,
+ 0xd06c96e7, 0x3604e7d5, 0x5bdfdaeb, 0x2f7ba8d4, 0x06cd2e1d, 0x06a828bd,
+ 0xbc53fbb2, 0x85b6fc7f, 0x74e290ec, 0x5cfce82c, 0xf3cb1328, 0x2b960f21,
+ 0x7dd29f61, 0x65641f2f, 0x36714770, 0xf7416fec, 0xb3ab981f, 0xe93d1daa,
+ 0x7b0fb8db, 0x08192bd2, 0x3d2fabf2, 0x7e2242a0, 0x125defd8, 0xf9e26393,
+ 0x0907ce19, 0xadfb8559, 0xb1fb6542, 0x05fee5e2, 0xd42a2fb0, 0xa3b56e68,
+ 0xb3497eef, 0x8d28f384, 0x5ba1ddd0, 0xf806a1cf, 0x6f1dff58, 0x2afc7098,
+ 0x83379be0, 0x912fe09e, 0xb1e8fc60, 0x0063d9ac, 0x44a95f1e, 0x349691db,
+ 0xa11d87e4, 0x28cefde9, 0x963f3f80, 0x584542e7, 0xb0050d9e, 0xc12a133c,
+ 0x3550fdf2, 0x1aa1ed96, 0xc2854f2c, 0x5431fe58, 0xa13be587, 0x0adf2c7a,
+ 0x3ff2c26d, 0x3b2c1142, 0xbb2c3e43, 0xcb12d4e9, 0xbc92bd05, 0x1aa0216b,
+ 0xb7ae5493, 0xb09b7d09, 0x6fae52fa, 0xe31785f7, 0x3f89f7ba, 0xb72f9612,
+ 0x5b1b366e, 0x74ea3a0f, 0xdaf9f742, 0xe77aaf51, 0x9042bab3, 0x137b343f,
+ 0x7eeed2f5, 0x62ae2d61, 0xbc80ce5d, 0x98e13d01, 0x8920e509, 0xed9de2be,
+ 0x5d07c44c, 0x4737e023, 0x945d91ec, 0x3c950d7f, 0x80ae5e8c, 0x9f270b97,
+ 0x5d7f0173, 0xcfbb299a, 0xfcf7d8dc, 0xdc739b2a, 0x8278048e, 0x85fafa2d,
+ 0xd33a697a, 0x77493d23, 0x707a018d, 0x830ccfbb, 0x52c4cb75, 0x5334b3f4,
+ 0x07e99f75, 0x1f3822ed, 0xe91927b2, 0xd831da8b, 0x470dafee, 0xe1c4fd5f,
+ 0xd34e47d8, 0x1f3751ef, 0x3efb77da, 0x4cf942e9, 0xb49bfd05, 0x3c822f9a,
+ 0xbeffd1b5, 0x144fb906, 0x837e8bac, 0xe5b0a6cd, 0x47be7806, 0xcefd1e37,
+ 0xf8446c23, 0x53fa6fae, 0x1f4159c8, 0x05bd2594, 0x9d01a41d, 0x7e7add58,
+ 0x07abac9d, 0x75bbfa5b, 0x41fe1bfc, 0x28992bf7, 0x15074029, 0xb52a2a9c,
+ 0x49403576, 0x374e15e6, 0x4ea38a5d, 0x2506f0a2, 0x7ee97ed6, 0xa5f7ca27,
+ 0x189db81b, 0xaf206d26, 0x1de44fe7, 0xcaa1497c, 0x3947f78f, 0x7d699127,
+ 0x7b09af01, 0xac244fed, 0xd0ffbc82, 0x720f9f54, 0x72befe6a, 0xcd65eb94,
+ 0x65e82a8d, 0x3a79131f, 0xc98f9df0, 0x4c6eb9bf, 0xb24dffd0, 0xa82d708a,
+ 0xaa2dcbd3, 0x54eae8e7, 0x17d5d1cf, 0x60e95993, 0x306e2d7f, 0xf50b9553,
+ 0x4ffbdd1e, 0xe1d23725, 0x38fd5212, 0xfbd3f7f0, 0x16e7bc6e, 0x6d81c7c0,
+ 0x9f5a01f9, 0xa40f5f4f, 0xe9acb7fb, 0x93ec2a77, 0x0a5f8d2b, 0x84f5c7ed,
+ 0x98ae38c3, 0x963b0f57, 0x49b2a1e3, 0xe17a45f2, 0xe2596ee7, 0xeccc2072,
+ 0x94ec4b41, 0x88f07c04, 0xe9a0f915, 0xfa0c35b0, 0x15bb7065, 0xfb63abed,
+ 0xd61bbcff, 0x0b59f3ad, 0x597d30b1, 0xdb91bd42, 0xffec1fb7, 0xa6fff6f3,
+ 0x8f803fef, 0xd92fd2e9, 0xbe03db4e, 0x4891d8f6, 0x1a4e5ebb, 0x2c1d284b,
+ 0x8fc8f239, 0x963fd508, 0xdfd0c7d0, 0x44665f92, 0x45bf051e, 0x7d9fab1a,
+ 0x0c247071, 0x9d9785fe, 0x1858d351, 0x23d540f7, 0xed2fee30, 0xcef15404,
+ 0xd76c1623, 0x7e8ccff9, 0x3a3c7e28, 0x9e28947d, 0x00e4fc6e, 0xbde22a9d,
+ 0x89c4b5f4, 0x2fd39f28, 0x96f29ba5, 0x8e959f24, 0xb639b1f3, 0xf61a3bdc,
+ 0x8a3fbe81, 0xd232019f, 0xe8007466, 0xffbd7d6d, 0x2af8ccbe, 0xbdcb2795,
+ 0x6a7b788e, 0xf5662da7, 0xbf4c01fa, 0x3ff6c36c, 0x2e3d9994, 0x97ecf7de,
+ 0xf45dbfb5, 0xfb0fdddb, 0x3bdb8abe, 0x87bd75c6, 0xf4de5bf7, 0xf4de88d5,
+ 0xc7e05ef2, 0x54aaafe7, 0x0af5d130, 0xc08d6cbf, 0xa2b85612, 0xcebd3f68,
+ 0x5b0ae0ed, 0x01bbed14, 0x13d05c7c, 0xf6b44ea0, 0x75bfd097, 0x6ec04ac0,
+ 0xf4e23caa, 0xbe56fac1, 0xffb3e7fa, 0xec779f44, 0x1e817bb7, 0x03fc8f2a,
+ 0x25a57bae, 0xeba24f3a, 0xf54bdb17, 0x63beda27, 0x08b3afef, 0x1cc3a7ed,
+ 0x8cb94acd, 0xd9b2a69f, 0x182fd062, 0xde43e7dc, 0x779e40bb, 0xdff73dd3,
+ 0x597fbf18, 0xd32e582e, 0xbecb0ff6, 0x5e41907f, 0x650afc18, 0x13b36535,
+ 0xa7e885e5, 0x0d7e614c, 0xdf1d7cf1, 0xc6fca237, 0x7441d37c, 0x2915f37c,
+ 0xfae00eb0, 0x03a5b498, 0xfa6aab5f, 0xad550544, 0xd815740c, 0xb84d2797,
+ 0x49e1c42e, 0x8bfe4dea, 0xe2685cf2, 0x25f5056c, 0x1dc1962f, 0x5006b9ef,
+ 0xf4de2ffc, 0xa1f01649, 0xa2d643ae, 0x235fda08, 0xf0c32b67, 0xf1edca39,
+ 0x8dd23b26, 0x8e8caf18, 0xe7c52b57, 0xc571a57f, 0xaefc6278, 0xec6c9fcd,
+ 0xd3f1c1ef, 0xb8e37c61, 0x2e313be2, 0xb45f4b95, 0xb125c827, 0x584a25be,
+ 0x425a7e05, 0x128f5c14, 0x878eab52, 0x9aa9a975, 0xa4b7720d, 0x95b3fbe6,
+ 0x00f6f17e, 0x807fc807, 0xcdaeca03, 0x9e541f92, 0x0d648ee0, 0xce070a4a,
+ 0xa0756c2f, 0xa0f00cdd, 0x454e183e, 0x8c69093b, 0xf14d2bc2, 0xfaa07f22,
+ 0xe1f4962a, 0xe84eb9c4, 0x7f6c4eff, 0xe11ebe52, 0x17ba173e, 0xfa1339c7,
+ 0xe74e7c3b, 0x01ee0b9d, 0x93f85f31, 0xbeabbf69, 0x35f67447, 0xf7e24f21,
+ 0xf70cfaf1, 0x3e956459, 0xdaed35f2, 0xe748f40d, 0xc6c48175, 0xc81f142a,
+ 0x5a0e8166, 0xe0bcfed9, 0xad0bf560, 0xc32fc819, 0x89d9a2a1, 0x726820fb,
+ 0x6ad5bf21, 0x2856cd26, 0x02916f5d, 0xe309c96f, 0x17769e69, 0xf2a483d0,
+ 0xd411277e, 0x4f9fe8f7, 0x5511fca1, 0x126f0a42, 0xe8eb8689, 0x64e53bfc,
+ 0x3953afc4, 0xca8917f1, 0x73a9b0d9, 0xc24f7c22, 0xb53f206f, 0x17f0f6f3,
+ 0xfc1b75a3, 0x5767f683, 0xd3da1448, 0x4b4ed47a, 0x7ce548fb, 0x7a71ff22,
+ 0x89a4f5f5, 0x9f71bafa, 0x7a87be82, 0x886ff712, 0x9fbf6971, 0xccfdfa19,
+ 0x9767efd0, 0x2fe057eb, 0x03f0eda8, 0x0a15581f, 0xf5215d60, 0x4f14feb8,
+ 0x4f01db13, 0x87685c43, 0xa4cdf18b, 0x66f10ffb, 0x6f5cf0e1, 0xaee2fe62,
+ 0x4adf1643, 0x240d33f0, 0x5d3fe08d, 0xf4abfdc9, 0x6848efcf, 0xf21adc4f,
+ 0xbfbbc783, 0x2565fc67, 0xdb3dbfe7, 0xbf18155b, 0x5f6b7b47, 0xb7bd6ded,
+ 0x8f05f677, 0xae7857bd, 0x1d55df95, 0xd4574ff9, 0xdcf7c093, 0xebe58774,
+ 0x26f5def8, 0xf34aa78a, 0xe3b7efd9, 0xc1ea1893, 0x66674e16, 0x2cdd7eb7,
+ 0xd5bafa99, 0xa575f973, 0x4fe8e4eb, 0xe7c451e7, 0x3c54d451, 0xb4d0e403,
+ 0xfec2ccc8, 0xabee5d74, 0x6738bc90, 0x851ffd1f, 0xeb870e6b, 0xf7097abe,
+ 0x4ccb7dc5, 0x8bd48f11, 0x41fe04bf, 0x96adcfdf, 0x57a65122, 0x0e9519ec,
+ 0x8e3626fe, 0xe8229fd1, 0xffde41e5, 0xeb0a423c, 0x87f9bd4c, 0xf3151d18,
+ 0x96fe8c7e, 0x7e8bc4f9, 0xa5dfa319, 0xf5a8894c, 0x7b95e8bd, 0xd7437820,
+ 0x82e00e6d, 0x2f1179e2, 0x4fe5e21f, 0xe58df979, 0x390f6a58, 0x93d708b6,
+ 0xd04101db, 0x45be93ff, 0xfa3d99ff, 0xdaafe87f, 0x18a220ff, 0x7fa7f1e8,
+ 0xf587fed5, 0x298d7f80, 0xc1ff67ad, 0xf79436a4, 0xcc75d064, 0x4872e6ae,
+ 0x042f6df8, 0x9729493c, 0x0b6ccbf1, 0xe1dfa115, 0x2c26d0c5, 0x08f996b3,
+ 0x3eca55e8, 0x637ffa82, 0x8f9f04a8, 0x2d2ed7d9, 0xddc575a0, 0xe5a62d2e,
+ 0x3e0d50ae, 0x6fab521f, 0x479f663f, 0x323ced66, 0x14367bb4, 0x85cf76c0,
+ 0xf5dfd1aa, 0xeb0ea842, 0x58c287cf, 0x2d2036e6, 0x86856510, 0x0e7fc771,
+ 0xda3b63d5, 0xeb2f931f, 0x0970c8b4, 0x72ed65fa, 0x008c4eb7, 0xbcdc543f,
+ 0xeb04a7be, 0xb0450cbf, 0xf276ebbf, 0xea095afe, 0xeecb59f9, 0x3c35f9d3,
+ 0xf4ebe62b, 0x90f70141, 0xbb5d32da, 0xf222fb31, 0x61af3a02, 0xdbea96eb,
+ 0xc43223bb, 0x7e1b730d, 0x723e7ba2, 0xf7dd2aeb, 0xab5cedd7, 0xcf7a3f7b,
+ 0xc7ef75cf, 0xaba2dbee, 0xe8775b7b, 0x0e7d62ea, 0x40938129, 0x0a971557,
+ 0xbd72a108, 0x082fd2fc, 0xe95a11b9, 0x11c995f9, 0x9bf17b43, 0x2133c1d2,
+ 0x356fe21f, 0xcca107b5, 0x1aec7ae4, 0xfad253f0, 0xc4a7e013, 0x57f322b8,
+ 0xaafee7ad, 0xf891a10d, 0x1790a9fc, 0x26874feb, 0xc29e7d62, 0xa1cd8fec,
+ 0x9ffcf8e9, 0x4e7c7e42, 0xf00e21e1, 0x656b3d13, 0xfb2a437a, 0x5a5b6baf,
+ 0x9200ec04, 0x85453f59, 0xf41ce6fa, 0xb434974f, 0x3e97789c, 0xf3d0e0ff,
+ 0xdc79ce8c, 0xbf8894a1, 0x47f6027a, 0x12a5d506, 0x8a5786e3, 0x467b5037,
+ 0x18587f1f, 0x28fc8171, 0x3901f9ad, 0xb47bf14d, 0x3b5739e9, 0xcee97f9d,
+ 0x97776895, 0x0f558454, 0x614f4d94, 0x82a4bb7c, 0x977d8178, 0x6bfe3635,
+ 0xf5771d0e, 0x03691267, 0x5c44a879, 0xe7274754, 0x8254cc9b, 0xa6d6ebc4,
+ 0xd38024e7, 0x56f3fdca, 0xf48a37b7, 0xc3bc4a9d, 0xb67a713d, 0x9c635666,
+ 0x7b11983c, 0xf6b7fa09, 0xa9bc9761, 0xd2556edc, 0x311b7de0, 0x057b678d,
+ 0x46278bf4, 0xfc037d2f, 0x27efe792, 0xe73c4337, 0xe5c02b89, 0xf7c170a4,
+ 0x3b8f6e4e, 0x1d1e3cdd, 0x5de30b87, 0x272b804e, 0xe893970e, 0xb8049bed,
+ 0xe0132906, 0x7f425bbd, 0xf98234e0, 0xd56feb08, 0xe01eb5c3, 0x570df472,
+ 0xfc0b8532, 0x5f1cc926, 0x85f13dc9, 0x0364867e, 0xc6fb92be, 0x57000dd7,
+ 0x664bf132, 0x862ee7e8, 0xe866a7af, 0x0aea7ae1, 0x70a34af8, 0x1c69f7c1,
+ 0xf13d695f, 0x0334f585, 0xc6fad2be, 0xa3ac0157, 0xf1d64836, 0x9b30db0b,
+ 0xef881f8e, 0x4bff101d, 0xe7b19768, 0x3474a921, 0xe807c7c4, 0x1d6fbb9e,
+ 0x4ca7aba2, 0x4f574ebb, 0xd74e319d, 0x935dfa7f, 0xfbccf574, 0x01f5740b,
+ 0xfba07f0b, 0x2cc5507e, 0xfb8cfbdd, 0x1ff02aa3, 0xc1e6afca, 0xed2f2a7c,
+ 0xb8abf1d0, 0x5be7a2bd, 0x0c35665d, 0x31aebe7e, 0x07c3868c, 0x355ecc2d,
+ 0x010bb1f0, 0x3196edc2, 0xfd77188d, 0xe9cf7f23, 0xd195a963, 0x6343d2e9,
+ 0x0afbc076, 0x86f78fbe, 0xbcef909a, 0x3e466a12, 0x82633144, 0xdcfd92fc,
+ 0xf20075ef, 0xf1596826, 0xe409ae66, 0xb56fe758, 0x76bb8822, 0xccb82f5a,
+ 0x190fc063, 0xeb4ddd73, 0x829c6075, 0xe990ae5e, 0xe3e3adbd, 0xac8f8b0a,
+ 0x29c1f83a, 0x41e2e380, 0xe742c7ab, 0xd2b5f531, 0xa7909d07, 0x7ff30ef2,
+ 0xdf7fc5f5, 0x298f0254, 0xcc07ae3c, 0x4fe5eab7, 0x7e3a12c6, 0x13649ede,
+ 0x07bf9ff0, 0x71069106, 0xb02cf6c2, 0xff1dc76b, 0xe3ff0e85, 0xb7597cdf,
+ 0x9bc7793e, 0xf5d16f91, 0x17ba07a8, 0x48e421eb, 0xb8f41f5e, 0x25fee15b,
+ 0xc41e9f23, 0xf001fff0, 0xd564da69, 0xa63b296f, 0xb56f17ef, 0x2e7980ec,
+ 0xc4f2b4de, 0xfef0219a, 0x3d7789c0, 0x4f818608, 0xff3f5047, 0x1bf9fcc6,
+ 0x07413bca, 0x5f9679c6, 0x743c426a, 0xf77b9bd7, 0x30aebe77, 0x7f11833f,
+ 0x2bafaf14, 0xc6687fe8, 0x4bf2a57c, 0x9ef3e12f, 0xfd078476, 0x71e2cb03,
+ 0xf0207559, 0x2e2c039f, 0xb9af2cbb, 0x5ecbea10, 0x0a3ef64c, 0xfafcbfcd,
+ 0x5e82536b, 0x2f826cb9, 0xfc65e963, 0x2c7b155b, 0x7f8bd224, 0xe5640bab,
+ 0xf40ebe24, 0x1f912efb, 0x4336ea21, 0x57da25dd, 0x857c82ad, 0x385fcf20,
+ 0x8414d4a7, 0x95e7ea13, 0x0ef57587, 0x7aba27e5, 0xd608f2a7, 0xadef55af,
+ 0xc4e8fd6c, 0xffae24bb, 0x1cf77d52, 0x7ad187ee, 0x79d84fbb, 0x4accddc4,
+ 0x31e25f3e, 0x5d4335d4, 0xe5bfd431, 0x903fb0f7, 0x17debfef, 0x5bebd2bf,
+ 0x327b4617, 0xde02df60, 0xaa8bdc99, 0x938af780, 0x2ca09213, 0xf4e16baf,
+ 0x23f2c115, 0x4797ef6e, 0x4bcaf3d8, 0xbe90a174, 0x3ffcea56, 0xa4a4c91f,
+ 0xb37c7db7, 0x95ddd999, 0x7aaeffad, 0x467f801c, 0xdf7c95df, 0x88525e57,
+ 0x548bee8f, 0x8ddb05b3, 0xdfb15b30, 0x4898e0f1, 0x3bff65eb, 0xfec57cd8,
+ 0xec12c707, 0xe7360fff, 0x7fee9d60, 0x7ff66af5, 0x6bdf5f25, 0x0337ffdd,
+ 0xb4dfb05c, 0x0fcc5cf6, 0xe718fde4, 0x42ef555d, 0x7a7e513c, 0x4f013983,
+ 0x6f7fb015, 0x6122fd84, 0x8b45639e, 0x9b86f505, 0xbeb61ecd, 0xb01c58fb,
+ 0xb66ed2e2, 0x4e36158f, 0x8c4efb5f, 0xea3fcdd3, 0xa4fc745b, 0xf9e1bf07,
+ 0xf7e7c689, 0xbdbf199a, 0x8c7d2840, 0xfa3e9bee, 0x92f2b7ea, 0xf747074d,
+ 0xb3af777a, 0x3e39d70b, 0xf7e2c69e, 0x3c098f9c, 0x66f8a9be, 0xf88cbe03,
+ 0x10a5e389, 0xfdc9d7f1, 0x21f93d4a, 0xedc5f3f3, 0xea4fb613, 0x9ddd6f42,
+ 0xfad45fe8, 0x38ab3b90, 0x0a1e3ebd, 0x3a4cffa3, 0x3f8376ea, 0x8495a57b,
+ 0x794b4fbf, 0xd3fa115d, 0x9407402c, 0x49925a5f, 0xc4fd2564, 0xa30af902,
+ 0xe266f4e3, 0x451126d4, 0x4d263f47, 0xea95575f, 0x1fb43993, 0x5e6a5075,
+ 0x22fe83d8, 0x99b0fbdd, 0x1fadc5e5, 0xfe0c23b4, 0xb3d53b5f, 0xcae3f3b1,
+ 0x6cf97ec2, 0x7d9fc03b, 0xd74172a4, 0xe63b666f, 0xfabd3a35, 0xf51349e7,
+ 0x9d264b75, 0x9be465e7, 0xac3f31a2, 0x90200e02, 0xee0e9917, 0x1f305567,
+ 0x27973574, 0x4a39c0ab, 0x6cf1ebd7, 0xe34bd719, 0x691b477e, 0x7001d2c6,
+ 0x6245d2d3, 0x0d21ba58, 0x60299694, 0x81b2d0be, 0x72372ffb, 0x168565bf,
+ 0xadd302cb, 0x567812ca, 0xcbfbefa2, 0x1740cd81, 0x8c0e0f1f, 0x35fcc330,
+ 0x259cf905, 0xc9bf8d99, 0xd0f3ce14, 0x629acfe7, 0x165fd079, 0x0a56fc7d,
+ 0xdf21b32b, 0x57109028, 0x78e97163, 0x9eb3d4dd, 0xe218a35d, 0x488e5f4c,
+ 0xecb0ff7c, 0x5278026b, 0xe7284b4f, 0xfea3f9e3, 0x3b4fc824, 0x4e8dd7c2,
+ 0xcfc1f51c, 0x5d98735b, 0x4cfe0579, 0xc7d9a995, 0x0d797075, 0x8fb389f5,
+ 0x8219c427, 0xf6e9a697, 0xf3a04efb, 0x30c4f884, 0x5c4327c5, 0x7d3d7870,
+ 0xfacf93ae, 0x53505e75, 0x83f74e40, 0x0a7b9a38, 0xede13bd8, 0x30582f4c,
+ 0xd27267cd, 0x27549d75, 0xe6ec1c61, 0x5f98ed33, 0x9921a0b1, 0xe0b29d80,
+ 0xe7e855e1, 0xb4f36aaf, 0x8e9f03b4, 0xb4e1de48, 0x943d30c8, 0xee3a53f7,
+ 0x83c947d3, 0xfeacd1fe, 0x7c61c610, 0x7f82471e, 0x9d5cc3b0, 0x85dfa6e7,
+ 0x40f8701f, 0xe5df157e, 0xa6fc1b7b, 0x1be8944b, 0x3cf8d8d2, 0x4cf7ef8a,
+ 0x7178f884, 0xa587d5b3, 0x5d1b1446, 0x688562d7, 0x44a86650, 0xf5bd42b1,
+ 0x7de1cff9, 0xac688d86, 0x80bfebfe, 0x81f054bf, 0x9d549beb, 0x59a63a7e,
+ 0x45a1bf5f, 0xea8bcf5f, 0xd49e37eb, 0x9f4173d7, 0xfebefda1, 0x3d808995,
+ 0x12d17b16, 0xa3aabc81, 0x46c42c87, 0x4bfe55e7, 0x53a5ea2b, 0x3fb81dcb,
+ 0x3585fa3e, 0xde37f502, 0xec1f2d79, 0x3a5fb2dd, 0xdfda3c59, 0x2fbc12fc,
+ 0x0120697f, 0x352af639, 0x37fdb893, 0xabeef816, 0xefc263ff, 0xfed02f63,
+ 0x0e8ffb69, 0x23d2ff3e, 0x5e8ffbf4, 0x79229818, 0x1ecd71e2, 0x1f49befc,
+ 0x49b11c77, 0x88a8ff0f, 0x99566ebe, 0x5f8bf0fd, 0x37af42a8, 0x9999cd7d,
+ 0x45eb9d27, 0xe3d7bc74, 0x03658071, 0x3c0d1e21, 0x79fc487a, 0x37e84939,
+ 0x6538dec1, 0x0b9ffd66, 0x9f613379, 0x2f2ccaa7, 0x58e45cf8, 0x3f2d317a,
+ 0x1d2c79dc, 0x87ce85f2, 0x552e306a, 0x0a5777b1, 0x2f15d7e8, 0x3e81731c,
+ 0xf7673158, 0x2e409393, 0x066a60bc, 0x74f3e838, 0xfcd1de78, 0xf4b9ae2f,
+ 0xfd9db9f9, 0xf65d01c6, 0x234aa725, 0xfb899979, 0xe1e95ae0, 0xecff44c0,
+ 0xcbde283b, 0xdf309ab7, 0x83df3bbf, 0xe6f2c1f3, 0x06387fbb, 0x3356c1f6,
+ 0x7b15e1da, 0x53f604cd, 0xb416f1b0, 0xfcf7cbc3, 0x8321f30e, 0xcf318b9b,
+ 0x7e215f35, 0xad7438d3, 0xb9e505df, 0xf02efdd6, 0x57ff952f, 0x4078aa83,
+ 0x1fafd13f, 0xafcc03a5, 0x7f371ca2, 0x7cb90416, 0xae21f32b, 0x9cf79e29,
+ 0xe37bfeaf, 0x4aa1dcba, 0x64738f22, 0xdb1afae2, 0x46119bf5, 0x66a2ae3b,
+ 0x5cce2e95, 0x055ea671, 0x071c6421, 0x3e04dd8d, 0x7882e945, 0x68bf9f60,
+ 0x493a7115, 0x0f3e93a3, 0xeaca1aff, 0x80cb17c0, 0xd7fe608e, 0x8a1e6991,
+ 0x6459f28f, 0x4c03943a, 0xc9f2f304, 0xdc8e2c2b, 0xfd846141, 0x7ae7b1d0,
+ 0x92edb3cc, 0x13ff77da, 0xbe44eff6, 0xba8ee1d5, 0xd65f1e20, 0xfe78c56a,
+ 0xc8ab1f47, 0x1f365637, 0x641e4173, 0x59564bc7, 0xf7cfa24e, 0xb9302bf6,
+ 0xc37e7e80, 0xfdcd2cfc, 0x65d7540a, 0xdea6a7f4, 0xf1f6f8e3, 0x3af607c4,
+ 0x717b15e8, 0x58a3227d, 0x5928b27e, 0xcc9a613e, 0x1e1da9d6, 0xf15d7f81,
+ 0x827c87f5, 0xe443a58d, 0x88de2cb5, 0x7ea8b2f4, 0x2bd00ec4, 0xfe31769e,
+ 0x3e40e549, 0xd407ade8, 0xc1547f82, 0x7829647f, 0xfac09d58, 0x8490fd07,
+ 0xd47ea1fb, 0xf6dddc17, 0x31976f03, 0xb7af3ab4, 0x2ed1493c, 0x25f86555,
+ 0x7ad8925b, 0x07dc7b51, 0x31bf30f9, 0xf165ae37, 0xb5079622, 0x12b5c98d,
+ 0x9d718f52, 0x835faa0a, 0x2358b27e, 0xb75d1761, 0x493e74c5, 0x77480f2c,
+ 0xb49ca22e, 0xc0d23b61, 0x7e00a9e0, 0x5bfd42ef, 0x6352aed7, 0x698ad771,
+ 0xa174ea24, 0x5f7bae3e, 0x1830ed45, 0xff59b2b7, 0x2335337c, 0xdf6029ac,
+ 0xede9657d, 0x38d24bbc, 0xc063ce5f, 0xf66d7faf, 0x3e40f0ee, 0xf1e9d116,
+ 0x4782a496, 0x9336bf01, 0x485ff88c, 0x6bac14f9, 0x3993c867, 0xf5a5f28c,
+ 0x59c1e4c9, 0xed6fe0bd, 0xa012d66b, 0x59549783, 0xaa951f67, 0xafe7ac66,
+ 0x6c40fa62, 0xc2728a8e, 0xedd12376, 0xc4aafddb, 0xa32209f3, 0x30dd2266,
+ 0xb921ab3b, 0xdb7e0a39, 0x17920d2d, 0xb3e9c4f4, 0xff014a4a, 0xa06c8a17,
+ 0xb085927b, 0x1f8f1426, 0x0396c5a7, 0x5ce62b5e, 0x082d4ddc, 0x1c0e4732,
+ 0xca747981, 0x72c7acb1, 0x024fbf50, 0x88fdfefd, 0xfa53361c, 0x1e361f7f,
+ 0x2756fbc8, 0xaf891fb3, 0xefda22ff, 0x5e1935e9, 0x9e1363f0, 0x20fa714f,
+ 0x9a36afb3, 0x3f9085fd, 0xf4cfde1c, 0x9ecdf783, 0xeb4fc82c, 0xd851abf2,
+ 0xcf640b37, 0x13d01af6, 0xbdf1db0f, 0x27c13f11, 0x32fc6097, 0x47e2b658,
+ 0x2cfb32e4, 0x67dfa2d8, 0x0596249d, 0x3252daf3, 0xf90a39a4, 0xbca3ad53,
+ 0xcc673e40, 0x38f987c4, 0x4f88cc87, 0x39c0188c, 0xbd17ee03, 0x9e61feda,
+ 0xc20cb710, 0x4aaf41bf, 0xafc85fe4, 0x100cfcf4, 0xaf65f985, 0xcebd3065,
+ 0xe7eabef0, 0x83553e7f, 0x22e58bf8, 0xffbc369f, 0xe18becd0, 0x7967adfe,
+ 0x511e74c3, 0x6677f68d, 0x3be513b3, 0x01cf1eed, 0x2ddc862c, 0x0af64fda,
+ 0x362adfb6, 0x3e1c6065, 0x5f6b1a79, 0x0ec469b1, 0xfae24fa8, 0xa91362db,
+ 0x59df60d5, 0xe9469d48, 0xea85817f, 0xcf1eb06f, 0x7b3af5b2, 0xb093f4cf,
+ 0x5afbe8cf, 0xe2615f78, 0xe984f8f9, 0x124d2575, 0x2ac77881, 0xf7e429fb,
+ 0x1243f946, 0xf7953cf9, 0x4d1b9a93, 0x5f008468, 0x2e7f191c, 0xbccf73f6,
+ 0xe8b1ffa7, 0xfc1618f1, 0x89f4c026, 0x3fa01961, 0x4968fd8b, 0x505ba7f2,
+ 0x8032793e, 0x05359e8f, 0x4287bb96, 0x9fcb229e, 0x2c51252c, 0xf23348cb,
+ 0x186fca01, 0xdf18d1df, 0x0bd6d281, 0xed24a9ff, 0xf915ddf8, 0x77ca0ace,
+ 0x3be4f6c6, 0xa1e75484, 0xe1dfbf5c, 0xe4617d85, 0x0ef83d3f, 0x9d6273e7,
+ 0xfc8abea8, 0x088ad269, 0x1e057bfa, 0xc7f8b16e, 0xfbff705b, 0xe3cfd172,
+ 0x054b0df3, 0xe784267a, 0x7d22d4a7, 0xb2ffbf8b, 0xf43e587b, 0xbdfa18e8,
+ 0xf90916a5, 0xa4790f64, 0x3f19f378, 0x30dea2f1, 0xaef4c5d9, 0xc0924fc9,
+ 0x053cb4cb, 0xf7c66eaf, 0x966ed0b9, 0x9305e985, 0x265d6c6d, 0x50eda5af,
+ 0x13efa51f, 0x1da211fc, 0x4e533fb9, 0xbd0a2ff4, 0x3eefb8ce, 0x044993ae,
+ 0x0435f5ec, 0xdff78fcb, 0x5f7a0b94, 0x729bdec7, 0x567bef41, 0xf385dff5,
+ 0xf0b2f9f7, 0xc9939f3c, 0x4a56adbf, 0xb71d74cf, 0x8d6e8c4a, 0x7e9a93f0,
+ 0xe6929e4c, 0xbcbf802c, 0xb39bf84f, 0xbf2fe112, 0x03cff846, 0x29ff54fc,
+ 0x7f9ff0e5, 0xea1640e1, 0x640ebbad, 0xff684fcd, 0x5c7eb751, 0xe415eb8f,
+ 0xc9575ef6, 0xefc41705, 0xe9718b96, 0x9a0f414c, 0xbe77d7cf, 0xe80f7b5f,
+ 0x29ab7e71, 0x685f016a, 0x9d3e6ddd, 0xe629badd, 0xba3ffe62, 0xeff1e9b6,
+ 0x70be4aba, 0x8ae5bf81, 0xcb3a73df, 0xff43682f, 0x8490ec4a, 0x7cdd8c79,
+ 0xa1c58db1, 0x89f0e71f, 0x993b37e7, 0xc5bdfa5c, 0x63f61ab7, 0x469adbc7,
+ 0xcf18fca8, 0xcaa46162, 0xb44888ef, 0xefd82a9f, 0x41586710, 0x49fa412d,
+ 0xe91948d5, 0x2665aab0, 0xe7fc3881, 0x5806c0d6, 0x38efd5df, 0xfdfa26c2,
+ 0x08b391da, 0x2b83e9c4, 0x41becfda, 0x1ad57abb, 0x77de1a78, 0x37decdbe,
+ 0x163f3acc, 0xd7fe50f8, 0x7d3e3e9f, 0x06ebc23c, 0x616a9d79, 0x7c04e0e7,
+ 0xde4c2cc7, 0x116a328a, 0x57ea9472, 0x2259c790, 0x30677e63, 0x029ee7d5,
+ 0x0aadcd7a, 0x4f76a9da, 0x57de0f9b, 0x4d4a63ed, 0x3ea7f0be, 0x61e50832,
+ 0x7929bed5, 0x66f502ff, 0xf3e81e6b, 0x903aeff9, 0x3c3c77ef, 0x761cfd00,
+ 0xc00f6047, 0xb91f1ceb, 0x3650e41d, 0xfaf4071d, 0xe7b7bd8e, 0x5f5ddc01,
+ 0x2e8f3869, 0x7557f327, 0x21148cfd, 0xb1b16abd, 0x565da740, 0x39fb2746,
+ 0x30d6bbbe, 0x743e12b9, 0xa497cf3d, 0x5ebd28ed, 0x0007fc52, 0xf27e94ef,
+ 0xf93d231f, 0xc6498642, 0xab98ccf5, 0x39451e45, 0x29013b1d, 0x183f829e,
+ 0x13e086f9, 0x7dec2d5b, 0x8bf19530, 0xb24ceb60, 0x3baf11c8, 0x3cf02978,
+ 0x56db79c6, 0x45ab6380, 0x377976f9, 0x91a9519f, 0x28d25790, 0xc85fb005,
+ 0x75f1612b, 0x5fb75fe6, 0x869e9052, 0x2fa455b8, 0xf9611d67, 0x20be9418,
+ 0x58d6f1ff, 0x3a24d4db, 0xd10d61ef, 0x87ef015b, 0xef2cc92f, 0x689be662,
+ 0x6c49256f, 0xdaeba1bc, 0x85488cd7, 0x3dff7e7e, 0xef57663c, 0x1fa3802e,
+ 0xeffd5b9f, 0xaa517ca3, 0x0578c247, 0xff63307f, 0x31d90f17, 0xab21bc6f,
+ 0xf4193b22, 0x982c778d, 0x3e97d80f, 0x06ab2611, 0x21dc39c2, 0xfe8eff2d,
+ 0x493ee752, 0x7e513787, 0xde207165, 0x856dc2aa, 0x30e8079a, 0x3a2b9d95,
+ 0xe4186ef4, 0x2306b2b9, 0xecd6a4f0, 0x67a0ad93, 0xb72824ad, 0x65b83787,
+ 0xdcd9efe0, 0xf875d4cf, 0x9806c7bf, 0x29fd881d, 0x21c7f6e6, 0x6caca37e,
+ 0xd6187eff, 0x5cb25f61, 0x6a572095, 0x462ab1cd, 0xfa027657, 0xd0cb767c,
+ 0x7ad0b755, 0x489b9d76, 0x2b5e3fc0, 0x903d46cf, 0x2f7873ce, 0x616b3cf3,
+ 0xd03b6bfa, 0x6bc01a4b, 0xf3c03597, 0x5185e206, 0xee7d6a72, 0x70fdfa62,
+ 0xfff482b7, 0xadc04b7b, 0xed88bb31, 0xe61b1aa7, 0x1e1538cf, 0xe779afc7,
+ 0xb66fb045, 0x706e2cab, 0xb3f5f0f4, 0x35c5dda0, 0xbf78048a, 0x0d9c5c98,
+ 0x4d20ea7a, 0x38a1f1d6, 0x7c628fbe, 0x7fa1c872, 0xd807ba47, 0xfb857fa0,
+ 0xa9359565, 0x43bd9f18, 0x1c03640b, 0x9a8dabdf, 0xbb0f2c80, 0xdd353ccf,
+ 0x0c23f283, 0x49af25f8, 0x3908df68, 0xbafca412, 0x42539d86, 0x31af9239,
+ 0xe4b0727f, 0x8377c7fd, 0xb922dedd, 0x92575f01, 0xe71af92b, 0xb9237f3f,
+ 0xa7defc62, 0xd889e5e9, 0x0f201557, 0xd152fea8, 0xd079312a, 0x8241e54c,
+ 0x5a7f069e, 0x29ed2f7a, 0xed8cb07f, 0x7c8c67c9, 0xc61de844, 0xcecbff7e,
+ 0x3e0893ce, 0xa0bc1ef3, 0xe6977e74, 0x83d613bb, 0x9d7932d4, 0x764aefd1,
+ 0x079e7568, 0xc39e6868, 0xda93eccb, 0x2ebbd01c, 0xc0bd3204, 0xddb98bcf,
+ 0xfbc4f543, 0x8cc3e435, 0x9a4e52de, 0x6d3e2f50, 0xb8bea2f2, 0x3f51f890,
+ 0xa03e385c, 0xe84a9f82, 0x12140b8f, 0x064f4055, 0xac58e3bf, 0xd82cfd23,
+ 0x5d1f2129, 0x8bacceb8, 0x933d0b6f, 0x1dbd32d4, 0xea24d3ce, 0x9f5ca5b7,
+ 0x91fd032c, 0xd5b257f6, 0xa37fd06c, 0x76cad7c8, 0xec579fea, 0x3892caf9,
+ 0xe7ff988e, 0xb7cfcc44, 0x5b87e61c, 0x21b6e81e, 0xf043e509, 0xe09949e1,
+ 0xd9645d7f, 0x525ff4cb, 0xf739658d, 0x7cbb0a9f, 0xe0f4c291, 0x5f2edc45,
+ 0x72f2edc4, 0x760c476a, 0x74f879b1, 0x357a64f3, 0xa75b3df9, 0x633f4a72,
+ 0x893e6c5c, 0x3cf82aed, 0xcf893e61, 0x3debf5bb, 0x9e6279f4, 0xbde98d88,
+ 0xb2befb55, 0xef997af8, 0x137addd3, 0xf4e37fb3, 0xa160ecc0, 0xf77d3ea7,
+ 0x5f20fee2, 0x7fff83d7, 0xf280ef00, 0x78f1b5df, 0xd0d35473, 0x7c7516be,
+ 0xac6fed4f, 0x69fe6a37, 0x9c81069b, 0x7887f40c, 0xb03501e8, 0xc0bbf013,
+ 0xb9b947e4, 0x4165f540, 0x2bd0bade, 0x3d57199f, 0x7d97baaa, 0x28dee027,
+ 0x7c3cfb31, 0xeed5ea50, 0x33fbe56d, 0x09fb68e9, 0xf6c5fff0, 0xb68bbd53,
+ 0x77bd2cdb, 0xe6f6f802, 0x51e43ddb, 0xeba4cf5a, 0xcdc07e02, 0x2895cf54,
+ 0x3973c69e, 0x8a6fb952, 0xfcc1d2a9, 0xb74fe80e, 0xdc423757, 0x91c1e333,
+ 0xd1fce0e3, 0x69261051, 0x8b309fcc, 0x155ccfbe, 0x7d7881ce, 0xd348d1d2,
+ 0xc69bd00e, 0x91cfd0d8, 0x4ce27141, 0xef392b01, 0x9947d80d, 0x20e33c33,
+ 0xd79f4fde, 0xf85cbf81, 0x354fc09b, 0xe3f7fc13, 0xda853d58, 0x5d703b13,
+ 0x1938e036, 0xe01d3216, 0x2fa0e783, 0x63233b0a, 0x8c1e756a, 0xa5a5fe0b,
+ 0x0c87f209, 0xeb907ce3, 0x7e0f82c1, 0x0497c836, 0x7e2eba7e, 0x0e67c7ef,
+ 0xdb9c125f, 0xf547c721, 0x0d9737ca, 0xfb4065f6, 0xe0f39520, 0xefc01aca,
+ 0x5d160843, 0xbc1bb944, 0x827092a4, 0x2978327f, 0x6eef5f45, 0xc7df8e97,
+ 0xef90d9db, 0x42e76cf6, 0x476f1cbe, 0xfcb5fdf4, 0xb053b799, 0xddb1323f,
+ 0x4eb8fe05, 0x1ffa3b4f, 0x02cfc0bb, 0xe0844579, 0x374ebe79, 0xefbe2e7b,
+ 0x1449522c, 0xfb0c47e5, 0xc06908e9, 0xd696c899, 0xafcf304f, 0x428df5a2,
+ 0xda495e78, 0x655e5cf0, 0x7b849db3, 0x08eccfc9, 0xc13b6441, 0xd4725b2f,
+ 0x44899df0, 0xe96fd97a, 0xb1fd8a8f, 0x2b77d6a6, 0xa2d18da5, 0xc178f6be,
+ 0xa8e4da30, 0xeb513fa8, 0xdd25fba3, 0x13f6eb24, 0xdf9e77ca, 0xb4fb4b01,
+ 0x71fbe26c, 0x41b4ed5d, 0x3ed67589, 0xa6cffdfe, 0x8de3a34d, 0x5965e3e7,
+ 0x4abe3c9f, 0xf9643c41, 0x52f3ce13, 0x775f593d, 0xf9f4b2c4, 0xa9f78613,
+ 0x8699f786, 0xfb7d20fa, 0x63befece, 0x5da96fb8, 0x836fb891, 0xe238b760,
+ 0xc8ed677c, 0x4702ea0b, 0xa3b4bbfc, 0xb0a3b1cd, 0xdc252b8f, 0x9f65f657,
+ 0xfd7f04ac, 0x4def1503, 0xa375fd00, 0xdf02b114, 0x464728dd, 0xe8cc1f01,
+ 0xc643f8c7, 0x5f983d0f, 0x63e72ef3, 0x7f02cca7, 0xf3834dcf, 0xbcaca78e,
+ 0xd59e7e1e, 0x35bf829d, 0x0738834d, 0xef8083de, 0x34fbd89b, 0x5605fef1,
+ 0xbfea2fef, 0x8b07ed61, 0x473d79fe, 0x560bff7c, 0x1fda2e1f, 0xbc51f564,
+ 0xfac83e1e, 0xafdac31b, 0x5a70735d, 0x0fdfcd98, 0x460cb27e, 0x22ff8c4a,
+ 0x6fd0517f, 0xf36acce5, 0x0fe8bf00, 0x87f297bc, 0xf7aaeb8c, 0x6f325da2,
+ 0x8129f234, 0xdf343bbf, 0x7284d633, 0xcf959392, 0xd0de9958, 0xe23ccf6d,
+ 0xeb95f3c4, 0x090f8cad, 0xaf8386bf, 0xd32b5ccf, 0x995ae6b3, 0xbb4cb7dd,
+ 0xdb99fb0d, 0x739bfcc8, 0x3d061225, 0x5154cc95, 0x3324365e, 0xf4a1afbd,
+ 0x24773c3a, 0x790d26e2, 0x8710febe, 0x86abf115, 0xc9febe99, 0x43497a09,
+ 0xf82f7b23, 0xad0e434d, 0xaa47f027, 0x0bbc2100, 0xa0a4e636, 0xe7615c7f,
+ 0x186e37d0, 0x07ea03b1, 0x58cf59d4, 0xb11b8fd1, 0xaacf77c2, 0x81738401,
+ 0x0599c989, 0xe8172fb2, 0xff5819e5, 0xffe18fff, 0x240ce7e6, 0x8d8639e3,
+ 0xcd655e30, 0x907b3a07, 0xa013ed28, 0xcd4528dc, 0xb2df6c19, 0x73e8aafb,
+ 0xa0bd6bf0, 0x1359b605, 0x1ef3eefc, 0x813d44a9, 0xfe393054, 0x76f7b2c0,
+ 0xd9dfa6ed, 0x9da2b11f, 0xf3beea72, 0x5af31263, 0xd32e7d04, 0x27398f7c,
+ 0x3ecde9c4, 0x80864fde, 0xa696f07d, 0xba006e79, 0x4576829d, 0xb42f9f90,
+ 0x235f11b7, 0x4acdbf7d, 0xbdd287d7, 0x4ce3cb9d, 0xcd63f995, 0x39e49f8a,
+ 0x0512efd0, 0x234b1db9, 0xb670c7e8, 0x39b7feb1, 0xe0e377e9, 0x8827a63b,
+ 0x9977c5ef, 0xfd05a91a, 0x7635e0ad, 0x41e2effe, 0x8591c627, 0x9af9d49d,
+ 0x220ee313, 0xfbb5262f, 0xb1c79cbe, 0xb2e0379f, 0x5d9834b4, 0x44a9da01,
+ 0x7640c1fa, 0x1fb3147f, 0xb401cd2b, 0xb6de3aff, 0xdfb45590, 0xb30f5683,
+ 0x42b12d53, 0xeaadcfb8, 0x21980488, 0x5dfcafa9, 0x16fbe81e, 0x347bb2d3,
+ 0xa685eeba, 0xe987b115, 0x1d839577, 0xa70d306e, 0x3ff1ff65, 0x87fad0e6,
+ 0x1678ccfb, 0xd4d774ab, 0xf3997222, 0xe0f3c6fc, 0x7afa4de5, 0x1ebeb365,
+ 0xdfd7d16c, 0xe1533ab1, 0x11d521dc, 0x808f70bc, 0xae7d52c5, 0x796bc291,
+ 0x9ca5e2dd, 0xff49fc1b, 0x4aa1e817, 0x7c009d8e, 0xd03bb259, 0xfd6c149f,
+ 0x8e7bc244, 0x7b3889fa, 0xeb941b20, 0xcf86568b, 0x7fa5e0be, 0x4d073b1a,
+ 0xf8265dc5, 0x1eb81c07, 0xe84b2f0d, 0x67cfa2ef, 0xbd07c84c, 0xc97b709b,
+ 0x41977987, 0xfc0dd74e, 0xabc362bc, 0xf04ac8a6, 0xada95197, 0x36b85c41,
+ 0xeda51f96, 0xde18d947, 0x7825fc4b, 0xca43401f, 0x970051f4, 0x87e295f2,
+ 0x9d0d5df5, 0xccf9c424, 0x9ddbf936, 0xe32455e3, 0x6db31ef9, 0x4cc3f302,
+ 0xfe4ca0a1, 0xefb433ea, 0xc045fea8, 0xb3b645bf, 0xb6976bf8, 0x41c0e314,
+ 0x7fe6356b, 0x7e664e4c, 0x9983259a, 0x700bb01f, 0x648bfe01, 0x1710b7c6,
+ 0xcd07fdf4, 0x80c60f3c, 0x58db25a7, 0x6fd9037e, 0x92cebf42, 0x37ac666d,
+ 0xfd1336bc, 0xfd6c1f6c, 0xc014dfb4, 0xdcdbf6db, 0xf6d396a0, 0x8acf947e,
+ 0xf5ee0daf, 0xe4dfb653, 0x7c753e01, 0x2e3ff31b, 0xc376d649, 0xcafe4f7a,
+ 0xe14dfc84, 0xd506bbf1, 0x93f60a37, 0x42aeeb67, 0x3307ebc0, 0xfed8c807,
+ 0x61b88945, 0x749ae4dc, 0x5244be78, 0xe8ff6cfc, 0xcbac4fd7, 0x98fdacaf,
+ 0x12fa6f7d, 0xcf8f7ff3, 0x34e782da, 0xfd6f64a6, 0x6fe824d1, 0xe5cf1997,
+ 0x0f71fdd1, 0xe92a75f8, 0xca9e007c, 0x17487f6d, 0xfcd15b49, 0xdf55bdf8,
+ 0xec581f76, 0x73ab8e82, 0x592d9f81, 0x789b9d55, 0x3a0f4f4f, 0xcdf74ade,
+ 0x9b5e14f5, 0x73c6be44, 0xe6bd295b, 0xa2f91a31, 0x979abb90, 0xd03976f8,
+ 0x1049f00e, 0xf829b167, 0x654db17e, 0x2cbfa8fe, 0x07adfa6d, 0xda77bdfd,
+ 0xe56fc0d2, 0x4f2cbcc3, 0xc5405dcc, 0xfd00a01a, 0xcf2b6440, 0x10bf055b,
+ 0xa2349bc8, 0xbe6cbfbb, 0x4177dd8d, 0x0d9171f7, 0x9e5fc2fd, 0x6556bc00,
+ 0xbe058c75, 0x19f4bc1f, 0x568ec9ea, 0xbc392766, 0x6cbfe67e, 0x8e16499d,
+ 0xa0c1f38e, 0xe367f197, 0x666d9abc, 0x8d49dfe6, 0xc1eb3f61, 0x72869a5f,
+ 0x4b68e916, 0xece50d8d, 0xcfaa5496, 0x9f7dae39, 0x5290fc89, 0x3b68f76e,
+ 0x1e61f15f, 0x83724443, 0x807d193f, 0x9dd7e0a9, 0xe1fe7487, 0xac61a1ce,
+ 0xf9829bef, 0xcf9d8e21, 0x3c010dd5, 0x127cb0b5, 0x05ddb787, 0xe770fbf3,
+ 0xafcc1769, 0xe709a764, 0x24f9125d, 0xf8e8d17d, 0x02946ebe, 0xb93bc021,
+ 0x7eb3f7a4, 0xf4d3f3b8, 0xfe788e85, 0xdeb7c823, 0x996c92f0, 0xf7df0b52,
+ 0xbf70b388, 0xc9b76898, 0x2baff4c6, 0xbb44c3f9, 0xd61fcaef, 0xf523c628,
+ 0xbe57c6bd, 0x0ae55c75, 0xff63317e, 0xbee9c57d, 0x92fedf31, 0xcebe6bae,
+ 0x436c5e7f, 0x04ec79ff, 0xe946fbdc, 0x68b7e304, 0xf1be81df, 0xe3e31963,
+ 0x8143956a, 0x70d77bf8, 0xf54cad5b, 0xa6407518, 0x9999f803, 0x661e63d4,
+ 0x7be58daa, 0x24a89066, 0xf2eb4651, 0x015defb1, 0xd1fd7c82, 0x9db19b9b,
+ 0xe7e1cf62, 0x143cffc3, 0x603c19c6, 0x993bf624, 0x5c4b17df, 0x2aafce9a,
+ 0xa8f825f0, 0x6da75f11, 0xc97fdc39, 0x956a4be8, 0x257aee30, 0x1dfd3aba,
+ 0xb5c755d3, 0xd24795d2, 0xed9f53d1, 0x7eabb2fa, 0x06bcf1ac, 0x83351f96,
+ 0x734333f7, 0x5b32fde0, 0xf109bea9, 0x168f81d0, 0x551e587b, 0x71e83b5b,
+ 0x94349bf6, 0x6dc84f87, 0x0a7f6039, 0xcd788c7b, 0xda7e891d, 0xa0d9f69e,
+ 0x200b9064, 0x94be6163, 0xc3fb303f, 0xbeffa2af, 0x42f3e433, 0x5340de5e,
+ 0x3ae7de0e, 0x82f6e430, 0x4cb06adf, 0x4c718935, 0xcff5c04f, 0xa67e2c25,
+ 0x3bbea334, 0x2f6e87e0, 0x4a82deb8, 0x2f566f24, 0x6486917e, 0xc95c8f66,
+ 0xfa75219e, 0x9aec29fd, 0xe09d272e, 0x0efc710d, 0x92387130, 0x42d79e34,
+ 0x2efd1e59, 0x44d3dc5d, 0x07d43c77, 0x9c59d774, 0x1b3f7bb6, 0x4bd847d6,
+ 0x7fc8ff71, 0x12502f1e, 0x76ff23fd, 0xf091fe6d, 0xffc1c7d6, 0x247fa7d1,
+ 0xf82a647c, 0xae88344f, 0x0e18f7f0, 0x9f77291c, 0x7d150197, 0x1efe33b5,
+ 0x5ad44aae, 0xdbfdfe24, 0xe30db785, 0xbf8e187a, 0xefb031fb, 0x6e895bd7,
+ 0x14f844bc, 0x2470ff43, 0xede1e1c1, 0x069bbfc3, 0x4e3d3dfd, 0x31f43f7c,
+ 0xb37aef98, 0x19443fbe, 0xbd5b8fad, 0x11d6b0b8, 0x0f54fb97, 0xe2d3dbf0,
+ 0x3bf57ff2, 0xa06fea33, 0x9fdddb7d, 0x90a0fe62, 0xded4c1e3, 0xb7cd3fcf,
+ 0xcf4edf4b, 0xb9e87ad5, 0xcf4cedf3, 0x46ad842d, 0xcbe401ed, 0xcc7e15c1,
+ 0xc6faa43f, 0x1bea3b62, 0xee97181d, 0x89c5f59c, 0xf7681e81, 0x8fbc3cd0,
+ 0x1092e205, 0x21326a0f, 0x255ad45f, 0x662d6f46, 0x9e8227dc, 0x6a3f38ca,
+ 0xf9e30e48, 0xd24386e0, 0x94e03084, 0x4ddd6754, 0xdda4eed7, 0x638e10f7,
+ 0x2873dfd6, 0xa676b5ca, 0x164707df, 0xfe85ce6c, 0xf4044a77, 0xdf23b580,
+ 0x76885f4f, 0x8be97bcc, 0x6d2bbe12, 0x63e59a79, 0xc57b9936, 0x89bb5ae3,
+ 0xf70775d9, 0x7cfbdc63, 0x5ebdc244, 0x80d644a2, 0x22525ade, 0x3e379da3,
+ 0xf5073c52, 0xe31522f1, 0x2f5cd581, 0x0ecd360a, 0x906dfe43, 0x47d127fe,
+ 0x8b8bfc5b, 0xd22a4f51, 0x3d1f101c, 0xe300b23f, 0xeabf61ed, 0xcd283c46,
+ 0xbdbddf98, 0xf40e31ca, 0xccefc1ba, 0x8171ee98, 0x7f3bdefd, 0x0679e14d,
+ 0x7c3f92b5, 0x93a7f327, 0x765cbf44, 0xb6f3d30b, 0x5c5d55da, 0xc59dab70,
+ 0xb70d6fa3, 0x9f38c54d, 0xfd076ed2, 0x9f7c4837, 0xfc4a7d80, 0xf7bb0f0e,
+ 0xd4a3f184, 0xdbf30790, 0x27f6d4b4, 0x3cf7806e, 0xed28801f, 0x9db8c14f,
+ 0xdcf1526b, 0x6a7ae137, 0x31a3c3e7, 0x08eecdff, 0x95eb00bc, 0xcecaf5cf,
+ 0x37977f83, 0xcb93e41f, 0x4fc873f3, 0xe8285f20, 0x64fc9fff, 0xe02a6dac,
+ 0xcc218bef, 0xfde3c13f, 0xc2bd9e42, 0x35ca99e9, 0x7c3cbf16, 0xd4df3f3d,
+ 0x0fdfef1d, 0xbf7888e3, 0x009eb539, 0x0233527d, 0xaa5a0bfd, 0x325e809f,
+ 0xc0ac5c35, 0x3ea308f9, 0x7fc79532, 0xf3e94890, 0x27f74e02, 0x014bbcbf,
+ 0x00b596fa, 0x2b4e0fe6, 0x3bd011b2, 0x8755d387, 0xabe8f7fb, 0x7cf1afda,
+ 0x19e655d7, 0xd011b6a5, 0x5ee12b67, 0x72a4da4d, 0xc7e8cbe4, 0xbb18e716,
+ 0x3b4aa8fd, 0xecdb61fa, 0x6be72e76, 0x6901de59, 0xd907f8c3, 0x9099d6c3,
+ 0xf3c4acf6, 0x2affc24e, 0xb15753fa, 0xee4ac97c, 0xb29bc197, 0xed77fbe9,
+ 0x7f332e42, 0x1e2f1886, 0xde9de99f, 0x2e22ecba, 0xfd842b13, 0xe2283b19,
+ 0x02149f32, 0x9719f49d, 0xd55874e1, 0xccb8f972, 0x7f6f1ce7, 0xd7ccb8eb,
+ 0x8a6be4f6, 0x8ff674cb, 0x494f982a, 0x02efb7da, 0x82c5bd3b, 0x2d19effe,
+ 0xe40b7abf, 0x348d0ce7, 0xd7745e43, 0x63b767c7, 0x6f4189be, 0x5536adf8,
+ 0x38804c73, 0xf45eabdc, 0x06f419af, 0x43b0dda3, 0xdfae61f0, 0xceae3b65,
+ 0xbeed106e, 0xebacfceb, 0x98d7b8c4, 0x87bc659f, 0x93acfa6e, 0x78bcf167,
+ 0x1af315b3, 0x73b3375e, 0xccfde1f9, 0x31b0adee, 0x987152fe, 0xc0381bdd,
+ 0x567cc7e2, 0xf9198af2, 0xfcecb048, 0x798cb24b, 0x203b37bc, 0x646b3e1e,
+ 0xfaefb412, 0x6df709b5, 0xaec7bf05, 0xa753eb91, 0x9551ca47, 0x2046fbee,
+ 0x9d67187c, 0xebb7af3e, 0x5f190367, 0xaeee71e3, 0xf7af2c35, 0x264a75a2,
+ 0xb30fc3c6, 0x3c05dcfc, 0x6a75773f, 0x749997e0, 0x3e7fcb5e, 0x8bb9e305,
+ 0xcdc58048, 0x9d79f4eb, 0x964c7cf1, 0xb70e5dff, 0x4bf3b3fe, 0xdc6abcfc,
+ 0xfff7066f, 0x0294ea79, 0xc4395390, 0xb4f80abd, 0x7bb14c27, 0x096b2d13,
+ 0x925c67bb, 0x9427d025, 0x5836a935, 0xf2b5d58f, 0xe16fd874, 0x1fef195a,
+ 0xd0b8eb17, 0x5fba4261, 0x80f260e1, 0xe3022ca2, 0xdf96b288, 0x5bfa2dd7,
+ 0x9428e449, 0xd5cac4b2, 0x6f7a656e, 0x57f45272, 0x20d6ae6b, 0x58362c5f,
+ 0x45ed7f46, 0x798457d5, 0x04b9292a, 0x9d6a4bf2, 0xd9d375d5, 0x8bf1a47b,
+ 0xdf1f98d6, 0x0a614f7f, 0x00a4f11b, 0x21cfbb3f, 0xf53b7bf3, 0x6f545b78,
+ 0xdf21a3c0, 0x8c090176, 0xe7b43fe8, 0x6b8b8af9, 0x021e5873, 0x5cf1afc7,
+ 0xe7307dc2, 0xaff9f109, 0x26f0c41c, 0x90e5660f, 0x984505c1, 0x62ac9557,
+ 0x6490d35e, 0x33a45fe6, 0x7c87f841, 0xba02552f, 0x0b5bc230, 0xd5d012ca,
+ 0xeae9091a, 0x3cf7f04a, 0x04cbe217, 0x56e05efa, 0x08cf1f31, 0xf983ad77,
+ 0x77e4ae8f, 0xf92afe78, 0x3b7ff3c7, 0x89eec1fe, 0xb9426358, 0xeef25a7d,
+ 0x8efca28e, 0xf985c9ac, 0xefe131ad, 0xe501e047, 0x2a7f7674, 0xed9d4dfc,
+ 0x755f7940, 0x5a4bdd98, 0x0b3da2b9, 0x41556e84, 0x6d5bde3b, 0xab4037c4,
+ 0xdb43fe08, 0x78254fcd, 0xd3a927df, 0x92f761e7, 0xfc0ade5f, 0xdd1ccba2,
+ 0xce3a2bfd, 0x1440e61b, 0x622b55ea, 0xed7f41bb, 0x429df878, 0xbf37c289,
+ 0x6fcba2d6, 0x2c297521, 0x3e9d780f, 0xe8349b9f, 0xf55b25eb, 0x03546ddf,
+ 0xffbdd8a3, 0x4f77e7bd, 0x2e73b176, 0xfbc64ca4, 0x32bae959, 0x6393ef7f,
+ 0x962079f8, 0xfbf02c77, 0xaaba43be, 0xeed163fc, 0x7c7f95af, 0x09fc0d40,
+ 0x5cd1b4f0, 0x75fd83ef, 0x09ff36e6, 0xf4cae739, 0xe13e97f8, 0x5fe3d3d5,
+ 0xbfde11ae, 0x9c533c96, 0x37ca37d2, 0x29a5fc3e, 0x6f3a056c, 0x5b738935,
+ 0xf9d8ff06, 0xb91ca21f, 0xff104b24, 0x5f97f630, 0xf3ef8ed0, 0xe80990bf,
+ 0x091a9943, 0x30c21fa3, 0x70c40b4e, 0x9dfae2d2, 0xdc190f11, 0xf4e3182e,
+ 0x06ff653d, 0xeb696076, 0x402af0ef, 0xe12d8fe1, 0x2bc8b56d, 0xa8b7bc3e,
+ 0xfe837255, 0x51a279af, 0x3aa9cfc8, 0xff06ec54, 0xe9c8b9eb, 0x97fb8874,
+ 0xb59f9846, 0x2e7be774, 0xb84e63c8, 0xc434621f, 0xfe874909, 0x9dfa361e,
+ 0xf0a3be0b, 0xde3d07ae, 0x81531a9e, 0x644aabfe, 0x4ab84fbc, 0x501e6189,
+ 0xd2f12a55, 0x49f5421d, 0xc5b5bdbd, 0xd8fee2af, 0xfde12ad2, 0x206ae961,
+ 0xbe239067, 0x85bea89f, 0x7d8a6df7, 0xbbe9c936, 0x9f88e017, 0xeaddf09b,
+ 0x39ccbb4c, 0x3534ffae, 0x09ebe5ae, 0xcadf3fef, 0x2f9100f4, 0x029e7096,
+ 0xf316e3f3, 0x473838fc, 0xffcc4d11, 0x205c7382, 0x06f9f887, 0x7ba14738,
+ 0xf081ce2f, 0x8e7014f3, 0xe27df122, 0xe7c4adf9, 0x98a5a619, 0x28e70817,
+ 0xf9c79f12, 0x37f295c9, 0xc68d79f5, 0x791ecdfc, 0x1b3f7c8e, 0x399718f3,
+ 0x88ce4eaf, 0x1f95df76, 0x78c51ff2, 0xf9ef9ad7, 0x5c93cf0d, 0xbe6dff89,
+ 0xfe6d3c4a, 0x2fa9e31b, 0x1bf3b7fe, 0x57ffbff2, 0x3d0f8171, 0x1ae0e9f5,
+ 0x3fd0f67c, 0xa05208fc, 0xee8e4d0b, 0x30b361df, 0x71b2fe7d, 0x266dcae6,
+ 0xab939c2f, 0xfcc4e43c, 0x2cb7116c, 0x010b7b23, 0x6378c6e5, 0x0e6be405,
+ 0xe3b8f6bd, 0xc77671ff, 0x7f1273df, 0x40bf2037, 0x398fc7cf, 0xf897ed3e,
+ 0xa305663b, 0x0bdfc2a9, 0x984a6b5d, 0xbdc7e624, 0xf37a64ed, 0x1f3bfe31,
+ 0x073b2a99, 0xc769deb4, 0x8a94bd73, 0x49d03cf0, 0xe05dffbb, 0xe1879a77,
+ 0xf783d9f1, 0xe5e29912, 0xe6337359, 0x1d2b870f, 0xc213e05e, 0x9ffa227f,
+ 0x5730fc21, 0xafcfefa0, 0xff3fbe92, 0xffc0f98e, 0xd5f5d374, 0x8e28b9c6,
+ 0xe919da12, 0x3ebbfbb5, 0x7d05bcf2, 0xc263a4f6, 0xf1622fef, 0x226fe10e,
+ 0xee2eb0be, 0x13f9c053, 0x603cf7d5, 0x0f388917, 0xea7cf4d1, 0xf9e11b13,
+ 0x90959e89, 0x29fb1487, 0x88893f41, 0xcbe1194f, 0x81abf1e4, 0xce256e3c,
+ 0x244c6633, 0x6dc3d06e, 0xdfd821ae, 0x33ade236, 0x78f9850d, 0x888f9824,
+ 0xc1f5d067, 0x966417f3, 0x0416e3ca, 0xb980e2e5, 0x87c811e9, 0x797b7209,
+ 0xf891dcc0, 0xf109883b, 0x1767660b, 0xf50e50d9, 0xe2c59f92, 0xe632a56f,
+ 0xb1e435c7, 0x7b861b7e, 0xebfadcf0, 0x99f88ec2, 0x886f7d93, 0x8a3c0873,
+ 0x9fc08738, 0xe232e3c8, 0xff9ae7ed, 0x3c5a5756, 0x3136415e, 0x54abbbbd,
+ 0x76dce226, 0xa55dbf62, 0x1279645f, 0xb5682dfa, 0xe8663e30, 0x9e774b77,
+ 0xe78ac46a, 0x5ebaf915, 0xdf891cab, 0xc136111b, 0x7fc398fe, 0xb528857f,
+ 0xdddc9eac, 0x6f69ea05, 0xcb5aa26b, 0x0a8edcea, 0xc7bf67ce, 0x9cc1f620,
+ 0xc02896c3, 0xfee1f6ff, 0x5e17c005, 0xda8ec737, 0xcc7e5d61, 0xfbefb1f2,
+ 0x803371c3, 0x3bf7ffb4, 0x1687c09c, 0x9d3ed8b9, 0xa0666247, 0xbdff009b,
+ 0x313f7128, 0xc4e6ffdd, 0xa3fbd13c, 0xa0efbb91, 0x478e07b5, 0x307100ee,
+ 0x5fec64ef, 0xcd029960, 0xfd2042ee, 0x13de2df9, 0x7fd31d4c, 0xbc5f3097,
+ 0x5f3e272f, 0x3093e70d, 0xf117e45f, 0x0f886af9, 0xe0cfdf31, 0x33f212ff,
+ 0x3f02bae6, 0x39e84d71, 0x4e6f716f, 0x8ff0397f, 0xa6550740, 0x50fa7640,
+ 0x1a4e6f76, 0xeaedabcc, 0x32e809ee, 0x097d7bb3, 0x758a3b8f, 0x3df10c1e,
+ 0xc8f90188, 0xf674d4b0, 0xbcf02dfb, 0x7b23c78a, 0x6a983bc8, 0xeecbec3a,
+ 0x9ba054bf, 0xfebbfc41, 0xe03fada4, 0x25bc033b, 0x3a3cab74, 0x8c965bd1,
+ 0x103637fb, 0xcf1d2ee4, 0x241bbf07, 0x2feafeb5, 0xf45a37c8, 0x3bf4487e,
+ 0xc77ee35a, 0x9775e6be, 0x91c277e6, 0x1793bbfc, 0xbdfec198, 0x27f78497,
+ 0x33cf8d0f, 0x854af9c8, 0xf00bb02b, 0x1e7d96fa, 0x13a1139e, 0x1ef57bc5,
+ 0x5dbb7d96, 0x75456fa8, 0xbdf14271, 0x1e374bc0, 0xe231f80c, 0xcc14f805,
+ 0xf8c49b7b, 0x993f9896, 0xe712d5e8, 0x376f9c6d, 0xde72ae1e, 0xc47fce22,
+ 0xf7053b1c, 0x4af91cc5, 0xc0437b43, 0xc1eac47d, 0xa7f86e38, 0x11999cec,
+ 0xadf8beee, 0xf8133f80, 0x6af809a9, 0xc3ffc23d, 0x0fcce1a4, 0xc06f3c4d,
+ 0xef010a39, 0x4ab3e051, 0x8cb87c42, 0x205523dd, 0x74eceaf8, 0xaa9d5f1d,
+ 0x80f3b8b0, 0x39ecb9d9, 0x938073f0, 0x938073f2, 0xa3f459f2, 0x15c9cc34,
+ 0xd4ed167c, 0xe30da958, 0xe2cf94e5, 0x730dacbd, 0xe6ee1f18, 0x330f94b3,
+ 0x1f384b3e, 0xefd84776, 0x00720627, 0xc9e57def, 0xfdca3fa6, 0xe74f8a88,
+ 0x32c5b8a7, 0x0aba4d45, 0xae57d57f, 0x880ff3ab, 0xfe95df76, 0xf5e926a0,
+ 0xeebe4287, 0xc80f4285, 0x6a79cbd4, 0xbe617a57, 0x6ed8d65d, 0x635117cc,
+ 0xc8ae8167, 0x5fbc166b, 0x558f6837, 0x173eecc9, 0xfeab33b4, 0x9d99d995,
+ 0x9dff0c69, 0xdf1ccd07, 0xf7e1dbed, 0x196d3e55, 0x8325f781, 0x7dc2a07e,
+ 0x214bfe1d, 0x12159dfc, 0x17fd0529, 0x3c4869ee, 0xff49d427, 0x93a7192b,
+ 0x5b5d6cbf, 0xc13fdcec, 0x73555ae2, 0xaaef286d, 0xd972f7e4, 0xff161439,
+ 0x15527617, 0x71a51bd5, 0x92ae75f1, 0x90ed17df, 0x707b895f, 0x10e3bb68,
+ 0xd6d0a94f, 0x043c41b5, 0x1d22c87f, 0x77455f7f, 0x9f6ab41e, 0x09ce7745,
+ 0x9fd4c3ee, 0xefe352a7, 0x38b0ce11, 0xf385117f, 0x2643b1ab, 0xb3a1e791,
+ 0xf264fe33, 0x5ef8872f, 0xbf7626d7, 0xb6735756, 0x37a7a577, 0x8f9a23bb,
+ 0xefa8c772, 0x35c02435, 0x2debcd84, 0x0121efbc, 0xbcfc531e, 0x71b9f198,
+ 0x4bdfe01e, 0xe2f94f7c, 0xe20f40ed, 0xf7909fbc, 0x7839f7dd, 0xeae80524,
+ 0xd0bbc704, 0x5cf90b0f, 0x0f363555, 0x740dcff3, 0x34baf026, 0xfd2abe49,
+ 0xeae934bc, 0xf76897f6, 0xa5afed5d, 0x88bfb8d7, 0x790ade41, 0x2bcf0cf2,
+ 0xf8b124df, 0x083ba6e0, 0x37b5a7bb, 0x87109879, 0x0ccf72a3, 0xa93dc62a,
+ 0xf3dca10f, 0x612b03b8, 0x7c468abd, 0x43bf0592, 0x23c5fc4c, 0xcfba6e80,
+ 0xec234ee9, 0xdbaf2e9c, 0xfbb1b7a7, 0x15bdf9a3, 0xfb02ef98, 0xf509ab6b,
+ 0x7f4cdbd9, 0x85d9ff44, 0xe41c64d1, 0xf1cf0665, 0xd849367e, 0xc6d6a4cf,
+ 0x4ae7e063, 0x1836de9e, 0xefc83c96, 0xdf5c228f, 0xf937bee9, 0xbb614fd7,
+ 0xf5627fa5, 0xe7163e69, 0xe1349e0a, 0x385d95ef, 0x3cc15b39, 0xe91283dd,
+ 0x2b76fe07, 0x70494b95, 0xbbac999f, 0x44546377, 0xd7cc7bff, 0xeae8a537,
+ 0xe8079a63, 0x32d0dfda, 0x2f3ef744, 0xfdee9d7a, 0xe9c7278d, 0x26da13ea,
+ 0xf4dfdae9, 0x7eae8156, 0x740ffb73, 0x37396fed, 0x5eff574b, 0x7b5d3eec,
+ 0xc1b5f612, 0xe42ec0ef, 0x78ec2deb, 0x5f267fc1, 0x77bfaf9a, 0xa5452a24,
+ 0xe2eff8fc, 0xe2c75c2e, 0x75a6e575, 0x0537f798, 0xfd096f22, 0xb65df8f7,
+ 0x4f3c4696, 0x65dfa571, 0x0c5a911b, 0xc3d398bf, 0x249bf01f, 0x19c3ef6a,
+ 0x1fa47ea1, 0xf4beffec, 0xbfb8db8e, 0x13a502e2, 0xba6b7bfe, 0xc325cef5,
+ 0xefa3819e, 0x126693c1, 0x44bdc0f1, 0x74a7b584, 0xc2e1f203, 0xf197bfc9,
+ 0x7af8d5f7, 0xc964f11b, 0xd5bbafd4, 0xfb775fa3, 0x3bbafd48, 0x4f75fabd,
+ 0xf75fa89a, 0xdd7e9f64, 0xafd74dfb, 0xbf5f9a7b, 0xfa4519ee, 0xd01fef75,
+ 0x12c0fbaf, 0xae0fbafd, 0x767bafd6, 0x735d7e8d, 0xba7a65c2, 0xd081d030,
+ 0x2dd686c3, 0xbf63b435, 0x41e8282f, 0xee42c1d0, 0xff5e19ef, 0x4638dd13,
+ 0xfe5ff87a, 0x00f95254, 0x000080
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1[] = {
+ 0x00088b1f, 0x00000000, 0x7de50300, 0xd554787b, 0x733ef8b5, 0x932795e6,
+ 0x13848bf7, 0x0f209212, 0x28204807, 0x042010ea, 0x2d004c44, 0x42438b54,
+ 0x20c79020, 0xb6de2f58, 0x08a3c337, 0x51b43488, 0x341d82d1, 0x83b05428,
+ 0xc49498c6, 0x2d110f0e, 0x60b4406a, 0x2880697b, 0xc189212a, 0xf5b6f452,
+ 0xfbdad6b7, 0x124ce724, 0xeefdbd41, 0xf9f8bf1f, 0xafd9f66d, 0x6b5ed7b5,
+ 0x5ad7b5ed, 0xfa92cf7b, 0x6066661d, 0xd356f16c, 0xa32b16b9, 0xffe1afbf,
+ 0xbe7d1e25, 0x1f3e9774, 0xfc890b60, 0x11fe0838, 0x96bfc2ce, 0xe0c87b19,
+ 0x3165b408, 0x5e0a61d6, 0x5ac00d2f, 0x32c6c63e, 0x54ff8156, 0x31844b18,
+ 0xdff868d8, 0xf08d52c1, 0x2bdf125d, 0x793ec1ac, 0x30666624, 0xffbacd16,
+ 0x624f9812, 0x976d8c29, 0x618d28aa, 0x38c1896e, 0xcd6edb2c, 0x39fd411f,
+ 0x35266c60, 0x84a5f1be, 0x6d4debed, 0xbe02192d, 0x6277d8c1, 0x8c01c7d8,
+ 0x009d7c9a, 0x6ddfe3ff, 0xccd3d3bd, 0xc042d4dd, 0xbc20326c, 0xae1c6cf3,
+ 0x3c69f8cb, 0x5e643f63, 0x1a7f8e13, 0xfc0364ea, 0xca66b2f7, 0x949d67cf,
+ 0x8ccd993a, 0x53b32169, 0x53e590ba, 0x196d665a, 0x388e00cb, 0xc446f383,
+ 0xc70595cb, 0xcc0048cf, 0xc20fc469, 0x0a022c7b, 0x318b87fb, 0x8c516337,
+ 0x3b9cac1d, 0xd8c8d5bb, 0xece74ae1, 0x6fc054d6, 0x6f95e480, 0xc4aa14c4,
+ 0xf21bb563, 0xef11c31c, 0x9e737e6a, 0x21f21823, 0x309beff0, 0xe52a733f,
+ 0x89f2d4c3, 0xca251f3c, 0xa9536bd9, 0xfe5aa27d, 0x10dfde6b, 0x3ccffcb5,
+ 0x9fe6a71f, 0xf327fde7, 0xdeaad3fa, 0x470f73c9, 0xb5b008fa, 0xdca3e86a,
+ 0xbbcba61b, 0xad6ce3ea, 0x52f93d19, 0xd9f607fc, 0xeeb88cca, 0x5fdd6265,
+ 0xd9779c96, 0xd672b600, 0xc719aeb2, 0x5c669d60, 0x66ae956f, 0x21e73a86,
+ 0xcd054f3e, 0x75830dcf, 0xd1311b9a, 0x82f5061c, 0x321e8132, 0x8b64faa1,
+ 0x53b50867, 0x19231956, 0x6c951e3b, 0xe0b908df, 0x2c40200c, 0x0cf00e0f,
+ 0x5860c491, 0x6787721e, 0x560fd423, 0x9632dc5a, 0x10fb24db, 0x896d0b05,
+ 0x8bdc6073, 0x1923a101, 0x64a2fbe0, 0x5003d1fb, 0xb2090eee, 0x6572a4ef,
+ 0x33940140, 0x166032a7, 0x572b65a4, 0xc31d6ecf, 0xbed58e58, 0xc74919ad,
+ 0x005645bb, 0x3b2a272f, 0x3d8d18e7, 0xc49efaeb, 0x7b837ae6, 0x9b16f7af,
+ 0xcb3deb44, 0xce5baea0, 0x09fbc451, 0x932eba83, 0xe64b3f29, 0xb95595f9,
+ 0xde17bf47, 0xef0e926d, 0xa796d6e5, 0xffc215ab, 0xc56fc416, 0xb921fff4,
+ 0xd2fd3ed0, 0x222f4c58, 0x4e11c3dc, 0x4664e085, 0xd201667b, 0x267b5ad8,
+ 0x7957bfce, 0x7e239430, 0x48794136, 0xd156e51f, 0x5f6f3d7e, 0x324ced66,
+ 0x0c797e72, 0x82caffd7, 0xf3220fb3, 0xf9c8183e, 0x3989b8e6, 0xb8ff884c,
+ 0x5c4ecf10, 0xd6919b3f, 0x30a0c8ef, 0xdb663f5a, 0xf314293a, 0xa7bd7c29,
+ 0x057cdd01, 0x799d387c, 0x338fc88d, 0x085f251a, 0x58d4ddf0, 0xc1a2d293,
+ 0x9f4534c7, 0x6edac3bf, 0x619dbe44, 0x3e401df4, 0x5f433dbd, 0xcc68f40e,
+ 0xb0efb807, 0x99dfbfeb, 0x6d74cffd, 0x1ee1e41e, 0x807ee3c4, 0x9fbee095,
+ 0x2523b871, 0x61f904b7, 0xd8efc6af, 0xc250e9c8, 0xae2df875, 0xb5c6a019,
+ 0x079d8732, 0x1962c0d1, 0x6e7cc333, 0x7e685428, 0x759962c3, 0xbabbc810,
+ 0x481c457f, 0x9f9def80, 0xa08cf632, 0xbfa15be1, 0xaa58acba, 0x917f2dd7,
+ 0xcffbf146, 0x407e3952, 0xf74646ee, 0x27c05dc8, 0x8f5c21b3, 0xdd5c1206,
+ 0x344d9472, 0x918e7ca2, 0xa40ebd78, 0xabe7927f, 0xa213fbe8, 0x0204877d,
+ 0x9967db0a, 0xefe0bcf9, 0x6ba5802b, 0x278f8d8e, 0x826c62f8, 0x07f91035,
+ 0x6be48608, 0x40af9086, 0xa83fb438, 0xa09f2a7f, 0x133843dc, 0xc4c99ff0,
+ 0xa39c3e2f, 0xc62ace3b, 0x913ed1b1, 0x31fb5568, 0x389fb03a, 0x2c2d9701,
+ 0x9b17d38c, 0xd17ac16d, 0x5f377be2, 0x514795b1, 0x15f3757e, 0x55e519fb,
+ 0xb55f3abe, 0x57c5dffa, 0xbd516151, 0x5243aaf9, 0xd38f098a, 0x3f346c02,
+ 0x5d013e63, 0x6b62c623, 0x1a9f299b, 0x2851b3c0, 0xe47ab2f4, 0xcfbcecc6,
+ 0x703518e7, 0x84e57f41, 0xb64169af, 0x0cbf809d, 0xa05ce9c0, 0x4f9c161b,
+ 0xcdfb56f8, 0x888e6588, 0xd8fe9ef0, 0x572a66a6, 0xdfa3e9c7, 0x437ef31f,
+ 0xf55afdf4, 0x4777c2f0, 0xbf4d68c4, 0xf7f0f5eb, 0xc3cb97ee, 0xd55bcd6b,
+ 0xf58ba627, 0x0deaae9c, 0x19601f42, 0x1b3ffb7e, 0x30f1f618, 0x9e03ffb1,
+ 0x57fd048e, 0x773be22a, 0x3e91fdc0, 0x086f0790, 0x56b3c93e, 0x72dd48e1,
+ 0xd2872342, 0xc4aebd70, 0xdf8b1d9d, 0x7c7c1c1f, 0x4e7ae33e, 0x6f54587a,
+ 0xebbe5478, 0xcf4fcb86, 0x34dfade9, 0x03bf6007, 0x4149af51, 0xa94659d2,
+ 0xf9ba3cff, 0x6199f512, 0xae4cfa3d, 0xe7cd1975, 0x826e258d, 0xafd86a7b,
+ 0x6c57988c, 0xbe105bce, 0x9e7e37b9, 0xb1cac464, 0x5e51d20b, 0x86b7dc01,
+ 0xc3dffd65, 0x702431dd, 0xc1e401ad, 0x7d4daf6d, 0xc8d06ad2, 0xa4f93f2b,
+ 0xe40c8fb6, 0xa57b6ffb, 0x4ffa8ec3, 0xee2df224, 0x240d4bd3, 0x7c8c2a0f,
+ 0xb4af8f9f, 0x3b4357d9, 0xc7979197, 0x6acf14bb, 0x831e8794, 0x12fa84db,
+ 0x0fdddfe3, 0x5ef83b40, 0xd5f3c61d, 0x981e2bf7, 0x9955c809, 0x02e76964,
+ 0xcb0679e6, 0x57ca3147, 0x9072f317, 0xe9196ee3, 0x5b8f843f, 0x70c2d05d,
+ 0x36f1eadc, 0xac139b9b, 0xef559e4e, 0xf548fae0, 0x1f6a34bc, 0x8360a32f,
+ 0xbcb87b82, 0xe3164ead, 0xca81b92f, 0xf3150b6f, 0xb7f7ccda, 0xf1f336db,
+ 0xf0429a59, 0x8d149fe2, 0x0fe6b07a, 0x14da9fca, 0xfac8fb40, 0xdc3fae30,
+ 0xb89cc816, 0x91b6decf, 0x8e1a5f39, 0xc34f657c, 0x1795567d, 0x6f763d6a,
+ 0xf5d701ac, 0x018f2101, 0xf4beceaf, 0x0deb4b92, 0x51fb03cc, 0xe94606d9,
+ 0xa5c657a5, 0x6d7a802d, 0x15a5c6fb, 0xd9aafa42, 0x55d208f9, 0x924770f1,
+ 0x0f1f3069, 0x93e811f9, 0xb63ca0f4, 0xc14e552c, 0x49d978fd, 0xe7d10a43,
+ 0x61cfa216, 0x3a299f40, 0xa725fcfa, 0x9bd1374f, 0x87579f3f, 0x015cff79,
+ 0xd1aa79f8, 0x5d137762, 0x3b6124b6, 0xdb7bba7f, 0xef35f8ea, 0x1affcf47,
+ 0x391a1678, 0x4cb2913c, 0xf58b3cf0, 0x8fe9e1fd, 0x9798624f, 0x7e5a21ce,
+ 0x76edd2d1, 0xb8c8b73c, 0x8b73f37d, 0xf2a85d3f, 0xa408c62a, 0xfc37ba34,
+ 0x6bf2190f, 0xfd9e9e11, 0x721e6fd8, 0xddc9d130, 0x058f64f3, 0xa9057506,
+ 0x4663b3fb, 0x2051c01c, 0x437bb8e0, 0xac30e4fe, 0x7c712057, 0x803fe0f9,
+ 0x2f289663, 0xc19f2c68, 0xb6d9ffa0, 0x3bea1302, 0xf9c326b3, 0x38e7a74e,
+ 0x8ae61d68, 0xe86673fa, 0x2d8c7fcf, 0xe69e2133, 0xcb9f4db2, 0xcf77bb40,
+ 0x7b9fb7d1, 0x6eff3eaf, 0x87179c18, 0x5fe95f51, 0x9b0e5e03, 0x2077bd38,
+ 0x5e3cc1bf, 0xedbc5a8f, 0xf4e7a07e, 0x2d1f0f5f, 0xa25378c3, 0x816cd497,
+ 0xdd4ff3fc, 0xa3d7f940, 0x38e079ef, 0x469d3f96, 0x8906c9f9, 0xc7e3bfe8,
+ 0x8cd7e206, 0x27a6f3b1, 0x03871c03, 0x73f7bf44, 0x740d8e3e, 0xbd401756,
+ 0x478391d8, 0xc9a281af, 0x1d37ce66, 0xf6fcbcc5, 0x3f28431b, 0x23c53ef6,
+ 0x03939743, 0x8ed3e215, 0xfa8ec910, 0x1651b1d5, 0x29311f2a, 0x860f9799,
+ 0x17cb0dfd, 0x63fb5084, 0xa87c83a3, 0xe1f0bd47, 0x2c3f2a50, 0x1f3f3e7d,
+ 0x3cbda896, 0x52eb88d8, 0x62b56f11, 0xf2432c3a, 0x4f7c050d, 0x97e3170e,
+ 0x18cf79f3, 0xf91e3bbd, 0xe74e7268, 0xd7e07cfc, 0x286b78f6, 0xcba03bca,
+ 0xc307482b, 0xa43713ec, 0x74b41d20, 0x52e96926, 0x9502e75d, 0xd3fb270e,
+ 0xc81fe391, 0xd7c9fd67, 0x4752e8fe, 0x743d0177, 0xf539dfd7, 0x414f9e1c,
+ 0xf9e2b72e, 0x47a1a8d4, 0x35225307, 0x24e148fb, 0xa5ca1969, 0xf4881fc2,
+ 0x0b8d3cef, 0xf04f4897, 0xe4acd74f, 0x47ca8afb, 0x20ef9103, 0x90ae131d,
+ 0x1a0edafc, 0x97f13066, 0x817886dd, 0x7cfcb8fe, 0x12f24cd6, 0x0abc62a6,
+ 0x8a061eb8, 0x83dbb628, 0x76e68c80, 0x3fbe0908, 0x39136462, 0xc06fda7f,
+ 0xcc8c23f6, 0x5dca157a, 0x72865b32, 0x40dc3d30, 0xf1c50ce3, 0xf79a9e00,
+ 0xca033599, 0xc662ee6b, 0xb35f680c, 0x4a98f20a, 0xf08d1f90, 0x645bd7d9,
+ 0xb79c4a8e, 0xc0c6bfaa, 0x932ddb81, 0xf5e0286a, 0xfc395fd7, 0x6dcc4cdb,
+ 0x6412fe85, 0x17282010, 0x63ec2998, 0x0ff1b5eb, 0xab1f64d3, 0xe0f72eeb,
+ 0x0adebfd9, 0x63cc0f9c, 0xbba9e57d, 0x51e7355a, 0x6ccdd1ab, 0x0500df30,
+ 0xdbf86bbe, 0xe21c7a0a, 0x7ba55d61, 0x9cfeb6b6, 0xcbc270f0, 0xdb9703c3,
+ 0xee3e509c, 0x0408b2e0, 0xe700d5f2, 0xcd215b9a, 0x332f54de, 0x68900859,
+ 0x3f88a132, 0x35f48c8f, 0x63f194ee, 0xdf185cad, 0xfcdfcfa2, 0xaeaf3e89,
+ 0xe127f607, 0x863ea2f9, 0xa09c9b9f, 0xfd3e5080, 0x625bcc19, 0x3b4d4e01,
+ 0x5967f9ff, 0xfb017ce1, 0xa78d9657, 0xcf572bb1, 0x5de98e31, 0x8fa115ef,
+ 0xfef81966, 0x9c8f1bd9, 0xdde7bb3e, 0x914658b0, 0x7f5d5d92, 0xffc9cfe8,
+ 0x2c2ef37b, 0x8b175e4d, 0xecc09cf4, 0x6cb1213b, 0x80e2c55a, 0xb7ab8a5e,
+ 0x2ffbc430, 0x992e1c05, 0x60382bcb, 0x8ed53d50, 0xf78dbcf5, 0x6dc03695,
+ 0xca1f3a40, 0x7784063c, 0x7e51f318, 0xfca16b04, 0x9062488d, 0x5a14c51f,
+ 0x93ac31b7, 0xd90ac1f6, 0x48009bf9, 0x9f3a252f, 0xe837f3c7, 0xe9c31bc3,
+ 0xf489bedc, 0xde30f486, 0x03cbdb7f, 0xf73d9e48, 0x3fc9031b, 0x09a53e55,
+ 0xe5534fbe, 0xbfa356d3, 0xfea2aa7c, 0xd91b40d8, 0x6afd0511, 0xedfa9bd6,
+ 0x83b1163a, 0x8f4093ce, 0x0cf29f3c, 0xa50f0fe5, 0xfe858a71, 0x1f989c52,
+ 0xaf59ae1d, 0xceaf2ae7, 0x005ddad6, 0xc5f2071e, 0x3980caae, 0x77df3593,
+ 0x287d7387, 0xf95e7583, 0xa8bff433, 0x21eec836, 0x79a0ccbe, 0x7ffd172e,
+ 0x8777392c, 0xb52fbe03, 0xa2067528, 0xca032aef, 0x48dff29b, 0x278029ec,
+ 0x617e719d, 0xb83ab1a9, 0xcdc65576, 0x71f20c99, 0x25c718a5, 0xabd871f3,
+ 0x9c548edc, 0xf42858c8, 0x0a4afc53, 0x228081e9, 0x58e101b7, 0x48f1e21f,
+ 0xc7036e34, 0xff1e1e93, 0xbee257f1, 0x8f724592, 0x46c18deb, 0x0d0323d2,
+ 0x8eb01eb0, 0xf909c68f, 0xda2870e4, 0xabb5407d, 0x45bd09c6, 0x11d9efd5,
+ 0x8dd30dbb, 0x2c7ffce2, 0xe79f993c, 0x2fcd1558, 0x39438550, 0xb97ea0ae,
+ 0x89c73d51, 0xf768a63c, 0x3fbc0ab1, 0xcbeec21c, 0x25cfacd7, 0x092f5f21,
+ 0xb95874bc, 0xcc7a8f9e, 0xa7b468a8, 0x1b0bfef2, 0xd0b0668b, 0x63a7bd1e,
+ 0xa83de81b, 0xcaae1fd7, 0xb47dc409, 0x4237e84a, 0x4822595f, 0xafd37167,
+ 0x3e08fac6, 0x2de00ff8, 0x778bdf12, 0x5dfce939, 0xcfaf5eb4, 0xebf95714,
+ 0xca336e37, 0xc5d96be5, 0x76170b3f, 0x851b3b70, 0x4df9cd7a, 0x01024729,
+ 0xb332734e, 0x20929ea1, 0x596a34bf, 0x59c1e230, 0x79f91135, 0xd4f891b8,
+ 0x46c4ae5f, 0xbbbf099a, 0xee7ebe24, 0x8fb4c121, 0x76e2caed, 0xba075db3,
+ 0x7e810e66, 0xf8e6896e, 0x12dddb52, 0x8376a26d, 0x7bfaf822, 0x4bedc541,
+ 0xe08e0f8f, 0xdb3bfff2, 0x0a61b235, 0x8d763563, 0x412396fa, 0x8235d90a,
+ 0x7feed022, 0xe1d0abe4, 0x639d0eb4, 0x3efdde51, 0x7083c39a, 0x3ecf002b,
+ 0xb5f3e7c3, 0xc2283feb, 0x1418f348, 0x3be0e9c1, 0xc3d0e5c3, 0xc9f86975,
+ 0xae1ce9e8, 0xb7e808a4, 0x1a2e77dd, 0x23b55bd7, 0xcbed70ab, 0x03ec7a01,
+ 0x2fbea34f, 0xe2fd993c, 0xf4f08ec9, 0xe67da787, 0x15c9e1be, 0xbaf0bcf0,
+ 0xcfa7ae79, 0xc1fbe972, 0xab2409bb, 0x9a7b7f16, 0x2363c6ef, 0xeb8b9bc0,
+ 0x1adb1eda, 0x8120674d, 0xa0a66f3f, 0x5f2e4ccf, 0x3059ee80, 0x8e1f5de4,
+ 0xec3ee0f3, 0x1988b235, 0xd0bb1f98, 0x79e60abe, 0x0839cc25, 0x3f570bf5,
+ 0x8affcbe7, 0xbed8fbe0, 0xf9cfa978, 0x77e6243f, 0x20e158e0, 0x391fefdc,
+ 0xffc86165, 0xb11ebe2a, 0xb1a3ad79, 0x22e7737f, 0xbf33e63b, 0x7dc12ab0,
+ 0xfde06ff4, 0x3f8fc2ff, 0x74d5fed4, 0x97064445, 0x1961d273, 0x98bfb06d,
+ 0x1279b270, 0x9917f9cc, 0xdf999246, 0x816bcf19, 0xc176342e, 0xd193be4b,
+ 0xac5d3933, 0x48573c40, 0x09de851f, 0xf9d49779, 0xd73c70ce, 0x5f349d99,
+ 0xb61687d7, 0x978dea43, 0xd42e82f9, 0x57f3a9f9, 0x65b90ee1, 0x33b420e1,
+ 0x90b69c87, 0xd4487fb0, 0x00f7e557, 0xbce27fa1, 0xc1322ec8, 0x90917e48,
+ 0xff576e2c, 0x1e4df645, 0xc6f09939, 0xcde322ed, 0x87f15e74, 0xff18b763,
+ 0x35efab91, 0x1a7ec60f, 0x8ff2364d, 0x67625b18, 0xdeb8bd03, 0xdd23e636,
+ 0xede4dd02, 0xec75c60b, 0xf4816d0a, 0xc11308b9, 0x99845cf3, 0x72abffcb,
+ 0x8eb9ca1e, 0x64d85f63, 0x3e789c8d, 0x4efb1642, 0xd0cdf373, 0xccd1e6ff,
+ 0x0ffa11b6, 0xf06dfb16, 0x8412d6b1, 0x3ffb383f, 0x4f72522d, 0x2c2227bb,
+ 0x7366efd4, 0xfa1db467, 0x62813573, 0x16c6764d, 0xc8ae3633, 0xb8b20c3c,
+ 0xb12e1f07, 0x9a37059f, 0xf3ef081c, 0x47b50a11, 0x5ea0ebb8, 0x6c2fd0e0,
+ 0x67069045, 0x7b8378c2, 0x3d0885da, 0xe60b302b, 0xe5e91c39, 0xa4216d84,
+ 0x8f962403, 0x9a46c5f0, 0xd7daf674, 0xbd2a0da3, 0xbc470d07, 0x9ce81a26,
+ 0x99b1b0f9, 0x2db0f7f0, 0x118ab6d5, 0xd47ec9de, 0xe74ade39, 0xce9109cc,
+ 0xcd93a406, 0xdb973626, 0x27f39a75, 0xa36c3e11, 0x8231dfd0, 0x7da5cf35,
+ 0xf64cd33f, 0x488fd059, 0xa0b1f85f, 0xfe7f754d, 0x01fcc0db, 0x221927a8,
+ 0x785dbaf9, 0xee13783d, 0x1f7c2abb, 0x67068255, 0xdb17c9ee, 0x4f1173f3,
+ 0x1d73988b, 0x6aa2f1f2, 0xde86a3c0, 0xbf78982f, 0x990357c5, 0x2ed3422f,
+ 0x6c6687fb, 0x94357c57, 0xbecf40f9, 0x5debc010, 0xd9fbe108, 0x5dbf055f,
+ 0xf7f3f414, 0xecc72bef, 0xfdb5fc7e, 0x7215cf4f, 0xc457f639, 0x62d4b95b,
+ 0xf374fd46, 0x51995f4d, 0xd2a8fe7f, 0xdf697cc6, 0xe608cf34, 0x513ce3eb,
+ 0xf34ad57c, 0x4886f351, 0x99efe085, 0xe1e1306f, 0x6bd8caa3, 0x874131e0,
+ 0x07fe9ec7, 0xbbd8f0eb, 0xff1a34ff, 0x6b8ccaa3, 0x9fac3ff4, 0xfc1d15fe,
+ 0xd2a6fd3d, 0x0b07edb8, 0xfa020f9f, 0xfd5be83e, 0x2fa07ed4, 0x9b166bd7,
+ 0xdeb9f905, 0x78f4839b, 0x12d02f65, 0xaf83d7d0, 0x27e6797d, 0x19f07f90,
+ 0xe8c71db3, 0xb7ce7530, 0x53bf21f7, 0xc86dcd99, 0x220349ee, 0xfd9d6853,
+ 0x1e8d5bbf, 0xad5ffa1b, 0xee1b4619, 0xecd6561b, 0x6cf44d59, 0x9ea27925,
+ 0xbb7ed5df, 0x3c9d65c2, 0x76790973, 0x8c4ce8d5, 0xd0c47d44, 0x7a885759,
+ 0xa117c662, 0xe1181fb8, 0xacfa88c0, 0x0333e585, 0xa8c2d39d, 0x8f0e7a9d,
+ 0x62a6768b, 0xbb035fbb, 0x1e5c39e2, 0x7b44e351, 0x6fc2a3d1, 0x734068f9,
+ 0x97235dac, 0xdf8d22b2, 0xfbd75e8f, 0x07d66bd1, 0x7ef8f9cf, 0x94708590,
+ 0x222fcdcb, 0x62d62efc, 0x850a76e6, 0xccc2d1f4, 0xd024a723, 0x73d50b87,
+ 0xbf7f7ad5, 0xea186247, 0x20ddaaa3, 0x1aa70f14, 0x105172bb, 0x31fd17cf,
+ 0xa246b3c2, 0x21c902f3, 0x5f8595e6, 0xba27db9b, 0xac3a1cc4, 0xff50939b,
+ 0xe7e408ef, 0x43c6ae80, 0x5de0ed0c, 0xbad087eb, 0x27e1fd17, 0x073f5133,
+ 0x5aedc679, 0x4fb4214d, 0x38c45914, 0xacf50c8f, 0x9e247dc1, 0xa35e7feb,
+ 0x46b4742f, 0x60787c1f, 0x6860f34e, 0x887eb6d7, 0x1ee5f501, 0x077be6f9,
+ 0x3abd73fb, 0x50cde894, 0xb9f1f437, 0x334f2f90, 0x9cebb1d8, 0x0ceb2fba,
+ 0x0cd9fe78, 0xd78c00fa, 0xd71a7206, 0x7a7750c9, 0x382fee24, 0xe59fee36,
+ 0x7e740975, 0x24ea0a2c, 0xa0795cbb, 0xf506cd3d, 0x4e6eea8a, 0xff3fba43,
+ 0xdc24d0e8, 0x2945ce0f, 0xd718e149, 0x192028f0, 0x29ae79e6, 0x30df7f9d,
+ 0x8bca246e, 0xce41cd90, 0x552ff4be, 0xb7ad17be, 0x5d4761d0, 0xa3f17de7,
+ 0x1f11ebda, 0xdf24ad43, 0xfe914041, 0x73b47454, 0x83da1296, 0xa39cf567,
+ 0x49b363e2, 0x29501f1f, 0xc29ab4e4, 0x82d499fe, 0xa166bf70, 0xcc7f3ff5,
+ 0x448f33e8, 0xc7cec87d, 0xe34410db, 0x6c1cc115, 0x173f2fc0, 0xb85ce3f2,
+ 0x5ef11232, 0xb6951864, 0xe7d6387c, 0xb60dc6f6, 0x0fdc50ce, 0xbd6c8c8a,
+ 0xb037f50c, 0xcd30d0ce, 0xb28d45f8, 0x7beb4ccf, 0x7f3a1de0, 0x5c308535,
+ 0x421fc35f, 0xfaee3ce8, 0xd419e583, 0xeeff00c7, 0x4f0bd420, 0x72dce859,
+ 0x7a42c9b0, 0x20e9c761, 0xe3f9af3a, 0x26770587, 0xfeb9fae1, 0xdbeb4090,
+ 0x34f9d891, 0x980323d7, 0x9dc7f31b, 0x3fb46ce3, 0x2c4338b3, 0xd4388e26,
+ 0x0534ae6b, 0x81af50f8, 0x35f683d4, 0xa589ab37, 0x3105afef, 0xea43373c,
+ 0xaa4d4521, 0x0b33858d, 0xbed107ca, 0x983fda99, 0xf9474ce4, 0xf40a60f8,
+ 0x5bed8c1f, 0xc195dea9, 0xdc6d1bce, 0xc62f10ee, 0x137ea78b, 0xa4cafeb9,
+ 0xe81c682f, 0x5337944f, 0x1ce2cbb9, 0x73f8f347, 0xc7d1db08, 0xf4ab8b3c,
+ 0xf55bc5f9, 0x7d1e25f9, 0x74af855e, 0x757bfe97, 0x2a779724, 0xe5e3fb9d,
+ 0x2bd72460, 0xd3f87c54, 0x5e7af769, 0x36b63e03, 0xea17e750, 0x69a3d73e,
+ 0x568e7342, 0xfd0cfbfb, 0x2c9fb043, 0xcfa1fe11, 0x42485f76, 0x3ba7d0ff,
+ 0x6a15242f, 0xc85da8e8, 0x1434e851, 0x76c103ed, 0xe910b425, 0xf5ec90d0,
+ 0x1a3c9d21, 0x19bb7440, 0x474802fd, 0xdf85d25b, 0x74e4832b, 0xceb3d0a1,
+ 0xfe76790b, 0xd20f64b9, 0xe5e652c9, 0x79cc56f1, 0x61c63c5f, 0xc3632905,
+ 0x6c8df435, 0x8c59f386, 0x11428134, 0x57f416a5, 0x7a199d82, 0x523da3e3,
+ 0x387073b5, 0xf08faf16, 0x250d38f0, 0x9557f91a, 0x68c92e63, 0xd2fc0958,
+ 0x2284a61a, 0x486eb63d, 0x4d055f09, 0xe894c30b, 0xbb799ad1, 0x059f330e,
+ 0x846953f8, 0xb8c1c64e, 0xa5342cdb, 0x3181396e, 0x6de7a86c, 0xf9b92209,
+ 0xf996c4d2, 0xdfd073da, 0x5dffdf05, 0xf709afac, 0xccf7da3c, 0xbcc0fd3d,
+ 0xb79dd836, 0x293af9da, 0x2c5dbfe8, 0x6f5fe7e6, 0x8e01d6f1, 0xbe3ed080,
+ 0x0fffed57, 0xd36ffbb2, 0x93f603e0, 0xb858e35f, 0xbb351e9f, 0x71d08fd1,
+ 0x943ca9f4, 0x64c7aed7, 0x1a07ff92, 0x3f3e932f, 0x99ca69b1, 0x16fbf19b,
+ 0xca0ac790, 0xdcefc1a9, 0xbd62f283, 0x175e50cc, 0xb344a536, 0x87397ae1,
+ 0xedf0be72, 0xfa06a139, 0xe71335de, 0x47b14e7d, 0xb3ecd68f, 0x2f5c5129,
+ 0x3ff2da2c, 0xd75f5ca1, 0x26c95faf, 0x44a7cd13, 0xf0a1dfc0, 0x0aa8eb75,
+ 0x747ae0f2, 0x7ea4ec0c, 0x68cc8c4b, 0x250fe8d6, 0x9e757f38, 0xb28a07e8,
+ 0x76e77589, 0xe764d69f, 0xef707b58, 0x0afd16f1, 0xb6fec0e0, 0x46023886,
+ 0xeab8ff5e, 0x2d4c69bc, 0x3d395a3d, 0x4c9d3eb7, 0x71c36d76, 0xcf793923,
+ 0x424d4d55, 0x390228ba, 0x229ae78a, 0xee0cf3a9, 0xd0579067, 0xa5b4584e,
+ 0xaf1c3ef4, 0x80c5b4e8, 0x4dafade5, 0xf970491d, 0x8de017d1, 0x79ff31f6,
+ 0x26772474, 0xe2a33ea1, 0xd12fe40f, 0x0d1f3a9d, 0xe80704dc, 0x21cf0c81,
+ 0x6eb0c91d, 0x2e9cfa1a, 0xdbea07d6, 0x70b7e4cc, 0x75fc448c, 0xff9fd7cf,
+ 0x3df37e6c, 0x982f88c9, 0x59f349dd, 0x80c5a1f8, 0xf2fe17df, 0xdbd434f6,
+ 0xa24e375a, 0x3b86b579, 0x6c5ca246, 0x87fe824d, 0xc2e79ef7, 0xfb3cc25f,
+ 0x79ee8fa0, 0x7ad00556, 0xf0cf3bf5, 0x37d9a7ce, 0xdfb173cc, 0x2a323f3c,
+ 0xdfac46a1, 0x7855b320, 0xdfcc4f5e, 0xdbcf337c, 0x2ed0c356, 0xc05cc721,
+ 0xed5eb8d7, 0x3c3ca68d, 0x93fb421f, 0x75de3e46, 0xe88183d2, 0x794735a1,
+ 0xa4e49b3c, 0x677b436c, 0xef31c6eb, 0xadf204fc, 0xca1b659b, 0x8e1cd6e9,
+ 0x1fc056bf, 0xa4d6c5ca, 0x7f9499fc, 0x2d5b64cd, 0xffd35c61, 0x7e91207c,
+ 0xcd185266, 0xea337f2f, 0xef001d53, 0x72f0852a, 0x4ddfdf37, 0xeb0dff34,
+ 0xe58f5b1f, 0xda37adee, 0x1fd21e30, 0x50f9bddf, 0x3321f1d6, 0xeb9e342a,
+ 0xce0a0997, 0x4833c543, 0x0b8c34ba, 0x7981f153, 0xf154b38c, 0xf8f332e2,
+ 0x9996c605, 0x95507e29, 0xc19f8867, 0x1fa17e5c, 0xfa15e515, 0xd9f9bb7b,
+ 0xc9faae5f, 0xf07dff19, 0xfe9eb119, 0x36897072, 0xe256f5cf, 0xdf7ea5e3,
+ 0x47e4fd4b, 0x45b95f99, 0xfb5569d8, 0x12a3c749, 0x6f1577c9, 0x856f0285,
+ 0x9cbcc546, 0xb7823fcb, 0x7ca768c8, 0xb5ad91a1, 0xd406e468, 0xbd816b5f,
+ 0x97205f62, 0x679e502b, 0xf955e4d6, 0xadefcea9, 0xa86fbe28, 0xa73e77e9,
+ 0x29cfe9e4, 0x5be67b1a, 0x33d87d51, 0x7df26f5d, 0x9d89a5e2, 0xfb41ef8f,
+ 0x9ecc9346, 0xfa3afa41, 0x30c1d08f, 0x66a3f68f, 0x6c2c078a, 0xbd21c88c,
+ 0x0753bc32, 0x59fe9ab7, 0x44d2fdc0, 0x376be76e, 0x681684b6, 0x12d609f5,
+ 0xaeb34b3a, 0x2b97f585, 0xf0019e31, 0x783596e2, 0x9514df3b, 0xd1727a83,
+ 0x0639f15b, 0xd625ff48, 0x7949b37d, 0x77d21376, 0x3dce8583, 0x35ce6fed,
+ 0x37f6fb60, 0xa0fa444b, 0xce8fd283, 0xa1f8e127, 0xea974e06, 0xf8a39778,
+ 0x38645c7e, 0x282df4fb, 0x931f7fa7, 0x7f6346bc, 0x268c322a, 0x9c0f7b3d,
+ 0xd06e118b, 0xdfa3d67f, 0x5fe7ed59, 0xd1c10a51, 0x69e170de, 0x9bf3e3e4,
+ 0xfb234713, 0x8fa437b7, 0x4e9e2274, 0xb8c3498f, 0xe347f682, 0x7bbfc8ec,
+ 0x4483ca4c, 0xec421b47, 0x7f6a9fc8, 0x17fa0e38, 0x8dc61bda, 0xfb4a73c5,
+ 0xe42f0e69, 0xf502dce9, 0x564fe8dc, 0x28350dfb, 0xe78098bf, 0xe44cb7bd,
+ 0xcffe5887, 0xf7d41894, 0xdb7dcd43, 0x523f5167, 0x9abf7c74, 0xef1fede6,
+ 0x2d47afee, 0xefc5fe02, 0x0965fafe, 0xf1875aab, 0x307afef6, 0xeeadd01c,
+ 0xf533e468, 0xb0fb4bcf, 0xba5c7ebf, 0xae8b6beb, 0xa793889d, 0x42af804a,
+ 0x748db3e0, 0xfb70f5ae, 0x4fb97ac1, 0xe8d8cb7f, 0x44f76a64, 0xb7e6bfd0,
+ 0x9cf5d668, 0x01631981, 0xcccce7af, 0xaaf28b1a, 0x07b87d1f, 0x5a1c533f,
+ 0x1cb9d07f, 0x8c0e554f, 0x6ca36e7b, 0xb7c1fb47, 0xe1fd8fd5, 0xf7156c64,
+ 0xc13f0b37, 0xe10d8039, 0xd7bf5feb, 0x27e2a3c3, 0xfd55f840, 0xf614cfeb,
+ 0xca7f8cc8, 0x577001cc, 0x483c9934, 0xbe3b416f, 0xa41efc78, 0x2d9346b7,
+ 0xa9fb2159, 0x1be3e283, 0xefaf8a64, 0xba1f3c68, 0xc37be514, 0xc1ac9b18,
+ 0x647fec2f, 0xbfaf6d07, 0x52f68d1c, 0x3ffc87e8, 0xecc7a6ae, 0xc1fd8f48,
+ 0xbf968ce1, 0x82653d9f, 0xf8453d9f, 0x7c77da81, 0x1672869c, 0x1a3395e4,
+ 0x1fed2df9, 0xb717ae66, 0x02fa458c, 0x4e3142f8, 0x8573c3bf, 0xa36b3af4,
+ 0xb1f4f0ec, 0xcda3cb0e, 0xc9be0fdf, 0x9e00f87a, 0x0a8f08e5, 0x69d28567,
+ 0x5aedfdc6, 0x0dc9d07e, 0x3203abc5, 0xf513dfb9, 0x3c8d85ec, 0x36e1716e,
+ 0xbac0a3d9, 0xe9ff4e4c, 0x0bd400c1, 0x4ec8931f, 0xf84f2b92, 0x5fd42e60,
+ 0xf94ca8fc, 0xfc1e3b03, 0xbaeb84c0, 0x947e44cd, 0xcdb34dc5, 0x1f8b37c8,
+ 0xf68d9893, 0x8fce8727, 0x232e44ba, 0xa5fdfcb8, 0xc16e59ed, 0x77df7edf,
+ 0x30759bac, 0x93235312, 0x53fede94, 0x8d1c3bfc, 0xb7fe2d76, 0x78a6c86b,
+ 0x5fbfbbc4, 0x4e003db5, 0x6a0764d8, 0xf30373a1, 0xf6bf78f1, 0x70928f86,
+ 0xffbf5cbd, 0xfa6fd93b, 0xc8d603e3, 0x61dbb2fd, 0x80dafe1f, 0x66797df4,
+ 0xbff51f7e, 0x5de87e12, 0xea3c7726, 0x5c770789, 0x474afb21, 0xf7f73f03,
+ 0x07733fdb, 0x2fb7f3f0, 0x9902ec80, 0xe474db5e, 0xd0b7d007, 0x667aef1e,
+ 0x2067acdd, 0xa4dfb01f, 0x435d5a20, 0x902f8982, 0xfd358a0f, 0x4bb0fcaa,
+ 0xdfd515c8, 0x8bf095fb, 0xd55efeab, 0x870febff, 0x4afdffea, 0xa2e3fff8,
+ 0xb3a31bf3, 0x19dfefd0, 0xf7f0faca, 0xe55717f7, 0x6fe54f1f, 0x9fc3ec47,
+ 0x61e9cfc0, 0x19835efc, 0x1cac63f6, 0xbbd66232, 0x9d305e78, 0x725ce994,
+ 0x6889d8e0, 0x675d7cad, 0xbb450e6c, 0x935aa5ce, 0x9274c7f0, 0xec74d9fd,
+ 0xca32730b, 0xa3273817, 0x3c82e9be, 0x304d777e, 0xb776b43a, 0x1ef988bf,
+ 0xb4a34e8b, 0x8a38e8dd, 0x5b76c6fe, 0x62f519a1, 0x7985b1d3, 0xd8a6cf48,
+ 0x3f1f3342, 0xeb8c9ac7, 0xfa246612, 0x8ea8d75f, 0xfec36cdb, 0x48477f55,
+ 0xd21b49d8, 0x9ce67161, 0x0877f66f, 0xefea897f, 0xd47ff6e8, 0x52bf26cf,
+ 0x7f8efe7f, 0x880c758a, 0xcc5469e1, 0x2acbd377, 0x799e4f32, 0xefdfe948,
+ 0x9fe57201, 0x37e5feb8, 0x7c8d107c, 0x6fb8720b, 0x79af477f, 0x43bf9f5e,
+ 0x3fb85189, 0xfdbe7ba2, 0xf57a3bf8, 0x8efe7d7f, 0xe3f7fdde, 0xffd5e8ef,
+ 0xba3bfa75, 0x8efee5fb, 0x140dc3b5, 0x94f6b37f, 0xad0ddb85, 0x116f7fdc,
+ 0x37d6b2fc, 0x564fe759, 0x9c9b3753, 0xb5c37680, 0xd21e72b5, 0xa15b25e7,
+ 0x14d3f90d, 0xacf3a066, 0xc3c8e4c5, 0x2c25a0f3, 0x72e9023c, 0xcd0a4c48,
+ 0x32d84aeb, 0xa02bcfa2, 0xbec9b9ee, 0xf31f2cb5, 0x942e076b, 0xef499db9,
+ 0xfd0108cf, 0xe3f7ec99, 0x7ddf62ad, 0x4c1456cf, 0x629bc0fe, 0x90c57e34,
+ 0x1714c3ac, 0x839deac6, 0x061f7f90, 0xe899a57d, 0x26ec85bc, 0x1bf9c966,
+ 0xd3b0cfb4, 0xd0fa8616, 0xba670095, 0xd397c34d, 0x8f42cc63, 0x3ca025f2,
+ 0x4a6ab373, 0x0997f55d, 0x4afdaacf, 0x4eb1772d, 0x2bf23bc2, 0x19c7a505,
+ 0x77af2a15, 0x0c7dd3a6, 0x5eb74701, 0x1bb046f0, 0x4d2dfee3, 0x4c7f24ff,
+ 0x2673b187, 0x8dbc57da, 0xbf169072, 0xe45f040b, 0x76417e24, 0x376c0afc,
+ 0xa54dfd00, 0xb5b7e4e9, 0xb8448e74, 0x3ff6be0f, 0x5cae5123, 0x841d2a69,
+ 0x7d4177df, 0x9dcdc7da, 0x943f5a15, 0x87e99fbf, 0x9ffb7d31, 0x89ad3576,
+ 0xe0f63847, 0x69641db9, 0xa4ffcac5, 0xe6567cfb, 0x0fca15f8, 0xce837206,
+ 0xe5b3f509, 0xbd27a889, 0xe403ba0f, 0xfef81b33, 0x3cc8999b, 0x68aa57e8,
+ 0xae2e7f7a, 0xd9964557, 0xc0bf4786, 0x158fdc51, 0xe1b56598, 0xce15d87e,
+ 0xfb8cc0e9, 0x9fb60a6c, 0x16eb8112, 0x77e5c91b, 0xeb7babf9, 0xa5bf80dc,
+ 0x942c7bbf, 0x353efe01, 0xbaff9156, 0x43cfe76c, 0x27dffef1, 0xe2287746,
+ 0x9c8f53fd, 0xf29e97d7, 0x3e5f215b, 0x3323edfb, 0x9a76ce89, 0xcf2e3c6c,
+ 0xee692c11, 0x5976bae3, 0x27d0167c, 0x50976a2a, 0xcfe4381c, 0x9fc3fcf2,
+ 0xe96979e3, 0x2b458ff3, 0xbdfeb821, 0xc412a2e2, 0x507447be, 0x2e51f351,
+ 0x07a55fe2, 0x1e38faff, 0xbcbae1c6, 0x80f302f2, 0x9073fabe, 0x03eaa1be,
+ 0xde9197a0, 0x847daaef, 0x104bcae2, 0xdbbdf1f6, 0xe223193d, 0x71b1c7c9,
+ 0xf1576e78, 0x24513cc1, 0xb757e517, 0xedcb3c8f, 0x4e6e3c41, 0xcd5b53f0,
+ 0xfa25431f, 0x5d31cfce, 0xfc5f67de, 0x4eb3fa3d, 0xd99ec859, 0x0edf7edf,
+ 0xc8d304fb, 0xd05ea54f, 0x42ff4abd, 0x79332ecf, 0xfa0a7b9e, 0xefcd3b2b,
+ 0xe5ed9429, 0xdee970fa, 0x09b83fd7, 0x9f74a3d6, 0x9f067229, 0xe7de3046,
+ 0xf80f5ee8, 0xeac9ed1f, 0xf97d2c7a, 0xf87f8e75, 0x9ef0d3fe, 0xf7dd2975,
+ 0xed3a347a, 0x0931f1fc, 0xef0cb7be, 0x7cbc7d63, 0xff57e47d, 0xa7de7a49,
+ 0x262c49af, 0xc47b77b9, 0x58a3ad0b, 0xf375eea7, 0x23faa7ab, 0x76c1f5d5,
+ 0xd5f98fa4, 0xd30c49fb, 0x29a83dc5, 0xbbe137d0, 0x1d8b43e4, 0xe2f250f1,
+ 0xcf9c508a, 0x4e32e305, 0x1e7fdbe7, 0x4af1f78d, 0x1b68ee4c, 0xc97bfca5,
+ 0x7c263fd3, 0x63fe3e2c, 0x47320fae, 0x3bfc819c, 0x147ff26e, 0xb74bbb6f,
+ 0x976c941f, 0x6fe4ee29, 0xafb79646, 0x62513e0f, 0xf0b99cb9, 0x7dfc858c,
+ 0x00bdc417, 0xdc5909f7, 0xe49fbc33, 0x00efaab0, 0x6ffe5105, 0x1efe8e82,
+ 0x04fd5063, 0x7efd2d56, 0x4188e896, 0x79aae4f9, 0x4bd719b8, 0xa6253e3e,
+ 0xe8c3f885, 0xbe91f816, 0xe127fe86, 0x649f4e77, 0xb0f6a2df, 0x4d9abb5f,
+ 0xc754a764, 0xa78c407b, 0x25f64f69, 0x02503b80, 0x9a217a79, 0x6e75f495,
+ 0x07e6219c, 0x434ccd7f, 0xe77e1a67, 0x81b35ffc, 0x938beae8, 0xe5ba7f9c,
+ 0x8f20a780, 0x7c9b35ea, 0x7dbca131, 0xe7a7d202, 0xefb41cc0, 0xba2deab9,
+ 0x5e9bb6fd, 0xcf824c6a, 0xdd2ae5f5, 0xb446dc00, 0x03f4a90f, 0x06f12f78,
+ 0x8427f9f3, 0xd16e3ee3, 0x1c2e21e9, 0x7f77b42f, 0x162eff2a, 0x562121f2,
+ 0xb6d80f2f, 0x5fbaeba8, 0x4d5f9bdf, 0xf717afc4, 0x87e0fa1c, 0xbd172fc0,
+ 0xc9fabf2a, 0x2d7e3f4f, 0x7e6fa979, 0x6efde8bd, 0x92effafc, 0x91fb8ba7,
+ 0x456293a7, 0x5fc0ab1c, 0x37e8b797, 0xc7fa57bf, 0x6c3cbfa3, 0x6f5b7a11,
+ 0x6a4ec8b9, 0xf15081df, 0xd2ddd2a5, 0xa107ca17, 0xde9baa5d, 0xf414ba54,
+ 0x2a8f43d6, 0x7ef37ddd, 0x821e5fe4, 0xd9789a65, 0x73f786fc, 0xcb5d6013,
+ 0x19f9f91a, 0x3cc11fda, 0xc741cbe0, 0x0475561e, 0xe4f757ef, 0xaf797e3d,
+ 0x5f877d5f, 0xbeafdf3e, 0xab2f9753, 0xfee6643f, 0xed7e6598, 0x38ed7e7c,
+ 0xff87be7d, 0x1e3ffc04, 0xb11fff9b, 0xebbb87e8, 0xc9f875cd, 0x493a7065,
+ 0xdab78c2f, 0x233a4fc9, 0x303a5f82, 0xfb408fe6, 0xe77a6f7a, 0xd636b2fc,
+ 0xa8fd8951, 0xfbbfdff5, 0x3ece119e, 0x7c755bf4, 0x3f7bd9b3, 0x0795a1c5,
+ 0xdd11dd93, 0xd9eed835, 0xa43e2dbb, 0xd17ef527, 0x47f9a0a9, 0x3339a4d0,
+ 0x2c68f9d4, 0x83fb9bb4, 0x2f30eb69, 0x96508c1d, 0xa0b7bea3, 0xc6d1ee85,
+ 0xb05b9c19, 0x1ceaccbc, 0x4ba7a684, 0x01f4ce89, 0x11f9afc8, 0xfe7712e2,
+ 0xe13efc88, 0x94fd0b77, 0x62e5e7ef, 0x536abb8d, 0xdb3e2006, 0xf6bd5c05,
+ 0xa606ab9b, 0x2e51e7bd, 0xebfdd1e2, 0xe5cb18bd, 0xff2f67f9, 0xa04fcaee,
+ 0xab7f8bab, 0x5c79434b, 0xdc11b52a, 0x9f1f7657, 0x8ddfe02f, 0xabb07bf8,
+ 0x700cc933, 0x980f7997, 0xe02ddeb9, 0x7da67637, 0x5ea2fc23, 0xc553de39,
+ 0x00c694f8, 0x5f9617f2, 0x44633335, 0x3209faef, 0xf3a2b77f, 0x01c51267,
+ 0x7bb41fd2, 0x3ddfcdd5, 0x9f2e18b0, 0xf6768d9c, 0xb08e3c11, 0x41deecce,
+ 0xb1859cf1, 0x0aef1744, 0x77436cbc, 0xb3d3f005, 0x68190d39, 0xf2027aff,
+ 0xc05f9001, 0xdb9e3314, 0xe483988b, 0x7ece7373, 0x608fef5a, 0xf3fe31bd,
+ 0x51e758ed, 0x835fef9c, 0x0c9595fe, 0xf127f2ed, 0xa72d72fb, 0x5e907703,
+ 0xdefae139, 0x6cc59931, 0x882f7e26, 0x25994fdf, 0x99b3f9fc, 0xb951de83,
+ 0xfca9398b, 0xe94dcc07, 0x03b37689, 0x98f35ded, 0x30f7f287, 0x11fbd51f,
+ 0xb17ca16b, 0xa542f9c4, 0xfba7a02b, 0x5d3d3922, 0xe3f28188, 0x57132341,
+ 0x7f5eb42a, 0x782b7a45, 0xce087d22, 0x0efa84fb, 0x9f54754d, 0x770fe2f4,
+ 0x8f979081, 0x413f3ac7, 0xfde5743c, 0x1bf3ee8d, 0x775a3eac, 0x4d99ae35,
+ 0xffeb128e, 0xdcd7fccd, 0x0bdf6dd5, 0x4c3c038e, 0xd53a4b15, 0x3df64a51,
+ 0x4ee82e35, 0xe453df41, 0xeb0e1660, 0xfbf0acd1, 0xde914c9e, 0xbcf9031e,
+ 0x38c33289, 0x315637d8, 0x46378fa2, 0xa5cf14c9, 0xa299ffca, 0x671319df,
+ 0xf5001daf, 0x92d1ff72, 0x5a7483e9, 0x78b58ee4, 0xa06f2775, 0xede67efe,
+ 0xf748d9ac, 0xdff5535a, 0xcbd70c67, 0x063803d3, 0x96e027bd, 0x99995f71,
+ 0x1c1fafa9, 0x1b91f627, 0xcb5f0dd8, 0xceaafc3d, 0x65c66ba7, 0x27cafa33,
+ 0xe22339c4, 0xefcb6500, 0xc53e68f8, 0xdbd91ad3, 0xf55cf063, 0x2b579f0e,
+ 0x91402fec, 0x2b4ae3ec, 0xda549fa5, 0x9bf60398, 0x29632acf, 0xe854ab6d,
+ 0x99ce33bb, 0xa0768710, 0x2fca0cca, 0x88dcfaac, 0x4eab09fb, 0x085771a3,
+ 0xf8366b3a, 0xf49f140c, 0x9efe448c, 0x39cd0115, 0x15b78041, 0xb0ed933b,
+ 0xbd696cd2, 0xbd8208f7, 0x8b9f97d0, 0xe8e8b9cb, 0xfe9823b2, 0x4e99d628,
+ 0x773c9ffd, 0xf90c1df7, 0x7904c614, 0x7b3c68e2, 0x2f844304, 0xdc69da54,
+ 0x29b32b4f, 0x39ce3fbd, 0xac5feb02, 0x0e9c1074, 0xc9d139f6, 0x1ace7b1d,
+ 0x14fea013, 0xa9b8a245, 0xe3cc1d5b, 0x6adafe01, 0x6b7c72e2, 0xfe8ed59c,
+ 0x662389a3, 0xa1807f6d, 0xc38e769c, 0xbe9aee7e, 0x338e0a64, 0x11817b33,
+ 0x1fe0fdeb, 0xf724458c, 0xe8b5dbd0, 0xcbc9f997, 0x4449af4b, 0xca0c977f,
+ 0x700f689d, 0xb9d325bf, 0xefc8cbb6, 0xe29d77ab, 0xbf97d1f7, 0x72831292,
+ 0x8949b975, 0xfd9a78c1, 0x11713fc2, 0xb1a8c5d6, 0xfbdc5cc3, 0x340bd1a7,
+ 0xc5f4b4f2, 0x421f2b86, 0x099c2fbf, 0xdf3c63b7, 0xbfee70c5, 0x082efd83,
+ 0x4dda7ee3, 0xb2d13c6a, 0x541fbc20, 0x804efc21, 0x4ef461d5, 0x3faf204c,
+ 0x1c84c5f6, 0x4f1c07e4, 0x6c72f331, 0x13e2f69f, 0xf4a27f83, 0x5bcbb78c,
+ 0x9053e1fc, 0xfcf784bf, 0xc4ba1f61, 0xbe78edbc, 0x9304d770, 0x324327df,
+ 0xa8dde206, 0x8f6e2fdd, 0x15e535ff, 0x3dd1cae3, 0xe52fd9f8, 0xe5087fcf,
+ 0xff5e76e5, 0x2a1fc7f9, 0xb1f4c06c, 0xcec897f2, 0x7c461716, 0x25a9e8bb,
+ 0x8d5d2037, 0x10c076d8, 0xac6fdf0f, 0x531abb39, 0x83ca5e17, 0x247b51f2,
+ 0x8e7cef19, 0x835e4da9, 0xdb7c3ceb, 0x39e307e7, 0x977de9ca, 0xf7fe041b,
+ 0x87977bc6, 0xa57abc81, 0xf77bf671, 0xee1c2d30, 0xbdc22b38, 0x73f7ccc0,
+ 0xc871c80f, 0xd866725f, 0xef942ec9, 0xe7d7127e, 0x8eda3392, 0xe0cebf72,
+ 0xeb09bd0e, 0x89f7e19f, 0xe557e52e, 0x727ee3c6, 0xb63d230b, 0x2e67547c,
+ 0x544b0fdd, 0x4b1786f0, 0x1e6a7a7c, 0x2bfdf3a3, 0x2a5c3fb4, 0x3ed1dab3,
+ 0x65caf25a, 0x34d83bd2, 0x9f27c766, 0xfcf2d52e, 0xb41d9323, 0x78884f7e,
+ 0xaae35758, 0x20ef7c64, 0x7da569d3, 0x248cb581, 0x06244339, 0xbb26b6f5,
+ 0xde5f51a3, 0xb590c23a, 0xd799e946, 0x0dfbc50f, 0xd013f1a7, 0x677c46eb,
+ 0xf961de81, 0x67b40ce3, 0x51085a10, 0x1e618e27, 0x33979279, 0x89fa019f,
+ 0x2ff3c83a, 0xa6def93c, 0x3b1903b5, 0x15bf9f12, 0x970fc6e5, 0x5f212406,
+ 0x91ee287d, 0x77f047bb, 0xecfde615, 0xfa8e7457, 0x50df61b5, 0x8dee8bf4,
+ 0x13f7e70b, 0x2efdfccc, 0xd61cefd0, 0xf0dfb8b1, 0x024abbbf, 0xc2bc52ce,
+ 0x6d0e299c, 0x945eed1c, 0x2a9859e5, 0x0cf99262, 0x26edf5f7, 0xef080ee6,
+ 0xe9921ef9, 0x2384bc26, 0x8de5505e, 0xbdf74658, 0x8637d198, 0x1e39d1db,
+ 0xb714de60, 0x982afee8, 0xd7e7f4e0, 0x5e7e38d6, 0x373333ab, 0xbbba13c6,
+ 0xc6e63df8, 0x7e179690, 0x2e37fd07, 0xbaeb4819, 0xe309ef1f, 0x728817ba,
+ 0x71bddf71, 0x677f345e, 0x58f9c2c2, 0xd1a2677d, 0x38f9d9e4, 0x52c41796,
+ 0x4f8253fb, 0x3ddf314e, 0x7773cfe8, 0x47bd199a, 0xa7dfc611, 0x4e955ea8,
+ 0xff757571, 0x11c7f15a, 0xe2ac57a8, 0xa3d5a4f1, 0xee31eb3c, 0x2967faab,
+ 0x97c90e1c, 0x4bf6c2e0, 0x569e4902, 0xd0e23817, 0x199cec8f, 0xabdef744,
+ 0x30e23877, 0xfd1e369e, 0xbdf1c31b, 0xa70fc80b, 0x807112f5, 0xc7c4388e,
+ 0x90870b53, 0x43c5412f, 0x19ce5c5b, 0xc579df5c, 0xaf48033b, 0xb9d0f612,
+ 0xa670e7dd, 0x2553bf5b, 0xfed043ab, 0x5de3aea0, 0x0fce994e, 0x16d9ebfe,
+ 0xf28338e7, 0xf5542d94, 0xe2115f64, 0x2b4eb5e9, 0xb9029fc5, 0x6dead18d,
+ 0x355dbaea, 0x3c202f3a, 0xe7ae661d, 0x9cbf4aba, 0xe9a2b779, 0x7f9dafc7,
+ 0x5659bcfb, 0xd6b96f7e, 0x7df7fb42, 0x59716f42, 0xdea3777c, 0xfce0cf32,
+ 0x2d77fb02, 0xea246cfd, 0x32b39127, 0xce1c5006, 0x7a43329b, 0xebd6233a,
+ 0x8271e30c, 0xdd2165ee, 0xde612def, 0xfe0893f9, 0x11d192de, 0x15f98c57,
+ 0xabfde8c3, 0xe9271116, 0xfea890ae, 0x75771119, 0xc78231a6, 0xfabacd23,
+ 0xe3cc1a78, 0xb795fe4c, 0x677c01c7, 0xdf3c79ea, 0x78f2565f, 0xa7358adf,
+ 0xde95ea93, 0x3577baf3, 0xdee2377f, 0xb8a53fa5, 0x9ff6feef, 0x7ef4cb7b,
+ 0x11de257b, 0xf3851f1a, 0x728b9abb, 0xecb4be25, 0x3ef862c9, 0x8119de31,
+ 0x2dcc2bdf, 0x8a8f8815, 0x849dfffd, 0xc3475b7a, 0x408efbf3, 0x19d9877a,
+ 0xa7abe543, 0x3b1cff26, 0x8575fa13, 0xe403d611, 0xcef10bca, 0x4d772c04,
+ 0xbb61a5f6, 0x2e735336, 0xbd3fa5e9, 0xb3eefd3e, 0x12759dc6, 0x8d81f9ea,
+ 0x9eca9415, 0x45c70891, 0xa52a17c9, 0xbec91e10, 0x85f366d2, 0x4adfa186,
+ 0xf1fe83ec, 0xb45a04b9, 0x1f90cbf0, 0xdef143cd, 0x171e5ea5, 0x14bf5fe5,
+ 0xf5deb1ca, 0x5ce3577e, 0x37eac34b, 0xcdeb4cdf, 0x8c4cbe7c, 0xf7421827,
+ 0xf2bd2fa1, 0x9e369a7c, 0x0ded3fc0, 0xcbff9f2f, 0x6d739712, 0x369c9de2,
+ 0xdb2bde26, 0x777ee963, 0xfb42e506, 0x674138ee, 0x77da8e9c, 0x7cb47ba7,
+ 0x6bdf1ddb, 0xb8a58ef7, 0x2c77872d, 0xff2ae7ee, 0x2477ab33, 0xf0ce0bdd,
+ 0x58fd448e, 0xbe5827d5, 0x61a7de97, 0xd61a6f1e, 0x7b7033af, 0xd2ee3a90,
+ 0x7df81217, 0x8b972b7f, 0x46185f4b, 0x7ed5fdf7, 0xf4cf35af, 0x7e5d66ad,
+ 0x2f9f47a8, 0xf772e78a, 0x8eedbfb7, 0xde8592df, 0x3d7514ca, 0x1b8efe15,
+ 0x496ed3f1, 0x0903cbc5, 0xc87cf163, 0xdfd9bf68, 0x70a85d0f, 0x9fb9e239,
+ 0x8828cf19, 0x7f21f65f, 0x90cead37, 0x940efb3f, 0x38f34fe7, 0xf951ba95,
+ 0xaddca3b7, 0xf4843edb, 0x274376d2, 0x4fdc09d9, 0x75fdfbf1, 0x9404ce61,
+ 0xfe6215a3, 0x63da549f, 0xcf867df1, 0x3bd2572a, 0x8a789f1c, 0x942e5012,
+ 0x20368e9d, 0xc35a7c1f, 0x7b6513fd, 0xdf3ee853, 0xbe0fd3ea, 0xd7940777,
+ 0xfd9135ed, 0xa1f76ca3, 0x68f38c68, 0xe3b465db, 0xde6ca8d1, 0xaf519b73,
+ 0x7b2ddb28, 0x7b472899, 0xf5f79b6c, 0x49f7ac50, 0xbfbd044d, 0xebe06752,
+ 0xc72dfee3, 0x2c3aff87, 0xd58a8cf1, 0x644b31fa, 0x7f1c66f7, 0xfe3d2ed8,
+ 0xc27ba93f, 0x4afe846c, 0x147b9cfe, 0xaf08f7e5, 0x7ac6fcbe, 0xf15afe7d,
+ 0x9ce9bdf3, 0x652ccfc7, 0xbe4623ee, 0x75da196e, 0x917faff5, 0xe076ef79,
+ 0x877d5eb9, 0x78f1f04f, 0x8f3316ef, 0x78d6b853, 0xa1fef16e, 0x2f9dee83,
+ 0x3765e6c8, 0x3a6dfda9, 0x5b788b9e, 0xfb4488f0, 0xd39782de, 0x3d1ca30f,
+ 0x74de6fbb, 0x23ceef4a, 0x71e7a83c, 0x73c7365b, 0xee8956f1, 0xef162c3b,
+ 0xf5ae1618, 0xe4dd7f8b, 0x7d656717, 0x5aebbf9a, 0xb44be07f, 0x555da29f,
+ 0x39e9bf1f, 0xd2de7a84, 0xb79d184f, 0x9727e3fc, 0xd16d7cd6, 0xbaf3e7d7,
+ 0x1397076f, 0xadb98fb0, 0x9c05c748, 0x40c3ab8e, 0xf7c4c94f, 0x7e9386ac,
+ 0x992ff750, 0xc79c5fdf, 0x8f568def, 0x5605efe2, 0x7d41bbcf, 0x25692b4f,
+ 0x558175d2, 0x9e7c0fe8, 0xa9e24bd5, 0xf7dc29fc, 0xf223d465, 0xa59e3073,
+ 0x4e7e31fa, 0x1f39978b, 0x74045fb2, 0xfb85a3bf, 0x7496f56b, 0xd9aaf76a,
+ 0xa4f1dff9, 0x1e29d9af, 0x33ac3ab1, 0xb891ee84, 0x583f6faf, 0xde9fad6c,
+ 0x53cf811a, 0x7a4f044a, 0x6df6819b, 0xe344a66b, 0x52356c66, 0x96c1b8fe,
+ 0xbccdf085, 0x0f8bd5f9, 0xde31fe21, 0xc7fb610d, 0x184f5fd7, 0xcd087e8b,
+ 0x8107be1f, 0xe9c63269, 0x28605f30, 0xec48cdc6, 0xf5ae8e9c, 0x35bbfc79,
+ 0x6b9fa7ba, 0x5e6fefd5, 0xabe9dbff, 0x073b1e70, 0xd301a6f2, 0xa8de1a54,
+ 0x6b8f37b5, 0x1d7278e4, 0xc4c19e63, 0xeb590e6f, 0xc09a9e07, 0xfeaf93fd,
+ 0x7831a5e5, 0x31d89a9e, 0x83b7007c, 0x5539d2a7, 0x31777bf5, 0x71fa0065,
+ 0x06531abb, 0xeba75fa0, 0xece21ca8, 0x16efde43, 0x2a17e876, 0xd47694ad,
+ 0xef192ab0, 0xf24eb029, 0xac6bba7f, 0x7b7d2fac, 0xffb74274, 0x7163c986,
+ 0x577898fd, 0xbdf89f23, 0x66da9d7b, 0xd91c6a7c, 0x77f8ff1b, 0xfc37134e,
+ 0xf68af17d, 0xeeebc46e, 0xbedc9680, 0x0b2761e2, 0xf83ccdbc, 0xf80159a5,
+ 0x61dc686e, 0x86f8fd40, 0xef8e831a, 0x3f082427, 0x1a3668c8, 0x30799ae1,
+ 0xd7132420, 0x0f6ca8e3, 0xf71cf050, 0x87d9d9b9, 0x478feabe, 0x63cf1fec,
+ 0x7bf0250f, 0x5e4dfb11, 0x5ff797d2, 0xacfdd2b2, 0x69557306, 0x1f9e705f,
+ 0xf9bce1c8, 0xbf332cc2, 0xafc7ad27, 0xf8fecf8a, 0xd785dfe0, 0xbec11d89,
+ 0xd46fb41c, 0xeb476e30, 0xae5c6f45, 0x6462ed74, 0x7112ed8f, 0x187b5d75,
+ 0x2a0085c5, 0x11209d1e, 0xf5a6df7f, 0xefd7a467, 0x4fe5017b, 0xfe44a345,
+ 0x8b630afe, 0xd79bee99, 0xf7e8c987, 0x7788a519, 0x11b68c61, 0xf07c3473,
+ 0xf0918250, 0xfda6e87a, 0x97b8e0f7, 0x8f14ccdb, 0x49dc38e7, 0x372e69f7,
+ 0x57d0198e, 0x6843db7c, 0x55f8d05c, 0xd364ae5f, 0xf8d9efb5, 0xb2cdc3d3,
+ 0x68f91e33, 0xdd409ef8, 0x969699f7, 0xafbafa07, 0xefd6271b, 0xe799e5ba,
+ 0x767913ff, 0x4e679552, 0x3bde7b59, 0xc59e5bd7, 0x96cf25f4, 0xe20c4a4b,
+ 0x4a53797b, 0xf2ebae0c, 0x7d514d37, 0x00bdb3c9, 0xf7fc0287, 0x4c43e03b,
+ 0x9e416a3b, 0x6791a8dd, 0xfacf20b5, 0x258eb7d0, 0xf43befa8, 0xff3ccf23,
+ 0x2f6cf237, 0xe63eb3ca, 0xae04d7f9, 0x6cf2ab77, 0x9259e364, 0x0d6b2367,
+ 0x0ff378ba, 0xb93d8412, 0x4526795f, 0xd9bf41cd, 0xa83d9351, 0x7c41ba0f,
+ 0xc40cd5e2, 0x0e38a627, 0x81c8b5ca, 0x75ae4edf, 0xeb5caf5c, 0x5dfe1f87,
+ 0xdae555f8, 0xdd1857f2, 0x774dedb3, 0x7977e88c, 0xb435c803, 0xb97136eb,
+ 0x9189bcb6, 0xcf2fe93e, 0x33c97a32, 0x7c2bf546, 0x3eabbdbc, 0xa17b89f9,
+ 0x930ed1bf, 0x47f50add, 0x2cb7c8f7, 0x1c8b7cad, 0x3b7c8fd8, 0x4df2cdfa,
+ 0x72115f4d, 0x60d7e40d, 0x74fea794, 0xd40c6f61, 0xbf8ff7e5, 0xe465e7b0,
+ 0x7a65b78f, 0x81b8fdbf, 0x19dfdb9f, 0xe913217f, 0x7e40f16a, 0xb116ff5f,
+ 0x6e95ed8e, 0x61d27fea, 0x3df2bf3e, 0x150bed12, 0xabef5cb5, 0x183d91a8,
+ 0xd37b9bb8, 0xb3371497, 0x37a249a4, 0x552c0bb1, 0x653de38f, 0x0989bcf6,
+ 0x518ccc3b, 0x98583a1a, 0x91f64a5d, 0x45664685, 0x366975ff, 0x8a9773f7,
+ 0x51ef133c, 0x589a0b15, 0x91ff7f54, 0x8e3bd604, 0x3fb8a67a, 0xc959f33f,
+ 0x7b8af783, 0x73f351c7, 0xa77eb5c9, 0x9c81dee1, 0x16e40acf, 0xb77b0fc2,
+ 0x6a10fbef, 0x1cbc6ebd, 0x91a97815, 0x48f178f5, 0x8d45e27d, 0xb0f15757,
+ 0x7596ede4, 0xf25d6e78, 0xbb7a44a4, 0x3c55bcff, 0xbfe46e2d, 0xfdfbd13f,
+ 0x97d9072d, 0xff9a73d5, 0x5ebc55fc, 0x07f3fe6b, 0x14687d0a, 0x73ef831b,
+ 0xfc905d01, 0xdfc5bf70, 0x389fc83b, 0x872b4624, 0x18fa0a17, 0x12713553,
+ 0xc40b809a, 0xd6d17b39, 0xc1c48ffb, 0x294eb3fc, 0xe6e74f74, 0x1ef42c9b,
+ 0x4e80eec0, 0x9d2a6f92, 0xdb3a09d5, 0x1fd9fa22, 0xee872cbf, 0x364bd601,
+ 0xbe5c2bd4, 0x102f7e00, 0xaa002de8, 0x4af27a1c, 0x8da3c0ae, 0x17ad73de,
+ 0x1de00dfb, 0xd57309e3, 0x8ef007fd, 0x91a633fc, 0x176b83af, 0xc64c875f,
+ 0x5b1503ed, 0xe60fbb25, 0xbf7f5153, 0xcaa3e719, 0xd60bf85d, 0x3e868bae,
+ 0xa4fa5a8d, 0x57becd42, 0x5a67ca2a, 0x73c03eaa, 0xf7a04ce2, 0xf076441d,
+ 0xfd1d669f, 0xfedbedd7, 0xa0ad488e, 0xc788bdbb, 0x2757c460, 0xb07c9fd7,
+ 0x94f4842f, 0x1d6e8cbb, 0x753d271e, 0x9357d395, 0xa31da0a4, 0xfc354f1b,
+ 0x152cb87d, 0x88af484f, 0x3205c6f7, 0x7e0117e6, 0x37e67fc9, 0x6ac7f45f,
+ 0xd34978f9, 0x76ffde59, 0x98facec9, 0x6fc78ab7, 0x76ddb74b, 0xdfa4ebc1,
+ 0x7dfa3f3a, 0x18f3a027, 0x4ddd7ffa, 0xc6c7bde2, 0xf01f9d30, 0x0f5c8183,
+ 0x74001dd8, 0x37fbf68e, 0x7fbc764d, 0x6fefcfe7, 0xbd44fa08, 0xf3f8d15f,
+ 0xd004e286, 0xcacbbbbf, 0x0c70abce, 0x56a57ae6, 0x600deede, 0xfb327351,
+ 0xd17dffef, 0x8dfa7f7f, 0xe3811f9a, 0x87ac5ca1, 0x7af634f1, 0x9eaf797f,
+ 0xaf35afcf, 0xbe5e8273, 0x71d4bceb, 0xbe5c6dbe, 0xfb73358b, 0xa3887e2c,
+ 0x13dbfc38, 0xe8a97cf0, 0x7d400f7f, 0xa17fed47, 0xa2138fff, 0xc59feffa,
+ 0x42ce28da, 0x71ab7ff5, 0x1ee2f905, 0xc27914db, 0xbf1f709f, 0x82f7e0ec,
+ 0xfdec0d32, 0xe43fb809, 0xfc3e2898, 0xd91331f2, 0xe64f2e6f, 0xf9dc69ef,
+ 0x5f7a21f6, 0x8a144efe, 0xb33bff80, 0x1d273a24, 0xa3c7aec7, 0x7f256d1e,
+ 0x0c6fe037, 0xd5477fda, 0x78c24d54, 0x3cbbd1ea, 0x4fb5306b, 0x077c8cea,
+ 0xbf226dd7, 0x88ecda0f, 0xe8fb8498, 0x28d88f8a, 0x7ec227b4, 0x1f47ed4f,
+ 0xef585165, 0x1d144726, 0x7ed7c63f, 0xc0367271, 0x6c98fe31, 0xc15ea057,
+ 0xf460e0a1, 0x3cc4de27, 0x2e3e306b, 0x39819b63, 0xdf1b7835, 0x708d98ea,
+ 0x82fe8097, 0xc692c6f6, 0xbe306b1d, 0x449b64bf, 0x676e5ded, 0x67cc286e,
+ 0x73cfd6ef, 0x803ca187, 0xb5dcd87a, 0xd573d78d, 0xa9747648, 0x62dc6a2d,
+ 0xc3517926, 0xf5ed45ef, 0xfbcacc48, 0xdfa158f5, 0x7da0dbbd, 0x6ce3d926,
+ 0x6ab907a8, 0x1c38a73e, 0xed49c017, 0xb2b8f0f7, 0x414ed045, 0x9fb9a97e,
+ 0x4db25bfa, 0x599a1862, 0x43ef87b2, 0x764cc725, 0xf03daf2c, 0x33a7ed24,
+ 0x64b8bc60, 0x937c77dc, 0x4635cec9, 0x6d79efe2, 0xbb9d31fd, 0x6c7b1de8,
+ 0x9700f250, 0x8bc8925f, 0xc7aa8b73, 0x9838933d, 0x7d9178e8, 0xfa023995,
+ 0x0a3b2779, 0xae8077c3, 0x357ba73e, 0x25dc45c7, 0x013859c6, 0xcfb287ef,
+ 0xf2dcf19b, 0x9f1e4487, 0x227eb0be, 0xb31621c5, 0x9c438a7c, 0x8deb9e39,
+ 0xe012deef, 0xbbf1bf41, 0xf881cea6, 0xfc2dd0fd, 0xbdf6ec7d, 0x27b6ee5c,
+ 0x053bd0b6, 0x6341f017, 0x36cd6d80, 0x85c4e499, 0x2cdedc3d, 0x9c91376f,
+ 0xeb97bc5e, 0xf1b68715, 0xe2ec2f7e, 0xeda4d7fa, 0x3ee2e577, 0x1aa778bb,
+ 0xb2e5c79f, 0x645c6e7a, 0x5596f113, 0x3efccc3b, 0xb7f2df78, 0x5fc1e05c,
+ 0x1f6de2be, 0xf1728fe4, 0xbcbfb96e, 0xc7faf72d, 0x9cf7073b, 0x7ddd703f,
+ 0x571d125f, 0x3c31331c, 0xdbe7487f, 0x29fb9ec8, 0x3e50dfee, 0x847251be,
+ 0x94e4be40, 0xb3fa43c5, 0xff7dc167, 0x69c8fb89, 0x8c14930b, 0xa37c0167,
+ 0xf9d2da2f, 0xf7c15f97, 0x315b8f4f, 0x64e80832, 0x317be101, 0xcef8465b,
+ 0x50e3c9dc, 0x47578f33, 0x7c7dc22f, 0x5ab38f32, 0x4e6655bc, 0x54f85c8d,
+ 0x21fecc72, 0x9de80fdf, 0x65de552c, 0xe116ab9a, 0xc891da3e, 0xd3b2a1e5,
+ 0xb637f744, 0xf7e83c8a, 0x496aaf74, 0xb36896c3, 0xd259ff46, 0x9f1a25b4,
+ 0xe2275d5a, 0x7b88d738, 0x7ccc4b1f, 0x49af259c, 0x719a1db6, 0x7ed47ed4,
+ 0x5dbc0dcd, 0xfb4f134a, 0xc2097feb, 0x9bfcf347, 0x7f83e519, 0xefc6bd3f,
+ 0xf7ec9fa7, 0xbfa356ae, 0x995dfb23, 0x9f65b92e, 0x57d2919f, 0x93d8e33c,
+ 0xe0d0e606, 0x812ffb2d, 0xdd87d1cc, 0xf80b36be, 0x8eefd61c, 0xd59fae7a,
+ 0x97359d66, 0x86de5267, 0xec215d7c, 0x439315c2, 0x1f2c563c, 0xf22d7c75,
+ 0x894c8cf9, 0x9db981e8, 0x1e1f7c66, 0xed0531f4, 0x79338bea, 0x1ed0c5fb,
+ 0x49f6aff9, 0x17208fce, 0x151b9414, 0x52e4b6db, 0xc1491afd, 0x2c776bfe,
+ 0x24a3bd20, 0x5e54665b, 0xa0f49673, 0x91b3fa92, 0xa7c0b7c8, 0x57ffb8d5,
+ 0x50d8b04c, 0xa87cab6e, 0x6abbf1f2, 0x36d58d7c, 0x9c5fdf02, 0xc9f4a892,
+ 0x2631f2cf, 0x3bf150f4, 0x4f9cd902, 0xc26bdddf, 0x5f0f5e19, 0x7cab1f13,
+ 0x66df232b, 0xa1edf0f6, 0xc8cc936d, 0xfc3c17c7, 0xe424ea1e, 0xddebe47b,
+ 0x71bfb092, 0xaf9fd4bd, 0x5796f1cb, 0x23d7b7ca, 0xe7f67e55, 0xcb6366df,
+ 0xc5771c1c, 0xf704012d, 0x3e1b5ba4, 0x11e5c158, 0xe93353bd, 0x0e2887d6,
+ 0xc791917b, 0xc478ab1b, 0x478c4cf8, 0xcabd525f, 0xb7de5b8c, 0x8e0fc786,
+ 0xbb7a8945, 0xfe44d6ec, 0x1aee453b, 0xb5f9d113, 0x5f17b1f8, 0x5e3f275d,
+ 0x8b5d1f2f, 0xe5f1d51f, 0x5b3f7d26, 0xf7f97d05, 0xd7bc4537, 0xdb98a2bc,
+ 0x9c485625, 0x339456de, 0xefa8d3f2, 0xf7c40f4e, 0x90f635a6, 0x56813a5b,
+ 0xdb7a7c35, 0xa85b2b55, 0x1644e3c1, 0xb24fcba6, 0x4feae9c6, 0xcaeb25b1,
+ 0xd50ec6a7, 0x46534f95, 0x67b7f2e9, 0xbfd5d78c, 0x97513ec3, 0x9a7b33bf,
+ 0xa3817eae, 0xe0779740, 0xbd01910f, 0xe9df8a36, 0x0efc4d7b, 0x99fcbf82,
+ 0xdf883160, 0x27741b75, 0x042753fa, 0xe64b3c89, 0xf10601f9, 0x77a96f3b,
+ 0x426a7da2, 0x21b3c88c, 0x96a09f3c, 0x07f5e10f, 0x78d3eda9, 0x3cb530f9,
+ 0xa8df978d, 0xfcf3a796, 0xf3ca8ccd, 0x13bf4e9f, 0x6d6adf7f, 0x0920b3ac,
+ 0xabeeefe8, 0x9fc75ecb, 0xd57f786b, 0x5464e2ac, 0x210d96b8, 0x2fbd433d,
+ 0x73ac40f5, 0x4f56526a, 0x597f5ab9, 0x7e017e52, 0xc79cf8ef, 0x0471a977,
+ 0xdf5535df, 0xa8e1cf8d, 0xbef83965, 0x58f1c621, 0x7cdd6d4d, 0xe4bdfb04,
+ 0x379d6fe0, 0x1619d256, 0xd4a56df0, 0xf4a36957, 0xa52c6560, 0xb6152b87,
+ 0x23b19530, 0x1e941995, 0xf7d3b4ad, 0x29b32ab7, 0xa0e9563d, 0x3cca9df4,
+ 0xf32b9b4a, 0x46ac6529, 0x6c477bf7, 0x0c5df8ae, 0x8bdd9225, 0xf1b707e7,
+ 0xc32efd3b, 0x45470643, 0xff53cd12, 0xd4877dde, 0x57bc50ac, 0x0fe38f16,
+ 0x651ded59, 0xa9093e03, 0x3c63b608, 0x2f8e486f, 0x0a19df0e, 0xf8a66e59,
+ 0xfc4427d0, 0xff084d59, 0x59d489dd, 0xe628f7e2, 0xe1887cf3, 0xfbbd3278,
+ 0x278f20fb, 0x4778b18d, 0x718edca1, 0x9af0fef1, 0xb6dfb627, 0xa05159aa,
+ 0xab2cb6de, 0xf9c52fda, 0x7fca3cd5, 0x84f522d7, 0x338bbdf8, 0x4f13df3c,
+ 0x3229d3ca, 0x9fa1dbf7, 0x1dabfd0e, 0xebdd0052, 0xbfd008e9, 0x15be9163,
+ 0x97e1a130, 0xd32b1ea1, 0xb0d7fefe, 0x7e5d365d, 0x57563784, 0x457ac6ff,
+ 0x97ca3e57, 0x731f2ba1, 0x67cbaed4, 0xeaeb6735, 0xd0e53b8f, 0xe4b7c7e5,
+ 0xfcdfeae9, 0xdf2ebe49, 0xf3e61c35, 0x5334710d, 0xfd5d2563, 0x6b6bb069,
+ 0x233dbffb, 0x0aef974c, 0xe351f8e6, 0xbbfbfc10, 0xefefaec3, 0x7f7d6cce,
+ 0x7f7d0e05, 0xcfff16df, 0x53189f01, 0xac0877f1, 0xf816fe94, 0x61177f04,
+ 0xe609f00f, 0xc13e045f, 0x827c0bd4, 0x3e025fdf, 0xf02d7cc1, 0x80ebe609,
+ 0x0f5f304f, 0xefe9827c, 0xfbf04f81, 0x4474f0b5, 0x8c547b8c, 0xf71896fb,
+ 0x2638f85a, 0xda23bdda, 0xd4bb6335, 0x0c4f799e, 0xf68cd4ff, 0x21bcf2e3,
+ 0xe507bc06, 0xf742de58, 0xe4df3a79, 0xf4e64ae7, 0x7d44ad1c, 0xe28221aa,
+ 0xcbd436fa, 0x5ed36f14, 0x2a77a26f, 0xfe5fd60f, 0x7b5bf223, 0x53fa4cad,
+ 0xef7bc345, 0x82bcf254, 0xd5db63fa, 0xb187ba40, 0xdd3cfeb1, 0x92fb2e53,
+ 0x4c65eee9, 0x1f3327db, 0x52f46fc2, 0xaa5b483c, 0xb9d0f79a, 0x3ecf7f2a,
+ 0xee95473a, 0x6fe547da, 0xf2fa4d7a, 0xe5743b5d, 0x8c1fac36, 0xdd0f36f6,
+ 0x5eacfdeb, 0xf547cfed, 0x3ef952cb, 0x43aed9fc, 0xbb5e30eb, 0x0882df7c,
+ 0xee972f3c, 0xf45d1e39, 0x54bff80d, 0xb470c2f7, 0xa8379603, 0xfef35eef,
+ 0xf7d41bca, 0x65fc380f, 0xf172fba9, 0xb03e017e, 0xa5bff18b, 0x70cb3bf5,
+ 0xb8cd2edf, 0x81fe84c7, 0xf7455636, 0xfcbc3adc, 0xf1133b9e, 0x8ec265e4,
+ 0x1cbde6d0, 0xfcbcef8a, 0x4cfafbc1, 0xc6d89dfa, 0x6e38a143, 0x7efead47,
+ 0xae20e472, 0xe20e4447, 0x6adbccf7, 0xd1bdd10f, 0xe443de0d, 0xfa33680f,
+ 0x4507fe68, 0xc45203be, 0x997ab4ff, 0x8f7845eb, 0x830eb347, 0xc177f106,
+ 0x090fd5a7, 0xf09d79c1, 0x0e86f1f2, 0x183f5452, 0x6e3a2fd9, 0xc6277db8,
+ 0x5d4b4cd9, 0x6ff310b0, 0x42cbcec5, 0xe5c600bb, 0xfa7f75f5, 0x11efd166,
+ 0x99bf47a1, 0x8c11f2fa, 0x2f2b7eab, 0x9df69462, 0x7883319b, 0xd9ae40fc,
+ 0xbef18a99, 0x8a158227, 0x979d5933, 0x7beb8212, 0x9efc5310, 0xffc52cf7,
+ 0xe3e5ad2f, 0x8735b09d, 0xa89e7d22, 0x1ea3231d, 0x1b076dd4, 0x6be4eb24,
+ 0x69b9bacf, 0x3b3c4a9d, 0x9e9fb182, 0x87dfe3f5, 0xfd51b20e, 0xefc73cb7,
+ 0x4f16f7c6, 0x71d90464, 0xf3888e5d, 0x7e1ee97d, 0x98d1395e, 0xdde703b0,
+ 0xc41b0f6d, 0x191d73ed, 0xe0575a06, 0x9eef510f, 0x8f574c9d, 0x56d1b7bf,
+ 0xe6c787a3, 0xe319bb39, 0xf3b6cac1, 0x4ccb1df7, 0xfe71a2cb, 0xc1d03e78,
+ 0x665cf02d, 0x6b4745f2, 0xa1acb5e8, 0x89826f9b, 0x3e541bce, 0xd53d6851,
+ 0xc1913c75, 0x622703ed, 0x650cfbf9, 0x5d1276fb, 0xd3350427, 0x1ff0973e,
+ 0x3602ff7c, 0xa67de374, 0xa9a7891a, 0x1a4fb106, 0x290cde78, 0xe3527fde,
+ 0x29794db7, 0x78c18659, 0xc51f6abf, 0x0bbfab6b, 0xbbd0fd05, 0x3926afb9,
+ 0xf1820e16, 0xcfe525d7, 0xee41e34d, 0xf8376421, 0xe31bb05b, 0x7fc8a79b,
+ 0xefc71c79, 0xe8efe5aa, 0xa1b88b94, 0x77a33b2e, 0x99b6bb68, 0x077dfc3c,
+ 0x51746f7e, 0x0b97e736, 0xfe2c738a, 0x2af95e1e, 0x83cb8f03, 0x324057f3,
+ 0x72894fbf, 0xe4bed2ee, 0xcb4e913b, 0x3c36ca8e, 0x26f24e5f, 0x72ed02ff,
+ 0x527ec265, 0x18ec95e1, 0x1b5159f7, 0x8facf642, 0xe3062a03, 0x55e3e9b9,
+ 0xfa3f649d, 0x5ff3f418, 0x1db971f1, 0x959fc444, 0x3f216fd4, 0x5f3c52d3,
+ 0x3cfedfc9, 0xf1e6b643, 0x1b35cfbd, 0xcd738907, 0xf5143650, 0x04f22999,
+ 0x1bfcefba, 0x77d43f5c, 0x6ec9c3aa, 0x3d8462b1, 0x837bf906, 0xef4e9951,
+ 0x6c9a3598, 0xd3571f88, 0x6e104bcb, 0x9da0594f, 0x7f2b25ec, 0xf8ec784f,
+ 0x7e8cf002, 0x075b7a6f, 0x9f1c5eed, 0xaec2f51d, 0x3876e26f, 0x0ec59df5,
+ 0xc9fe44ab, 0xbd17770e, 0x7e21d093, 0xbcf961e7, 0x17d40621, 0xc6f8781d,
+ 0x0e42c5fb, 0xe297ef75, 0x8d5b9ddd, 0xf7c6322d, 0xe9f1161e, 0x4c1a0c2f,
+ 0xf78b26f5, 0xd8845708, 0xe816fb75, 0x2577a449, 0x7e897844, 0x7d231f40,
+ 0x755fe549, 0xda302e1f, 0xd57eda4c, 0xf97e1df6, 0x1eefddc9, 0x35627bf2,
+ 0xd73eb85b, 0x5e987fdd, 0x0f3c030f, 0xa66a3f20, 0xa4e1f69d, 0x8fbdf502,
+ 0x2a77c465, 0x5d01b59f, 0xd10fefe1, 0xfac35e6f, 0x403b6d95, 0xd6728076,
+ 0xdc80764c, 0xae6e3e50, 0x1b9387b8, 0x8437d3c8, 0x8bd7a07c, 0x456c9e00,
+ 0xfba7c9d2, 0x41d1c715, 0x8a47fdf0, 0xae20d8f3, 0x07b8888f, 0x215e676e,
+ 0xdbf96468, 0x19704edc, 0xcae51ce8, 0x4a49968f, 0x29df46aa, 0xee59fb7d,
+ 0x9a3b774f, 0x7bc5a233, 0xfd0f4a92, 0xfb99feaa, 0xa9280656, 0x1f283d5a,
+ 0xf3db1bfe, 0xda09554e, 0xb89ef00f, 0x44fe46dc, 0x2568cae7, 0x3fb7cc75,
+ 0x0e7ba3a7, 0x2217c9e9, 0xff3a7dd1, 0x0c9fc4fb, 0x8208f112, 0xfd0493de,
+ 0x744a70ed, 0x0ff1ddae, 0xee19fbfe, 0x3dfa257b, 0x23e0bb8d, 0x131336fd,
+ 0x52264af5, 0x5fde34dc, 0x7544f3a0, 0xebc7f124, 0xea326f26, 0x5b97affd,
+ 0x54496eed, 0x11cdf986, 0x7e2798f8, 0xfdfd5e87, 0x2a820ff9, 0xa751f15e,
+ 0xefd444ee, 0xd0b4e4ff, 0xf0bba0bd, 0x0f01ab77, 0x433ed63b, 0xd92372f1,
+ 0x439e1b5a, 0xbebb2500, 0xcef7e3ee, 0xcda51ffe, 0x8000fdec, 0x0000
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2[] = {
+ 0x00088b1f, 0x00000000, 0x7ded0300, 0x45547c79, 0x5e9d6fbe, 0x0b3b59d3,
+ 0x93c40859, 0x3624813d, 0x34e8a8ab, 0x3501104b, 0x113e0280, 0xc3d9ac3a,
+ 0xce2f3332, 0x6469b9f8, 0x8c2e7077, 0xede88db8, 0xb41209b0, 0x83410081,
+ 0xee22c8d3, 0x33bd1511, 0xc2e0370e, 0x50624c12, 0xc661be1f, 0xd55fdf57,
+ 0x1269f749, 0xff3379d1, 0x2b19f3d9, 0x9d554e75, 0xfbfedfaa, 0xef8aafd5,
+ 0x5fbfe7bf, 0xb133fe30, 0xfd18722f, 0x563237be, 0x684bcc68, 0xcdcd43c9,
+ 0xeec62f58, 0xeaac8b57, 0xc5cec610, 0x90389633, 0xf70ff2b1, 0xc634b246,
+ 0x67b97f5a, 0xaade54ca, 0x1858758c, 0x60b657ef, 0xa8199989, 0x50ce735b,
+ 0x84304ac6, 0xe97b4bca, 0x7f491604, 0x2f3f8cab, 0xbc67f265, 0x31c59138,
+ 0x465ffd56, 0xede54c66, 0x627ddff8, 0xf98f7bf8, 0x9c884b4c, 0x2fffff0f,
+ 0xfc3ffccc, 0x8a03fcdd, 0xd8c28967, 0xd5856e3d, 0xdbe576f0, 0x32a6edf4,
+ 0x33a5998f, 0x79837676, 0x31d7da03, 0xf680c3ab, 0xde74ddfc, 0x6fabd2be,
+ 0x46f3d6cf, 0x68a3f849, 0x8a8fda3a, 0x7987b2b3, 0xe27464fb, 0x8a79e4f5,
+ 0x132a6967, 0xbef3e71f, 0x3ee7ae5b, 0xc2d83ae6, 0xfb094f9f, 0xf0380cc4,
+ 0x7855f705, 0xab2ee993, 0xfcfe61e3, 0x23b9e623, 0x98f79787, 0xbe14877c,
+ 0xfd46eaee, 0x32d80b77, 0x41cde03b, 0x41fbedb5, 0x43c499fc, 0xbc2d7970,
+ 0xc35d542c, 0x73ff1781, 0x471c633b, 0x16b7e58b, 0x0d3bcdbd, 0xbd52ec66,
+ 0x7cf8c3d1, 0xbbc7542a, 0xa2bd79c3, 0xf0f0ecde, 0x146b33f7, 0x3fc72335,
+ 0x3676e62f, 0xf1fbc4e7, 0xc69398c6, 0xe5f0d6ab, 0xc00bffe0, 0x5226ab9f,
+ 0xc7e418cd, 0xdeb1b56f, 0xe3047802, 0xf07f12af, 0x2a3656ef, 0xd5ea5f1e,
+ 0x8bc60b78, 0x8e1fe14f, 0xd36e1ab9, 0x2fb888d4, 0x723ff3fa, 0xa1e02e59,
+ 0xff5b4fe1, 0x7013f0d5, 0x1031693a, 0x36bfdd0a, 0xeff0b67a, 0x1df155ff,
+ 0xfef2f3b5, 0x409913dc, 0xaffed682, 0x2efb9a4b, 0x75fce3e4, 0x5a4f2884,
+ 0xa0378958, 0x33650cee, 0xb24f508b, 0xbfdeb1ba, 0x3923b92a, 0xbff97932,
+ 0x04f514ef, 0xbdfa8a8b, 0xbced2309, 0xda2cd27e, 0x6310f633, 0x86fcf043,
+ 0x615ef4d1, 0x6d3eb047, 0x825c7c7e, 0x8a03c74f, 0xbd272367, 0xc18d8c99,
+ 0x3e4752fc, 0x3f8d3631, 0xf49bf53f, 0x7387c001, 0x5bbc7e91, 0x8b98772f,
+ 0xb15dbd79, 0xc7af5299, 0xbcf425f3, 0x61a6c6dd, 0x7f4713de, 0xefb5ef45,
+ 0xe78b311c, 0x1699159d, 0x939b0ff0, 0x4b7e0069, 0x319d8c24, 0xc26751b9,
+ 0x7a4f7bf9, 0xcbb78194, 0x376173e4, 0x3df1faf2, 0xf800aee1, 0xcfe5af9e,
+ 0xdcf5012d, 0xb8585247, 0xeb687ebf, 0x8f80b2ef, 0xc0bb8b12, 0xab9f9fc1,
+ 0x89c53a7b, 0x5995d6fa, 0x75b25768, 0x728a9675, 0x9cb2efe3, 0x79730f54,
+ 0x09dc89c2, 0x6f3bad0e, 0xd23e04dc, 0x6e9a3bc6, 0x0f4ff9a4, 0xf8c85439,
+ 0x7ffae338, 0xdbcedcb9, 0xb146fe65, 0x67ee0c83, 0xbcedcbcd, 0x411c8cff,
+ 0x887d6cef, 0xe26ee687, 0xbef1c474, 0xcd8ef725, 0x7237ebe0, 0xe1cf353e,
+ 0x26a8f6ed, 0xf3066f1a, 0xefe049ac, 0xbec52ad9, 0xefb60585, 0xc5f6875b,
+ 0x224b14cb, 0x20bfdfaf, 0x4551807a, 0xef8268bf, 0x8e0355ac, 0x078cf9e1,
+ 0x5671f3c5, 0x8c09c34f, 0xb1c584f3, 0x28a6f885, 0x3fdf28ad, 0x85aa3dff,
+ 0xa35ccdfa, 0xfe793d38, 0x1e3e64ef, 0xceb8175f, 0xf342aa3d, 0x443d9f62,
+ 0x892ee6f2, 0xbe0f0997, 0x8f912477, 0xebb7a67b, 0xbfdfca80, 0x1917d8f3,
+ 0x747cfe3e, 0x173cf9cc, 0xc5a64f5f, 0xac52c7f5, 0x81d5a37b, 0x482e0c75,
+ 0xf6f02636, 0xe2397f03, 0x1f339451, 0x2963fe2c, 0x2193e7e4, 0x3fcc8c03,
+ 0x6a8a45bf, 0xfcf2e1a8, 0x59d4dd70, 0xc7b9db80, 0xcf959842, 0x765d5167,
+ 0x9f86eb02, 0x8e39f2b4, 0xb18b357f, 0x5421b5ed, 0x33b5a8ee, 0x6d67712c,
+ 0xac5fd522, 0xd364a955, 0xb22d7d04, 0xd3d2790b, 0xe3eb7f78, 0x1aeb00fa,
+ 0xa9943974, 0x5e0c9e5c, 0xe58dc7c5, 0xb957eaeb, 0x575cb571, 0xc03fef26,
+ 0x700a3a9d, 0xe17abc18, 0x09c844b1, 0x7af04cd5, 0x14aac4f3, 0x07fcf1f0,
+ 0xca5b3f4f, 0x16a447df, 0x317215fd, 0x1657c364, 0x03e1e1d0, 0xde00672b,
+ 0x62ad1b25, 0xe7dd727d, 0xf84acb1e, 0xfddf1f23, 0xf26599ba, 0x9c37aaf1,
+ 0x2f35767e, 0x6859af67, 0x9ef7a409, 0x3517fbd6, 0xbc1af093, 0x67ca9fee,
+ 0xa7e5c13d, 0x52efd9f3, 0x72369f88, 0xe7fbcb3e, 0xc1faacf9, 0x41cf0425,
+ 0x549645a9, 0x3bb37de8, 0x2e75fc05, 0x7ba216f7, 0xf08541f7, 0xad5fc9a1,
+ 0xe05529bf, 0x5de0dca3, 0x2fd53c33, 0x1961be77, 0x0743ef04, 0xf0b566ce,
+ 0xbc69be71, 0x1d702a37, 0xbe3ee5c1, 0x775f1f6e, 0xcfb78723, 0xa1fbf572,
+ 0x83ba5716, 0x81a86faf, 0x8cddbcb9, 0x106a9053, 0x0a7fc47c, 0xa6857b87,
+ 0xa5b358bf, 0x9bd78228, 0x01685f14, 0xe76dd1f4, 0x3fd0914d, 0x68133b0a,
+ 0x99dff017, 0xd3dbbd00, 0x5655af3c, 0xbf931c61, 0x06c7c37e, 0xb7d00be6,
+ 0x3284b637, 0x7abbee9f, 0x85180d39, 0x1db53c70, 0x89c9d248, 0xa215525b,
+ 0xbe16d1bb, 0x63e3b47e, 0x01da0258, 0xd438a6bf, 0x7ea23773, 0xddf022de,
+ 0x4fdb8fb6, 0xc67be2a9, 0x9cb87ea1, 0x005ad03f, 0xa5c1acf9, 0xa256a5ea,
+ 0x95c68a9f, 0xa704295f, 0x0a9bcfdb, 0x43a70dae, 0x800b5b5b, 0x96e6f3df,
+ 0xbfde76a1, 0x0052d2cd, 0x2cbd553c, 0x854fffe4, 0x3e2ae957, 0xb87e41f1,
+ 0x03762954, 0x78d0a9f8, 0xeb0571f1, 0x7e266e39, 0x89b03aae, 0x53676fe4,
+ 0xa6720398, 0x263cd0da, 0x62a88381, 0x9063e9c1, 0x8e899d7f, 0x1f2fd028,
+ 0x0d7809df, 0xd47a974f, 0x113291d4, 0x5e8bb072, 0x073cfe84, 0x1c60b77e,
+ 0x06e4056f, 0x5b63082b, 0xc01778f8, 0x8cf9fcff, 0xe015d49a, 0x5e9e7383,
+ 0xdf4f2103, 0x155bf82c, 0xa7fe5be0, 0xd8ec3b30, 0x1a7f2f4a, 0xf5aee780,
+ 0x19cc8c78, 0x6df2bf00, 0xd019cc61, 0xdea2daae, 0x1bf0f645, 0x5c4dc646,
+ 0xf04fdd56, 0xf0497b1b, 0x43b2e55b, 0xf180c496, 0x1b7e4866, 0x11bfa7f7,
+ 0x9a706abf, 0x41b99fd4, 0x8dbf6c37, 0x87d61dec, 0x671f01f3, 0x0f04fed2,
+ 0x63cda1e8, 0x78a39b70, 0x87ae7afd, 0x558f6ed0, 0x87544bb4, 0x8c6d1e00,
+ 0x2a9c058d, 0x62b39a63, 0x1fefb978, 0x1c4599c6, 0x7903957e, 0x2b2f979d,
+ 0x272b3e82, 0xf3456735, 0x33629b7a, 0xe55e3e30, 0x84fef146, 0x954dd841,
+ 0x1b7fa269, 0x277219e8, 0x91329bc4, 0xc1fb5ff3, 0x78b329fd, 0xdf70e1fd,
+ 0x5f07813c, 0xae739e16, 0xbfc49acf, 0xdddd0adf, 0x3519cb1b, 0x35ab7211,
+ 0x9e8fab42, 0x856a3a08, 0xea13703f, 0x4dbde285, 0x75118fab, 0xad759145,
+ 0xfd9756bf, 0x178d057b, 0x07de82cd, 0xaa0a4fb5, 0xbfb20d9b, 0xd15f7efc,
+ 0xdbc6dd7f, 0x7d79ba26, 0xbc73d5bc, 0xd17d7016, 0xdb5700cc, 0x005fbdce,
+ 0x8407e5fe, 0x73b919fe, 0xa0ddc5ef, 0x0e11bd97, 0x9a9d562b, 0xf4b7744a,
+ 0x066b73c0, 0x9977ae82, 0xef8e561d, 0x7c3feb87, 0xced4b7f6, 0xf19200ca,
+ 0xd66f3956, 0x8eef8452, 0xb379ca37, 0xe35e69db, 0x45f7b4c3, 0x51f1af34,
+ 0x8a26bada, 0xbf78ac7a, 0x44f26d2d, 0x77b2f037, 0x3741afe7, 0xe89b9dbc,
+ 0x17a70760, 0x88b6a1fe, 0x6ef819e6, 0x8756f3d5, 0x6ca3cf9b, 0xd868ee4f,
+ 0xd6fda5b9, 0x7abfc0a6, 0xe88d353b, 0xf6d2f0cc, 0x438dbfad, 0xd4c31b3b,
+ 0x8c24f6ca, 0x46203f24, 0x6332a5c8, 0x4485d0dd, 0x3eb69b3f, 0xb76d758d,
+ 0xbc7c8db1, 0x8f2148d2, 0x7a66b74a, 0x2fe97cdc, 0x19d3fdff, 0xe34283a0,
+ 0xfe78ad86, 0x019b66f5, 0x71613a70, 0x7d02dd46, 0x764cc273, 0x97aca955,
+ 0xf3158c9e, 0x43196b0a, 0x36b713f4, 0x91a71265, 0xee07d8b2, 0x1bc73cc4,
+ 0xbd0b3ed7, 0x32b39ece, 0xb7e743d8, 0x7ef2b873, 0x0798b7e7, 0xdb6d3a02,
+ 0xd7a04c23, 0x8ced6556, 0x2dfc623f, 0x6dab5da2, 0xbddbc12d, 0x7be19b25,
+ 0xd7631dbc, 0xdd3adda3, 0x9e5bf3f3, 0x75dd802b, 0x64f1f9e1, 0xa4fc697f,
+ 0x66d965f1, 0xf1ff8eab, 0x27e1e353, 0xcddd9fcb, 0xa8fc03c2, 0x6a9efb0b,
+ 0x5f0063fb, 0xfb37a85f, 0xa5461c2c, 0x242cb656, 0x658fcfc6, 0xc58db7c9,
+ 0x750ccafa, 0xbd788b59, 0x0ccb5074, 0x1b79e5f0, 0xede4490b, 0xf1df04de,
+ 0x92c3597a, 0x3ddb9089, 0x4d3e27cd, 0x126f8fe8, 0xd37fff05, 0xde40f368,
+ 0x3f9724f4, 0x5bea65a9, 0xfef97201, 0x39d25605, 0x5a6f78da, 0x3fb015bc,
+ 0x3e8462aa, 0xd7dbc53e, 0xa4b47067, 0x66767b09, 0x2dbdbe8d, 0x5fbe862d,
+ 0x82c96965, 0xa9a4b65c, 0x0efb4ed4, 0x4164b533, 0x23f7074f, 0xdc3c877a,
+ 0x2abc90a1, 0x1b4e506b, 0xe3482523, 0x0b2cf0fd, 0x058c7b71, 0x7121e3dd,
+ 0x1f03c4a8, 0xe09a7b6b, 0x96d0f2bb, 0xb2a9e848, 0xc6d39b7a, 0x6888abc7,
+ 0xfa0fbc89, 0xdb2325f3, 0xa717d128, 0xffe69f8d, 0x9727e69e, 0x5b4ecd7a,
+ 0x1bf72301, 0x3c7cde76, 0x5bdac307, 0x4b2e8286, 0xdc68c31a, 0x92bcf9e0,
+ 0xc94ef426, 0xac73fd06, 0x8fc81ed3, 0x03e29b8d, 0x319bd1ed, 0xfbf05eef,
+ 0xb4df134e, 0x0a4cfdff, 0xc0cca0e8, 0xb41c2996, 0x5b1f7817, 0x8859d50c,
+ 0x9c6dbba8, 0x0dbecbf2, 0x5cfd050f, 0xf882a6f8, 0xce4badb4, 0x687c9316,
+ 0xab2ce4d3, 0xce4d7511, 0x5f24f9b2, 0xece4bada, 0xe4d75122, 0x57bed6a6,
+ 0xe0a4ff50, 0xd4dca4f1, 0xf37293c6, 0x43ff1b1f, 0xc7634dc8, 0x77e0069b,
+ 0xfc2ed993, 0xf9af8128, 0x51dcce12, 0x7a4b593b, 0x3d92acd7, 0x8c8be924,
+ 0x443b00e4, 0xa636c7e3, 0x7f006cee, 0x5f938497, 0x7ea798c4, 0xdfb7af37,
+ 0x5878ef1b, 0xd4ee1abd, 0x71bbfb86, 0x03cddf31, 0x5d9bcf9e, 0x3e9c6925,
+ 0x845af32a, 0xbf0a757e, 0x2b15eaad, 0xe6ed55d9, 0x8790ad8e, 0x8aaecc87,
+ 0x0a8f3e34, 0xc18af34b, 0xcd174a7c, 0x4210c72d, 0x257a071a, 0xb5e82439,
+ 0x85936f2d, 0x431f59c6, 0x256ff376, 0xdc6e1dfd, 0x53e416f3, 0xc93a735b,
+ 0x7c95c67d, 0x114de81d, 0x8fcc1474, 0xc4fb731f, 0xbe7c97cd, 0xc848d1f1,
+ 0x9f8b8f9f, 0xb69ca0b3, 0xfb02cead, 0x64caf3ab, 0x2d6677b2, 0x35ffa20b,
+ 0xf1d07501, 0x183d7d7a, 0x9f57a01e, 0x04dc7f8e, 0x76a91def, 0x9b2337c1,
+ 0xaefeb0ab, 0x375e24fa, 0x0d5fd406, 0x67b507aa, 0xf82cde45, 0x7b603ba1,
+ 0x7d7d7e00, 0xdd4ec927, 0x0bd06669, 0xa4beb94b, 0x8f30defa, 0xb0c1c395,
+ 0x38c3eb93, 0x6fa10fa1, 0xc99b23ca, 0x6bdb6baf, 0x43fda3b5, 0xb4a6ce07,
+ 0x90b59d10, 0x607e52bf, 0x58ec3c7f, 0xe34aaa5f, 0x8f1bbd73, 0x0f7be5f7,
+ 0xd6b6c3c4, 0xbc18579e, 0xf7179859, 0x77200a0f, 0x4695e7b4, 0x5fe6165f,
+ 0xe01734ae, 0xa6f30fbd, 0x446ebcf6, 0x2a3ad19d, 0xd82f2114, 0x87e92301,
+ 0x24bd7c60, 0x2b972de5, 0x1f8bb005, 0xc9d8497a, 0xb9211c9a, 0x157bc7c2,
+ 0x1c84f3cf, 0x53f16bb1, 0xf214b5de, 0x36791ba3, 0x91c24d20, 0x66bf202d,
+ 0x10e8e41f, 0x571a7f7f, 0xbef461f8, 0x82d6e5ea, 0x93f43cb4, 0x1c8058ed,
+ 0x53900f4b, 0xf1cc8786, 0xcf653d7c, 0xaaa58e2a, 0x2fd02790, 0x8c97d3a5,
+ 0x9af70789, 0xff218e16, 0x0057b992, 0x0af3c1ce, 0x6949a3a6, 0x3265bf02,
+ 0x55b65aae, 0x982f55c4, 0xcb993c45, 0xd6e41f29, 0xc64bd1fc, 0xc6e6ef80,
+ 0xe3025a55, 0x7f1ad772, 0x7d7d7ade, 0x632582fe, 0xd597f760, 0xabd63bac,
+ 0xe3c1f69b, 0xc6eaba95, 0x3f57abc4, 0xa47bcff7, 0x3c2057b9, 0xa5de626c,
+ 0xe98c96d3, 0x43f3ebc5, 0x887859fe, 0x60385f75, 0x735f41f5, 0xf4fc52f8,
+ 0x740bcbd6, 0x8d6b87f1, 0x143cca57, 0xfe69ec2f, 0xe28565c1, 0x89ff093b,
+ 0x42dafe71, 0x26f9c67c, 0x49f77be0, 0x50693d7a, 0x25678ec8, 0x2fc1d7c5,
+ 0xebe2ae60, 0xb27acfa0, 0xec80b813, 0xf446186d, 0xc3e72546, 0xe06e8e19,
+ 0x22b7b5a1, 0xdf0430de, 0x7bdc7413, 0xbb53f97c, 0x2995fbf9, 0x5e74b8ce,
+ 0xe11cc30f, 0x7946250f, 0xb633d260, 0x5562e296, 0x6f0826d2, 0x3d54f412,
+ 0xabef48d6, 0x092c8d1b, 0x3c23127d, 0x635d7c99, 0xe8135ad9, 0x0ef31c7a,
+ 0xbb717f07, 0xf337f7e2, 0x64ffe3f7, 0xaf30f41c, 0xfc8c6cfa, 0xaea1319a,
+ 0x7c53d80c, 0xf42fd2bd, 0x10189e0e, 0x2e949bbf, 0xa370ccf4, 0x23bff242,
+ 0xb4e28c29, 0x9cab4fb7, 0xffa7481e, 0x5d7688ad, 0x1474f370, 0xebe35f90,
+ 0xdb840828, 0x2d853f94, 0xf32038a0, 0xf0129e0e, 0x16e9d99d, 0x5a697fea,
+ 0xaa4bc526, 0xc37709bf, 0x5e342cfe, 0xc3fe1c79, 0xdfdc83a2, 0xea7e3055,
+ 0xa3d80647, 0x7d844fdc, 0xd2fdcad0, 0x5df1f0d1, 0x3c84e9cc, 0x7e45efcc,
+ 0x854ef55e, 0x1fc76099, 0xe10c6eb0, 0x2dccaaed, 0x5673b0f1, 0x81687e37,
+ 0xfbdeadfe, 0xbf85459e, 0x2989f5c5, 0x0181a483, 0xf196adf0, 0xecc6caba,
+ 0x2ad7208f, 0x61a88b8f, 0x0b3de9a5, 0x52e226e4, 0xc3795ef8, 0x57a831ae,
+ 0x7dd11f30, 0xefdebd45, 0xa3544ced, 0xfdf8ddec, 0xfc85d3b3, 0x3fb7ead1,
+ 0x29fcfc29, 0x2bc0b646, 0xa5d922e4, 0x502627b7, 0x4fdfd61c, 0xd8d3a5d0,
+ 0xdb711cba, 0xa1c534f6, 0x43daa1f0, 0x2f60cbdd, 0x1c44b3b9, 0x1d95fdb7,
+ 0x5c51e783, 0x327833c4, 0x8cbb5f5f, 0x6abedfe3, 0x3018c99d, 0x8c9bdb9f,
+ 0x0f6d8f14, 0x08fb2565, 0xc03eaeef, 0xa294c9c7, 0x76bfa0b9, 0x373bc74b,
+ 0x4bb64ff3, 0x1d783abb, 0xf813af53, 0xe7da437e, 0x27c7bcda, 0x0c388b27,
+ 0x1d1d10f3, 0xd3b0fe93, 0xf40fdfc0, 0x74926ff7, 0x2c5feda5, 0xf6091c52,
+ 0x6d8b881f, 0xc39f70e5, 0xe38db4f1, 0xb5f3e51b, 0xdb873676, 0x89b5f5cb,
+ 0x56a17f54, 0x9b5bd2a5, 0xd777cf43, 0x50dea83a, 0xfbea8c3b, 0x6f549d6a,
+ 0xe54b1dac, 0xf445b54b, 0x954c0dfc, 0xd6d7baec, 0xd63b4ec1, 0xfa8a1765,
+ 0x7aa098c9, 0x93fb7d6f, 0xdebe8a31, 0x8ff6a15b, 0x1d6d7a6c, 0x2915ccfc,
+ 0x23529e9a, 0xf8b5efa0, 0xa3b189d6, 0x8f01d632, 0x1103f94d, 0x35766747,
+ 0x84f2fc0a, 0x5365cb84, 0x10e9e3d1, 0xa41d21e0, 0xe4c74797, 0x1e2e4146,
+ 0xf6993e3f, 0xace33aeb, 0x4dbf0fc4, 0xbb406d75, 0x9eef98ea, 0x63ba0bdd,
+ 0xe446ee82, 0x98365a0c, 0xb84463e3, 0xb5c7ed22, 0xfb6917d7, 0xa33f1c59,
+ 0x9b078a9a, 0x63b0bc84, 0x58d0a0bf, 0x2ee30731, 0x820db24a, 0x3affb9ff,
+ 0x571873d7, 0xde98ff83, 0xfdf033f3, 0x23f56663, 0xb7eea9d8, 0x38bf7f85,
+ 0xf3a3a1c2, 0x62375fdf, 0x9eddfa2f, 0xfe0cbe93, 0x87cce33c, 0xc2d38df8,
+ 0x4e1f41ea, 0x94b29843, 0xc26a99e4, 0xf5caf77a, 0xfec5548e, 0x9aa2cf80,
+ 0xbef8f862, 0xf07111d0, 0xbc498f73, 0x7f78971f, 0x2dfde243, 0xa72f21f0,
+ 0xffd4a965, 0x5e01c81d, 0x51efe66f, 0x7a2d494e, 0x3ac7e085, 0x76f70052,
+ 0xe071f709, 0x527f2133, 0xd7d9d700, 0x285abe09, 0xa87fcfe5, 0x09d34745,
+ 0x2b3ec25f, 0xaebf08b7, 0xba71c655, 0xf3f651f8, 0x85fa17f7, 0xd0b7efcb,
+ 0x81a316ff, 0x1d306be4, 0xdbd7287f, 0x2bf11f1c, 0xdb37f846, 0x1b24e761,
+ 0xbc81df3a, 0x508f8e49, 0x17f43297, 0x5470b1fa, 0xd0776898, 0x6d888766,
+ 0xc51df83f, 0x8797dbb9, 0x29fb134f, 0xbf892ce1, 0xbf98963f, 0xba4e3031,
+ 0x8bcc4338, 0xcbe211eb, 0x0ff31cea, 0x88bc91eb, 0x7e423d2e, 0xed185e66,
+ 0x5e35b523, 0xbda4bf22, 0x741d8869, 0x09ecd6da, 0xfea95e87, 0x8789fffb,
+ 0xfa6b68be, 0xf671123c, 0x23672bb6, 0x1babbfc1, 0x7d848d3f, 0x7a636af7,
+ 0xcd13ca04, 0xb79e046a, 0x0c74fd8f, 0x4b2c3dda, 0xd3311cbf, 0x88f2b53c,
+ 0x0eb199d9, 0x0331ecf2, 0xdc9a2df9, 0xbf97e608, 0x7b4b47a7, 0x720628af,
+ 0x15cbf386, 0x1bdcbf3d, 0x2fc0bf03, 0xee84d45f, 0x7ca071e4, 0xf90930c9,
+ 0x25f21282, 0x17c84323, 0x505f21d4, 0x39e0be42, 0x90ea0be4, 0xbe43a82f,
+ 0x82f90ea0, 0xcf05f212, 0xa33e86bf, 0xd9386db8, 0x18b78bf3, 0x76afe03d,
+ 0xf9e2a86e, 0xdf6283e2, 0xe29d716e, 0xe45c1d01, 0xc5965fdf, 0xf42d7fdf,
+ 0x9e823b5f, 0x837b7dfc, 0xed45e299, 0x2fb475de, 0xe8d7bd5a, 0xf02f0a00,
+ 0xbc432f79, 0x1471dcd6, 0x977aa17a, 0xe2a258e2, 0xc79a34f9, 0x1f21a6ea,
+ 0x2df3c74d, 0xfa018766, 0x789be9a2, 0xa6b2bde8, 0x46bfa42d, 0x10b41c27,
+ 0x8615ebfe, 0xab14f1b8, 0x234a8fe0, 0xf6903a7f, 0x57fe498f, 0x9e299b5a,
+ 0x514dbe55, 0x25c404e7, 0x457d87aa, 0x7fb69ff6, 0x62bc4f3e, 0x3a9b5e95,
+ 0x393fe747, 0xfb403e29, 0xfe132ae1, 0x3b7f8064, 0x88e8fb0f, 0x98af1823,
+ 0x65fcbf68, 0xd82ac585, 0x83efd3b7, 0x5aed3597, 0xdeaecc91, 0x20e48767,
+ 0xfec6bd7e, 0xb90c88fa, 0x0d803e8f, 0xf63cbf80, 0xf73b39b1, 0xae75eff2,
+ 0xc9ff92b5, 0x0cd8e9e5, 0x4147574e, 0x472e1c87, 0xde28da0f, 0xecbad9f6,
+ 0xebc3c228, 0x79246646, 0xdbe487d9, 0xfe42b322, 0x77979718, 0x1bfa7066,
+ 0xc9367635, 0xae5c51d5, 0xdd1a9f02, 0xa2bafefd, 0x945fbc22, 0x2b9e92af,
+ 0xd15fb2b4, 0x09ff9c78, 0xe2664daf, 0x8aa5c2bb, 0xc5ebc0c7, 0x9f0161cc,
+ 0x8360e4cd, 0xcfd1a43d, 0xf90a75a2, 0xf0e6ed83, 0xed144a55, 0x477e5397,
+ 0xf3ec41b2, 0xfdcc3f27, 0x3ef3e20b, 0x1219ef04, 0x8b9973be, 0xc3e654f2,
+ 0x7f92367b, 0x6f0b4af4, 0x93eb0ae7, 0x6a3ae222, 0x7e2fc602, 0x4720ccc3,
+ 0xc8ee130a, 0xb6ccff02, 0xccca388a, 0x53bed7a6, 0x9a34de28, 0xdf1437f2,
+ 0xfbefc67d, 0xac3d90ff, 0x6a38dfcf, 0x7583ea2e, 0x665d031f, 0xf1f6e5f8,
+ 0xdfd5175a, 0xb2a12da8, 0x5dfee0fd, 0x75614798, 0xce7003b8, 0x4df88a30,
+ 0x20c4e1b2, 0x36fbeb15, 0x69f581dc, 0x8cb36172, 0x781864ef, 0x39b9e7c9,
+ 0x5e169454, 0xfbcfe10f, 0x06f912f2, 0x4953afb3, 0x1c26145e, 0x297b001c,
+ 0x8c3f1b5d, 0xc818908b, 0xc065a2ed, 0xb99233bb, 0xd23ec751, 0x31bf0e5a,
+ 0x7b028058, 0xc234ebd9, 0xd8a83dfe, 0xc9ddaa37, 0xedcb75d1, 0xc50ca3e0,
+ 0xabb0a8ae, 0xf3c616d7, 0x4b498cef, 0x739e4075, 0xadfa4ab9, 0xef02978d,
+ 0x8a8c7b37, 0x878a6be8, 0x74f02e9d, 0x44f5c532, 0xf3ff10c6, 0xda9f92f1,
+ 0x42452e9b, 0x7b08feff, 0x77c6336c, 0x8b639b33, 0x31741f1c, 0xb25f7fbe,
+ 0xea3a34cb, 0x08d84fac, 0xf521da3a, 0xefe9f4c4, 0xfe07e199, 0x0adaea87,
+ 0xe7319d3a, 0xb4f1e5ab, 0x20f5eece, 0x9051ab97, 0x507ac1ab, 0x4ab66fb3,
+ 0xd4f21abb, 0x9335ed24, 0xd24cd7b4, 0x7b49335e, 0x35ed24cd, 0x4cd7b493,
+ 0x49335ed2, 0xed24cd7b, 0xfde91335, 0x53be5405, 0x7365435b, 0x1fde9bad,
+ 0xc17110ca, 0xae2aec9e, 0xd7047c1f, 0x834a7b20, 0xd576375f, 0xaed2196b,
+ 0xd9a39f82, 0x436fe055, 0x6d5f7f00, 0x5acf4557, 0xbd67bb05, 0xf57d81c5,
+ 0xc6571631, 0x0f9270e2, 0x6b7465ef, 0x0cf0694f, 0x93abfb27, 0xfbe206d9,
+ 0x4dd27323, 0x4bff1fd8, 0xd6abc086, 0x3263fc0f, 0x7507f9e9, 0x67ca0ff0,
+ 0x07d59c2c, 0x4dc17b0b, 0xf08d82f6, 0x970962bd, 0x9b3ebc2b, 0xe57275d9,
+ 0x8c2394a2, 0x7c2ffd15, 0xc8935e7f, 0x4ae4d303, 0x76ef50df, 0x155beff4,
+ 0xc2dc40ea, 0x7f1e1889, 0x9717923e, 0x05af8207, 0xad5d1d7d, 0x583d1c50,
+ 0x4561ccee, 0xe46ebdf4, 0xdae0244e, 0xc9f4b07e, 0xda7e3e62, 0x9fa411d3,
+ 0x863ac766, 0x98f0e02e, 0x93fffde9, 0xd3e12737, 0x0e8cf871, 0x1e802c8d,
+ 0x8df5ab6d, 0x7c832cfb, 0x17efb137, 0xe5f14113, 0xf68526ea, 0x12e2aa7f,
+ 0x0d0b1f88, 0xc1cf1545, 0x4f79345f, 0x141d80af, 0x5af22117, 0x89c0de64,
+ 0xe00f6498, 0x55ad8273, 0x73666e28, 0xba726445, 0x40b79c9a, 0x0290fb11,
+ 0xc363891e, 0xf04c3e36, 0x3c021ecf, 0xa092824f, 0x9323f178, 0x0a4dbf60,
+ 0x0703aa0b, 0x547e1f14, 0xde8363d4, 0x65ef6827, 0xb3d4593d, 0x84991f32,
+ 0x36f971f8, 0x9d33fd9b, 0xd5d68bde, 0xec931bab, 0xe3e8059f, 0x1881fc72,
+ 0x62628675, 0x7be1fb01, 0xd6165714, 0x4bf63953, 0x1d65af11, 0x8e5957a4,
+ 0x937c043a, 0x3b20ee62, 0x698afdaf, 0xb053e52c, 0x03bbc88e, 0x9b67f8fc,
+ 0x183cf48c, 0x0a651f3f, 0x119d50f9, 0xa8f806be, 0xa1090c4a, 0xb22be9b2,
+ 0x28a99843, 0xdc9ffb03, 0x4438a04f, 0x33d7ff70, 0x753fd40d, 0x81c24585,
+ 0xf99551e3, 0x66eea263, 0xfbab18c3, 0x1b84a875, 0xb795c273, 0x77d51fa0,
+ 0x867461fe, 0xed13bdae, 0xf6c5effd, 0xca7fd6b4, 0x587f8d96, 0x07bf2196,
+ 0xc8c7997a, 0x1c664e1e, 0xa98446cf, 0x95ff847d, 0xf95d3159, 0x33fbc016,
+ 0xdbf23671, 0x03bcc393, 0xfe9ac740, 0x7a136cda, 0x194f4ba9, 0xd70b73c4,
+ 0x9aafd057, 0xe2915a9e, 0xc7c5969a, 0xd2ee364b, 0x40fb33fa, 0xdf4bcaa0,
+ 0x6027ded3, 0x6e08dc97, 0x1ca1b66b, 0x1ba37f0e, 0x1ccc5db8, 0xd9f000f1,
+ 0xe7e9e5c6, 0x6d58fb01, 0x81359161, 0xf20aaa78, 0x8e662e57, 0xff5a7ea4,
+ 0xfb031aca, 0xed29341c, 0x030ccaac, 0x232ab3e9, 0xced0a23b, 0xd12fc8a2,
+ 0x72e49dfa, 0xbf0e73ff, 0x401eb80f, 0xff9731f9, 0xb99ffef8, 0x09f947fc,
+ 0x7e78ff97, 0x947fcb8a, 0xe3fe5c2d, 0xff2e19f9, 0x2fb94e51, 0xa6f83062,
+ 0xfb0471ba, 0xb9cf6f5c, 0x93b9ed02, 0x97a7ba23, 0x9cbd2547, 0xfdfeed4c,
+ 0x5bfbdaf3, 0xe7dade05, 0xd4c6cf32, 0xd7cbf1ab, 0x38bac365, 0x5d832e5d,
+ 0xe4211ed0, 0xe3f4ac75, 0xfd4493da, 0x1f2299f7, 0x27c7cb81, 0x5d362ed1,
+ 0x434dbde4, 0xbf10d82e, 0x8fe9c9ff, 0xf1e6d1c6, 0x6b471ca6, 0x8c30c9e7,
+ 0xdf3374f5, 0x1da299f3, 0x6ffc27d1, 0x006a63d0, 0x44a9567d, 0xb174c19f,
+ 0x33ac4b32, 0xafc84c39, 0xd91b04e4, 0x41561987, 0x51da3d87, 0xd9067d1a,
+ 0xe4fa7e51, 0xdbf18a1f, 0xbbf93d4f, 0xa27f327b, 0x7c32bbbf, 0xe3f27741,
+ 0xfaf57f8b, 0x5e0cbe35, 0xfb7ba5b7, 0x7775a7b1, 0x7e82afe5, 0x270f91ba,
+ 0xfc646333, 0xc5d1d047, 0x6673674c, 0x0ab7912f, 0xabe5abbd, 0x3637af06,
+ 0x6a8fec5d, 0x4b32b1f4, 0xac64b3e8, 0xff3fdd2b, 0xdd2f7c24, 0xee4d3dff,
+ 0x542bad74, 0x9f0833ae, 0xebe15c9a, 0xaafc0cfa, 0x3b9353ad, 0x7ec4b2d3,
+ 0xb3af7b4f, 0x4ff1d633, 0x8710412f, 0x20da7bb7, 0x793461f2, 0x315cf5dd,
+ 0xa7989cce, 0x4ecce393, 0xf895b2f6, 0xd6edc7ca, 0x7dfee1dd, 0xd79d6d46,
+ 0x76758965, 0xedb93f4a, 0xb6f7e15b, 0x8538eef5, 0x93db6fb8, 0x8f8c3f62,
+ 0x6cf90138, 0x57631173, 0xb26c9f85, 0xc4d7ff08, 0xfde6d361, 0xfae214ea,
+ 0x11194fd5, 0xa7c66272, 0xf64299be, 0x1db341cc, 0x27d2f6fe, 0x7a0e3d1f,
+ 0x5141a2fb, 0x1adb8aa1, 0x67e09a38, 0xd8f08fae, 0x0d31fb78, 0x7f320e22,
+ 0x5483d19b, 0x556dcfd4, 0x4747f069, 0xf876653d, 0xbb79bb78, 0xe1cabe44,
+ 0x7f931727, 0xfb8785fa, 0x31dc7ccb, 0x218f07c6, 0x8cf65eee, 0xd963fe42,
+ 0x37a5b776, 0x14ea4bf6, 0xbf351bf2, 0x7bce42b7, 0x8fee7ade, 0xbc2ff6ea,
+ 0x6c951f64, 0xdb2f3fd0, 0xd457afac, 0xded8fdeb, 0xe0f95d59, 0xb83e4403,
+ 0xe4d557d8, 0x91f6d5e6, 0xaea7c85b, 0xe3afea3c, 0x1e379711, 0x4ce526fc,
+ 0x944fa8b8, 0xfebcd3f5, 0x6bbf8ca5, 0x9cfcd7f3, 0x60d8932f, 0xd825ec2f,
+ 0xebe22a97, 0x8e32469f, 0x96d0eaef, 0x5f0f893b, 0x1711da32, 0x7468dd5c,
+ 0x4d959e03, 0x3bb04db6, 0x8f6f10ab, 0x92179c00, 0xfb0dbfbe, 0x71f78845,
+ 0xe899b5bf, 0xebe299a6, 0x8f31d9cc, 0xd80f3df6, 0x55a3d0ec, 0xec747d2f,
+ 0x5507da3e, 0xdbe0b618, 0x5d10b6fa, 0xe44a7bcc, 0x04dff189, 0x2e9fa865,
+ 0x0578018c, 0xe107e7de, 0xf094f8d5, 0x8aede7b3, 0xe97a3f22, 0x0f874693,
+ 0xf815e174, 0x435c631d, 0x3f8e10f1, 0xa7a8efc2, 0x0a1e3cb6, 0xfb176ffc,
+ 0x705d1a0f, 0x7fbc203a, 0xdde041b1, 0xe1397072, 0xd24eadbd, 0x316ff601,
+ 0xd71116ce, 0xe90e9ee1, 0xfffc60c7, 0x6677bc54, 0xff713d0a, 0xbb99d384,
+ 0xc54e77f8, 0x03e67d9f, 0xe6db28fe, 0x086b3fba, 0x5f5feff6, 0x189c340e,
+ 0xe80063b7, 0x769e2ba0, 0x58ec26d0, 0xfc85040e, 0xa92f9903, 0x04f2de9e,
+ 0x7f7472e4, 0x33e2c3c7, 0x4e20242c, 0x1a77f1c3, 0x747b7876, 0x68fdceeb,
+ 0xc0eacbd7, 0xac9b2a72, 0xf4016b3e, 0x42dfa09f, 0x858cc74b, 0xb15f97b0,
+ 0xc2843ed2, 0xa9ce86c9, 0x31f6bd34, 0x4358f7f6, 0x1d6bb3a1, 0x773dfc69,
+ 0x945fe1e6, 0x90fb8487, 0x709e92af, 0xe6f64a8b, 0x11624734, 0x266dc3e5,
+ 0x8a7ed3ba, 0x4e316dfd, 0x1762f9bd, 0xcb38f87c, 0xcbf0fca5, 0xef93a677,
+ 0x5ca598cf, 0x0afec9ef, 0x765df392, 0xccef9497, 0x8bfa27dd, 0x66a2da30,
+ 0xebfc2794, 0x80b14c37, 0xe88566df, 0xf34b9345, 0x95398987, 0x13f97136,
+ 0xa229f147, 0x05ee73b7, 0xd0460cfb, 0xd1a327d5, 0xe8bb62af, 0x44741677,
+ 0xf1ef8dfe, 0xa2fede50, 0x577e4cd7, 0xf1c9bf17, 0xf095ce18, 0x143b55f7,
+ 0x55f1cb16, 0x456eb9ba, 0xa6e86eef, 0x745fdb9c, 0xf41ae90e, 0x7fa0d553,
+ 0x047209bf, 0xf965cbb0, 0x3e3c73df, 0xabe82194, 0xf289bf3b, 0x5045c653,
+ 0x8cb5473e, 0xb1cd571b, 0xe9a4df93, 0xa6fd1edd, 0xb11eb171, 0xe30faf3e,
+ 0x9533b89c, 0x97e250f2, 0x8ebbfc8a, 0x13d208e8, 0x19456d47, 0xafe8e718,
+ 0x1e81e5c7, 0xe9ae3d34, 0x695969b9, 0xd844bf34, 0xa9afb4c3, 0x6b1c810e,
+ 0xe20bde47, 0x7fe44ca5, 0xe42c8bba, 0x568faddf, 0xfaf03677, 0x923cd2fa,
+ 0x21fefbc7, 0xf71ddbe2, 0xaf5f485a, 0x1d34501f, 0xdefebb74, 0x65fef47e,
+ 0xfb047d45, 0x50d2ee26, 0x89faff9a, 0x7eb80e22, 0xffbd2262, 0x6258eb23,
+ 0x463abf42, 0x247face3, 0x7fb2e29f, 0x0dbd7108, 0xf72debfe, 0x3aa7d617,
+ 0xf9ff9093, 0xef7452b8, 0x1f978c5c, 0x7e69e34e, 0xfb7bd1fb, 0xf015b23d,
+ 0xdfe623e9, 0x11d8f5c6, 0xab5ecfae, 0x2c7944df, 0xfa7f3e5f, 0xfe5f8c4e,
+ 0x3e27a732, 0x047d5b7e, 0xf49c91f3, 0x2d6f1058, 0xf3ca306b, 0x93a1be14,
+ 0xfce50223, 0xfe879152, 0x3f908462, 0x099eadbb, 0xbed97fbc, 0xa7200b4f,
+ 0x38ea1edb, 0xe9fb0c96, 0x05e44579, 0xb00a5bb9, 0xea66584f, 0x956e4ede,
+ 0x03c5d3f6, 0x9760d361, 0x510edb29, 0x779949de, 0x50f219aa, 0x4b26776b,
+ 0x1dbcbfd8, 0xb7bb13ed, 0x8a1cf22b, 0x7ee0686f, 0x7c6796b2, 0x9fa0bb71,
+ 0xc7b346b2, 0xdb6df986, 0xea12f6d5, 0x201d5b1f, 0x5f6deac7, 0xa8ed3ed1,
+ 0x7ed27717, 0x8e25f602, 0xcebde2e8, 0x2afdc870, 0xb7aaa729, 0x551e4919,
+ 0xf38a5435, 0xa78cdb58, 0xddfdeea9, 0xce6ec657, 0x2619f1a1, 0xff89121b,
+ 0x14739192, 0xc5fcbefc, 0x1cdcfb83, 0x9e7be584, 0xbade848b, 0x1225bcd0,
+ 0x16e3e770, 0x77c4a25b, 0x4e73772f, 0x6373aaeb, 0x7ee485ac, 0xcd3577b5,
+ 0x251e02e3, 0x2e2fdd5d, 0x1bf3ea5b, 0xcfa40dd8, 0x9d92c5b7, 0x3437e7c4,
+ 0xb04d3cf0, 0xf9df2f3e, 0xfe6eb3cd, 0xd6eee2fe, 0x8adf3167, 0x3ca25c7f,
+ 0x8d8af621, 0x9faac8f2, 0xb3f490ff, 0x5b20afd6, 0xdb6d93d8, 0x3c8adb9f,
+ 0xb6ffb6d1, 0xdb5a303a, 0x2a29b3c1, 0xbebb93e2, 0x5f81fda3, 0x73a42c1e,
+ 0x3bdcbf30, 0xce87e12a, 0x3d6e802b, 0xdabafe59, 0xb180c248, 0x79ca5926,
+ 0x9c386e1e, 0xc97d7982, 0x0eed6bf1, 0x4788aa7f, 0x692b7955, 0x07f5001f,
+ 0xeaab7c39, 0xfd057e57, 0x55fc2d70, 0xebbe4c35, 0xdf24c196, 0x6aab601c,
+ 0xf2fb41d6, 0xf0bafdc1, 0xe3c701f6, 0x7f013ff5, 0x1e69abf5, 0x8dd1e25f,
+ 0x909bf757, 0xc4a8e52d, 0x730d37df, 0xad790bff, 0x775621ac, 0x6e10244e,
+ 0xb7011fbe, 0x2f7c4512, 0x3539db29, 0x7bb5fc1b, 0xede456c7, 0x54136f02,
+ 0x937d8be4, 0x4e7022c2, 0xc90663a5, 0x3b5683d1, 0xc1d95ae4, 0xda7f888f,
+ 0xff039e64, 0xb54f4385, 0x358bad75, 0x31919e93, 0x11cdeae2, 0x1fa46b3e,
+ 0x899e55fe, 0x7a48d563, 0x7b9e9a7e, 0x7e02fd04, 0xe793c0c9, 0x8fa4ddd0,
+ 0x7d68bd3d, 0x42ff9b95, 0x5c305bf6, 0x9dad9f7e, 0x4be3f02f, 0x9d3c0619,
+ 0x27b03b26, 0xb0f0693c, 0x04371e03, 0xe0b36de0, 0xd5f6e0bf, 0x2fb44f1c,
+ 0xfc04f129, 0xe63da325, 0xc3ea2919, 0xc47caea9, 0x6d0791ba, 0xc7f25675,
+ 0x79f682da, 0xce26fcfd, 0xc20eae1d, 0x9efeb6b3, 0xfceba3f8, 0xffe635c6,
+ 0x9bf3e153, 0x13e6956c, 0xc359a70c, 0xae14b3a2, 0x00c67122, 0x2f59f0f4,
+ 0x7e0879e6, 0xadb989a9, 0x4c7d6f1c, 0x1194de22, 0x8851dcc2, 0x3d84993b,
+ 0x2b07fc54, 0x5e28939d, 0x5c28f561, 0xdba6671e, 0xb93d20bf, 0x146ea6dc,
+ 0x18969dfd, 0x62a2cfea, 0xfe710524, 0xfe19d4a5, 0x017cbebd, 0xc27cfe06,
+ 0x038ba628, 0xd7f8959c, 0x54723bca, 0x7bb61f2a, 0x338f9042, 0xd12e596b,
+ 0xf765accd, 0xce1f6256, 0xf6461f55, 0x9bddeb65, 0x9778e2da, 0xde67a372,
+ 0x253e7c87, 0xd903ae39, 0xa78f9043, 0x00aee0ce, 0x61cf759b, 0xb9c3ce0b,
+ 0x7f6dd1bc, 0x74efede6, 0x79c267bf, 0x2b073b91, 0x93bff476, 0xb09f4979,
+ 0xcf48c3bb, 0x325fd6b5, 0x3ff1f225, 0x86cc2e1c, 0x05bb10e2, 0xe07799fb,
+ 0xf8374c5c, 0xe22d98be, 0xccfbda95, 0xca7575a0, 0x42d99df7, 0x8ba6663f,
+ 0x595673f7, 0xa247a74f, 0x79b2fb34, 0xc8ee65f9, 0x09ef3077, 0x93cc6ce9,
+ 0x2203e780, 0x8db4faaf, 0x07be08f9, 0xe21d93fb, 0x56b34562, 0xf94dbe63,
+ 0x1e9c2764, 0x44594f61, 0x67d89a7e, 0x92f32b9a, 0xdf108f4e, 0x896f6539,
+ 0x0213c988, 0xe228642b, 0x79f7e2fa, 0x73dfa5cd, 0xd7b36032, 0x3edd9087,
+ 0xb4c9b1f7, 0xbd7b3f3f, 0x0d6c8fd0, 0xec03c3b7, 0xe726cbe7, 0xd695c819,
+ 0x98a7e71c, 0xcf91a667, 0x8a49d38b, 0x0e04d3c4, 0xc3f6852c, 0x0720925a,
+ 0xcf96cc5f, 0xe159ed63, 0xec183e82, 0x7b66d3b6, 0xd38afc16, 0xd8066dcb,
+ 0x8a9613df, 0xb136ae79, 0xe18b9c50, 0xc26213f4, 0x3fec817e, 0xa8a9897d,
+ 0xc3ef3f8e, 0x3e08f8dd, 0x01ee1dfe, 0xfa030744, 0x3cc0deb9, 0x86c63dce,
+ 0xbd9cfec1, 0xf7e51d66, 0x7ee7f06a, 0xe7d1d922, 0x840ea4b6, 0x63e1a2bf,
+ 0x7f91bf40, 0xf0ba3ac3, 0xf042b770, 0x0e39ebe7, 0xdccbfebb, 0xe60e4a59,
+ 0x1837ca3d, 0x0fefe570, 0xc6854f01, 0x8ba015bc, 0x7a4638ce, 0xbe0993a9,
+ 0x3ccb5ce9, 0x56b0ee22, 0x8f8d5f07, 0x77f9be34, 0xb87173ed, 0x78699f10,
+ 0x76c1c19c, 0x1e3f40eb, 0x3cc47e34, 0x3da9030c, 0x7e3075f1, 0x10f7f053,
+ 0x73b6373a, 0x1255d63f, 0xd769fe4e, 0x6843c33a, 0x42e966df, 0xbe6af167,
+ 0x6b0b14de, 0xc3f7ae54, 0x80ae3ef5, 0xc2fe014c, 0xcc6c0bfd, 0x66872014,
+ 0xeaeb44d6, 0x3fde6bd3, 0xee53fc8a, 0x780f5e8f, 0x8bfc7a9f, 0xcfe23e67,
+ 0x217e3cb7, 0x5c63e453, 0xbe04f2dc, 0xce543ebb, 0x6bcc45a3, 0xebec85bd,
+ 0x3be8d4e2, 0x049d4bb7, 0x1316743f, 0x5cbc5f74, 0xdda7edd8, 0xcca9e50a,
+ 0x100a5c02, 0xaf04664f, 0x4ffc244f, 0x5acff849, 0x957de926, 0x8964efde,
+ 0x68fde52a, 0xc799e9fe, 0x1fc052b2, 0x5aea3f9a, 0xa555fc25, 0x3fed38e6,
+ 0x929fe0b9, 0xf7a4d69f, 0x098e6b47, 0xfdcdd47f, 0x5bf1c0d1, 0xace2fef4,
+ 0x6fb4dd9c, 0x762ad6cc, 0xd7c2ca84, 0xcec0b08e, 0x945e139a, 0xce7b7b02,
+ 0x7d44dbfa, 0xd27fc895, 0x47353ee0, 0x9ddd479c, 0xdbf2a26d, 0x88e3266c,
+ 0xf4681e42, 0xaae70738, 0x076bef41, 0xc805e658, 0xf9f259a7, 0x33831cec,
+ 0x3bba9e30, 0xbfa5c45b, 0x796b36cd, 0x68df6469, 0x0ce566ed, 0x92fc815c,
+ 0xc4466b59, 0x9afe00b1, 0xf6a26395, 0x2a3ce5bb, 0x9a9b907a, 0x49e7cf7d,
+ 0x2f6504fb, 0xec8178ec, 0xb888bffa, 0x32f5d941, 0x43cf2aff, 0x1db04b7e,
+ 0x5fc77a38, 0x5cafb123, 0x7b2460dd, 0xfec29784, 0xec225f58, 0xdead6e12,
+ 0x0e74f1ca, 0x745db9ed, 0x48bf85e4, 0xf65ae0ff, 0xa794a7e1, 0xad3e93d2,
+ 0x8a44ae56, 0x8f71083c, 0x577ca544, 0x7c4cd078, 0xe4407d52, 0xbdef545d,
+ 0xd5f3f944, 0xbbc79707, 0x8fff59ba, 0x9ad927b6, 0xc7daed6e, 0x00fc8272,
+ 0xd4bca313, 0x3e022145, 0x1fcc9e9d, 0xfd5c3f3c, 0x49f281a4, 0x146a4d3b,
+ 0xf23b6bf4, 0xff69bb33, 0x5fd08e7e, 0x61fe725f, 0x37aa37c8, 0x5ed6df92,
+ 0xaac0f22f, 0x763d1fea, 0xcdfbfc33, 0x2acb3e0a, 0xadc13359, 0xa3fb81aa,
+ 0x9136e781, 0xf3db1abf, 0x4477cb3c, 0xd4bf3c50, 0xf0b738ab, 0xa88674f9,
+ 0xe602bd51, 0xd0473fb3, 0x3bd5b977, 0xe722f094, 0x67fa13bf, 0x695dbf88,
+ 0xf7e4a3d3, 0x7f6d76f2, 0x18be6506, 0x9939c4c6, 0xcf30778e, 0x28830dd6,
+ 0xddea509e, 0x6bf94555, 0xd79461f5, 0xdbd14178, 0x3a4aaf73, 0xbfae557e,
+ 0x25e96b12, 0x2bfe07e6, 0xcc8e9ef5, 0x36cfede0, 0x5be54fbe, 0xe1a57e72,
+ 0xd7e005cd, 0xb4610db3, 0xe1b6733f, 0xc32f31e9, 0x888ef19f, 0xe4f80253,
+ 0x1f84727f, 0xb106e5fc, 0xb13cca0f, 0x2f159ef2, 0x3eb5abcd, 0xaddc4159,
+ 0xb6fde652, 0x3489ec36, 0x0b771e90, 0xfbb3fc38, 0x898a79b8, 0x71f6ebc5,
+ 0x7d61e5d7, 0x7dba2d21, 0xf8f77fdc, 0x80bb570c, 0x7f92ec7f, 0xe46ee18c,
+ 0x62da2c4b, 0xd199fe23, 0xe74a9d5f, 0x1334de45, 0xaae516fe, 0x969ee953,
+ 0xf9c52366, 0x1f32a517, 0x0fc588ec, 0x7c51d444, 0x61399137, 0x91d8ce97,
+ 0x53a3f14d, 0xe51b7b16, 0xa08becb7, 0x558aeffc, 0x8838c39c, 0xb8dd39cb,
+ 0x3c2b3c39, 0x75e2e606, 0x3708fec3, 0x88f781c5, 0xfa72b6ef, 0x1957bf86,
+ 0xb2aeec26, 0xbf4823e7, 0xe679a457, 0xc57af235, 0x00c049f3, 0xee8c656b,
+ 0x366f70bd, 0xf638dd93, 0xd764e3f1, 0x466d7a74, 0x5151738c, 0xfdcc0f29,
+ 0x2f3fc8ba, 0x6595be34, 0x792fede6, 0x97de0a6d, 0xf743513d, 0xf46c54a1,
+ 0x8be079d1, 0x62baff32, 0xf10b2f92, 0x3e818aee, 0x3dac373a, 0x2b5c8d2f,
+ 0xb07f72ea, 0xf3d79434, 0xe7914eb0, 0xf5116a53, 0xd76166d3, 0xa4f2485c,
+ 0x94975c60, 0x8bcf65bf, 0xf7e74273, 0xff21d446, 0x1b16fce4, 0x7d79ddc5,
+ 0x5a93d523, 0xf4fe7022, 0x82b34efc, 0xf2df9df5, 0xfe34aadc, 0x660bc2fe,
+ 0x90998fca, 0xdcf921ee, 0x03a858f1, 0x72c14d79, 0x42fcf822, 0x2708fed9,
+ 0xcad962f4, 0x9d63461b, 0x04764665, 0xb369e2f6, 0x8c69eb2f, 0x21cc3db3,
+ 0x27320dcf, 0xc655bbbe, 0xf48c7cfd, 0xf9adf9f7, 0x9daf9f94, 0x2b109cf3,
+ 0xcdec779e, 0xf9dff8a7, 0xb005b598, 0x7760cb6b, 0x0bcc7ce2, 0xf3ee49b3,
+ 0xf51a33ba, 0x4ef6fcdf, 0xf9153711, 0xde5215fa, 0x39bcae54, 0xd81be70a,
+ 0x37ca46bb, 0xf91264be, 0x5ff3c1e4, 0xcde52b9c, 0x6e8867be, 0xb8dd382b,
+ 0x137e5106, 0x79fcb1c1, 0xbe52c791, 0x4827e6e2, 0x6663bc8e, 0xe8bc67d8,
+ 0x7032347d, 0x397ee55f, 0x83bfbf8e, 0xf6f397da, 0x919bffa2, 0x66ad9f34,
+ 0x0c1ebf3a, 0xffdd1fd7, 0xd53fe379, 0xe22bccbf, 0xbfebc15f, 0xfd7f9ac4,
+ 0xebeede17, 0x4dc39b7a, 0x741e454f, 0x4f3bd9ab, 0x23618bdc, 0x168d6c3e,
+ 0xad6cf372, 0xbe576f38, 0xd27ffc62, 0xc989cefe, 0x7cce3774, 0x5ae7f74f,
+ 0xbb0ae566, 0x11d632a2, 0x7cafbe05, 0xc735f057, 0xffd45dcf, 0x0ff5335d,
+ 0xf6538f5e, 0xfc4e74e3, 0x9c53b1de, 0x7bf3e133, 0x8579a141, 0xad374019,
+ 0xe026adcb, 0x5687e35f, 0xbec08585, 0xea2d1d3f, 0x14decda7, 0x01c13fd1,
+ 0xe11d6a7a, 0xd79f814d, 0x68c6def5, 0xd955b29f, 0xc0e9cf45, 0x6ac5ce21,
+ 0x171c95fe, 0x97f38af4, 0x3a439815, 0x34d629f6, 0x1e435f43, 0xab28fec2,
+ 0xf949f611, 0x5d39fd36, 0x7fd4cf4e, 0xb388ae4f, 0xcb62e769, 0x13f90e31,
+ 0xa1e20b5e, 0x118f7f9c, 0xa844357d, 0xd457a788, 0xf261c7eb, 0xe3f52ddc,
+ 0x5bb94976, 0x7be2e671, 0xe29616cb, 0x65f2a51e, 0xa4a316eb, 0x8deef01f,
+ 0x94ab3e26, 0xc6abe7f1, 0xbefa0bb3, 0xf2952bb0, 0xf3939e53, 0x2777b0bb,
+ 0x44d4bfd9, 0xbc46ef93, 0x08fbc557, 0xadaf9d0f, 0xf3a566d8, 0xd9ff9a71,
+ 0xf834bad3, 0xc35f7f05, 0x2d5cdef3, 0xb73fa41e, 0x232e6afa, 0x95cdaffc,
+ 0xfb7125e7, 0xd67b8709, 0x9c6e8b06, 0x7afacd9c, 0x3d7d7abf, 0x2f5f41af,
+ 0x1dd7d268, 0xaf75f447, 0x7936eefc, 0x2ffc05bf, 0x515363dc, 0x3813f627,
+ 0x5e749dfe, 0xb88b5eec, 0x0afe0227, 0x3ed2a4ec, 0xffc06f64, 0x7df83f43,
+ 0x0fbf07e8, 0x287df875, 0x39e1f7e1, 0xe1d43efc, 0xbf0ea1f7, 0xbf08b54f,
+ 0xe3dc650f, 0x1e41e797, 0x74cd29b5, 0xbcf8367e, 0x0e32cded, 0xfcecde78,
+ 0xee97b738, 0xa827edfc, 0x0dedfce3, 0xfc4ede22, 0x91c62ecc, 0x22bceede,
+ 0x26db41ef, 0x65acdae4, 0xac5d3d66, 0xb9d3a809, 0xccbaa0d8, 0x6f5d2c0b,
+ 0x92e0bca1, 0x99fd410d, 0x7cec9637, 0xba9c672e, 0xf3c26ee7, 0x2843dba7,
+ 0x9953ebdf, 0xc795d0e7, 0xf94288fc, 0x5d9a6ca7, 0xe52493dc, 0x4572dff8,
+ 0x71e744be, 0xb3763f6e, 0xb395a11f, 0x70187c91, 0x35ecdc7f, 0xc9df018a,
+ 0xb1b808b4, 0xffda4693, 0xa4918961, 0xe17bb427, 0x065f61b2, 0x4f5cadc8,
+ 0xfd3d6ea8, 0xeae8c5b7, 0xbadedef9, 0xa637d7f6, 0xf00fdee9, 0x9fbdd3f5,
+ 0x4392f773, 0xc92f17f0, 0x9b4baf7d, 0x98cec813, 0xae9066bc, 0x9ba29cdf,
+ 0xcbe7ce83, 0x69bb4a79, 0x1668b9b1, 0xbc5a7fee, 0xf4e48937, 0xe76f3e1c,
+ 0x155e7920, 0xbdc519f1, 0x9d69e482, 0xce5d00e2, 0xd5807a96, 0x67e2f5e8,
+ 0x83b01e7c, 0xd026f62a, 0x262581fd, 0xd1acdf91, 0xe6bf6953, 0x2de59c02,
+ 0x50d37d7d, 0x634a99c8, 0xd39d8a5d, 0xcf152fd5, 0x76305c56, 0xfc576621,
+ 0xc77fd08d, 0x0c33bc87, 0x46f594fb, 0xade667ba, 0x7eff5704, 0xe80f90bd,
+ 0x8e181f8b, 0x7e84f07b, 0xc52ee8d6, 0xfe850f6c, 0x246b5bad, 0x1371197b,
+ 0xb1ea0c63, 0x7ee119a1, 0xf8b4c8fa, 0x3ac62cfa, 0x39e4db76, 0x1f9d48f5,
+ 0x23cc6851, 0xb8e971bd, 0x92abec91, 0x761b8a11, 0xed4eb69c, 0x3d6d2d7e,
+ 0x867f499f, 0x7e7188e5, 0xcc5fdf29, 0xf2a0543d, 0xd13c54f5, 0x5c446298,
+ 0x35bf50d1, 0xbab880c9, 0x51d60c6b, 0x11f99752, 0xfb2c07ee, 0x1760c8d0,
+ 0x547ebe7d, 0x93b08de4, 0xce299a76, 0x26ed72be, 0xccab4fba, 0xafc0b1e4,
+ 0x475ed92a, 0x70dbf5f1, 0xf3979cee, 0x7f9315b6, 0x202d9f39, 0x769ce93f,
+ 0x47848bef, 0x836548c9, 0xb9fbcf9d, 0x83def27e, 0x5d4f9150, 0x347e1c68,
+ 0x00e7f04e, 0x2eee9fc4, 0x862965da, 0xc44fd77d, 0xa3f98315, 0x85c9adf3,
+ 0x551ec8bd, 0xf13d0f08, 0xbc383dc7, 0xf261e9ce, 0xbbca9565, 0x3f23f72f,
+ 0xb9c643ed, 0x796d7915, 0xc4ad7f7a, 0x1c3bbea2, 0x9573837c, 0x191de70c,
+ 0xe450361b, 0x7284dc01, 0xdd855bbd, 0x7f5c3457, 0x0e8d91ce, 0x698bc9d3,
+ 0x387f802c, 0xb2414cdd, 0xeefd4065, 0x3e3ae909, 0xff777a98, 0xe8183e20,
+ 0x2f474f7f, 0x09e9d26f, 0xa80e3cca, 0x520f7e63, 0xae9c7a3c, 0xe49b255f,
+ 0xdefa076f, 0x15c11efc, 0x4fc88a79, 0xf1d513e2, 0xe3ba665b, 0xe3bfac23,
+ 0x67c5336d, 0x7b8ad6ab, 0x183e5136, 0x31916e70, 0x6e39388e, 0x34ceff14,
+ 0xf4bb0fee, 0xf039bb7a, 0x8ca54b9c, 0x84cfc05b, 0x6ee950dd, 0x80bf20b6,
+ 0x2c94d7c3, 0x7d821be0, 0x8f85760a, 0x62d3143f, 0xef046f64, 0xec3c63d3,
+ 0x171d541f, 0xefc156fb, 0x7ffee4ab, 0x880ae215, 0xabf1c897, 0xbd1af8e4,
+ 0x669e755d, 0xc863aedb, 0x245c995b, 0xf0abf3ee, 0x137ba44e, 0xcb3fc783,
+ 0xd79c47c9, 0xe7451e1c, 0x67e883f7, 0x7ee9531e, 0x8dc779cd, 0x1b5ea3cc,
+ 0x60e3880e, 0xbdd2afbf, 0x7de742c0, 0xd1ec2836, 0x0be9abd4, 0x8c5f80ed,
+ 0xbc4cf583, 0x7c74491c, 0x5c25fad5, 0xf414e0ba, 0x57dd783e, 0x1f8e4bc1,
+ 0x0b0d8fdc, 0xc7eba75a, 0x039353ad, 0xd3337ada, 0xe4212d9b, 0xd80e28e7,
+ 0x0b2e93b5, 0x83a35fff, 0x544d9729, 0x70922aaf, 0x7bbb7891, 0x5f8e9842,
+ 0xb8f01ef0, 0x68bc72e7, 0x93a62fff, 0xd414e0ab, 0x6baf8b5f, 0x17cfd6f2,
+ 0xcbec7f62, 0x6c7f727e, 0xfc421b08, 0x4f5fe52a, 0x07afca72, 0xc9767d04,
+ 0x17b7297f, 0xf804d599, 0xef1e9abf, 0x35268392, 0x3ec03a2a, 0x0ffae628,
+ 0x1a1627f7, 0x173dd0fb, 0x5a47192e, 0xce9d2cb1, 0xd4726bf7, 0x633dc725,
+ 0xc7205356, 0x5f3fcb5d, 0xa77d8357, 0x11f6e847, 0x9624b296, 0x36c57be2,
+ 0x2f179d3b, 0xf22c625e, 0x9f1b1950, 0xd5bdf811, 0x6ebdd1b7, 0x4eb3ae9f,
+ 0x355f2eeb, 0xb388bfae, 0x31fe3e56, 0x0d2f9be9, 0x034e456f, 0x1bdf2d7f,
+ 0xf29ed489, 0xb50fefe5, 0x28b97973, 0x1fde95c1, 0x4752b676, 0xebd996fa,
+ 0x694f600a, 0x796cbe7a, 0x72f40261, 0x3f0e3fc5, 0x5aecbd0b, 0xfe478e62,
+ 0xc40ff9cc, 0x67ae3439, 0x439f9f48, 0xf61c5c72, 0x7ee8c245, 0xa1e35289,
+ 0xdf4ebb02, 0x77c14d35, 0xba1e282f, 0x6c9ee3ef, 0x70e65df1, 0x739ef9d3,
+ 0x7ec5cedc, 0xa6496b86, 0x704c5cee, 0x57ea55b9, 0x6128cbd8, 0x8794c2f7,
+ 0xd3fa8bdd, 0xf6125f72, 0x7fb0ea2f, 0xfcebbef1, 0x78a32563, 0xcc4562cc,
+ 0xb942f177, 0xab9f52cf, 0x835f7bc3, 0xaf673f58, 0x96efcc24, 0x05036e0e,
+ 0x2e2fe1d0, 0x73c0b087, 0xb4582388, 0x242a3eae, 0xd0bed749, 0x7f7baa9e,
+ 0xeeae625b, 0x00eaedfd, 0xce7c7d5d, 0x77f6ba8d, 0xeae84638, 0x5dbb0d77,
+ 0x73a27ed7, 0x793eaea2, 0xf6babdec, 0xeb1514f7, 0x569d4fde, 0xaf7f7baa,
+ 0x7eaea16b, 0xba03c95f, 0x582ff7f6, 0x17df7ba2, 0x5f1cdb79, 0x7ee2b54d,
+ 0xd3b3274e, 0xdf8b0f7d, 0x6afba4ce, 0x75f7915f, 0xf57b0f0e, 0xfa61ca92,
+ 0xf7abdc41, 0xb87ce68c, 0xc42836d8, 0x1f3af14a, 0x98a3bdf9, 0x9928f780,
+ 0xf5c2c787, 0x3eda75f9, 0x7383be09, 0xa51718d7, 0x7ec39e4f, 0x79efe715,
+ 0xbf9e4479, 0xf7f3863f, 0x21db5e74, 0xf3cbd7ce, 0xfce16ff7, 0x1adb9d3d,
+ 0x3cb3654b, 0x76a27f7f, 0xd41f951a, 0xc9dfa8ba, 0x3f2a12da, 0xcf405dae,
+ 0x435b5cff, 0x6eb527e5, 0x3ed57e7a, 0x61b7dc8c, 0x2fe8a62d, 0x2efbfc42,
+ 0xfd1bcb3d, 0x0c07a139, 0x0f8887ce, 0xc93b1f58, 0x6fbcf92d, 0x9e39739e,
+ 0xe8cc6677, 0x70f6103b, 0xea356ba2, 0xbd9c0cf7, 0xebd38a3c, 0x302cae2f,
+ 0xf61fce03, 0x666f1e70, 0x69e7617f, 0x0bf4ecfb, 0xde0f2fd8, 0x45b76c47,
+ 0xb65ee016, 0x71767d80, 0xabee442e, 0x717e4bb7, 0x87e462f7, 0x4c23fd6a,
+ 0xe81867cc, 0xf6d797df, 0xdd781303, 0x8d3bde22, 0x89df4ea2, 0xf2203f80,
+ 0xc8394d21, 0xca249803, 0x125f58e4, 0x2f26adce, 0x2f39d0b6, 0xed110ff4,
+ 0x37dfe8dd, 0x26e74bc6, 0xd38556fb, 0x59abcdfb, 0xc8f20e48, 0x6672884f,
+ 0x8bd6957f, 0x9fa2617e, 0x70e1df0f, 0x9b70017c, 0x23eb7d1c, 0x9fae1c2d,
+ 0xf776ba25, 0xbde1f2e7, 0x075f6a83, 0x98a4eb87, 0xf0ce7bf4, 0xe20d13e7,
+ 0xe09ebcde, 0x8357ada8, 0x1fa706a7, 0xe1abd70b, 0xbf001de9, 0x4e195dde,
+ 0x0abfd3fe, 0xe370c18e, 0x780a399c, 0xe461f733, 0x0a87273f, 0x384b2638,
+ 0x9cd1186e, 0x86d5788a, 0xb9d0855f, 0x570b1fd6, 0xe2a7b82e, 0xaae3d39e,
+ 0x537d1bc8, 0x69fb13ae, 0xfaf80203, 0x72405b38, 0x3759ab81, 0x825a34e0,
+ 0x7cde546c, 0x5cc653b2, 0xc5165a29, 0xef0e8ddb, 0x3b4adf7e, 0xbc9b7a97,
+ 0x9c4c664f, 0x27181ede, 0x7db188ed, 0xe8679e82, 0xe5fd1deb, 0x4b2a56be,
+ 0x668d7f05, 0xb62f310e, 0x68fee486, 0x2593f729, 0xb3b9d3bc, 0x429d7c86,
+ 0xa98132e6, 0x2a6e636f, 0x2a1e676f, 0xf51f33c7, 0x3e3383bf, 0x107177ea,
+ 0xd2115ea3, 0xcf2b8291, 0xffae8cab, 0xb2fcbe81, 0x761b2baf, 0x3bb0e1fa,
+ 0x2ca723a7, 0x6032e0c9, 0xa0d462df, 0x7a679451, 0x04e2cda4, 0x2d1d5e1c,
+ 0x1abf69ce, 0x0ffa4e92, 0xf18e65f4, 0xf2ebe1d3, 0xb5c3801e, 0xa3809ee2,
+ 0x138027b8, 0x27b86bdd, 0xe5c7d780, 0x37e8612c, 0x97efd546, 0x3bc7fd6b,
+ 0x0fd33247, 0xfe3f77dc, 0xb07d83fa, 0x7466f89f, 0xdfd5c536, 0xee81be8c,
+ 0x3a337c9d, 0xab4a20c1, 0xfdfcca85, 0x77dbbb83, 0xffc4e8d4, 0x14cc31bd,
+ 0x3db6fd8b, 0x2b73f055, 0xaf3e44c3, 0xc3047f73, 0xbda2c6fe, 0xf3821ee2,
+ 0xe0126898, 0xec17e626, 0x65ad9f37, 0xb64eb07d, 0xff9e8a2d, 0xdcc8d24a,
+ 0xfc689b9a, 0xa8c33579, 0x572c89df, 0x717ae001, 0xa7cb2fa0, 0x5821dfe0,
+ 0xf613791a, 0x3a305ec7, 0x15f6f026, 0x838d7546, 0x228c7df6, 0x61caf82f,
+ 0x6d92b7ba, 0x91d9d58e, 0x2211595a, 0x1f65dfe6, 0x3efa0a86, 0xe5f25ac5,
+ 0xf19bcbb9, 0x71d624bd, 0xb5e5e714, 0xe342e3fc, 0xafb85395, 0x8226b3b2,
+ 0x44660bf2, 0x7c4c51a9, 0xc86bf697, 0x527ec0b7, 0xa5e29db5, 0x7c0f86b8,
+ 0xf13ae33e, 0x14662d9c, 0x927eca37, 0xeb98f0e9, 0x39e5d109, 0xd766dff4,
+ 0x89bdf3d5, 0x37d7f6ba, 0x03f7baaa, 0xf81e3fb8, 0xf283cf9e, 0x113c679e,
+ 0x8321fb4f, 0xef743b8e, 0xd30f3487, 0x9c819ff5, 0x9e49c440, 0xbffc9130,
+ 0xeea763e1, 0xe51c5f7d, 0xcabdc18a, 0x7ce37563, 0xe32a9f92, 0xba8ec2ad,
+ 0xee915cf9, 0x0a0804fd, 0xc0f8ff3a, 0xc8e1ce63, 0xf775929b, 0x9ce3efdb,
+ 0x2635b3e9, 0x1bcfcfaa, 0xa073853a, 0xcb8a1f3f, 0xe05fc821, 0xc5cbcad6,
+ 0x615f22f9, 0x5eed6c25, 0xe3cce701, 0x2759d118, 0xceb97113, 0xaf2e8b1a,
+ 0xd2a625c6, 0x325db725, 0x9ddfe5df, 0x01e9a357, 0x332bf726, 0x7a10f3fc,
+ 0x1e7dddc5, 0xa4d7968d, 0x6d17342e, 0xa8fca70c, 0x9c804ab1, 0xe22f9158,
+ 0x384a2f36, 0x87fc1da0, 0xb3fdda9e, 0xd9f4d270, 0xc14e0bbf, 0x5e1a81f9,
+ 0x601e6c7e, 0xced3f04f, 0xd08cae37, 0xca9f9be7, 0x2478f013, 0x9fcbec4f,
+ 0x06f1ed56, 0x733e1fa3, 0xdf92331f, 0x7e446ac0, 0x3c9f7686, 0x177d7373,
+ 0x630f87ef, 0x0d37f145, 0xeb8efc46, 0xdefb9545, 0x3d7c464e, 0xa9e2ad6b,
+ 0x128eb053, 0x53270fca, 0xcd9f3f90, 0x70e21f9f, 0xaf77762e, 0x49fbb4ff,
+ 0x7e0aaf66, 0xeefda2ef, 0xcdff52f9, 0x1f7fab5d, 0xe73747ec, 0x60e7fd49,
+ 0x658bf20e, 0x875b52fc, 0xee029f76, 0x09ff87c5, 0x81fb083d, 0x006b3e97,
+ 0x6bf0a8dd, 0x0e75fd63, 0xd81cd0cf, 0xdd4ccb31, 0xf06a13ee, 0x66ab8e0c,
+ 0x997c445a, 0x82e713ed, 0x45eb38b4, 0x774159c4, 0x5784ecd3, 0xd17f6c97,
+ 0xc44dfdcd, 0xf4ac1b7f, 0x7f70a9ef, 0xea9a4a76, 0xf6afb3f7, 0xe22459cf,
+ 0xbdf59dc5, 0x27abaf28, 0x316ae7bd, 0x57f8e2e8, 0x97b25fbd, 0xd8acf9ee,
+ 0x8af0fc29, 0x33e3879d, 0xb7dff402, 0x839f2279, 0xa77fd1fb, 0xbf19047c,
+ 0x9ebffb2e, 0x38139402, 0x5d7e02bd, 0x5c577ffe, 0x70ddf259, 0xe9d3d791,
+ 0x9d65f916, 0x1f5a1563, 0x7c0c6f97, 0x652f15d6, 0x55f63376, 0xb5d7ff34,
+ 0x41e1186a, 0x7d8b83f3, 0xf71d68c3, 0xc66f9d2c, 0xefacd091, 0xb9c48ed7,
+ 0x15fb96b1, 0xdfaa43c7, 0x2be96e4f, 0x7f3441f6, 0x9e4fd839, 0xe341d97c,
+ 0x26f97dde, 0xe42faf1a, 0x9732f237, 0xf910b23d, 0x31b6fd66, 0x62d1e033,
+ 0x68dcfeee, 0x232b94ae, 0xfdbf05f3, 0x5c1ef9d3, 0x7c98fc5c, 0xeeb5fc8f,
+ 0xee21b0a3, 0x0476d0d8, 0x7b044b65, 0xb84be156, 0x5313e761, 0xb7af5c4c,
+ 0x689494d8, 0xcf2b375e, 0xebcd194c, 0x536fb92e, 0x800c3ac0, 0x4bee4bab,
+ 0xfce27cba, 0xc83f16ac, 0xde512eff, 0x74f82f7f, 0x7da30340, 0xd6bded4b,
+ 0x46ecc1df, 0x8b674f94, 0xbd7f437d, 0x3fdd76a7, 0x0ffb8adf, 0x3eb75c39,
+ 0xea4e66c4, 0x25f3ae06, 0x761ab75c, 0x5af38abd, 0xe50ac51d, 0x5dafe44b,
+ 0x2f721030, 0xe38ec4cb, 0xf2bbed86, 0x5dbea5a3, 0xcce21370, 0x3b34bcda,
+ 0x460e96f5, 0x3bc37679, 0xff0e6598, 0x335f2dce, 0x11e85ccb, 0xe557dcab,
+ 0xda8fb0fd, 0x3738addf, 0xbdf9d006, 0xd6bf62f9, 0x13785ee5, 0xfe971dfe,
+ 0x9a6e0bf5, 0x2612bd0b, 0x5ff73dfa, 0x3ba70491, 0x711b2997, 0x7af0ff0f,
+ 0xed7e44e6, 0xfeef392c, 0x1ccb76f5, 0x32ddaefa, 0xb58e3037, 0xfd82c521,
+ 0x32d662df, 0x1fdbee9a, 0x5ffc50ac, 0xd75f1383, 0x938bac11, 0xc3d871e8,
+ 0xba7a6eff, 0x21747065, 0x9bb843f6, 0xdca7f74f, 0x3978b831, 0x79751fee,
+ 0xa7c40e9c, 0xc17af96f, 0x2e6faa51, 0xc7913aa2, 0x03e5b150, 0x2b76cebe,
+ 0xe448b0be, 0xe219d783, 0x2f15e454, 0x5d5cfba1, 0xb101ccf5, 0x0d9ac796,
+ 0x238bef38, 0x5f94b19c, 0xfa242f60, 0x40b0ad1a, 0x239a42fa, 0xf5b56df2,
+ 0xe0cbcb07, 0x9f972538, 0xb8e98f22, 0x14f524d9, 0xfb962fbd, 0x9996970b,
+ 0xef167e49, 0xa0f38ab5, 0x8b52f241, 0x49b9725f, 0x1b3b51e7, 0x5fbed3c6,
+ 0x290fc2c5, 0xd521784e, 0xd39a35b3, 0x5db485e9, 0x42a58653, 0x139232ee,
+ 0xc86dee5c, 0xd8fc821f, 0xd29f94a3, 0xf243dee2, 0xc7b2d2f2, 0x855c0522,
+ 0xc247383f, 0x1714b987, 0x7895979d, 0xf717ce28, 0x15a99cb2, 0xc8e7b667,
+ 0x71a175f8, 0x45e431f8, 0xce20da5f, 0xb7eb062b, 0x4fa2ab59, 0x1e64bf62,
+ 0x9d4f45d6, 0x7e401f22, 0x687984a7, 0x9974beff, 0xc1d0e299, 0xea5cb0fa,
+ 0xbc7be0cd, 0xdaefef82, 0x37a41f9f, 0xeda6bda5, 0x7dbf16e7, 0xdb921ef8,
+ 0x0f32cc0b, 0x7e0f4f41, 0x7f3e0b7c, 0x89efca57, 0xbe494397, 0x9bdcba4c,
+ 0x72e538e0, 0x2f539522, 0x49b37d8b, 0xefc845e0, 0x4fce8542, 0xf4e52fbc,
+ 0x0347d83d, 0x4409dc9e, 0x4e9c9da7, 0x4e7ea9f1, 0x95dc30e5, 0x8952d329,
+ 0x2ac6729e, 0x9dcd9f14, 0xf9085d1e, 0x39e40770, 0xf20d306f, 0x5ce8107d,
+ 0x31dee7e4, 0x8d4fa358, 0xd03c85be, 0x67a353f8, 0x09b4fb97, 0xadc3bd78,
+ 0x4bb0be50, 0xd13de1da, 0x4f9bbfeb, 0xc63fa49b, 0xf98bb0fd, 0xe3a60474,
+ 0xd61fa070, 0x20ecf07e, 0xdaade3d0, 0x2bee37bd, 0xdc4fe053, 0xd754161a,
+ 0x1b71bdee, 0x363d52a6, 0xef76bde8, 0xf797568d, 0xb85f98de, 0x7c5fe532,
+ 0x00b98def, 0x517cbceb, 0xcf834ebf, 0xdbb88d96, 0x901f22ad, 0x3e524785,
+ 0x3ce5e763, 0x8858dbf2, 0x979dbb90, 0xe9fd537b, 0x67c89957, 0xf940cefb,
+ 0x70aa966c, 0x49a9f813, 0x5c026df1, 0xfe10286e, 0xafb833d8, 0xabd9e881,
+ 0x56453be0, 0x43530f71, 0x80be2ba2, 0x2afe6fbf, 0xa7207334, 0xf498e69b,
+ 0xf8ae1cff, 0xfcd37bef, 0x6fa4a701, 0xfda4e9c5, 0x28476722, 0xaa2bc3e5,
+ 0xb8a74d89, 0x6b79d053, 0xf326dfdc, 0xaf579085, 0xa1ea67f5, 0xdbf794d9,
+ 0x4ff24211, 0x63bda71b, 0xdfdc00df, 0xee115ed0, 0x672079c0, 0x0a77c893,
+ 0xbb9db71e, 0xde6f8419, 0x3709c69f, 0xb3b0fe50, 0xf0c7f0e9, 0xd573b417,
+ 0xe189de96, 0x5a9dbbb0, 0x639e199c, 0x6fb71c40, 0xe714b1ef, 0xc5d598e0,
+ 0x37da999f, 0x714ffc1a, 0x4c7a64dd, 0xe52d5ffc, 0xf552fc66, 0x76ffe45d,
+ 0x7fa46ebc, 0xdf31835f, 0x92f3c0a0, 0x74d20b23, 0xd7efc479, 0xd622fb8a,
+ 0x048d1524, 0xd3c999be, 0xfddd7617, 0x11325a57, 0x79d53a1f, 0x197799ee,
+ 0x0db85f9d, 0xdf3ae3ef, 0x7f3d7e58, 0x7dffcafe, 0x0fd3ce9e, 0x79d0b637,
+ 0x42c97679, 0x37ea70f4, 0xee07a66f, 0x502acc97, 0x022f7de4, 0x347e1a5f,
+ 0x8784f4bc, 0x08407576, 0xff87e916, 0xf3e091b7, 0x32fdc36b, 0xe0d1ef9d,
+ 0xaf7c13dd, 0xe7abd705, 0x3feae22b, 0x86e3df30, 0x7ce57ff4, 0xe8dfc86b,
+ 0xfacdbe71, 0xe2b7fef9, 0xfc9f01ac, 0xfe5cfe5c, 0xfe5cfe5c, 0xfe5cfe5c,
+ 0xfe5cfe5c, 0xfe5cfe5c, 0x5e5cfe5c, 0x4f7ffcab, 0x00219aed, 0x000080
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x40c83584,
+ 0x86d2ab2c, 0xcd9f6e20, 0x193757e9, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x3fb6db6d, 0xf55d017e, 0x8000de46, 0x0000
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x40c83584,
+ 0x86d2ab2c, 0xcd9f6e20, 0x193757e9, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x3fb6db6d, 0xf55d017e, 0x8000de46, 0x0000
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x40c83584,
+ 0x86d2ab2c, 0xcd9f6e20, 0x193757e9, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x3fb6db6d, 0xf55d017e, 0x8000de46, 0x0000
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x40c83584,
+ 0x86d2ab2c, 0xcd9f6e20, 0x193757e9, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x3fb6db6d, 0xf55d017e, 0x8000de46, 0x0000
+ };
+static const u32 EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7[] = {
+ 0x00088b1f, 0x00000000, 0xc5ed0300, 0x20000141, 0x33b00408, 0x40c83584,
+ 0x86d2ab2c, 0xcd9f6e20, 0x193757e9, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x6db6db6d, 0xdb6db6db, 0xb6db6db6, 0x6db6db6d,
+ 0xdb6db6db, 0xb6db6db6, 0x3fb6db6d, 0xf55d017e, 0x8000de46, 0x0000
+ };
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE0,
+ 0, 13355);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE1,
+ 8192, 14614);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE2,
+ 16384, 13895);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE3,
+ 24576, 94);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE4,
+ 32768, 94);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE5,
+ 40960, 94);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE6,
+ 49152, 94);
+ INIT_GUNZIP_DMAE(XSEM, XSEM_REGISTERS_PRAM, COMMON,
+ INIT_HARDWARE, EVST_XSEM_PRAM_COMMON_MEMORY_INIT_HARDWARE7,
+ 57344, 94);
+}
+
--
1.4.2
^ permalink raw reply related
* [BNX2X][PATCH 7/8] bnx2x_self_test.h
From: Eliezer Tamir @ 2007-10-07 16:25 UTC (permalink / raw)
To: davem, jeff, netdev@vger.kernel.org, Michael Chan
bnx2x_self_test.h
This file contains a self-test derived from HW specs, and the code that
prints HW/FW/BC assert codes.
Signed-off-by: Eliezer Tamir <eliezert@broadcom.com
<mailto:eliezert@broadcom.com>>
---
drivers/net/bnx2x_self_test.h | 1387
+++++++++++++++++++++++++++++++++++++++++
1 files changed, 1387 insertions(+), 0 deletions(-)
diff --git a/drivers/net/bnx2x_self_test.h b/drivers/net/bnx2x_self_test.h
new file mode 100644
index 0000000..b1d62e7
--- /dev/null
+++ b/drivers/net/bnx2x_self_test.h
@@ -0,0 +1,1387 @@
+/* bnx2x_self_test.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ */
+
+/* self test */
+static int bnx2x_idle_chk(struct bnx2x *bp)
+{
+ u32 val, i, val2;
+ u32 errors = 0;
+ u32 warnings = 0;
+ u32 varr[32];
+ u32 usem_foc_credits[4] = {26, 78, 16, 32};
+ u32 xsem_foc_credits[4] = {0, 24, 12, 102};
+ u32 csem_foc_credits[4] = {16, 18, 48, 14};
+ u32 tsem_foc_credits[4] = { 52, 24, 12, 32};
+ u32 foc_num = 0;
+ u8 err_pkt = 0;
+ u32 pci_reg;
+/* Disable timer scans for port 0,1 */
+/* is_enable_timer0 = lm_disable_timer(pdev, 0); */
+/* is_enable_timer1 = lm_disable_timer(pdev, 1); */
+
+
+/* Check errors on PCI configuration space ucorr_err_status 0x114 */
+/* check port 0 */
+ val = REG_RD(bp, GRCBASE_PXPCS, 0x2114);
+ if ((val & 0x1FF010) != 0x0) {
+ BNX2X_ERR("Error PCIE IP function %d,"
+ " ucorr_err_status is not 0x0. Equal to 0x%x\n",
+ bp->port, val);
+ err_pkt = 1;
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXPCS, 0x2120);
+ if (((val & 0x31C1) != 0x2000) && ((val & 0x31C1) != 0)) {
+ BNX2X_ERR("Error PCIE IP function %d,"
+ " corr_err_status is not 0x2000. Equal to 0x%x\n",
+ bp->port, val);
+ err_pkt = 1;
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXPCS, 0x2814);
+ if ((val != 0x40100) && (val != 0)) {
+ BNX2X_ERR("Error PCIE IP function %d,"
+ " attentions register is not 0x40100. Equal to 0x%x\n",
+ bp->port, val);
+ err_pkt = 1;
+ errors++;
+ }
+
+ if (err_pkt) {
+ pci_reg = 0x212c;
+ for (i = 0; i < 4; i++) {
+ val = REG_RD(bp, GRCBASE_PXPCS, pci_reg+i*4);
+ BNX2X_ERR("Error PCIE IP function %d,"
+ " error packet header %d Equal to 0x%x\n",
+ bp->port, i, val);
+ }
+ }
+
+/* Check that all VQs in PXP are empty */
+ varr[0] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT);
+ varr[1] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT);
+ varr[2] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT);
+ varr[3] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT);
+ varr[4] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT);
+ varr[5] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT);
+ varr[6] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT);
+ varr[7] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT);
+ varr[8] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT);
+ varr[9] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT);
+ varr[10] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT);
+ varr[11] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT);
+ varr[12] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT);
+ varr[13] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT);
+ varr[14] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT);
+ varr[15] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT);
+ varr[16] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT);
+ varr[17] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT);
+ varr[18] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT);
+ varr[19] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT);
+ varr[20] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT);
+ varr[21] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT);
+ varr[22] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT);
+ varr[23] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT);
+ varr[24] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT);
+ varr[25] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT);
+ varr[26] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT);
+ varr[27] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT);
+ varr[28] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT);
+ varr[29] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT);
+ varr[30] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT);
+ varr[31] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT);
+
+ for (i = 0; i < 32; i++) {
+ if (varr[i] != 0) {
+ if ((i == 3) && (varr[i] <= 2)) {
+ continue;
+ } else {
+ BNX2X_ERR("Error, PXP, VQ%d is not empty."
+ " Fill level equal to %d\n",
+ i, varr[i]);
+ errors++;
+ }
+ }
+ }
+
+/* Check that PXP2 register rq_ufifo_num_of_entry is 0 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY);
+ if (val != 0) {
+ BNX2X_ERR("Error, PXP, rq_ufifo_num_of_entry is not zero."
+ " value equals %d\n", val);
+ errors++;
+ }
+
+ /* Check that rq_rbc_done is 1 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_RBC_DONE);
+ if (val != 1) {
+ BNX2X_ERR("Error, PXP, rq_rbc_done is not 1."
+ " value equals %d\n", val);
+ errors++;
+ }
+
+ /* Check that rq_cfg_done is 1 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RQ_CFG_DONE);
+ if (val != 1) {
+ BNX2X_ERR("Error, PXP, rq_cfg_done is not 1. "
+ "value equals %d\n", val);
+ errors++;
+ }
+
+ /* Check that rq_read_credit and rq_write_credit are 3 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_PSWRQ_BW_CREDIT);
+ if (val != 0x1B) {
+ BNX2X_ERR("Error, PXP, rq_read_credit and rq_write_credit "
+ "are not 3. value equals %d\n", val);
+ errors++;
+ }
+
+ /* Check that rd_start_init is 1 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_START_INIT);
+ if (val != 1) {
+ BNX2X_ERR("Error, PXP, rd_start_init is not 1."
+ " value equals %d\n", val);
+ errors++;
+ }
+
+/* Check that rd_init_done is 1 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_INIT_DONE);
+ if (val != 1) {
+ BNX2X_ERR("Error, PXP, rd_init_done is not 1. "
+ "value equals %d\n", val);
+ errors++;
+ }
+
+/* Check that rd_sr_cnt equals rd_sr_num_cfg */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_SR_CNT);
+ val2 = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_SR_NUM_CFG);
+ if (val != (val2-1)) {
+ BNX2X_ERR("Warning, PXP, rd_sr_cnt != rd_sr_num_cfg-1."
+ " values are %d %d\n", val, val2);
+ warnings++;
+ }
+
+/* Check that rd_blk_cnt equals rd_blk_num_cfg */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_BLK_CNT);
+ val2 = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_BLK_NUM_CFG);
+ if (val != val2) {
+ BNX2X_ERR("Error, PXP, rd_blk_cnt is not equal to "
+ "rd_blk_num_cfg. values are %d %d\n", val, val2);
+ errors++;
+ }
+/* Check that delivery ports are idle */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_PORT_IS_IDLE_0);
+ if (val != 1) {
+ BNX2X_ERR("Error PXP2 P0, All delivery ports are not idle."
+ " Equal to %d\n", val);
+ errors++;
+ }
+
+/* Check that delivery ports are idle */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_PORT_IS_IDLE_1);
+ if (val != 1) {
+ BNX2X_ERR("Error PXP2 P1, All delivery ports are not idle."
+ " Equal to %d\n", val);
+ errors++;
+ }
+
+/* Check that rd_almost_full is 0 */
+ varr[0] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_0);
+ varr[1] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_1);
+ varr[2] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_2);
+ varr[3] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_3);
+ varr[4] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_4);
+ varr[5] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_5);
+ varr[6] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_6);
+ varr[7] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_7);
+ varr[8] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_8);
+ varr[9] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_9);
+ varr[10] = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_ALMOST_FULL_10);
+ for (i = 0;i < 11; i++) {
+ if (varr[i] != 0) {
+ BNX2X_ERR("Error, PXP, rd_almost_full_%d is not zero."
+ " Value is %d\n", i, varr[i]);
+ errors++;
+ }
+ }
+
+ /* Check that host i/f data and descriptor FIFOs are empty */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_HST_HEADER_FIFO_STATUS);
+ if (val != 0) {
+ BNX2X_ERR("Error PXP2 HST, header FIFO status is not"
+ " empty and is equal to %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_HST_DATA_FIFO_STATUS);
+ if (val != 0) {
+ BNX2X_ERR("Error PXP2 HST, data FIFO status is not"
+ " empty and is equal to %d\n", val);
+ errors++;
+ }
+
+ /* Check that pgl_write_blocked and pgl_read_blocked is 0 */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_PGL_WRITE_BLOCKED);
+ if (val != 0) {
+ BNX2X_ERR("Error PXP2 pgl_write_blocked is not zero and is"
+ " equal to %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_PGL_READ_BLOCKED);
+ if (val != 0) {
+ BNX2X_ERR("Error PXP2 pgl_read_blocked is not zero and is "
+ "equal to %d\n", val);
+ errors++;
+ }
+
+/* Check that the HST I/F arbiter is idle*/
+ val = REG_RD(bp, GRCBASE_PXP, PXP_REGISTERS_HST_ARB_IS_IDLE);
+ if (val != 1) {
+ BNX2X_ERR("Error PXP HST, arbiter is not idle! %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXP, PXP_REGISTERS_HST_CLIENTS_WAITING_TO_ARB);
+ if (val != 0) {
+ BNX2X_ERR("Error PXP HST, one of the clients is"
+ " waiting for delivery: 0x%x\n", val);
+ errors++;
+ }
+
+/* On PXP2 (glue) check that tag_is_ready is equal to 1
+ and that data_is_ready is equal to 0*/
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_PGL_TXR_CDTS);
+ if (((val>>5)&1) != 1) {
+ BNX2X_ERR("Error, PXP2: Tag is not ready.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_PGL_TXW_CDTS);
+ if (((val>>17)&1) != 0) {
+ BNX2X_ERR("Error, PXP2 There is data which is ready.\n");
+ errors++;
+ }
+
+/* Check that all SR are unused (counter equal to 127)*/
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_SR_CNT);
+ if (val < 123) {
+ BNX2X_ERR("Error, PXP2, The number of unused SRs < 123."
+ " Equal to %d\n", val);
+ errors++;
+ }
+
+/* Check that all read blocks are unused */
+ val = REG_RD(bp, GRCBASE_PXP2, PXP2_REGISTERS_RD_BLK_CNT);
+ if (val < 156) {
+ BNX2X_ERR("Error, PXP2, The number of unused Read blocks "
+ "< 156. Equal to %d\n", val);
+ errors++;
+ }
+/* Check that DMAE registers go_co..c15 are zero */
+ varr[0] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C0);
+ varr[1] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C1);
+ varr[2] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C2);
+ varr[3] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C3);
+ varr[4] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C4);
+ varr[5] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C5);
+ varr[6] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C6);
+ varr[7] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C7);
+ varr[8] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C8);
+ varr[9] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C9);
+ varr[10] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C10);
+ varr[11] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C11);
+ varr[12] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C12);
+ varr[13] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C13);
+ varr[14] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C14);
+ varr[15] = REG_RD(bp, GRCBASE_DMAE, DMAE_REGISTERS_GO_C15);
+ for (i = 0;i < 16; i++) {
+ if (varr[i] != 0) {
+ BNX2X_ERR("Error, DMAE, GO_C%d is not empty. "
+ "Value is %d\n", i, varr[i]);
+ errors++;
+ }
+ }
+
+/* Check that all AC counters are empty (expect leading connection 0) */
+ for (i = 0; i < CFC_REGISTERS_ACTIVITY_COUNTER_SIZE ; i++) {
+ val = REG_RD(bp, GRCBASE_CFC,
+ CFC_REGISTERS_ACTIVITY_COUNTER + i*4);
+ if ((val != 0) && (i != 0)) {
+ BNX2X_ERR("Error, CFC: LCID %d, AC is not zero. "
+ "AC equal to %d\n", i, val);
+ errors++;
+ }
+ }
+
+/* Check that all QM queues are empty */
+ for (i = 0; i < 64 ; i++) {
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_QTASKCTR_0 + i*4);
+ if (val != 0) {
+ BNX2X_ERR("Error, QM: Q %d, Queue is not empty. "
+ "Fill level is: %d\n", i, val);
+ errors++;
+ }
+ }
+
+/* Check that all VOQ 0 credit is full */
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQINITCREDIT_0);
+ val2 = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQCREDIT_0);
+ if (val2 != val) {
+ BNX2X_ERR("Error, QM: VOQ0, VOQ credit not equal to initial"
+ " credit. credit: %d, initial credit: %d\n",
+ val2, val);
+ errors++;
+ }
+
+/* Check that all VOQ 1 credit is full */
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQINITCREDIT_1);
+ val2 = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQCREDIT_1);
+ if (val2 != val) {
+ BNX2X_ERR("Error, QM: VOQ1, VOQ credit not equal to initial"
+ " credit. credit: %d, initial credit: %d\n",
+ val2, val);
+ errors++;
+ }
+
+/* Check that all VOQ 4 credit is full */
+ /* Check that all VOQ 1 credit is full */
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQINITCREDIT_4);
+ val2 = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQCREDIT_4);
+ if (val2 != val) {
+ BNX2X_ERR("Error, QM: VOQ4, VOQ credit not equal to initial."
+ " credit: %d, initial credit: %d\n", val2, val);
+ errors++;
+ }
+
+/* Check that all byte credit for port 0 credit is full */
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_BYTECRDINITVAL);
+ val2 = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_PORT0BYTECRD);
+ if (val2 != val) {
+ BNX2X_ERR("Error, QM: port0, Byte credit not equal to initial"
+ " credit. credit: %d, initial credit: %d\n",
+ val2, val);
+ errors++;
+ }
+
+/* Check that all byte credit for port 1 credit is full */
+ val2 = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_PORT1BYTECRD);
+ if (val2 != val) {
+ BNX2X_ERR("Error, QM: port1, Byte credit not equal to initial "
+ "credit. credit: %d, initial credit: %d\n",
+ val2, val);
+ errors++;
+ }
+
+/* Check that XXq lock tables are empt */
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_CAM_OCCUP);
+ if (val != 0) {
+ BNX2X_ERR("Error, CCM: CAM is not empty. "
+ "Occupancy equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_CAM_OCCUP);
+ if (val != 0) {
+ BNX2X_ERR("Error, XCM: CAM is not empty. "
+ "Occupancy equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_CAM_OCCUP);
+ if (val != 0) {
+ BNX2X_ERR("Error, TCM: CAM is not empty. "
+ "Occupancy equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_CAM_OCCUP);
+ if (val != 0) {
+ BNX2X_ERR("Error, UCM: CAM is not empty. "
+ "Occupancy equal to: %d\n", val);
+ errors++;
+ }
+
+/* Check that BRB1 is empty: */
+ val = REG_RD(bp, GRCBASE_BRB1, BRB1_REGISTERS_NUM_OF_FULL_BLOCKS);
+ if (val != 0) {
+ BNX2X_ERR("Error, BRB: is not empty. Occupancy equal to:"
+ " %d\n", val);
+ errors++;
+ }
+
+/* SEMI checks */
+/* 1. check thread ready is equal to 0 */
+ val = REG_RD(bp, GRCBASE_TSEM, TSEM_REGISTERS_SLEEP_THREADS_VALID);
+ if (val != 0) {
+ BNX2X_ERR("Error, TSEM: There are slebping threads. "
+ "Slebp mask is equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSEM, XSEM_REGISTERS_SLEEP_THREADS_VALID);
+ if (val != 0) {
+ BNX2X_ERR("Error, XSEM: There are slebping threads."
+ " Slebp mask is equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_USEM, USEM_REGISTERS_SLEEP_THREADS_VALID);
+ if (val != 0) {
+ BNX2X_ERR("Error, USEM: There are slebping threads."
+ " Slebp mask is equal to: %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSEM, CSEM_REGISTERS_SLEEP_THREADS_VALID);
+ if (val != 0) {
+ BNX2X_ERR("Error, CSEM: There are slebping threads."
+ " Slebp mask is equal to: %d\n", val);
+ errors++;
+ }
+
+/* 2. check external store fifo is empty */
+
+ val = REG_RD(bp, GRCBASE_TSEM, TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, TSEM: External store FIFO is not empty\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSEM, XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, XSEM: External store FIFO is not empty\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_USEM, USEM_REGISTERS_SLOW_EXT_STORE_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, USEM: External store FIFO is not empty\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSEM, CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, CSEM: External store FIFO is not empty\n");
+ errors++;
+ }
+
+/*SDM checks*/
+/*1. Input queue empty
+#set name [format "%sSDM_REGISTERS_QUEUE_EMPTY" $ins]
+#set level [reg_read -n $name]
+#if {$level != 1 } {
+# puts "Error, $ins-SDM: Parser input queue is not empty."
+# incr errors
+#}*/
+
+/*2. Parser serial FIFO check*/
+ val = REG_RD(bp, GRCBASE_TSDM, TSDM_REGISTERS_SYNC_PARSER_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, TSDM: Parser serial FIFO is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSDM, XSDM_REGISTERS_SYNC_PARSER_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, XSDM: Parser serial FIFO is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_USDM, USDM_REGISTERS_SYNC_PARSER_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, USDM: Parser serial FIFO is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSDM, CSDM_REGISTERS_SYNC_PARSER_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, CSDM: Parser serial FIFO is not empty.\n");
+ errors++;
+ }
+
+/*3. Parser serial FIFO check */
+
+ val = REG_RD(bp, GRCBASE_TSDM, TSDM_REGISTERS_SYNC_SYNC_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, TSDM: Parser SYNC serial FIFO "
+ "is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSDM, XSDM_REGISTERS_SYNC_SYNC_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, XSDM: Parser SYNC serial FIFO "
+ "is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_USDM, USDM_REGISTERS_SYNC_SYNC_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, USDM: Parser SYNC serial FIFO "
+ "is not empty.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSDM, CSDM_REGISTERS_SYNC_SYNC_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, CSDM: Parser SYNC serial FIFO "
+ "is not empty.\n");
+ errors++;
+ }
+
+/*4. pxp_ctrl rd_data fifo empty in sdm_dma_rsp block*/
+ val = REG_RD(bp, GRCBASE_TSDM, TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, TSDM: pxp_ctrl rd_data fifo not empty in "
+ "sdm_dma_rsp block.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSDM, XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, XSDM: pxp_ctrl rd_data fifo not empty in "
+ "sdm_dma_rsp block.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_USDM, USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, USDM: pxp_ctrl rd_data fifo not empty in "
+ "sdm_dma_rsp block.\n");
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSDM, CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY);
+ if (val != 1) {
+ BNX2X_ERR("Error, CSDM: pxp_ctrl rd_data fifo not empty in "
+ "sdm_dma_rsp block.\n");
+ errors++;
+ }
+
+/*DORQ fill level check */
+ val = REG_RD(bp, GRCBASE_DQ, DORQ_REGISTERS_DQ_FILL_LVLF);
+ if (val != 0) {
+ BNX2X_ERR("Error, DORQ: DORQ is not empty. Occupancy equal to:"
+ " %d.\n", val);
+ errors++;
+ }
+
+/*Check that all interrupt statuses are zero.*/
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_CFC_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, CFC: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CDU, CDU_REGISTERS_CDU_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, CDU: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_CCM_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, CCM: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_XCM_INT_STS);
+ if (val != 0x0) {
+ BNX2X_ERR("Error, XCM: Interrupt status is not 0x0. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_TCM_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, TCM: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_UCM_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, UCM: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_PBF_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, PBF: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_TIMERS, TM_REGISTERS_TM_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, TIMERS: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_DQ, DORQ_REGISTERS_DORQ_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, DORQ: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_SRCH, SRC_REGISTERS_SRC_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, SRC: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PRS_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, PRS: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_BRB1, BRB1_REGISTERS_BRB1_INT_STS);
+ if ((val & ~0xFC00) != 0) {
+ BNX2X_ERR("Error, BRB1: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+/* Check pxp PORT 0 interrupts */
+ val = REG_RD(bp, GRCBASE_PXP, PXP_REGISTERS_PXP_INT_STS_0);
+ if (val != 0) {
+ BNX2X_ERR("Error, PXP 0: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+/* Check pxp PORT 1 interrupts */
+ val = REG_RD(bp, GRCBASE_PXP, PXP_REGISTERS_PXP_INT_STS_1);
+ if (val != 0) {
+ BNX2X_ERR("Error, PXP 1: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+/* Check UPB interrupts */
+ val = REG_RD(bp, GRCBASE_UPB, PB_REGISTERS_PB_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, PB: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+/* Check XPB interrupts */
+ val = REG_RD(bp, GRCBASE_XPB, PB_REGISTERS_PB_INT_STS);
+ if (val != 0) {
+ BNX2X_ERR("Error, PB: Interrupt status is not zero. "
+ "Pending interrupts equal to 0x%x.\n", val);
+ errors++;
+ }
+
+/*Check credits of the DORQ to the XCM*/
+ val = REG_RD(bp, GRCBASE_DQ, DORQ_REGISTERS_RSPA_CRD_CNT);
+ if (val != 2) {
+ BNX2X_ERR("Error DORQ, Credit to XCM is not full. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+/*Check credits of the DORQ to the UCM*/
+ val = REG_RD(bp, GRCBASE_DQ, DORQ_REGISTERS_RSPA_CRD_CNT);
+ if (val != 2) {
+ BNX2X_ERR("Error DORQ, Credit to UCM is not full."
+ " Value is %d\n", val);
+ errors++;
+ }
+
+/* Check there are no QM VOQ and byte credit errors*/
+ val = REG_RD(bp, GRCBASE_QM, QM_REGISTERS_VOQCRDERRREG);
+ if (val != 0) {
+ BNX2X_ERR("Error QM, Credit error register is not zero"
+ "(byte or credit overflow/underflow). Value is %d\n",
+ val);
+ errors++;
+ }
+/* Check that CFC num_lcid_inside is <=2 */
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_NUM_LCIDS_INSIDE);
+ if (val > 2) {
+ BNX2X_ERR("Error CFC, num_lcid_inside is larger than 2. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_ERROR_VECTOR);
+ if (val != 0) {
+ BNX2X_ERR("Error CFC, error vector is not zero. Value is %d\n",
+ val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_NUM_LCIDS_ARRIVING);
+ if (val != 0) {
+ BNX2X_ERR("Error CFC, number of arriving LCIDs is not zero. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_NUM_LCIDS_ALLOC);
+ if (val != 0) {
+ BNX2X_ERR("Error CFC, number of alloc LCIDs is not zero. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_NUM_LCIDS_LEAVING);
+ if (val != 0) {
+ BNX2X_ERR("Error CFC, number of leaving LCIDs is not zero. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+
+ val = REG_RD(bp, GRCBASE_CFC, CFC_REGISTERS_NUM_LCIDS_LEAVING);
+ if (val != 0) {
+ BNX2X_ERR("Error CFC, number of leaving LCIDs is not zero. "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_DQ, DORQ_REGISTERS_DQ_FULL_ST);
+ if (val != 0) {
+ BNX2X_ERR("Error DORQ_REGISTERS_DQ_FULL_ST is not zero "
+ "Value is %d\n", val);
+ errors++;
+ }
+
+ /* Check AEU registers (func 0) */
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0);
+ if ((val & ~0xCFFC) != 0) {
+ BNX2X_ERR("Warning MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0"
+ " after mask !=0 (%x). no support of "
+ "UNICORE in driver yet\n", (val & ~0xCFFC));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0);
+ if (val != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0"
+ " is not zero. Value is %x\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0);
+ if ((val & ~0xC2000000) != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0 !=0 "
+ "(%x). no MCP code.\n", (val & ~0xC2000000));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0);
+ if ((val & ~0xFFFFFF) != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0"
+ " after mask is not zero. Value is %x\n",
+ (val & ~0xFFFFF));
+ warnings++;
+ }
+
+ /* Check AEU registers (func 1) */
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1);
+ if ((val & ~0xCFFC) != 0) {
+ BNX2X_ERR("Warning MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1"
+ " after mask !=0 (%x)\n", (val & ~0xCFFC));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1);
+ if (val != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1"
+ " is not zero. Value is %x\n", val);
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1);
+ if ((val & ~0xC2000000) != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1"
+ " !=0 (%x). no MCP code.\n", (val & ~0xC2000000));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC,
+ MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1);
+ if ((val & ~0xFFFFFF) != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1"
+ " after mask is not zero. Value is %x\n",
+ (val & ~0xFFFFF));
+ warnings++;
+ }
+
+ /* Check AEU registers (MCP) */
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP);
+ if ((val & ~0xCFFC) != 0) {
+ BNX2X_ERR("Warning MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP"
+ " after mask !=0 (%x).\n", (val & ~0xCFFC));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP);
+ if (val != 0) {
+ BNX2X_ERR("Warning MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP is"
+ " not zero. Value is %x\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP);
+ if ((val & ~0xC2000000) != 0) {
+ BNX2X_ERR("Warning MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP !=0 "
+ "(%x). no MCP code.\n", (val & ~0xC2000000));
+ warnings++;
+ }
+ val = REG_RD(bp, GRCBASE_MISC, MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP);
+ if ((val & ~0xFFFFFF) != 0) {
+ BNX2X_ERR("Error MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP"
+ " after mask is not zero. Value is %x\n",
+ (val & ~0xFFFFF));
+ warnings++;
+ }
+
+ /* Add idle checks for PBF block */
+ if (!REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0)) {
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P0_CREDIT);
+ val2 = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P0_INIT_CRD);
+ if (val != val2) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P0_CREDIT %d "
+ "differs PBF_REGISTERS_P0_INIT_CRD %d\n",
+ val, val2);
+ errors++;
+ }
+ }
+
+ if (!REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P1)) {
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P1_CREDIT);
+ val2 = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P1_INIT_CRD);
+ if (val != val2) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P1_CREDIT %d"
+ " differs PBF_REGISTERS_P1_INIT_CRD %d\n",
+ val, val2);
+ errors++;
+ }
+ }
+
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P4_CREDIT);
+ val2 = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P4_INIT_CRD);
+ if (val != val2) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P4_CREDIT %d differs"
+ " PBF_REGISTERS_P4_INIT_CRD %d\n", val, val2);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P0_TASK_CNT);
+ if (val != 0) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P0_TASK_CNT is not zero."
+ " Value is %d \n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P1_TASK_CNT);
+ if (val != 0) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P1_TASK_CNT is not zero."
+ " Value is %d \n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PBF, PBF_REGISTERS_P4_TASK_CNT);
+ if (val != 0) {
+ BNX2X_ERR("Error PBF, PBF_REGISTERS_P4_TASK_CNT is not zero."
+ " Value is %d \n", val);
+ errors++;
+ }
+
+ /* Extra checks for XCM blocks */
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_CFC_INIT_CRD);
+ if (val != 1) {
+ BNX2X_ERR("Error XCM, XCM_REGISTERS_CFC_INIT_CRD != 1,"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_XQM_INIT_CRD);
+ if (val != 32) {
+ BNX2X_ERR("Error XCM, XCM_REGISTERS_XQM_INIT_CRD != 32,"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_TM_INIT_CRD);
+ if (val != 4) {
+ BNX2X_ERR("Error XCM, XCM_REGISTERS_TM_INIT_CRD different "
+ "than 4,Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_FIC0_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error XCM, XCM_REGISTERS_FIC0_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_FIC1_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error XCM, XCM_REGISTERS_FIC1_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ /* Extra checks for UCM blocks */
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_CFC_INIT_CRD);
+ if (val != 1) {
+ BNX2X_ERR("Error UCM, UCM_REGISTERS_CFC_INIT_CRD different"
+ " than 1, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_UQM_INIT_CRD);
+ if (val != 32) {
+ BNX2X_ERR("Error UCM, UCM_REGISTERS_UQM_INIT_CRD different"
+ " than 32, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_TM_INIT_CRD);
+ if (val != 4) {
+ BNX2X_ERR("Error UCM, UCM_REGISTERS_TM_INIT_CRD different"
+ " than 4, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_FIC0_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error UCM, UCM_REGISTERS_FIC0_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_FIC1_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error UCM, UCM_REGISTERS_FIC1_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ /* Extra checks for TCM blocks */
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_CFC_INIT_CRD);
+ if (val != 1) {
+ BNX2X_ERR("Error TCM, TCM_REGISTERS_CFC_INIT_CRD different "
+ "than 1, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_TQM_INIT_CRD);
+ if (val != 32) {
+ BNX2X_ERR("Error TCM, TCM_REGISTERS_TQM_INIT_CRD different "
+ "than 32, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_FIC0_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error TCM, TCM_REGISTERS_FIC0_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_FIC1_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error TCM, TCM_REGISTERS_FIC1_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ /* Extra checks for CCM blocks */
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_CFC_INIT_CRD);
+ if (val != 1) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_CFC_INIT_CRD different"
+ " than 1, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_CQM_INIT_CRD);
+ if (val != 32) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_TQM_INIT_CRD different"
+ " than 32, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_FIC0_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_FIC0_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_FIC1_INIT_CRD);
+ if (val != 64) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_FIC1_INIT_CRD different"
+ " than 64, Value is %d\n", val);
+ errors++;
+ }
+ /* Extra checks for FOC credits */
+ for (foc_num = 0; foc_num < 4; foc_num++) {
+ val = REG_RD(bp, GRCBASE_USEM,
+ (USEM_REGISTERS_FAST_MEMORY +
+ 0x18000+foc_num*0x40));
+ if (val != usem_foc_credits[foc_num]) {
+ BNX2X_ERR("Error USEM, FOC%d_CREDIT different than %d,"
+ " Value is %d\n",
+ foc_num, usem_foc_credits[foc_num], val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_XSEM,
+ (XSEM_REGISTERS_FAST_MEMORY +
+ 0x18000 + foc_num*0x40));
+ if (val != xsem_foc_credits[foc_num]) {
+ BNX2X_ERR("Error XSEM, FOC%d_CREDIT different than %d,"
+ " Value is %d\n",
+ foc_num, xsem_foc_credits[foc_num], val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CSEM,
+ (CSEM_REGISTERS_FAST_MEMORY +
+ 0x18000 + foc_num*0x40));
+ if (val != csem_foc_credits[foc_num]) {
+ BNX2X_ERR("Error CSEM, FOC%d_CREDIT different than %d,"
+ " Value is %d\n",
+ foc_num, csem_foc_credits[foc_num], val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_TSEM,
+ (TSEM_REGISTERS_FAST_MEMORY +
+ 0x18000 + foc_num*0x40));
+ if (val != tsem_foc_credits[foc_num]) {
+ BNX2X_ERR("Error TSEM, FOC%d_CREDIT different than %d, "
+ "Value is %d\n",
+ foc_num, tsem_foc_credits[foc_num], val);
+ errors++;
+ }
+ }
+
+ /* Extra PRS checks */
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_TSDM_CURRENT_CREDIT);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_TSDM_CURRENT_CREDIT "
+ "different than 0,"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_TCM_CURRENT_CREDIT);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_TCM_CURRENT_CREDIT "
+ "different than 0,"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_CFC_LD_CURRENT_CREDIT);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_CFC_LD_CURRENT_CREDIT "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_CFC_SEARCH_CURRENT_CREDIT);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_CFC_SEARCH_CURRENT_CREDIT "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_SRC_CURRENT_CREDIT);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_SRC_CURRENT_CREDIT "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_PRS_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_PRS_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC0_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC0_RQ "
+ "different than 0,Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC1_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC1_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC2_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC2_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC3_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC3_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC4_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC0_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_PENDING_BRB_CAC4_RQ);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_PENDING_BRB_CAC0_RQ "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_SERIAL_NUM_STATUS_LSB);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_SERIAL_NUM_STATUS_LSB "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_PRS, PRS_REGISTERS_SERIAL_NUM_STATUS_MSB);
+ if (val != 0) {
+ BNX2X_ERR("Error PRS, PRS_REGISTERS_SERIAL_NUM_STATUS_MSB "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+
+ val = REG_RD(bp, GRCBASE_CDU, CDU_REGISTERS_ERROR_DATA);
+ if (val != 0) {
+ BNX2X_ERR("Error CDU, CDU_REGISTERS_ERROR_DATA "
+ "Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_STORM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_STORM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_CSDM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_CSDM_LENGTH_MIS "
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_TSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_TSEM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_XSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_XSEM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_CCM, CCM_REGISTERS_USEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_USEM_LENGTH_MIS"
+ "Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, CCM_REGISTERS_PBF_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, CCM_REGISTERS_PBF_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_STORM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_STORM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_TSDM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_TSDM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_PRS_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_PRS_LENGTH_MIS"
+ "Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_PBF_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_PBF_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_USEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_USEM_LENGTH_MIS"
+ " Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_USEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_USEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_TCM, TCM_REGISTERS_CSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, TCM_REGISTERS_CSEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_STORM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_STORM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_USDM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_USDM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_TSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_TSEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_CSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_CSEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_XSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_XSEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_UCM, UCM_REGISTERS_DORQ_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, UCM_REGISTERS_DORQ_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_STORM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_STORM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_XSDM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_XSDM_LENGTH_MIS "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_TSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_TSEM_LENGTH_MIS "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_CSEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_CSEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_USEM_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_USEM_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_DORQ_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_DORQ_LENGTH_MIS"
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_DORQ_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_DORQ_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_PBF_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_PBF_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_NIG0_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_NIG0_LENGTH_MIS"
+ " different than 0, Value is %d\n", val);
+ errors++;
+ }
+ val = REG_RD(bp, GRCBASE_XCM, XCM_REGISTERS_NIG1_LENGTH_MIS);
+ if (val != 0) {
+ BNX2X_ERR("Error CCM, XCM_REGISTERS_NIG1_LENGTH_MIS "
+ "different than 0, Value is %d\n", val);
+ errors++;
+ }
+
+ if (errors == 0) {
+ BNX2X_ERR("completed successfuly (with %d warnings)\n",
+ warnings);
+ } else {
+ BNX2X_ERR("failed (with %d errors, %d warnings)\n",
+ errors, warnings);
+ }
+ return errors;
+}
+
+static int bnx2x_mc_assert(struct bnx2x *bp)
+{
+ u8 i, j;
+ int rc = 0;
+ char last_idx;
+ const char storm[] = {"XTCU"};
+ const u32 intmem_base[] = {
+ BAR_XSTRORM_INTMEM,
+ BAR_TSTRORM_INTMEM,
+ BAR_CSTRORM_INTMEM,
+ BAR_USTRORM_INTMEM
+ };
+
+ /* Go through all instances of all SEMIs */
+ for (i = 0; i < 4; i++) {
+ last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET,
+ intmem_base[i]);
+ BNX2X_ERR("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n",
+ storm[i], last_idx);
+
+ /* print the asserts */
+#define STROM_ASSERT_ARRAY_SIZE 50
+ for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) {
+ u32 row0, row1, row2, row3;
+ row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j),
+ intmem_base[i]);
+ row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4,
+ intmem_base[i]);
+ row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8,
+ intmem_base[i]);
+ row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12,
+ intmem_base[i]);
+
+ if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+ BNX2X_ERR("DATA %cSTORM_ASSERT_INDEX 0x%x ="
+ " 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ storm[i], j, row3, row2, row1, row0);
+ rc++;
+ } else {
+ break;
+ }
+ }
+ }
+ return rc;
+}
+
--
1.4.2
^ permalink raw reply related
* Re: duplicated u32 filters in tc show output
From: jamal @ 2007-10-07 16:43 UTC (permalink / raw)
To: Abhijit Menon-Sen; +Cc: netdev
In-Reply-To: <20071006131056.GA17693@toroid.org>
On Sat, 2007-06-10 at 18:40 +0530, Abhijit Menon-Sen wrote:
> The HTB user guide (http://luxik.cdi.cz/~devik/qos/htb/manual/userg.htm)
> says the following:
>
> Note: The U32 classifier has an undocumented design bug which causes
> duplicate entries to be listed by "tc filter show" when you use U32
> classifiers with different prio values.
>
> What exactly is this bug? (I'm seeing its effects, i.e. the duplicates,
> and it's making my life a little difficult while trying to parse the tc
> output.)
If it is the bug i think it is - then it was fixed a long time ago; the
doc you are referencing seemed to be dated.
Try a newer kernel if you are not and if it still persists, send the
simplest setup you have that causes duplicates.
cheers,
jamal
^ permalink raw reply
* Re: MSI interrupts and disable_irq
From: Manfred Spraul @ 2007-10-07 16:54 UTC (permalink / raw)
To: Jeff Garzik
Cc: Yinghai Lu, Ayaz Abdulla, nedev, Linux Kernel Mailing List,
David Miller, Andrew Morton
In-Reply-To: <4707CCF1.8080909@pobox.com>
Jeff Garzik wrote:
>
> Interested parties should try the forcedeth patches I just posted :)
>
The patches look good, but I would still prefer to understand why the
current implementation causes crashes before rewriting everything.
I've just noticed that netpoll_send_skb() calls ->hard_start_xmit() and
->poll() within local_irq_save().
Thus it seems that spin_lock_irqsave() must be used in the poll() and
hard_start_xmit() callbacks, at least in nics that support
POLL_CONTROLLER :-(
--
Manfred
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