* [PATCH 10/14 v2] nes: eeprom and phy routines
From: ggrundstrom @ 2007-10-19 20:21 UTC (permalink / raw)
To: ewg, rdreier; +Cc: general, ggrundstrom, netdev
Misc eeprom, phy, and debug routines.
Signed-off-by: Glenn Grundstrom <ggrundstrom@neteffect.com>
---
--- NULL 1969-12-31 18:00:00.000000000 -0600
+++ ofa_kernel-1.3/drivers/infiniband/hw/nes/nes_utils.c 2007-10-19 09:43:32.000000000 -0500
@@ -0,0 +1,873 @@
+/*
+ * Copyright (c) 2006 - 2007 NetEffect, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/if_vlan.h>
+#include <linux/crc32.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/byteorder.h>
+
+#include "nes.h"
+
+#define BITMASK(X) (1L << (X))
+#define NES_CRC_WID 32
+
+static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
+
+static u32 nesCRCTable[256];
+static u32 nesCRCInitialized = 0;
+
+static u32 nesCRCWidMask(u32);
+static u32 nes_crc_table_gen(u32 *, u32, u32, u32);
+static u32 reflect(u32, u32);
+static u32 byte_swap(u32, u32);
+
+u32 mh_detected;
+u32 mh_pauses_sent;
+
+/**
+ * nes_read_eeprom_values -
+ */
+int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
+{
+ u32 mac_addr_low;
+ u16 mac_addr_high;
+ u16 eeprom_data;
+ u16 eeprom_offset;
+ u16 next_section_address;
+ u32 index;
+
+ /* TODO: deal with EEPROM endian issues */
+ if (nesadapter->firmware_eeprom_offset == 0) {
+ /* Read the EEPROM Parameters */
+ eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
+ nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
+ eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
+ ((eeprom_data & 0x0080) >> 7));
+ nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
+ nesadapter->firmware_eeprom_offset = eeprom_offset;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
+ if (eeprom_data != 0x5746) {
+ nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
+ return -1;
+ }
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
+ nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
+ nesadapter->software_eeprom_offset = eeprom_offset;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
+ if (eeprom_data != 0x5753) {
+ printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
+ return -1;
+ }
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
+ ((eeprom_data & 0x0100) >> 8));
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x414d) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_offset = next_section_address;
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
+ ((eeprom_data & 0x0100) >> 8));
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x4f52) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_offset = next_section_address;
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x5746) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_offset = next_section_address;
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x5753) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_offset = next_section_address;
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x414d) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_offset = next_section_address;
+
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
+ nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
+ eeprom_offset + 2, eeprom_data);
+ next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
+ if (eeprom_data != 0x464e) {
+ nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
+ eeprom_data);
+ goto no_fw_rev;
+ }
+ eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
+ printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
+
+ nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
+ (u32)((u8)eeprom_data);
+
+no_fw_rev:
+ /* eeprom is valid */
+ eeprom_offset = nesadapter->software_eeprom_offset;
+ eeprom_offset += 8;
+ nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ mac_addr_low <<= 16;
+ mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
+ mac_addr_high, mac_addr_low);
+ nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
+
+ nesadapter->mac_addr_low = mac_addr_low;
+ nesadapter->mac_addr_high = mac_addr_high;
+
+ /* Read the Phy Type array */
+ eeprom_offset += 10;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "PhyType: 0x%04x\n", eeprom_data);
+
+ /* Read the port array */
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ /* port_count is set by soft reset reg */
+ for (index = 0; index < 4; index++) {
+ nesadapter->ports[index] = eeprom_data & 0x000f;
+ eeprom_data >>= 4;
+ }
+ nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u, port 2 -> %u, port 3 -> %u\n",
+ nesadapter->port_count,
+ nesadapter->ports[0], nesadapter->ports[1],
+ nesadapter->ports[2], nesadapter->ports[3]);
+
+ eeprom_offset += 46;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
+ nesadapter->tcp_timer_core_clk_divisor);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->cm_config = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
+
+ eeprom_offset += 2;
+ eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ eeprom_offset += 2;
+ nesadapter->core_clock = (((u32)eeprom_data) << 16) +
+ nes_read16_eeprom(nesdev->regs, eeprom_offset);
+ nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
+ }
+
+ nesadapter->phy_index[0] = 4;
+ nesadapter->phy_index[1] = 5;
+ nesadapter->phy_index[2] = 6;
+ nesadapter->phy_index[3] = 7;
+
+ /* TODO: get this from EEPROM */
+ nesdev->base_doorbell_index = 1;
+
+ return 0;
+}
+
+
+/**
+ * nes_read16_eeprom
+ */
+static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
+{
+ writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
+ (void __iomem *)addr + NES_EEPROM_COMMAND);
+
+ do {
+ } while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
+ NES_EEPROM_READ_REQUEST);
+
+ return(readw((void __iomem *)addr + NES_EEPROM_DATA));
+}
+
+
+/**
+ * nes_write_1G_phy_reg
+ */
+void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
+{
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ u32 u32temp;
+ u32 counter;
+ unsigned long flags;
+
+ spin_lock_irqsave(&nesadapter->phy_lock, flags);
+
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1))
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+
+ spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
+}
+
+
+/**
+ * nes_read_1G_phy_reg
+ * This routine only issues the read, the data must be read
+ * separately.
+ */
+void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
+{
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ u32 u32temp;
+ u32 counter;
+ unsigned long flags;
+
+ /* nes_debug(NES_DBG_PHY, "%s: phy addr = %d, mac_index = %d\n",
+ __FUNCTION__, phy_addr, nesdev->mac_index); */
+ spin_lock_irqsave(&nesadapter->phy_lock, flags);
+
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ /* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1)) {
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+ *data = 0xffff;
+ } else {
+ *data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
+ }
+ spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
+}
+
+
+/**
+ * nes_write_10G_phy_reg
+ */
+void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_reg,
+ u8 phy_addr, u16 data)
+{
+ u32 dev_addr;
+ u32 port_addr;
+ u32 u32temp;
+ u32 counter;
+
+ dev_addr = 5;
+ port_addr = 0;
+
+ /* set address */
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x00020000 | phy_reg | (dev_addr << 18) | (port_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1))
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+
+ /* set data */
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x10020000 | data | (dev_addr << 18) | (port_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1))
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+}
+
+
+/**
+ * nes_read_10G_phy_reg
+ * This routine only issues the read, the data must be read
+ * separately.
+ */
+void nes_read_10G_phy_reg(struct nes_device *nesdev, u16 phy_reg, u8 phy_addr)
+{
+ u32 dev_addr;
+ u32 port_addr;
+ u32 u32temp;
+ u32 counter;
+
+ dev_addr = 5;
+ port_addr = 0;
+
+ /* set address */
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x00020000 | phy_reg | (dev_addr << 18) | (port_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1))
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+
+ /* issue read */
+ nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
+ 0x30020000 | (dev_addr << 18) | (port_addr << 23));
+ for (counter = 0; counter < 100 ; counter++) {
+ udelay(30);
+ u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
+ if (u32temp & 1) {
+ nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
+ break;
+ }
+ }
+ if (!(u32temp & 1))
+ nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
+ u32temp);
+}
+
+
+/**
+ * nes_arp_table
+ */
+int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
+{
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ int arp_index;
+ int err = 0;
+
+ for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
+ if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
+ break;
+ }
+
+ if (action == NES_ARP_ADD) {
+ if (arp_index != nesadapter->arp_table_size) {
+ return -1;
+ }
+
+ arp_index = 0;
+ err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
+ nesadapter->arp_table_size, &arp_index, &nesadapter->next_arp_index);
+ if (err) {
+ nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
+ return err;
+ }
+ nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
+
+ nesadapter->arp_table[arp_index].ip_addr = ip_addr;
+ memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
+ return arp_index;
+ }
+
+ /* DELETE or RESOLVE */
+ if (arp_index == nesadapter->arp_table_size) {
+ nes_debug(NES_DBG_NETDEV, "mac address not in ARP table - cannot delete or resolve\n");
+ return -1;
+ }
+
+ if (action == NES_ARP_RESOLVE) {
+ nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
+ return arp_index;
+ }
+
+ if (action == NES_ARP_DELETE) {
+ nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
+ nesadapter->arp_table[arp_index].ip_addr = 0;
+ memset(nesadapter->arp_table[arp_index].mac_addr, 0x00, ETH_ALEN);
+ nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
+ return arp_index;
+ }
+
+ return -1;
+}
+
+
+/**
+ * nes_mh_fix
+ */
+void nes_mh_fix(unsigned long parm)
+{
+ unsigned long flags;
+ struct nes_device *nesdev = (struct nes_device *)parm;
+ struct nes_adapter *nesadapter = nesdev->nesadapter;
+ struct nes_vnic *nesvnic;
+ u32 used_chunks_tx;
+ u32 temp_used_chunks_tx;
+ u32 temp_last_used_chunks_tx;
+ u32 used_chunks_mask;
+ u32 mac_tx_frames_low;
+ u32 mac_tx_frames_high;
+ u32 mac_tx_pauses;
+ u32 serdes_status;
+ u32 reset_value;
+ u32 tx_control;
+ u32 tx_config;
+ u32 tx_pause_quanta;
+ u32 rx_control;
+ u32 rx_config;
+ u32 mac_exact_match;
+ u32 mpp_debug;
+ u32 i=0;
+ u32 chunks_tx_progress = 0;
+
+ spin_lock_irqsave(&nesadapter->phy_lock, flags);
+ if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
+ spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
+ goto no_mh_work;
+ }
+ nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
+ spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
+ do {
+ mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
+ mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
+ mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
+ used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
+ nesdev->mac_pause_frames_sent += mac_tx_pauses;
+ used_chunks_mask = 0;
+ temp_used_chunks_tx = used_chunks_tx;
+ temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
+
+ if (nesdev->netdev[0]) {
+ nesvnic = netdev_priv(nesdev->netdev[0]);
+ } else {
+ break;
+ }
+
+ for (i=0; i<4; i++) {
+ used_chunks_mask <<= 8;
+ if (nesvnic->qp_nic_index[i] != 0xff) {
+ used_chunks_mask |= 0xff;
+ if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
+ chunks_tx_progress = 1;
+ }
+ }
+ temp_used_chunks_tx >>= 8;
+ temp_last_used_chunks_tx >>= 8;
+ }
+ if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
+ (!(used_chunks_tx&used_chunks_mask)) ||
+ (!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
+ (chunks_tx_progress) ) {
+ nesdev->last_used_chunks_tx = used_chunks_tx;
+ break;
+ }
+ nesdev->last_used_chunks_tx = used_chunks_tx;
+ barrier();
+
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
+ mh_pauses_sent++;
+ mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
+ if (mac_tx_pauses) {
+ nesdev->mac_pause_frames_sent += mac_tx_pauses;
+ break;
+ }
+
+ tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
+ tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
+ tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
+ rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
+ rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
+ mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
+ mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
+
+ /* one last ditch effort to avoid a false positive */
+ mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
+ if (mac_tx_pauses) {
+ nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
+ nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
+ break;
+ }
+ mh_detected++;
+
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
+ reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
+
+ nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
+
+ while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
+ & 0x00000040) != 0x00000040) && (i++ < 5000)) {
+ /* mdelay(1); */
+ }
+
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
+ serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
+
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
+ if (nesadapter->OneG_Mode) {
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
+ } else {
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
+ }
+ serdes_status = nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
+ nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
+
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
+ nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
+ nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
+ nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
+ nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
+ nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
+
+ } while (0);
+
+ nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
+no_mh_work:
+ nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
+ add_timer(&nesdev->nesadapter->mh_timer);
+}
+
+
+/*
+"Everything you wanted to know about CRC algorithms, but were afraid to ask
+ for fear that errors in your understanding might be detected." Version : 3.
+Date : 19 August 1993.
+Author : Ross N. Williams.
+Net : ross@guest.adelaide.edu.au.
+FTP : ftp.adelaide.edu.au/pub/rocksoft/crc_v3.txt
+Company : Rocksoft™ Pty Ltd.
+Snail : 16 Lerwick Avenue, Hazelwood Park 5066, Australia.
+Fax : +61 8 373-4911 (c/- Internode Systems Pty Ltd).
+Phone : +61 8 379-9217 (10am to 10pm Adelaide Australia time).
+Note : "Rocksoft" is a trademark of Rocksoft Pty Ltd, Australia.
+Status : Copyright (C) Ross Williams, 1993. However, permission is granted to
+ make and distribute verbatim copies of this document provided that this information
+ block and copyright notice is included. Also, the C code modules included in this
+ document are fully public domain.
+
+Thanks : Thanks to Jean-loup Gailly (jloup@chorus.fr) and Mark Adler
+ (me@quest.jpl.nasa.gov) who both proof read this document and picked
+ out lots of nits as well as some big fat bugs.
+
+The current web page for this seems to be http://www.ross.net/crc/crcpaper.html.
+
+*/
+
+/****************************************************************************/
+/* Generate width mask */
+/****************************************************************************/
+/* */
+/* Returns a longword whose value is (2^p_cm->cm_width)-1. */
+/* The trick is to do this portably (e.g. without doing <<32). */
+/* */
+/* Author: Tristan Gross */
+/* Source: "A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS" */
+/* Ross N. Williams */
+/* http://www.rocksoft.com */
+/* */
+/****************************************************************************/
+
+static u32 nesCRCWidMask (u32 width)
+{
+ return(((1L<<(((u32)width)-1))-1L)<<1)|1L;
+}
+
+
+/****************************************************************************/
+/* Generate CRC table */
+/****************************************************************************/
+/* */
+/* Source: "A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS" */
+/* Ross N. Williams */
+/* http://www.rocksoft.com */
+/* */
+/****************************************************************************/
+static u32 nes_crc_table_gen ( u32 *pCRCTable,
+ u32 poly,
+ u32 order,
+ u32 reflectIn)
+{
+ u32 i;
+ u32 reg;
+ u32 byte;
+ u32 topbit = BITMASK(NES_CRC_WID-1);
+ u32 tmp;
+
+ for (byte=0;byte<256;byte++) {
+
+ // If we need to creat a reflected table we must reflect the index (byte) and
+ // reflect the final reg
+ tmp = (reflectIn) ? reflect(byte,8): byte;
+
+ reg = tmp << (NES_CRC_WID-8);
+
+ for (i=0; i<8; i++) {
+ if (reg & topbit) {
+ reg = (reg << 1) ^ poly;
+ } else {
+ reg <<= 1;
+ }
+ }
+
+ reg = (reflectIn) ? reflect(reg,order): reg;
+ pCRCTable[byte] = reg & nesCRCWidMask(NES_CRC_WID);
+ }
+
+ return 0;
+}
+
+
+/****************************************************************************/
+/* Perform 32 bit based CRC calculation */
+/****************************************************************************/
+/* */
+/* Source: "A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS" */
+/* Ross N. Williams */
+/* http://www.rocksoft.com */
+/* */
+/* This performs a standard 32 bit crc on an array of arbitrary length */
+/* with an arbitrary initial value and passed generator polynomial */
+/* in the form of a crc table. */
+/* */
+/****************************************************************************/
+static u32 reflect (u32 data, u32 num)
+{
+ /* Reflects the lower num bits in 'data' around their center point. */
+ u32 i;
+ u32 j = 1;
+ u32 result = 0;
+
+ for (i=(u32)1<<(num-1); i; i>>=1) {
+ if (data & i) result|=j;
+ j <<= 1;
+ }
+ return result;
+}
+
+
+/**
+ * byte_swap
+ */
+static u32 byte_swap (u32 data, u32 num)
+{
+ u32 i;
+ u32 result = 0;
+
+ if (num%16) {
+ dprintk("\nbyte_swap: ERROR: num is not an even number of bytes\n");
+ /* ASSERT(0); */
+ }
+
+ for (i = 0; i < num; i += 8) {
+ result |= (0xFF & (data >> i)) << (num-8-i);
+ }
+
+ return result;
+}
+
+
+/**
+ * nes_crc32 -
+ * This is a reflected table algorithm. ReflectIn basically
+ * means to reflect each incomming byte of the data. But to make
+ * things more complicated, we can instead reflect the initial
+ * value, the final crc, and shift data to the right using a
+ * reflected pCRCTable. CRC is FUN!!
+ */
+u32 nes_crc32 ( u32 reverse,
+ u32 initialValue,
+ u32 finalXOR,
+ u32 messageLength,
+ u8 *pMessage,
+ u32 order,
+ u32 reflectIn,
+ u32 reflectOut)
+
+{
+ u8 *pBlockAddr = pMessage;
+ u32 mlen = messageLength;
+ u32 crc;
+
+ if (0 == nesCRCInitialized) {
+ nes_crc_table_gen( &nesCRCTable[0], CRC32C_POLY, ORDER, REFIN);
+ nesCRCInitialized = 1;
+ }
+
+ crc = (reflectIn) ? reflect(initialValue,order): initialValue;
+
+ while (mlen--) {
+ /* printf("byte = %x, index = %u, crctable[index] = %x\n",
+ *pBlockAddr, (crc & 0xffL) ^ *pBlockAddr,
+ nesCRCTable[(crc & 0xffL) ^ *pBlockAddr]);
+ */
+ if (reflectIn) {
+ crc = nesCRCTable[(crc & 0xffL ) ^ *pBlockAddr++] ^ (crc >> 8);
+ } else {
+ crc = nesCRCTable[((crc>>24) ^ *pBlockAddr++) & 0xFFL] ^ (crc << 8);
+ }
+ }
+
+ /* if reflectOut and reflectIn are both set, we don't */
+ /* do anything since reflecting twice effectively does nothing. */
+ crc = ((reflectIn)^(reflectOut)) ? reflect(crc,order): crc;
+
+ crc = crc^finalXOR;
+
+ /* We don't really use this, but it is here for completeness */
+ crc = (reverse) ? byte_swap(crc,32): crc;
+
+ return crc;
+}
+
^ permalink raw reply
* [ofa-general] [PATCH 14/14 v2] nes: kernel build infrastructure
From: ggrundstrom @ 2007-10-19 20:28 UTC (permalink / raw)
To: ewg, rdreier; +Cc: netdev, general
Makefile kernel build file.
Signed-off-by: Glenn Grundstrom <ggrundstrom@neteffect.com>
---
--- NULL 1969-12-31 18:00:00.000000000 -0600
+++ ofa_kernel-1.3/drivers/infiniband/hw/nes/Makefile 2007-10-19 09:43:32.000000000 -0500
@@ -0,0 +1,7 @@
+
+EXTRA_CFLAGS += -DNES_MINICM
+
+obj-$(CONFIG_INFINIBAND_NES) += iw_nes.o
+
+iw_nes-objs := nes.o nes_hw.o nes_nic.o nes_utils.o nes_verbs.o nes_cm.o
+
^ permalink raw reply
* Re: multicast: bug or "feature"
From: Brian Haley @ 2007-10-19 20:39 UTC (permalink / raw)
To: David Stevens; +Cc: Vlad Yasevich, Herbert Xu, netdev, netdev-owner
In-Reply-To: <OFC9CC5B3C.F6B38A10-ON88257379.006F6FDE-88257379.006FE742@us.ibm.com>
Hi David,
David Stevens wrote:
> From looking at the code, it appears that validate
> source is failing just because of the rp_filter. Do you have
> rp_filter set to nonzero?
> If so, it may do what you want just by setting that
> to 0:
>
> sysctl -w net.ipv4.conf.all.rp_filter=0
rp_filter is set to zero, it's the "if (res.type != RTN_UNICAST)" check
in fib_validate_source() that's doing it. If I add a new
"accept_local_addr" sysctl to ipv4_devconf to allow RTN_LOCAL here,
everything works just fine. I just don't know how palatable that would
be to upstream...
-Brian
^ permalink raw reply
* Re: multicast: bug or "feature"
From: David Stevens @ 2007-10-19 21:25 UTC (permalink / raw)
To: Brian Haley; +Cc: Herbert Xu, netdev, netdev-owner, Vlad Yasevich
In-Reply-To: <471915FC.1000604@hp.com>
I don't know about a new knob, but it's the same notion
as rp_filter, so why not use rpf for RTN_LOCAL types?
Ie, allow RTN_LOCAL and RTN_UNICAST at the top, but
check rpf if the devs aren't equal or RTN_LOCAL....
It seems like not a good thing to rely on in the first place, though;
usually receiving things from yourself is a bad thing. :-)
+-DLS
^ permalink raw reply
* [PATCH 0/7] tg3: PCI error recovery and more
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patchset adds PCI error recovery, 5723 support and a few other odds
and ends.
^ permalink raw reply
* [PATCH 1/7] tg3: Add 5723 support
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patch adds support for upcoming 5723 devices.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 014dc2c..253d761 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -200,6 +200,7 @@ static struct pci_device_id tg3_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index df948b4..4e10a07 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1943,6 +1943,7 @@
#define PCI_DEVICE_ID_TIGON3_5720 0x1658
#define PCI_DEVICE_ID_TIGON3_5721 0x1659
#define PCI_DEVICE_ID_TIGON3_5722 0x165a
+#define PCI_DEVICE_ID_TIGON3_5723 0x165b
#define PCI_DEVICE_ID_TIGON3_5705M 0x165d
#define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
#define PCI_DEVICE_ID_TIGON3_5714 0x1668
^ permalink raw reply related
* [PATCH 2/7] tg3: MII => TP
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patch changes the PHY type reported through ethtool for copper
devices from MII to TP. The latter is more accurate.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 253d761..66682b8 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -8274,7 +8274,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
SUPPORTED_100baseT_Full |
SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
- SUPPORTED_MII);
+ SUPPORTED_TP);
cmd->port = PORT_TP;
} else {
cmd->supported |= SUPPORTED_FIBRE;
^ permalink raw reply related
* [PATCH 4/7] tg3: PCI command adjustment
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patch changes the way the driver works with the PCI command
register. It adjusts the access size from dwords to words. This patch
is done both as a PCI configuration space cleanup and as preparatory
work for PCI error recovery.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 68472ce..9920751 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5029,10 +5029,7 @@ static int tg3_poll_fw(struct tg3 *tp)
/* Save PCI command register before chip reset */
static void tg3_save_pci_state(struct tg3 *tp)
{
- u32 val;
-
- pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
- tp->pci_cmd = val;
+ pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
}
/* Restore PCI state after chip reset */
@@ -5055,7 +5052,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
PCISTATE_ALLOW_APE_SHMEM_WR;
pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
- pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
+ pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 495a1df..1d5b2a3 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2421,7 +2421,7 @@ struct tg3 {
#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
u32 led_ctrl;
- u32 pci_cmd;
+ u16 pci_cmd;
char board_part_number[24];
#define TG3_VER_SIZE 32
^ permalink raw reply related
* [PATCH 3/7] tg3: Add management FW version to ethtool report
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patch appends the management firmware version to the bootcode
firmware string reported through ethtool.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 66682b8..68472ce 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -10821,9 +10821,24 @@ out_not_found:
strcpy(tp->board_part_number, "none");
}
+static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
+{
+ u32 val;
+
+ if (tg3_nvram_read_swab(tp, offset, &val) ||
+ (val & 0xfc000000) != 0x0c000000 ||
+ tg3_nvram_read_swab(tp, offset + 4, &val) ||
+ val != 0)
+ return 0;
+
+ return 1;
+}
+
static void __devinit tg3_read_fw_ver(struct tg3 *tp)
{
u32 val, offset, start;
+ u32 ver_offset;
+ int i, bcnt;
if (tg3_nvram_read_swab(tp, 0, &val))
return;
@@ -10836,29 +10851,71 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
return;
offset = tg3_nvram_logical_addr(tp, offset);
- if (tg3_nvram_read_swab(tp, offset, &val))
+
+ if (!tg3_fw_img_is_valid(tp, offset) ||
+ tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
return;
- if ((val & 0xfc000000) == 0x0c000000) {
- u32 ver_offset, addr;
- int i;
+ offset = offset + ver_offset - start;
+ for (i = 0; i < 16; i += 4) {
+ if (tg3_nvram_read(tp, offset + i, &val))
+ return;
+
+ val = le32_to_cpu(val);
+ memcpy(tp->fw_ver + i, &val, 4);
+ }
- if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
- tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
+ if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
+ (tp->tg3_flags & TG3_FLG3_ENABLE_APE))
+ return;
+
+ for (offset = TG3_NVM_DIR_START;
+ offset < TG3_NVM_DIR_END;
+ offset += TG3_NVM_DIRENT_SIZE) {
+ if (tg3_nvram_read_swab(tp, offset, &val))
return;
- if (val != 0)
+ if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
+ break;
+ }
+
+ if (offset == TG3_NVM_DIR_END)
+ return;
+
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+ start = 0x08000000;
+ else if (tg3_nvram_read_swab(tp, offset - 4, &start))
+ return;
+
+ if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
+ !tg3_fw_img_is_valid(tp, offset) ||
+ tg3_nvram_read_swab(tp, offset + 8, &val))
+ return;
+
+ offset += val - start;
+
+ bcnt = strlen(tp->fw_ver);
+
+ tp->fw_ver[bcnt++] = ',';
+ tp->fw_ver[bcnt++] = ' ';
+
+ for (i = 0; i < 4; i++) {
+ if (tg3_nvram_read(tp, offset, &val))
return;
- addr = offset + ver_offset - start;
- for (i = 0; i < 16; i += 4) {
- if (tg3_nvram_read(tp, addr + i, &val))
- return;
+ val = le32_to_cpu(val);
+ offset += sizeof(val);
- val = cpu_to_le32(val);
- memcpy(tp->fw_ver + i, &val, 4);
+ if (bcnt > TG3_VER_SIZE - sizeof(val)) {
+ memcpy(&tp->fw_ver[bcnt], &val, TG3_VER_SIZE - bcnt);
+ break;
}
+
+ memcpy(&tp->fw_ver[bcnt], &val, sizeof(val));
+ bcnt += sizeof(val);
}
+
+ tp->fw_ver[TG3_VER_SIZE - 1] = 0;
}
static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 6dbdad2..495a1df 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1540,6 +1540,12 @@
#define TG3_EEPROM_MAGIC_HW 0xabcd
#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
+#define TG3_NVM_DIR_START 0x18
+#define TG3_NVM_DIR_END 0x78
+#define TG3_NVM_DIRENT_SIZE 0xc
+#define TG3_NVM_DIRTYPE_SHIFT 24
+#define TG3_NVM_DIRTYPE_ASFINI 1
+
/* 32K Window into NIC internal memory */
#define NIC_SRAM_WIN_BASE 0x00008000
@@ -2418,7 +2424,8 @@ struct tg3 {
u32 pci_cmd;
char board_part_number[24];
- char fw_ver[16];
+#define TG3_VER_SIZE 32
+ char fw_ver[TG3_VER_SIZE];
u32 nic_sram_data_cfg;
u32 pci_clock_ctrl;
struct pci_dev *pdev_peer;
^ permalink raw reply related
* [PATCH 7/7] tg3: Update version to 3.85
From: Matt Carlson @ 2007-10-19 21:37 UTC (permalink / raw)
To: davem; +Cc: netdev, andy, Michael Chan
This patch updates the version number to 3.85.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d866387..e5cf97a 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -64,8 +64,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.84"
-#define DRV_MODULE_RELDATE "October 12, 2007"
+#define DRV_MODULE_VERSION "3.85"
+#define DRV_MODULE_RELDATE "October 18, 2007"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
^ permalink raw reply related
* [PATCH 6/7] tg3: Add PCI error recovery
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, linux-pci, Linas Vepstas, Michael Chan
This patch adds PCI error recovery support.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 9920751..d866387 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5026,12 +5026,6 @@ static int tg3_poll_fw(struct tg3 *tp)
return 0;
}
-/* Save PCI command register before chip reset */
-static void tg3_save_pci_state(struct tg3 *tp)
-{
- pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
-}
-
/* Restore PCI state after chip reset */
static void tg3_restore_pci_state(struct tg3 *tp)
{
@@ -5107,12 +5101,6 @@ static int tg3_chip_reset(struct tg3 *tp)
*/
tp->nvram_lock_cnt = 0;
- /* GRC_MISC_CFG core clock reset will clear the memory
- * enable bit in PCI register 4 and the MSI enable bit
- * on some chips, so we save relevant registers here.
- */
- tg3_save_pci_state(tp);
-
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
@@ -12527,6 +12515,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
tg3_ape_lock_init(tp);
}
+ pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
+
pci_set_drvdata(pdev, dev);
err = register_netdev(dev);
@@ -12706,11 +12696,148 @@ out:
return err;
}
+/**
+ * tg3_io_error_detected - called when PCI error is detected
+ * @pdev: Pointer to PCI device
+ * @state: The current pci connection state
+ *
+ * This function is called after a PCI bus error affecting
+ * this device has been detected.
+ */
+static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
+ pci_channel_state_t state)
+{
+ int rc;
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct tg3 *tp = netdev_priv(netdev);
+ struct device *dev = &netdev->dev;
+
+ rtnl_lock();
+
+ dev_info(dev, "PCI I/O error detected on %s\n", netdev->name);
+
+ if (!netif_running(netdev)) {
+ rc = PCI_ERS_RESULT_NEED_RESET;
+ goto done;
+ }
+
+ /* Want to make sure that the reset task doesn't run */
+ cancel_work_sync(&tp->reset_task);
+ tg3_netif_stop(tp);
+ del_timer_sync(&tp->timer);
+ netif_device_detach(netdev);
+ pci_disable_device(pdev);
+
+ if (state == pci_channel_io_perm_failure) {
+ /* avoid hang in dev_close() with rtnl_lock held */
+ napi_enable(&tp->napi);
+ rc = PCI_ERS_RESULT_DISCONNECT;
+ goto done;
+ }
+
+ rc = PCI_ERS_RESULT_NEED_RESET;
+
+done:
+ rtnl_unlock();
+
+ return rc;
+}
+
+/**
+ * tg3_io_slot_reset - called after the pci bus has been reset.
+ * @pdev: Pointer to PCI device
+ *
+ * Restart the card from scratch, as if from a cold-boot.
+ * At this point, the card has exprienced a hard reset,
+ * followed by fixups by BIOS, and has its config space
+ * set up identically to what it was at cold boot.
+ */
+static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
+{
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct tg3 *tp = netdev_priv(netdev);
+ int rc;
+
+ rtnl_lock();
+
+ pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
+
+ if (!netif_running(netdev)) {
+ rc = PCI_ERS_RESULT_RECOVERED;
+ goto done;
+ }
+
+ if (pci_enable_device(pdev)) {
+ printk(KERN_ERR "tg3: %s: "
+ "Cannot re-enable PCI device after reset.\n",
+ netdev->name);
+ rc = PCI_ERS_RESULT_DISCONNECT;
+ goto done;
+ }
+
+ pci_set_master(pdev);
+ pci_restore_msi_state(tp->pdev);
+ netif_device_attach(netdev);
+
+ tg3_full_lock(tp, 0);
+ tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
+ rc = tg3_restart_hw(tp, 1);
+ tg3_full_unlock(tp);
+ if (rc) {
+ printk(KERN_ERR "tg3: %s: "
+ "Cannot restart hardware after reset.\n", netdev->name);
+ rc = PCI_ERS_RESULT_DISCONNECT;
+ goto done;
+ }
+
+ rc = PCI_ERS_RESULT_RECOVERED;
+
+done:
+ rtnl_unlock();
+
+ return rc;
+}
+
+/**
+ * tg3_io_resume - called when traffic can start flowing again.
+ * @pdev: Pointer to PCI device
+ *
+ * This callback is called when the error recovery driver tells
+ * us that its OK to resume normal operation.
+ */
+static void tg3_io_resume(struct pci_dev *pdev)
+{
+ struct net_device *netdev = pci_get_drvdata(pdev);
+ struct tg3 *tp = netdev_priv(netdev);
+
+ rtnl_lock();
+
+ if (!netif_running(netdev))
+ goto done;
+
+ netif_wake_queue(netdev);
+
+ tp->timer.expires = jiffies + tp->timer_offset;
+ add_timer(&tp->timer);
+
+ tg3_netif_start(tp);
+
+done:
+ rtnl_unlock();
+}
+
+static struct pci_error_handlers tg3_err_handler = {
+ .error_detected = tg3_io_error_detected,
+ .slot_reset = tg3_io_slot_reset,
+ .resume = tg3_io_resume
+};
+
static struct pci_driver tg3_driver = {
.name = DRV_MODULE_NAME,
.id_table = tg3_pci_tbl,
.probe = tg3_init_one,
.remove = __devexit_p(tg3_remove_one),
+ .err_handler = &tg3_err_handler,
.suspend = tg3_suspend,
.resume = tg3_resume
};
^ permalink raw reply related
* [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Matt Carlson @ 2007-10-19 21:36 UTC (permalink / raw)
To: davem; +Cc: netdev, linux-pci, Linas Vepstas, Michael Chan
This patch exports the pci_restore_msi_state() function. This function
is needed to restore the MSI state during PCI error recovery.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 87e0161..f57762d 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -224,7 +224,6 @@ static struct msi_desc* alloc_msi_entry(void)
return entry;
}
-#ifdef CONFIG_PM
static void __pci_restore_msi_state(struct pci_dev *dev)
{
int pos;
@@ -282,7 +281,7 @@ void pci_restore_msi_state(struct pci_dev *dev)
__pci_restore_msi_state(dev);
__pci_restore_msix_state(dev);
}
-#endif /* CONFIG_PM */
+EXPORT_SYMBOL_GPL(pci_restore_msi_state);
/**
* msi_capability_init - configure device's MSI capability structure
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 6fda33d..23c6c17 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -45,12 +45,6 @@ static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif
-#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM)
-void pci_restore_msi_state(struct pci_dev *dev);
-#else
-static inline void pci_restore_msi_state(struct pci_dev *dev) {}
-#endif
-
#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
#else
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 768b933..5575227 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -662,6 +662,7 @@ static inline int pci_enable_msix(struct pci_dev* dev,
struct msix_entry *entries, int nvec) {return -1;}
static inline void pci_disable_msix(struct pci_dev *dev) {}
static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {}
+static inline void pci_restore_msi_state(struct pci_dev *dev) {}
#else
extern int pci_enable_msi(struct pci_dev *dev);
extern void pci_disable_msi(struct pci_dev *dev);
@@ -669,6 +670,7 @@ extern int pci_enable_msix(struct pci_dev* dev,
struct msix_entry *entries, int nvec);
extern void pci_disable_msix(struct pci_dev *dev);
extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
+void pci_restore_msi_state(struct pci_dev *dev);
#endif
#ifdef CONFIG_HT_IRQ
^ permalink raw reply related
* Re: [PATCH] PHYLIB: IRQ event workqueue handling fixes
From: Benjamin Herrenschmidt @ 2007-10-19 21:46 UTC (permalink / raw)
To: Jarek Poplawski
Cc: Maciej W. Rozycki, Andy Fleming, Andrew Morton, Jeff Garzik,
netdev, linux-kernel
In-Reply-To: <20071019143921.GB2598@ff.dom.local>
> Actually I'm not convinced with this explanation. It seems to me that
> since there are such serious locking problems (especially with rntl),
> there could be once more considered a private workqueue. You've
> written earlier about being a lonely user of this code. But, since
> Benjamin offered his help with changing to mutexes, which looks like
> very reasonable idea to me (probably I miss most of the points...),
> maybe it's very good opportunity to both: make this code better and
> double the user base! I'm interested in looking for such solution
> if Benjamin thinks there could be too few problems for him... So,
> let somebody tell us what could be wrong with this idea?
My main problem is time :-) But I need to do the change to mutex if I am
to use phylib for emac. I can't tell when I'll have time to do it tho.
Ben.
^ permalink raw reply
* [patch 1/1] qeth: remove header_ops bug
From: Ursula Braun @ 2007-10-19 22:03 UTC (permalink / raw)
To: jgarzik, netdev, linux-s390; +Cc: mschwid2, apw, linux-kernel, kamalesh, kaber
In-Reply-To: <20071019215538.395133000@linux.vnet.ibm.com>
[-- Attachment #1: qeth.patch --]
[-- Type: text/plain, Size: 859 bytes --]
From: Ursula Braun <braunu@de.ibm.com>
Remove qeth bug caused by commit:
[NET]: Move hardware header operations out of netdevice.
Signed-off-by: Ursula Braun <braunu@de.ibm.com>
---
drivers/s390/net/qeth_main.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Index: linux-2.6-uschi/drivers/s390/net/qeth_main.c
===================================================================
--- linux-2.6-uschi.orig/drivers/s390/net/qeth_main.c
+++ linux-2.6-uschi/drivers/s390/net/qeth_main.c
@@ -6643,7 +6643,8 @@ qeth_netdev_init(struct net_device *dev)
dev->vlan_rx_kill_vid = qeth_vlan_rx_kill_vid;
dev->vlan_rx_add_vid = qeth_vlan_rx_add_vid;
#endif
- dev->header_ops = &qeth_null_ops;
+ if (qeth_get_netdev_flags(card) & IFF_NOARP)
+ dev->header_ops = &qeth_null_ops;
#ifdef CONFIG_QETH_IPV6
/*IPv6 address autoconfiguration stuff*/
--
^ permalink raw reply
* [patch 0/1] remove header_ops bug in qeth driver
From: Ursula Braun @ 2007-10-19 21:55 UTC (permalink / raw)
To: jgarzik, netdev, linux-s390; +Cc: mschwid2, apw, linux-kernel, kamalesh, kaber
--
Remove qeth driver bug introduced by this commit:
commit 3b04ddde02cf1b6f14f2697da5c20eca5715017f
Author: Stephen Hemminger <shemminger@linux-foundation.org>
Date: Tue Oct 9 01:40:57 2007 -0700
[NET]: Move hardware header operations out of netdevice.
^ permalink raw reply
* [patch 1/1] qeth: remove header_ops bug
From: Ursula Braun @ 2007-10-19 22:02 UTC (permalink / raw)
To: jgarzik, netdev, linux-s390; +Cc: mschwid2, apw, linux-kernel, kamalesh, kaber
In-Reply-To: <20071019215538.395133000@linux.vnet.ibm.com>
[-- Attachment #1: qeth.patch --]
[-- Type: text/plain, Size: 859 bytes --]
From: Ursula Braun <braunu@de.ibm.com>
Remove qeth bug caused by commit:
[NET]: Move hardware header operations out of netdevice.
Signed-off-by: Ursula Braun <braunu@de.ibm.com>
---
drivers/s390/net/qeth_main.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Index: linux-2.6-uschi/drivers/s390/net/qeth_main.c
===================================================================
--- linux-2.6-uschi.orig/drivers/s390/net/qeth_main.c
+++ linux-2.6-uschi/drivers/s390/net/qeth_main.c
@@ -6643,7 +6643,8 @@ qeth_netdev_init(struct net_device *dev)
dev->vlan_rx_kill_vid = qeth_vlan_rx_kill_vid;
dev->vlan_rx_add_vid = qeth_vlan_rx_add_vid;
#endif
- dev->header_ops = &qeth_null_ops;
+ if (qeth_get_netdev_flags(card) & IFF_NOARP)
+ dev->header_ops = &qeth_null_ops;
#ifdef CONFIG_QETH_IPV6
/*IPv6 address autoconfiguration stuff*/
--
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Linas Vepstas @ 2007-10-19 23:29 UTC (permalink / raw)
To: Matt Carlson; +Cc: davem, netdev, linux-pci, Michael Chan
In-Reply-To: <1192829817.22064.559.camel@teletran1>
On Fri, Oct 19, 2007 at 02:36:56PM -0700, Matt Carlson wrote:
> This patch exports the pci_restore_msi_state() function. This function
> is needed to restore the MSI state during PCI error recovery.
>
> Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
> Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
> Signed-off-by: Michael Chan <mchan@broadcom.com>
Davem,
This patch is generically needed for recovery from PCI errors,
and not just the tg3 that Matt is working on.
Matt, there are also several msi-related bugs in the pseries
architecture implementation, those patches will go out to
Paul Mackerras seperately. I was hoping today ... but things
came up. One little iddy-biddy problem is that the pseries
is not actually *saving* the msi state, and so, ahem, the
restore isn't quite working out either. I'm still trying
to navigate around that.
--linas
^ permalink raw reply
* Re: [PATCH] netdev: Interfamily support for IPSEC BEET
From: David Miller @ 2007-10-19 23:33 UTC (permalink / raw)
To: joakim.koskela; +Cc: netdev, kaber
In-Reply-To: <200710191307.55589.joakim.koskela@hiit.fi>
Please fix up these whitespace errors in your patch, thank you:
+ git apply --check --whitespace=error-all diff
Space in indent is followed by a tab.
diff:329: if (x->sel.family == AF_INET) {
Space in indent is followed by a tab.
diff:330: x->props.header_len += IPV4_BEET_PHMAXLEN +
Space in indent is followed by a tab.
diff:331: (sizeof(struct ipv6hdr) - sizeof(struct iphdr));
Space in indent is followed by a tab.
diff:332: }
Space in indent is followed by a tab.
diff:347: (x->props.mode != XFRM_MODE_BEET ||
Space in indent is followed by a tab.
diff:348: x->sel.family != AF_INET6)) {
fatal: 6 lines add whitespace errors.
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Michael Chan @ 2007-10-20 0:36 UTC (permalink / raw)
To: linas; +Cc: Matt Carlson, David Miller, netdev, linux-pci
In-Reply-To: <20071019232926.GL29903@austin.ibm.com>
On Fri, 2007-10-19 at 18:29 -0500, linas@austin.ibm.com wrote:
> On Fri, Oct 19, 2007 at 02:36:56PM -0700, Matt Carlson wrote:
> > This patch exports the pci_restore_msi_state() function. This function
> > is needed to restore the MSI state during PCI error recovery.
> >
> > Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
> > Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
> > Signed-off-by: Michael Chan <mchan@broadcom.com>
>
> Davem,
>
> This patch is generically needed for recovery from PCI errors,
> and not just the tg3 that Matt is working on.
>
> Matt, there are also several msi-related bugs in the pseries
> architecture implementation, those patches will go out to
> Paul Mackerras seperately. I was hoping today ... but things
> came up. One little iddy-biddy problem is that the pseries
> is not actually *saving* the msi state, and so, ahem, the
> restore isn't quite working out either. I'm still trying
> to navigate around that.
>
Linas, the MSI state is saved automatically when the driver calls
pci_enable_msi(), so it doesn't need to be saved by pseries code.
^ permalink raw reply
* Re: [PATCH] [POWERPC] ucc_geth: Eliminate compile warnings
From: David Miller @ 2007-10-19 23:41 UTC (permalink / raw)
To: Emilian.Medve; +Cc: jgarzik, LeoLi, netdev, linuxppc-dev
In-Reply-To: <598D5675D34BE349929AF5EDE9B03E270168520B@az33exm24.fsl.freescale.net>
From: "Medve Emilian-EMMEDVE1" <Emilian.Medve@freescale.com>
Date: Fri, 19 Oct 2007 06:39:12 -0700
> For the current situation, 32-bit QE, 32-bit PowerPC, do you find
> the patch acceptable?
No piece of code in the kernel should live in a vacuum.
In order to improve overall code quality, every piece of
driver code should avoid assuming things about pointer
sizes and things of this nature.
Then the driver can get enabled into the build on every
platform, and therefore nobody will break the build of
this driver again since it will get hit by "allmodconfig"
et al. builds even on platforms other than the one it is
meant for.
This hack fix is not acceptable, really.
^ permalink raw reply
* linux kernel networking code review request
From: Templin, Fred L @ 2007-10-19 23:10 UTC (permalink / raw)
To: netdev; +Cc: Templin, Fred L
In-Reply-To: <1192829803.22064.556.camel@teletran1>
Hello,
I would like to get a review on some new Linux
kernel networking code. The code is based on the
2.6.23 source tree and touches three files - two
in ./net/ipv6 and one in ./include/net. What is
the proper procedure for requesting a review?
Thanks - Fred
fred.l.templin@boeing.com
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Linas Vepstas @ 2007-10-20 0:04 UTC (permalink / raw)
To: Michael Chan; +Cc: Matt Carlson, David Miller, netdev, linux-pci
In-Reply-To: <1192840577.5369.9.camel@dell>
On Fri, Oct 19, 2007 at 05:36:17PM -0700, Michael Chan wrote:
> On Fri, 2007-10-19 at 18:29 -0500, linas@austin.ibm.com wrote:
> > On Fri, Oct 19, 2007 at 02:36:56PM -0700, Matt Carlson wrote:
> > > This patch exports the pci_restore_msi_state() function. This function
> > > is needed to restore the MSI state during PCI error recovery.
> > >
> > > Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
> > > Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
> > > Signed-off-by: Michael Chan <mchan@broadcom.com>
> >
> > Davem,
> >
> > This patch is generically needed for recovery from PCI errors,
> > and not just the tg3 that Matt is working on.
> >
> > Matt, there are also several msi-related bugs in the pseries
> > architecture implementation, those patches will go out to
> > Paul Mackerras seperately. I was hoping today ... but things
> > came up. One little iddy-biddy problem is that the pseries
> > is not actually *saving* the msi state, and so, ahem, the
> > restore isn't quite working out either. I'm still trying
> > to navigate around that.
> >
> Linas, the MSI state is saved automatically when the driver calls
> pci_enable_msi(), so it doesn't need to be saved by pseries code.
I'm working in linux-2.6.23-rc8-mm1 at the moment, and I don't see
that happening. viz. read_msi_msg() is not called anywhere, and I need
to have valid msg->address_lo and msg->address_hi and msg->data
in order to be able to restore.
In particular, this has to happen after the call to arch_setup_msi_irqs
as otherwise, the arch hasn't yet filled these fields with correct values.
Perhaps this is fixed in the kernel you're working with?
--linas
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Michael Chan @ 2007-10-20 1:12 UTC (permalink / raw)
To: linas; +Cc: Matt Carlson, David Miller, netdev, linux-pci
In-Reply-To: <20071020000421.GO29903@austin.ibm.com>
On Fri, 2007-10-19 at 19:04 -0500, linas@austin.ibm.com wrote:
> I'm working in linux-2.6.23-rc8-mm1 at the moment, and I don't see
> that happening. viz. read_msi_msg() is not called anywhere, and I need
> to have valid msg->address_lo and msg->address_hi and msg->data
> in order to be able to restore.
>
> In particular, this has to happen after the call to
> arch_setup_msi_irqs
> as otherwise, the arch hasn't yet filled these fields with correct
> values.
>
> Perhaps this is fixed in the kernel you're working with?
It's possible that this doesn't work on pseries. I've only tested
pci_restore_msi_state() on x86 in the context of suspend and resume.
During resume, the MSI state gets restored correctly on x86.
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: Linas Vepstas @ 2007-10-20 0:25 UTC (permalink / raw)
To: Michael Chan; +Cc: Matt Carlson, David Miller, netdev, linux-pci
In-Reply-To: <1192842723.5369.23.camel@dell>
On Fri, Oct 19, 2007 at 06:12:03PM -0700, Michael Chan wrote:
> On Fri, 2007-10-19 at 19:04 -0500, linas@austin.ibm.com wrote:
> > I'm working in linux-2.6.23-rc8-mm1 at the moment, and I don't see
> > that happening. viz. read_msi_msg() is not called anywhere, and I need
> > to have valid msg->address_lo and msg->address_hi and msg->data
> > in order to be able to restore.
> >
> > In particular, this has to happen after the call to
> > arch_setup_msi_irqs
> > as otherwise, the arch hasn't yet filled these fields with correct
> > values.
> >
> > Perhaps this is fixed in the kernel you're working with?
>
> It's possible that this doesn't work on pseries. I've only tested
> pci_restore_msi_state() on x86 in the context of suspend and resume.
> During resume, the MSI state gets restored correctly on x86.
:-) Yes, I think that is being done in arch/i386/kernel/io_apic.c
and arch/ia64/kernel/msi_ia64.c and etc. but its not being done
on most of the powerpc's. Its possible that none of the
old macintosh laptops use msi, and so no one noticed before;
I know that no one ever suspends/resumes the big servers I work
on, sooo :-)
Actually, looking at arch/i386/kernel/io_apic.c, it looks like
the msi state is being saved only when CONFIG_SMP is set, so
it seems to me that the restore will fail on uni systems ...
are there any of those left?
--linas
^ permalink raw reply
* Re: [PATCH 5/7] pci: Export the pci_restore_msi_state() function
From: David Miller @ 2007-10-20 0:27 UTC (permalink / raw)
To: linas; +Cc: mchan, mcarlson, netdev, linux-pci
In-Reply-To: <20071020000421.GO29903@austin.ibm.com>
From: linas@austin.ibm.com (Linas Vepstas)
Date: Fri, 19 Oct 2007 19:04:21 -0500
> I'm working in linux-2.6.23-rc8-mm1 at the moment, and I don't see
> that happening. viz. read_msi_msg() is not called anywhere, and I need
> to have valid msg->address_lo and msg->address_hi and msg->data
> in order to be able to restore.
The generic PCI layer will save away the PCI config space elements
during pci_enable_msi(), including the MSI address and data values.
You can fetch the values you need from there during restore if
you need them.
See the pci_restore_msi_state() call done from pci_restore_state()
in drivers/pci/pci.c, that pci_restore_msi_state() code in
drivers/pci/msi.c very much relies upon the entry->msg values
being uptodate and valid.
The MSI arch layer code is supposed to fill the entry->msg values in
via arch_setup_msi_irq(). Perhaps the pseries code is forgetting to
do that.
So I can't really see what the problem is you're talking about.
^ permalink raw reply
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