* [Patch]net/xfrm/xfrm_policy.c: replace timer with delayed_work
From: WANG Cong @ 2008-02-16 15:55 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Herbert Xu, David Miller, Andrew Morton, netdev
As suggested by Herbert, using workqueue is better than timer
for net/xfrm/xfrm_policy.c, so replace them with delayed_work.
Note that, this patch is not fully tested, just compile and
run as a whole on an Intel Core Duo matchine. So should be
in -mm first.
Signed-off-by: WANG Cong <xiyou.wangcong@gmail.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David Miller <davem@davemloft.net>
---
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index ac72116..53f4794 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -430,7 +430,7 @@ struct xfrm_policy
/* This lock only affects elements except for entry. */
rwlock_t lock;
atomic_t refcnt;
- struct timer_list timer;
+ struct delayed_work work;
u32 priority;
u32 index;
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index 47219f9..58066f0 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -126,9 +126,10 @@ static inline unsigned long make_jiffies(long secs)
return secs*HZ;
}
-static void xfrm_policy_timer(unsigned long data)
+static void xfrm_policy_worker(struct work_struct *w)
{
- struct xfrm_policy *xp = (struct xfrm_policy*)data;
+ struct xfrm_policy *xp =
+ container_of((struct delayed_work *)w, struct xfrm_policy, work);
unsigned long now = get_seconds();
long next = LONG_MAX;
int warn = 0;
@@ -181,7 +182,7 @@ static void xfrm_policy_timer(unsigned long data)
if (warn)
km_policy_expired(xp, dir, 0, 0);
if (next != LONG_MAX &&
- !mod_timer(&xp->timer, jiffies + make_jiffies(next)))
+ !schedule_delayed_work(&xp->work, make_jiffies(next)))
xfrm_pol_hold(xp);
out:
@@ -208,12 +209,11 @@ struct xfrm_policy *xfrm_policy_alloc(gfp_t gfp)
policy = kzalloc(sizeof(struct xfrm_policy), gfp);
if (policy) {
+ INIT_DELAYED_WORK(&policy->work, xfrm_policy_worker);
INIT_HLIST_NODE(&policy->bydst);
INIT_HLIST_NODE(&policy->byidx);
rwlock_init(&policy->lock);
atomic_set(&policy->refcnt, 1);
- setup_timer(&policy->timer, xfrm_policy_timer,
- (unsigned long)policy);
}
return policy;
}
@@ -227,7 +227,7 @@ void xfrm_policy_destroy(struct xfrm_policy *policy)
BUG_ON(policy->bundles);
- if (del_timer(&policy->timer))
+ if (cancel_delayed_work(&policy->work))
BUG();
security_xfrm_policy_free(policy);
@@ -244,7 +244,7 @@ static void xfrm_policy_gc_kill(struct xfrm_policy *policy)
dst_free(dst);
}
- if (del_timer(&policy->timer))
+ if (cancel_delayed_work(&policy->work))
atomic_dec(&policy->refcnt);
if (atomic_read(&policy->refcnt) > 1)
@@ -566,7 +566,7 @@ int xfrm_policy_insert(int dir, struct xfrm_policy *policy, int excl)
hlist_add_head(&policy->byidx, xfrm_policy_byidx+idx_hash(policy->index));
policy->curlft.add_time = get_seconds();
policy->curlft.use_time = 0;
- if (!mod_timer(&policy->timer, jiffies + HZ))
+ if (!schedule_delayed_work(&policy->work, HZ))
xfrm_pol_hold(policy);
write_unlock_bh(&xfrm_policy_lock);
^ permalink raw reply related
* [Patch]net/xfrm/xfrm_state.c: replace timer with delayed_work
From: WANG Cong @ 2008-02-16 16:00 UTC (permalink / raw)
To: Linux Kernel Mailing List; +Cc: Herbert Xu, David Miller, Andrew Morton, netdev
Also suggested by Herbert Xu, using workqueue is better than timer
for net/xfrm/xfrm_state.c, so replace them with delayed_work.
Note that, this patch is not fully tested, just compile and
run as a whole on an Intel Core Duo matchine. So should be
in -mm first.
Signed-off-by: WANG Cong <xiyou.wangcong@gmail.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: David Miller <davem@davemloft.net>
---
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index ac72116..ff718b4 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -188,14 +188,14 @@ struct xfrm_state
u32 replay_maxage;
u32 replay_maxdiff;
- /* Replay detection notification timer */
- struct timer_list rtimer;
+ /* Replay detection notification delayed work */
+ struct delayed_work rwork;
/* Statistics */
struct xfrm_stats stats;
struct xfrm_lifetime_cur curlft;
- struct timer_list timer;
+ struct delayed_work work;
/* Last used time */
unsigned long lastused;
diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c
index 7ba65e8..e0511c9 100644
--- a/net/xfrm/xfrm_state.c
+++ b/net/xfrm/xfrm_state.c
@@ -379,8 +379,8 @@ static void xfrm_put_mode(struct xfrm_mode *mode)
static void xfrm_state_gc_destroy(struct xfrm_state *x)
{
- del_timer_sync(&x->timer);
- del_timer_sync(&x->rtimer);
+ cancel_delayed_work_sync(&x->work);
+ cancel_delayed_work_sync(&x->rwork);
kfree(x->aalg);
kfree(x->ealg);
kfree(x->calg);
@@ -423,9 +423,10 @@ static inline unsigned long make_jiffies(long secs)
return secs*HZ;
}
-static void xfrm_timer_handler(unsigned long data)
+static void xfrm_work_handler(struct work_struct *w)
{
- struct xfrm_state *x = (struct xfrm_state*)data;
+ struct xfrm_state *x =
+ container_of((struct delayed_work *)w, struct xfrm_state, work);
unsigned long now = get_seconds();
long next = LONG_MAX;
int warn = 0;
@@ -476,7 +477,7 @@ static void xfrm_timer_handler(unsigned long data)
km_state_expired(x, 0, 0);
resched:
if (next != LONG_MAX)
- mod_timer(&x->timer, jiffies + make_jiffies(next));
+ schedule_delayed_work(&x->work, make_jiffies(next));
goto out;
@@ -499,7 +500,7 @@ out:
spin_unlock(&x->lock);
}
-static void xfrm_replay_timer_handler(unsigned long data);
+static void xfrm_replay_work_handler(struct work_struct *);
struct xfrm_state *xfrm_state_alloc(void)
{
@@ -513,9 +514,8 @@ struct xfrm_state *xfrm_state_alloc(void)
INIT_HLIST_NODE(&x->bydst);
INIT_HLIST_NODE(&x->bysrc);
INIT_HLIST_NODE(&x->byspi);
- setup_timer(&x->timer, xfrm_timer_handler, (unsigned long)x);
- setup_timer(&x->rtimer, xfrm_replay_timer_handler,
- (unsigned long)x);
+ INIT_DELAYED_WORK(&x->work, xfrm_work_handler);
+ INIT_DELAYED_WORK(&x->rwork, xfrm_replay_work_handler);
x->curlft.add_time = get_seconds();
x->lft.soft_byte_limit = XFRM_INF;
x->lft.soft_packet_limit = XFRM_INF;
@@ -851,8 +851,7 @@ xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr,
hlist_add_head(&x->byspi, xfrm_state_byspi+h);
}
x->lft.hard_add_expires_seconds = sysctl_xfrm_acq_expires;
- x->timer.expires = jiffies + sysctl_xfrm_acq_expires*HZ;
- add_timer(&x->timer);
+ schedule_delayed_work(&x->work, sysctl_xfrm_acq_expires*HZ);
xfrm_state_num++;
xfrm_hash_grow_check(x->bydst.next != NULL);
} else {
@@ -923,9 +922,9 @@ static void __xfrm_state_insert(struct xfrm_state *x)
hlist_add_head(&x->byspi, xfrm_state_byspi+h);
}
- mod_timer(&x->timer, jiffies + HZ);
+ schedule_delayed_work(&x->work, HZ);
if (x->replay_maxage)
- mod_timer(&x->rtimer, jiffies + x->replay_maxage);
+ schedule_delayed_work(&x->rwork, x->replay_maxage);
wake_up(&km_waitq);
@@ -1034,8 +1033,7 @@ static struct xfrm_state *__find_acq_core(unsigned short family, u8 mode, u32 re
x->props.reqid = reqid;
x->lft.hard_add_expires_seconds = sysctl_xfrm_acq_expires;
xfrm_state_hold(x);
- x->timer.expires = jiffies + sysctl_xfrm_acq_expires*HZ;
- add_timer(&x->timer);
+ schedule_delayed_work(&x->work, sysctl_xfrm_acq_expires*HZ);
hlist_add_head(&x->bydst, xfrm_state_bydst+h);
h = xfrm_src_hash(daddr, saddr, family);
hlist_add_head(&x->bysrc, xfrm_state_bysrc+h);
@@ -1302,7 +1300,7 @@ out:
memcpy(&x1->lft, &x->lft, sizeof(x1->lft));
x1->km.dying = 0;
- mod_timer(&x1->timer, jiffies + HZ);
+ schedule_delayed_work(&x1->work, HZ);
if (x1->curlft.use_time)
xfrm_state_check_expire(x1);
@@ -1327,7 +1325,7 @@ int xfrm_state_check_expire(struct xfrm_state *x)
if (x->curlft.bytes >= x->lft.hard_byte_limit ||
x->curlft.packets >= x->lft.hard_packet_limit) {
x->km.state = XFRM_STATE_EXPIRED;
- mod_timer(&x->timer, jiffies);
+ schedule_delayed_work(&x->work, 0);
return -EINVAL;
}
@@ -1596,13 +1594,14 @@ void xfrm_replay_notify(struct xfrm_state *x, int event)
km_state_notify(x, &c);
if (x->replay_maxage &&
- !mod_timer(&x->rtimer, jiffies + x->replay_maxage))
+ !schedule_delayed_work(&x->rwork, x->replay_maxage))
x->xflags &= ~XFRM_TIME_DEFER;
}
-static void xfrm_replay_timer_handler(unsigned long data)
+static void xfrm_replay_work_handler(struct work_struct *w)
{
- struct xfrm_state *x = (struct xfrm_state*)data;
+ struct xfrm_state *x =
+ container_of((struct delayed_work *)w, struct xfrm_state, rwork);
spin_lock(&x->lock);
^ permalink raw reply related
* [PATCH] mv643xx_eth: Define module alias for platform device
From: Martin Michlmayr @ 2008-02-16 17:16 UTC (permalink / raw)
To: Dale Farnsworth, netdev
The mv643xx_eth driver can be loaded as a platform device, as is done by
various Orion (ARM) based devices. The driver needs to define a module
alias for the platform driver so udev will load it automatically.
Tested with Debian on a QNAP TS-209.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -2104,6 +2104,7 @@ MODULE_LICENSE("GPL");
MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
" and Dale Farnsworth");
MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
+MODULE_ALIAS("platform:mv643xx_eth");
/*
* The second part is the low level driver of the gigE ethernet ports.
--
Martin Michlmayr
http://www.cyrius.com/
^ permalink raw reply
* Re: include/linux/pcounter.h
From: Andrew Morton @ 2008-02-16 19:26 UTC (permalink / raw)
To: Eric Dumazet; +Cc: Herbert Xu, David S. Miller, netdev, linux-kernel
In-Reply-To: <47B6D12A.3090401@cosmosbay.com>
On Sat, 16 Feb 2008 13:03:54 +0100 Eric Dumazet <dada1@cosmosbay.com> wrote:
> Andrew Morton a écrit :
> > On Sat, 16 Feb 2008 11:07:29 +0100 Eric Dumazet <dada1@cosmosbay.com> wrote:
> >
> >> Andrew, pcounter is a temporary abstraction.
> >
> > It's buggy! Main problems are a) possible return of negative numbers b)
> > some of the API can't be from preemptible code c) excessive interrupt-off
> > time on some machines if used from irq-disabled sections.
This is starting to get tiresome. Please do not waste my time and everyone
else's by defending the indefensible.
> a) We dont care of possibly off values when reading /proc/net/sockstat
So take the damn thing out of ./lib/ and hide it down in networking
somewhere.
> Same arguments apply for percpu_counters.
No it does not, Not at all. Callers regularly use percpu_counters to count
the number of some object. These counts never go negative!
And how the heck can you say that we don't care if /proc/net/sockstat goes
negative? You don't know that. Someone's system-monitoring app might very
well take drastic action if it sees connection-related statistics go
negative, or around 4 gigaconnections.
> b) It is called from network parts where preemption is disabled.
It's in ./lib/
> net/ipv4/inet_timewait_sock.c:94:
> sock_prot_inuse_add(sk->sk_prot, -1);
> net/ipv4/inet_hashtables.c:291: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv4/inet_hashtables.c:335: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv4/inet_hashtables.c:357: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv4/inet_hashtables.c:390: sock_prot_inuse_add(sk->sk_prot, -1);
> net/ipv4/raw.c:95: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv4/raw.c:104: sock_prot_inuse_add(sk->sk_prot, -1);
> net/ipv4/udp.c:235: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv6/ipv6_sockglue.c:271:
> sock_prot_inuse_add(sk->sk_prot, -1);
> net/ipv6/ipv6_sockglue.c:272:
> sock_prot_inuse_add(&tcp_prot, 1);
> net/ipv6/ipv6_sockglue.c:285:
> sock_prot_inuse_add(sk->sk_prot, -1);
> net/ipv6/ipv6_sockglue.c:286:
> sock_prot_inuse_add(prot, 1);
> net/ipv6/inet6_hashtables.c:46: sock_prot_inuse_add(sk->sk_prot, 1);
> net/ipv6/inet6_hashtables.c:207: sock_prot_inuse_add(sk->sk_prot, 1);
>
> c) No need to play with irq games here.
It's in ./lib/
> >
> >> It is temporaty because it will vanish as soon as Christoph Clameter (or
> >> somebody else) provides real cheap per cpu counter implementation.
> >
> > numbers?
> >
> > most of percpu_counter_add() is only executed once per FBC_BATCH calls.
>
>
>
> >
> >> At time I introduced it in network tree (locally, not meant to invade kernel
> >> land and makes you unhappy :) ), the goals were :
> >
> > Well maybe as a temporary networking-only thing OK, based upon
> > performance-tested results. But I don't think the present code is suitable
> > as part of the kernel-wide toolkit.
> >
> >> Some counters (total sockets count) were a single integer, that were doing
> >> ping-pong between cpus (SMP/NUMA). As they are basically lazy values (as we
> >> dont really need to read their value), using plain atomic_t was overkill.
> >>
> >> Using a plain percpu_counters was expensive (NR_CPUS*(32+sizeof(void *))
> >> instead of num_possible_cpus()*4).
> >
> > No, percpu_counters use alloc_percpu(), which is O(num_possible_cpus), not
> > O(NR_CPUS).
>
> You are playing with words.
I assumed the comment was comparing with percpu_counters.
Seems that it was comparing with some hand-rolled static array of NR_CPUS
entries or something.
> >
> >> We want really fast write side. Real fast.
> >
> > eh? It's called on a per-connection basis, not on a per-packet basis?
>
> Yes, per connection basis. Some workloads want to open/close more than 1000
> sockets per second.
ie: slowpath
> You are right we also need to reduce all atomic inc/dec done per packet :)
>
> A pcounter/perc_cpu for the device refcounter would be a very nice win, but as
> number of devices in the system might be very big, David said no to a percpu
> conversion. We will reconsider this when new percpu stuff can go in, so that
> the memory cost will be minimal (4 bytes per cpu per device)
>
> >
> >> Read side is when you do a "cat /proc/net/sockstat".
> >> That is ... once in a while...
> >
> > For the current single caller. But it's in ./lib/.
> >
> > And there's always someone out there who does whatever we don't expect them
> > to do.
> >
> >> Now when we allocate a new socket, code to increment the "socket count" is :
> >>
> >> c03a74a8 <tcp_pcounter_add>:
> >> c03a74a8: b8 90 26 5f c0 mov $0xc05f2690,%eax
> >> c03a74ad: 64 8b 0d 10 f1 5e c0 mov %fs:0xc05ef110,%ecx
> >> c03a74b4: 01 14 01 add %edx,(%ecx,%eax,1)
> >> c03a74b7: c3 ret
> >
> > I can't find that code. I suspect that's the DEFINE_PER_CPU flavour, which
> > isn't used anywhere afaict. Plus this omits the local_irq_save/restore (or
> > preempt_disable/enable) and the indirect function call, which can be
> > expensive.
>
> Please do : nm vmlinux | grep tcp_pcounter_add
>
> c03a74a8 t tcp_pcounter_add
>
> It should be there, even if its a static function
>
Probably - the macros hide it well. And the function itself doesn't tell
the whole story: callers must still do preempt_dsable or local_irq_enable
and must wear the cost of an indirect call.
> >
> >> It is even clearly stated at the top of include/linux/pcounter.h
> >>
> >> /*
> >> * Using a dynamic percpu 'int' variable has a cost :
> >> * 1) Extra dereference
> >> * Current per_cpu_ptr() implementation uses an array per 'percpu variable'.
> >> * 2) memory cost of NR_CPUS*(32+sizeof(void *)) instead of num_possible_cpus()*4
> >> *
> >> * This pcounter implementation is an abstraction to be able to use
> >> * either a static or a dynamic per cpu variable.
> >> * One dynamic per cpu variable gets a fast & cheap implementation, we can
> >> * change pcounter implementation too.
> >> */
> >>
> >>
> >> We all agree.
> >>
> >
> > No we don't. That comment is afaict wrong about the memory consumption and
> > the abstraction *isn't useful*.
>
> Fact is that we need percpu 32bits counters, and we need to have pointers to them.
>
> Current percpu_counters cannot cope that.
yes they can.
> >
> > Why do we want some abstraction which makes alloc_percpu() storage and
> > DEFINE_PERCPU storage "look the same"? What use is there in that? One is
> > per-object storage and one is singleton storage - they're quite different
> > things and they are used in quite different situations and they are
> > basically never interchangeable. Yet we add this pretend-they're-the-same
> > wrapper around them which costs us an indirect function call on the
> > fastpath.
>
> I believe all 'pcounter' are in fact statically allocated 'one per struct
> proto' to track inuse count. (search for DEFINE_PROTO_INUSE() uses)
>
> # find net include|xargs grep -n DEFINE_PROTO_INUSE
> net/dccp/ipv6.c:1105:DEFINE_PROTO_INUSE(dccp_v6)
> net/dccp/ipv4.c:920:DEFINE_PROTO_INUSE(dccp_v4)
> net/ipv6/udp.c:1001:DEFINE_PROTO_INUSE(udpv6)
> net/ipv6/udplite.c:43:DEFINE_PROTO_INUSE(udplitev6)
> net/ipv6/raw.c:1187:DEFINE_PROTO_INUSE(rawv6)
> net/ipv6/tcp_ipv6.c:2108:DEFINE_PROTO_INUSE(tcpv6)
> net/ipv4/udp.c:1477:DEFINE_PROTO_INUSE(udp)
> net/ipv4/udplite.c:47:DEFINE_PROTO_INUSE(udplite)
> net/ipv4/tcp_ipv4.c:2406:DEFINE_PROTO_INUSE(tcp)
> net/ipv4/raw.c:828:DEFINE_PROTO_INUSE(raw)
> net/sctp/socket.c:6461:DEFINE_PROTO_INUSE(sctp)
> net/sctp/socket.c:6495:DEFINE_PROTO_INUSE(sctpv6)
> include/net/sock.h:624:# define DEFINE_PROTO_INUSE(NAME) DEFINE_PCOUNTER(NAME)
> include/net/sock.h:644:# define DEFINE_PROTO_INUSE(NAME)
>
> So pcounter_alloc()/pcounter_free() could just be deleted from pcounter.h
Well if you do that and if pcounters become helpers functions around
DEFINE_PERCPU memory then things are starting to get a bit more sensible.
We can then remove the indirect function call.
Yes, a general wrapper around a DEFINE_PERCPU'ed counter could be a useful
thing to have. It could use raw_smp_processor_id() and local_add().
Problem is the read side will still be far too inefficient for it to be
presentable as a general-purpose library - it really will need to do all
the batching which experience told us was needed in percpu_counters.
The read side should also present two interfaces: one which returns a +ve
or -ve value and one which returns a never-negative value.
> indirect functions calls are everywhere in kernel, network, fs, everywhere.
That doesn't make them fast.
> As soon we can put in 'struct pcounter' the address of a percpu variable, we
> wont need anymore pointers to the pcounter_add()/getval() function.
>
> mov 0(pcounter),%eax # get the address of a percpuvar
> add %edx,fs:%eax
>
> This just need the percpu work done by SGI guys to be finished.
So... I need to keep watching the tree to make sure that nobody actually
uses this code in ./lib/?
^ permalink raw reply
* Re: include/linux/pcounter.h
From: Arjan van de Ven @ 2008-02-16 19:39 UTC (permalink / raw)
To: Andrew Morton
Cc: Eric Dumazet, Herbert Xu, David S. Miller, netdev, linux-kernel
In-Reply-To: <20080216112618.ec450f9b.akpm@linux-foundation.org>
On Sat, 16 Feb 2008 11:26:18 -0800
Andrew Morton <akpm@linux-foundation.org> wrote:
> > indirect functions calls are everywhere in kernel, network, fs,
> > everywhere.
>
> That doesn't make them fast.
just to emphasize this: an indirect function call is at least as expensive as an atomic operation on
x86 cpus.... (if not more)
--
If you want to reach me at my work email, use arjan@linux.intel.com
For development, discussion and tips for power savings,
visit http://www.lesswatts.org
^ permalink raw reply
* Re: [PATCH] plusb.c patched to support Belkin F5U258 USB host-to-host cable
From: David Brownell @ 2008-02-16 20:41 UTC (permalink / raw)
To: tony_gibbs; +Cc: NETDEV mailing list, Linux USB mailing list
In-Reply-To: <200802141557_MC3-1-FBB3-3DA7@compuserve.com>
Here's a patch with cleanups and without various encoding bugs.
Can you verify it still works?
Also, some of the Prolific chips use some bizarre control requests,
which by all rights should not be needed. They seem to exist only
to cope with things the device firmware should have handled ... like
resetting one end of a link after it's unplugged.
When you test this, please enable CONFIG_USB_DEBUG and let us know
if those the host software still needs to do that reset ... or at
least, whether the diagnostic appears.
- Dave
====== CUT HERE
Some plusb driver updates: pl25a1 support (based on info from
Tony Gibbs), and various cleanups.
---
drivers/net/usb/Kconfig | 2 -
drivers/net/usb/plusb.c | 52 ++++++++++++++++++++++++++++++++----------------
2 files changed, 36 insertions(+), 18 deletions(-)
--- g26.orig/drivers/net/usb/plusb.c 2008-02-16 11:49:04.000000000 -0800
+++ g26/drivers/net/usb/plusb.c 2008-02-16 12:28:54.000000000 -0800
@@ -17,9 +17,6 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-// #define DEBUG // error path messages, extra info
-// #define VERBOSE // more; success messages
-
#include <linux/module.h>
#include <linux/init.h>
#include <linux/netdevice.h>
@@ -45,6 +42,14 @@
* seems to get wedged under load. Prolific docs are weak, and
* don't identify differences between PL2301 and PL2302, much less
* anything to explain the different PL2302 versions observed.
+ *
+ * NOTE: pl2501 has several modes, including pl2301 and pl2302
+ * compatibility. Some docs suggest the difference between 2301
+ * and 2302 is only to make MS-Windows use a different driver...
+ *
+ * pl25a1 glue based on patch from Tony Gibbs. Prolific "docs" on
+ * this chip are as usual incomplete about what control messages
+ * are supported.
*/
/*
@@ -86,16 +91,20 @@ pl_set_QuickLink_features(struct usbnet
static int pl_reset(struct usbnet *dev)
{
+ int status;
+
/* some units seem to need this reset, others reject it utterly.
* FIXME be more like "naplink" or windows drivers.
*/
- (void) pl_set_QuickLink_features(dev,
+ status = pl_set_QuickLink_features(dev,
PL_S_EN|PL_RESET_OUT|PL_RESET_IN|PL_PEER_E);
+ if (status != 0 && netif_msg_probe(dev))
+ devdbg(dev, "pl_reset --> %d\n", status);
return 0;
}
static const struct driver_info prolific_info = {
- .description = "Prolific PL-2301/PL-2302",
+ .description = "Prolific PL-2301/PL-2302/PL-25A1",
.flags = FLAG_NO_SETINT,
/* some PL-2302 versions seem to fail usb_set_interface() */
.reset = pl_reset,
@@ -110,16 +119,25 @@ static const struct driver_info prolific
*/
static const struct usb_device_id products [] = {
+ /* full speed cables */
+ {
+ USB_DEVICE(0x067b, 0x0000), /* PL-2301 */
+ .driver_info = (unsigned long) &prolific_info,
+ }, {
+ USB_DEVICE(0x067b, 0x0001), /* PL-2302 */
+ .driver_info = (unsigned long) &prolific_info,
+ },
+
+ /* high speed cables */
+ {
+ USB_DEVICE(0x067b, 0x25a1), /* PL-25A1, no eeprom */
+ .driver_info = (unsigned long) &prolific_info,
+ }, {
+ USB_DEVICE(0x050d, 0x258a), /* Belkin F5U258 (PL-25A1) */
+ .driver_info = (unsigned long) &prolific_info,
+ },
-{
- USB_DEVICE(0x067b, 0x0000), // PL-2301
- .driver_info = (unsigned long) &prolific_info,
-}, {
- USB_DEVICE(0x067b, 0x0001), // PL-2302
- .driver_info = (unsigned long) &prolific_info,
-},
-
- { }, // END
+ { }, /* END */
};
MODULE_DEVICE_TABLE(usb, products);
@@ -134,16 +152,16 @@ static struct usb_driver plusb_driver =
static int __init plusb_init(void)
{
- return usb_register(&plusb_driver);
+ return usb_register(&plusb_driver);
}
module_init(plusb_init);
static void __exit plusb_exit(void)
{
- usb_deregister(&plusb_driver);
+ usb_deregister(&plusb_driver);
}
module_exit(plusb_exit);
MODULE_AUTHOR("David Brownell");
-MODULE_DESCRIPTION("Prolific PL-2301/2302 USB Host to Host Link Driver");
+MODULE_DESCRIPTION("Prolific PL-2301/2302/25A1 USB Host to Host Link Driver");
MODULE_LICENSE("GPL");
--- g26.orig/drivers/net/usb/Kconfig 2008-02-16 12:23:13.000000000 -0800
+++ g26/drivers/net/usb/Kconfig 2008-02-16 12:23:39.000000000 -0800
@@ -208,7 +208,7 @@ config USB_NET_NET1080
optionally with LEDs that indicate traffic
config USB_NET_PLUSB
- tristate "Prolific PL-2301/2302 based cables"
+ tristate "Prolific PL-2301/2302/25A1 based cables"
# if the handshake/init/reset problems, from original 'plusb',
# are ever resolved ... then remove "experimental"
depends on USB_USBNET && EXPERIMENTAL
^ permalink raw reply
* Re: RESEND, HTB(?) softlockup, vanilla 2.6.24
From: Jarek Poplawski @ 2008-02-16 20:45 UTC (permalink / raw)
To: Denys Fedoryshchenko; +Cc: netdev
In-Reply-To: <20080216102502.M41110@visp.net.lb>
On Sat, Feb 16, 2008 at 12:25:31PM +0200, Denys Fedoryshchenko wrote:
> Thanks, i will try it.
> You think lockdep can be buggy?
Just like every code... But the main reason is it has quite meaningful
overhead, so could be right "in production" only after lockups happen.
But if it doesn't report anything anyway...
Your report shows there are quite long paths of calls during softirqs
with some actions (ipt + mirred here?) and qdiscs, so if I'm not wrong
with this stack problem, this would need some optimization. And, of
course, there could be some additional bugs involved around too:
otherwise it seems this should happen more often. But I don't expect
you would try to debug this on your servers, so I hope, it simply will
be found BTW some day...
Regards,
Jarek P.
^ permalink raw reply
* [PATCH][2.6.25-rc2] Fix double lock in do_setlink introduced by 45b503548210fe6f23e92b856421c2a3f05fd034
From: Andrey Borzenkov @ 2008-02-16 23:57 UTC (permalink / raw)
To: netdev; +Cc: linux-kernel, Laszlo Attila Toth
[-- Attachment #1: Type: text/plain, Size: 1210 bytes --]
[ 58.097923] =============================================
[ 58.098883] [ INFO: possible recursive locking detected ]
[ 58.099603] 2.6.25-rc2-1avb #1
[ 58.100013] ---------------------------------------------
[ 58.100672] wpa_supplicant/2682 is trying to acquire lock:
[ 58.100672] (dev_base_lock){-.--}, at: [<c0278697>] do_setlink+0x327/0x3
[ 58.100672]
[ 58.100672] but task is already holding lock:
[ 58.100672] (dev_base_lock){-.--}, at: [<c0278680>] do_setlink+0x310/0x3
with final effect
[ 58.537509] Kernel panic - not syncing: Aiee, killing interrupt handler!
Signed-off-by: Andrey Borzenkov <arvidjaar@mail.ru>
---
net/core/rtnetlink.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index ecb02af..dd9e4da 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -853,7 +853,7 @@ static int do_setlink(struct net_device *dev, struct ifinfomsg *ifm,
if (dev->link_mode != nla_get_u8(tb[IFLA_LINKMODE])) {
write_lock_bh(&dev_base_lock);
dev->link_mode = nla_get_u8(tb[IFLA_LINKMODE]);
- write_lock_bh(&dev_base_lock);
+ write_unlock_bh(&dev_base_lock);
modified = 1;
}
}
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply related
* Re: RESEND, HTB(?) softlockup, vanilla 2.6.24
From: Denys Fedoryshchenko @ 2008-02-17 0:03 UTC (permalink / raw)
To: Jarek Poplawski; +Cc: netdev
In-Reply-To: <20080216204519.GA2739@ami.dom.local>
Server is fully redundant now, so i apply patches (but i apply both, probably
it will make system more reliable somehow) and i enable required debug
options in kernel. So i will try to catch this bug few more times, probably
if it will generate more detailed info over netconsole it will be useful.
Is there any project to dump console messages/kernel dump to disk? For
example such issues related to networking, and i guess netconsole doesn't
always work, especially when network driver is crashed, but tech's on
location told there is some messages running non-stop on the screen. Probably
some generic code writing such data over x86 INT 13 (or even kernel dump?) to
separate partition will be useful to debug this problem. I know there is some
3rd party patches(for example LKCD), but i prefer to not apply them to not
add more bugs.
I notice some code in MTD(CONFIG_MTD_OOPS), but i am not sure it is correct
and will work if i will setup MTD emulation for block device.
That just idea.
On Sat, 16 Feb 2008 21:45:19 +0100, Jarek Poplawski wrote
> On Sat, Feb 16, 2008 at 12:25:31PM +0200, Denys Fedoryshchenko wrote:
> > Thanks, i will try it.
> > You think lockdep can be buggy?
>
> Just like every code... But the main reason is it has quite
> meaningful overhead, so could be right "in production" only after
> lockups happen. But if it doesn't report anything anyway...
>
> Your report shows there are quite long paths of calls during softirqs
> with some actions (ipt + mirred here?) and qdiscs, so if I'm not
> wrong with this stack problem, this would need some optimization.
> And, of course, there could be some additional bugs involved around too:
> otherwise it seems this should happen more often. But I don't expect
> you would try to debug this on your servers, so I hope, it simply
> will be found BTW some day...
>
> Regards,
> Jarek P.
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Denys Fedoryshchenko
Technical Manager
Virtual ISP S.A.L.
^ permalink raw reply
* [PATHCH 1/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:30 UTC (permalink / raw)
To: netdev
NIC driver header files, h/w initialization function and
driver entry points.
------------------------------
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be.h benet/linux-2.6.24.2/drivers/net/benet/be.h
--- orig/linux-2.6.24.2/drivers/net/benet/be.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be.h 2008-02-14 15:23:07.787208928 +0530
@@ -0,0 +1,373 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef _BE_H
+#define _BE_H
+
+#include <linux/netdevice.h>
+#include "bni.h"
+
+typedef union _PHYSICAL_ADDRESS {
+ struct {
+ u32 pa_lo;
+ u32 pa_hi;
+ };
+ u64 pa;
+} PHYSICAL_ADDRESS;
+
+#define BE_ETHERNET_FCS_SIZE 4
+#define BE_ENET_HEADER_SIZE 14
+#define BE_VLAN_HEADER_SIZE 4
+#define BE_SNAP_HEADER_SIZE 5
+#define BE_HEADER_ETHERNET_II_802_3_SIZE 14
+#define BE_HEADER_802_2_SIZE 3
+#define BE_MIN_ETHER_FRAME_SIZE 64
+#define BE_MIN_SUPPORT_FRAME_SIZE 256
+#define BE_MAX_JUMBO_FRAME_SIZE 9000
+#define BE_MAXIMUM_ETHERNET_FRAME_SIZE 1518 /*With FCS */
+
+extern unsigned int dbg_mask;
+extern unsigned int pm_resume;
+
+extern char be_drvr_ver[];
+extern char be_fw_ver[];
+extern char be_driver_name[];
+
+typedef enum {
+ BE_DEVICE_1,
+ BE_DEVICE_2,
+ MAX_BE_DEVICES
+} BE_DEVICE_NUM;
+
+typedef enum {
+ BE_DEV_STATE_NONE,
+ BE_DEV_STATE_INIT,
+ BE_DEV_STATE_OPEN
+} BE_DEV_STATE;
+
+#define BE_DEV_STATE_OPEN(adapter) (adapter->dev_state == BE_DEV_STATE_OPEN)
+
+/*
+ * BE driver statistics.
+ */
+struct _be_stat {
+ u32 bes_tx_reqs; /* number of TX requests initiated */
+ u32 bes_tx_fails; /* number of TX requests that failed */
+ u32 bes_fwd_reqs; /* number of send reqs through forwarding i/f */
+ u32 bes_tx_wrbs; /* number of tx WRBs used */
+
+ u32 bes_ints; /* number of interrupts */
+ u32 bes_polls; /* number of times NAPI called poll function */
+ u32 bes_events; /* total evet entries processed */
+ u32 bes_tx_events; /* number of tx completion events */
+ u32 bes_ucrx_events; /* number of ucast rx completion events */
+ u32 bes_bcrx_events; /* number of bcast rx completion events */
+ u32 bes_tx_compl; /* number of tx completion entries processed */
+ u32 bes_ucrx_compl; /* number of ucrx completion entries
+ processed */
+ u32 bes_bcrx_compl; /* number of bcrx completion entries
+ processed */
+ u32 bes_ethrx_post_fail; /* number of ethrx buffer alloc
+ failures */
+ /*
+ *
+ * number of non ether type II frames dropped where
+ * frame len > length field of Mac Hdr
+ */
+ u32 bes_802_3_dropped_frames;
+ /*
+ * number of non ether type II frames malformed where
+ * in frame len < length field of Mac Hdr
+ */
+ u32 bes_802_3_malformed_frames;
+ u32 bes_ips; /* interrupts / sec */
+ u32 bes_prev_ints; /* bes_ints at last IPS calculation */
+ u16 bes_eth_tx_rate; /* ETH TX rate - Mb/sec */
+ u16 bes_eth_rx_rate; /* ETH RX rate - Mb/sec */
+#ifdef RX_PKT_COALESCE
+ u32 bes_rx_coal; /* Num pkts coalasced */
+ u32 bes_rx_flush; /* Num times coalasced */
+#endif
+ u32 bes_link_change_physical; /*Num of times physical link changed */
+ u32 bes_link_change_virtual; /*Num of times virtual link changed */
+};
+
+/* Macro to update RX/TX rates */
+#define UPDATE_RATE(AP, JIF, BYTES, RATE) \
+ if ((jiffies - AP->JIF) > 2*(HZ)) { \
+ u32 r; \
+ r = AP->BYTES / ((jiffies-AP->JIF)/(HZ)); \
+ r = (r / 1000000); /* MB/Sec */ \
+ AP->be_stat.RATE = (r * 8); /* Mega Bits/Sec */ \
+ AP->JIF = jiffies; \
+ AP->BYTES = 0; \
+ }
+
+/*
+ * Every second we look at the ints/sec and adjust eq_delay
+ * between AP->min_eqd and AP->max_eqd to keep the ints/sec between
+ * IPS_HI_WM and IPS_LO_WM.
+ */
+#define IPS_HI_WM 18000
+#define IPS_LO_WM 8000
+#define UPDATE_IPS(AP, NP) \
+ if ((jiffies - AP->ips_jiffies) > 1*(HZ)) { \
+ /* One second elapsed since last update */ \
+ u32 r, new_eqd = -1; \
+ if (AP->be_stat.bes_prev_ints > \
+ AP->be_stat.bes_ints) { \
+ /* interrupt counter wrapped aroud */ \
+ r = (0xFFFFFFFF - \
+ AP->be_stat.bes_prev_ints) + \
+ AP->be_stat.bes_ints; \
+ } \
+ else \
+ r = AP->be_stat.bes_ints - \
+ AP->be_stat.bes_prev_ints; \
+ r = r / ((jiffies - AP->ips_jiffies)/(HZ)); \
+ AP->be_stat.bes_ips = r; \
+ AP->ips_jiffies = jiffies; \
+ AP->be_stat.bes_prev_ints = \
+ AP->be_stat.bes_ints; \
+ if (r > IPS_HI_WM && \
+ AP->cur_eqd < AP->max_eqd) { \
+ /* increase eqdelay by a notch */ \
+ new_eqd = (AP->cur_eqd + 8); \
+ } \
+ if (r < IPS_LO_WM && \
+ AP->cur_eqd > AP->min_eqd) { \
+ /* decrease eqdelay by a notch */ \
+ new_eqd = (AP->cur_eqd - 8); \
+ } \
+ if (AP->enable_aic && new_eqd != -1) { \
+ /* program new delay */ \
+ if (bni_change_eqd(NP, new_eqd) == \
+ BE_SUCCESS) \
+ AP->cur_eqd = new_eqd; \
+ } \
+ }
+
+#define FAIL 1
+#define SUCCESS 0
+
+#define MAX_EQD 120
+
+/*
+ * timer to prevent system shutdown hang for ever if h/w stops responding
+ */
+typedef struct {
+ atomic_t get_stat_flag;
+ struct timer_list get_stats_timer;
+ unsigned long get_stat_sem; /* semaphore to wait */
+} be_timer_ctxt_t;
+
+#ifdef RX_PKT_COALESCE
+#define MAX_COALESCE_SIZE 48*1024
+#define MAX_COALESCE_FRAGS (MAX_SKB_FRAGS - 1)
+#define MAX_COALESCE_OBJECTS 8
+/* struture to keep track of adjacent packets in a connection that
+ * can be colesced to a larger packet during RX completion processing.
+ */
+struct be_coalesce_object {
+ PBNI_NET_OBJECT pnob;
+ struct sk_buff *skb;
+ unsigned int frag_cnt;
+ unsigned int next_pkt_seq;
+ unsigned int next_ack_seq;
+ unsigned int tcp_timestamp;
+ unsigned int tcp_tsecr;
+ unsigned int tcp_tsval;
+ unsigned short sport;
+ unsigned short dport;
+ unsigned int saddr;
+ unsigned int daddr;
+ unsigned short last_seen_window;
+ unsigned short mss;
+ unsigned short vlant;
+ unsigned short rsvd;
+
+};
+#endif /* RX_PKT_COALESCE */
+
+/* This structure is the main BladeEngine driver context. */
+typedef struct _BE_ADAPTER {
+ struct net_device *netdevp;
+ struct _be_stat be_stat;
+ struct net_device_stats benet_stats;
+ u32 num_bars;
+ SA_DEV_BAR_LOCATIONS pci_bars[3]; /* PCI BAR details */
+#ifdef CONFIG_PM
+ u32 pci_state[16];
+#endif
+ SA_DEV sa_device; /* device object owned by beclib */
+ BE_CHIP_OBJECT chip_object; /* BEClib chip object */
+
+ struct tasklet_struct sts_handler;
+ struct timer_list cq_timer;
+ spinlock_t int_lock;
+
+ PIOCTL_ETH_GET_STATISTICS eth_statsp;
+ /*
+ * This will enable the use of ethtool to enable or disable
+ * Checksum on Rx pkts to be obeyed or disobeyed.
+ * If this is TRUE = 1, then whatever is the checksum on the
+ * Received pkt as per BE, it will be given to the stack.
+ * Else the stack will re calculate it.
+ */
+ BOOLEAN rx_csum;
+#ifdef RX_PKT_COALESCE
+ /*
+ * This will enable the use of ethtool to enable or disable
+ * Coalese on Rx pkts to be obeyed or disobeyed.
+ * If this is grater than 0 and less than 16 then coalascing
+ * is enabled else it is disabled
+ */
+ u32 max_rx_coal;
+#endif
+ struct pci_dev *pdev; /* Pointer to OS's PCI dvice */
+
+ spinlock_t txq_lock;
+
+ u32 isr; /* copy of Intr status reg. */
+
+ u32 port0_link_sts; /* Port 0 link status */
+ u32 port1_link_sts; /* port 1 list status */
+ PBE_LINK_STATUS be_link_sts;
+ PBNI_NET_OBJECT net_obj;
+
+ /* Flags to indicate what to clean up */
+ BOOLEAN tasklet_started;
+ BOOLEAN isr_registered;
+ /*
+ * adaptive interrupt coalescing (AIC) related
+ */
+ u16 enable_aic; /* 1 if AIC is enabled */
+ u16 min_eqd; /* minimum EQ delay in usec */
+ u16 max_eqd; /* minimum EQ delay in usec */
+ u16 cur_eqd; /* current EQ delay in usec */
+ /*
+ * book keeping for interrupt / sec and TX/RX rate calculation
+ */
+ ulong ips_jiffies; /* jiffies at last IPS calc */
+ u32 eth_tx_bytes;
+ ulong eth_tx_jiffies;
+ u32 eth_rx_bytes;
+ ulong eth_rx_jiffies;
+
+ struct semaphore get_eth_stat_sem;
+ be_timer_ctxt_t *ctxt; /* context for get stats timer */
+
+#define BE_MAX_MSIX_VECTORS 32
+#define BE_MAX_REQ_MSIX_VECTORS 1
+ struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS];
+ BOOLEAN msix_enabled; /*MSI has been enabled */
+ BOOLEAN dma_64bit_cap; /* is the Device DAC capable */
+ int be_fw_ver; /* BE F/W version */
+ BOOLEAN dev_state; /* The current state of the device */
+
+} BE_ADAPTER, *PBE_ADAPTER;
+
+extern PBE_ADAPTER be_adapter[MAX_BE_DEVICES];
+
+typedef struct be_rx_page_info {
+ struct page *page;
+ dma_addr_t bus;
+ u16 page_offset;
+} BE_RX_PAGE_INFO;
+
+/*
+ * linux_net_object is an extension to BNI's NetObject structure.
+ * NetObject has a pointer to this structure
+ */
+typedef struct {
+ PVOID os_handle; /* Context info for VMM */
+ BNI_RECV_BUFFER eth_rx_bufs[256]; /* to pass Rx buffer
+ addresses */
+ PBE_ADAPTER adapter; /* Pointer to OSM adapter */
+ u32 devno; /* OSM, network dev no. */
+ u32 use_port; /* Current active port */
+ BE_RX_PAGE_INFO *rx_page_info; /* Array of Rx buf pages */
+ u32 rx_pg_info_hd; /* Head of queue */
+ int rxbuf_post_fail; /* RxBuff posting fail count */
+ BOOLEAN rx_pg_shared; /* Is an allocsted page shared as two frags ? */
+ struct vlan_group *vlan_grp;
+ u32 num_vlans; /* Number of vlans in BE's filter */
+ u16 vlan_tag[BE_NUM_VLAN_SUPPORTED]; /* vlans currently configured */
+#ifdef CONFIG_BENET_NAPI
+ struct napi_struct napi;
+ u32 work_quota; /* Max RX packets to process */
+ BOOLEAN rx_sched;
+ spinlock_t rx_lock;
+#endif
+#ifdef RX_PKT_COALESCE
+ struct be_coalesce_object rxc_obj[MAX_COALESCE_OBJECTS];
+ u32 num_coalesce_objects;
+#endif
+} linux_net_object_t;
+
+/* convenience macro to access members in Linux extension of NetObject */
+#define OSM_NOB(x) ((linux_net_object_t *) (x)->osm_netobj)
+
+/* proto declarations */
+
+int benet_probe(struct net_device *netdev);
+void be_set_ethtool_ops(struct net_device *netdev);
+int be_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr);
+struct net_device_stats *benet_get_stats(struct net_device *);
+
+int be_prepare_interface(PBE_ADAPTER adapter);
+void cleanup_netobject(PBNI_NET_OBJECT);
+void osm_process_sts(unsigned long context);
+irqreturn_t be_int(int irq, PVOID dev, struct pt_regs *regs);
+
+int betx_ether_frame(PBE_ADAPTER pBeAdapter, PBNI_NET_OBJECT NetObject,
+ struct sk_buff *skb, u8 proto, u8 forward,
+ u16 lso_mss);
+
+void post_eth_rx_buffs(PBNI_NET_OBJECT NetObject);
+void get_stat_cb(PVOID context, BESTATUS status, MCC_WRB *optional_wrb);
+
+void get_stats_timer_handler(unsigned long context);
+
+void enable_eq_intr(PBNI_NET_OBJECT pnob);
+void disable_eq_intr(PBNI_NET_OBJECT pnob);
+
+void wait_nic_tx_cmpl(PBNI_NET_OBJECT pnob);
+void be_print_link_info(PBE_LINK_STATUS lnk_status);
+void be_update_link_status(PBE_ADAPTER adapter);
+
+void be_init_procfs(PBE_ADAPTER adapter);
+void be_cleanup_procfs(PBE_ADAPTER adapter);
+
+#ifdef CONFIG_BENET_NAPI
+int be_poll(struct napi_struct *napi, int budget);
+#endif
+#endif /* _BE_H */
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/bni.h benet/linux-2.6.24.2/drivers/net/benet/bni.h
--- orig/linux-2.6.24.2/drivers/net/benet/bni.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/bni.h 2008-02-14 15:23:07.788208776 +0530
@@ -0,0 +1,374 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+
+@file
+ bni.h
+
+@brief
+ Definitions and macros that are required for all .c files
+ that use the BNI API and implement the BNI API functions
+*/
+#ifndef _BNI_H
+#define _BNI_H
+
+#define _SA_MODULE_NAME "net-driver"
+#include "beclib_ll.h"
+
+#define VLAN_VALID_BIT 0x8000
+#define BE_NUM_VLAN_SUPPORTED 32
+#define BE_PORT_LINK_DOWN 0000
+#define BE_PORT_LINK_UP 0001
+
+typedef unsigned char BOOLEAN;
+
+#define TOU32(_struct_) *((u32 *)(&(_struct_)))
+
+/*
+ * DLs used by the Network driver. 0x00000000 to 0x00000800 are used
+ * by SA/BECLIB
+ */
+typedef enum _NETD_DEBUG_LEVELS {
+ DL_ERROR = DL_ERR,
+ DL_EVENT = 0x00001000,
+ DL_CQ = 0x00002000,
+ DL_SEND = 0x00004000,
+ DL_RECV = 0x00008000,
+ DL_WINDOW = 0x00010000,
+ DL_OFFLOAD = 0x00020000,
+ DL_UPLOAD = 0x00040000,
+ DL_VLAN = 0x00080000,
+ DL_IPSEC = 0x00100000,
+ DL_INT = 0x00200000,
+ DL_PNP = 0x00400000,
+ DL_ETH_INFO = 0x00800000,
+ DL_TIMER = 0x01000000,
+ DL_INIT = 0x02000000,
+ DL_SHUTDOWN = 0x04000000,
+} NET_DEBUG_LEVELS;
+
+/*
+ * Structure to return Ethernet statistics counters maintained by BE.
+ * Defined in srcgen.
+ */
+typedef BE_RXF_STATS BLADE_ETH_STATS, *PBLADE_ETH_STATS;
+
+/*
+@brief
+ This structure is used by the OSM driver to give BNI
+ physical fragments to use for DMAing data from NIC.
+*/
+typedef struct _BNI_RECV_BUFFER {
+ SA_LIST_ENTRY rxb_list; /* for maintaining a linked list */
+ PVOID rxb_va; /* buffer virtual address */
+ u32 rxb_pa_lo; /* low part of physical address */
+ u32 rxb_pa_hi; /* high part of physical address */
+ u32 rxb_len; /* length of recv buffer */
+ PVOID rxb_ctxt; /* context for OSM driver to use */
+} BNI_RECV_BUFFER, *PBNI_RECV_BUFFER;
+
+/*
+ * fragment list to describe scattered data.
+ */
+typedef struct _BNI_TX_FRAG_LIST {
+ u32 txb_len; /* Size of this fragment */
+ u32 txb_pa_lo; /* Lower 32 bits of 64 bit physical addr */
+ u32 txb_pa_hi; /* Higher 32 bits of 64 bit physical addr */
+} BNI_TX_FRAG_LIST, *PBNI_TX_FRAG_LIST;
+/*
+ * maximum fragements in a TX request
+ */
+#define BE_MAX_TX_FRAG_COUNT (30)
+
+/*
+ * Flag bits for send operation
+ */
+#define IPCS (1 << 0) /* Enable IP checksum offload */
+#define UDPCS (1 << 1) /* Enable UDP checksum offload */
+#define TCPCS (1 << 2) /* Enable TCP checksum offload */
+#define LSO (1 << 3) /* Enable Large Segment offload */
+#define ETHVLAN (1 << 4) /* Enable VLAN insert */
+#define ETHEVENT (1 << 5) /* Generate event on completion */
+#define ETHCOMPLETE (1 << 6) /* Generate completion when done */
+#define IPSEC (1 << 7) /* Enable IPSEC */
+#define FORWARD (1 << 8) /* Send the packet in forwarding path */
+#define FIN (1 << 9) /* Issue FIN segment */
+
+/* @brief
+ * This structure is the main tracking structure for a NIC interface.
+ * This data structure contains OS agnostic data members for processing
+ * intialization, sends, receives, and asynchronous events from the
+ * BladeEngine network function. The OSM driver makes
+ * calls into functions defined at this layer for initialization,
+ * eumeration and population of physical fragments with per-packet
+ * control flags for send and receive operations, population of
+ * receive buffers for NIC , and handling asynchronous
+ * events (such as link status change, packet pattern recognition etc.).
+ */
+typedef struct _BNI_NET_OBJECT {
+
+ /*
+ * MCC Ring - used to send ioctl cmds to embedded ARM processor
+ */
+ PMCC_WRB mcc_q; /* VA of the start of the ring */
+ u32 mcc_q_len; /* # of WRB entries in this ring */
+ u32 mcc_q_hd; /* MCC ring head */
+ u8 mcc_q_created; /* flag to help cleanup */
+ u8 mcc_q_pages; /* Num of pages allocacted by OSM */
+ BE_MCC_OBJECT mcc_q_obj; /* BECLIB's MCC ring Object */
+ SA_PHYSICAL_ADDRESS mcc_q_pa; /* Physical address in LE order */
+ /*
+ * MCC Completion Ring - ARM's responses to ioctls sent from MCC ring
+ */
+ PMCC_CQ_ENTRY mcc_cq; /* VA of the start of the ring */
+ u32 mcc_cq_len; /* # of compl. entries in this ring */
+ u32 mcc_cq_tl; /* compl. ring tail */
+ u8 mcc_cq_created; /* flag to help cleanup */
+ u8 mcc_cq_pages; /* Num of pages allocacted by OSM */
+ BE_CQ_OBJECT mcc_cq_obj; /* BECLIB's MCC compl. ring object */
+ u32 mcc_cq_id; /* MCC ring ID */
+ SA_PHYSICAL_ADDRESS mcc_cq_pa; /* Physical address in LE order */
+ /*
+ * BEClib uses an array of context objects to track outstanding
+ * requests to the MCC. We need allocate the same number of
+ * conext entries as the number of entries in the MCC WRB ring
+ */
+ u8 mcc_wrb_ctxt_pages; /* Num of pages allocacted by OSM */
+ PVOID mcc_wrb_ctxt; /* pointer to the context area */
+ u32 mcc_wrb_ctxtLen; /* Number of entries in the context */
+ /*
+ * NIC send request ring - used for xmitting raw ether frames.
+ */
+ PETH_WRB tx_q; /* VA of the start of the ring */
+ u32 tx_q_len; /* # if entries in the send ring */
+ u32 tx_q_hd; /* Head index. Next req. goes here */
+ u32 tx_q_tl; /* Tail indx. oldest outstanding req. */
+ u8 tx_q_created; /* flag to help cleanup */
+ u8 tx_q_pages; /* Num of pages allocacted by OSM */
+ BE_ETHSQ_OBJECT tx_q_obj; /* BECLIB's send Q handle */
+ SA_PHYSICAL_ADDRESS tx_q_pa; /* Physical address in LE order */
+ u32 tx_q_id; /* send queue ring ID */
+ u32 tx_q_port; /* 0 no binding, 1 port A, 2 port B */
+
+ u32 tx_q_used; /* # of WRBs used */
+ /* ptr to an array in which we store context info for each send req. */
+ PVOID *tx_ctxt;
+ /*
+ * NIC Send compl. ring - completion status for all NIC frames xmitted.
+ */
+ PETH_TX_COMPL tx_cq; /* VA of start of the ring */
+ u32 txcq_len; /* # of entries in the ring */
+ /*
+ * index into compl ring where the host expects next completion entry
+ */
+ u32 tx_cq_tl;
+ u32 tx_cq_id; /* completion queue id */
+ u8 tx_cq_created; /* flag to help cleanup */
+ u8 tx_cq_pages; /* Num of pages allocacted by OSM */
+ BE_CQ_OBJECT tx_cq_obj;
+ SA_PHYSICAL_ADDRESS tx_cq_pa; /* Physical address in LE order */
+ /*
+ * Event Queue - all completion entries post events here.
+ */
+ PEQ_ENTRY event_q; /* VA of start of event queue */
+ u32 event_q_len; /* # of entries */
+ u32 event_q_tl; /* Tail of the event queue */
+ u32 event_q_id; /* Event queue ID */
+ u8 event_q_created; /* flag to help cleanup */
+ u8 event_q_pages; /* Num of pages allocacted by OSM */
+ BE_EQ_OBJECT event_q_obj; /* Queue handle */
+ SA_PHYSICAL_ADDRESS event_q_pa; /* Physical address in LE order */
+ /*
+ * NIC receive queue - Data buffers to be used for receiving unicast,
+ * broadcast and multi-cast frames are posted here.
+ */
+ PETH_RX_D rx_q; /* VA of start of the queue */
+ u32 rx_q_len; /* # of entries */
+ u32 rx_q_hd; /* Head of the queue */
+ u32 rx_q_posted; /* number of posted buffers */
+ u32 rx_q_id; /* queue ID */
+ u8 rx_q_created; /* flag to help cleanup */
+ u8 rx_q_pages; /* Num of pages allocacted by OSM */
+ BE_ETHRQ_OBJECT rx_q_obj; /* NIC RX queue handle */
+ SA_PHYSICAL_ADDRESS rx_q_pa; /* Physical address */
+ /*
+ * Pointer to an array of opaque context object for use by OSM driver
+ */
+ PVOID *rx_ctxt;
+ /*
+ * NIC unicast RX completion queue - all unicast ether frame completion
+ * statuses from BE come here.
+ */
+ PETH_RX_COMPL ucrx_cq; /* VA of start of the queue */
+ u32 ucrx_cq_len; /* # of entries */
+ u32 ucrx_cq_tl; /* Tail of the queue */
+ u32 ucrx_cq_id; /* queue ID */
+ u8 ucrx_cq_created; /* flag to help cleanup */
+ u8 ucrx_cq_pages; /* Num of pages allocacted by OSM */
+ BE_CQ_OBJECT ucrx_cq_obj; /* queue handle */
+ SA_PHYSICAL_ADDRESS ucrx_cq_pa; /* Physical address in LE order */
+ /*
+ * Broadcast RX completion queue - all broadcast and multicast ether
+ * completion statues from BE come here.
+ */
+ PETH_RX_COMPL bcrx_cq; /* VA of start of queue */
+ u32 bcrx_cq_len; /* # of entries */
+ u32 bcrx_cq_tl; /* Tail of the queue */
+ u32 bcrx_cq_id; /* Queue ID */
+ u8 bcrx_cq_created; /* flag to help cleanup */
+ u8 bcrx_cq_pages; /* Num of pages allocacted by OSM */
+ BE_CQ_OBJECT bcrx_cq_obj; /* queue handle */
+ SA_PHYSICAL_ADDRESS bcrx_cq_pa; /* Physical address in LE order */
+
+ BE_FUNCTION_OBJECT fn_obj; /* function object */
+ u32 rx_buf_size; /* Size of the RX buffers */
+ u8 mac_address[6]; /* MAC address */
+ /*
+ * OSM handle. OSM drivers can use this pointer to extend NetObject.
+ */
+ PVOID osm_netobj;
+ SA_SGL mb_sgl; /* SGL for MCC_MAIL_BOX */
+ PVOID mb_ptr; /* mailbox ptr to be freed */
+} BNI_NET_OBJECT, *PBNI_NET_OBJECT;
+
+/*
+ * convenience macros to access some NetObject members
+ */
+#define NET_FH(np) (&(np)->fn_obj)
+
+/*
+ * Functions to advance the head and tail in various rings.
+ */
+static INLINE void bni_adv_eq_tl(PBNI_NET_OBJECT pnob)
+{
+ pnob->event_q_tl = (pnob->event_q_tl + 1) % pnob->event_q_len;
+}
+
+static INLINE void bni_adv_txq_hd(PBNI_NET_OBJECT pnob)
+{
+ pnob->tx_q_hd = (pnob->tx_q_hd + 1) % pnob->tx_q_len;
+}
+
+static INLINE void bni_adv_txq_tl(PBNI_NET_OBJECT pnob)
+{
+ pnob->tx_q_tl = (pnob->tx_q_tl + 1) % pnob->tx_q_len;
+}
+
+static INLINE void bni_adv_txcq_tl(PBNI_NET_OBJECT pnob)
+{
+ pnob->tx_cq_tl = (pnob->tx_cq_tl + 1) % pnob->txcq_len;
+}
+
+static INLINE void bni_adv_rxq_hd(PBNI_NET_OBJECT pnob)
+{
+ pnob->rx_q_hd = (pnob->rx_q_hd + 1) % pnob->rx_q_len;
+}
+
+static INLINE void bni_adv_ucrxcq_tl(PBNI_NET_OBJECT pnob)
+{
+ pnob->ucrx_cq_tl = (pnob->ucrx_cq_tl + 1) % pnob->ucrx_cq_len;
+}
+
+static INLINE void bni_adv_bcrxcq_tl(PBNI_NET_OBJECT pnob)
+{
+ pnob->bcrx_cq_tl = (pnob->bcrx_cq_tl + 1) % pnob->bcrx_cq_len;
+}
+
+static INLINE BESTATUS bni_process_mcc_cmpl(BE_MCC_OBJECT *pMccObj)
+{
+ return (be_mcc_process_cq(pMccObj, 1));
+}
+
+/* forward declarations of function prototypes */
+BESTATUS bni_init(PBE_CHIP_OBJECT);
+BESTATUS bni_create_mcc_rings(PBNI_NET_OBJECT pnob);
+extern void bni_destroy_netobj(PBNI_NET_OBJECT, SA_DEV *);
+void bni_cleanup(PBE_CHIP_OBJECT chipobj);
+
+BESTATUS bni_create_netobj(PBNI_NET_OBJECT, SA_DEV_BAR_LOCATIONS *, u32,
+ SA_DEV *, PBE_CHIP_OBJECT);
+
+BESTATUS bni_tx_pkt(PBNI_NET_OBJECT, PBNI_TX_FRAG_LIST, u32,
+ u32, u32, void *, u32);
+void bni_start_tx(PBNI_NET_OBJECT, u32);
+
+u32 bni_post_rx_buffs(PBNI_NET_OBJECT, PSA_LIST_ENTRY);
+BESTATUS bni_change_eqd(PBNI_NET_OBJECT, u32);
+
+PETH_TX_COMPL bni_get_tx_cmpl(PBNI_NET_OBJECT);
+PETH_RX_COMPL bni_get_ucrx_cmpl(PBNI_NET_OBJECT);
+PETH_RX_COMPL bni_get_bcrx_cmpl(PBNI_NET_OBJECT);
+void bni_notify_cmpl(PBNI_NET_OBJECT, int, int, int);
+
+void bni_enable_intr(PBNI_NET_OBJECT);
+void bni_enable_eq_intr(PBNI_NET_OBJECT);
+void bni_disable_intr(PBNI_NET_OBJECT);
+void bni_disable_eq_intr(PBNI_NET_OBJECT);
+
+u32 bni_get_isr(PBNI_NET_OBJECT);
+
+PEQ_ENTRY bni_get_event(PBNI_NET_OBJECT);
+void bni_notify_event(PBNI_NET_OBJECT, int, int);
+
+BESTATUS bni_get_uc_mac_adrr(PBNI_NET_OBJECT, u8, u8, u8 Pd,
+ PSA_MAC_ADDRESS macAddr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc);
+
+BESTATUS bni_set_uc_mac_adr(PBNI_NET_OBJECT, u8, u8, u8 Pd,
+ PSA_MAC_ADDRESS macAddr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc);
+
+BESTATUS bni_set_mc_filter(PBNI_NET_OBJECT pnob, u32 NumMac,
+ BOOLEAN Promiscuous,
+ PSA_MAC_ADDRESS macAddr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc);
+
+void bni_set_promisc(PBNI_NET_OBJECT pnob);
+void bni_reset_promisc(PBNI_NET_OBJECT pnob);
+BESTATUS bni_config_vlan(PBNI_NET_OBJECT pnob, u16 *VlanId,
+ u32 numVlans, MCC_WRB_CQE_CALLBACK cbf,
+ PVOID cbc, BOOLEAN Promiscuous);
+
+BESTATUS bni_get_stats(PBNI_NET_OBJECT pnob,
+ IOCTL_ETH_GET_STATISTICS *ioctl_va,
+ u64 ioctl_pa, MCC_WRB_CQE_CALLBACK cbf, PVOID cbc);
+
+BESTATUS bni_get_link_sts(PBNI_NET_OBJECT pnob,
+ PBE_LINK_STATUS be_link_sts,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc);
+BESTATUS bni_set_flow_ctll(PBE_FUNCTION_OBJECT pFnObj, boolean txfc_enable,
+ boolean rxfc_enable);
+BESTATUS bni_get_flow_ctl(PBE_FUNCTION_OBJECT pFnObj,
+ boolean *txfc_enable, boolean *rxfc_enable);
+u32 bni_process_rx_flush_cmpl(PBNI_NET_OBJECT pnob);
+
+#endif /* #ifndef _BNI_H_ */
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_init.c benet/linux-2.6.24.2/drivers/net/benet/be_init.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_init.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_init.c 2008-02-14 15:29:34.088482208 +0530
@@ -0,0 +1,1426 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/etherdevice.h>
+
+#include "be.h"
+
+#define DRVR_VERSION "1.0.688"
+
+static struct pci_device_id be_device_id_table[] = {
+ {0x19a2, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0}
+};
+
+MODULE_DEVICE_TABLE(pci, be_device_id_table);
+
+MODULE_VERSION(DRVR_VERSION);
+
+#define DRV_DESCRIPTION "ServerEngines BladeEngine Network Driver Version " \
+ DRVR_VERSION
+
+MODULE_DESCRIPTION(DRV_DESCRIPTION);
+MODULE_AUTHOR("ServerEngines");
+MODULE_LICENSE("GPL");
+
+unsigned int dbg_mask = (DL_ALWAYS | DL_ERR); /* always show error messages */
+unsigned int msix; /*By default */
+unsigned int ls_mss = (60 * 1024);
+
+unsigned int rxbuf_size = 2048; /*Size of Receive buffers posted */
+
+module_param(msix, uint, (0 | 1));
+module_param(dbg_mask, uint, (DL_ALWAYS | DL_ERR));
+module_param(rxbuf_size, uint, 0);
+
+MODULE_PARM_DESC(msix, "Use MSI-x interrupts");
+MODULE_PARM_DESC(dbg_mask, "Debug mask");
+MODULE_PARM_DESC(rxbuf_size, "Size of buffers to hold Rx data");
+
+static int be_probe(struct pci_dev *, const struct pci_device_id *);
+static void be_remove(struct pci_dev *);
+
+#ifdef CONFIG_PM
+static void be_pm_cleanup(PBE_ADAPTER, PBNI_NET_OBJECT,
+ struct net_device *);
+static void be_up(PBE_ADAPTER);
+static int be_resume(struct pci_dev *);
+
+static int be_suspend(struct pci_dev *, pm_message_t);
+#endif
+
+int be_mcc_init(PBE_ADAPTER adapter);
+void be_update_link_status(PBE_ADAPTER adapter);
+void be_link_status_async_callback(PVOID context, u32 event_code,
+ PVOID event);
+
+char be_drvr_ver[] = DRVR_VERSION;
+char be_fw_ver[32]; /* F/W version filled in by be_probe */
+
+char be_driver_name[] = "benet";
+
+static struct pci_driver be_driver = {
+ name:be_driver_name,
+ id_table:be_device_id_table,
+ probe:be_probe,
+#ifdef CONFIG_PM
+ suspend:be_suspend,
+ resume:be_resume,
+#endif
+ remove:be_remove
+};
+
+/*
+ * Number of entries in each queue.
+ */
+#define EVENT_Q_LEN 1024
+#define ETH_TXQ_LEN 2048
+#define ETH_TXCQ_LEN 1024
+#define ETH_RXQ_LEN 1024 /* Does not support any other value */
+#define ETH_UC_RXCQ_LEN 1024
+#define ETH_BC_RXCQ_LEN 256
+#define MCC_Q_LEN 64 /* total size not to exceed 8 pages */
+#define MCC_CQ_LEN 256
+
+PBE_ADAPTER be_adapter[MAX_BE_DEVICES];
+
+/*
+ * Intialize and register a network device for the NetObject.
+ */
+static int init_be_netdev(PBE_ADAPTER adapter, PBNI_NET_OBJECT pnob)
+{
+ struct net_device *netdev;
+ int ret = 0;
+ unsigned char *p;
+
+#ifdef CONFIG_PM
+ if (pm_resume) {
+ bni_set_uc_mac_adr(pnob, 0, 0, 0,
+ (PSA_MAC_ADDRESS) pnob->mac_address,
+ NULL, NULL);
+ return 0;
+ }
+#endif
+
+ /*
+ * Allocate netdev. No private data structure is
+ * allocated with netdev
+ */
+ netdev = alloc_etherdev(0);
+ if (netdev == NULL)
+ return -ENOMEM;
+
+ p = (u8 *) (pnob->mac_address);
+ /*
+ * Get MAC address from receive table
+ */
+ bni_get_uc_mac_adrr(pnob, 0, 0, OSM_NOB(pnob)->devno,
+ (PSA_MAC_ADDRESS) pnob->mac_address, NULL, NULL);
+
+ memcpy(netdev->dev_addr, pnob->mac_address, 6);
+ netdev->priv = pnob; /* We use the Net Object as private data */
+ netdev->init = &benet_probe;
+ /*
+ * Initialize to No Link. Link will be enabled during
+ * benet_open() or when physical Link is up
+ */
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
+ strcpy(netdev->name, "eth%d");
+
+ SET_NETDEV_DEV(netdev, &(adapter->pdev->dev));
+ ret = register_netdev(netdev);
+ if (ret != 0) {
+ TRACE(DL_INIT,
+ "Netdevice registration failed - Errno %d\n", ret);
+ free_netdev(netdev);
+ return (ret);
+ }
+ OSM_NOB(pnob)->os_handle = netdev;
+ return ret;
+}
+
+/* Initialize the pci_info structure for this function */
+static int init_pci_be_function(PBE_ADAPTER adapter, struct pci_dev *pdev)
+{
+ adapter->num_bars = 3;
+ /* CSR */
+ adapter->pci_bars[0].base_pa = pci_resource_start(pdev, 2);
+ adapter->pci_bars[0].base_va =
+ ioremap_nocache(adapter->pci_bars[0].base_pa,
+ pci_resource_len(pdev, 2));
+ if (adapter->pci_bars[0].base_va == NULL)
+ return -ENOMEM;
+ adapter->pci_bars[0].length = sizeof(BLADE_ENGINE_CSRMAP);
+ adapter->pci_bars[0].mem_or_io_mapped = SA_MEM_MAPPED;
+ adapter->pci_bars[0].type = SA_BAR_TYPE_CSR;
+
+ /* Door Bell */
+ adapter->pci_bars[1].base_pa = pci_resource_start(pdev, 4);
+ adapter->pci_bars[1].base_va =
+ ioremap_nocache(adapter->pci_bars[1].base_pa, (128 * 1024));
+ if (adapter->pci_bars[1].base_va == NULL) {
+ iounmap(adapter->pci_bars[0].base_va);
+ return -ENOMEM;
+ }
+ adapter->pci_bars[1].length = sizeof(PROTECTION_DOMAIN_DBMAP);
+ adapter->pci_bars[1].mem_or_io_mapped = SA_MEM_MAPPED;
+ adapter->pci_bars[1].type = SA_BAR_TYPE_PD;
+
+ /* PCI */
+ adapter->pci_bars[2].base_pa = pci_resource_start(pdev, 1);
+ adapter->pci_bars[2].length = pci_resource_len(pdev, 1);
+ adapter->pci_bars[2].base_va =
+ ioremap_nocache(adapter->pci_bars[2].base_pa,
+ adapter->pci_bars[2].length);
+ if (adapter->pci_bars[2].base_va == NULL) {
+ iounmap(adapter->pci_bars[0].base_va);
+ iounmap(adapter->pci_bars[1].base_va);
+ return -ENOMEM;
+ }
+ adapter->pci_bars[2].mem_or_io_mapped = SA_MEM_MAPPED;
+ adapter->pci_bars[2].type = SA_BAR_TYPE_PCI;
+
+ adapter->pdev = pdev;
+
+ return 0;
+}
+
+/*
+ * Enable MSIx and return 1 if successful. Else return 0
+ */
+int be_enable_msix(PBE_ADAPTER adapter)
+{
+ unsigned int i, ret;
+
+ if (!msix)
+ return 0;
+
+ adapter->msix_enabled = 1;
+
+ for (i = 0; i < BE_MAX_REQ_MSIX_VECTORS; i++) {
+ adapter->msix_entries[i].entry = i;
+ }
+
+ ret = pci_enable_msix(adapter->pdev,
+ adapter->msix_entries,
+ BE_MAX_REQ_MSIX_VECTORS);
+
+ if (ret) {
+ adapter->msix_enabled = 0;
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Module init entry point. Registers our our device and return.
+ * Our probe will be called if the device is found.
+ */
+
+static int __init be_init_module(void)
+{
+ int ret;
+
+ if ((rxbuf_size != 8192) && (rxbuf_size != 4096)
+ && (rxbuf_size != 2048)) {
+ printk(KERN_WARNING
+ "Unsupported receive buffer size (%d) requested\n",
+ rxbuf_size);
+ printk(KERN_WARNING
+ "Must be 2048 or 4096. Defaulting to 2048\n");
+ rxbuf_size = 2048;
+ }
+
+ ret = pci_register_driver(&be_driver);
+ TRACE(DL_INIT, "pci_module_init returned %d", ret);
+
+ return ret;
+}
+
+module_init(be_init_module);
+
+/*
+ * be_exit_module - Driver Exit Cleanup Routine
+ */
+static void __exit be_exit_module(void)
+{
+ TRACE(DL_SHUTDOWN, "%s Entry\n", __FUNCTION__);
+
+ pci_unregister_driver(&be_driver);
+}
+
+module_exit(be_exit_module);
+
+/*
+ * Registers ISR for BE. Uses MSIx interrupt if configured and requested.
+ * If not, uses INTx interrupt. Returns 0 for success and -1 for filure.
+ */
+int register_isr(PBE_ADAPTER adapter, PBNI_NET_OBJECT pnob)
+{
+ int msix_intr, r;
+ struct net_device *netdev = OSM_NOB(pnob)->os_handle;
+ u32 msix_ret = 0;
+
+ netdev->irq = adapter->pdev->irq;
+
+ msix_intr = 0;
+ msix_ret = be_enable_msix(adapter);
+ if (msix_ret) {
+ /* Register MSIx Interrupt handler */
+ r = request_irq(adapter->msix_entries[0].vector,
+ (void *)be_int, IRQF_SHARED,
+ netdev->name, netdev);
+ if (r) {
+ printk(KERN_WARNING
+ "MSIX Request IRQ failed - Errno %d\n", r);
+ } else {
+ msix_intr = 1;
+ TRACE(DL_INIT, "MSIx IRQ %d for %s\n",
+ adapter->msix_entries[0].vector,
+ netdev->name);
+ }
+ }
+ if (msix_intr == 0) {
+ /* request legacy INTx interrupt */
+ r = request_irq(netdev->irq, (void *)be_int,
+ IRQF_SHARED, netdev->name, netdev);
+ if (r) {
+ printk(KERN_ERR
+ "INTx Request IRQ failed - Errno %d\n", r);
+ return (-1);
+ }
+ TRACE(DL_INIT, "BE: INTx IRQ %d for %s\n",
+ netdev->irq, netdev->name);
+ }
+ return (0);
+}
+
+/*
+ * This function is called by the PCI sub-system when it finds a PCI
+ * device with dev/vendor IDs that match with one of our devices.
+ * All of the driver initialization is done in this function.
+ */
+static int be_probe(struct pci_dev *pdev,
+ const struct pci_device_id *pdev_id)
+{
+ int status = 0;
+ PBE_ADAPTER adapter = NULL;
+ u32 r;
+ u32 adapt_num = 0;
+ IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD ioctl_pload;
+ PBNI_NET_OBJECT pnob = NULL;
+
+ TRACE(DL_INFO, "Entering probe");
+ while (adapt_num < MAX_BE_DEVICES) {
+ if (!be_adapter[adapt_num])
+ break;
+ adapt_num++;
+ }
+
+ if (adapt_num == MAX_BE_DEVICES) {
+ printk(KERN_WARNING "Cannot support more than %d BE Adapters",
+ MAX_BE_DEVICES);
+ return -1;
+ }
+
+ status = pci_enable_device(pdev);
+ if (status) {
+ printk(KERN_ERR "pci_enable_device() for BE adapter %d failed",
+ adapt_num);
+ return status;
+ }
+
+ status = pci_request_regions(pdev, be_driver_name);
+ if (status)
+ return status;
+
+ pci_set_master(pdev);
+
+ adapter = (PBE_ADAPTER) kmalloc(sizeof(BE_ADAPTER), GFP_KERNEL);
+ if (adapter == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory for adapter structure\n");
+ pci_release_regions(pdev);
+ goto err_ret;
+ }
+
+ memset(adapter, 0, sizeof(BE_ADAPTER));
+
+ be_adapter[adapt_num] = adapter;
+ /*
+ * Adapative interrupt coalescing limits in usecs.
+ * should be a multiple of 8.
+ */
+ adapter->enable_aic = 1;
+ adapter->max_eqd = MAX_EQD;
+ adapter->min_eqd = 0;
+ adapter->cur_eqd = 0; /* start with no EQ delay */
+ r = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
+ if (!r) {
+ /* Device is DAC Capable. */
+ adapter->dma_64bit_cap = TRUE;
+ } else {
+ adapter->dma_64bit_cap = FALSE;
+ r = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
+ if (r) {
+ printk(KERN_ERR "Could not set PCI DMA Mask\n");
+ return r;
+ }
+ }
+
+ status = init_pci_be_function(adapter, pdev);
+ if (status < 0) {
+ printk(KERN_ERR "Failed to map PCI BARS\n");
+ status = -ENOMEM;
+ goto cleanup1;
+ }
+
+ (void)sa_trace_set_level(dbg_mask);
+
+ r = bni_init(&adapter->chip_object);
+ if (r != 0) {
+ printk("bni_init() failed - Error %d\n", r);
+ goto cleanup1;
+ }
+
+ /* Allocate Memory for getting the Link status */
+ adapter->be_link_sts = (PBE_LINK_STATUS)
+ kmalloc(sizeof(BE_LINK_STATUS), GFP_KERNEL);
+ if (adapter->be_link_sts == NULL) {
+ printk("Memory allocation for link status buffer failed\n");
+ goto cleanup1;
+ }
+ spin_lock_init(&adapter->txq_lock);
+
+ status = be_prepare_interface(adapter);
+ if (status < 0) {
+ goto cleanup1;
+ }
+ pnob = adapter->net_obj;
+
+ /* if the rx_frag size if 2K, one page is shared as two RX frags */
+ OSM_NOB(pnob)->rx_pg_shared =
+ (pnob->rx_buf_size <= PAGE_SIZE / 2) ? TRUE : FALSE;
+ if (pnob->rx_buf_size != rxbuf_size) {
+ printk(KERN_WARNING
+ "Could not set Rx buffer size to %d. Using %d\n",
+ rxbuf_size, pnob->rx_buf_size);
+ rxbuf_size = pnob->rx_buf_size;
+ }
+
+ tasklet_init(&(adapter->sts_handler), osm_process_sts,
+ (unsigned long)adapter);
+ adapter->tasklet_started = 1; /* indication to cleanup */
+ spin_lock_init(&(adapter->int_lock));
+
+ if (register_isr(adapter, pnob) != 0)
+ goto cleanup;
+
+ adapter->isr_registered = 1;
+ adapter->rx_csum = 1; /* enable RX checksum check */
+#ifdef RX_PKT_COALESCE
+ adapter->max_rx_coal = MAX_COALESCE_FRAGS;
+#endif
+
+ /* print the version numbers */
+ memset(&ioctl_pload, 0,
+ sizeof(IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD));
+ printk(KERN_INFO "BladeEngine Driver version:%s. "
+ "Copyright ServerEngines, Corporation 2005 - 2008\n",
+ be_drvr_ver);
+ if (be_function_get_fw_version(&pnob->fn_obj, &ioctl_pload, NULL,
+ NULL) == BE_SUCCESS) {
+ adapter->be_fw_ver =
+ simple_strtoul(ioctl_pload.firmware_version_string + 4,
+ NULL, 10);
+ strncpy(be_fw_ver, ioctl_pload.firmware_version_string, 32);
+ printk(KERN_INFO "BladeEngine Firmware Version:%s\n",
+ ioctl_pload.firmware_version_string);
+ } else {
+ printk(KERN_WARNING "Unable to get BE Firmware Version\n");
+ }
+
+ sema_init(&adapter->get_eth_stat_sem, 0);
+
+ adapter->ctxt = (be_timer_ctxt_t *)
+ kmalloc(sizeof(be_timer_ctxt_t), GFP_KERNEL);
+
+ init_timer(&adapter->ctxt->get_stats_timer);
+ atomic_set(&adapter->ctxt->get_stat_flag, 0);
+ adapter->ctxt->get_stats_timer.function = &get_stats_timer_handler;
+
+ status = be_mcc_init(adapter);
+ if (status < 0) {
+ goto cleanup;
+ }
+
+ be_update_link_status(adapter);
+
+ /* Register async call back function to handle link status updates */
+ if (be_mcc_add_async_event_callback(&adapter->net_obj->mcc_q_obj,
+ be_link_status_async_callback,
+ (PVOID) adapter) != BE_SUCCESS) {
+ printk(KERN_WARNING "add_async_event_callback failed");
+ printk(KERN_WARNING
+ "Link status changes may not be reflected\n");
+ }
+
+ /* Enable ChipInterrupt and EQ Interrupt */
+ bni_enable_intr(adapter->net_obj);
+ enable_eq_intr(adapter->net_obj);
+ adapter->dev_state = BE_DEV_STATE_INIT;
+ return 0; /* successful return */
+
+cleanup1:
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ be_adapter[adapt_num] = NULL;
+ kfree(adapter);
+ goto err_ret;
+
+cleanup:
+ be_remove(pdev);
+
+err_ret:
+ printk(KERN_ERR "BladeEngine init failed\n");
+ return -ENOMEM;
+}
+
+/*
+ * Get the current link status and print the status on console
+ */
+void be_update_link_status(PBE_ADAPTER adapter)
+{
+ int status;
+ PBNI_NET_OBJECT pnob = adapter->net_obj;
+
+ status = bni_get_link_sts(pnob, adapter->be_link_sts, NULL, NULL);
+
+ if (status == BE_SUCCESS) {
+ if (adapter->be_link_sts->mac0_speed &&
+ adapter->be_link_sts->mac0_duplex)
+ adapter->port0_link_sts = BE_PORT_LINK_UP;
+ else
+ adapter->port0_link_sts = BE_PORT_LINK_DOWN;
+
+ if (adapter->be_link_sts->mac1_speed &&
+ adapter->be_link_sts->mac1_duplex)
+ adapter->port1_link_sts = BE_PORT_LINK_UP;
+ else
+ adapter->port1_link_sts = BE_PORT_LINK_DOWN;
+
+ printk(KERN_INFO "Link Properties for %s:\n",
+ ((struct net_device *)(OSM_NOB(pnob)->os_handle))->name);
+ be_print_link_info(adapter->be_link_sts);
+ return;
+ }
+ printk(KERN_WARNING "Could not get link status for %s\n",
+ ((struct net_device *)(OSM_NOB(pnob)->os_handle))->name);
+ return;
+}
+
+/* This function handles async callback for link status */
+void be_link_status_async_callback(PVOID context, u32 event_code,
+ PVOID event)
+{
+ ASYNC_EVENT_LINK_STATE *link_status = (ASYNC_EVENT_LINK_STATE *) event;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) context;
+ BOOLEAN link_enable = FALSE;
+ PBNI_NET_OBJECT pnob;
+ ASYNC_EVENT_TRAILER *async_trailer;
+ struct net_device *netdev;
+
+ if (event_code != ASYNC_EVENT_CODE_LINK_STATE) {
+ /* Not our event to handle */
+ return;
+ }
+ async_trailer = (ASYNC_EVENT_TRAILER *) ((u8 *) event +
+ sizeof(MCC_CQ_ENTRY) - sizeof (ASYNC_EVENT_TRAILER));
+
+ SA_ASSERT(async_trailer->event_code == ASYNC_EVENT_CODE_LINK_STATE);
+
+ pnob = adapter->net_obj;
+ SA_ASSERT(pnob);
+ netdev = (struct net_device *)OSM_NOB(pnob)->os_handle;
+ SA_ASSERT(netdev);
+
+ /* Determine if this event is a switch VLD or a physical link event */
+ if (async_trailer->event_type == NTWK_LINK_TYPE_VIRTUAL) {
+ adapter->be_stat.bes_link_change_virtual++;
+ if (adapter->be_link_sts->active_port !=
+ link_status->active_port) {
+ printk("Active port changed due to VLD on switch\n");
+ } else {
+ /* Link of atleast one of the ports changed */
+ printk("Link status update\n");
+ }
+
+ } else {
+ adapter->be_stat.bes_link_change_physical++;
+ if (adapter->be_link_sts->active_port !=
+ link_status->active_port) {
+ printk("Active port changed due to port link status"
+ " change\n");
+ } else {
+ /* Link of atleast one of the ports changed */
+ printk("Link status update\n");
+ }
+ }
+
+ /* Clear memory of adapter->be_link_sts */
+ memset(adapter->be_link_sts, 0, sizeof(adapter->be_link_sts));
+
+ if ((link_status->port0_link_status == ASYNC_EVENT_LINK_UP) ||
+ (link_status->port1_link_status == ASYNC_EVENT_LINK_UP)) {
+ if ((adapter->port0_link_sts == BE_PORT_LINK_DOWN) &&
+ (adapter->port1_link_sts == BE_PORT_LINK_DOWN)) {
+ /*
+ * Earlier both the ports are down
+ * So link is up
+ */
+ link_enable = TRUE;
+ }
+
+ if (link_status->port0_link_status == ASYNC_EVENT_LINK_UP) {
+ adapter->port0_link_sts = BE_PORT_LINK_UP;
+ adapter->be_link_sts->mac0_duplex =
+ link_status->port0_duplex;
+ adapter->be_link_sts->mac0_speed =
+ link_status->port0_speed;
+ if (link_status->active_port == NTWK_PORT_A)
+ adapter->be_link_sts->active_port = 0;
+ } else
+ adapter->port0_link_sts = BE_PORT_LINK_DOWN;
+
+ if (link_status->port1_link_status == ASYNC_EVENT_LINK_UP) {
+ adapter->port1_link_sts = BE_PORT_LINK_UP;
+ adapter->be_link_sts->mac1_duplex =
+ link_status->port1_duplex;
+ adapter->be_link_sts->mac1_speed =
+ link_status->port1_speed;
+ if (link_status->active_port == NTWK_PORT_B)
+ adapter->be_link_sts->active_port = 1;
+ } else
+ adapter->port1_link_sts = BE_PORT_LINK_DOWN;
+
+ printk(KERN_INFO "Link Properties for %s:\n", netdev->name);
+ be_print_link_info(adapter->be_link_sts);
+
+ if (!link_enable)
+ return;
+ /*
+ * Both ports were down previously, but atleast one of
+ * them has come up if this netdevice's carrier is not up,
+ * then indicate to stack
+ */
+ if (!netif_carrier_ok(netdev)) {
+ netif_start_queue(netdev);
+ netif_carrier_on(netdev);
+ }
+ return;
+ }
+
+ /* Now both the ports are down. Tell the stack about it */
+ printk(KERN_INFO "Both ports are down\n");
+
+ adapter->port0_link_sts = BE_PORT_LINK_DOWN;
+ adapter->port1_link_sts = BE_PORT_LINK_DOWN;
+
+ /* if this netdevice's carrier is not down, then indicate to stack */
+ if (netif_carrier_ok(netdev)) {
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+ }
+ return;
+}
+
+/* Function to initialize MCC rings */
+int be_mcc_init(PBE_ADAPTER adapter)
+{
+ u32 n, r, m;
+ PBNI_NET_OBJECT pnob;
+
+ pnob = adapter->net_obj;
+ if (!pm_resume) {
+ be_init_procfs(adapter);
+ /*
+ * Create the MCC ring so that all further communication with
+ * MCC can go thru the ring. we do this at the end since
+ * we do not want to be dealing with interrupts until the
+ * initialization is complete.
+ */
+ pnob->mcc_q_len = MCC_Q_LEN;
+ n = pnob->mcc_q_len * sizeof(MCC_WRB);
+ n = MAX(n, PAGE_SIZE);
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->mcc_q =
+ (PMCC_WRB) __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->mcc_q == NULL)
+ goto cleanup;
+ pnob->mcc_q_pages = m;
+ pnob->mcc_q_pa = virt_to_phys(pnob->mcc_q);
+ pnob->mcc_q_pa = cpu_to_le64(pnob->mcc_q_pa);
+ /*
+ * space for MCC WRB context
+ */
+ pnob->mcc_wrb_ctxtLen = MCC_Q_LEN;
+ n = pnob->mcc_wrb_ctxtLen * sizeof(BE_MCC_WRB_CONTEXT);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->mcc_wrb_ctxt =
+ (PVOID) __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->mcc_wrb_ctxt == NULL)
+ goto cleanup;
+ pnob->mcc_wrb_ctxt_pages = m;
+ /*
+ * Space for MCC compl. ring
+ */
+ pnob->mcc_cq_len = MCC_CQ_LEN;
+ n = pnob->mcc_cq_len * sizeof(MCC_CQ_ENTRY);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->mcc_cq =
+ (PMCC_CQ_ENTRY) __get_free_pages(GFP_KERNEL,
+ sa_log2(m));
+ if (pnob->mcc_cq == NULL)
+ goto cleanup;
+ pnob->mcc_cq_pa = virt_to_phys(pnob->mcc_cq);
+ pnob->mcc_cq_pa = cpu_to_le64(pnob->mcc_cq_pa);
+ pnob->mcc_cq_pages = m;
+
+ }
+ memset(pnob->mcc_q, 0, pnob->mcc_q_pages * PAGE_SIZE);
+ pnob->mcc_q_hd = 0;
+
+ memset(pnob->mcc_wrb_ctxt, 0,
+ pnob->mcc_wrb_ctxt_pages * PAGE_SIZE);
+
+ memset(pnob->mcc_cq, 0, pnob->mcc_cq_pages * PAGE_SIZE);
+ pnob->mcc_cq_tl = 0;
+
+ r = bni_create_mcc_rings(adapter->net_obj);
+ if (r != BE_SUCCESS)
+ goto cleanup;
+
+ return 0;
+cleanup:
+ TRACE(DL_INIT, "Failed to create MCC rings\n");
+ return -ENOMEM;
+
+}
+
+static void be_remove(struct pci_dev *pdev)
+{
+ PBNI_NET_OBJECT pnob = NULL;
+ PBE_ADAPTER adapter = NULL;
+ int adapt_num = 0;
+ int i;
+
+ while (adapt_num < MAX_BE_DEVICES) {
+ if ((be_adapter[adapt_num]) &&
+ (be_adapter[adapt_num]->pdev == pdev)) {
+ adapter = be_adapter[adapt_num];
+ pnob = (BNI_NET_OBJECT *) adapter->net_obj;
+ break;
+ }
+ adapt_num++;
+ }
+
+ SA_ASSERT(adapter);
+
+ flush_scheduled_work();
+
+ /* Unregister async call back function for link status updates */
+ if (be_mcc_add_async_event_callback(&pnob->mcc_q_obj,
+ NULL, NULL) != BE_SUCCESS)
+ printk(KERN_WARNING "Unregister async callback for link "
+ "status updates failed.\n");
+
+ cleanup_netobject(adapter->net_obj);
+
+ be_cleanup_procfs(adapter);
+
+ bni_cleanup(&adapter->chip_object);
+
+ for (i = 0; i < adapter->num_bars; i++) {
+ if (adapter->pci_bars[i].base_va) {
+ iounmap(adapter->pci_bars[i].base_va);
+ }
+ }
+
+ pci_release_regions(adapter->pdev);
+ pci_disable_device(adapter->pdev);
+
+ /* Free Link status structure */
+ if (adapter->be_link_sts) {
+ kfree(adapter->be_link_sts);
+ }
+
+ if (adapter->eth_statsp) {
+ kfree(adapter->eth_statsp);
+ }
+
+ del_timer_sync(&adapter->ctxt->get_stats_timer);
+
+ if (adapter->ctxt) {
+ kfree(adapter->ctxt);
+ }
+
+ be_adapter[adapt_num] = NULL;
+ kfree(adapter);
+}
+
+static int be_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+#ifdef CONFIG_PM
+ struct net_device *netdev = NULL;
+ PBNI_NET_OBJECT pnob = NULL;
+ PBE_ADAPTER adapter = NULL;
+
+ int adapt_num = 0;
+ while (adapt_num < MAX_BE_DEVICES) {
+ if (be_adapter[adapt_num] &&
+ (be_adapter[adapt_num]->pdev == pdev)) {
+ adapter = be_adapter[adapt_num];
+ pnob = (BNI_NET_OBJECT *) adapter->netdevp->priv;
+ netdev = adapter->netdevp;
+ netif_device_detach(netdev);
+ break;
+ }
+ adapt_num++;
+ }
+ SA_ASSERT(adapter);
+
+ netif_device_detach(netdev);
+ if (netif_running(netdev))
+ be_pm_cleanup(adapter, pnob, netdev);
+
+ pci_enable_wake(pdev, 3, 1);
+ pci_enable_wake(pdev, 4, 1); /* D3 Cold = 4 */
+ pci_save_state(pdev);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+#endif
+ return 0;
+}
+
+static int be_resume(struct pci_dev *pdev)
+{
+#ifdef CONFIG_PM
+ int status = 0;
+ struct net_device *netdev = NULL;
+ PBNI_NET_OBJECT pnob = NULL;
+ PBE_ADAPTER adapter = NULL;
+ u32 adapt_num = 0;
+
+ pm_resume = 1;
+ while (adapt_num < MAX_BE_DEVICES) {
+ if (be_adapter[adapt_num] &&
+ (be_adapter[adapt_num]->pdev == pdev)) {
+ adapter = be_adapter[adapt_num];
+ pnob = (BNI_NET_OBJECT *) adapter->netdevp->priv;
+ netdev = adapter->netdevp;
+ netif_device_detach(netdev);
+ break;
+ }
+ adapt_num++;
+ }
+ SA_ASSERT(adapter);
+
+ status = pci_enable_device(pdev);
+ if (status)
+ return status;
+
+ pci_set_power_state(pdev, 0);
+ pci_restore_state(pdev);
+ pci_enable_wake(pdev, 3, 0);
+ pci_enable_wake(pdev, 4, 0); /* 4 is D3 cold */
+
+ netif_carrier_on(netdev);
+ netif_start_queue(netdev);
+
+ if (netif_running(netdev)) {
+ status = be_prepare_interface(adapter);
+
+ if (status < 0) {
+ return (status);
+ }
+ status = be_mcc_init(adapter);
+ if (status < 0) {
+ printk(KERN_ERR "be_mcc_init failed\n");
+ return (status);
+ }
+ be_update_link_status(adapter);
+ /*
+ * Register async call back function to handle link
+ * status updates
+ */
+ if (be_mcc_add_async_event_callback(
+ &adapter->net_obj->mcc_q_obj,
+ be_link_status_async_callback,
+ (PVOID) adapter) != BE_SUCCESS) {
+ printk(KERN_WARNING "add_async_event_callback failed");
+ printk(KERN_WARNING
+ "Link status changes may not be reflected\n");
+ }
+ bni_enable_intr(pnob);
+ enable_eq_intr(pnob);
+ be_up(adapter);
+ }
+ netif_device_attach(netdev);
+ pm_resume = 0;
+#endif
+ return 0;
+
+}
+
+#ifdef CONFIG_PM
+static void be_pm_cleanup(PBE_ADAPTER adapter,
+ PBNI_NET_OBJECT pnob, struct net_device *netdev)
+{
+ u32 i;
+
+ netif_carrier_off(netdev);
+ netif_stop_queue(netdev);
+
+ wait_nic_tx_cmpl(pnob);
+ disable_eq_intr(pnob);
+ if (adapter->tasklet_started) {
+ tasklet_kill(&(adapter->sts_handler));
+ adapter->isr_registered = 0;
+ }
+ if (adapter->isr_registered) {
+ free_irq(netdev->irq, netdev);
+ adapter->tasklet_started = 0;
+ }
+ /* Disable chip interrupt */
+ bni_disable_intr(pnob);
+ bni_destroy_netobj(pnob, &adapter->sa_device);
+
+ if (pnob->rx_ctxt) {
+ BE_RX_PAGE_INFO *rx_page_info;
+
+ /*
+ * go through RX context array and free
+ * data buffs
+ */
+ for (i = 0; i < pnob->rx_q_len; i++) {
+ rx_page_info = &(OSM_NOB(pnob)->rx_page_info[i]);
+ if ((OSM_NOB(pnob)->rx_pg_shared == FALSE) ||
+ (rx_page_info->page_offset))
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info,
+ bus),
+ pnob->rx_buf_size,
+ PCI_DMA_FROMDEVICE);
+ if (rx_page_info->page)
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ }
+ OSM_NOB(pnob)->rx_pg_info_hd = 0;
+ }
+
+}
+
+static void be_up(PBE_ADAPTER adapter)
+{
+ PBNI_NET_OBJECT pnob = adapter->net_obj;
+
+ if (OSM_NOB(pnob)->num_vlans != 0)
+ bni_config_vlan(pnob, OSM_NOB(pnob)->vlan_tag,
+ OSM_NOB(pnob)->num_vlans, NULL, NULL, 0);
+
+}
+#endif
+
+static int be_setup_tx_res(PBNI_NET_OBJECT NetObject)
+{
+ int n;
+
+ n = NetObject->tx_q_len * sizeof(PVOID *);
+ if (!pm_resume) {
+ NetObject->tx_ctxt = (PVOID *) kmalloc(n, GFP_KERNEL);
+
+ if (NetObject->tx_ctxt == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory for tx_ctxt\n");
+ return -1;
+ }
+ }
+ memset(NetObject->tx_ctxt, 0, n);
+ return 0;
+}
+
+static int be_setup_rx_res(PBNI_NET_OBJECT NetObject)
+{
+ int n;
+
+ if (!pm_resume) {
+ n = (NetObject->rx_q_len * sizeof(PVOID));
+ NetObject->rx_ctxt = kmalloc(n, GFP_KERNEL);
+ if (NetObject->rx_ctxt == NULL) {
+ TRACE(DL_INIT, "Failed to alloc memory for rx_ctxt\n");
+ return -1;
+ }
+
+ n = (NetObject->rx_q_len * sizeof(BE_RX_PAGE_INFO));
+ OSM_NOB(NetObject)->rx_page_info = kmalloc(n, GFP_KERNEL);
+ if (OSM_NOB(NetObject)->rx_page_info == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory for receive page info\n");
+ kfree(NetObject->rx_ctxt);
+ return -1;
+ }
+ }
+
+ memset(NetObject->rx_ctxt, 0, NetObject->rx_q_len * sizeof(PVOID));
+ memset(OSM_NOB(NetObject)->rx_page_info, 0,
+ NetObject->rx_q_len * sizeof(BE_RX_PAGE_INFO));
+ OSM_NOB(NetObject)->rx_pg_info_hd = 0;
+ NetObject->rx_q_hd = 0;
+ NetObject->rx_q_posted = 0;
+ /* post ETH RX buffers */
+ post_eth_rx_buffs(NetObject);
+
+ return 0;
+}
+
+/*
+ * free all resources associated with a NetObject
+ * Called at the time of module cleanup as well a any error during
+ * module init. Some resources may be partially allocated in a NetObj.
+ */
+void cleanup_netobject(PBNI_NET_OBJECT pnob)
+{
+ struct net_device *netdev;
+ PBE_ADAPTER adapter;
+ struct sk_buff *skb;
+ int i;
+
+ SA_ASSERT(pnob);
+ netdev = (struct net_device *)OSM_NOB(pnob)->os_handle;
+ SA_ASSERT(netdev);
+ adapter = (PBE_ADAPTER) OSM_NOB(pnob)->adapter;
+ SA_ASSERT(adapter);
+
+ /* Only if this netdev is up */
+ if (netif_running(netdev)) {
+ /*
+ * Let us stop the dev queue for the
+ * interface associated with this netobj.
+ */
+ netif_stop_queue(netdev);
+
+ /* Wait until no more pending transmits */
+ wait_nic_tx_cmpl(pnob);
+
+ /* Disable this EQ's interrupt */
+ disable_eq_intr(pnob);
+ }
+
+ if ((adapter->isr_registered) & (adapter->msix_enabled))
+ free_irq(adapter->msix_entries[0].vector, netdev);
+ else if ((adapter->isr_registered) & !(adapter->msix_enabled))
+ free_irq(netdev->irq, netdev);
+
+ adapter->isr_registered = 0;
+ if (adapter->msix_enabled) {
+ pci_disable_msix(adapter->pdev);
+ adapter->msix_enabled = 0;
+ }
+ if (adapter->tasklet_started) {
+ tasklet_kill(&(adapter->sts_handler));
+ adapter->tasklet_started = 0;
+ }
+ /* Disable chip interrupt */
+ bni_disable_intr(pnob);
+
+ unregister_netdev(netdev);
+ /* memory associted with netdev is freed by OS */
+
+ /* Destroy Net Object */
+ bni_destroy_netobj(pnob, &adapter->sa_device);
+
+ adapter->net_obj = NULL;
+ adapter->netdevp = NULL;
+
+ /* free all the memory allocated for the queues */
+
+ if (pnob->mcc_q) {
+ free_pages((unsigned long)pnob->mcc_q,
+ sa_log2(pnob->mcc_q_pages));
+ }
+
+ if (pnob->mcc_wrb_ctxt) {
+ free_pages((unsigned long)pnob->mcc_wrb_ctxt,
+ sa_log2(pnob->mcc_wrb_ctxt_pages));
+ }
+
+ if (pnob->mcc_cq) {
+ free_pages((unsigned long)pnob->mcc_cq,
+ sa_log2(pnob->mcc_cq_pages));
+ }
+
+ if (pnob->event_q) {
+ free_pages((unsigned long)pnob->event_q,
+ sa_log2(pnob->event_q_pages));
+ }
+
+ if (pnob->tx_cq) {
+ free_pages((unsigned long)pnob->tx_cq,
+ sa_log2(pnob->tx_cq_pages));
+ }
+
+ if (pnob->tx_q) {
+ free_pages((unsigned long)pnob->tx_q,
+ sa_log2(pnob->tx_q_pages));
+ }
+
+ if (pnob->bcrx_cq) {
+ free_pages((unsigned long)pnob->bcrx_cq,
+ sa_log2(pnob->bcrx_cq_pages));
+ }
+
+ if (pnob->rx_q) {
+ free_pages((unsigned long)pnob->rx_q,
+ sa_log2(pnob->rx_q_pages));
+ }
+
+ if (pnob->ucrx_cq) {
+ free_pages((unsigned long)pnob->ucrx_cq,
+ sa_log2(pnob->ucrx_cq_pages));
+ }
+
+ /* free all allocated memory stored in the net object */
+ if (pnob->rx_ctxt) {
+ BE_RX_PAGE_INFO *rx_page_info;
+ /*
+ * go through RX context array and free data buffs
+ */
+ for (i = 0; i < pnob->rx_q_len; i++) {
+ rx_page_info = &(OSM_NOB(pnob)->rx_page_info[i]);
+ if ((OSM_NOB(pnob)->rx_pg_shared == FALSE) ||
+ (rx_page_info->page_offset)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus),
+ pnob->rx_buf_size, PCI_DMA_FROMDEVICE);
+ }
+ if (rx_page_info->page) {
+ put_page(rx_page_info->page);
+ }
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ }
+ OSM_NOB(pnob)->rx_pg_info_hd = 0;
+ kfree(OSM_NOB(pnob)->rx_page_info);
+ kfree(pnob->rx_ctxt);
+ }
+
+ if (pnob->tx_ctxt) {
+ for (i = 0; i < pnob->tx_q_len; i++) {
+ skb = (struct sk_buff *)pnob->tx_ctxt[i];
+ if (skb) {
+ kfree_skb(skb);
+ }
+ }
+ kfree(pnob->tx_ctxt);
+ }
+
+ if (pnob->mb_ptr) {
+ kfree(pnob->mb_ptr);
+ }
+
+ if (OSM_NOB(pnob)) {
+ kfree(OSM_NOB(pnob));
+ }
+
+ /* finally, free the net object itself */
+ kfree(pnob);
+
+}
+
+/*
+ * this function creates a NetObject with a set of Eth rings.
+ */
+int be_prepare_interface(PBE_ADAPTER adapter)
+{
+ struct net_device *netdev = NULL;
+ PBNI_NET_OBJECT pnob = NULL;
+ SA_DEV_BAR_LOCATIONS pci_bars[3];
+ int status;
+ u32 n, m;
+ PVOID p;
+
+ if (!pm_resume) {
+ /*Normal Mode */
+ memcpy(pci_bars, adapter->pci_bars,
+ sizeof(adapter->pci_bars));
+
+ pnob = (PBNI_NET_OBJECT)
+ kmalloc(sizeof(BNI_NET_OBJECT), GFP_KERNEL);
+
+ if (pnob == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory for NetObject\n");
+ goto err_ret1;
+ }
+ memset(pnob, 0, sizeof(BNI_NET_OBJECT));
+ TRACE(DL_INIT, "Done with net obj alloc\n");
+
+ pnob->osm_netobj = (linux_net_object_t *)
+ kmalloc(sizeof(linux_net_object_t), GFP_KERNEL);
+ if (pnob->osm_netobj == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory OSM NetObject\n");
+ kfree(pnob);
+ goto err_ret1;
+ }
+ memset(pnob->osm_netobj, 0, sizeof(linux_net_object_t));
+
+ OSM_NOB(pnob)->devno = 0;
+ OSM_NOB(pnob)->adapter = adapter;
+
+ /* Mail box sgl */
+ pnob->mb_sgl.length = sizeof(MCC_MAILBOX);
+ p = kmalloc(pnob->mb_sgl.length + 16, GFP_KERNEL);
+ if (p == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc mem for MCC_MAILBOX\n");
+ goto err_ret1;
+ }
+ /* Mailbox pointer needs to be 16 byte aligned */
+ pnob->mb_ptr = p;
+ p = (PVOID) ((unsigned long)(p + 15) & ~0xf);
+ pnob->mb_sgl.va = (void *)p;
+ pnob->mb_sgl.pa = virt_to_phys(p);
+ pnob->mb_sgl.pa = cpu_to_le64(pnob->mb_sgl.pa);
+ /*
+ * Event queue
+ */
+ pnob->event_q_len = EVENT_Q_LEN;
+ n = pnob->event_q_len * sizeof(EQ_ENTRY);
+ n = MAX(n, (2 * PAGE_SIZE));
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->event_q = (PEQ_ENTRY)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->event_q == NULL)
+ goto err_ret1;
+ pnob->event_q_pa = virt_to_phys(pnob->event_q);
+ pnob->event_q_pa = cpu_to_le64(pnob->event_q_pa);
+ pnob->event_q_pages = m;
+ /*
+ * Eth TX queue
+ */
+ pnob->tx_q_len = ETH_TXQ_LEN;
+ pnob->tx_q_port = 0; /* No port binding */
+ n = pnob->tx_q_len * sizeof(ETH_WRB);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->tx_q = (PETH_WRB)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->tx_q == NULL)
+ goto err_ret1;
+ pnob->tx_q_pa = virt_to_phys(pnob->tx_q);
+ pnob->tx_q_pa = cpu_to_le64(pnob->tx_q_pa);
+ pnob->tx_q_pages = m;
+ /*
+ * Eth TX Compl queue
+ */
+ pnob->txcq_len = ETH_TXCQ_LEN;
+ n = pnob->txcq_len * sizeof(ETH_TX_COMPL);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->tx_cq = (PETH_TX_COMPL)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->tx_cq == NULL)
+ goto err_ret1;
+ pnob->tx_cq_pa = virt_to_phys(pnob->tx_cq);
+ pnob->tx_cq_pa = cpu_to_le64(pnob->tx_cq_pa);
+ pnob->tx_cq_pages = m;
+ /*
+ * Eth RX queue
+ */
+ pnob->rx_q_len = ETH_RXQ_LEN;
+ n = pnob->rx_q_len * sizeof(ETH_RX_D);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->rx_q = (PETH_RX_D)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->rx_q == NULL)
+ goto err_ret1;
+ pnob->rx_q_pa = virt_to_phys(pnob->rx_q);
+ pnob->rx_q_pa = cpu_to_le64(pnob->rx_q_pa);
+ pnob->rx_q_pages = m;
+ /*
+ * Eth Unicast RX Compl queue
+ */
+ pnob->ucrx_cq_len = ETH_UC_RXCQ_LEN;
+ n = pnob->ucrx_cq_len * sizeof(ETH_RX_COMPL);
+ n = MAX(n, PAGE_SIZE); /* Need to allocate alteast one page */
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->ucrx_cq = (PETH_RX_COMPL)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->ucrx_cq == NULL)
+ goto err_ret1;
+ pnob->ucrx_cq_pa = virt_to_phys(pnob->ucrx_cq);
+ pnob->ucrx_cq_pa = cpu_to_le64(pnob->ucrx_cq_pa);
+ pnob->ucrx_cq_pages = m;
+ /*
+ * Eth Broadcast RX Compl queue
+ */
+ pnob->bcrx_cq_len = ETH_BC_RXCQ_LEN;
+ n = pnob->bcrx_cq_len * sizeof(ETH_RX_COMPL);
+ n = MAX(n, PAGE_SIZE);
+ /* Get number of pages */
+ m = (n + (PAGE_SIZE - 1)) / (PAGE_SIZE);
+ pnob->bcrx_cq = (PETH_RX_COMPL)
+ __get_free_pages(GFP_KERNEL, sa_log2(m));
+ if (pnob->bcrx_cq == NULL)
+ goto err_ret1;
+ pnob->bcrx_cq_pa = virt_to_phys(pnob->bcrx_cq);
+ pnob->bcrx_cq_pa = cpu_to_le64(pnob->bcrx_cq_pa);
+ pnob->bcrx_cq_pages = m;
+
+ /* Allocate DMA'ble Memory for IOCTL_ETH_GET_STATISTICS */
+ adapter->eth_statsp = (IOCTL_ETH_GET_STATISTICS *)
+ kmalloc(sizeof(IOCTL_ETH_GET_STATISTICS), GFP_KERNEL);
+ if (adapter->eth_statsp == NULL) {
+ TRACE(DL_INIT,
+ "Failed to alloc memory for Eth stats\n");
+ goto err_ret1;
+ }
+ pnob->rx_buf_size = rxbuf_size;
+ /*
+ * Set dev close to be TRUE. This will be enabled on dev open
+ */
+ adapter->dev_state = BE_DEV_STATE_NONE;
+ } else {
+ pnob = adapter->net_obj;
+ memcpy(pci_bars, adapter->pci_bars,
+ sizeof(adapter->pci_bars));
+ }
+
+ memset(pnob->event_q, 0, pnob->event_q_pages * PAGE_SIZE);
+ pnob->event_q_tl = 0;
+
+ memset(pnob->tx_q, 0, pnob->tx_q_pages * PAGE_SIZE);
+ pnob->tx_q_hd = 0;
+ pnob->tx_q_tl = 0;
+
+ memset(pnob->tx_cq, 0, pnob->tx_cq_pages * PAGE_SIZE);
+ pnob->tx_cq_tl = 0;
+
+ memset(pnob->rx_q, 0, pnob->rx_q_pages * PAGE_SIZE);
+
+ memset(pnob->ucrx_cq, 0, pnob->ucrx_cq_pages * PAGE_SIZE);
+ pnob->ucrx_cq_tl = 0;
+
+ memset(pnob->bcrx_cq, 0, pnob->bcrx_cq_pages * PAGE_SIZE);
+ pnob->bcrx_cq_tl = 0;
+ n = bni_create_netobj(pnob, pci_bars, adapter->num_bars,
+ &adapter->sa_device,
+ &adapter->chip_object);
+ if (n != BE_SUCCESS) {
+ TRACE(DL_ERROR, "bni_create_netobj failed - returned %x", n);
+ goto err_ret1;
+ }
+ TRACE(DL_INIT, "Creation of NetObject Done");
+
+ status = init_be_netdev(adapter, pnob);
+ if (status < 0)
+ goto err_ret;
+ netdev = OSM_NOB(pnob)->os_handle;
+
+#ifdef CONFIG_BENET_NAPI
+ netif_napi_add(netdev, &OSM_NOB(pnob)->napi, be_poll, 64);
+ OSM_NOB(pnob)->rx_sched = FALSE;
+ spin_lock_init(&OSM_NOB(pnob)->rx_lock);
+#endif
+
+ if (be_setup_tx_res(pnob))
+ goto err_ret;
+ if (be_setup_rx_res(pnob))
+ goto err_ret;
+
+ if (!pm_resume) {
+ adapter->netdevp = OSM_NOB(pnob)->os_handle;
+ adapter->net_obj = pnob;
+ }
+ return 0;
+
+err_ret:
+ cleanup_netobject(pnob);
+
+err_ret1:
+ printk(KERN_ERR "Interface initialization failed\n");
+ return -1;
+}
+
+void enable_eq_intr(PBNI_NET_OBJECT pnob)
+{
+ bni_enable_eq_intr(pnob);
+}
+
+void disable_eq_intr(PBNI_NET_OBJECT pnob)
+{
+ bni_disable_eq_intr(pnob);
+}
+
+/* Wait until no more pending transmits */
+void wait_nic_tx_cmpl(PBNI_NET_OBJECT pnob)
+{
+ int i;
+
+ /* Wait for 20us * 50000 (= 1s) and no more */
+ i = 0;
+ while ((pnob->tx_q_tl != pnob->tx_q_hd) && (i < 50000)) {
+ ++i;
+ udelay(20);
+ }
+
+ /* Check for no more pending transmits */
+ if (i >= 50000) {
+ printk(KERN_WARNING
+ "Did not receive completions for all TX requests\n");
+ }
+}
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_netif.c benet/linux-2.6.24.2/drivers/net/benet/be_netif.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_netif.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_netif.c 2008-02-14 15:31:33.420341008 +0530
@@ -0,0 +1,600 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+ * be_netif.c
+ *
+ * This file contains various entry points of drivers seen by tcp/ip stack.
+ */
+
+#include <linux/pci.h>
+#include "be.h"
+#include <linux/ip.h>
+
+extern unsigned int ls_mss;
+
+unsigned int pm_resume;
+
+/* Strings to print Link properties */
+char *link_speed[] = {
+ "Invalid link Speed Value",
+ "10 Mbps",
+ "100 Mbps",
+ "1 Gbps",
+ "10 Gbps"
+};
+
+char *link_duplex[] = {
+ "Invalid Duplex Value",
+ "Half Duplex",
+ "Full Duplex"
+};
+
+#ifdef BE_POLL_MODE
+struct net_device *irq_netdev;
+#endif
+
+int benet_xmit(struct sk_buff *skb, struct net_device *netdev);
+int benet_set_mac_addr(struct net_device *netdev, void *p);
+
+void be_print_link_info(PBE_LINK_STATUS lnk_status)
+{
+ printk("PortNo 0:");
+ if (lnk_status->mac0_speed && lnk_status->mac0_duplex) {
+ /* Port is up and running */
+ if (lnk_status->mac0_speed < 5)
+ printk(" Link Speed: %s,",
+ link_speed[lnk_status->mac0_speed]);
+ else
+ printk(" %s,", link_speed[0]);
+
+ if (lnk_status->mac0_duplex < 3)
+ printk(" %s",
+ link_duplex[lnk_status->mac0_duplex]);
+ else
+ printk(" %s", link_duplex[0]);
+
+ if (lnk_status->active_port == 0)
+ printk("(active)\n");
+ else
+ printk("\n");
+ } else
+ printk(" Down \n");
+
+ printk("PortNo 1:");
+ if (lnk_status->mac1_speed && lnk_status->mac1_duplex) {
+ /* Port is up and running */
+ if (lnk_status->mac1_speed < 5)
+ printk(" Link Speed: %s,",
+ link_speed[lnk_status->mac1_speed]);
+ else
+ printk(" %s,", link_speed[0]);
+
+ if (lnk_status->mac1_duplex < 3)
+ printk(" %s",
+ link_duplex[lnk_status->mac1_duplex]);
+ else
+ printk(" %s", link_duplex[0]);
+
+ if (lnk_status->active_port == 1)
+ printk("(active)\n");
+ else
+ printk("\n");
+ } else
+ printk(" Down \n");
+
+ return;
+}
+
+int benet_open(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = (BNI_NET_OBJECT *) netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ TRACE(DL_INIT, "entered-benet_open()");
+
+ if (adapter->dev_state < BE_DEV_STATE_INIT)
+ return -EAGAIN;
+
+ be_update_link_status(adapter);
+
+ /*
+ * Set carrier on only if Physical Link up
+ * Either of the port link status up signifies this
+ */
+ if ((adapter->port0_link_sts == BE_PORT_LINK_UP) ||
+ (adapter->port1_link_sts == BE_PORT_LINK_UP)) {
+ netif_start_queue(netdev);
+ netif_carrier_on(netdev);
+ }
+
+ enable_eq_intr(pnob);
+ adapter->dev_state = BE_DEV_STATE_OPEN;
+
+#ifdef CONFIG_BENET_NAPI
+ napi_enable(&OSM_NOB(pnob)->napi);
+#endif
+ return 0;
+}
+
+int benet_close(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = (BNI_NET_OBJECT *) netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ /* Stop Transmitting */
+ netif_stop_queue(netdev);
+
+ synchronize_irq(netdev->irq);
+
+ /* Wait until no more pending transmits */
+ wait_nic_tx_cmpl(pnob);
+
+ adapter->dev_state = BE_DEV_STATE_INIT;
+
+ netif_carrier_off(netdev);
+
+ adapter->port0_link_sts = BE_PORT_LINK_DOWN;
+ adapter->port1_link_sts = BE_PORT_LINK_DOWN;
+
+#ifdef CONFIG_BENET_NAPI
+ napi_disable(&OSM_NOB(pnob)->napi);
+#endif
+ return 0;
+}
+
+int benet_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ TRACE(DL_INIT, "entered benet_ioctl()");
+
+ switch (cmd) {
+ case SIOCETHTOOL:
+ return be_ethtool_ioctl(dev, ifr);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+/*
+ * Setting a Mac Address for BE
+ * Takes netdev and a void pointer as arguments.
+ * The pointer holds the new addres to be used.
+ */
+int benet_set_mac_addr(struct net_device *netdev, void *p)
+{
+ struct sockaddr *addr = p;
+ PBNI_NET_OBJECT pnob;
+ SA_MAC_ADDRESS mac_addr;
+
+ SA_ASSERT(netdev);
+ pnob = (PBNI_NET_OBJECT) netdev->priv;
+ SA_ASSERT(pnob);
+
+ memcpy(pnob->mac_address, addr->sa_data, netdev->addr_len);
+ memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
+ memcpy(mac_addr.bytes, pnob->mac_address, SA_MAC_ADDRESS_SIZE);
+ bni_set_uc_mac_adr(pnob, 0, 0, OSM_NOB(pnob)->devno,
+ &mac_addr, NULL, NULL);
+ /*
+ * Since we are doing Active-Passive failover, both
+ * ports should have matching MAC addresses everytime.
+ */
+ bni_set_uc_mac_adr(pnob, 1, 0, OSM_NOB(pnob)->devno,
+ &mac_addr, NULL, NULL);
+
+ return 0;
+}
+
+void get_stats_timer_handler(unsigned long context)
+{
+ be_timer_ctxt_t *ctxt = (be_timer_ctxt_t *) context;
+ if (atomic_read(&ctxt->get_stat_flag)) {
+ atomic_dec(&ctxt->get_stat_flag);
+ up((PVOID) ctxt->get_stat_sem);
+ }
+ del_timer(&ctxt->get_stats_timer);
+ return;
+}
+
+void get_stat_cb(PVOID context, BESTATUS status, MCC_WRB *optional_wrb)
+{
+ be_timer_ctxt_t *ctxt = (be_timer_ctxt_t *) context;
+ /*
+ * just up the semaphore if the get_stat_flag
+ * reads 1. so that the waiter can continue.
+ * If it is 0, then it was handled by the timer handler.
+ */
+ if (atomic_read(&ctxt->get_stat_flag)) {
+ atomic_dec(&ctxt->get_stat_flag);
+ up((PVOID) ctxt->get_stat_sem);
+ }
+}
+
+struct net_device_stats *benet_get_stats(struct net_device *dev)
+{
+ PBNI_NET_OBJECT pnob = dev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ u64 pa;
+ be_timer_ctxt_t *ctxt = adapter->ctxt;
+
+ if (!BE_DEV_STATE_OPEN(adapter) || (pm_resume)) {
+ /* Return previously read stats */
+ return &(adapter->benet_stats);
+ }
+ /* Get Physical Addr */
+ pa = pci_map_single(adapter->pdev, adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ pa = cpu_to_le64(pa);
+ ctxt->get_stat_sem = (unsigned long)&adapter->get_eth_stat_sem;
+ bni_get_stats(adapter->net_obj, adapter->eth_statsp,
+ pa, get_stat_cb, (PVOID) ctxt);
+ atomic_inc(&ctxt->get_stat_flag);
+ ctxt->get_stats_timer.data = (unsigned long)ctxt;
+ mod_timer(&ctxt->get_stats_timer, (jiffies + (HZ * 2)));
+ down((PVOID) ctxt->get_stat_sem); /* block till callback is called */
+
+ /*Adding port0 and port1 stats. */
+ adapter->benet_stats.rx_packets =
+ adapter->eth_statsp->params.response.p0recvdtotalframes +
+ adapter->eth_statsp->params.response.p1recvdtotalframes;
+ adapter->benet_stats.tx_packets =
+ adapter->eth_statsp->params.response.p0xmitunicastframes +
+ adapter->eth_statsp->params.response.p1xmitunicastframes;
+ adapter->benet_stats.tx_bytes =
+ adapter->eth_statsp->params.response.p0xmitbyteslsd +
+ adapter->eth_statsp->params.response.p1xmitbyteslsd;
+ adapter->benet_stats.rx_errors =
+ adapter->eth_statsp->params.response.p0crcerrors +
+ adapter->eth_statsp->params.response.p1crcerrors;
+ adapter->benet_stats.rx_errors +=
+ adapter->eth_statsp->params.response.p0alignmentsymerrs +
+ adapter->eth_statsp->params.response.p1alignmentsymerrs;
+ adapter->benet_stats.rx_errors +=
+ adapter->eth_statsp->params.response.p0inrangelenerrors +
+ adapter->eth_statsp->params.response.p1inrangelenerrors;
+ adapter->benet_stats.rx_bytes =
+ adapter->eth_statsp->params.response.p0recvdtotalbytesLSD +
+ adapter->eth_statsp->params.response.p1recvdtotalbytesLSD;
+ adapter->benet_stats.rx_crc_errors =
+ adapter->eth_statsp->params.response.p0crcerrors +
+ adapter->eth_statsp->params.response.p1crcerrors;
+
+ adapter->benet_stats.tx_packets +=
+ adapter->eth_statsp->params.response.p0xmitmulticastframes +
+ adapter->eth_statsp->params.response.p1xmitmulticastframes;
+ adapter->benet_stats.tx_packets +=
+ adapter->eth_statsp->params.response.p0xmitbroadcastframes +
+ adapter->eth_statsp->params.response.p1xmitbroadcastframes;
+ adapter->benet_stats.tx_errors = 0;
+
+ adapter->benet_stats.multicast =
+ adapter->eth_statsp->params.response.p0xmitmulticastframes +
+ adapter->eth_statsp->params.response.p1xmitmulticastframes;
+
+ adapter->benet_stats.rx_fifo_errors =
+ adapter->eth_statsp->params.response.p0rxfifooverflowdropped +
+ adapter->eth_statsp->params.response.p1rxfifooverflowdropped;
+ adapter->benet_stats.rx_frame_errors =
+ adapter->eth_statsp->params.response.p0alignmentsymerrs +
+ adapter->eth_statsp->params.response.p1alignmentsymerrs;
+ adapter->benet_stats.rx_length_errors =
+ adapter->eth_statsp->params.response.p0inrangelenerrors +
+ adapter->eth_statsp->params.response.p1inrangelenerrors;
+ adapter->benet_stats.rx_length_errors +=
+ adapter->eth_statsp->params.response.p0outrangeerrors +
+ adapter->eth_statsp->params.response.p1outrangeerrors;
+ adapter->benet_stats.rx_length_errors +=
+ adapter->eth_statsp->params.response.p0frametoolongerrors +
+ adapter->eth_statsp->params.response.p1frametoolongerrors;
+
+ pci_unmap_single(adapter->pdev, (ulong) adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ return &(adapter->benet_stats);
+
+}
+
+/*
+ * function called by the stack for transmitting an ether frame
+ */
+int benet_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ u8 proto;
+ struct iphdr *ip;
+ u16 lso_mss;
+#ifdef NETIF_F_TSO
+ u32 segs;
+
+ lso_mss = skb_shinfo(skb)->gso_size;
+ segs = skb_shinfo(skb)->gso_segs;
+ /*
+ * bug# 3356.
+ * If a LSO request translates into a single segment,
+ * it should be posted as a ethernet WRB with no LSO.
+ */
+ if (segs == 1)
+ lso_mss = 0;
+#else
+ lso_mss = 0;
+#endif /*TSO */
+
+ TRACE(DL_SEND, "benet_xmit: Entry... len = %d", skb->len);
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ ip = (struct iphdr *)ip_hdr(skb);
+ proto = ip->protocol;
+ } else {
+ proto = 0;
+ }
+
+ if (betx_ether_frame(adapter, pnob, skb, proto, 0, lso_mss) !=
+ BE_SUCCESS) {
+ return 1; /* NETDEV_TX_BUSY */
+ }
+
+ netdev->trans_start = jiffies;
+ TRACE(DL_SEND, "benet_xmit() : Exit");
+ return 0; /*NETDEV_TX_OK */
+
+}
+
+/*
+ * This is the driver entry point to change the mtu of the device
+ * Returns 0 for success and errno for failure.
+ */
+int benet_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ u32 mtu, max_mtu, max_hdr;
+ max_hdr = BE_ENET_HEADER_SIZE + BE_ETHERNET_FCS_SIZE +
+ BE_SNAP_HEADER_SIZE + BE_HEADER_802_2_SIZE;
+
+ if (netdev->priv_flags & IFF_802_1Q_VLAN)
+ max_hdr += BE_VLAN_HEADER_SIZE;
+
+ mtu = new_mtu + max_hdr;
+
+ /*
+ * BE supports jumbo frame size upto 9000 bytes including the link layer
+ * header. Considering the different variants of frame formats possible
+ * like VLAN, SNAP/LLC, the maximum possible value for MTU is 8974 bytes
+ */
+ max_mtu = BE_MAX_JUMBO_FRAME_SIZE;
+
+ if ((mtu < BE_MIN_ETHER_FRAME_SIZE) || (mtu > max_mtu)) {
+ printk(KERN_WARNING "Invalid MTU requested. "
+ "Must be between %d and %d bytes\n",
+ BE_MIN_SUPPORT_FRAME_SIZE, (max_mtu - max_hdr));
+ return -EINVAL;
+ }
+ printk(KERN_INFO "MTU changed from %d to %d\n", netdev->mtu,
+ new_mtu);
+ netdev->mtu = new_mtu;
+ return 0;
+}
+
+/*
+ * This is the driver entry point to register a vlan with the device
+ */
+void benet_vlan_register(struct net_device *netdev, struct vlan_group *grp)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+
+ TRACE(DL_VLAN, "vlan register called");
+
+ disable_eq_intr(pnob);
+ OSM_NOB(pnob)->vlan_grp = grp;
+ OSM_NOB(pnob)->num_vlans = 0;
+ enable_eq_intr(pnob);
+}
+
+/*
+ * This is the driver entry point to add a vlan vlan_id
+ * with the device netdev
+ */
+void benet_vlan_add_vid(struct net_device *netdev, u16 vlan_id)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+
+ TRACE(DL_VLAN, "Add vlan ID");
+ if (OSM_NOB(pnob)->num_vlans == (BE_NUM_VLAN_SUPPORTED-1)) {
+ /* no way to return an error */
+ printk(KERN_ERR
+ "BladeEngine: Cannot configure more than %d Vlans\n",
+ BE_NUM_VLAN_SUPPORTED);
+ return;
+ }
+ /*The new vlan tag will be in the slot indicated by num_vlans. */
+ OSM_NOB(pnob)->vlan_tag[OSM_NOB(pnob)->num_vlans++] = vlan_id;
+ bni_config_vlan(pnob, OSM_NOB(pnob)->vlan_tag,
+ OSM_NOB(pnob)->num_vlans, NULL, NULL, 0);
+}
+
+/*
+ * This is the driver entry point to remove a vlan vlan_id
+ * with the device netdev
+ */
+void benet_vlan_rem_vid(struct net_device *netdev, u16 vlan_id)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+
+ u32 i, value;
+
+ TRACE(DL_VLAN, "Remove vlan ID");
+ /*
+ * In Blade Engine, we support 32 vlan tag filters across both ports.
+ * To program a vlan tag, the RXF_RTPR_CSR register is used.
+ * Each 32-bit value of RXF_RTDR_CSR can address 2 vlan tag entries.
+ * The Vlan table is of depth 16. thus we support 32 tags.
+ */
+
+ value = vlan_id | VLAN_VALID_BIT;
+ TRACE(DL_VLAN, "Value is %x", value);
+ TRACE(DL_VLAN, "Number of vlan tags is %d", OSM_NOB(pnob)->num_vlans);
+ for (i = 0; i < BE_NUM_VLAN_SUPPORTED; i++) {
+ TRACE(DL_VLAN, "Value at index %d is %x", i,
+ OSM_NOB(pnob)->vlan_tag[i]);
+ if (OSM_NOB(pnob)->vlan_tag[i] == vlan_id) {
+ TRACE(DL_VLAN, "Vlan ID found at index %d", i);
+ break;
+ }
+ }
+
+ if (i == BE_NUM_VLAN_SUPPORTED) {
+ TRACE(DL_VLAN, "Vlan ID %d not dound - remove failed", value);
+ return;
+ }
+ /* Now compact the vlan tag array by removing hole created. */
+ while ((i + 1) < BE_NUM_VLAN_SUPPORTED) {
+ OSM_NOB(pnob)->vlan_tag[i] = OSM_NOB(pnob)->vlan_tag[i + 1];
+ i++;
+ }
+ if ((i + 1) == BE_NUM_VLAN_SUPPORTED) {
+ OSM_NOB(pnob)->vlan_tag[i] = (u16) 0x0;
+ }
+ OSM_NOB(pnob)->num_vlans--;
+ bni_config_vlan(pnob, OSM_NOB(pnob)->vlan_tag,
+ OSM_NOB(pnob)->num_vlans, NULL, NULL, 0);
+ TRACE(DL_VLAN, "Removed the vlan ID of %d", vlan_id);
+}
+
+/*
+ * This function is called to program multicast
+ * address in the multicast filter of the ASIC.
+ */
+void be_set_multicast_filter(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ struct dev_mc_list *mc_ptr;
+ SA_MAC_ADDRESS mac_addr[32];
+ int i;
+
+ if (netdev->flags & IFF_ALLMULTI) {
+ /* set BE in Multicast promiscuous */
+ bni_set_mc_filter(pnob, 0, TRUE, NULL, NULL, NULL);
+ return;
+ }
+
+ for (mc_ptr = netdev->mc_list, i = 0; mc_ptr;
+ mc_ptr = mc_ptr->next, i++) {
+ memcpy(mac_addr[i].bytes, mc_ptr->dmi_addr,
+ SA_MAC_ADDRESS_SIZE);
+ }
+ /* reset the promiscuous mode also. */
+ bni_set_mc_filter(pnob, i, FALSE, mac_addr, NULL, NULL);
+
+}
+
+/*
+ * This is the driver entry point to set multicast list
+ * with the device netdev. This function will be used to
+ * set promiscuous mode or multicast promiscuous mode
+ * or multicast mode....
+ */
+void benet_set_multicast_list(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ if (netdev->flags & IFF_PROMISC) {
+ bni_set_promisc(adapter->net_obj);
+
+ } else if (netdev->flags & IFF_ALLMULTI) {
+ bni_reset_promisc(adapter->net_obj);
+ be_set_multicast_filter(netdev);
+ } else {
+ bni_reset_promisc(adapter->net_obj);
+ be_set_multicast_filter(netdev);
+ }
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void be_netpoll(struct net_device *netdev)
+{
+ disable_irq(netdev->irq);
+ be_int(netdev->irq, netdev, NULL);
+ enable_irq(netdev->irq);
+}
+#endif
+
+/*
+ * standard entry point functions for all Linux network interface drivers
+ */
+int benet_probe(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ TRACE(DL_INIT, "entered-benet_probe().");
+
+ ether_setup(netdev);
+
+ netdev->open = &benet_open;
+ netdev->stop = &benet_close;
+ netdev->do_ioctl = &benet_ioctl;
+
+ netdev->hard_start_xmit = &benet_xmit;
+
+ netdev->get_stats = &benet_get_stats;
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+ netdev->poll_controller = &be_netpoll;
+#endif
+
+ netdev->set_multicast_list = &benet_set_multicast_list;
+
+ netdev->change_mtu = &benet_change_mtu;
+ netdev->set_mac_address = &benet_set_mac_addr;
+
+ netdev->vlan_rx_register = benet_vlan_register;
+ netdev->vlan_rx_add_vid = benet_vlan_add_vid;
+ netdev->vlan_rx_kill_vid = benet_vlan_rem_vid;
+
+ netdev->features =
+ NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_RX |
+ NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM;
+
+ netdev->flags |= IFF_MULTICAST;
+
+ /* If device is DAC Capable, set the HIGHDMA flag for netdevice. */
+ if (adapter->dma_64bit_cap)
+ netdev->features |= NETIF_F_HIGHDMA;
+
+#ifdef NETIF_F_TSO
+ netdev->features |= NETIF_F_TSO;
+#endif
+
+ be_set_ethtool_ops(netdev);
+
+ return 0;
+}
___________________________________________________________________________________
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^ permalink raw reply
* [PATHCH 2/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:30 UTC (permalink / raw)
To: netdev
NIC driver transmit and interrupt / completion processing functions.
----------------
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_int.c benet/linux-2.6.24.2/drivers/net/benet/be_int.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_int.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_int.c 2008-02-14 15:30:42.802036160 +0530
@@ -0,0 +1,1254 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/if_vlan.h>
+
+#ifdef RX_PKT_COALESCE
+#include <net/tcp.h>
+#endif
+
+#include "be.h"
+
+/* number of bytes of RX frame that are copied to skb->data */ #define
+BE_HDR_LEN 64
+
+#ifdef CONFIG_BENET_NAPI
+#define VLAN_ACCEL_RX(skb, pnob, vt) \
+ vlan_hwaccel_receive_skb(skb, OSM_NOB(pnob)->vlan_grp, vt); #else
+#define VLAN_ACCEL_RX(skb, pnob, vt) \
+ vlan_hwaccel_rx(skb, OSM_NOB(pnob)->vlan_grp, vt); #endif
+
+#ifdef CONFIG_BENET_NAPI
+#define NETIF_RX(skb) netif_receive_skb(skb); #else #define
+NETIF_RX(skb) netif_rx(skb); #endif
+
+/*
+ * adds additional receive frags indicated by BE starting from given
+ * frag index (fi) to specified skb's frag list */ static inline void
+add_skb_frags(PBNI_NET_OBJECT pnob, struct sk_buff *skb,
+ int nresid, u32 fi)
+{
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ u32 sk_frag_idx, n;
+ BE_RX_PAGE_INFO *rx_page_info;
+ u32 frag_sz = pnob->rx_buf_size;
+
+ sk_frag_idx = skb_shinfo(skb)->nr_frags;
+ while (nresid) {
+ fi = (fi + 1) % pnob->rx_q_len; /* frag index */
+
+ rx_page_info = (BE_RX_PAGE_INFO *) pnob->rx_ctxt[fi];
+ pnob->rx_ctxt[fi] = (void *)NULL;
+ if ((rx_page_info->page_offset) ||
+ (OSM_NOB(pnob)->rx_pg_shared == FALSE)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus),
+ frag_sz, PCI_DMA_FROMDEVICE);
+ }
+
+ n = MIN(nresid, frag_sz);
+ skb_shinfo(skb)->frags[sk_frag_idx].page
+ = rx_page_info->page;
+ skb_shinfo(skb)->frags[sk_frag_idx].page_offset
+ = rx_page_info->page_offset;
+ skb_shinfo(skb)->frags[sk_frag_idx].size = n;
+
+ sk_frag_idx++;
+ skb->len += n;
+ skb->data_len += n;
+ skb_shinfo(skb)->nr_frags++;
+ nresid -= n;
+
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ sa_atomic_decrement(&pnob->rx_q_posted);
+ }
+}
+
+/*
+ * This function processes incoming nic packets over various Rx queues.
+ * This function takes the adapter, the current Rx status descriptor
+ * entry and the Rx completion queue ID as argument.
+ */
+static inline int process_nic_rx_completion(PBNI_NET_OBJECT pnob,
+ PETH_RX_COMPL rxcp)
+{
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ struct sk_buff *skb;
+ int udpcksm, tcpcksm;
+ int n, fi;
+ int nresid;
+ unsigned int frag_sz = pnob->rx_buf_size;
+ u8 *va;
+ BE_RX_PAGE_INFO *rx_page_info;
+
+ fi = rxcp->fragndx;
+ SA_ASSERT(fi < (int)pnob->rx_q_len);
+ SA_ASSERT(fi >= 0);
+
+ rx_page_info = (BE_RX_PAGE_INFO *) pnob->rx_ctxt[fi];
+ SA_ASSERT(rx_page_info->page);
+ pnob->rx_ctxt[fi] = (void *)NULL;
+
+ /*
+ * If one page is used per fragment or if this is the second half of
+ * of the page, unmap the page here
+ */
+ if ((rx_page_info->page_offset) ||
+ (OSM_NOB(pnob)->rx_pg_shared == FALSE)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus), frag_sz,
+ PCI_DMA_FROMDEVICE);
+ }
+
+ sa_atomic_decrement(&pnob->rx_q_posted);
+ udpcksm = rxcp->udpcksm;
+ tcpcksm = rxcp->tcpcksm;
+ /*
+ * get rid of RX flush completions first.
+ */
+ if ((tcpcksm) && (udpcksm) && (rxcp->pktsize == 32)) {
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ return SUCCESS;
+ }
+ skb = alloc_skb(BE_HDR_LEN + 16, GFP_ATOMIC);
+ if (skb == NULL) {
+ printk(KERN_WARNING "alloc_skb() failed\n");
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ goto free_frags;
+ }
+ skb_reserve(skb, NET_IP_ALIGN);
+
+ skb->dev = OSM_NOB(pnob)->os_handle;
+
+ SA_ASSERT(rxcp->numfrags > 0);
+ SA_ASSERT(rxcp->numfrags ==
+ ((rxcp->pktsize + frag_sz - 1) / frag_sz));
+
+ /* Only one of udpcksum and tcpcksum can be set */
+ SA_ASSERT(!(udpcksm && tcpcksm));
+
+ TRACE(DL_RECV, "First fragment");
+ n = MIN(rxcp->pktsize, frag_sz);
+
+ va = page_address(rx_page_info->page) + rx_page_info->page_offset;
+ prefetch(va);
+
+ skb->len = skb->data_len = n;
+ if (n <= BE_HDR_LEN) {
+ memcpy(skb->data, va, n);
+ put_page(rx_page_info->page);
+ skb->data_len -= n;
+ skb->tail += n;
+ } else {
+
+ /* Setup the SKB with page buffer information */
+ skb_shinfo(skb)->frags[0].page = rx_page_info->page;
+ skb_shinfo(skb)->nr_frags++;
+
+ /* Copy the header into the skb_data */
+ memcpy(skb->data, va, BE_HDR_LEN);
+ skb_shinfo(skb)->frags[0].page_offset =
+ rx_page_info->page_offset + BE_HDR_LEN;
+ skb_shinfo(skb)->frags[0].size = n - BE_HDR_LEN;
+ skb->data_len -= BE_HDR_LEN;
+ skb->tail += BE_HDR_LEN;
+ }
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ nresid = rxcp->pktsize - n;
+
+ skb->protocol = eth_type_trans(skb, OSM_NOB(pnob)->os_handle);
+
+ if ((tcpcksm || udpcksm) && adapter->rx_csum) {
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ } else {
+ skb->ip_summed = CHECKSUM_NONE;
+ }
+
+ /*
+ * if we have more bytes left, the frame has been
+ * given to us in multiple fragments. This happens
+ * with Jumbo frames. Add the remaining fragments to
+ * skb->frags[] array.
+ */
+ if (nresid)
+ add_skb_frags(pnob, skb, nresid, fi);
+
+ /* update the the true size of the skb. */
+ skb->truesize = skb->len + sizeof(struct sk_buff);
+
+ /*
+ * If a 802.3 frame or 802.2 LLC frame
+ * (i.e) contains length field in MAC Hdr
+ * and frame len is greater than 64 bytes
+ */
+ if (((skb->protocol == ntohs(ETH_P_802_2)) ||
+ (skb->protocol == ntohs(ETH_P_802_3)))
+ && (rxcp->pktsize > BE_HDR_LEN)) {
+ /*
+ * If the length given in Mac Hdr is less than frame size
+ * Erraneous frame, Drop it
+ */
+ if ((ntohs(*(u16 *) (va + 12)) + ETH_HLEN) < rxcp->pktsize) {
+ /* Increment Non Ether type II frames dropped */
+ adapter->be_stat.bes_802_3_dropped_frames++;
+
+ kfree_skb(skb);
+ return SUCCESS;
+ }
+ /*
+ * else if the length given in Mac Hdr is greater than
+ * frame size, should not be seeing this sort of frames
+ * dump the pkt and pass to stack
+ */
+ else if ((ntohs(*(u16 *) (va + 12)) + ETH_HLEN) >
+ rxcp->pktsize) {
+ /* Increment Non Ether type II frames malformed */
+ adapter->be_stat.bes_802_3_malformed_frames++;
+ }
+ }
+
+ if (rxcp->vtp && rxcp->vtm) {
+ /* Vlan tag present in pkt and BE found
+ * that the tag matched an entry in VLAN table
+ */
+ if (!(OSM_NOB(pnob)->vlan_grp) ||
+ OSM_NOB(pnob)->num_vlans == 0) {
+ /* But we have no VLANs configured.
+ * This should never happen. Drop the packet.
+ */
+ printk(KERN_ERR
+ "BladeEngine: Unexpected vlan tagged packet\n");
+ kfree_skb(skb);
+ return SUCCESS;
+ }
+ /* pass the VLAN packet to stack */
+ VLAN_ACCEL_RX(skb, pnob, be16_to_cpu(rxcp->vlan_tag));
+
+ } else {
+ NETIF_RX(skb);
+ }
+
+ return SUCCESS;
+free_frags:
+ /* free all frags associated with the current rxcp */
+ while (rxcp->numfrags-- > 1) {
+ fi = (fi + 1) % pnob->rx_q_len;
+
+ rx_page_info = (BE_RX_PAGE_INFO *)
+ pnob->rx_ctxt[fi];
+ pnob->rx_ctxt[fi] = (void *)NULL;
+ if ((rx_page_info->page_offset) ||
+ (OSM_NOB(pnob)->rx_pg_shared == FALSE)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus),
+ frag_sz, PCI_DMA_FROMDEVICE);
+ }
+
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ sa_atomic_decrement(&pnob->rx_q_posted);
+ }
+ return -ENOMEM;
+}
+
+#ifdef RX_PKT_COALESCE
+/*
+ * This function updates ip header checksum and tcp timestamps in the
+ * skb associtated with the given coalesce objcet and passes the
+ * skb to the stack.
+ */
+static inline void
+prep_skb_final(PBNI_NET_OBJECT pnob, struct be_coalesce_object *obj) {
+ struct sk_buff *skb;
+ struct iphdr *iph;
+ struct tcphdr *th;
+ u32 *ts_ptr;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ skb = obj->skb;
+ if (obj->frag_cnt > 2) {
+ /*update the ip header */
+ iph = (struct iphdr *)skb->data;
+ iph->tot_len = ntohs(skb->len);
+ iph->check = 0;
+ iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
+
+ /*update the tcp header */
+ th = (struct tcphdr *)((char *)skb->data + sizeof(*iph));
+ th->ack_seq = obj->next_ack_seq;
+ th->window = obj->last_seen_window;
+
+ /*Update the tcp timestamp. */
+ if (obj->tcp_timestamp) {
+ ts_ptr = (u32 *) (th + 1);
+ ts_ptr[1] = htonl(obj->tcp_tsval);
+ ts_ptr[2] = obj->tcp_tsecr;
+ }
+#ifdef NETIF_F_TSO
+ skb_shinfo(skb)->gso_size = obj->mss; #endif
+ skb->truesize = skb->len + sizeof(struct sk_buff);
+ }
+ adapter->be_stat.bes_rx_coal += obj->frag_cnt;
+ adapter->be_stat.bes_rx_flush++;
+ if (obj->vlant) {
+ /* Vlan tag present in pkt and BE found
+ * that the tag matched an entry in VLAN table
+ */
+ if (!(OSM_NOB(pnob)->vlan_grp) ||
+ OSM_NOB(pnob)->num_vlans == 0) {
+ /* But we have no VLANs configured.
+ * This should never happen. Drop the packet.
+ */
+ printk(KERN_ERR
+ "BladeEngine: Unexpected vlan tagged packet\n");
+ kfree_skb(obj->skb);
+ return;
+ }
+
+ /* pass the VLAN packet to stack */
+ VLAN_ACCEL_RX(skb, pnob, obj->vlant);
+ } else {
+ NETIF_RX(obj->skb);
+ }
+}
+
+/*
+ * This function does the following:
+ * 1) Checks if the fragment pointed to by rxcp is a candidate for coalescing.
+ * 2) Determines the connection to which the received fragment belongs
+to
+ * 3) Checks if a coalesce object has already allocated for this
+connection
+ * 4) Allocates a new coalesce object if a matching object is not found.
+ * 5) Adds the fragment to the coalescce object if it is in-order with
+ * rest of the frgmnets in the coalesce object.
+ * 6) If the fragmentg is not in-order, passes the fragments in the
+ * existing coalesce object to stack and adds the current fragment to
+ * a new coalesce object.
+ *
+ */
+static inline int
+fill_rx_skb(PETH_RX_COMPL rxcp, BE_RX_PAGE_INFO *rx_page_info,
+ PBNI_NET_OBJECT pnob)
+{
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ u8 *va;
+ struct sk_buff *skb;
+ struct ethhdr *eh;
+ struct iphdr *iph;
+ struct tcphdr *th = NULL;
+ unsigned int hdr_len;
+ int idx = 0, tcp_opt_bytes = 0;
+ u32 *ts_ptr = NULL;
+ unsigned int iplen, tcpdata_len = 0;
+ __u32 tcp_seq = 0;
+ u32 num_frags, pkt_size, nresid, fi;
+ unsigned int frag_sz = pnob->rx_buf_size;
+ int n = 0;
+ int trim = 0;
+ struct be_coalesce_object *obj = NULL, *tmp_obj;
+ u32 i, first_free_rxc_obj = MAX_COALESCE_OBJECTS;
+ int vlanf = 0, vtm = 0;
+ u16 vlant;
+ BOOLEAN not_cc = 0; /* not a coalesce candidate */
+
+ num_frags = rxcp->numfrags;
+ pkt_size = rxcp->pktsize;
+ fi = rxcp->fragndx;
+ vlant = be16_to_cpu(rxcp->vlan_tag);
+ vlanf = rxcp->vtp;
+ vtm = rxcp->vtm;
+ SA_ASSERT(num_frags > 0);
+
+ /* jumbo frames could come in multiple fragments */
+ SA_ASSERT(num_frags == ((pkt_size + (frag_sz - 1)) / frag_sz));
+ n = MIN(pkt_size, frag_sz);
+ nresid = pkt_size - n; /* will be useful for jumbo pkts */
+
+ va = page_address(rx_page_info->page) + rx_page_info->page_offset;
+ prefetch(va);
+
+ eh = (struct ethhdr *)(va);
+ iph = (struct iphdr *)(eh + 1);
+ th = (struct tcphdr *)(iph + 1);
+
+ /* confirm that there are no IP options */
+ if ((iph->ihl << 2) != sizeof(*iph)) {
+ not_cc = 1;
+ goto first_frag;
+ }
+
+ /* .. and that the packet does not have the fragmentation bet set */
+ if (iph->frag_off & htons(IP_MF | IP_OFFSET)) {
+ not_cc = 1;
+ goto first_frag;
+ }
+
+ /*
+ * No coalescing if any TCP flag(s) other than ack
+ * or psh is encountered in the TCP header
+ */
+ if (th->fin || th->syn || th->rst || th->urg || th->ece
+ || th->cwr || !th->ack) {
+ not_cc = 1;
+ goto first_frag;
+ }
+ /* Check for aligned timestamps */
+ tcp_opt_bytes = (th->doff << 2) - sizeof(*th);
+ if (tcp_opt_bytes != 0) {
+ ts_ptr = (u32 *) (th + 1);
+ if (unlikely(tcp_opt_bytes != TCPOLEN_TSTAMP_ALIGNED) ||
+ (*ts_ptr != ntohl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)
+ | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP))) {
+ not_cc = 1;
+ goto first_frag;
+ }
+ }
+
+ iplen = ntohs(iph->tot_len);
+ trim = pkt_size - (iplen + sizeof(*eh));
+ if (unlikely(trim)) {
+ not_cc = 1;
+ goto first_frag;
+ }
+
+ tcpdata_len = iplen - (th->doff << 2) - sizeof(*iph);
+ if (!tcpdata_len) {
+ /* If this is a pure ack, give it away. */
+ not_cc = 1;
+ goto first_frag;
+ }
+
+ tcp_seq = ntohl(th->seq);
+ hdr_len = iplen + sizeof(*eh) - tcpdata_len;
+
+ /*
+ * If the number of connections is zero, coalesce using the first
+ * coalesce object in array
+ */
+ if (OSM_NOB(pnob)->num_coalesce_objects == 0) {
+ obj = &OSM_NOB(pnob)->rxc_obj[0];
+ goto first_frag;
+ }
+ /* Get the coalesce object to which this pkt belongs to */
+ for (i = 0; i < MAX_COALESCE_OBJECTS; ++i) {
+ tmp_obj = &OSM_NOB(pnob)->rxc_obj[i];
+ /* Check if this coalesce object is active */
+ if (tmp_obj->skb) {
+ /*
+ * Check if this is a packet for same or
+ * different connection
+ * */
+ if ((tmp_obj->sport == th->source) &&
+ (tmp_obj->saddr == iph->saddr) &&
+ (tmp_obj->dport == th->dest) &&
+ (tmp_obj->daddr == iph->daddr)) {
+ obj = tmp_obj;
+ break;
+ }
+ } else {
+ if (first_free_rxc_obj > i) {
+ first_free_rxc_obj = i;
+ }
+ }
+ } /* end for */
+
+ if (obj == NULL) {
+ /*
+ * current pkt doesn't fit into any of the
+ * active coalesce objects.
+ */
+ if (OSM_NOB(pnob)->num_coalesce_objects
+ == MAX_COALESCE_OBJECTS) {
+ /*
+ * All the coalesce objects are active
+ * So let the pkt go in the normal path
+ */
+ not_cc = 1;
+ goto first_frag;
+ } else {
+ /*
+ * Not all the coalesce objects are active.
+ * Use the first vacant coalesce object for this pkt
+ */
+ obj = &OSM_NOB(pnob)->rxc_obj[first_free_rxc_obj];
+ goto first_frag;
+ }
+ }
+ /* pkt fits into one of the active coalesce objects */
+ prefetch(ts_ptr);
+ skb = obj->skb;
+
+ if ((obj->next_pkt_seq != tcp_seq)) {
+ /*
+ * This is an out of order segment.
+ * flush the existing bucket and start fresh.
+ */
+ goto first_frag;
+ }
+ /* Check the time stamp */
+ if (obj->tcp_timestamp) {
+ __u32 tsval = ntohl(*(ts_ptr + 1));
+ /* timestamp values should be increasing */
+ if (unlikely(obj->tcp_tsval > tsval || *(ts_ptr + 2) == 0)) {
+ not_cc = 1;
+ goto first_frag;
+ }
+ obj->tcp_tsval = tsval;
+ obj->tcp_tsecr = *(ts_ptr + 2);
+ }
+
+ obj->next_pkt_seq += tcpdata_len;
+ obj->last_seen_window = th->window;
+ obj->next_ack_seq = th->ack_seq;
+ if (tcpdata_len > obj->mss) {
+ obj->mss = tcpdata_len;
+ }
+
+ /*
+ * Now let us fill the skb frag with page buffer info.
+ */
+ if ((pkt_size - hdr_len) <= 0) {
+ /*
+ * This is probably just an ack pkt, or pkt
+ * without any data in it. free the page.
+ */
+ put_page(rx_page_info->page);
+ } else {
+ idx = skb_shinfo(skb)->nr_frags;
+ skb_shinfo(skb)->nr_frags++;
+ obj->frag_cnt++;
+ skb_shinfo(skb)->frags[idx].page = rx_page_info->page;
+ skb_shinfo(skb)->frags[idx].page_offset =
+ (rx_page_info->page_offset + hdr_len);
+ skb_shinfo(skb)->frags[idx].size = (n - hdr_len);
+ }
+ skb->data_len += (n - hdr_len);
+ skb->len += (n - hdr_len);
+
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ /*
+ * if we have more bytes left, the frame has been
+ * given to us in multiple fragments. This happens
+ * with Jumbo frames. Add the remaining fragments to
+ * skb->frags[] array.
+ */
+ if (nresid)
+ add_skb_frags(pnob, skb, nresid, fi);
+
+ /* We have accumulated enough. give skb to stack */
+ if ((skb_shinfo(skb)->nr_frags >= adapter->max_rx_coal) ||
+ (skb->len > MAX_COALESCE_SIZE)) {
+ prep_skb_final(pnob, obj);
+ memset(obj, 0, sizeof(struct be_coalesce_object));
+ --OSM_NOB(pnob)->num_coalesce_objects;
+ }
+
+ return 0;
+
+first_frag:
+ /*
+ * We come here if this packet is not a candidate for coalescing,
+ * or this packet is the first packet in a coalesce object
+ * or it is an out-of-order packet.
+ */
+ if ((obj) && (obj->skb)) {
+ /* out-of-order packet. pass already accumulated fragments
+ * to stack
+ */
+ prep_skb_final(pnob, obj);
+ memset(obj, 0, sizeof(struct be_coalesce_object));
+ --OSM_NOB(pnob)->num_coalesce_objects;
+ }
+ skb = alloc_skb(BE_HDR_LEN + 16, GFP_ATOMIC);
+ if (skb == NULL) {
+ printk(KERN_WARNING "alloc_skb() failed\n");
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ goto free_frags; /* if there are more frags, free them */
+ }
+ skb_reserve(skb, NET_IP_ALIGN);
+ prefetch(va);
+ skb->dev = OSM_NOB(pnob)->os_handle;
+
+ hdr_len = BE_HDR_LEN > n ? n : BE_HDR_LEN;
+ /* Copy the header into the skb_data */
+ memcpy(skb->data, va, hdr_len);
+
+ if ((n - hdr_len) <= 0) {
+ /* Complete packet has now been moved to data */
+ put_page(rx_page_info->page);
+ } else {
+ /* Setup the SKB with page buffer information */
+ skb_shinfo(skb)->frags[0].page = rx_page_info->page;
+ skb_shinfo(skb)->frags[0].page_offset =
+ (rx_page_info->page_offset + hdr_len);
+ skb_shinfo(skb)->nr_frags++;
+ skb_shinfo(skb)->frags[0].size = (n - hdr_len);
+ skb->data_len = (n - hdr_len);
+ }
+
+ skb->len = n;
+ skb->tail += hdr_len;
+
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ skb->protocol = eth_type_trans(skb, OSM_NOB(pnob)->os_handle);
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ /*
+ * if we have more bytes left, the frame has been
+ * given to us in multiple fragments. This happens
+ * with Jumbo frames. Add the remaining fragments to
+ * skb->frags[] array.
+ */
+ if (nresid)
+ add_skb_frags(pnob, skb, nresid, fi);
+ skb->truesize = skb->len + sizeof(struct sk_buff);
+ /*
+ * The skb is ready for passing to stack. If it is not a candidate
+ * for coalescing or if the skb already has more frags than the
+ * max coalesce limit, pass it to stack.
+ */
+ if (not_cc || ((skb_shinfo(skb)->nr_frags + num_frags) >=
+ adapter->max_rx_coal)
+ || ((skb->len + pkt_size) >= MAX_COALESCE_SIZE)) {
+ if (vlanf && vtm) {
+ /* Vlan tag present in pkt and BE found
+ * that the tag matched an entry in VLAN table
+ */
+ if (!(OSM_NOB(pnob)->vlan_grp)
+ || OSM_NOB(pnob)->num_vlans == 0) {
+ /* But we have no VLANs configured.
+ * This should never happen. Drop the packet.
+ */
+ printk(KERN_ERR "BladeEngine: Unexpected vlan"
+ " tagged packet\n");
+ kfree_skb(obj->skb);
+ }
+
+ /* pass the VLAN packet to stack */
+ VLAN_ACCEL_RX(skb, pnob, vlant);
+
+ } else {
+ NETIF_RX(skb);
+ }
+ } else {
+ /* This is the first packet for coalescing into the
+ * new object pointed to by obj.
+ */
+ ++OSM_NOB(pnob)->num_coalesce_objects;
+ if (vlanf && vtm) {
+ obj->vlant = vlant;
+ }
+ obj->skb = skb;
+ obj->saddr = iph->saddr;
+ obj->sport = th->source;
+ obj->dport = th->dest;
+ obj->daddr = iph->daddr;
+ obj->mss = tcpdata_len;
+ obj->last_seen_window = th->window;
+ obj->next_ack_seq = th->ack_seq;
+ obj->next_pkt_seq = tcp_seq + tcpdata_len;
+ /* Update the timestamp info here.... */
+ if (tcp_opt_bytes) {
+ obj->tcp_timestamp = 1;
+ obj->tcp_tsval = ntohl(*(ts_ptr + 1));
+ obj->tcp_tsecr = *(ts_ptr + 2);
+ }
+ /*
+ *If it is a pkt with frag_sz is exactly 64 bytes
+ *then it has already been memcpy to skb->data.
+ */
+ obj->frag_cnt = skb_shinfo(skb)->nr_frags + 1;
+ }
+
+ return 0;
+
+free_frags:
+ /* free all frags associated with the current rxcp */
+ while (num_frags-- > 1) {
+ fi = (fi + 1) % pnob->rx_q_len;
+
+ rx_page_info = (BE_RX_PAGE_INFO *) pnob->rx_ctxt[fi];
+ pnob->rx_ctxt[fi] = (void *)NULL;
+ if ((rx_page_info->page_offset) ||
+ (OSM_NOB(pnob)->rx_pg_shared == FALSE)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus),
+ frag_sz, PCI_DMA_FROMDEVICE);
+ }
+
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ sa_atomic_decrement(&pnob->rx_q_posted);
+ }
+ return -ENOMEM;
+}
+#endif
+
+/*
+ * Process unicast completions
+ */
+void process_ucast_rx_completion(PBNI_NET_OBJECT pnob) {
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ PETH_RX_COMPL rxcp;
+ u32 nc = 0;
+#ifdef RX_PKT_COALESCE
+ unsigned int udpcksm, tcpcksm;
+ unsigned int i, fi;
+ BE_RX_PAGE_INFO *rx_page_info;
+ unsigned int frag_sz = pnob->rx_buf_size;
+ struct be_coalesce_object *obj;
+ BOOLEAN rx_coal = (adapter->max_rx_coal <= 1) ? 0 : 1; #endif
+ int rearm = 1;
+
+#ifdef CONFIG_BENET_NAPI
+ if (OSM_NOB(pnob)->work_quota == 0)
+ /*
+ * We were called from process_events without quota
+ * because the device is not open yet. Give ourselves
+ * a large quota.
+ */
+ OSM_NOB(pnob)->work_quota = 128;
+ while ((OSM_NOB(pnob)->work_quota) &&
+ (rxcp = bni_get_ucrx_cmpl(pnob))) #else
+ while ((rxcp = bni_get_ucrx_cmpl(pnob))) #endif
+ {
+ prefetch(rxcp);
+ TRACE(DL_RECV, "%s: valid ucast completion: len %d, index %d",
+ __FUNCTION__, rxcp->pktsize, rxcp->fragndx); #ifdef
+RX_PKT_COALESCE
+ if ((!rxcp->tcpf) || (rxcp->ipsec) || rxcp->err || !rx_coal) {
+ /*
+ * We won't coalesce Rx pkts
+ * if they are udp or ipsec or have the err bit set.
+ * take the path of normal completion processing
+ */
+ process_nic_rx_completion(pnob, rxcp);
+ goto next_compl;
+ }
+
+ fi = rxcp->fragndx;
+ SA_ASSERT(fi < (int)pnob->rx_q_len);
+ SA_ASSERT(fi >= 0);
+ rx_page_info = (BE_RX_PAGE_INFO *)
+ pnob->rx_ctxt[fi];
+ SA_ASSERT(rx_page_info);
+ SA_ASSERT(rx_page_info->page);
+ pnob->rx_ctxt[fi] = (void *)NULL;
+ /*
+ * If one page is used per fragment or if this is the
+ * second half of the page, unmap the page here
+ */
+ if ((rx_page_info->page_offset) ||
+ (OSM_NOB(pnob)->rx_pg_shared == FALSE)) {
+ pci_unmap_page(adapter->pdev,
+ pci_unmap_addr(rx_page_info, bus),
+ frag_sz, PCI_DMA_FROMDEVICE);
+ }
+
+ udpcksm = rxcp->udpcksm;
+ tcpcksm = rxcp->tcpcksm;
+
+ sa_atomic_decrement(&pnob->rx_q_posted);
+
+ if ((tcpcksm) && (udpcksm) && (rxcp->pktsize == 32)) {
+ put_page(rx_page_info->page);
+ memset(rx_page_info, 0, sizeof(BE_RX_PAGE_INFO));
+ goto next_compl;
+ }
+ /* Only one of udpcksum and tcpcksum can be set */
+ SA_ASSERT(!(udpcksm && tcpcksm));
+
+ fill_rx_skb(rxcp, rx_page_info, pnob);
+
+next_compl:
+#else
+ process_nic_rx_completion(pnob, rxcp); #endif
+ adapter->eth_rx_bytes += rxcp->pktsize;
+ /*
+ * RX rate calculation.
+ */
+ UPDATE_RATE(adapter, eth_rx_jiffies, eth_rx_bytes,
+ bes_eth_rx_rate);
+ nc++; /* number of cq entries that we have processed */
+ adapter->be_stat.bes_ucrx_compl++;
+#ifdef CONFIG_BENET_NAPI
+ OSM_NOB(pnob)->work_quota--;
+#endif
+ }
+#ifdef RX_PKT_COALESCE
+ for (i = 0; i < MAX_COALESCE_OBJECTS; ++i) {
+ obj = &OSM_NOB(pnob)->rxc_obj[i];
+ if (obj && (obj->skb)) {
+ prep_skb_final(pnob, obj);
+ memset(obj, 0, sizeof(struct be_coalesce_object));
+ --OSM_NOB(pnob)->num_coalesce_objects;
+ }
+ }
+#endif
+#ifdef CONFIG_BENET_NAPI
+ if (OSM_NOB(pnob)->work_quota == 0) {
+ /* we ran out of work budget */
+ rearm = 0;
+ } else {
+ /* we finished all work. We are in interrupt mode */
+ rearm = 1;
+ }
+#endif
+ /*
+ * we call notfiy completions even when nc is zero, since
+ * rearm value needs to take effect
+ */
+ bni_notify_cmpl(pnob, nc, pnob->ucrx_cq_id, rearm); }
+
+/*
+ * Process broadcast and multicat completions */ void
+process_bcast_rx_completion(PBNI_NET_OBJECT pnob) {
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ PETH_RX_COMPL rxcp;
+
+ u32 nc = 0;
+
+ adapter->be_stat.bes_bcrx_events++;
+
+ nc = 0;
+ while ((rxcp = (bni_get_bcrx_cmpl(pnob)))) {
+
+ TRACE(DL_RECV, "Got valid bcast completion: len %d, index %d",
+ rxcp->pktsize, rxcp->fragndx);
+
+ process_nic_rx_completion(pnob, rxcp);
+
+ nc++;
+ adapter->be_stat.bes_bcrx_compl++;
+ }
+ bni_notify_cmpl(pnob, nc, pnob->bcrx_cq_id, 1);
+
+}
+
+/* Process NIC TX COMPLETIONS */
+void process_nic_tx_completions(PBNI_NET_OBJECT pnob) {
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ PETH_TX_COMPL txcp; /* Eth Tx completion entry */
+ struct net_device *netdev = (struct net_device *)
+ OSM_NOB(pnob)->os_handle;
+ int num_processed = 0, cur_index, tx_wrbs_completed = 0, exp_index;
+ struct sk_buff *skb;
+ PHYSICAL_ADDRESS busaddr;
+ u64 pa;
+ PETH_WRB curr_wrb;
+
+ adapter->be_stat.bes_tx_events++;
+ /*
+ * there is no need to take an SMP lock here since currently
+ * we have only one instance of the tasklet that does completion
+ * processing.
+ */
+
+ /* process each valid completion entry */
+ while ((txcp = bni_get_tx_cmpl(pnob))) {
+ /* Get the expected completion index */
+ exp_index = (pnob->tx_q_tl +
+ ((int)pnob->tx_ctxt[pnob->tx_q_tl] - 1))
+ % pnob->tx_q_len;
+ pnob->tx_ctxt[pnob->tx_q_tl] = NULL;
+ if (exp_index != txcp->wrb_index) {
+ printk ("Expected Wrb Index (=%d) doesn't match with"
+ " Completion Wrb Index (=%d)\n", exp_index,
+ txcp->wrb_index);
+ }
+ /*
+ * All reqs in the TX ring from the current tail index upto
+ * the one indicated in this completion entry's wrb_index
+ * are now completed.
+ */
+ do {
+ cur_index = pnob->tx_q_tl;
+
+ curr_wrb = &pnob->tx_q[cur_index];
+ busaddr.pa_hi = curr_wrb->frag_pa_hi;
+ busaddr.pa_lo = curr_wrb->frag_pa_lo;
+ if (busaddr.pa != 0) {
+ pa = le64_to_cpu(busaddr.pa);
+
+ pci_unmap_single(adapter->pdev, pa,
+ curr_wrb->frag_len,
+ PCI_DMA_TODEVICE);
+ }
+ /*
+ * this Tx request is complete. The OSM context
+ * we stored is the skb address. free this skb.
+ */
+ skb = (struct sk_buff *) pnob->tx_ctxt[cur_index];
+ if (skb) {
+ unsigned int j;
+
+ for (j = 0; j < skb_shinfo(skb)->nr_frags;
+ j++) {
+ struct skb_frag_struct *frag;
+ frag = &skb_shinfo(skb)->frags[j];
+ pci_unmap_page(adapter->pdev,
+ (ulong) frag->page,
+ frag->size,
+ PCI_DMA_TODEVICE);
+ }
+ kfree_skb(skb);
+ pnob->tx_ctxt[cur_index] = NULL;
+ }
+
+ tx_wrbs_completed++;
+ bni_adv_txq_tl(pnob);
+ } while (cur_index != txcp->wrb_index);
+
+ num_processed++;
+ adapter->be_stat.bes_tx_compl++;
+ }
+ sa_atomic_sub(tx_wrbs_completed, &pnob->tx_q_used);
+ bni_notify_cmpl(pnob, num_processed, pnob->tx_cq_id, 1);
+ /*
+ * We got Tx completions and have usable WRBs.
+ * If the netdev's queue has been stopped
+ * because we had run out of WRBs, wake it now.
+ */
+ spin_lock(&adapter->txq_lock);
+ if (netif_queue_stopped(netdev)
+ && (pnob->tx_q_used < pnob->tx_q_len / 2)) {
+ netif_wake_queue(netdev);
+ }
+ spin_unlock(&adapter->txq_lock);
+}
+
+/*
+ * posts receive buffers to the Eth receive queue.
+ */
+void post_eth_rx_buffs(PBNI_NET_OBJECT pnob) {
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ u32 num_bufs, r;
+ PHYSICAL_ADDRESS busaddr, tmp_pa;
+ u32 max_bufs;
+ u32 frag_size;
+ PBNI_RECV_BUFFER rxbp;
+ SA_LIST_ENTRY rxbl;
+ BE_RX_PAGE_INFO *rx_page_info;
+ struct page *page = NULL;
+ u32 page_order = 0;
+ u32 alloc_flags = GFP_ATOMIC;
+
+ SA_ASSERT(adapter);
+
+ max_bufs = (u32) 64; /* should be even # <= 255. */
+ SA_ASSERT(max_bufs < 255 && (max_bufs & 1) == 0);
+
+ frag_size = pnob->rx_buf_size;
+
+ if (frag_size == 8192) {
+ page_order = 1;
+ alloc_flags |= __GFP_COMP;
+ }
+
+ /*
+ * Form a linked list of RECV_BUFFFER structure to be be posted.
+ * We will post even number of buffer so that pages can be
+ * shared.
+ */
+ sa_initialize_list_head(&rxbl);
+
+ for (num_bufs = 0; num_bufs < max_bufs; ++num_bufs) {
+
+ rxbp = &(OSM_NOB(pnob)->eth_rx_bufs[num_bufs]);
+ rx_page_info =
+ &(OSM_NOB(pnob)->
+ rx_page_info[OSM_NOB(pnob)->rx_pg_info_hd]);
+
+ if (!page) {
+ /*
+ * before we allocate a page make sure that we
+ * have space in the RX queue to post the buffer.
+ * We check for two vacant slots since with
+ * 2K frags, we will need two slots.
+ */
+ if ((pnob->
+ rx_ctxt[(pnob->rx_q_hd +
+ num_bufs) % pnob->rx_q_len] != NULL)
+ || (pnob->
+ rx_ctxt[(pnob->rx_q_hd + num_bufs +
+ 1) % pnob->rx_q_len] != NULL)) {
+ break;
+ }
+ page = alloc_pages(alloc_flags, page_order);
+ if (unlikely(page == NULL)) {
+ adapter->be_stat.bes_ethrx_post_fail++;
+ OSM_NOB(pnob)->rxbuf_post_fail++;
+ break;
+ }
+ OSM_NOB(pnob)->rxbuf_post_fail = 0;
+ busaddr.pa = pci_map_page(adapter->pdev, page, 0,
+ frag_size,
+ PCI_DMA_FROMDEVICE);
+ rx_page_info->page_offset = 0;
+ rx_page_info->page = page;
+ /*
+ * If we are sharing a page among two skbs,
+ * alloc a new one on the next iteration
+ */
+ if (OSM_NOB(pnob)->rx_pg_shared == FALSE)
+ page = NULL;
+ } else {
+ get_page(page);
+ rx_page_info->page_offset += frag_size;
+ rx_page_info->page = page;
+ /*
+ * We are finished with the alloced page,
+ * Alloc a new one on the next iteration
+ */
+ page = NULL;
+ }
+ rxbp->rxb_ctxt = (void *)rx_page_info;
+ OSM_NOB(pnob)->rx_pg_info_hd =
+ (OSM_NOB(pnob)->rx_pg_info_hd + 1) % pnob->rx_q_len;
+
+ pci_unmap_addr_set(rx_page_info, bus, busaddr.pa);
+ tmp_pa.pa = busaddr.pa + rx_page_info->page_offset;
+ rxbp->rxb_pa_lo = tmp_pa.pa_lo;
+ rxbp->rxb_pa_hi = tmp_pa.pa_hi;
+ rxbp->rxb_len = frag_size;
+ InsertTailList(&rxbl, &rxbp->rxb_list);
+ } /* End of for */
+
+ r = bni_post_rx_buffs(pnob, &rxbl);
+ SA_ASSERT(r == num_bufs);
+ return;
+}
+
+/*
+ * Interrupt service for network function. We just schedule the
+ * tasklet which does all completion processing.
+ */
+irqreturn_t be_int(int irq, PVOID dev, struct pt_regs *regs) {
+ struct net_device *netdev = dev;
+ PBNI_NET_OBJECT pnob = (PBNI_NET_OBJECT) (netdev->priv);
+ PBE_ADAPTER adapter = (PBE_ADAPTER) OSM_NOB(pnob)->adapter;
+ u32 isr;
+
+ /*
+ * If not our interrupt, just return.
+ */
+ isr = bni_get_isr(pnob);
+ if (unlikely(!isr)) {
+ return 0;
+ }
+
+ spin_lock(&adapter->int_lock);
+ adapter->isr |= isr;
+ spin_unlock(&adapter->int_lock);
+
+ adapter->be_stat.bes_ints++;
+
+ tasklet_schedule(&adapter->sts_handler);
+ return 1;
+}
+
+#ifdef CONFIG_BENET_NAPI
+/*
+ * Poll function called by NAPI with a work budget.
+ * We process as many UC. BC and MC receive completions
+ * as the budget allows and return the actual number of
+ * RX ststutses processed.
+ */
+int be_poll(struct napi_struct *napi, int budget) {
+ struct net_device *netdev = napi->dev;
+ PBNI_NET_OBJECT pnob = (PBNI_NET_OBJECT) netdev->priv;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) OSM_NOB(pnob)->adapter;
+ u32 work_done;
+
+ adapter->be_stat.bes_polls++;
+ OSM_NOB(pnob)->work_quota = budget;
+ process_ucast_rx_completion(pnob);
+ process_bcast_rx_completion(pnob);
+ if (pnob->rx_q_posted < 900)
+ post_eth_rx_buffs(pnob);
+
+ work_done = (budget - OSM_NOB(pnob)->work_quota);
+
+ if (OSM_NOB(pnob)->work_quota == 0) {
+ return budget;
+ }
+ netif_rx_complete(netdev, napi);
+
+ /* If another rx was attempted while we were in poll, schedule again */
+ spin_lock_bh(&OSM_NOB(pnob)->rx_lock);
+ if (OSM_NOB(pnob)->rx_sched) {
+ OSM_NOB(pnob)->rx_sched = FALSE;
+ if (netif_rx_schedule_prep(netdev, napi))
+ __netif_rx_schedule(netdev, napi);
+ }
+ spin_unlock_bh(&OSM_NOB(pnob)->rx_lock);
+ return (budget - OSM_NOB(pnob)->work_quota); }
+
+#define SCHEDULE_NAPI_RX(no, nd) \
+ { \
+ spin_lock_bh(&OSM_NOB(no)->rx_lock); \
+ if (netif_rx_schedule_prep(nd, \
+ &OSM_NOB(no)->napi)) { \
+ __netif_rx_schedule(nd, \
+ &OSM_NOB(no)->napi); \
+ OSM_NOB(no)->rx_sched = FALSE; \
+ } \
+ else { \
+ OSM_NOB(no)->rx_sched = TRUE; \
+ } \
+ spin_unlock_bh(&OSM_NOB(no)->rx_lock); \
+ }
+#endif
+
+/*
+ * Processes all valid events in the event ring associated with given
+ * NetObject. Also, notifies BE the number of events processed.
+ */
+inline u32 process_events(PBNI_NET_OBJECT pnob) {
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ PEQ_ENTRY eqp;
+ u32 rid, num_events = 0;
+
+#ifdef CONFIG_BENET_NAPI
+ struct net_device *netdev = OSM_NOB(pnob)->os_handle; #endif
+
+ while ((eqp = bni_get_event(pnob)) != NULL) {
+ adapter->be_stat.bes_events++;
+ rid = eqp->ResourceID;
+
+ if (rid == pnob->ucrx_cq_id) {
+ adapter->be_stat.bes_ucrx_events++;
+#ifdef CONFIG_BENET_NAPI
+ if (BE_DEV_STATE_OPEN(adapter))
+ SCHEDULE_NAPI_RX(pnob, netdev)
+ else
+#endif
+ process_ucast_rx_completion(pnob);
+ } else if (rid == pnob->bcrx_cq_id) {
+ adapter->be_stat.bes_bcrx_events++;
+#ifdef CONFIG_BENET_NAPI
+ if (BE_DEV_STATE_OPEN(adapter))
+ SCHEDULE_NAPI_RX(pnob, netdev)
+ else
+#endif
+ process_bcast_rx_completion(pnob);
+ } else if (rid == pnob->tx_cq_id) {
+ process_nic_tx_completions(pnob);
+ } else if (rid == pnob->mcc_cq_id) {
+ bni_process_mcc_cmpl(&pnob->mcc_q_obj);
+ } else {
+ printk(KERN_WARNING "Invalid EQ ResourceID %d\n", rid);
+ }
+ eqp->Valid = 0;
+ num_events++;
+ }
+ return (num_events);
+}
+
+/*
+ * Called from the tasklet scheduled by ISR. All real interrupt
+processing
+ * is done here.
+ */
+void osm_process_sts(unsigned long context) {
+ PBE_ADAPTER adapter = (PBE_ADAPTER) context;
+ PBNI_NET_OBJECT pnob;
+ u32 isr, n;
+ ulong flags = 0;
+
+ SA_ASSERT(adapter);
+
+ isr = adapter->isr;
+
+ /*
+ * we create only one NIC event queue in Linux. Event is
+ * expected only in the first event queue
+ */
+ SA_ASSERT((isr & 0xfffffffe) == 0)
+ if ((isr & 1) == 0)
+ return; /* not our interrupt */
+ pnob = adapter->net_obj;
+ n = process_events(pnob);
+ /*
+ * Clear the event bit. adapter->isr is set by
+ * hard interrupt. Prevent race with lock.
+ */
+ spin_lock_irqsave(&adapter->int_lock, flags);
+ adapter->isr &= ~1;
+ spin_unlock_irqrestore(&adapter->int_lock, flags);
+ bni_notify_event(pnob, n, 1);
+
+#ifdef CONFIG_BENET_NAPI
+ /*
+ * In NAPI, posting of rx bufs is normally done
+ * in poll. However, if the device is not open
+ * or if previous allocation attempts had failed and
+ * BE has used up all posted buffers, we need to
+ * post here, since be_poll may never be called.
+ */
+ if ((!BE_DEV_STATE_OPEN(adapter) && pnob->rx_q_posted < 900) ||
+ ((OSM_NOB(pnob)->rxbuf_post_fail) && (pnob->rx_q_posted == 0))) {
+ post_eth_rx_buffs(pnob);
+ }
+#else
+ if (pnob->rx_q_posted < 900) {
+ post_eth_rx_buffs(pnob);
+ }
+#endif
+ UPDATE_IPS(adapter, pnob);
+ return;
+}
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_tx.c benet/linux-2.6.24.2/drivers/net/benet/be_tx.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_tx.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_tx.c 2008-02-14 15:23:07.793208016 +0530
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+ * This file contains the transmit functions.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/if_vlan.h>
+#include <linux/in.h>
+#include "be.h"
+
+/* Transmit Function */
+int betx_ether_frame(PBE_ADAPTER adapter, PBNI_NET_OBJECT pnob,
+ struct sk_buff *skb, u8 proto, u8 forward,
+ u16 lso_mss)
+{
+ unsigned int nfrags = 0, j, frame_size = 0;
+ BNI_TX_FRAG_LIST TxFragList[BE_MAX_TX_FRAG_COUNT];
+ unsigned int uiSendFlags;
+ void *ctxtp;
+ unsigned short vlanTag = 0;
+ unsigned short TxMss = 0;
+ PHYSICAL_ADDRESS busaddr;
+ int iStatus;
+
+ TRACE(DL_SEND, "betx_ether_frame() - Entry");
+
+ uiSendFlags = ETHCOMPLETE;
+
+ if (OSM_NOB(pnob)->vlan_grp && vlan_tx_tag_present(skb)) {
+ uiSendFlags |= ETHVLAN;
+ vlanTag = vlan_tx_tag_get(skb);
+ }
+ ctxtp = (void *)skb;
+
+ if (proto == IPPROTO_TCP) {
+ uiSendFlags |= TCPCS;
+ }
+
+ if (proto == IPPROTO_UDP) {
+ uiSendFlags |= UDPCS;
+ }
+
+ if (forward) {
+ uiSendFlags |= FORWARD;
+ adapter->be_stat.bes_fwd_reqs++;
+ }
+
+ if (lso_mss) {
+ uiSendFlags |= LSO;
+ TxMss = lso_mss;
+ }
+
+ TRACE(DL_SEND, "NIC TX: ");
+ adapter->be_stat.bes_tx_reqs++;
+ /* populate the fragment (SG) list for this request */
+ while (skb) {
+ /*
+ * Check whether Fragment count goes above
+ * BE_MAX_TX_FRAG_COUNT
+ */
+ if ((nfrags + 1) > BE_MAX_TX_FRAG_COUNT)
+ goto max_tx_frag_error;
+
+ /*
+ * Get required info from main fragment of skb
+ * First get Quad Address
+ */
+ busaddr.pa = pci_map_single(adapter->pdev, skb->data,
+ (skb->len - skb->data_len),
+ PCI_DMA_TODEVICE);
+ busaddr.pa = cpu_to_le64(busaddr.pa);
+ TxFragList[nfrags].txb_pa_lo = busaddr.pa_lo;
+ TxFragList[nfrags].txb_pa_hi = busaddr.pa_hi;
+ /* Next get Length */
+ TxFragList[nfrags].txb_len = skb->len - skb->data_len;
+ frame_size += TxFragList[nfrags].txb_len;
+ TRACE(DL_SEND, "(0x%x) %d", TxFragList[nfrags].txb_pa_lo,
+ TxFragList[nfrags].txb_len);
+ nfrags++;
+
+ /* For all the data fragments in this skb */
+ for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
+ struct skb_frag_struct *frag;
+
+ /*
+ * Check whether Fragment count goes
+ * above BE_MAX_TX_FRAG_COUNT
+ */
+ if ((nfrags + 1) > BE_MAX_TX_FRAG_COUNT)
+ goto max_tx_frag_error;
+
+ /* For each fragment get required info */
+ frag = &skb_shinfo(skb)->frags[j];
+ /* First get Quad Address */
+ busaddr.pa = pci_map_page(adapter->pdev,
+ frag->page,
+ frag->page_offset,
+ frag->size,
+ PCI_DMA_TODEVICE);
+ busaddr.pa = cpu_to_le64(busaddr.pa);
+ TxFragList[nfrags].txb_pa_lo = busaddr.pa_lo;
+ TxFragList[nfrags].txb_pa_hi = busaddr.pa_hi;
+ /* Next get Length */
+ TxFragList[nfrags].txb_len = frag->size;
+ frame_size += TxFragList[nfrags].txb_len;
+ TRACE(DL_SEND, ", (0x%x) %d",
+ TxFragList[nfrags].txb_pa_lo,
+ TxFragList[nfrags].txb_len);
+ nfrags++;
+ } /* End For Loop */
+
+ /*
+ * If the skb shared info points to another
+ * sk_buff then traverse this pointed
+ * skbuff in the same way till the end of the list
+ */
+ skb = skb_shinfo(skb)->frag_list;
+ } /* End While Loop */
+
+ spin_lock_bh(&adapter->txq_lock);
+ TRACE(DL_SEND, "\n");
+
+ /* Transmit the packet */
+ iStatus = bni_tx_pkt(pnob, TxFragList,
+ uiSendFlags, vlanTag, TxMss, ctxtp, nfrags);
+ if (iStatus != BE_SUCCESS) {
+ /*Tell the stack that Tx failed. */
+ netif_stop_queue((struct net_device *)
+ OSM_NOB(pnob)->os_handle);
+ adapter->be_stat.bes_tx_fails++;
+ spin_unlock_bh(&adapter->txq_lock);
+ return BE_ETH_TX_ERROR;
+ }
+ adapter->eth_tx_bytes += frame_size; /* for rate calculation */
+ /*
+ * TX rate calculation. If one second has passed since
+ * last calculation update the rate now.
+ */
+ UPDATE_RATE(adapter, eth_tx_jiffies, eth_tx_bytes,
+ bes_eth_tx_rate);
+ if (nfrags & 1)
+ nfrags++;
+
+ adapter->be_stat.bes_tx_wrbs += nfrags;
+
+ /* Ring the send doorbell */
+ bni_start_tx(pnob, nfrags);
+ spin_unlock_bh(&adapter->txq_lock);
+
+ TRACE(DL_SEND, "betx_ether_frame() - Exit");
+ return BE_SUCCESS;
+
+ max_tx_frag_error:
+ /*
+ * This skb cannot be transmitted since it exceeds max tx frag count
+ * Return with appropriate error
+ */
+ printk(KERN_WARNING "%s: Exceeds Max Tx Frags\n", __FUNCTION__);
+ return BE_ETH_TX_ERROR; /*//Set the proper error code */
+}
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
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review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
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^ permalink raw reply
* [PATHCH 3/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:31 UTC (permalink / raw)
To: netdev
ethtool, proc files, Kconfig, Makefile etc.
----------------------------------
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/bni.c benet/linux-2.6.24.2/drivers/net/benet/bni.c
--- orig/linux-2.6.24.2/drivers/net/benet/bni.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/bni.c 2008-02-14 15:23:07.794207864 +0530
@@ -0,0 +1,1506 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+
+@file
+ bni.c
+
+@brief
+ This file contains finctions that will be used by the BladeEngine
+ Network drivers to access BladeEngine Hardware. All code in
+ this file must be completely OS neutral.
+
+*/
+
+#include "bni.h"
+
+/*
+ * Initial Interrupt coalascing related parameters.
+ * Never enable Watermark on Compl ring without eq_delay enabled
+ */
+u32 tx_cmpl_wm = CEV_WMARK_96; /* 0xffffffff to disable */
+u32 rx_cmpl_wm = CEV_WMARK_160; /* 0xffffffff to disable */
+u32 eq_delay; /* delay in 8usec units. 0xffffffff to disable */
+
+/*!
+ This function initializes the data structures in BNI / BECLIB for network
+ operation. The OSM driver must call this function before making any other
+ BNI call.
+
+ If this functions succeeds, the caller must call bni_cleanup() as part
+ of driver cleanup procedure.
+
+@param
+ chipobj - Address of the space allocated by OSM for FunctionObject
+ (BE_CHIP_OBJECT). The space for this is allocated by
+ OSM, but this object is maintained by BECLIB and is
+ opaque to OSM.
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+
+ */
+BESTATUS bni_init(PBE_CHIP_OBJECT chipobj)
+{
+ int r;
+ r = be_initialize_library();
+ if (r != BE_SUCCESS) {
+ TRACE(DL_ERR, "be_initialize_library() failed - %x\n", r);
+ goto error;
+ }
+ r = be_chip_object_create(chipobj);
+ if (r != BE_SUCCESS) {
+ TRACE(DL_ERR, "be_chip_object_create() failed - %x\n", r);
+ goto error;
+ }
+
+ error:
+ if (r != BE_SUCCESS) {
+ TRACE(DL_ERR, "bni_init failed. Cleaning up everything.");
+ }
+
+ return (r);
+}
+
+/*!
+ This function initializes the data structures in BNI / BECLIB for network
+ operation. The OSM driver must call this function before making any other
+ BNI call.
+
+@param
+ chipobj - Pointer to the chip object passed as argument
+ to bni_init().
+ */
+void bni_cleanup(PBE_CHIP_OBJECT chipobj)
+{
+ SA_ASSERT(chipobj);
+
+ be_chip_object_destroy(chipobj);
+}
+
+/*!
+@brief
+ This function initializes the BNI_NET_OBJECT for subsequent
+ network operations. As part of the initialization, this function
+ registers this device with beclib and creates the
+ required set of queues (rings) that are needed to interact
+ with BaldeEngine as a network NIC device and registers them
+ with BladeEngine.
+
+ Before calling this function, the OSM driver must have allocated
+ space for the NetObject structure, initialized the structure,
+ allocated DMAable memory for all the network queues that form
+ part of the NetObject and populated the start address (virtual)
+ and number of entries allocated for each queue in the NetObject structure.
+
+ The OSM driver must also have allocated memory to hold the
+ mailbox structure (MCC_MAILBOX) and post the physical address,
+ virtual addresses and the size of the mailbox memory in the
+ NetObj.mb_sgl. This structure is used by BECLIB for
+ initial communication with the embedded MCC processor. BECLIB
+ uses the mailbox until MCC rings are created for more efficient
+ communication with the MCC processor.
+
+ If the OSM driver wants to create multiple network interface for more
+ than one protection domain, it can call bni_create_netobj()
+ multiple times once for each protection domain. A Maximum of
+ 32 protection domains are supported.
+
+@param
+ pnob - Pointer to the NetObject structure
+ pbars - Pointer to the BAR address structure containing
+ the addresses assigned OS to various BARS of the
+ network PCI function of BladeEngine.
+
+ nbars - Number of BARs in the BAR structure.
+
+ sa_devp - Address of the space allocated for SA_DEVICE structure.
+ This structure is initialized by the BECLIB and is
+ opaque to the OSM drivers.
+
+ chipobj - Address of the space allocated by OSM for FunctionObject
+ (BE_CHIP_OBJECT). The space for this is allocated by OSM,
+ but this object is maintained by BECLIB and is
+ opaque to OSM.
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+*/
+BESTATUS
+bni_create_netobj(PBNI_NET_OBJECT pnob,
+ SA_DEV_BAR_LOCATIONS *pbars,
+ u32 nbars, SA_DEV *sa_devp, PBE_CHIP_OBJECT chipobj)
+{
+ BESTATUS Status = 0;
+ BOOLEAN eventable = FALSE, tx_no_delay = FALSE, rx_no_delay =
+ FALSE;
+ PBE_EQ_OBJECT eq_objectp = NULL;
+ PBE_FUNCTION_OBJECT pfob = &pnob->fn_obj;
+ SA_SGL sgl;
+ SA_STATUS r;
+ u32 tempSz;
+
+ memset(&sgl, 0, sizeof(SA_SGL));
+ r = sa_dev_create(pbars, nbars, 0, sa_devp);
+ if (r != SA_SUCCESS) {
+ TRACE(DL_ERR, "sa_dev_create() failed - %x\n", r);
+ return r;
+ }
+
+ Status = be_function_object_create(sa_devp,
+ BE_FUNCTION_TYPE_NETWORK,
+ &pnob->mb_sgl,
+ pfob,
+ chipobj);
+ if (Status != BE_SUCCESS) {
+ TRACE(DL_ERR, "be_function_object_create() failed - %x\n", r);
+ return Status;
+ /*
+ * the function object is ZERO'd so nothing to do after
+ * this .
+ */
+ }
+
+ if (tx_cmpl_wm == 0xffffffff)
+ tx_no_delay = TRUE;
+ if (rx_cmpl_wm == 0xffffffff)
+ rx_no_delay = TRUE;
+ /*
+ * now create the necessary rings
+ * Event Queue first.
+ */
+ if (pnob->event_q_len) {
+ (void)sa_sgl_create_contiguous(pnob->event_q,
+ pnob->event_q_pa,
+ pnob->event_q_len *
+ sizeof(EQ_ENTRY), &sgl);
+
+ Status = be_eq_create(pfob, &sgl, 4, pnob->event_q_len,
+ (u32) -1, /* CEV_WMARK_* or -1 */
+ eq_delay, /* in 8us units, or -1 */
+ &pnob->event_q_obj);
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+ pnob->event_q_id = be_eq_get_id(&pnob->event_q_obj);
+ pnob->event_q_created = 1;
+ eventable = TRUE;
+ eq_objectp = &pnob->event_q_obj;
+ }
+ /*
+ * Now Eth Tx Compl. queue.
+ */
+ if (pnob->txcq_len) {
+
+ (void)sa_sgl_create_contiguous(pnob->tx_cq, pnob->tx_cq_pa,
+ pnob->txcq_len *
+ sizeof(ETH_TX_COMPL), &sgl);
+ Status = be_cq_create(pfob, &sgl,
+ pnob->txcq_len * sizeof(ETH_TX_COMPL),
+ FALSE, /* solicted events, */
+ tx_no_delay, /* nodelay */
+ tx_cmpl_wm, /* Watermark encodings */
+ eq_objectp, &pnob->tx_cq_obj);
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+
+ pnob->tx_cq_id = be_cq_get_id(&pnob->tx_cq_obj);
+ pnob->tx_cq_created = 1;
+ }
+ /*
+ * Eth Tx queue
+ */
+ if (pnob->tx_q_len) {
+ BE_ETH_SQ_PARAMETERS ex_params = { 0 };
+ u32 type;
+
+ if (pnob->tx_q_port) {
+ /* TXQ to be bound to a specific port */
+ type = BE_ETH_TX_RING_TYPE_BOUND;
+ ex_params.port = pnob->tx_q_port - 1;
+ } else
+ type = BE_ETH_TX_RING_TYPE_STANDARD;
+
+ (void)sa_sgl_create_contiguous(pnob->tx_q, pnob->tx_q_pa,
+ pnob->tx_q_len *
+ sizeof(ETH_WRB), &sgl);
+ Status = be_eth_sq_create_ex(pfob, &sgl,
+ pnob->tx_q_len * sizeof(ETH_WRB),
+ type, 2,
+ &pnob->tx_cq_obj,
+ &ex_params, &pnob->tx_q_obj);
+
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+
+ pnob->tx_q_id = be_eth_sq_get_id(&pnob->tx_q_obj);
+ pnob->tx_q_created = 1;
+ }
+ /*
+ * Now Eth Broadcast Rx compl. Queue. VM NetObjects will not need this
+ */
+ if (pnob->bcrx_cq_len) {
+
+ (void)sa_sgl_create_contiguous(pnob->bcrx_cq,
+ pnob->bcrx_cq_pa,
+ pnob->bcrx_cq_len *
+ sizeof(ETH_RX_COMPL), &sgl);
+ Status = be_cq_create(pfob, &sgl,
+ pnob->bcrx_cq_len * sizeof(ETH_RX_COMPL),
+ FALSE, /* solicted events, */
+ rx_no_delay, /* nodelay */
+ rx_cmpl_wm, /* Watermark encodings */
+ eq_objectp, &pnob->bcrx_cq_obj);
+
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+
+ pnob->bcrx_cq_id = be_cq_get_id(&pnob->bcrx_cq_obj);
+ pnob->bcrx_cq_created = 1;
+ }
+ /*
+ * Now Eth Unicast Rx compl. queue. Always needed.
+ */
+ (void)sa_sgl_create_contiguous(pnob->ucrx_cq, pnob->ucrx_cq_pa,
+ pnob->ucrx_cq_len *
+ sizeof(ETH_RX_COMPL), &sgl);
+ Status = be_cq_create(pfob, &sgl,
+ pnob->ucrx_cq_len * sizeof(ETH_RX_COMPL),
+ FALSE, /* solicted events, */
+ rx_no_delay, /* nodelay */
+ rx_cmpl_wm, /* Watermark encodings */
+ eq_objectp, &pnob->ucrx_cq_obj);
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+
+ pnob->ucrx_cq_id = be_cq_get_id(&pnob->ucrx_cq_obj);
+ pnob->ucrx_cq_created = 1;
+
+ Status = be_eth_rq_set_frag_size(pfob,
+ pnob->rx_buf_size, /* desired frag size in bytes */
+ (u32 *) &tempSz); /* actual frag size set */
+ if (Status != BE_SUCCESS) {
+ be_eth_rq_get_frag_size(pfob, (u32 *) &pnob->rx_buf_size);
+ if ((pnob->rx_buf_size != 2048)
+ && (pnob->rx_buf_size != 4096)
+ && (pnob->rx_buf_size != 8192))
+ goto error_ret;
+ } else {
+ /*be_eth_rq_get_frag_size (pfob, (u32*)&pnob->rx_buf_size); */
+ if (pnob->rx_buf_size != tempSz) {
+ pnob->rx_buf_size = tempSz;
+ TRACE(DL_ERR,
+ "%s: Could not set desired frag size. using %d\n",
+ __FUNCTION__, pnob->rx_buf_size);
+ }
+ }
+ /*
+ * Eth RX queue. be_eth_rq_create() always assumes 2 pages size
+ */
+ (void)sa_sgl_create_contiguous(pnob->rx_q, pnob->rx_q_pa,
+ pnob->rx_q_len * sizeof(ETH_RX_D),
+ &sgl);
+ Status =
+ be_eth_rq_create(pfob, &sgl, &pnob->ucrx_cq_obj,
+ pnob->bcrx_cq_len ? &pnob->bcrx_cq_obj : NULL,
+ &pnob->rx_q_obj);
+
+ if (Status != BE_SUCCESS)
+ goto error_ret;
+
+ pnob->rx_q_id = be_eth_rq_get_id(&pnob->rx_q_obj);
+ pnob->rx_q_created = 1;
+
+ return BE_SUCCESS; /* All required queues created. */
+
+ error_ret:
+ /*
+ * Some queue creation failed. Clean up any we successfully created.
+ */
+ bni_destroy_netobj(pnob, sa_devp);
+ return Status;
+}
+
+/*!
+@brief
+ This function changes the EQ delay - the interval that BladeEngine
+ should wait after an event entry is made in an EQ before the host
+ is interrupted.
+
+@param
+ pnob - Pointer to the NetObject structure
+ Delay - The delay in microseconds. Must be between 0 and 240 and
+ must be a multiple of 8.
+
+@return
+ None
+*/
+BESTATUS bni_change_eqd(PBNI_NET_OBJECT pnob, u32 Delay)
+{
+ BESTATUS Status = 0;
+ PBE_EQ_OBJECT eq_objectp = NULL;
+ PBE_FUNCTION_OBJECT pfob = &pnob->fn_obj;
+
+ eq_objectp = &pnob->event_q_obj;
+
+ /*
+ * Caller must ensure Delay <= 240 and is a multiple of 8.
+ */
+ Status = be_eq_modify_delay(pfob, 1, &eq_objectp, &Delay,
+ NULL, NULL, NULL);
+ if (Status < 0)
+ TRACE(DL_ERR, "bni_change_eqd failed \n");
+
+ return Status;
+}
+
+/*!
+@brief
+ This function creates the MCC request and completion ring required
+ for communicating with the ARM processor. The caller must have
+ allocated required amount of memory for the MCC ring and MCC
+ completion ring and posted the virtual address and number of
+ entries in the corresponding members (mcc_q and mcc_cq) in the
+ NetObject struture.
+
+ When this call is completed, all further communication with
+ ARM will switch from mailbox to this ring.
+
+@param
+ pnob - Pointer to the NetObject structure. This NetObject
+ should have been created using a previous call to
+ bni_create_netobj()
+
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+*/
+BESTATUS bni_create_mcc_rings(PBNI_NET_OBJECT pnob)
+{
+ BESTATUS Status = 0;
+ SA_SGL sgl;
+ PBE_FUNCTION_OBJECT pfob = &pnob->fn_obj;
+
+ memset(&sgl, 0, sizeof(SA_SGL));
+
+ /*
+ * Create the MCC completion ring.
+ */
+ if (pnob->mcc_cq_len) {
+
+ (void)sa_sgl_create_contiguous(pnob->mcc_cq,
+ pnob->mcc_cq_pa,
+ pnob->mcc_cq_len *
+ sizeof(MCC_CQ_ENTRY), &sgl);
+
+ Status = be_cq_create(pfob, &sgl,
+ pnob->mcc_cq_len * sizeof(MCC_CQ_ENTRY),
+ FALSE, /* solicted events, */
+ TRUE, /* nodelay */
+ 0, /* 0 Watermark since Nodelay is true */
+ &pnob->event_q_obj,
+ &pnob->mcc_cq_obj);
+
+ if (Status != BE_SUCCESS)
+ return (Status);
+
+ pnob->mcc_cq_id = be_cq_get_id(&pnob->mcc_cq_obj);
+ pnob->mcc_cq_created = 1;
+ }
+ /*
+ * Now Eth Tx queue. Needed in DMA mode TX.
+ */
+ if (pnob->mcc_q_len) {
+
+ (void)sa_sgl_create_contiguous(pnob->mcc_q,
+ pnob->mcc_q_pa,
+ pnob->mcc_q_len *
+ sizeof(MCC_WRB), &sgl);
+
+ Status = be_mcc_ring_create(pfob,
+ &sgl,
+ pnob->mcc_q_len *
+ sizeof(MCC_WRB),
+ pnob->mcc_wrb_ctxt,
+ pnob->mcc_wrb_ctxtLen,
+ &pnob->mcc_cq_obj,
+ &pnob->mcc_q_obj);
+
+ if (Status != BE_SUCCESS)
+ return (Status);
+
+ /* be_mcc_get_id() is not exposed to drivers since we
+ * do not need post any commands directly. BECLib
+ * does it for us.
+ */
+ pnob->mcc_q_created = 1;
+ }
+ return (BE_SUCCESS);
+}
+
+/*!
+@brief
+ This function destroys a NetObject created using a previous call to
+ BeCreateNetObject(). All the queues associated with the NetObject are
+ de-registered from BladeEngine. The actual memory allocated for the
+ queues as well as the space allocated for the NetObject must be freed
+ by the OSM driver after this call returns.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+@return
+ None
+
+*/
+void bni_destroy_netobj(PBNI_NET_OBJECT pnob, SA_DEV *sa_devp)
+{
+
+ BESTATUS beStatus;
+
+ /* free the queues */
+
+ if (pnob->tx_q_created) {
+ beStatus = be_eth_sq_destroy(&pnob->tx_q_obj);
+ pnob->tx_q_created = 0;
+ }
+
+ if (pnob->rx_q_created) {
+ beStatus = be_eth_rq_destroy(&pnob->rx_q_obj);
+ if (beStatus != 0) {
+ beStatus =
+ be_eth_rq_destroy_options(&pnob->rx_q_obj, 0,
+ NULL, NULL);
+ SA_ASSERT(0 == beStatus);
+ }
+ pnob->rx_q_created = 0;
+ }
+
+ bni_process_rx_flush_cmpl(pnob);
+
+ if (pnob->tx_cq_created) {
+ beStatus = be_cq_destroy(&pnob->tx_cq_obj);
+ pnob->tx_cq_created = 0;
+ }
+
+ if (pnob->bcrx_cq_created) {
+ beStatus = be_cq_destroy(&pnob->bcrx_cq_obj);
+ pnob->bcrx_cq_created = 0;
+ }
+
+ if (pnob->ucrx_cq_created) {
+ beStatus = be_cq_destroy(&pnob->ucrx_cq_obj);
+ pnob->ucrx_cq_created = 0;
+ }
+
+ if (pnob->mcc_q_created) {
+ beStatus = be_mcc_ring_destroy(&pnob->mcc_q_obj);
+ pnob->mcc_q_created = 0;
+ }
+ if (pnob->mcc_cq_created) {
+ beStatus = be_cq_destroy(&pnob->mcc_cq_obj);
+ pnob->mcc_cq_created = 0;
+ }
+
+ if (pnob->event_q_created) {
+ beStatus = be_eq_destroy(&pnob->event_q_obj);
+ pnob->event_q_created = 0;
+ }
+ /*
+ * This will cleanup all the other functions, including page tables,
+ * jell, templates, etc.
+ */
+ be_function_cleanup(&pnob->fn_obj);
+
+ /* Cleanup the SA device object. */
+ sa_dev_destroy(sa_devp);
+
+}
+
+/*!
+
+@brief
+ This function processes the Flush Completions that are issued by the
+ ARM F/W, when a Recv Ring is destroyed.
+ A flush completion is identified when a Rx COmpl descriptor has
+ the tcpcksum and udpcksum set and the pktsize is 32.
+ These completions are received on the Unicast Rx Completion Queue.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+@return
+ Number of Flush Completions processed.
+
+*/
+u32 bni_process_rx_flush_cmpl(PBNI_NET_OBJECT pnob)
+{
+ PETH_RX_COMPL rxcp;
+ unsigned int i = 0;
+ while ((rxcp = bni_get_ucrx_cmpl(pnob)) != NULL) {
+ bni_notify_cmpl(pnob, 1, pnob->ucrx_cq_id, 1);
+ i++;
+ }
+ return i;
+}
+
+/*!
+@brief
+ This Function fills in required number of WRBs in the ether send ring
+ for transmitting the given ether frame. The entire ether frame can be
+ in one or more scattered locations. The physical address of the
+ fragments and the count of the bytes in each fragment are indicated
+ by a fragment list pointer. Pointer to an opaque context is also
+ passed to this function. This context is stored in the array
+ NetObj.tx_ctxt[] at the same index as that of the
+ last WRB entry used for this request. OSM driver can retrieve
+ this context from this array at the wrb_index indicated by the
+ completion status entry for this transmit and use it to identify
+ the request and do appropriate processing when the transmit is completed.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ txb_list - Pointer to the fragment list describing the ether
+ frame fragments to be transmitted
+
+ flags - A 32 bit flag indicating a required transmit option. The
+ Valid options are :
+
+ IPCS - Enable IP checksum offload
+ UDPCS - Enable UDP checksum offload
+ TCPCS - Enable TCP checksum offload
+ LSO - Enable Large Segmnet offload
+ ETHVLAN - Insert VLAN
+ ETHEVENT - Enable event generation on completion
+ ETHCOMPLETE - Enable completion generation on completion
+ IPSEC - Enable IPSEC
+ FORWARD - Send in the Forwarding Path
+
+ vlant - VLAN tag to be inserted (if ETHVLAN set in flags)
+
+ mss - Mss to be used if LSO is enabled.
+
+ ctxtp - An OSM context handle that the OSM can use to
+ identify a completion with a send request.
+
+ nfrags - Number of fragments in the txb_list (1 to 15)
+
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+
+*/
+BESTATUS
+bni_tx_pkt(PBNI_NET_OBJECT pnob,
+ PBNI_TX_FRAG_LIST txb_list,
+ u32 flags, u32 vlant, u32 mss, void *ctxtp, u32 nfrags)
+{
+ PETH_WRB first_wrb, curr_wrb;
+ int txq_hd;
+ u32 fi, total_frags;
+
+ if (((pnob->tx_q_len - 2) - pnob->tx_q_used) > nfrags) {
+ if (nfrags & 1)
+ total_frags = nfrags + 1;
+ else
+ total_frags = nfrags;
+ } else {
+ return BE_NOT_OK;
+ }
+
+ sa_atomic_add((u32) total_frags, (u32 *) &pnob->tx_q_used);
+
+ /* Store number of WRBS for this pkt in 1st WRb of this pkt */
+ *(u32 *) (&(pnob->tx_ctxt[pnob->tx_q_hd])) = total_frags;
+
+ /*
+ * fill in the first WRB depending on the options passed to us,
+ */
+ txq_hd = pnob->tx_q_hd;
+ curr_wrb = &pnob->tx_q[txq_hd];
+ first_wrb = curr_wrb;
+
+ *((u32 *) curr_wrb + 2) = 0x00000000;
+ *((u32 *) curr_wrb + 3) = 0x00000000;
+ curr_wrb->crc = 1;
+
+ if (flags & LSO) {
+ curr_wrb->lso = 1;
+ curr_wrb->lso_mss = mss;
+ } else {
+ if (flags & TCPCS) {
+ curr_wrb->tcpcs = 1;
+ }
+ if (flags & IPCS) {
+ curr_wrb->ipcs = 1;
+ }
+ if (flags & UDPCS) {
+ curr_wrb->udpcs = 1;
+ }
+ }
+
+ /* Transmit the packet in forwarding path for loopback packet */
+ if (flags & FORWARD) {
+ curr_wrb->forward = 1;
+ }
+
+ curr_wrb->vlan_tag = vlant;
+ if (flags & ETHVLAN) {
+ curr_wrb->vlan = 1;
+ }
+
+ if (flags & ETHEVENT) {
+ curr_wrb->event = 1;
+ }
+ curr_wrb->last = 0;
+ curr_wrb->frag_pa_hi = txb_list[0].txb_pa_hi;
+ curr_wrb->frag_pa_lo = txb_list[0].txb_pa_lo;
+ curr_wrb->frag_len = txb_list[0].txb_len;
+ /*
+ * Fill in rest of the WRBs. Only the fragment address and count
+ * are different from the first WRB. So just copy other words from
+ * the first WRB.
+ *
+ */
+ for (fi = 1; fi < nfrags; fi++) {
+ bni_adv_txq_hd(pnob);
+ txq_hd = pnob->tx_q_hd;
+ curr_wrb = &pnob->tx_q[txq_hd];
+
+ *((u32 *) curr_wrb + 2) = *((u32 *) first_wrb + 2);
+ *((u32 *) curr_wrb + 3) = *((u32 *) first_wrb + 3);
+ curr_wrb->frag_pa_hi = txb_list[fi].txb_pa_hi;
+ curr_wrb->frag_pa_lo = txb_list[fi].txb_pa_lo;
+ curr_wrb->frag_len = txb_list[fi].txb_len;
+ }
+ /*
+ * BladeEngine does not like odd number of WRBs. make it even
+ * with a dummy entry
+ */
+ if (nfrags & 1) {
+ bni_adv_txq_hd(pnob);
+ txq_hd = pnob->tx_q_hd;
+ curr_wrb = &pnob->tx_q[txq_hd];
+
+ *((u32 *) curr_wrb + 2) = *((u32 *) first_wrb + 2);
+ *((u32 *) curr_wrb + 3) = *((u32 *) first_wrb + 3);
+ curr_wrb->frag_pa_lo = 0;
+ curr_wrb->frag_pa_hi = 0;
+ curr_wrb->frag_len = 0;
+ }
+ /*
+ * Fix up the last fragment
+ */
+ if (flags & ETHCOMPLETE) {
+ curr_wrb->complete = 1;
+ }
+ curr_wrb->last = 1;
+
+ /*
+ * pnob->tx_q_hd-1 represents the last wrb index of
+ * this packet. That will be the wrb index that we will get
+ * in Tx completion
+ */
+ pnob->tx_ctxt[pnob->tx_q_hd] = ctxtp;
+ bni_adv_txq_hd(pnob);
+
+ return BE_SUCCESS;
+}
+
+/*!
+
+@brief
+ This function writes the number of posted WRBs into the doorbell
+ to kick off the actual transmit of the ether frames whose
+ addresses are filled in the ether send ring by the function
+ bni_tx_pkt().
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ NumPosted - Number of WRBs filled in.
+
+*/
+void bni_start_tx(PBNI_NET_OBJECT pnob, u32 NumPosted)
+{
+#define CSR_ETH_MAX_SQPOSTS 255
+ SQ_DB sqdb;
+
+ TOU32(sqdb) = 0;
+
+ sqdb.cid = pnob->tx_q_id;
+ while (NumPosted) {
+ if (NumPosted > CSR_ETH_MAX_SQPOSTS) {
+ sqdb.numPosted = CSR_ETH_MAX_SQPOSTS;
+ NumPosted -= CSR_ETH_MAX_SQPOSTS;
+ } else {
+ sqdb.numPosted = NumPosted;
+ NumPosted = 0;
+ }
+ PD_WRITE(NET_FH(pnob), etx_sq_db, sqdb);
+ }
+
+ return;
+}
+
+/*!
+
+@brief
+ This function posts receive buffers to the ether receive queue.
+ The caller must allocate the buffers, populate the addresses in
+ list of BNI_RECV_BUFFER structures and pass the address of this
+ list. The number of the receive buffers in the list should not be
+ more than 255. If the list has more than 255 receive buffers or
+ the RX ring has less free slots than the number of buffers in
+ the list, the function will post whatever buffers it can in the
+ available free slots in the RX ring and remove these entries from
+ the list. The caller is responsible for freeing the remaining
+ buffers in the list.
+
+ The OSM driver must have filled in the context handle for each
+ BNI_RECV_BUFFER entry in the member context1. This function stores
+ the handle in the array NetObj.rx_ctxt at the index
+ corresponding to the entry in the recieve buffer queue where the
+ buffer was posted. OSM driver can retrieve this context information
+ using the fragndx field in the RX completion descriptor and use it
+ for the receive completion processing.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ rxb_list - A List of PBNI_RECV_BUFFER structures that hold the
+ free recv buffer address.
+
+@return
+ Number of buffers that were posted to this queue
+
+*/
+u32 bni_post_rx_buffs(PBNI_NET_OBJECT pnob, PSA_LIST_ENTRY rxb_list)
+{
+ PSA_LIST_ENTRY list_element;
+ u32 nposted = 0;
+ PETH_RX_D pRxDescr = NULL;
+ PBNI_RECV_BUFFER rxbp;
+ PVOID *rx_ctxp;
+ RQ_DB rqdb;
+
+ pRxDescr = pnob->rx_q;
+ rx_ctxp = pnob->rx_ctxt;
+
+ SA_ASSERT(pRxDescr);
+ SA_ASSERT(rx_ctxp);
+
+ while (!IsListEmpty(rxb_list) &&
+ (rx_ctxp[pnob->rx_q_hd] == NULL) && nposted < 255) {
+
+ list_element = RemoveHeadList(rxb_list);
+
+ rxbp =
+ SA_CONTAINING_RECORD(list_element, BNI_RECV_BUFFER,
+ rxb_list);
+
+ pRxDescr[pnob->rx_q_hd].fragpa_lo = rxbp->rxb_pa_lo;
+ pRxDescr[pnob->rx_q_hd].fragpa_hi = rxbp->rxb_pa_hi;
+
+ rx_ctxp[pnob->rx_q_hd] = rxbp->rxb_ctxt;
+ bni_adv_rxq_hd(pnob);
+
+ nposted++;
+
+ }
+
+ if (nposted) {
+ /* Now press the door bell to notify BladeEngine. */
+ TOU32(rqdb) = 0;
+ rqdb.numPosted = nposted;
+ rqdb.rq = pnob->rx_q_id;
+ PD_WRITE(NET_FH(pnob), erx_rq_db, rqdb);
+ }
+
+ pnob->rx_q_posted += nposted;
+ return nposted;
+}
+
+/*!
+
+@brief
+ This function checks the Eth send completion queue and returns
+ the address of the TX completion entry at the tail of the completion
+ queue. If no valid completion is present, this function returns NULL.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+@return
+ If a valid entry is found, it returns the pointer to ETH_TX_COMPL
+ If no valid entry is found, NULL is returned
+
+*/
+PETH_TX_COMPL bni_get_tx_cmpl(PBNI_NET_OBJECT pnob)
+{
+ PETH_TX_COMPL txcp = &pnob->tx_cq[pnob->tx_cq_tl];
+
+ if (txcp->valid == 0)
+ return (NULL);
+
+ SA_ASSERT(txcp->ct == 0);
+ SA_ASSERT(txcp->wrb_index < (u32) pnob->tx_q_len);
+ SA_ASSERT(txcp->ringid == pnob->tx_q_id);
+
+ txcp->valid = 0;
+ bni_adv_txcq_tl(pnob);
+ return (txcp);
+
+}
+
+/*!
+
+@brief
+ This function checks the Eth unicast receive completion queue and returns
+ the address of the RX completion entry at the tail of the completion
+ queue. If no valid completion is present, this function returns NULL.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+@return
+ If a valid entry is found, it returns the pointer to ETH_RX_COMPL
+ If no valid entry is found, NULL is returned
+
+*/
+PETH_RX_COMPL bni_get_ucrx_cmpl(PBNI_NET_OBJECT pnob)
+{
+ PETH_RX_COMPL rxcp = &pnob->ucrx_cq[pnob->ucrx_cq_tl];
+
+ if (rxcp->valid == 0)
+ return (NULL);
+
+ if (rxcp->ct != 0) {
+ rxcp->err = 1;
+
+ TRACE(DL_ERR, "Invalid chute %d in ucrx cmpl\n", rxcp->ct);
+ }
+
+ SA_ASSERT(rxcp->fragndx >= 0);
+ SA_ASSERT(rxcp->fragndx < pnob->rx_q_len);
+ SA_ASSERT(rxcp->pktsize <= ((pnob->rx_buf_size) * (rxcp->numfrags)));
+
+ bni_adv_ucrxcq_tl(pnob);
+ rxcp->valid = 0;
+ return (rxcp);
+}
+
+/*!
+
+@brief
+ This function checks the Eth broadcast receive completion queue and returns
+ the address of the RX completion entry at the tail of the completion
+ queue. If no valid completion is present, this function returns NULL.
+
+@param
+ pnob - Pointer to NetObject
+
+@return
+ If a valid entry is found, it returns the pointer to ETH_RX_COMPL
+ If no valid entry is found, NULL is returned
+
+*/
+PETH_RX_COMPL bni_get_bcrx_cmpl(PBNI_NET_OBJECT pnob)
+{
+ PETH_RX_COMPL rxcp = &pnob->bcrx_cq[pnob->bcrx_cq_tl];
+
+ if (rxcp->valid == 0)
+ return (NULL);
+
+ SA_ASSERT(rxcp->ct == 0);
+ SA_ASSERT(rxcp->fragndx >= 0);
+ SA_ASSERT(rxcp->fragndx < pnob->rx_q_len);
+ SA_ASSERT(rxcp->pktsize <= pnob->rx_buf_size);
+
+ bni_adv_bcrxcq_tl(pnob);
+ rxcp->valid = 0;
+ return (rxcp);
+}
+
+/*!
+
+@brief
+ This function notifies BladeEngine of the number of completion
+ entries processed from the specified completion queue by writing
+ the number of popped entries to the door bell.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ n - Number of completion entries processed
+
+ cq_id - Queue ID of the completion queue for which notification
+ is being done.
+
+ re_arm - 1 - rearm the completion ring to generate an event.
+ - 0 - dont rearm the completion ring to generate an event
+
+*/
+void bni_notify_cmpl(PBNI_NET_OBJECT pnob, int n, int cq_id, int re_arm)
+{
+
+ CQ_DB sqdb;
+
+ TOU32(sqdb) = 0;
+ sqdb.qid = cq_id;
+ sqdb.rearm = re_arm;
+ sqdb.num_popped = n;
+
+ PD_WRITE(NET_FH(pnob), cq_db, sqdb);
+}
+
+/*!
+@brief
+ This function enables the interrupt corresponding to the Event
+ queue ID for the given NetObject
+
+@param
+ pnob - Pointer to the NetObject structure
+*/
+
+/*
+ * Doorbell, enable/disable of EQ interrupts. This will not mask
+ * the UE interrupt.
+ */
+void bni_enable_eq_intr(PBNI_NET_OBJECT pnob)
+{
+ CQ_DB cq_db;
+
+ SA_ASSERT(pnob);
+
+ cq_db.dw = 0; /* clear entire doorbell */
+
+ cq_db.event = 1;
+ cq_db.rearm = 1;
+ cq_db.num_popped = 0;
+ cq_db.qid = pnob->event_q_id;
+
+ PD_WRITE(NET_FH(pnob), cq_db, cq_db);
+}
+
+/*!
+@brief
+ This function disables the interrupt corresponding to the Event
+ queue ID for the given NetObject
+
+@param
+ pnob - Pointer to the NetObject structure
+*/
+void bni_disable_eq_intr(PBNI_NET_OBJECT pnob)
+{
+ CQ_DB cq_db;
+
+ SA_ASSERT(pnob);
+
+ cq_db.dw = 0; /* clear entire doorbell */
+
+ cq_db.event = 1;
+ cq_db.rearm = 0;
+ cq_db.num_popped = 0;
+ cq_db.qid = pnob->event_q_id;
+
+ PD_WRITE(NET_FH(pnob), cq_db, cq_db);
+}
+
+/*!
+
+@brief
+ This function enables the interrupt from the network function
+ of the BladeEngine. Use the function bni_disable_eq_intr()
+ to enable the interrupt from the event queue of only one specific
+ NetObject
+
+@param
+ pnob - Pointer to the NetObject structure
+
+*/
+void bni_enable_intr(PBNI_NET_OBJECT pnob)
+{
+
+ PCICFG_HOST_TIMER_INT_CTRL_CSR ctrl;
+
+ SA_ASSERT(pnob);
+
+ ctrl.dw = PCICFG1_READ(NET_FH(pnob), host_timer_int_ctrl);
+ if (!ctrl.hostintr) {
+ ctrl.hostintr = 1;
+ TRACE(DL_INFO, "Enabling Interrupt.\n");
+ PCICFG1_WRITE_CONST(NET_FH(pnob), host_timer_int_ctrl, ctrl.dw);
+ }
+}
+
+/*!
+
+@brief
+ This function disables the interrupt from the network function of
+ the BladeEngine. Use the function bni_disable_eq_intr() to
+ disable the interrupt from the event queue of only one specific NetObject
+
+@param
+ pnob - Pointer to the NetObject structure
+
+*/
+void bni_disable_intr(PBNI_NET_OBJECT pnob)
+{
+
+ PCICFG_HOST_TIMER_INT_CTRL_CSR ctrl;
+
+ SA_ASSERT(pnob);
+
+ ctrl.dw = PCICFG1_READ(NET_FH(pnob), host_timer_int_ctrl);
+ if (ctrl.hostintr) {
+ ctrl.hostintr = 0;
+ TRACE(DL_INFO, "Disable Interrupt.\n");
+ PCICFG1_WRITE_CONST(NET_FH(pnob), host_timer_int_ctrl, ctrl.dw);
+ }
+}
+
+/*
+
+@brief
+ This function reads the ISR and returns the value read. ISR is
+ a clear-on-read register
+
+@param
+ pnob - Pointer to the NetObject structure
+@return
+ Returns the 32 bit value in the ISR
+
+*/
+u32 bni_get_isr(PBNI_NET_OBJECT pnob)
+{
+ return (CSR_READ(NET_FH(pnob), cev.isr1));
+}
+
+/*!
+
+@brief
+ This function checks the event queue for a valid event. If a valid
+ entry is found, it returns pointer to the entry. The client is
+ responsible for tracking the number of event queue items popped
+ out of this queue for subsequently ringing the event queue doorbell.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+@return
+ Pointer to next valid event queue entry if one is found.
+ NULL if no valid entry is found.
+*/
+PEQ_ENTRY bni_get_event(PBNI_NET_OBJECT pnob)
+{
+ PEQ_ENTRY eqp = &(pnob->event_q[pnob->event_q_tl]);
+
+ if (!eqp->Valid)
+ return (NULL);
+ /*
+ * We got a Valid Event. Now increment the Event queue
+ * index to next event.
+ */
+ bni_adv_eq_tl(pnob);
+ return eqp;
+}
+
+/*!
+
+@brief
+ This function notifies BladeEngine of how many events were processed
+ from the event queue by ringing the corresponding door bell and
+ optionally re-arms the event queue.
+
+
+@param
+ pnob - Pointer to the NetObject structure
+ n - number of events processed
+ re_arm - 1 - re-arm the EQ, 0 - do not re-arm the EQ
+
+*/
+void bni_notify_event(PBNI_NET_OBJECT pnob, int n, int re_arm)
+{
+ CQ_DB eqdb;
+
+ TOU32(eqdb) = 0;
+ eqdb.qid = pnob->event_q_id;
+ eqdb.rearm = re_arm;
+ eqdb.event = 1;
+
+ eqdb.num_popped = n;
+
+ /*
+ * Under some situations we see an interrupt and no valid
+ * EQ entry. To keep going, we need to ring the DB even if
+ * numPOsted is 0.
+ */
+ PD_WRITE(NET_FH(pnob), cq_db, eqdb);
+
+ return;
+}
+
+/*!
+
+@brief
+ This function gets the current link status.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ lsp - Pointer to the stucture LINK_STATUS where the Link
+ status is to be returned.
+
+ cbf - Pointer to a function that will be called on completion.
+ If NULL, the call will block waiting for completion.
+
+ cbc - Opaque context argument that will be passed to the
+ completion call back function
+
+
+@return
+ none
+*/
+
+BESTATUS
+bni_get_link_sts(PBNI_NET_OBJECT pnob, PBE_LINK_STATUS lsp,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc)
+{
+ BESTATUS r;
+
+ r = be_rxf_link_status(NET_FH(pnob), lsp, cbf, cbc, NULL);
+
+ return (r);
+}
+
+/*!
+
+@brief
+ This function gets the specified MAC address from BladeEngine's MAC address
+ table.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ port - 0 for first port, 1 for second port.
+
+ instance - 0 for the first MAC address of the port, 1 for
+ the second instance of the AMC address for the port.
+
+ pd - The protection domain number (used only for
+ virtual machine)
+
+ mac_addr - Address the strcuture SA_MAC_ADDRESS where to return
+ the MAC address.
+
+ cbf - Pointer to a function that will be called on completion.
+ If NULL, the call will block waiting for completion.
+
+ cbc - Opaque context argument that will be passed to the
+ completion call back function.
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+*/
+
+BESTATUS
+bni_get_uc_mac_adrr(PBNI_NET_OBJECT pnob, u8 port,
+ u8 instance, u8 pd,
+ PSA_MAC_ADDRESS mac_addr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc)
+{
+ BESTATUS status;
+
+ if (pd) {
+ /* this call is for setting the VM MAC address */
+ port = 0;
+ instance = 0;
+ }
+
+ status = be_rxf_mac_address_read_write(NET_FH(pnob),
+ port,
+ instance,
+ FALSE, /* Not Management Mac */
+ FALSE, /* False for Read */
+ FALSE, mac_addr, cbf, cbc);
+
+ TRACE(DL_INFO, "be_rxf_mac_address_read_write Status is %d\n", status);
+ return status;
+}
+
+/*!
+
+@brief
+ This function sets the specified MAC address from BladeEngine's MAC address
+ table.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ port - 0 for first port, 1 for second port.
+
+ instance - 0 for the first MAC address of the port, 1 for
+ the second instance of the AMC address for the port.
+
+ pd - The protection domain number (used only for
+ virtual machie)
+
+ mac_addr - Address the strcuture SA_MAC_ADDRESS where the
+ MAC address to be set is stored.
+
+ cbf - Pointer to a function that will be called on completion.
+ If NULL, the call will block waiting for completion.
+
+ cbc - Opaque context argument that will be passed to the
+ completion call back function.
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+*/
+BESTATUS
+bni_set_uc_mac_adr(PBNI_NET_OBJECT pnob, u8 port,
+ u8 instance, u8 pd,
+ PSA_MAC_ADDRESS mac_addr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc)
+{
+ BESTATUS status;
+
+ if (pd) {
+ /* this call is for setting the VM MAC address */
+ port = 0;
+ instance = 0;
+ }
+
+ status = be_rxf_mac_address_read_write(NET_FH(pnob), port,
+ instance,
+ FALSE, /* Not Management Mac */
+ TRUE, /* TRUE for set */
+ FALSE, mac_addr, cbf, cbc);
+
+ TRACE(DL_INFO, "be_rxf_mac_address_read_write Status is %d\n", status);
+ return status;
+}
+
+/*!
+
+@brief
+ This function adds the given multicast MAC addresses into BE's
+ multicast filter table. The maximum number of multicast addresses
+ that can be added using this call is 32. More than 32 addresses
+ can be added through multiple calls.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ NumMac - number of MAC sddresses to be added - maximum is 32
+
+ Promiscuous - Whether to enable multicast promiscuous mode or not.
+ If 1, multicast promiscuous mode is enabled and the
+ parameters NumMac and mac_addr are ignored.
+ If this is not enabled, the multicast addresses in
+ the array mac_addr will programmed
+
+ mac_addr - Pointer to an address an array of type SA_MAC_ADDRESS
+
+ cbf - Pointer to a function that will be called on completion.
+ If NULL, the call will block waiting for completion.
+
+ cbc - Opaque context argument that will be passed to the
+ completion call back function.
+@return
+ none
+
+*/
+BESTATUS
+bni_set_mc_filter(PBNI_NET_OBJECT pnob,
+ u32 NumMac,
+ BOOLEAN promiscuous,
+ PSA_MAC_ADDRESS mac_addr,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc)
+{
+ BESTATUS status;
+
+ status = be_rxf_multicast_config(NET_FH(pnob), promiscuous,
+ NumMac,
+ mac_addr,
+ cbf, cbc, NULL);
+
+ return status;
+}
+
+/*!
+
+@brief
+ This function sets BE's network port into promiscuous mode.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+*/
+void bni_set_promisc(PBNI_NET_OBJECT pnob)
+{
+ /* Set promiscuous mode on both ports. */
+ be_rxf_promiscuous(NET_FH(pnob), 1, 1, NULL, NULL, NULL);
+}
+
+/*!
+
+@brief
+ This function takes BE's network port out of promiscuous mode.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+*/
+void bni_reset_promisc(PBNI_NET_OBJECT pnob)
+{
+ /* Reset promiscuous mode on both ports. */
+ be_rxf_promiscuous(NET_FH(pnob), 0, 0, NULL, NULL, NULL);
+}
+
+/*!
+
+@brief
+ This function configures the VLAN Id table of BladeEngine. If the table
+ has any VLAN, Vlan filtering is turned on. If there no VLANN Ids in the
+ table, VLAN filtering is turned off. BladeEngine supports a maximum of
+ 32 VLans.
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ vlanp - pointer to an array containing the VLAN IDs to be
+ configured.
+
+ nv - Number of Vlan IDs in the array.
+
+ cbf - Pointer to a function that will be called on completion.
+ If NULL, the call will block waiting for completion.
+
+ cbc - Opaque context argument that will be passed to the
+ completion call back function
+
+ promiscuous - Enable vlan Promiscuous mode or not. TRUE=Enable.
+
+@return
+ BESTATUS - (0 if successful, non-zero status code if not successful)
+
+*/
+BESTATUS
+bni_config_vlan(PBNI_NET_OBJECT pnob, u16 *vlanp, u32 nv,
+ MCC_WRB_CQE_CALLBACK cbf, PVOID cbc, BOOLEAN promiscuous)
+{
+ BESTATUS status;
+
+ status = be_rxf_vlan_config(NET_FH(pnob), promiscuous, nv, vlanp,
+ cbf, cbc, NULL);
+
+ return status;
+}
+
+/*!
+
+@brief
+ This function gets the ethernet port statistics from the ASIC
+
+@param
+ pnob - Pointer to the NetObject structure
+
+ ioctl_va - Virtual address of structure IOCTL_ETH_GET_STATISTICS
+
+ ioctl_pa - Physical address of structure IOCTL_ETH_GET_STATISTICS
+
+ cbf - Pointer to a function that will be
+ called on completion. If NULL, the call will block
+ waiting for completion.
+
+ cbc - Opaque context argument that will be passed to
+ the completion call back function
+
+
+*/
+BESTATUS
+bni_get_stats(PBNI_NET_OBJECT pnob,
+ IOCTL_ETH_GET_STATISTICS *ioctl_va,
+ u64 ioctl_pa, MCC_WRB_CQE_CALLBACK cbf, PVOID cbc)
+{
+ BESTATUS s;
+
+ SA_ASSERT(pnob);
+ SA_ASSERT(ioctl_va);
+ SA_ASSERT(ioctl_pa);
+
+ s = be_rxf_query_eth_statistics(NET_FH(pnob), ioctl_va, ioctl_pa,
+ cbf, cbc, NULL);
+
+ return (s);
+
+}
+
+/*!
+@brief
+ Wrapper function to Set Pause frame control
+@param
+ pfob - Pointer to the function object to read from.
+@param
+ txfc_enable - Boolean variable - 0 if TX flow control is to be
+ disabled, 1 if TX flow control is to be disabled.
+
+ rxfc_enable - Boolean variable - 0 if RX flow control is to be
+ disabled, 1 if XX flow control is to be disabled
+@return
+*/
+BESTATUS
+bni_set_flow_ctll(PBE_FUNCTION_OBJECT pfob, boolean txfc_enable,
+ boolean rxfc_enable)
+{
+ return be_eth_set_flow_control(pfob, txfc_enable, rxfc_enable);
+}
+
+/*!
+@brief
+ Wrapper function to Get Pause frame control
+@param
+ pfob - Pointer to the function object to read from.
+@param
+
+ txfc_enable - Pointer to a Boolean variable where the TX flow
+ control setting will be returned. 0 if the flow
+ control is disabled, 1 if flow control is disabled.
+
+ rxfc_enable - Pointer to a Boolean variable where the RX flow
+ control setting will be returned. 0 if the flow
+ control is disabled, 1 if flow control is disabled
+
+@return
+*/
+BESTATUS
+bni_get_flow_ctl(PBE_FUNCTION_OBJECT pfob, boolean *txfc_enable,
+ boolean *rxfc_enable)
+{
+ return be_eth_get_flow_control(pfob, txfc_enable, rxfc_enable);
+}
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_ethtool.c benet/linux-2.6.24.2/drivers/net/benet/be_ethtool.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_ethtool.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_ethtool.c 2008-02-14 15:23:07.795207712 +0530
@@ -0,0 +1,410 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+ * be_ethtool.c
+ *
+ * This file contains various functions that ethtool can use
+ * to talk to the driver and the BE H/W.
+ */
+
+#include <linux/pci.h>
+#include "be.h"
+
+#include <linux/ethtool.h>
+
+static const char benet_gstrings_stats[][ETH_GSTRING_LEN] = {
+/*net_device_stats */
+ "irq",
+ "rx_packets",
+ "tx_packets",
+ "rx_bytes",
+ "tx_bytes",
+ "rx_errors",
+ "tx_errors",
+ "rx_dropped",
+ "tx_dropped",
+ "multicast",
+ "collisions",
+ "rx_length_errors",
+ "rx_over_errors",
+ "rx_crc_errors",
+ "rx_frame_errors",
+ "rx_fifo_errors",
+ "rx_missed_errors",
+ "tx_aborted_errors",
+ "tx_carrier_errors",
+ "tx_fifo_errors",
+ "tx_heartbeat_errors",
+ "tx_window_errors",
+ "rx_compressed",
+ "tc_compressed",
+/*BE driver Stats */
+ "bes_tx_reqs",
+ "bes_tx_fails",
+ "bes_fwd_reqs",
+ "bes_tx_wrbs",
+ "bes_interrupts",
+ "bes_events",
+ "bes_tx_events",
+ "bes_ucrx_events",
+ "bes_bcrx_events",
+ "bes_tx_compl",
+ "bes_ucrx_compl",
+ "bes_bcrx_compl",
+ "bes_ethrx_post_fail",
+ "bes_802_3_dropped_frames",
+ "bes_802_3_malformed_frames",
+ "bes_eth_tx_rate",
+ "bes_eth_rx_rate",
+#ifdef RX_PKT_COALESCE
+ "Num Packets collected",
+ "Num Times Flushed",
+#endif
+};
+
+#define NET_DEV_STATS_LEN \
+ (sizeof(struct net_device_stats)/sizeof(unsigned long))
+#define BENET_STATS_LEN sizeof(benet_gstrings_stats) / ETH_GSTRING_LEN
+
+static void
+be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+
+ strncpy(drvinfo->driver, be_driver_name, 32);
+ strncpy(drvinfo->version, be_drvr_ver, 32);
+ strncpy(drvinfo->fw_version, be_fw_ver, 32);
+ strcpy(drvinfo->bus_info, pci_name(adapter->pdev));
+ drvinfo->testinfo_len = 0;
+ drvinfo->regdump_len = 0;
+ drvinfo->eedump_len = 0;
+}
+
+static int
+be_get_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *coalesce)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(NetObject)->adapter;
+
+#ifdef RX_PKT_COALESCE
+ coalesce->rx_max_coalesced_frames = adapter->max_rx_coal;
+#endif
+
+ coalesce->rx_coalesce_usecs = adapter->cur_eqd;
+ coalesce->rx_coalesce_usecs_high = adapter->max_eqd;
+ coalesce->rx_coalesce_usecs_low = adapter->min_eqd;
+
+ coalesce->tx_coalesce_usecs = adapter->cur_eqd;
+ coalesce->tx_coalesce_usecs_high = adapter->max_eqd;
+ coalesce->tx_coalesce_usecs_low = adapter->min_eqd;
+
+ coalesce->use_adaptive_rx_coalesce = adapter->enable_aic;
+ coalesce->use_adaptive_tx_coalesce = adapter->enable_aic;
+
+ return 0;
+}
+
+static int
+be_set_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *coalesce)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(NetObject)->adapter;
+ u32 max, min, cur;
+
+#ifdef RX_PKT_COALESCE
+ adapter->max_rx_coal = coalesce->rx_max_coalesced_frames;
+ if (adapter->max_rx_coal < 0)
+ adapter->max_rx_coal = 0;
+ if (adapter->max_rx_coal >= MAX_COALESCE_FRAGS)
+ adapter->max_rx_coal = MAX_COALESCE_FRAGS;
+#endif
+
+ if (adapter->enable_aic == 0 &&
+ coalesce->use_adaptive_rx_coalesce == 1) {
+ /* if AIC is being turned on now, start with an EQD of 0 */
+ adapter->cur_eqd = 0;
+ }
+ adapter->enable_aic = coalesce->use_adaptive_rx_coalesce;
+
+ /* round off to nearest multiple of 8 */
+ max = (((coalesce->rx_coalesce_usecs_high + 4) >> 3) << 3);
+ min = (((coalesce->rx_coalesce_usecs_low + 4) >> 3) << 3);
+ cur = (((coalesce->rx_coalesce_usecs + 4) >> 3) << 3);
+
+ if (adapter->enable_aic) {
+ /* accept low and high if AIC is enabled */
+ if (max > MAX_EQD)
+ min = MAX_EQD;
+ if (min > max)
+ min = max;
+ adapter->max_eqd = max;
+ adapter->min_eqd = min;
+ if (adapter->cur_eqd > max)
+ adapter->cur_eqd = max;
+ if (adapter->cur_eqd < min)
+ adapter->cur_eqd = min;
+ } else {
+ /* accept specified coalesce_usecs only if AIC is disabled */
+ if (cur > MAX_EQD)
+ cur = MAX_EQD;
+ if (bni_change_eqd(NetObject, cur) == BE_SUCCESS)
+ adapter->cur_eqd = cur;
+ }
+
+ return 0;
+}
+
+static u32 be_get_rx_csum(struct net_device *netdev)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(NetObject)->adapter;
+ return adapter->rx_csum;
+}
+
+static int be_set_rx_csum(struct net_device *netdev, uint32_t data)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(NetObject)->adapter;
+ if (data)
+ adapter->rx_csum = 1;
+ else
+ adapter->rx_csum = 0;
+
+ return 0;
+}
+
+static void
+be_get_strings(struct net_device *netdev, uint32_t stringset,
+ uint8_t *data)
+{
+
+ switch (stringset) {
+ case ETH_SS_STATS:
+ memcpy(data, *benet_gstrings_stats,
+ sizeof(benet_gstrings_stats));
+ break;
+ }
+}
+
+static int be_get_stats_count(struct net_device *netdev)
+{
+ return BENET_STATS_LEN;
+}
+
+static void
+be_get_ethtool_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, uint64_t *data)
+{
+ PBNI_NET_OBJECT pnob = netdev->priv;
+ PBE_ADAPTER adapter = OSM_NOB(pnob)->adapter;
+ int i;
+
+ data[0] = adapter->pdev->irq;
+
+ benet_get_stats(netdev);
+
+ for (i = 1; i <= NET_DEV_STATS_LEN; i++)
+ data[i] = ((unsigned long *)&adapter->benet_stats)[i - 1];
+
+ data[i++] = adapter->be_stat.bes_tx_reqs;
+ data[i++] = adapter->be_stat.bes_tx_fails;
+ data[i++] = adapter->be_stat.bes_fwd_reqs;
+ data[i++] = adapter->be_stat.bes_tx_wrbs;
+
+ data[i++] = adapter->be_stat.bes_ints;
+ data[i++] = adapter->be_stat.bes_events;
+ data[i++] = adapter->be_stat.bes_tx_events;
+ data[i++] = adapter->be_stat.bes_ucrx_events;
+ data[i++] = adapter->be_stat.bes_bcrx_events;
+ data[i++] = adapter->be_stat.bes_tx_compl;
+ data[i++] = adapter->be_stat.bes_ucrx_compl;
+ data[i++] = adapter->be_stat.bes_bcrx_compl;
+ data[i++] = adapter->be_stat.bes_ethrx_post_fail;
+ data[i++] = adapter->be_stat.bes_802_3_dropped_frames;
+ data[i++] = adapter->be_stat.bes_802_3_malformed_frames;
+
+ data[i++] = adapter->be_stat.bes_eth_tx_rate;
+ data[i++] = adapter->be_stat.bes_eth_rx_rate;
+
+#ifdef RX_PKT_COALESCE
+ data[i++] = adapter->be_stat.bes_rx_coal;
+ data[i++] = adapter->be_stat.bes_rx_flush;
+#endif
+
+}
+
+static int
+be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+
+ ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
+ ecmd->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
+ ecmd->port = PORT_FIBRE;
+ ecmd->transceiver = XCVR_EXTERNAL;
+
+ if (netif_carrier_ok(OSM_NOB(NetObject)->os_handle)) {
+ ecmd->speed = SPEED_10000;
+ ecmd->duplex = DUPLEX_FULL;
+ } else {
+ ecmd->speed = -1;
+ ecmd->duplex = -1;
+ }
+
+ ecmd->autoneg = AUTONEG_DISABLE;
+ return 0;
+}
+
+/*Get the Ring parameters from the NetObject */
+static void
+be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+
+ /*Pre Set Maxims */
+ ring->rx_max_pending = NetObject->rx_q_len;
+ ring->rx_mini_max_pending = ring->rx_mini_max_pending;
+ ring->rx_jumbo_max_pending = ring->rx_jumbo_max_pending;
+ ring->tx_max_pending = NetObject->tx_q_len;
+
+ /*Current hardware Settings */
+ ring->rx_pending = NetObject->rx_q_posted;
+ ring->rx_mini_pending = ring->rx_mini_pending;
+ ring->rx_jumbo_pending = ring->rx_jumbo_pending;
+ ring->tx_pending = NetObject->tx_q_used;
+
+}
+
+static void
+be_get_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *ecmd)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ boolean rxfc = FALSE;
+ boolean txfc = FALSE;
+ if (ecmd->cmd != ETHTOOL_GPAUSEPARAM) {
+ return;
+ }
+
+ if (bni_get_flow_ctl(&NetObject->fn_obj, &txfc, &rxfc) !=
+ BE_SUCCESS) {
+ printk(KERN_WARNING
+ "Unable to get pause frame settings\n");
+ }
+
+ if (txfc == TRUE)
+ ecmd->tx_pause = 1;
+ else
+ ecmd->tx_pause = 0;
+
+ if (rxfc == TRUE)
+ ecmd->rx_pause = 1;
+ else
+ ecmd->rx_pause = 0;
+
+ /* Always setting autoneg to TRUE */
+ ecmd->autoneg = 1;
+
+ return;
+}
+
+static int
+be_set_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *ecmd)
+{
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+ boolean txfc = FALSE;
+ boolean rxfc = FALSE;
+
+ if (ecmd->cmd != ETHTOOL_SPAUSEPARAM)
+ return -EINVAL;
+
+ if (ecmd->tx_pause)
+ txfc = TRUE;
+ else
+ txfc = FALSE;
+
+ if (ecmd->rx_pause)
+ rxfc = TRUE;
+ else
+ rxfc = FALSE;
+
+ if (bni_set_flow_ctll(&NetObject->fn_obj, txfc, rxfc) != BE_SUCCESS) {
+ printk(KERN_ERR "Unable to set pause frame settings\n");
+ }
+ return 0;
+}
+
+struct ethtool_ops be_ethtool_ops = {
+ .get_settings = be_get_settings,
+ .get_drvinfo = be_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+#ifdef RX_PKT_COALESCE
+ .get_coalesce = be_get_coalesce,
+ .set_coalesce = be_set_coalesce,
+#endif
+ .get_ringparam = be_get_ringparam,
+ .get_pauseparam = be_get_pauseparam,
+ .set_pauseparam = be_set_pauseparam,
+ .get_rx_csum = be_get_rx_csum, /*Yes */
+ .set_rx_csum = be_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum, /*Yes */
+ .set_tx_csum = ethtool_op_set_tx_csum, /*Yes */
+ .get_sg = ethtool_op_get_sg, /*Yes */
+ .set_sg = ethtool_op_set_sg, /*Yes */
+#ifdef NETIF_F_TSO
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = ethtool_op_set_tso,
+#endif
+ .get_strings = be_get_strings,
+ .get_stats_count = be_get_stats_count,
+ .get_ethtool_stats = be_get_ethtool_stats,
+};
+
+void be_set_ethtool_ops(struct net_device *netdev)
+{
+ SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
+}
+
+int be_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr)
+{
+ void *addr = ifr->ifr_data;
+ uint32_t cmd;
+
+ if (get_user(cmd, (uint32_t *) addr))
+ return -EFAULT;
+
+ return -EOPNOTSUPP;
+}
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/be_proc.c benet/linux-2.6.24.2/drivers/net/benet/be_proc.c
--- orig/linux-2.6.24.2/drivers/net/benet/be_proc.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/be_proc.c 2008-02-14 15:23:07.796207560 +0530
@@ -0,0 +1,679 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include "be.h"
+
+extern PBE_ADAPTER be_adapter[];
+
+char *be_adpt_name[] = {
+ "driver/benet0",
+ "driver/benet1"
+};
+
+struct proc_dir_entry *be_proc_dir[MAX_BE_DEVICES];
+
+/* path under /proc */
+#define BE_PORT_STAT_FILE "port_stat"
+#define BE_MISC_STAT_FILE "misc_stat"
+#define BE_DRVR_STAT_FILE "drvr_stat"
+
+/*File to read Eth Ring Information */
+#define BE_ETH_RING_FILE "eth_ring"
+
+/*File to read/set dbg_mask */
+#define BE_DBG_MASK "dbg_mask"
+
+#define BE_PROC_MODE 0600
+
+#define BE_PORT0_STAT_INDEX 0x00 /* index to read first port0 stat */
+#define BE_PORT1_STAT_INDEX 0x3B /* index to read first port1 stat */
+#define BE_MISC_STAT_INDEX 0x76 /* index to read first misc stat */
+#define BE_LAST_STAT_INDEX 0x95 /* last index */
+/*
+ * descriptor strings for port statistics
+ */
+char *stat_desc_port[] = {
+ /* 0x00 */ "total bytes received OK (LSD)",
+ /* 0x01 */ "total bytes received OK (MSD)",
+ /* 0x02 */ "total frames received OK",
+ /* 0x03 */ "unicast frames received OK",
+ /* 0x04 */ "multicast frames received OK",
+ /* 0x05 */ "broadcast frames received OK",
+ /* 0x06 */ "CRC errors",
+ /* 0x07 */ "alignment/bad symbol errors",
+ /* 0x08 */ "PAUSE frames received",
+ /* 0x09 */ "control frames received",
+ /* 0x0a */ "in range length errors 1",
+ /* 0x0b */ "out of range length errors 2",
+ /* 0x0c */ "frame too long errors 3",
+ /* 0x0d */ "dropped due to address mismatch",
+ /* 0x0e */ "dropped due to vlan mismatch",
+ /* 0x0f */ "dropped ip too small (ip length < ip header len)",
+ /* 0x10 */ "dropped ip too short (ip length > pkt len)",
+ /* 0x11 */ "dropped ip header too small (ip header len < 5)",
+ /* 0x12 */ "dropped bad tcp header length",
+ /* 0x13 */ "received runt pkts",
+ /* 0x14 */ "received 64 byte pkts",
+ /* 0x15 */ "received pkts 65 to 127 bytes",
+ /* 0x16 */ "received pkts 128 to 255 bytes",
+ /* 0x17 */ "received pkts 256 to 511 bytes",
+ /* 0x18 */ "received pkts 512 to 1023 bytes",
+ /* 0x19 */ "received pkts 1024 to 1518 bytes",
+ /* 0x1a */ "received pkts 1519 to 2047 bytes",
+ /* 0x1b */ "received pkts 2048 to 4095 bytes",
+ /* 0x1c */ "received pkts 4096 to 8191 bytes",
+ /* 0x1d */ "received pkts 8192 to 9216 bytes",
+ /* 0x1e */ "received IP checksum errors",
+ /* 0x1f */ "received TCP checksum errors",
+ /* 0x20 */ "received UDP checksum errors",
+ /* 0x21 */ "non-RSS pkts received",
+ /* 0x22 */ "IP pkts received (good and bad)",
+ /* 0x23 */ "chute 1 offloaded pkts received",
+ /* 0x24 */ "chute 2 offloaded pkts received",
+ /* 0x25 */ "chute 3 offloaded pkts received",
+ /* 0x26 */ "IPSEC pkts received",
+ /* 0x27 */ "mgmt pkts received",
+ /* 0x28 */ "bytes transmitted OK (LSD)",
+ /* 0x29 */ "total bytes transmitted OK (MSD)",
+ /* 0x2a */ "unicast frames transmitted OK",
+ /* 0x2b */ "multicast frames transmitted OK",
+ /* 0x2c */ "broadcast frames transmitted OK",
+ /* 0x2d */ "PAUSE frames sent",
+ /* 0x2e */ "control frames sent",
+ /* 0x2f */ "transmitted 64 byte pkts",
+ /* 0x30 */ "transmitted pkts 65 to 127 bytes",
+ /* 0x31 */ "transmitted pkts 128 to 255 bytes",
+ /* 0x32 */ "transmitted pkts 256 to 511 bytes",
+ /* 0x33 */ "transmitted pkts 512 to 1023 bytes",
+ /* 0x34 */ "transmitted pkts 1024 to 1518 bytes",
+ /* 0x35 */ "transmitted pkts 1519 to 2047 bytes",
+ /* 0x36 */ "transmitted pkts 2048 to 4095 bytes",
+ /* 0x37 */ "transmitted pkts 4096 to 8191 bytes",
+ /* 0x38 */ "transmitted pkts 8192 to 9216 bytes",
+ /* 0x39 */ "dropped pkts due to rx fifo overflow",
+ /* 0x3a */ "reserved"
+};
+
+char *stat_desc_misc[] = {
+ /* 0x76 */ "dropped pkts due to no pbuf space",
+ /* 0x77 */ "dropped pkts due to no txp buf space",
+ /* 0x78 */ "dropped pkts due to no ipsec buf space",
+ /* 0x79 */ "dropped pkts due to no erx desc space",
+ /* 0x7a */ "dropped pkts due to no tpre desc space",
+ /* 0x7b */ "pkts received on mgmt port",
+ /* 0x7c */ "bytes received on mgmt port",
+ /* 0x7d */ "pause frames received on mgmt port",
+ /* 0x7e */ "error frames received on mgmt port",
+ /* 0x7f */ "pkts transmitted on mgmt port",
+ /* 0x80 */ "bytes transmitted on mgmt port",
+ /* 0x81 */ "pause frames transmitted on mgmt port",
+ /* 0x82 */ "dropped pkts due to mgmt rx fifo overflow",
+ /* 0x83 */ "ipsec received IP checksum errors",
+ /* 0x84 */ "ipsec received TCP checksum errors",
+ /* 0x85 */ "ipsec received UDP checksum errors",
+ /* 0x86 */ "ipsec runt pkts",
+ /* 0x87 */ "ipsec number dropped due to address mismatch",
+ /* 0x88 */ "ipsec dropped pkts due to rx fifo overflow",
+ /* 0x89 */ "ipsec frame too long errors 3",
+ /* 0x8a */ "ipsec total ip frames (good and bad)",
+ /* 0x8b */ "ipsec dropped ip too small (ip length < ip hdr len)",
+ /* 0x8c */ "ipsec dropped ip too short (ip length > pkt len)",
+ /* 0x8d */ "ipsec dropped ip header too small (ip header len < 5)",
+ /* 0x8e */ "ipsec dropped bad tcp header length",
+ /* 0x8f */ "ipsec chute 1 offloaded pkts received",
+ /* 0x90 */ "ipsec chute 2 offloaded pkts received",
+ /* 0x91 */ "ipsec chute 3 offloaded pkts received",
+ /* 0x92 */ "pkts dropped due to needing more than 7 fragments",
+ /* 0x93 */ "pkts dropped due to insufficient fragments available",
+ /* 0x94 */ "pkts dropped due to invalid fragment ring",
+ /* 0x95 */ "forwarded pkts"
+};
+
+/*
+ * we use a buffer to read all stats in one shot to get
+ * a consistent set (best effort) of counters rather than read them in
+ * multiple calls from filesystems
+ */
+static char port_stats_buf[8192];
+static int port_stat_count;
+
+/*
+ * read the counters for port0 and port1, format them with description
+ * and return to the buffer given to us. These counters are
+ * clear on read.
+ */
+static int proc_read_port_stat(char *page, char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ int i, n;
+ u32 v1, v2;
+ char *p;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) data;
+
+ u32 *Stats = (u32 *) &adapter->eth_statsp->params.response;
+ u64 pa;
+ be_timer_ctxt_t *ctxt = adapter->ctxt;
+
+ if (!BE_DEV_STATE_OPEN(adapter)) {
+ /* Not ready to report Stats */
+ *eof = 1;
+ return 0;
+ }
+ /* Get Physical Addr */
+ pa = pci_map_single(adapter->pdev,
+ adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ pa = cpu_to_le64(pa);
+ ctxt->get_stat_sem = (unsigned long)&adapter->get_eth_stat_sem;
+ bni_get_stats(adapter->net_obj, adapter->eth_statsp,
+ pa, get_stat_cb, (PVOID) ctxt);
+ atomic_inc(&ctxt->get_stat_flag);
+ ctxt->get_stats_timer.data = (unsigned long)ctxt;
+ mod_timer(&ctxt->get_stats_timer, (jiffies + (HZ * 60)));
+ down((PVOID) ctxt->get_stat_sem); /* block till callback is called */
+
+ if (off == 0) {
+ /* first call to us. Read all port stats from BE */
+ for (p = port_stats_buf, i = 0, port_stat_count = 0;
+ i < BE_PORT1_STAT_INDEX; i++) {
+
+ v1 = Stats[i]; /* port 0 */
+ v2 = Stats[i + BE_PORT1_STAT_INDEX]; /* port 1 */
+
+ n = sprintf(p, "%50s: %11u:%11u\n",
+ stat_desc_port[i], v1, v2);
+ p += n;
+ port_stat_count += n;
+ }
+
+ }
+ *start = page;
+ if (count < (port_stat_count - off)) {
+ i = count;
+ *eof = 0; /* More bytes left */
+ } else {
+ i = port_stat_count - off;
+ *eof = 1; /* Nothing left. indicate EOF */
+ }
+ memcpy(page, port_stats_buf + off, i);
+ pci_unmap_single(adapter->pdev, (ulong) adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ return (i);
+}
+
+static int proc_write_port_stat(struct file *file,
+ const char *buffer, unsigned long count,
+ void *data)
+{
+ return (count); /* we do not support write */
+}
+
+/*
+ * we use a buffer to read all stats in one shot to get
+ * a consistent set (best effort) of counters rather than read them in
+ * multiple calls from filesystems
+ */
+static char misc_stats_buf[8192];
+static int misc_stat_count;
+
+/*
+ * read the miscellaneous counters, format them with description
+ * and return to the buffer given to us. These counters are
+ * clear on read.
+ */
+static int proc_read_misc_stat(char *page, char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ int i, n;
+ u32 v;
+ char *p;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) data;
+
+ u32 *Stats = (u32 *) &adapter->eth_statsp->params.response;
+ u64 pa;
+ be_timer_ctxt_t *ctxt = adapter->ctxt;
+
+ if (!BE_DEV_STATE_OPEN(adapter)) {
+ /* Not ready to report Stats */
+ *eof = 1;
+ return 0;
+ }
+ /* Get Physical Addr */
+ pa = pci_map_single(adapter->pdev,
+ adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ pa = cpu_to_le64(pa);
+ ctxt->get_stat_sem = (unsigned long)&adapter->get_eth_stat_sem;
+ bni_get_stats(adapter->net_obj, adapter->eth_statsp,
+ pa, get_stat_cb, (PVOID) ctxt);
+ atomic_inc(&ctxt->get_stat_flag);
+ ctxt->get_stats_timer.data = (unsigned long)ctxt;
+ mod_timer(&ctxt->get_stats_timer, (jiffies + (HZ * 60)));
+ down((PVOID) ctxt->get_stat_sem); /* block till callback is called */
+
+ if (off == 0) {
+ /* first call to us. Read all stats from BE */
+ for (p = misc_stats_buf, i = BE_MISC_STAT_INDEX,
+ misc_stat_count = 0; i <= BE_LAST_STAT_INDEX; i++) {
+ /* port 0 */
+
+ v = Stats[i];
+
+ n = sprintf(p, "%55s: %11u\n",
+ stat_desc_misc[i - BE_MISC_STAT_INDEX],
+ v);
+ p += n;
+ misc_stat_count += n;
+ }
+ }
+ *start = page;
+ /* copy whatever we can */
+ if (count < (misc_stat_count - off)) {
+ i = count;
+ *eof = 0; /* More bytes left */
+ } else {
+ i = misc_stat_count - off;
+ *eof = 1; /* Nothing left. indicate EOF */
+ }
+ memcpy(page, misc_stats_buf + off, i);
+ pci_unmap_single(adapter->pdev, (ulong) adapter->eth_statsp,
+ sizeof(IOCTL_ETH_GET_STATISTICS),
+ PCI_DMA_FROMDEVICE);
+ return (i);
+}
+
+static int proc_write_misc_stat(struct file *file,
+ const char *buffer, unsigned long count,
+ void *data)
+{
+ return (count); /* we do not support write */
+}
+
+/*
+ * read the driver stats.
+ */
+static int proc_read_drvr_stat(char *page, char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ int n;
+ char *p = page;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) data;
+
+ if (off == 0) {
+ n = sprintf(p, "tx_reqs = %d\n",
+ adapter->be_stat.bes_tx_reqs);
+ p += n;
+ n = sprintf(p, "tx_fails = %d\n",
+ adapter->be_stat.bes_tx_fails);
+ p += n;
+ n = sprintf(p, "fwd_reqs = %d\n",
+ adapter->be_stat.bes_fwd_reqs);
+ p += n;
+ n = sprintf(p, "tx_wrbs = %d\n",
+ adapter->be_stat.bes_tx_wrbs);
+ p += n;
+ n = sprintf(p, "ints = %d\n", adapter->be_stat.bes_ints);
+ p += n;
+ n = sprintf(p, "poll = %d\n", adapter->be_stat.bes_polls);
+ p += n;
+ n = sprintf(p, "events = %d\n",
+ adapter->be_stat.bes_events);
+ p += n;
+ n = sprintf(p, "tx_events = %d\n",
+ adapter->be_stat.bes_tx_events);
+ p += n;
+ n = sprintf(p, "ucrx_events = %d\n",
+ adapter->be_stat.bes_ucrx_events);
+ p += n;
+ n = sprintf(p, "bcrx_events = %d\n",
+ adapter->be_stat.bes_bcrx_events);
+ p += n;
+ n = sprintf(p, "tx_compl = %d\n",
+ adapter->be_stat.bes_tx_compl);
+ p += n;
+ n = sprintf(p, "ucrx_compl = %d\n",
+ adapter->be_stat.bes_ucrx_compl);
+ p += n;
+ n = sprintf(p, "bcrx_compl = %d\n",
+ adapter->be_stat.bes_bcrx_compl);
+ p += n;
+ n = sprintf(p, "ethrx_post_fail = %d\n",
+ adapter->be_stat.bes_ethrx_post_fail);
+ p += n;
+ n = sprintf(p, "802.3_dropped_frames = %d\n",
+ adapter->be_stat.bes_802_3_dropped_frames);
+ p += n;
+ n = sprintf(p, "802.3_malformed_frames = %d\n",
+ adapter->be_stat.bes_802_3_malformed_frames);
+ p += n;
+ n = sprintf(p, "eth_tx_rate = %d\n",
+ adapter->be_stat.bes_eth_tx_rate);
+ p += n;
+ n = sprintf(p, "eth_rx_rate = %d\n",
+ adapter->be_stat.bes_eth_rx_rate);
+ p += n;
+
+#ifdef RX_PKT_COALESCE
+ n = sprintf(p, "Num pkts collected = %d\n",
+ adapter->be_stat.bes_rx_coal);
+ p += n;
+ n = sprintf(p, "Num times flushed = %d\n",
+ adapter->be_stat.bes_rx_flush);
+ p += n;
+#endif
+ n = sprintf(p, "ints_per_sec = %d\n",
+ adapter->be_stat.bes_ips);
+ p += n;
+ n = sprintf(p, "eq_delay = %d / %d / %d\n",
+ adapter->min_eqd, adapter->cur_eqd,
+ adapter->max_eqd);
+ p += n;
+
+ }
+ *eof = 1;
+ return (p - page);
+}
+
+static int proc_write_drvr_stat(struct file *file,
+ const char *buffer, unsigned long count,
+ void *data)
+{
+ PBE_ADAPTER adapter = (PBE_ADAPTER) data;
+ memset(&(adapter->be_stat), 0, sizeof(adapter->be_stat));
+
+ return (count); /* we do not support write */
+}
+
+static char read_eth_ring_buf[4096];
+static int read_eth_ring_count;
+
+/*
+ * Get Various Eth Ring Properties
+ */
+static int proc_eth_read_ring(char *page, char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ int i, n;
+ char *p = read_eth_ring_buf;
+ PBE_ADAPTER adapter = (PBE_ADAPTER) data;
+ struct net_device *netdev = adapter->netdevp;
+ PBNI_NET_OBJECT NetObject = netdev->priv;
+
+ if (off == 0) {
+ /* Reset read_eth_ring_count */
+ read_eth_ring_count = 0;
+
+ n = sprintf(p, " PhyAddr VirtAddr Size TotalEntries ProducerIndex ConsumerIndex NumUsed\n");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, " ------- -------- ---- ------------ ------------- ------------- -------\n");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, "%s", "EthSendRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, " %7lx %8p %4u %12u %13u %13u %7u \n",
+ virt_to_phys(NetObject->tx_q),
+ (void *)NetObject->tx_q,
+ (u32) (NetObject->tx_q_len * sizeof(ETH_WRB)),
+ NetObject->tx_q_len, NetObject->tx_q_hd,
+ NetObject->tx_q_tl, NetObject->tx_q_used);
+
+ p += n;
+ read_eth_ring_count += n;
+
+ /* Get Eth Send Compl Queue Details */
+ n = sprintf(p, "%s", "EthSendCmplRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, " %7lx %8p %4u %12u %13s %13u %7s\n",
+ virt_to_phys(NetObject->tx_cq),
+ (void *)NetObject->tx_cq,
+ (u32) (NetObject->txcq_len *
+ sizeof(ETH_TX_COMPL)),
+ NetObject->txcq_len, "NA", NetObject->tx_cq_tl,
+ "NA");
+
+ p += n;
+ read_eth_ring_count += n;
+ /* Get Eth Rx Queue Details */
+ n = sprintf(p, "%s", "EthRxRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, " %7lx %8p %4u %12u %13u %13s %7u \n",
+ virt_to_phys(NetObject->rx_q),
+ (void *)NetObject->rx_q,
+ (u32) (NetObject->rx_q_len * sizeof(ETH_RX_D)),
+ NetObject->rx_q_len, NetObject->rx_q_hd, "NA",
+ NetObject->rx_q_posted);
+ p += n;
+ read_eth_ring_count += n;
+
+ /* Get Eth Unicast Rx Compl Queue Details */
+ n = sprintf(p, "%s", "EthUnicastRxCmplRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, "%7lx %8p %4u %12u %13s %13u %7s\n",
+ virt_to_phys(NetObject->ucrx_cq),
+ (void *)NetObject->ucrx_cq,
+ (u32) (NetObject->ucrx_cq_len *
+ sizeof(ETH_RX_COMPL)),
+ NetObject->ucrx_cq_len, "NA",
+ NetObject->ucrx_cq_tl, "NA");
+ p += n;
+ read_eth_ring_count += n;
+
+ /* Get Eth Broadcast Rx Compl Queue Details */
+ n = sprintf(p, "%s", "EthBdcastRxCmplRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p, " %7lx %8p %4u %12u %13s %13u %7s \n",
+ virt_to_phys(NetObject->bcrx_cq),
+ (void *)NetObject->bcrx_cq,
+ (u32) (NetObject->bcrx_cq_len *
+ sizeof(ETH_RX_COMPL)),
+ NetObject->bcrx_cq_len, "NA",
+ NetObject->bcrx_cq_tl, "NA");
+
+ p += n;
+ read_eth_ring_count += n;
+
+ /* Get Eth Event Queue Details */
+ n = sprintf(p, "%s", "EthEventRing");
+ p += n;
+ read_eth_ring_count += n;
+
+ n = sprintf(p,
+ " %7lx %8p %4u %12u %13s %13u %7s\n",
+ virt_to_phys(NetObject->event_q),
+ (void *)NetObject->event_q,
+ (u32) (NetObject->event_q_len *
+ sizeof(EQ_ENTRY)),
+ NetObject->event_q_len, "NA",
+ NetObject->event_q_tl, "NA");
+
+ p += n;
+ read_eth_ring_count += n;
+ }
+
+ *start = page;
+ /* copy whatever we can */
+ if (count < (read_eth_ring_count - off)) {
+ i = count;
+ *eof = 0; /* More bytes left */
+ } else {
+ i = read_eth_ring_count - off;
+ *eof = 1; /* Nothing left. indicate EOF */
+ }
+
+ memcpy(page, read_eth_ring_buf + off, i);
+ return (i);
+}
+
+static int proc_eth_write_ring(struct file *file,
+ const char *buffer, unsigned long count,
+ void *data)
+{
+ return (count); /* we do not support write */
+}
+
+/*
+ * read the dbg_mask file.
+ */
+static int proc_read_dbg_mask(char *page, char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ *eof = 1;
+ return sprintf(page, "0x%x\n", dbg_mask);
+}
+
+/*
+ * write the dbg_mask value
+ */
+static int proc_write_dbg_mask(struct file *file,
+ const char *buffer, unsigned long count,
+ void *data)
+{
+
+ u8 buf[32];
+
+ if (count > sizeof(buf))
+ return -EINVAL;
+ if (copy_from_user(buf, buffer, count))
+ return -EFAULT;
+ buf[count] = '\0';
+
+ dbg_mask = simple_strtoul(buf, NULL, 16);
+ sa_trace_set_level(dbg_mask);
+ return (count);
+}
+
+void be_init_procfs(PBE_ADAPTER adapter)
+{
+ static struct proc_dir_entry *pde;
+ int adapt_num = 0;
+
+ while (adapt_num < MAX_BE_DEVICES) {
+ if (be_adapter[adapt_num] == adapter)
+ break;
+ adapt_num++;
+ }
+
+ if (adapt_num == MAX_BE_DEVICES) {
+ printk("Invalid Adapter Pointer received");
+ return;
+ }
+
+ /* create directory */
+ be_proc_dir[adapt_num] =
+ proc_mkdir(be_adpt_name[adapt_num], NULL);
+ if (be_proc_dir[adapt_num]) {
+ (be_proc_dir[adapt_num])->owner = THIS_MODULE;
+ }
+
+ pde = create_proc_entry(BE_PORT_STAT_FILE, BE_PROC_MODE,
+ be_proc_dir[adapt_num]);
+ if (pde) {
+ pde->read_proc = proc_read_port_stat;
+ pde->write_proc = proc_write_port_stat;
+ pde->data = adapter;
+ pde->owner = THIS_MODULE;
+ }
+
+ pde = create_proc_entry(BE_MISC_STAT_FILE, BE_PROC_MODE,
+ be_proc_dir[adapt_num]);
+ if (pde) {
+ pde->read_proc = proc_read_misc_stat;
+ pde->write_proc = proc_write_misc_stat;
+ pde->data = adapter;
+ pde->owner = THIS_MODULE;
+ }
+ pde = create_proc_entry(BE_DRVR_STAT_FILE, BE_PROC_MODE,
+ be_proc_dir[adapt_num]);
+ if (pde) {
+ pde->read_proc = proc_read_drvr_stat;
+ pde->write_proc = proc_write_drvr_stat;
+ pde->data = adapter;
+ pde->owner = THIS_MODULE;
+ }
+
+ pde = create_proc_entry(BE_ETH_RING_FILE, BE_PROC_MODE,
+ be_proc_dir[adapt_num]);
+ if (pde) {
+ pde->read_proc = proc_eth_read_ring;
+ pde->write_proc = proc_eth_write_ring;
+ pde->data = adapter;
+ pde->owner = THIS_MODULE;
+ }
+
+ pde = create_proc_entry(BE_DBG_MASK, BE_PROC_MODE,
+ be_proc_dir[adapt_num]);
+ if (pde) {
+ pde->read_proc = proc_read_dbg_mask;
+ pde->write_proc = proc_write_dbg_mask;
+ pde->data = adapter;
+ pde->owner = THIS_MODULE;
+ }
+}
+
+void be_cleanup_procfs(PBE_ADAPTER adapter)
+{
+ int adapt_num = 0;
+
+ while (adapt_num < MAX_BE_DEVICES) {
+ if (be_adapter[adapt_num] == adapter)
+ break;
+ adapt_num++;
+ }
+
+ if (adapt_num == MAX_BE_DEVICES) {
+ printk(KERN_ERR "BldEng:Invalid Adapter Pointer received");
+ return;
+ }
+ remove_proc_entry(BE_PORT_STAT_FILE, be_proc_dir[adapt_num]);
+ remove_proc_entry(BE_MISC_STAT_FILE, be_proc_dir[adapt_num]);
+ remove_proc_entry(BE_DRVR_STAT_FILE, be_proc_dir[adapt_num]);
+ remove_proc_entry(BE_ETH_RING_FILE, be_proc_dir[adapt_num]);
+ remove_proc_entry(BE_DBG_MASK, be_proc_dir[adapt_num]);
+ remove_proc_entry(be_adpt_name[adapt_num], NULL);
+}
diff -uprN orig/linux-2.6.24.2/drivers/net/benet/Makefile benet/linux-2.6.24.2/drivers/net/benet/Makefile
--- orig/linux-2.6.24.2/drivers/net/benet/Makefile 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/benet/Makefile 2008-02-14 15:23:07.796207560 +0530
@@ -0,0 +1,25 @@
+#
+# Makefile to build the network driver for ServerEngine's BladeEngine.
+#
+BECLIBPATH = $(src)/../../message/beclib
+
+EXTRA_CFLAGS = -Wno-unknown-pragmas -DRX_PKT_COALESCE \
+ -DFUNCTION_NIC -I$(BECLIBPATH) -I$(BECLIBPATH)/sa \
+ -I$(BECLIBPATH)/fw -I$(BECLIBPATH)/fw/amap -I$(BECLIBPATH)/fw/bmap
+
+obj-$(CONFIG_BENET) := benet.o
+
+benet-objs := be_init.o be_int.o be_netif.o be_tx.o \
+ be_proc.o be_ethtool.o bni.o \
+ ../../message/beclib/funcobj_ll.o \
+ ../../message/beclib/chipobj_ll.o \
+ ../../message/beclib/cq_ll.o \
+ ../../message/beclib/eq_ll.o \
+ ../../message/beclib/main_ll.o \
+ ../../message/beclib/mpu_ll.o \
+ ../../message/beclib/ethrx_ll.o \
+ ../../message/beclib/ethtx_ll.o \
+ ../../message/beclib/rxf_ll.o \
+ ../../message/beclib/sa/sa.o
+
+clean-files := ../../message/beclib/*.o ../../message/beclib/sa/*.o
diff -uprN orig/linux-2.6.24.2/drivers/net/Kconfig benet/linux-2.6.24.2/drivers/net/Kconfig
--- orig/linux-2.6.24.2/drivers/net/Kconfig 2008-02-11 11:21:11.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/Kconfig 2008-02-14 15:16:13.000000000 +0530
@@ -2585,6 +2585,22 @@ config TEHUTI
help
Tehuti Networks 10G Ethernet NIC
+config BENET
+ tristate "ServerEngines 10Gb NIC - BladeEngine"
+ depends on PCI
+ help
+ This driver implements the NIC functionality for ServerEngines
+ 10Gb network adapter BladeEngine (EC 3210).
+
+config BENET_NAPI
+ bool "Use Rx Polling (NAPI) for benet"
+ depends on BENET
+ default y
+ help
+ NAPI is a new driver API designed to reduce CPU and interrupt load
+ when the driver is receiving lots of packets from the card. Selecting
+ this feature will give better performance in high traffic conditions.
+
endif # NETDEV_10000
source "drivers/net/tokenring/Kconfig"
diff -uprN orig/linux-2.6.24.2/drivers/net/Makefile benet/linux-2.6.24.2/drivers/net/Makefile
--- orig/linux-2.6.24.2/drivers/net/Makefile 2008-02-11 11:21:11.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/net/Makefile 2008-02-14 15:16:13.000000000 +0530
@@ -16,6 +16,7 @@ obj-$(CONFIG_BONDING) += bonding/
obj-$(CONFIG_ATL1) += atl1/
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
obj-$(CONFIG_TEHUTI) += tehuti.o
+obj-$(CONFIG_BENET) += benet/
gianfar_driver-objs := gianfar.o \
gianfar_ethtool.o \
diff -uprN orig/linux-2.6.24.2/MAINTAINERS benet/linux-2.6.24.2/MAINTAINERS
--- orig/linux-2.6.24.2/MAINTAINERS 2008-02-11 11:21:11.000000000 +0530
+++ benet/linux-2.6.24.2/MAINTAINERS 2008-02-14 15:16:27.000000000 +0530
@@ -3376,6 +3376,13 @@ L: linux-ide@vger.kernel.org
T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git
S: Supported
+SERVER ENGINES 10Gbe NIC - BLADE-ENGINE
+P: Subbu Seetharaman
+M: subbus@serverengines.com
+L: netdev@vger.kernel.org
+W: http://www.serverengines.com
+S: Supported
+
SGI SN-IA64 (Altix) SERIAL CONSOLE DRIVER
P: Pat Gefre
M: pfg@sgi.com
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
intended recipient of this message, please immediately advise the sender by reply email message and
delete all copies of this message and any attachment(s). Thank you.
^ permalink raw reply
* [PATHCH 4/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:31 UTC (permalink / raw)
To: netdev
beclib header files.
-----------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/pch.h benet/linux-2.6.24.2/drivers/message/beclib/pch.h
--- orig/linux-2.6.24.2/drivers/message/beclib/pch.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/pch.h 2008-02-14 15:23:07.797207408 +0530
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*!
+@file
+ pch.h
+
+@brief
+
+ Each .c file in beclib includes this "precompiled header" file.
+ It should ONLY be included by beclib files.
+ Clients of beclib should include "beclib.h" instead.
+*/
+#ifndef __pch_h__
+#define __pch_h__
+
+/*
+ * -----------------------------------------------------------------------
+ * Our custom includes
+ *
+-----------------------------------------------------------------------
+ */
+
+#define _SA_MODULE_NAME "beclib_lk"
+#define BECLIB_BUILD
+
+#include "beclib_ll.h"
+#include "beclib_private_ll.h"
+#include "bestatus.h"
+
+#endif /* __pch_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_common.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_common.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_common.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_common.h 2008-02-14 15:23:07.797207408 +0530
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef __beclib_common_h__
+#define __beclib_common_h__
+
+#include "sa.h"
+
+
+/* Enable each srcgen struct to be an array of dwords */ #define
+SG_BMAP_UNION
+
+/* Pack srcgen structs */
+#ifndef SG_ATTRIBUTE_PACK
+#define SG_ATTRIBUTE_PACK
+#endif
+
+
+/* Define the static inline srcgen qualifier for inline functions. */
+#define SG_STATIC_INLINE STATIC INLINE
+
+#if !defined(BE_CONFIG)
+#define BE_CONFIG 0
+#define CONFIG0
+#endif
+
+#define BE_GEN_STATIC_INLINE STATIC INLINE #define BE_GEN_ASSERT ASSERT
+/*Id ranges and RID conversions based on config */ #include
+"be_gen_id_ranges.h"
+
+/* Srcgen includes */
+
+#include "regmap.h" /* srcgen array map output */
+#include "host_struct.h" /* srcgen array map output */
+#include "ioctl_top.h" /* srcgen array map output */
+
+#include "regmap_bmap.h" /* srcgen bitmap output */
+#include "host_struct_bmap.h" /* srcgen bitmap output */
+#include "ioctl_top_bmap.h" /* srcgen bitmap output */
+
+#include "bestatus.h"
+
+/* Debug trace categories. */
+typedef enum _BE_DEBUG_LEVELS {
+ DL_HW = 0x00000100,
+ DL_IOCTL = 0x00000200,
+
+ BE_DL_MIN_VALUE = 0x100, /* this is the min value used */
+ BE_DL_MAX_VALUE = 0x800 /* this is the higheset value used */
+} BE_DEBUG_LEVELS, *PBE_DEBUG_LEVELS;
+
+SA_GLOBAL_C_ASSERT(beclib_debug_level_range,
+ ((u32) BE_DL_MIN_VALUE > (u32) SA_DL_MAX_VALUE));
+
+#include "beregister.h" /* Macros for register access using srcgen structs */
+#include "beclib_stats.h"
+
+/* BECLIB status data type maps to the SA_STATUS */ typedef SA_STATUS
+BESTATUS, *PBESTATUS;
+
+/* BECLIB calling convention. Use default currently. */ #define BECALL
+
+/* Forward declarations. */
+struct _BE_FUNCTION_OBJECT;
+struct _BE_EQ_OBJECT;
+struct _BE_CQ_OBJECT;
+
+/* Callback types. Deprecate most of these. */ typedef void (BECALL
+*MCC_WRB_CQE_CALLBACK) (PVOID context,
+ BESTATUS status,
+ MCC_WRB *optional_wrb);
+typedef void (BECALL *MCC_ASYNC_EVENT_CALLBACK) (PVOID context,
+ u32 event_code,
+ PVOID event);
+
+typedef BESTATUS(*EQ_CALLBACK) (struct _BE_FUNCTION_OBJECT *,
+ struct _BE_EQ_OBJECT *, PVOID context); typedef
+BESTATUS(*CQ_CALLBACK) (struct _BE_FUNCTION_OBJECT *,
+ struct _BE_CQ_OBJECT *, PVOID context);
+
+#endif /* __beclib_common_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll.h 2008-02-14 15:23:07.798207256 +0530
@@ -0,0 +1,682 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef __beclib_lower_h__
+#define __beclib_lower_h__
+
+#include "beclib_common.h" /* High and low level API commonalities */
+
+SA_CPP_HEADER
+/*!
+@brief
+ Internal memory descriptor for memory shared by both the host driver and
+ the controller
+*/
+ typedef struct _BE_SHARED_MEM_DESCRIPTOR {
+ PVOID va; /*! virtual address */
+ PSA_SGL sgl; /*! memory descriptor list */
+ u32 tag; /*! memory tracking tag */
+} BE_SHARED_MEM_DESCRIPTOR, *PBE_SHARED_MEM_DESCRIPTOR;
+
+/*!
+@brief
+ Locking structure for beklib.
+*/
+typedef struct _BE_LOCK {
+ SA_SPINLOCK lock;
+ SA_IRQ irql;
+} BE_LOCK, *PBE_LOCK;
+
+typedef SA_FAST_MUTEX BE_BLOCKING_LOCK, *PBE_BLOCKING_LOCK;
+
+/*!
+@brief
+ Represents a Blade Engine chip. This is used to manage
+ global chip resources. Only the ARM uses this from the low
+ level API.
+*/
+typedef struct _BE_CHIP_OBJECT {
+ u32 magic;
+ u32 ref_count;
+ BE_LOCK lock;
+ SA_LIST_ENTRY function_list_head;
+
+} BE_CHIP_OBJECT, *PBE_CHIP_OBJECT;
+
+typedef struct _BE_MCC_WRB_RESPONSE_COPY {
+
+ u16 length; /* bytes in response */
+ u16 ioctl_offset; /* offset within the wrb of the response */
+ PVOID va; /* user's va to copy response into */
+
+} BE_MCC_WRB_RESPONSE_COPY, *PBE_MCC_WRB_RESPONSE_COPY;
+
+typedef struct _BE_MCC_WRB_CONTEXT {
+
+ MCC_WRB_CQE_CALLBACK internal_callback; /* Function to call on
+ completion */
+ PVOID internal_callback_context; /* Parameter to pass
+ to completion function */
+
+ MCC_WRB_CQE_CALLBACK callback; /* Function to call on completion */
+ PVOID callback_context; /* Parameter to pass to completion function */
+
+ volatile BESTATUS *users_final_status; /* pointer to a local
+ variable for synchronous
+ commands */
+ MCC_WRB *wrb; /* pointer to original wrb for embedded
+ commands only */
+ SA_LIST_ENTRY next; /* links context structs together in
+ free list */
+
+ BE_MCC_WRB_RESPONSE_COPY copy; /* Optional parameters to copy
+ embedded response to user's va */
+
+#if defined(SA_DEBUG)
+ u16 subsystem, opcode; /* Track this IOCTL for debug builds. */
+ MCC_WRB *ring_wrb;
+ u32 consumed_count;
+#endif
+} BE_MCC_WRB_CONTEXT, *PBE_MCC_WRB_CONTEXT;
+
+/*!
+@brief
+ Represents a function object for network or storage. This
+ is used to manage per-function resources like MCC CQs, etc.
+*/
+typedef struct _BE_FUNCTION_OBJECT {
+
+ u32 magic; /*!< magic for detecting memory corruption. */
+ PBE_CHIP_OBJECT parent_chip;
+
+ /*
+ *! Generic system abstraction (SA) device object for accessing
+ * registers, physical memory, etc.
+ */
+ SA_DEV *sa_dev;
+
+ u32 emulate; /* if set, MPU is not available.
+ Emulate everything. */
+ u32 pend_queue_driving; /* if set, drive the queued WRBs
+ after releasing the WRB lock */
+
+ SA_SPINLOCK post_lock; /* lock for verifying one thread posting wrbs */
+ SA_SPINLOCK cq_lock; /* lock for verifying one thread
+ processing cq */
+ SA_SPINLOCK mcc_context_lock; /* lock for protecting mcc
+ context free list */
+ SA_IRQ post_irq;
+ SA_IRQ cq_irq;
+
+ u32 ref_count; /*!< number obejcts referencing this funcobj */
+ BE_LOCK lock; /*!< synchronization lock */
+ u32 type;
+ u32 pci_function_number;
+
+ SA_LIST_ENTRY function_list; /*!< for linking these objects
+ together */
+
+ struct {
+ SA_LIST_ENTRY pd_list_head; /* protection domain list */
+ SA_LIST_ENTRY cq_list_head; /* completion queue list */
+ SA_LIST_ENTRY eq_list_head; /* event queue list */
+ SA_LIST_ENTRY cxn_list_head; /* list of active
+ connections */
+ SA_LIST_ENTRY eth_sq_list_head; /* list of ethernet
+ send rings */
+ SA_LIST_ENTRY eth_rq_list_head; /* list of ether RX rings */
+ SA_LIST_ENTRY rdma_qp_list_head; /* queue pair list */
+
+ struct _BE_MCC_OBJECT *mcc; /* mcc rings. */
+ struct _BE_PD_OBJECT *pd_object; /* perceived PD 0 */
+
+ union {
+ struct {
+ SA_LIST_ENTRY wrbq_list_head;
+ SA_LIST_ENTRY defq_list_head;
+ } iscsi;
+
+ struct {
+ SA_LIST_ENTRY dq_list_head;
+ SA_LIST_ENTRY sq_list_head;
+ SA_LIST_ENTRY rq_list_head;
+ } networking;
+ };
+ } links;
+
+ struct {
+ PMCC_MAILBOX va; /* VA to the mailbox */
+ SA_PHYSICAL_ADDRESS pa; /* PA to the mailbox */
+ u32 length; /* byte length of mailbox */
+
+ /* One default context struct used for posting at
+ * least one MCC_WRB
+ */
+ BE_MCC_WRB_CONTEXT default_context;
+ boolean default_context_allocated;
+ } mailbox;
+
+ struct {
+ /* Page table */
+ u32 num_page_table;
+ u32 num_sgl;
+
+ /* Wake on lans configured. */
+ u32 wol_bitmask; /* bits 0,1,2,3 are set if
+ corresponding index is enabled */
+ u32 num_jell;
+ u32 num_vlan;
+ u32 num_template;
+ u32 num_multicast;
+ u32 rss_type;
+ u32 num_zero;
+ u32 num_ooo;
+ } config;
+
+ u32 own_semaphore;
+ SA_IRQ current_irql;
+
+ BE_FIRMWARE_CONFIG fw_config;
+ BECLIB_FUNCTION_STATS stats;
+
+} BE_FUNCTION_OBJECT, *PBE_FUNCTION_OBJECT;
+
+/*!
+@brief
+ Represents a protection domain
+*/
+typedef struct _BE_PD_OBJECT {
+ u32 magic;
+ u32 ref_count;
+
+ PBE_FUNCTION_OBJECT parent_function;
+ SA_LIST_ENTRY pd_list;
+
+ u32 pd_id;
+ u8 *pd_page_va;
+ u64 pd_page_pa;
+
+} BE_PD_OBJECT, *PBE_PD_OBJECT;
+
+/*!
+ @brief
+ Represents an Event Queue
+*/
+typedef struct _BE_EQ_OBJECT {
+ u32 magic;
+ u32 ref_count;
+ BE_LOCK lock;
+
+ PBE_FUNCTION_OBJECT parent_function;
+
+ SA_LIST_ENTRY eq_list;
+ SA_LIST_ENTRY cq_list_head;
+
+ u32 eq_id;
+ EQ_CALLBACK callback;
+ PVOID callback_context;
+
+} BE_EQ_OBJECT, *PBE_EQ_OBJECT;
+
+/*!
+@brief
+ Manages a completion queue
+*/
+typedef struct _BE_CQ_OBJECT {
+ u32 magic;
+ u32 ref_count;
+
+ PBE_FUNCTION_OBJECT parent_function;
+ PBE_EQ_OBJECT eq_object;
+
+ SA_LIST_ENTRY cq_list;
+ SA_LIST_ENTRY cqlist_for_eq;
+
+ PVOID va;
+ u32 num_entries;
+
+ CQ_CALLBACK callback;
+ PVOID callback_context;
+
+ u32 cq_id;
+
+} BE_CQ_OBJECT, *PBE_CQ_OBJECT;
+
+/*!
+@brief
+ Manages an ethernet send queue
+*/
+typedef struct _BE_ETHSQ_OBJECT {
+ u32 magic;
+
+ SA_LIST_ENTRY list;
+
+ PBE_FUNCTION_OBJECT parent_function;
+ PBE_CQ_OBJECT cq_object;
+ u32 bid;
+
+} BE_ETHSQ_OBJECT, *PBE_ETHSQ_OBJECT;
+
+/*!
+@brief
+ Manages an ethernet receive queue
+*/
+typedef struct _BE_ETHRQ_OBJECT {
+ u32 magic;
+ SA_LIST_ENTRY list;
+ PBE_FUNCTION_OBJECT parent_function;
+ u32 rid;
+ PBE_CQ_OBJECT cq_object;
+ PBE_CQ_OBJECT rss_cq_object[4];
+
+} BE_ETHRQ_OBJECT, *PBE_ETHRQ_OBJECT;
+
+/*!
+@brief
+ Manages an MCC
+*/
+typedef struct _BE_MCC_OBJECT {
+ u32 magic;
+
+ PBE_FUNCTION_OBJECT parent_function;
+ SA_LIST_ENTRY mcc_list;
+
+ PBE_CQ_OBJECT cq_object;
+
+ /* Async event callback for MCC CQ. */
+ MCC_ASYNC_EVENT_CALLBACK async_callback;
+ PVOID async_context;
+
+ struct {
+ struct _BE_MCC_WRB_CONTEXT *base;
+ u32 num;
+ SA_LIST_ENTRY list_head;
+ } wrb_context;
+
+ struct {
+ PSA_SGL sgl;
+ BE_SHARED_MEM_DESCRIPTOR sm_descriptor;
+ SA_RING ring;
+ } sq;
+
+ struct {
+ BE_SHARED_MEM_DESCRIPTOR sm_descriptor;
+ SA_RING ring;
+ } cq;
+
+ u32 processing; /* flag indicating that one thread
+ is processing CQ */
+ u32 rearm; /* doorbell rearm setting to make
+ sure the active processing thread */
+ /* rearms the CQ if any of the threads requested it. */
+
+ SA_LIST_ENTRY backlog;
+ u32 backlog_length;
+ u32 driving_backlog;
+ u32 consumed_index;
+
+} BE_MCC_OBJECT, *PBE_MCC_OBJECT;
+
+/*!
+@brief
+ Manages an iSCSI default PDU
+*/
+typedef struct _BE_DEFAULT_PDU_QUEUE_OBJECT {
+ u32 magic;
+
+ PBE_FUNCTION_OBJECT parent_function;
+ SA_LIST_ENTRY func_list;
+ PBE_CQ_OBJECT cq_object;
+ PSA_SGL sgl;
+ u32 rid;
+} BE_DEFAULT_PDU_QUEUE_OBJECT, *PBE_DEFAULT_PDU_QUEUE_OBJECT;
+
+typedef struct _BE_ISCSI_WRB_QUEUE_OBJECT {
+
+ u32 magic;
+
+ PBE_FUNCTION_OBJECT parent_function;
+
+ SA_LIST_ENTRY wrbq_list;
+
+ /*u32 cra, length; */
+ u32 cid;
+ PSA_SGL sgl;
+ u32 length;
+
+} BE_ISCSI_WRB_QUEUE_OBJECT, *PBE_ISCSI_WRB_QUEUE_OBJECT;
+
+/*!
+@brief
+ Manages iSCSI connection resources like CID, WRB ring, etc.
+*/
+typedef struct _BE_ISCSI_CONNECTION_OBJECT {
+ u32 magic;
+ PBE_FUNCTION_OBJECT parent_function;
+
+ PBE_CQ_OBJECT cq;
+ PBE_ISCSI_WRB_QUEUE_OBJECT wrbq;
+ PBE_DEFAULT_PDU_QUEUE_OBJECT defq;
+
+ SA_LIST_ENTRY connection_list;
+} BE_ISCSI_CONNECTION_OBJECT, *PBE_ISCSI_CONNECTION_OBJECT;
+
+/* Queue context header -- the required software information for
+ * queueing a WRB.
+ */
+typedef struct _BE_QUEUE_DRIVER_CONTEXT {
+ MCC_WRB_CQE_CALLBACK internal_callback; /* Function to call on
+ completion */
+ PVOID internal_callback_context; /* Parameter to pass
+ to completion function */
+
+ MCC_WRB_CQE_CALLBACK callback; /* Function to call on completion */
+ PVOID callback_context; /* Parameter to pass to completion function */
+
+ BE_MCC_WRB_RESPONSE_COPY copy; /* Optional parameters to copy
+ embedded response to user's va */
+
+ PVOID optional_ioctl_va;
+
+ SA_LIST_ENTRY list;
+
+ u32 bytes;
+
+} BE_QUEUE_DRIVER_CONTEXT, *PBE_QUEUE_DRIVER_CONTEXT;
+
+/*
+ *lint -e413
+ *lint -e831
+ *lint -e30
+ *lint -e84
+ * Common MCC WRB header that all commands require.
+ */
+typedef struct _BE_MCC_WRB_HEADER {
+ u8 rsvd[SA_FIELD_OFFSET(MCC_WRB, payload)]; } BE_MCC_WRB_HEADER,
+*PBE_MCC_WRB_HEADER; SA_GLOBAL_C_ASSERT(queue_header,
+ sizeof(BE_MCC_WRB_HEADER) == SA_FIELD_OFFSET(MCC_WRB,
+ payload));
+
+/*
+ * All non embedded commands supported by beclib functions only allow
+ * 1 SGE. This queue context handles them all.
+ */
+typedef struct _BE_NONEMBEDDED_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ MCC_SGE sge[1];
+} BE_NONEMBEDDED_QUEUE_CONTEXT, *PBE_NONEMBEDDED_QUEUE_CONTEXT;
+
+/*
+ *
+-----------------------------------------------------------------------
+-
+ * This section contains the specific queue struct for each command.
+ * The user could always provide a BE_GENERIC_QUEUE_CONTEXT but this
+is a
+ * rather large struct. By using the specific struct, memory
+consumption
+ * can be reduced.
+ *
+-----------------------------------------------------------------------
+-
+ */
+typedef BE_NONEMBEDDED_QUEUE_CONTEXT BE_ETH_STATS_QUEUE_CONTEXT,
+ *PBE_ETH_STATS_QUEUE_CONTEXT;
+
+typedef struct _BE_LINK_STATUS_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_NTWK_LINK_STATUS_QUERY ioctl; }
+BE_LINK_STATUS_QUEUE_CONTEXT, *PBE_LINK_STATUS_QUEUE_CONTEXT;
+
+typedef struct _BE_MULTICAST_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_NTWK_MULTICAST_SET ioctl; } BE_MULTICAST_QUEUE_CONTEXT,
+*PBE_MULTICAST_QUEUE_CONTEXT;
+
+typedef struct _BE_WAKE_ON_LAN_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_ETH_ACPI_CONFIG ioctl;
+} BE_WAKE_ON_LAN_QUEUE_CONTEXT, *PBE_WAKE_ON_LAN_QUEUE_CONTEXT;
+
+typedef struct _BE_VLAN_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_NTWK_VLAN_CONFIG ioctl;
+} BE_VLAN_QUEUE_CONTEXT, *PBE_VLAN_QUEUE_CONTEXT;
+
+typedef struct _BE_PROMISCUOUS_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_ETH_PROMISCUOUS ioctl;
+} BE_PROMISCUOUS_QUEUE_CONTEXT, *PBE_PROMISCUOUS_QUEUE_CONTEXT;
+
+typedef struct _BE_FORCE_FAILOVER_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_FORCE_FAILOVER ioctl;
+} BE_FORCE_FAILOVER_QUEUE_CONTEXT, *PBE_FORCE_FAILOVER_QUEUE_CONTEXT;
+
+typedef struct _BE_RSS_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_ETH_RSS_CONFIG ioctl;
+} BE_RSS_QUEUE_CONTEXT, *PBE_RSS_QUEUE_CONTEXT;
+
+typedef struct _BE_NOP_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_NOP ioctl;
+} BE_NOP_QUEUE_CONTEXT, *PBE_NOP_QUEUE_CONTEXT;
+
+typedef struct _BE_RXF_FILTER_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_NTWK_RX_FILTER ioctl;
+} BE_RXF_FILTER_QUEUE_CONTEXT, *PBE_RXF_FILTER_QUEUE_CONTEXT;
+
+typedef struct _BE_EQ_MODIFY_DELAY_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ IOCTL_COMMON_MODIFY_EQ_DELAY ioctl;
+} BE_EQ_MODIFY_DELAY_QUEUE_CONTEXT, *PBE_EQ_MODIFY_DELAY_QUEUE_CONTEXT;
+
+/*
+ * The generic context is the largest size that would be required.
+ * It is the software context plus an entire WRB.
+ */
+typedef struct _BE_GENERIC_QUEUE_CONTEXT {
+ BE_QUEUE_DRIVER_CONTEXT context;
+ BE_MCC_WRB_HEADER wrb_header;
+ MCC_WRB_PAYLOAD payload;
+} BE_GENERIC_QUEUE_CONTEXT, *PBE_GENERIC_QUEUE_CONTEXT;
+
+SA_GLOBAL_C_ASSERT(generic_queue_context,
+ sizeof(BE_GENERIC_QUEUE_CONTEXT) >=
+ sizeof(BE_QUEUE_DRIVER_CONTEXT) + sizeof(MCC_WRB));
+
+typedef BE_GENERIC_QUEUE_CONTEXT BE_CONFIG_RED_QUEUE_CONTEXT,
+ *PBE_CONFIG_RED_QUEUE_CONTEXT;
+typedef BE_GENERIC_QUEUE_CONTEXT BE_CONFIG_PORT_EQUALIXATION_QUEUE_CONTEXT,
+ *PBE_CONFIG_PORT_EQUALIXATION_QUEUE_CONTEXT;
+
+/*
+ * Types for the BE_QUEUE_CONTEXT object.
+ */
+#define BE_QUEUE_INVALID (0)
+#define BE_QUEUE_LINK_STATUS (0xA006)
+#define BE_QUEUE_ETH_STATS (0xA007)
+#define BE_QUEUE_TPM_STATS (0xA008)
+#define BE_QUEUE_TCP_STATS (0xA009)
+#define BE_QUEUE_MULTICAST (0xA00A)
+#define BE_QUEUE_VLAN (0xA00B)
+#define BE_QUEUE_RSS (0xA00C)
+#define BE_QUEUE_FORCE_FAILOVER (0xA00D)
+#define BE_QUEUE_PROMISCUOUS (0xA00E)
+#define BE_QUEUE_WAKE_ON_LAN (0xA00F)
+#define BE_QUEUE_NOP (0xA010)
+
+/*
+ * These define constant 32-bit values that are stored as the magic
+ * number in each data type. The magic number is a debugging tool.
+ * In debug mode we use asserts to constantly check the integrity
+ * of the magic value, which spots double frees and some memory corruption.
+ * In release mode, the magic value can be used for post-mortem
+ * debugging without symbols to locate data types in memory -- this is
+ * easier using 4 character strings.
+ */
+#define BE_CHIP_MAGIC SA_TAG("beco")
+#define BE_FUNCTION_MAGIC SA_TAG("befo")
+#define BE_PD_MAGIC SA_TAG("bepd")
+#define BE_CQ_MAGIC SA_TAG("becq")
+#define BE_EQ_MAGIC SA_TAG("beeq")
+#define BE_ETHSQ_MAGIC SA_TAG("bees")
+#define BE_ETHRQ_MAGIC SA_TAG("beer")
+#define BE_MCC_MAGIC SA_TAG("bemc")
+#define BE_DEFAULT_PDU_QUEUE_MAGIC SA_TAG("bedp")
+#define BE_ISCSI_CONNECTION_MAGIC SA_TAG("beic")
+#define BE_TPM_CONNECTION_MAGIC SA_TAG("betc")
+#define BE_TPM_SQ_MAGIC SA_TAG("besq")
+#define BE_TPM_RQ_MAGIC SA_TAG("berq")
+#define BE_TPM_DQ_MAGIC SA_TAG("bedq")
+#define BE_ISCSI_WRB_QUEUE_MAGIC SA_TAG("beiq")
+#define BE_RDMA_QP_MAGIC SA_TAG("beqp")
+#define BE_RDMA_CXN_MAGIC SA_TAG("brcx")
+
+/*
+ * Macro to declare an inline function that asserts on both a pointer
+and
+ * the magic value. Inline function nicely forces type safety at compile time.
+ */
+#define MAGIC_ASSERT_DECLARE(_short_type_) \ STATIC INLINE void
+_short_type_##_ASSERT(BE_##_short_type_##_OBJECT *p) { \
+ ASSERT(p); \
+ ASSERT(p->magic == BE_##_short_type_##_MAGIC); \
+ } \
+
+/*
+ * Declare inline functions, e.g. CHIP_ASSERT, that check the
+ * pointer for non-NULL and verify the magic constant. Since they
+ * are functions, they also verify the type of the pointer at compile time.
+ */
+MAGIC_ASSERT_DECLARE(CHIP)
+MAGIC_ASSERT_DECLARE(FUNCTION)
+MAGIC_ASSERT_DECLARE(PD)
+MAGIC_ASSERT_DECLARE(CQ)
+MAGIC_ASSERT_DECLARE(EQ)
+MAGIC_ASSERT_DECLARE(ETHSQ)
+MAGIC_ASSERT_DECLARE(ETHRQ)
+MAGIC_ASSERT_DECLARE(MCC)
+MAGIC_ASSERT_DECLARE(DEFAULT_PDU_QUEUE)
+MAGIC_ASSERT_DECLARE(ISCSI_CONNECTION)
+MAGIC_ASSERT_DECLARE(ISCSI_WRB_QUEUE)
+/* Shorter names */
+#define ISCSI_CXN_ASSERT ISCSI_CONNECTION_ASSERT #define
+ISCSI_WRBQ_ASSERT ISCSI_WRB_QUEUE_ASSERT #define ISCSI_DEFQ_ASSERT
+DEFAULT_PDU_QUEUE_ASSERT
+/* Include the srcgen API. */
+#include "beclib_ll_enum_nic.h"
+#include "beclib_ll_bmap_nic.h"
+/*
+ * ----------------------------------------------------------------------
+ * API MACROS
+ *
+----------------------------------------------------------------------
+ */
+#define BE_IOCTL_NAME(_short_name_) IOCTL_##_short_name_
+#define BE_OPCODE_NAME(_short_name_) OPCODE_##_short_name_
+#define BE_SUBSYSTEM_NAME(_short_name_) SUBSYSTEM_##_short_name_
+
+#define BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(_function_object_, _wrb_, \
+ _short_name_) \
+ (BE_IOCTL_NAME(_short_name_)*) \
+ be_function_prepare_embedded_ioctl ( \
+ _function_object_, \
+ _wrb_, \
+ sizeof (BE_IOCTL_NAME(_short_name_)), \
+ SA_SIZEOF_FIELD(BE_IOCTL_NAME(_short_name_), params.request), \
+ SA_SIZEOF_FIELD(BE_IOCTL_NAME(_short_name_), params.response), \
+ BE_OPCODE_NAME(_short_name_), \
+ BE_SUBSYSTEM_NAME(_short_name_));
+
+#define BE_FUNCTION_PREPARE_NONEMBEDDED_IOCTL(_function_object_, _wrb_, \
+ _ioctl_va_, _ioctl_pa_, _short_name_) \
+ (BE_IOCTL_NAME(_short_name_)*) \
+ be_function_prepare_nonembedded_ioctl ( \
+ (_function_object_), \
+ (_wrb_), \
+ (_ioctl_va_), \
+ (_ioctl_pa_), \
+ sizeof (BE_IOCTL_NAME(_short_name_)), \
+ SA_SIZEOF_FIELD(BE_IOCTL_NAME(_short_name_), params.request), \
+ SA_SIZEOF_FIELD(BE_IOCTL_NAME(_short_name_), params.response), \
+ BE_OPCODE_NAME(_short_name_), \
+ BE_SUBSYSTEM_NAME(_short_name_));
+
+/*
+ * ----------------------------------------------------------------------
+ * API Inline Functions
+ *
+----------------------------------------------------------------------
+ * Returns TRUE for the ISCSI function
+ */
+STATIC INLINE
+ boolean be_function_is_iscsi(PBE_FUNCTION_OBJECT function_object) {
+ FUNCTION_ASSERT(function_object);
+ return (function_object->type == BE_FUNCTION_TYPE_ISCSI); }
+
+/* Returns TRUE for the networking function */ STATIC INLINE
+ boolean be_function_is_networking(PBE_FUNCTION_OBJECT
+function_object) {
+ FUNCTION_ASSERT(function_object);
+ return (function_object->type == BE_FUNCTION_TYPE_NETWORK); }
+
+STATIC INLINE void
+be_function_copy_stats(IN PBE_FUNCTION_OBJECT function_object,
+ OUT PBECLIB_FUNCTION_STATS stats) {
+ FUNCTION_ASSERT(function_object);
+ ASSERT(stats);
+ sa_memcpy(stats, &function_object->stats,
+ sizeof(function_object->stats));
+
+}
+
+/* Returns a pointer to the parent chip object for this function. */
+STATIC INLINE
+ PBE_CHIP_OBJECT be_function_get_chip_object(PBE_FUNCTION_OBJECT
+ function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return (function_object->parent_chip); }
+
+SA_CPP_TRAILER
+#endif /* __beclib_lower__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_private_ll.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_private_ll.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_private_ll.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_private_ll.h 2008-02-14 15:23:07.799207104 +0530
@@ -0,0 +1,451 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef __beclib_private_h__
+#define __beclib_private_h__
+
+/*
+ * ------------------------------------------------------
+ * Chip Object
+ * ------------------------------------------------------
+ */
+
+void be_chip_lock(IN PBE_CHIP_OBJECT chip_object); void
+be_chip_unlock(IN PBE_CHIP_OBJECT chip_object);
+
+/*
+ * ------------------------------------------------------
+ * Function Object
+ * ------------------------------------------------------
+ */
+
+/* Init function object. */
+BESTATUS be_function_create(SA_DEV *sa_dev, /* previously created device */
+ u32 function_type, /* e.g FUNCTION_TYPE_ISCSI */
+ PSA_SGL mailbox_sgl,
+ PBE_FUNCTION_OBJECT function_object);
+
+/* Creates one chip object. */
+BESTATUS be_chip_create(OUT PBE_CHIP_OBJECT chip);
+
+/*
+ * Inserts the function object into the chip object. Both must be
+previously
+ * created. This function will initialize the chip during emulation.
+ */
+BESTATUS
+be_chip_insert_function_object(IN PBE_CHIP_OBJECT chip_object,
+ IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ * Cleans up the chip object.
+ * This function is called as part of be_function_cleanup.
+ */
+void be_chip_destroy(PBE_CHIP_OBJECT chip);
+
+/*
+ * Destroys the function object. This assumes that all resources for
+ * this function have already been destroy, and it asserts if that
+ * is not true.
+ * This function is called as part of be_function_cleanup.
+ */
+BESTATUS be_function_destroy(PBE_FUNCTION_OBJECT function_object);
+
+/*
+ * Removes the function object from the chip.
+ * This function is called as part of be_function_cleanup.
+ */
+void
+be_chip_remove_function_object(IN PBE_CHIP_OBJECT chip_object,
+ IN PBE_FUNCTION_OBJECT function_object);
+
+void _be_function_lock(PBE_FUNCTION_OBJECT fo); void
+_be_function_unlock(PBE_FUNCTION_OBJECT fo);
+
+void _be_function_add_eq(PBE_FUNCTION_OBJECT fo, PBE_EQ_OBJECT
+eq_object); void _be_function_remove_eq(PBE_FUNCTION_OBJECT fo,
+ PBE_EQ_OBJECT eq_object);
+
+void _be_function_add_cq(PBE_FUNCTION_OBJECT fo, PBE_CQ_OBJECT
+cq_object); void _be_function_remove_cq(PBE_FUNCTION_OBJECT fo,
+ PBE_CQ_OBJECT cq_object);
+
+void _be_function_add_eth_sq(PBE_FUNCTION_OBJECT fo,
+ PBE_ETHSQ_OBJECT eth_sq);
+void _be_function_remove_eth_sq(PBE_FUNCTION_OBJECT fo,
+ PBE_ETHSQ_OBJECT eth_sq);
+
+void _be_function_add_eth_rq(PBE_FUNCTION_OBJECT fo,
+ PBE_ETHRQ_OBJECT eth_rq);
+void _be_function_remove_eth_rq(PBE_FUNCTION_OBJECT fo,
+ PBE_ETHRQ_OBJECT eth_rq);
+
+void _be_function_add_mcc(PBE_FUNCTION_OBJECT fo, PBE_MCC_OBJECT mcc);
+void _be_function_remove_mcc(PBE_FUNCTION_OBJECT fo, PBE_MCC_OBJECT
+mcc);
+
+void _be_function_add_iscsi_connection(PBE_FUNCTION_OBJECT fo,
+ PBE_ISCSI_CONNECTION_OBJECT
+ connection_object);
+void _be_function_remove_iscsi_connection(PBE_FUNCTION_OBJECT fo,
+ PBE_ISCSI_CONNECTION_OBJECT
+ connection_object);
+PBE_ISCSI_CONNECTION_OBJECT
+_be_function_find_iscsi_connection(PBE_FUNCTION_OBJECT fo, u32 cid);
+
+void _be_function_add_wrbq(PBE_FUNCTION_OBJECT funcobj,
+ PBE_ISCSI_WRB_QUEUE_OBJECT wrbq); void
+_be_function_remove_wrbq(PBE_FUNCTION_OBJECT funcobj,
+ PBE_ISCSI_WRB_QUEUE_OBJECT wrbq);
+
+void _be_function_add_default_pdu_queue(PBE_FUNCTION_OBJECT func_obj,
+ PBE_DEFAULT_PDU_QUEUE_OBJECT defq); void
+_be_function_remove_default_pdu_queue(PBE_FUNCTION_OBJECT func_obj,
+ PBE_DEFAULT_PDU_QUEUE_OBJECT
+ defq);
+
+u32 _be_function_reference(PBE_FUNCTION_OBJECT fo);
+u32 _be_function_dereference(PBE_FUNCTION_OBJECT fo);
+
+BESTATUS
+be_function_ring_destroy(PBE_FUNCTION_OBJECT function_object,
+ u32 id, u32 ring_type);
+
+BESTATUS
+be_function_ring_destroy_async(PBE_FUNCTION_OBJECT function_object,
+ u32 id,
+ u32 ring_type,
+ MCC_WRB_CQE_CALLBACK callback,
+ PVOID callback_context,
+ MCC_WRB_CQE_CALLBACK internal_callback,
+ PVOID internal_callback_context);
+
+#define BE_CREATE_MCC_RESPONSE_COPY(_ioctl_type_, _field_, _va_) \
+ be_create_mcc_response_copy(SA_FIELD_OFFSET(_ioctl_type_, _field_), \
+ SA_SIZEOF_FIELD(_ioctl_type_, _field_), \
+ (_va_)) \
+
+STATIC INLINE
+ BE_MCC_WRB_RESPONSE_COPY
+be_create_mcc_response_copy(u16 offset, u16 length, PVOID va) {
+ BE_MCC_WRB_RESPONSE_COPY rc;
+ rc.length = length;
+ rc.ioctl_offset = offset;
+ rc.va = va;
+ return rc;
+}
+
+BESTATUS
+be_function_post_mcc_wrb_with_queue_context(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK
+ callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va);
+
+BESTATUS
+be_function_post_mcc_wrb_with_copy(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va,
+ IN BE_MCC_WRB_RESPONSE_COPY
+ response_copy);
+
+BESTATUS
+be_function_post_mcc_wrb_with_internal_callback(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN PMCC_WRB wrb,
+ IN
+ PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK
+ callback,
+ IN PVOID callback_context,
+ IN MCC_WRB_CQE_CALLBACK
+ internal_callback,
+ IN PVOID
+ internal_callback_context,
+ IN PVOID
+ optional_ioctl_va);
+
+BESTATUS
+be_function_post_mcc_wrb_complete(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN MCC_WRB_CQE_CALLBACK
+ internal_callback,
+ IN PVOID internal_callback_context,
+ IN PVOID optional_ioctl_va,
+ IN BE_MCC_WRB_RESPONSE_COPY
+ response_copy);
+
+/* Returns the protection domain number. 0 is host. */
+u32 be_function_get_pd_number(PBE_FUNCTION_OBJECT function_object);
+
+boolean be_function_is_vm(PBE_FUNCTION_OBJECT function_object);
+
+BESTATUS
+be_function_queue_mcc_wrb(PBE_FUNCTION_OBJECT function_object,
+ PBE_GENERIC_QUEUE_CONTEXT queue_context);
+
+BESTATUS
+be_function_internal_query_firmware_config(IN PBE_FUNCTION_OBJECT
+ function_object,
+ OUT BE_FIRMWARE_CONFIG *
+ config);
+
+/*
+ * ------------------------------------------------------
+ * Event Queue
+ * ------------------------------------------------------
+ */
+
+void _be_eq_add_cq(PBE_EQ_OBJECT eq_object, PBE_CQ_OBJECT cq_object);
+void _be_eq_remove_cq(PBE_EQ_OBJECT eq_object, PBE_CQ_OBJECT
+cq_object);
+
+u32 be_eq_reference(PBE_EQ_OBJECT cq_object);
+u32 be_eq_dereference(PBE_EQ_OBJECT cq_object);
+
+/* Deprecate.... */
+EQ_CALLBACK
+be_eq_set_callback(IN PBE_EQ_OBJECT eq_object,
+ IN EQ_CALLBACK callback, IN PVOID context);
+
+/* Deprecate... */
+void
+be_eq_delegate_processing(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 eq_id);
+
+/*
+ * ------------------------------------------------------
+ * Completion Queue Object
+ * ------------------------------------------------------
+ */
+
+u32 be_cq_object_reference(PBE_CQ_OBJECT cq_object);
+
+u32 be_cq_object_dereference(PBE_CQ_OBJECT cq_object);
+
+/* Deprecate.... */
+CQ_CALLBACK
+be_cq_object_set_callback(IN PBE_CQ_OBJECT cq_object,
+ IN CQ_CALLBACK callback, IN PVOID context);
+
+/* Deprecate.... */
+void
+be_cq_object_delegate_processing(PBE_FUNCTION_OBJECT function_object,
+ u32 cq_id);
+
+/*
+ * ------------------------------------------------------
+ * MCC QUEUE
+ * ------------------------------------------------------
+ */
+
+BESTATUS
+be_mpu_init_mailbox(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL mailbox);
+
+BESTATUS be_mpu_uninit_mailbox(IN PBE_FUNCTION_OBJECT function_object);
+
+PMCC_WRB
+_be_mpu_peek_ring_wrb(IN PBE_MCC_OBJECT mcc, IN boolean driving_queue);
+
+PBE_MCC_WRB_CONTEXT
+_be_mcc_allocate_wrb_context(PBE_FUNCTION_OBJECT function_object);
+
+void
+_be_mcc_free_wrb_context(PBE_FUNCTION_OBJECT function_object,
+ PBE_MCC_WRB_CONTEXT context);
+
+BESTATUS
+_be_mpu_post_wrb_mailbox(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_MCC_WRB_CONTEXT wrb_context);
+
+BESTATUS
+_be_mpu_post_wrb_ring(IN PBE_MCC_OBJECT mcc,
+ IN PMCC_WRB wrb, IN PBE_MCC_WRB_CONTEXT wrb_context);
+
+void
+be_mcc_process_cqe(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_CQ_ENTRY cqe);
+
+u32 be_mcc_get_id(PBE_MCC_OBJECT mcc);
+
+void be_drive_mcc_wrb_queue(IN PBE_MCC_OBJECT mcc);
+
+/*
+ * ------------------------------------------------------
+ * iSCSI connection
+ * ------------------------------------------------------
+ */
+
+BESTATUS
+be_iscsi_cxn_create(PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ISCSI_WRB_QUEUE_OBJECT wrbq,
+ IN PBE_DEFAULT_PDU_QUEUE_OBJECT defq,
+ IN PBE_CQ_OBJECT cq,
+ OUT PBE_ISCSI_CONNECTION_OBJECT cxn);
+
+void be_iscsi_cxn_destroy(PBE_ISCSI_CONNECTION_OBJECT cxn);
+
+/*
+ * ------------------------------------------------------
+ * Ring Sizes
+ * ------------------------------------------------------
+ */
+STATIC INLINE u32 be_ring_encoding_to_length(u32 encoding, u32
+object_size) {
+
+ ASSERT(encoding != 1); /* 1 is rsvd */
+ ASSERT(encoding < 16);
+ ASSERT(object_size > 0);
+
+ if (encoding == 0) /* 32k deep */
+ encoding = 16;
+
+ return (1 << (encoding - 1)) * object_size; }
+
+STATIC INLINE
+ u32 be_ring_length_to_encoding(u32 length_in_bytes, u32
+object_size) {
+
+ u32 count, encoding;
+
+ ASSERT(object_size > 0);
+ ASSERT(length_in_bytes % object_size == 0);
+
+ count = length_in_bytes / object_size;
+
+ ASSERT(count > 1);
+ ASSERT(count <= 32 * 1024);
+ ASSERT(length_in_bytes <= 8 * SA_PAGE_SIZE); /* max ring size in UT */
+
+ encoding = sa_log2(count) + 1;
+
+ if (encoding == 16)
+ encoding = 0; /* 32k deep */
+
+ return encoding;
+}
+
+/*
+ * ------------------------------------------------------
+ * Locking
+ * ------------------------------------------------------
+ */
+
+/* Init, acquire, or release a lock at any IRQL */ STATIC INLINE void
+be_lock_init(BE_LOCK *lock) {
+ sa_init_spinlock(&lock->lock);
+}
+
+STATIC INLINE void be_lock_acquire(IN BE_LOCK *lock) {
+ sa_acquire_spinlock(&lock->lock, &lock->irql); }
+
+STATIC INLINE void be_lock_release(IN BE_LOCK *lock) {
+ sa_release_spinlock(&lock->lock, &lock->irql); }
+
+/*
+ * Init, acquire, or release a blocking lock at IRQL<DISPATH_LEVEL.
+ * TODO - These may need to be implemented with spinlocks on some
+platforms,
+ * hence this extra layer of abstraction.
+ */
+STATIC INLINE void be_blocking_lock_init(IN BE_BLOCKING_LOCK *lock) {
+ sa_initialize_fast_mutex(lock);
+}
+
+STATIC INLINE void be_blocking_lock_acquire(IN BE_BLOCKING_LOCK *lock)
+{
+ SA_NOT_USED(lock);
+}
+
+STATIC INLINE void be_blocking_lock_release(IN BE_BLOCKING_LOCK *lock)
+{
+ SA_NOT_USED(lock);
+ /*sa_release_fast_mutex(lock); */
+}
+
+STATIC INLINE void be_lock_wrb_post(PBE_FUNCTION_OBJECT
+function_object) {
+ FUNCTION_ASSERT(function_object);
+ sa_acquire_spinlock(&function_object->post_lock,
+ &function_object->post_irq);
+}
+
+STATIC INLINE void be_unlock_wrb_post(PBE_FUNCTION_OBJECT
+function_object) {
+ FUNCTION_ASSERT(function_object);
+ sa_release_spinlock(&function_object->post_lock,
+ &function_object->post_irq);
+
+ if (function_object->pend_queue_driving
+ && function_object->links.mcc) {
+ function_object->pend_queue_driving = 0;
+ function_object->stats.pended_queue_driving++;
+ be_drive_mcc_wrb_queue(function_object->links.mcc);
+ }
+}
+
+STATIC INLINE void be_lock_cq_process(PBE_FUNCTION_OBJECT
+function_object) {
+ FUNCTION_ASSERT(function_object);
+ sa_acquire_spinlock(&function_object->cq_lock,
+ &function_object->cq_irq);
+}
+
+STATIC INLINE void be_unlock_cq_process(PBE_FUNCTION_OBJECT
+ function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ sa_release_spinlock(&function_object->cq_lock,
+ &function_object->cq_irq);
+}
+
+void be_sgl_to_pa_list(PSA_SGL sgl, PHYS_ADDR *pa_list, u32 max_num);
+
+#endif /* __beclib_private_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_stats.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_stats.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_stats.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_stats.h 2008-02-14 15:23:07.799207104 +0530
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef __beclib_stats_h__
+#define __beclib_stats_h__
+
+typedef struct _BECLIB_FUNCTION_STATS {
+
+ union {
+
+ u32 dw[32]; /* Reserve space for a fixed number of stats. */
+
+ struct {
+ u32 mailbox_wrbs;
+ u32 emulated_wrbs;
+
+ /* Pertain to WRBs posted to ring only */
+ u32 synchronous_wrbs;
+ u32 posted_wrbs;
+ u32 consumed_wrbs;
+ u32 completed_wrbs;
+
+ /* SW queueing */
+ u32 queued_wrbs;
+ u32 queue_length;
+ u32 max_queue_length;
+ u32 pended_queue_driving;
+
+ /* MCC CQ */
+ u32 processed_cq;
+ u32 cq_entries;
+ u32 async_events;
+ u32 ignored_async_events;
+
+ /* Locks */
+ u32 post_lock_acquires;
+ u32 cq_lock_acquires;
+ u64 post_lock_ticks;
+ u64 cq_lock_ticks;
+ };
+ };
+
+} BECLIB_FUNCTION_STATS, *PBECLIB_FUNCTION_STATS;
+
+#endif /* __beclib_stats_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll_enum_nic.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll_enum_nic.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll_enum_nic.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll_enum_nic.h 2008-02-14 15:23:07.799207104 +0530
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__beclib_ll_enum_h__ #define __beclib_ll_enum_h__ #include "setypes.h"
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/* --- BE_FUNCTION_ENUM --- */
+#define BE_FUNCTION_TYPE_ISCSI (0)
+#define BE_FUNCTION_TYPE_NETWORK (1)
+#define BE_FUNCTION_TYPE_ARM (2)
+
+typedef enum {
+ ENUM_BE_FUNCTION_TYPE_ISCSI = 0x0UL,
+ ENUM_BE_FUNCTION_TYPE_NETWORK = 0x1UL,
+ ENUM_BE_FUNCTION_TYPE_ARM = 0x2UL
+} BE_FUNCTION_ENUM;
+
+/* --- BE_ETH_TX_RING_TYPE_ENUM --- */
+#define BE_ETH_TX_RING_TYPE_FORWARDING (1) /* Ether ring for forwarding */
+#define BE_ETH_TX_RING_TYPE_STANDARD (2) /* Ether ring for sending */
+ /* network packets. */
+#define BE_ETH_TX_RING_TYPE_BOUND (3) /* Ethernet ring for sending */
+ /* network packets, bound */
+ /* to a physical port. */
+
+typedef enum {
+ ENUM_BE_ETH_TX_RING_TYPE_FORWARDING = 0x1UL,
+ ENUM_BE_ETH_TX_RING_TYPE_STANDARD = 0x2UL,
+ ENUM_BE_ETH_TX_RING_TYPE_BOUND = 0x3UL } BE_ETH_TX_RING_TYPE_ENUM;
+
+#endif /* __beclib_ll_enum_h__ */
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
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^ permalink raw reply
* [PATHCH 5/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:32 UTC (permalink / raw)
To: netdev
beclib header and functions.
----------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll_bmap_nic.h benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll_bmap_nic.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beclib_ll_bmap_nic.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beclib_ll_bmap_nic.h 2008-02-14 15:23:07.802206648 +0530
@@ -0,0 +1,1720 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __beclib_ll_bmap_h__
+#define __beclib_ll_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+/*
+ *-----------------------------------------------------
+ * Function: be_initialize_library
+ * Call to initialize the static library. This initializes the debug traces.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-----------------------------------------------------
+ */
+BESTATUS be_initialize_library(void
+ );
+
+/*
+ *---------------------------------------------------
+ * Function: be_function_and_chip_create
+ * Create both function and chip object with one call.
+ * The lower level API will rarely * use more than one function object.
+ * sa_dev - Previously created device.
+ * function_type -
+ * mailbox_sgl - SGL with length equal to sizeof(MCC_MAILBOX). This must be
+ * physically contiguous. The starting address must be
+ * aligned to 16 byte boundary.
+ * emulation_sgl - SGL with length equal to one page . Must be physically
+ * contiguous. Starting address must be 16 byte aligned.
+ * function_object - On input, a pointer to an allocated function object. On
+ * output, it is initialized. This is an opaque object.
+ * Do not access the members.
+ * chip - On input this is a pointer to an allocated chip object.
+ * On output, it is initialized. This is an opaque object.
+ * Do not access the members.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------
+ */
+BESTATUS
+be_function_and_chip_create(IN SA_DEV *sa_dev,
+ IN u32 function_type,
+ IN PSA_SGL mailbox_sgl,
+ IN PSA_SGL emulation_sgl,
+ OUT PBE_FUNCTION_OBJECT function_object,
+ OUT PBE_CHIP_OBJECT chip);
+
+/*
+ *---------------------------------------------------
+ * Function: be_function_object_create
+ * Create function object .
+ * sa_dev - Previously created device.
+ * function_type -
+ * mailbox_sgl - SGL with length equal to sizeof(MCC_MAILBOX).
+ * This must be physically contiguous. The starting
+ * address must be aligned to 16 byte boundary.
+ * function_object - On input this is a pointer to an allocated function
+ * object. On output, it is initialized. This is an
+ * opaque object. Do not access the members.
+ * chip - On input this is a pointer to an allocated chip object.
+ * On output, it is initialized. This is an opaque object.
+ * Do not access the members.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *----------------------------------------------------
+ */
+BESTATUS
+be_function_object_create(IN SA_DEV *sa_dev,
+ IN u32 function_type,
+ IN PSA_SGL mailbox_sgl,
+ OUT PBE_FUNCTION_OBJECT function_object,
+ OUT PBE_CHIP_OBJECT chip);
+
+/*
+ *-----------------------------------------------
+ * Function: be_chip_object_create
+ * Create chip object .
+ * chip - On input this is a pointer to an allocated chip object.
+ * On output, it is initialized. This is an opaque object.
+ * Do not access the members.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_chip_object_create(OUT PBE_CHIP_OBJECT chip);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_and_chip_destroy
+ * This destroys the function and chip object created by the
+ * be_function_and_chip_create function. It assumes that all
+ * sub-objects created for this function have already been
+ * destroyed -- it asserts if this is not true. This function is called by
+ * be_function_cleanup -- Use be_function_cleanup to automatically cleanup all
+ * sub-objects.
+ * function_object - Previously created function object.
+ * chip - Previously created chip object.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_and_chip_destroy(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_CHIP_OBJECT chip);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_object_destroy
+ * This destroys the function object created by the
+ * be_function_object_create function. It assumes that all
+ * sub-objects created for this function have already been destroyed
+ * -- it asserts if this is not true. This function is called by
+ * be_function_cleanup --
+ * Use be_function_cleanup to automatically cleanup all sub-objects.
+ * function_object - Previously created function object.
+ * chip - Previously created chip object.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_object_destroy(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_CHIP_OBJECT chip);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_chip_object_destroy
+ * This destroys the chip object created by the
+ * be_chip_object_create function. It assumes that all sub-objects
+ * created for this chip have already been destroyed -- it
+ * asserts if this is not true. This function is called by
+ * be_function_cleanup -- Use be_function_cleanup to automatically
+ * cleanup all sub-objects.
+ * chip - Previously created chip object.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_chip_object_destroy(IN PBE_CHIP_OBJECT chip);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_cleanup
+ * This function destroys all objects that reference the function
+ * object including the all queues (mcc, etx, erx, iscsi/wrbq/defq, eq) -
+ * iscsi ooo buffers - software jell buffers (during emulation) -
+ * template header buffers (if host based) - WDMA
+ * zero buffer (during emulation) - vlan tags - multicast addresses - rss
+ * configuration - wake on lan entries (ACPI) - chip object -
+ * function_object All objects are destroyed with synchronous ioctls
+ * that poll for their completions. This
+ * function is optional, all objects can be explicitly cleaned up.
+ * function_object - Previously created function object
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_function_cleanup(PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_get_function_number
+ * Returns the PCI function number.
+ * function_object - Previously created function object
+ * return function_number -
+ *---------------------------------------------------------------
+ */
+u32
+be_function_get_function_number(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_get_function_type
+ * Returns the function type.
+ * function_object -
+ * return function_type -
+ *---------------------------------------------------------------
+ */
+u32 be_function_get_function_type(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_is_iscsi
+ * Returns TRUE for the ISCSI function.
+ * function_object -
+ * return is_iscsi -
+ *---------------------------------------------------------------
+ */
+STATIC INLINE boolean
+be_function_is_iscsi(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_is_networking
+ * Returns TRUE for the networking function.
+ * function_object -
+ * return is_networking -
+ *---------------------------------------------------------------
+ */
+STATIC INLINE boolean
+be_function_is_networking(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_copy_stats
+ * Copies the function object stats into the memory supplied by the caller.
+ * function_object - The previously created function object.
+ * stats - Pointer to a stat struct. The stats are copied.
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+STATIC INLINE void
+be_function_copy_stats(IN PBE_FUNCTION_OBJECT function_object,
+ OUT PBECLIB_FUNCTION_STATS stats);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_iscsi_ooo_buffers_post
+ * Posts out-of-order buffers to BladeEngine.
+ * function_object -
+ * page_count -
+ * sgl -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_iscsi_ooo_buffers_post(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 page_count, IN PSA_SGL sgl);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_iscsi_ooo_buffers_remove
+ * Removes the out-of-order buffers from the chip. The caller may
+ * free the memory when this function completes. All iSCSI connections
+ * must be closed first. This function is called as part of
+ * be_function_cleanup.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_iscsi_ooo_buffers_remove(IN PBE_FUNCTION_OBJECT
+ function_object);
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_nop
+ * Issues a NOP command to the MCC ring. The command is completed with
+ * a successful status. This can be used to pend operations until
+ * a short time in the future, since the callback function will
+ * be invoked upon command completion. The returned status
+ * will be BE_PENDING if the command was issued successfully.
+ * function_object -
+ * callback - Callback function invoked when the NOP completes.
+ * callback_context - Passed to the callback function.
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted
+ * to the MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received. It is always valid
+ * to pass a pointer to a generic BE_GENERIC_QUEUE_CONTEXT.
+ * However, the specific context structs are
+ * generally smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING
+ * (postive value) if the IOCTL completion is
+ * pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_nop(IN PBE_FUNCTION_OBJECT function_object,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_NOP_QUEUE_CONTEXT queue_context);
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_get_fw_version
+ * Retrieves the firmware version on the adpater. If the callback
+ * is NULL this call executes synchronously. If the callback is
+ * not NULL, the returned status will be BE_PENDING if the
+ * command was issued successfully.
+ * function_object -
+ * fw_version - Pointer to response buffer if callback is NULL.
+ * callback - Callback function invoked when the IOCTL completes.
+ * callback_context - Passed to the callback function.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_get_fw_version(IN PBE_FUNCTION_OBJECT function_object,
+ OUT IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD
+ * fw_version, IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_manage_FAT_log
+ * This routine can be used to manage the BladeEngine Fault Analysis
+ * Tool (FAT) log. This includes querying the FAT log size,
+ * retrieving the FAT log, and clearing the FAT log. The log data
+ * can be anaylzed by BladeEngine support tools to diagnose faults.
+ * Only host domains (domain 0) may issue this request.
+ * function_object -
+ * sgl - SGL representing the FAT log buffer landing space.
+ * The SGL should be page aligned. It does not
+ * require a virtual address.
+ * num_pages - The number of pages in the SGL. A value of zero (0)
+ * implies no FAT log data transfer will take place.
+ * The num_pages is limited to 27 pages.
+ * page_offset - The page_offset specifies the starting page
+ * offset when retrieving the FAT log. For example,
+ * a value of 0 requests data starting at byte
+ * offset 0 of the FAT log. Likewise, a value
+ * of 5 requests data starting at byte offset 20480 of
+ * the FAT log. A caller may choose to issue multiple
+ * queries when the FAT log buffer size is larger
+ * than the number of pages specified.
+ * clear_log - Set to clear the log.
+ * log_size - The size of the BladeEngine FAT log in bytes.
+ * bytes_transferred - The number of FAT log data bytes transferred.
+ * return status - BE_SUCCESS (0) on success. Negative error code
+ * on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_manage_FAT_log(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 num_pages,
+ IN u32 page_offset,
+ IN boolean clear_log,
+ OUT u32 *log_size,
+ OUT u32 *bytes_transferred);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_query_firmware_config
+ * Queries the firmware configuration currently loaded. This
+ * configuration includes information regarding the EP processor
+ * configuration for various Upper Layer Protocols.
+ * function_object -
+ * config - The configuration parameters currently loaded by firmware.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_query_firmware_config(IN PBE_FUNCTION_OBJECT function_object,
+ OUT BE_FIRMWARE_CONFIG *config);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_config_red
+ * This function configures global and/or ULP specific Random Early Drop (RED)
+ * functionality.
+ * function_object -
+ * parameters - The RED parameters. Only parameters for the
+ * chutes owned by the
+ * current PCI function are applied.
+ * callback - Optional callback function.
+ * callback_context - Optional context for callback function.
+ * queue_context - Optional context for queueing the IOCTL.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_config_red(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_RED_PARAMETERS parameters,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_CONFIG_RED_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_config_port_equalization
+ * This function configures or returns the XAUI port equalization
+ * parameters of BladeEngine.
+ * function_object -
+ * parameters - XAUI port equalization parameters.
+ * write - Set (1) to write the parameters, otherwise
+ * clear (0) to read the
+ * parameters.
+ * callback - Optional callback function.
+ * callback_context - Optional context for callback function.
+ * queue_context - Optional context for queueing the IOCTL.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_config_port_equalization(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN OUT
+ PIOCTL_COMMON_PORT_EQUALIZATION_PARAMS
+ parameters, IN boolean write,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN
+ PBE_CONFIG_PORT_EQUALIXATION_QUEUE_CONTEXT
+ queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_passthru_ioctl
+ * This routine issues an embedded IOCTL in pass-through mode.
+ * function_object -
+ * payload - The embedded payload for the MCC_WRB structure.
+ * The input buffer is
+ * overwritten with response data.
+ * callback - Callback function invoked when the IOCTL completes.
+ * callback_context - Callback context passed to the callback function.
+ * return status - BE_SUCCESS (0) on success. Negative error code on
+ * failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_passthru_ioctl(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT MCC_WRB_PAYLOAD *payload,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_modify_delay
+ * Changes the EQ delay for a group of EQs.
+ * function_object -
+ * num_eq - The number of EQs in the eq_array to adjust.
+ * This also is the number of delay values in the
+ * eq_delay_array.
+ * eq_array - Array of BE_EQ_OBJECT pointers to adjust.
+ * eq_delay_array - Array of "num_eq" timer delays in units of
+ * microseconds. The be_eq_query_delay_range ioctl
+ * returns the resolution and range of legal EQ delays.
+ * callback -
+ * callback_context -
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted to
+ * the MCC ring when space becomes available. All
+ * queued commands will be posted to the ring
+ * in the order they are received. It is always
+ * valid to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the
+ * specific context structs
+ * are generally smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eq_modify_delay(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 num_eq,
+ IN BE_EQ_OBJECT **eq_array,
+ IN u32 *eq_delay_array,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_EQ_MODIFY_DELAY_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_query_delay_range
+ * Queries the resolution and range allowed for EQ delay. This is
+ * a constant set by the firmware, so it may be queried one time
+ * at system boot. It is the same for all EQs. This is a synchronous IOCTL.
+ * function_object -
+ * eq_delay_resolution - Resolution of EQ delay in microseconds.
+ * eq_delay_max - Max value of EQ delay in microseconds.
+ * return status - BE_SUCCESS (0) on success. Negative error code
+ * on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eq_query_delay_range(IN PBE_FUNCTION_OBJECT function_object,
+ OUT u32 *eq_delay_resolution,
+ OUT u32 *eq_delay_max);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_create
+ * Creates an eq_object. This is a synchronous IOCTL.
+ * function_object -
+ * sgl - No virtual address required.
+ * eqe_size - EQ entry size in bytes. Either 4 or 16.
+ * num_entries - Power of 2, fom 256 to 4k.
+ * watermark - Eventable CQs only. CEV_WMARK_* or ~0UL for no watermark.
+ * timer_delay - Interrupt timer delay. ~0UL disables timer. Otherwise,
+ * it is eq_delay_resolution units up to eq_delay_max
+ * decimal. The resolution and max are queried from
+ * be_eq_query_delay_range. e.g. If an 16 us delay
+ * is required, timer_delay should be
+ * 8us/eq_delay_resolution.
+ * eq_object - Created EQ object.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 eqe_size,
+ IN u32 num_entries,
+ IN u32 watermark,
+ IN u32 timer_delay, OUT BE_EQ_OBJECT *eq_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_fake_create
+ * Creates an eq_object that does not have an associated memory
+ * ring. The object is used to generate an interrupt from software.
+ * The EQ will interrupt the host every time the EQ is rearmed,
+ * after the EQ delay expires. The EQ should always be rearmed with a
+ * num_popped count of 0 in the doorbell register.
+ * The be_function_enable_interrupts function will cause an
+ * immediate interrupt from this EQ. This is a synchronous IOCTL.
+ * function_object -
+ * timer_delay - Interrupt timer delay. ~0UL disables timer.
+ * Otherwise, it is eq_delay_resolution units up to
+ * eq_delay_max decimal. The resolution and max are
+ * queried from be_eq_query_delay_range. e.g. If an
+ * 16 us delay is required, timer_delay should be
+ * 16 us/eq_delay_resolution.
+ * eq_object - Created EQ object.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eq_fake_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 timer_delay, OUT BE_EQ_OBJECT *eq_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_destroy
+ * Destroys an eq_object. This function is called as part of
+ * be_function_cleanup.
+ * eq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_eq_destroy(IN BE_EQ_OBJECT *eq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eq_get_id
+ * Return the allocated ID that must be used to ring the doorbell for the EQ.
+ *---------------------------------------------------------------
+ */
+u32 be_eq_get_id(IN BE_EQ_OBJECT *eq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_cq_create
+ * Creates a CQ. This uses a synchronous IOCTL.
+ * function_object -
+ * sgl - No virtual address required, except for MCC CQ.
+ * length - Length is bytes of queue. Number of entries is
+ * power of 2, from 256 to 1k. solicited_eventable -
+ * If TRUE, only CQEs with solicited event bit cause
+ * eqe write.
+ * no_delay - If eventable, TRUE means force interrupt
+ * immediately (ignore watermark & timer).
+ * wm_thresh - If eventable, watermark encodings CEV_WMARK_* or
+ * ~0UL for no watermark.
+ * eq_object - Optional, if set this is an eventable CQ.
+ * cq_object - Created CQ object.
+ * return status - BE_SUCCESS (0) on success.
+ * Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_cq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length,
+ IN boolean solicited_eventable,
+ IN boolean no_delay,
+ IN u32 wm_thresh,
+ IN PBE_EQ_OBJECT eq_object, OUT PBE_CQ_OBJECT cq_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_cq_destroy
+ * Destroys a CQ. All clients that reference this CQ must
+ * be destroyed first. This function is called as part of
+ * be_function_cleanup.
+ * cq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_cq_destroy(IN BE_CQ_OBJECT *cq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_cq_get_id
+ * Returns the allocated CQ id used for ringing the doorbell.
+ * cq -
+ * return id -
+ *---------------------------------------------------------------
+ */
+u32 be_cq_get_id(IN BE_CQ_OBJECT *cq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_mcc_ring_create
+ * This creates a MCC ring and switches from mailbox mode to ring mode.
+ * The number of outstanding MCC commands is the minimum of the
+ * number of entries in the ring and the number of context structures
+ * (i.e. num_context_entries). BECLIB uses the context entries to
+ * track outstanding MCC WRBs since they may complete out-of-order. You may
+ * provide zero context entries, which will limit BECLIB to one
+ * MCC WRB at a time.
+ * function_object -
+ * sgl - A virtual address is required.
+ * length - length in bytes
+ * context_array - Array of context structs. Each outstanding MCC WRB
+ * requires a context entry. BECLIB has 1 by
+ * default. The context array allows you to post
+ * more -- this must be non-pageable memory, but it is
+ * not used for DMA. Most likely the number of
+ * context structs will match the size of the
+ * MCC ring. Since commands complete out-of-order,
+ * this lets beclib fully utilize the ring. However,
+ * the size may be either lower or higher than
+ * the ring size. num_context_entries - number of
+ * context structs
+ * cq - Associated completion queue created with an SGL
+ * with a mapped virtual address
+ * mcc - On input this is a pointer to an allocated
+ * MCC_OBJECT On ouput this is a created MCC object.
+ * This is an opaque object. Do not reference any
+ * members.
+ * return status - BE_SUCCESS (0) on success.
+ * Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_mcc_ring_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length,
+ IN PBE_MCC_WRB_CONTEXT context_array,
+ IN u32 num_context_entries,
+ IN PBE_CQ_OBJECT cq, OUT PBE_MCC_OBJECT mcc);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_mcc_ring_destroy
+ * Cleans up MCC ring and switches to mailbox mode. This function is
+ * called as part of be_function_cleanup.
+ * mcc_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_mcc_ring_destroy(IN PBE_MCC_OBJECT mcc_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_mcc_process_cq
+ * Processes mcc completions. This should be called from
+ * the interrupt or DPC to process the MCC cq, when a corresponding
+ * event queue entry is received. It can also be called to
+ * poll the CQ from a timer routine for non-eventable completions.
+ * Keep in mind, only one thread can be inside beclib at any
+ * given time. That means this function must be
+ * serialized with the posting of MCC WRBs.
+ * mcc_object -
+ * rearm - rearm should be TRUE only if called due to EQE
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_mcc_process_cq(IN BE_MCC_OBJECT *mcc_object, IN boolean rearm);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_mcc_add_async_event_callback
+ * mcc_object -
+ * callback - Function callback invoked when an asynchronous event
+ * is received on the MCC cq. It follows the prototype:
+ * typedef void (BECALL *MCC_ASYNC_EVENT_CALLBACK) (PVOID context,
+ * u32 event_code, PVOID event);
+ *
+ * The context parameter is a copy of the
+ * callback_context pointer provided to this function.
+ * The event_code is the code from the common
+ * portion of the event entry. The event
+ * parameter is a pointer to the 16 byte async
+ * event message.
+ * callback_context - Passed to the callback function.
+ * return status - BE_SUCCESS (0) on success. Negative error code on
+ * failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_mcc_add_async_event_callback(IN BE_MCC_OBJECT *mcc_object,
+ IN MCC_ASYNC_EVENT_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_pci_soft_reset
+ * This function is called to issue a BladeEngine soft reset. Callers
+ * should acquire the soft reset semaphore before calling this function.
+ * Additionaly, callers should ensure they cannot be pre-empted while
+ * the routine executes. Upon completion of this routine, callers
+ * should release the reset semaphore. This routine implicitly waits
+ * for BladeEngine POST to complete.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_pci_soft_reset(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_acquire_reset_semaphore
+ * Acquires the reset semaphore. If success is returned, the caller owns
+ * the reset semaphore. Otherwise the caller does not own the
+ * reset semaphore. Callers must acquire the reset semaphore before
+ * inducing a BladeEngine runtime reset. Callers must also
+ * release the reset semaphore once they are done with a soft reset.
+ * Release of the reset semaphore is accomplished with
+ * be_release_reset_semaphore.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_acquire_reset_semaphore(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_release_reset_semaphore
+ * Releases the reset semaphore. Callers must release the reset
+ * semaphore once they are done with a soft reset.
+ * function_object -
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+void be_release_reset_semaphore(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_drive_POST
+ * This function is called to drive BladeEngine POST. The
+ * caller should ensure they cannot be pre-empted while this routine
+ * executes.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_drive_POST(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_defq_create
+ * Creates a default PDU ring for the current protection domain. Each queue
+ * contains 8 byte physical addresses to default PDU buffers.
+ * function_object -
+ * sgl - no virtual address required
+ * length - bytes in total ring
+ * default_buffer_length - bytes in each buffer posted to ring
+ * cq_object - cq that will receive completions
+ * defq -
+ * return status - BE_SUCCESS (0) on success. Negative
+ * error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_iscsi_defq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length,
+ IN u32 default_buffer_length,
+ IN PBE_CQ_OBJECT cq_object,
+ OUT PBE_DEFAULT_PDU_QUEUE_OBJECT defq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_defq_destroy
+ * Destroys the default queue. All connections for the PD should
+ * be torn down first. This function is called as part of
+ * be_function_cleanup.
+ * defq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_iscsi_defq_destroy(PBE_DEFAULT_PDU_QUEUE_OBJECT defq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_defq_get_id
+ * Gets the allocated ID for this queue. The id is used to
+ * ring the doorbell to post buffers to the default queue.
+ * defq -
+ * return id -
+ *---------------------------------------------------------------
+ */
+u32 be_iscsi_defq_get_id(IN PBE_DEFAULT_PDU_QUEUE_OBJECT defq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_wrb_queue_create
+ * Creates a WRB ring. Use the "get_cid" function to query
+ * the corresponding cid for the ring.
+ * function_object -
+ * sgl -
+ * num_entries - max = 32k / sizeof(ISCSI_INITIATOR_WRB)
+ * wrbq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_iscsi_wrb_queue_create(PBE_FUNCTION_OBJECT function_object,
+ PSA_SGL sgl,
+ u32 num_entries,
+ PBE_ISCSI_WRB_QUEUE_OBJECT wrbq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_wrb_queue_destroy
+ * Destroys the wrb ring. Make sure the connection is torn down
+ * before destroying the ring. This function is called as part
+ * of be_function_cleanup.
+ * wrbq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_iscsi_wrb_queue_destroy(IN PBE_ISCSI_WRB_QUEUE_OBJECT wrbq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_wrbq_get_cid
+ * Queries the allocated cid for the wrbq.
+ * wrbq -
+ * return cid -
+ *---------------------------------------------------------------
+ */
+u32 be_iscsi_wrbq_get_cid(IN PBE_ISCSI_WRB_QUEUE_OBJECT wrbq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_post_sgl_pages
+ * Posts memory for iSCSI SGLs to the chip for the given
+ * protection domain. The memory may be posted with multiple calls
+ * to this function by incrementing the page_offset. The SGL
+ * does not require a valid virtual address. The SGL should be page aligned.
+ * This must be done before any connections are offloaded.
+ * 1 page table must be posted to the chip per 2MB of frags.
+ * function_object -
+ * sgl - memory is posted starting with page 0 in this sgl
+ * page_offset - offset on the chip where the pages are mapped
+ * num_pages - number of pages to post from the current sgl
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_iscsi_post_sgl_pages(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 page_offset, IN u32 num_pages);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_iscsi_remove_sgl_pages
+ * Removes all the sgl memory for the given protection domain. This
+ * function is called as part of be_function_cleanup.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_iscsi_remove_sgl_pages(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_sq_create
+ * Creates an ethernet send ring.
+ * function_object -
+ * sgl - no virtual address required
+ * length_in_bytes -
+ * type - The type of ring to create.
+ * ulp - The requested ULP number for the ring. This
+ * should be zero based, i.e. 0,1,2. This must be valid
+ * NIC ULP based on the firmware config. All
+ * doorbells for this ring must be sent to this ULP. The
+ * first network ring allocated for each ULP are
+ * igher performance than subsequent rings.
+ * cq_object - cq object for completions
+ * eth_sq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_sq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length_in_bytes,
+ IN u32 type,
+ IN u32 ulp,
+ IN PBE_CQ_OBJECT cq_object, OUT PBE_ETHSQ_OBJECT eth_sq);
+
+/*
+ * This is a set of optional parameters for be_eth_sq_create_ex. Certain
+ * ring types require additional parameters provided in this struct.
+ */
+typedef struct _BE_ETH_SQ_PARAMETERS {
+ u32 port;
+ u32 rsvd0[2];
+} SG_PACK BE_ETH_SQ_PARAMETERS, *PBE_ETH_SQ_PARAMETERS;
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_sq_create_ex
+ * Creates an ethernet send ring - extended version with additional parameters
+ * function_object -
+ * sgl - no virtual address required
+ * length_in_bytes -
+ * type - The type of ring to create.
+ * ulp - The requested ULP number for the ring. This
+ * should be zero based, i.e. 0,1,2. This must be
+ * valid NIC ULP based on the firmware config.
+ * All doorbells for this ring must be sent to
+ * this ULP. The first network ring allocated for
+ * each ULP are higher performance than subsequent rings.
+ * cq_object - cq object for completions
+ * ex_parameters - Additional parameters (that may increase in future
+ * revisions). These parameters are only used for
+ * certain ring types -- see BE_ETH_SQ_PARAMETER
+ * for details.
+ * eth_sq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_sq_create_ex(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length_in_bytes,
+ IN u32 type,
+ IN u32 ulp,
+ IN PBE_CQ_OBJECT cq_object,
+ IN BE_ETH_SQ_PARAMETERS *ex_parameters,
+ OUT PBE_ETHSQ_OBJECT eth_sq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_sq_destroy
+ * Destroys an ethernet send ring. The driver must wait for
+ * all send completions before destroying the ring. This function
+ * is called as part of be_function_cleanup.
+ * eth_sq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_eth_sq_destroy(IN PBE_ETHSQ_OBJECT eth_sq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_sq_get_id
+ * Query the allocated id for the send ring. This ID is used
+ * to ring the doorbell.
+ * eth_sq -
+ * return id -
+ *---------------------------------------------------------------
+ */
+u32 be_eth_sq_get_id(IN PBE_ETHSQ_OBJECT eth_sq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_set_flow_control
+ * This function sets the flow control characteristics of BladeEngine.
+ * function_object -
+ * txfc_enable -
+ * rxfc_enable -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_set_flow_control(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean txfc_enable, IN boolean rxfc_enable);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_get_flow_control
+ * This function gets the flow control characteristics of BladeEngine.
+ * function_object -
+ * txfc_enable -
+ * rxfc_enable -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_get_flow_control(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean *txfc_enable,
+ IN boolean *rxfc_enable);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_set_qos
+ * This function sets the ethernet transmit Quality of Service (QoS)
+ * characteristics of BladeEngine for the domain. All ethernet transmit
+ * rings of the domain will evenly share the bandwidth. The exeception
+ * to sharing is the host primary (super) ethernet transmit
+ * ring as well as the host ethernet forwarding ring for missed offload
+ * data.
+ * function_object -
+ * max_bps - the maximum bits per second in units of
+ * 10 Mbps (valid 0-100)
+ * max_pps - the maximum packets per second in units
+ * of 1 Kpps (0 indicates no limit)
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_set_qos(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 max_bps, IN u32 max_pps);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_get_qos
+ * This function retrieves the ethernet transmit Quality of Service (QoS)
+ * characteristics for the domain.
+ * function_object -
+ * max_bps - the maximum bits per second in units of 10
+ * Mbps (valid 0-100)
+ * max_pps - the maximum packets per second in units of
+ * 1 Kpps (0 indicates no limit)
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_get_qos(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 *max_bps, IN u32 *max_pps);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_set_frame_size
+ * This function sets the ethernet maximum frame size. The
+ * previous values are returned.
+ * function_object -
+ * tx_frame_size - maximum transmit frame size in bytes
+ * rx_frame_size - maximum receive frame size in bytes
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_set_frame_size(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT u32 *tx_frame_size,
+ IN OUT u32 *rx_frame_size);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_create
+ * Creates an ethernet receive ring for posting rx buffers. Each
+ * buffer posted to the ring should be the size indicated from
+ * calling the be_eth_rq_get_frag_size function.
+ * Only the host protection domain can receive broadcast/multicast
+ * frames. It can choose to receive the CQ entries for these
+ * frames on a separate completion queue, or it can
+ * use the same CQ. This is determines by the bcmc_cq_object parameter.
+ * function_object -
+ * sgl -
+ * cq_object -
+ * bcmc_cq_object - optional
+ * eth_rq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN PBE_CQ_OBJECT cq_object,
+ IN PBE_CQ_OBJECT bcmc_cq_object,
+ OUT PBE_ETHRQ_OBJECT eth_rq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_destroy
+ * Destroys an ethernet receive ring. This function is called as part of
+ * be_function_cleanup.
+ * eth_rq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS be_eth_rq_destroy(IN PBE_ETHRQ_OBJECT eth_rq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_destroy_options
+ * Destroys an ethernet receive ring with finer granularity
+ * options than the standard be_eth_rq_destroy() API function.
+ * eth_rq -
+ * flush - Set to 1 to flush the ring, set to 0 to
+ * bypass the flush and force invalidation.
+ * callback - Callback function on completion
+ * callback_context - Callback context
+ * return status - BE_SUCCESS (0) on success. Negative error
+ * code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_destroy_options(IN PBE_ETHRQ_OBJECT eth_rq,
+ IN boolean flush,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_destroy_async
+ * Same as be_eth_rq_destroy, but this version allows an async callback.
+ * eth_rq -
+ * callback -
+ * callback_context -
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_destroy_async(IN PBE_ETHRQ_OBJECT eth_rq,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_get_id
+ * Queries the allocated ID for the ethernet receive ring.
+ * This should be used for ringing the doorbell to post buffers.
+ * EthRq -
+ * return id -
+ *---------------------------------------------------------------
+ */
+u32 be_eth_rq_get_id(IN PBE_ETHRQ_OBJECT EthRq);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_set_frag_size
+ * Changes the global ethernet receive fragment size. This
+ * is very expensive and should rarely be done. This function may
+ * require a reboot for the fragsize to take affect. If the function
+ * succeeds, and the returned actual_frag_size_bytes does not match
+ * new_frag_size_bytes, then the driver must continue to use
+ * the actual_frag_size_bytes until the next reboot.
+ * function_object -
+ * new_frag_size_bytes - New frag size to set. This must be a
+ * power of 2, from 128 to 16k.
+ * actual_frag_size_bytes - The current actual frag size. If the function
+ * succeeds, and this differs from the
+ * new_frag_size_bytes, then the new frag
+ * size will be applied after a reboot.
+ * The driver must use this size.
+ * return status - BE_SUCCESS (0) on success. Negative error
+ * code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_set_frag_size(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 new_frag_size_bytes,
+ OUT u32 *actual_frag_size_bytes);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_eth_rq_get_frag_size
+ * Queries the global ethernet receive fragment size. All drivers
+ * should query the frag size and use the specified size.
+ * Alternatively, they should use the maximum fragment size.
+ * function_object -
+ * frag_size_bytes - The current actual frag size. If the function
+ * succeeds, and this differs from the
+ * new_frag_size_bytes, then the new frag size will be
+ * applied after a reboot. The driver must use this size.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_get_frag_size(IN PBE_FUNCTION_OBJECT function_object,
+ OUT u32 *frag_size_bytes);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_prepare_embedded_ioctl
+ * Use the BE_FUNCTION_PREPARE_EMBEDDED_IOCTL macro, instead of calling this
+ * function directly.
+ * function_object -
+ * wrb -
+ * payload_length -
+ * request_length -
+ * response_length -
+ * opcode -
+ * subsystem -
+ * return ioctl -
+ *---------------------------------------------------------------
+ */
+PVOID
+be_function_prepare_embedded_ioctl(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN u32 payload_length,
+ IN u32 request_length,
+ IN u32 response_length,
+ IN u32 opcode, IN u32 subsystem);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_prepare_nonembedded_ioctl
+ * Use the BE_FUNCTION_PREPARE_NONEMBEDDED_IOCTL macro, instead of
+ * calling this function
+ * directly.
+ * function_object -
+ * wrb -
+ * ioctl_header_va -
+ * ioctl_header_pa -
+ * payload_length -
+ * request_length -
+ * response_length -
+ * opcode -
+ * subsystem -
+ * return ioctl -
+ *---------------------------------------------------------------
+ */
+PVOID
+be_function_prepare_nonembedded_ioctl(IN PBE_FUNCTION_OBJECT
+ function_object, IN PMCC_WRB wrb,
+ IN PVOID ioctl_header_va,
+ IN u64 ioctl_header_pa,
+ IN u32 payload_length,
+ IN u32 request_length,
+ IN u32 response_length,
+ IN u32 opcode, IN u32 subsystem);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_lock_mcc
+ * Acquires the MCC posting lock. This lock must be held while calling
+ * be_function_post_mcc_wrb. If using the be_function_peek_mcc_wrb,
+ * the caller should acquire the lock before the peek function
+ * call and hold it until after the post function call. Additionally,
+ * the "peeked" WRB should not be accessed after this lock
+ * is released since another thread may reuse the WRB.
+ * function_object -
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+void be_function_lock_mcc(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_unlock_mcc
+ * Releases the MCC posting lock acquired by calling be_function_lock_mcc.
+ * function_object -
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+void be_function_unlock_mcc(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_peek_mcc_wrb
+ * Returns a pointer to the next WRB to post, either the mailbox
+ * buffer or the next WRB in the ring. When using this function,
+ * the caller must ensure that no other thread
+ * will post an MCC wrb until after this WRB is posted.
+ * function_object -
+ * return wrb - Pointer to the next WRB to post, NULL on failure.
+ *---------------------------------------------------------------
+ */
+PMCC_WRB be_function_peek_mcc_wrb(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_post_mcc_wrb
+ * Posts a WRB to either mailbox or mcc ring. The wrb pointer
+ * may be the pointer returned by the be_function_peek_mcc_wrb function.
+ * It not, the wrb is copied into the ring/mailbox. The callback may
+ * be NULL, in which case the function will not return until the
+ * WRB completes. It will poll the mailbox status or MCC CQ in that case.
+ * Other outstanding MCC WRBs may be completed in this context
+ * if the callback is NULL. This function (nor any other synchronous
+ * IOCTL function) may be called from an MCC_WRB_CQE_CALLBACK context.
+ * Only asynchronous IOCTLs may be posted during the completion of
+ * another IOCTL. Otherwise, the software will deadlock.
+ * funcobj -
+ * wrb -
+ * callback -
+ * callback_context -
+ * optional_ioctl_va -
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_function_post_mcc_wrb(IN PBE_FUNCTION_OBJECT funcobj,
+ IN PMCC_WRB wrb,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_mac_address_read_write
+ * Reads or writes the MAC address.
+ * function_object -
+ * port1 - Specifies port 0 or 1
+ * mac1 - Specifies addres 0 or 1 (BE has 2 per port)
+ * mgmt - Specifies the management port. If TRUE, the
+ * port1 and mac1
+ * parameters are ignored.
+ * write - If TRUE, the MAC address is set.
+ * permanent - If TRUE, the MAC read is the permanent address
+ * mac_address - Address to set, or address returned.
+ * callback - optional
+ * callback_context - optional
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_mac_address_read_write(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean port1,
+ IN boolean mac1,
+ IN boolean mgmt,
+ IN boolean write,
+ IN boolean permanent,
+ IN OUT PSA_MAC_ADDRESS mac_address,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_multicast_config
+ * Writes all multicast addresses for this protection domain.
+ * This function is called as part of be_function_cleanup to
+ * remove all multicast filters.
+ * function_object -
+ * promiscuous - TRUE, enables promiscuous mode where all multicast
+ * packets are passed up. Allows supporting >32
+ * multicast addresses.
+ * num - number of mac addresses in the table. Max=32.
+ * mac_table -
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * struct. If the MCC WRB ring is full, this
+ * structure is used to queue the operation. It
+ * will be posted to the MCC ring when space
+ * becomes available. All queued commands will be
+ * posted to the ring in the order they are
+ * received. It is always valid to pass a pointer
+ * to a generic BE_GENERIC_QUEUE_CONTEXT. However, the
+ * specific context structs are generally smaller
+ * than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_multicast_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean promiscuous,
+ IN u32 num,
+ IN SA_MAC_ADDRESS *mac_table,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_MULTICAST_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_vlan_config
+ * Writes all vlan tags for this protection domain. This function
+ * is called as part of be_function_cleanup to remove all vlan filters.
+ * function_object -
+ * promiscuous - TRUE, enables promiscuous mode where all
+ * vlan packets are passed up the stack. Allows
+ * supporting >32 vlan tags.
+ * num - Number of vlan tags in the array.
+ * vlan_tag_array -
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is used
+ * to queue the operation. It will be posted to the
+ * MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received. It is always valid
+ * to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the specific
+ * context structs are generally smaller than
+ * the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_vlan_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean promiscuous,
+ IN u32 num,
+ IN u16 *vlan_tag_array,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_VLAN_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_wake_on_lan_config
+ * Configures wake-on-lan for the controller. Wake-on-lan is only
+ * supported for the host system virtual machine - wake-on-lan is not
+ * supported per protection domain. To enable magic packet
+ * reception, use null pointer arguments for pattern & pattern mask,
+ * set magic_packet_enable to true, and set the port enables
+ * to true. To disable magic packet reception, use null pointer
+ * arguments for pattern & pattern mask, set magic_packet_enable to true,
+ * and set the port enables to false. To remove a pattern, set both
+ * enable_port0 and enable_port1 to FALSE, and provide the index
+ * you previously used to enable the pattern. This function is
+ * not called as part of be_function_cleanup to remove all wake-on-lan
+ * patterns, since be_function_cleanup could be called when the
+ * system wants to wake up on a magic or interesting packet.
+ * function_object -
+ * enable_port0 - If TRUE, enable this pattern for port0.
+ * enable_port1 - If TRUE, enable this pattern for port1.
+ * magic_packet_enable - If TRUE, enable magic packet for the enabled ports.
+ * index - index 0-3 for the packet to program
+ * pattern - 128 byte magic pattern
+ * pattern_mask - 128 bit mask indicating which bytes in the
+ * pattern should be matched.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted
+ * to the MCC ring when space becomes available.
+ * All queued commands will be posted to the
+ * ring in the order they are received. It is
+ * always valid to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the specific
+ * context structs are generally smaller than
+ * the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING
+ * (postive value) if the IOCTL completion
+ * is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_wake_on_lan_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean enable_port0,
+ IN boolean enable_port1,
+ IN boolean magic_packet_enable,
+ IN u32 index,
+ IN PVOID pattern,
+ IN PVOID pattern_mask,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_WAKE_ON_LAN_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_rss_config
+ * Configures Receive Side Scaling for the host networking function.
+ * This function is called as part of be_function_cleanup
+ * to disable RSS.
+ * function_object -
+ * rss_type - Use enumeration ENABLE_RSS_ENUM.
+ * num_cq - Number of RSS CQs. 0, 2, 3, or 4
+ * cq_id_array - Array of num_cq IDs for RSS CQs.
+ * default_cq_id - CQ id for the default non-RSS ethernet CQ.
+ * flush_mask - Mask of CQ ids to flush.
+ * hash - 16 byte hash.
+ * cpu_table_length - bytes (power of 2 from 2 to 128)
+ * cpu_table - cpu_table_length bytes. Each byte
+ * indicates a CPU from 0 to num_cq-1.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * struct. If the MCC WRB ring is full, this
+ * structure is used to queue the operation. It
+ * will be posted to the MCC ring when space
+ * becomes available. All queued commands will be
+ * posted to the ring in the order they are
+ * received. It is always valid to pass
+ * a pointer to a generic BE_GENERIC_QUEUE_CONTEXT.
+ * However, the specific context structs
+ * are generally smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING
+ * (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_rss_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 rss_type,
+ IN u32 num_cq,
+ IN u32 *cq_id_array,
+ IN u32 default_cq_id,
+ IN u32 flush_mask,
+ IN PVOID hash,
+ IN u32 cpu_table_length,
+ IN u8 *cpu_table,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_RSS_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_link_status
+ * Queries the link status.
+ * function_object -
+ * link_status - returned status
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted
+ * to the MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received. It is always valid
+ * to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the specific
+ * context structs are generally smaller than
+ * the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_link_status(IN PBE_FUNCTION_OBJECT function_object,
+ OUT BE_LINK_STATUS *link_status,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_LINK_STATUS_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_query_eth_statistics
+ * Queries the ethernet statistics. The resulting statistics are
+ * stored in the ioctl response buffer.
+ * function_object -
+ * va_for_ioctl - Virtual address of the IOCTL buffer. This buffer must be
+ * physically contiguous.
+ * pa_for_ioctl - Physical address of the IOCTL buffer. This buffer must
+ * be physically contiguous.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * struct. If the MCC WRB ring is full, this
+ * structure is used to queue the operation.
+ * It will be posted to the MCC ring when space
+ * becomes available. All queued commands will be posted
+ * to the ring in the order they are received.
+ * It is always valid to pass a pointer to a
+ * generic BE_GENERIC_QUEUE_CONTEXT. However, the
+ * specific context structs are generally smaller than
+ * the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING (postive value)
+ * if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_query_eth_statistics(IN PBE_FUNCTION_OBJECT function_object,
+ IN IOCTL_ETH_GET_STATISTICS *va_for_ioctl,
+ IN u64 pa_for_ioctl,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_ETH_STATS_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_promiscuous
+ * Enables or disables promiscuous mode for each MAC port.
+ * function_object -
+ * enable_port0 - Enable/Disable promiscuous mode on port 0.
+ * enable_port1 - Enable/Disable promiscuous mode on port 1.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * struct. If the MCC WRB ring is full, this
+ * structure is used to queue the operation.
+ * It will be posted to the MCC ring when space
+ * becomes available. All queued commands will be
+ * posted to the ring in the order they are
+ * received. It is always valid to pass a
+ * pointer to a generic BE_GENERIC_QUEUE_CONTEXT.
+ * However, the specific context structs are
+ * generally smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_promiscuous(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean enable_port0,
+ IN boolean enable_port1,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_PROMISCUOUS_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_force_failover
+ * Forces failure of all traffic to the specified MAC port. Use
+ * the be_rxf_link_status to query to active port. Automatic failover
+ * feature of BladeEngine is implicitly disabled with this call.
+ * function_object -
+ * port - Port to use, 0 or 1.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * BE_QUEUE_CONTEXT struct. If the MCC WRB ring
+ * is full, this structure is used to queue
+ * the operation. It will be posted to the
+ * MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING
+ * (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_force_failover(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 port,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_FORCE_FAILOVER_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_rxf_filter_config
+ * Configures BladeEngine ethernet receive filter settings.
+ * function_object -
+ * settings - Pointer to the requested filter settings.
+ * The response from BladeEngine will be placed back
+ * in this structure.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted to
+ * the MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received. It is always valid
+ * to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the
+ * specific context structs are generally
+ * smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING (postive value)
+ * if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_filter_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT NTWK_RX_FILTER_SETTINGS *settings,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_RXF_FILTER_QUEUE_CONTEXT queue_context);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_enable_interrupts
+ * Enables interrupts for the given PCI function.
+ * function_object -
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+void be_function_enable_interrupts(IN PBE_FUNCTION_OBJECT function_object);
+
+/*
+ *---------------------------------------------------------------
+ * Function: be_function_disable_interrupts
+ * Disables interrupts for the given PCI function.
+ * function_object -
+ * return return_type -
+ *---------------------------------------------------------------
+ */
+void
+be_function_disable_interrupts(IN PBE_FUNCTION_OBJECT function_object);
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __beclib_ll_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/bestatus.h benet/linux-2.6.24.2/drivers/message/beclib/bestatus.h
--- orig/linux-2.6.24.2/drivers/message/beclib/bestatus.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/bestatus.h 2008-02-14 15:23:07.802206648 +0530
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef _BESTATUS_H_
+#define _BESTATUS_H_
+
+#define BE_SUCCESS ((SA_STATUS)0x00000000L)
+
+/*
+ * MessageId: BE_PENDING
+ * The BladeEngine Driver call succeeded, and pended operation.
+ */
+#define BE_PENDING ((SA_STATUS)0x20070001L)
+#define BE_STATUS_PENDING (BE_PENDING)
+
+/*
+ * MessageId: BE_NOT_OK
+ * An error occurred.
+ */
+#define BE_NOT_OK ((SA_STATUS)0xE0070002L)
+
+/*
+ * MessageId: BE_STATUS_SYSTEM_RESOURCES
+ * Insufficient host system resources exist to complete the API.
+ */
+#define BE_STATUS_SYSTEM_RESOURCES ((SA_STATUS)0xE0070003L)
+
+/*
+ * MessageId: BE_STATUS_CHIP_RESOURCES
+ * Insufficient chip resources exist to complete the API.
+ */
+#define BE_STATUS_CHIP_RESOURCES ((SA_STATUS)0xE0070004L)
+
+/*
+ * MessageId: BE_STATUS_NO_RESOURCE
+ * Insufficient resources to complete request.
+ */
+#define BE_STATUS_NO_RESOURCE ((SA_STATUS)0xE0070005L)
+
+/*
+ * MessageId: BE_STATUS_BUSY
+ * Resource is currently busy.
+ */
+#define BE_STATUS_BUSY ((SA_STATUS)0xE0070006L)
+
+/*
+ * MessageId: BE_STATUS_INVALID_PARAMETER
+ * Invalid Parameter in request.
+ */
+#define BE_STATUS_INVALID_PARAMETER ((SA_STATUS)0xE0000007L)
+
+/*
+ * MessageId: BE_STATUS_NOT_SUPPORTED
+ * Requested operation is not supported.
+ */
+#define BE_STATUS_NOT_SUPPORTED ((SA_STATUS)0xE000000DL)
+
+/*
+ * ***************************************************************************
+ * E T H E R N E T S T A T U S
+ * ***************************************************************************
+ */
+
+/*
+ * MessageId: BE_ETH_TX_ERROR
+ * The Ethernet device driver failed to transmit a packet.
+ */
+#define BE_ETH_TX_ERROR ((SA_STATUS)0xE0070101L)
+
+/*
+ * ***************************************************************************
+ * S H A R E D S T A T U S
+ * ***************************************************************************
+ */
+
+/*
+ * MessageId: BE_STATUS_VBD_INVALID_VERSION
+ * The device driver is not compatible with this version of the VBD.
+ */
+#define BE_STATUS_INVALID_VERSION ((SA_STATUS)0xE0070402L)
+
+/*
+ * MessageId: BE_STATUS_DOMAIN_DENIED
+ * The operation failed to complete due to insufficient access
+ * rights for the requesting domain.
+ */
+#define BE_STATUS_DOMAIN_DENIED ((SA_STATUS)0xE0070403L)
+
+/*
+ * MessageId: BE_STATUS_TCP_NOT_STARTED
+ * The embedded TCP/IP stack has not been started.
+ */
+#define BE_STATUS_TCP_NOT_STARTED ((SA_STATUS)0xE0070409L)
+
+/*
+ * MessageId: BE_STATUS_NO_MCC_WRB
+ * No free MCC WRB are available for posting the request.
+ */
+#define BE_STATUS_NO_MCC_WRB ((SA_STATUS)0xE0070414L)
+
+#endif /* _BESTATUS_ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/beregister.h benet/linux-2.6.24.2/drivers/message/beclib/beregister.h
--- orig/linux-2.6.24.2/drivers/message/beclib/beregister.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/beregister.h 2008-02-14 15:23:07.803206496 +0530
@@ -0,0 +1,366 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#ifndef __BEREGISTER_H__
+#define __BEREGISTER_H__
+
+/*!
+
+@brief
+ This macro zeros out a data structure whose contents happen to be
+ exactly 32-bits. Many controller registers have bit map structures
+ defined to represent them and this routine allows for easy and correct
+ initialization of the register to 0.
+
+@param
+ reg - Pointer to the 32-bit structure to zero out.
+
+@return
+
+@note
+ IRQL: any
+
+*/
+
+/*
+ *
+ * Macros for reading/writing a protection domain or CSR registers
+ * in BladeEngine.
+ */
+#define PD_READ(_fo_, _field_) \
+ BePdRead((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PROTECTION_DOMAIN_DBMAP, _field_), \
+ SA_DBG_CSTR(#_field_))
+
+#define PD_WRITE(_fo_, _field_, _value_) \
+ BePdWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PROTECTION_DOMAIN_DBMAP, _field_), \
+ (_value_).dw, SA_DBG_CSTR(#_field_)) \
+
+#define PD_WRITE_CONST(_fo_, _field_, _value_) \
+ BePdWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PROTECTION_DOMAIN_DBMAP, _field_), \
+ (_value_), SA_DBG_CSTR(#_field_))
+
+#define CSR_READ(_fo_, _field_) \
+ BeCsrRead((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(BLADE_ENGINE_CSRMAP, _field_), \
+ SA_DBG_CSTR(#_field_)) \
+
+#define CSR_WRITE(_fo_, _field_, _value_) \
+ BeCsrWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(BLADE_ENGINE_CSRMAP, _field_), \
+ (_value_).dw, SA_DBG_CSTR(#_field_))
+
+#define CSR_WRITE_CONST(_fo_, _field_, _value_) \
+ BeCsrWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(BLADE_ENGINE_CSRMAP, _field_), \
+ (_value_), SA_DBG_CSTR(#_field_))
+/*
+ *
+ * Macros for reading/writing a protection domain or
+ * CSR registers in BladeEngine.
+ */
+#define PCICFG0_READ(_fo_, _field_) \
+ BePciCfgRead((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG0_CSRMAP, _field_), \
+ SA_DBG_CSTR(#_field_))
+
+#define PCICFG0_WRITE(_fo_, _field_, _value_) \
+ BePciCfgWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG0_CSRMAP, _field_), \
+ (_value_).dw, SA_DBG_CSTR (#_field_))
+
+
+#define PCICFG0_WRITE_CONST(_fo_, _field_, _value_) \
+ BePciCfgWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG0_CSRMAP, _field_), \
+ (_value_), SA_DBG_CSTR(#_field_))
+
+#define PCICFG1_READ(_fo_, _field_) \
+ BePciCfgRead((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG1_CSRMAP, _field_), \
+ SA_DBG_CSTR(#_field_))
+
+#define PCICFG1_WRITE(_fo_, _field_, _value_) \
+ BePciCfgWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG1_CSRMAP, _field_), \
+ (_value_).dw, SA_DBG_CSTR(#_field_))
+
+#define PCICFG1_WRITE_CONST(_fo_, _field_, _value_) \
+ BePciCfgWrite((_fo_)->sa_dev, \
+ SA_FIELD_OFFSET(PCICFG1_CSRMAP, _field_), \
+ (_value_), SA_DBG_CSTR(#_field_))
+
+#define RXULP_PD_WRITE(_function_object_, _ulp_number_, _value_) \
+ switch (_ulp_number_) { \
+ case 0: \
+ PD_WRITE((_function_object_), iscsi_default_pdu_db, \
+ (_value_)); \
+ break; \
+ case 1: \
+ PD_WRITE((_function_object_), rdma_rq_db, (_value_)); \
+ break; \
+ case 2: \
+ PD_WRITE((_function_object_), tpm_rq_db, (_value_)); \
+ break; \
+ default: \
+ BREAKPOINT(); \
+ } \
+
+
+#define TXULP_PD_WRITE(_function_object_, _ulp_number_, _value_) \
+ switch (_ulp_number_) { \
+ case 0: \
+ PD_WRITE((_function_object_), iscsi_wrb_post_db, (_value_)); \
+ break; \
+ case 1: \
+ PD_WRITE((_function_object_), rdma_sq_db, (_value_)); \
+ break; \
+ case 2: \
+ PD_WRITE((_function_object_), etx_sq_db, (_value_)); \
+ break; \
+ default: \
+ BREAKPOINT(); \
+ } \
+
+
+/*!
+
+@brief
+ This routine reads from a register located within the protection domain
+ doorbell space for a given function object.
+
+@param
+ FuncObj - Pointer to the function object to read from.
+
+@param
+ Offset - The Offset(in bytes) to read from within the
+ function's PD space.
+
+@return
+ The value read.
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ u32 BePdRead(IN PSA_DEV sa_dev, IN u32 offset, IN const c8 *dbg_name)
+{
+ u32 v;
+ ASSERT(offset < sizeof(PROTECTION_DOMAIN_DBMAP));
+ v = sa_dev_read_u32(sa_dev, sa_get_pd_bar(sa_dev), offset);
+ TRACE(DL_HW, "PD Read. offset:0x%04x value:0x%08x (%s)", offset,
+ v, dbg_name);
+ return v;
+}
+
+/*!
+
+@brief
+ This routine writes to a register located within the protection domain
+ doorbell space for a given function object.
+
+@param
+ FuncObj - Pointer to the function object to read from.
+
+@param
+ Offset - The Offset (in bytes) to write to within the
+ function's PD space.
+
+@param
+ Value - The value to write to the register.
+
+@return
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ void
+BePdWrite(IN PSA_DEV sa_dev,
+ IN u32 offset, IN u32 value, IN const c8 *dbg_name)
+{
+ ASSERT(offset < sizeof(PROTECTION_DOMAIN_DBMAP));
+
+ TRACE(DL_HW, "PD Write. offset:0x%04x value:0x%08x (%s)", offset,
+ value, dbg_name);
+ sa_dev_write_u32(sa_dev, sa_get_pd_bar(sa_dev), offset, value);
+}
+
+/*!
+
+@brief
+ This routine reads from a register located within the CSR space for a
+ given function object.
+
+@param
+ sa_dev - Context for this set of register space
+
+@param
+ Offset - The Offset (in bytes) to read from within
+ the function's CSR space.
+
+@return
+ The value read.
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ u32 BeCsrRead(IN PSA_DEV sa_dev, IN u32 offset, IN const c8 *dbg_name)
+{
+ u32 value;
+ u32 bar;
+
+ ASSERT(offset < sizeof(BLADE_ENGINE_CSRMAP));
+
+ bar = sa_get_csr_bar(sa_dev);
+ value = sa_dev_read_u32(sa_dev, bar, offset);
+
+ TRACE(DL_HW, "CSR Read. offset:0x%04x value:0x%08x (%s)", offset,
+ value, dbg_name);
+
+ return value;
+}
+
+/*!
+
+@brief
+ This routine writes to a register located within the CSR
+ space for a given function object.
+
+@param
+ sa_dev - Context for this set of register space
+
+@param
+ Offset - The Offset (in bytes) to write to within
+ the function's CSR space.
+
+@param
+ Value - The value to write to the register.
+
+@return
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ void
+BeCsrWrite(IN PSA_DEV sa_dev,
+ IN u32 offset, IN u32 value, IN const c8 *dbg_name)
+{
+ ASSERT(offset < sizeof(BLADE_ENGINE_CSRMAP));
+
+ TRACE(DL_HW, "CSR Write. offset:0x%04x value:0x%08x (%s)", offset,
+ value, dbg_name);
+
+ sa_dev_write_u32(sa_dev, sa_get_csr_bar(sa_dev), offset, value);
+}
+
+/*!
+
+@brief
+ This routine reads from a register located within the pci cfg
+ space for a given function object.
+
+@param
+ sa_dev - Context for this set of register space
+
+@param
+ Offset - The Offset (in bytes) to read from within
+ the function's pci cfg space.
+
+@return
+ The value read.
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ u32
+BePciCfgRead(IN PSA_DEV sa_dev, IN u32 offset, IN const c8 *dbg_name)
+{
+ u32 value;
+
+ ASSERT(offset < sizeof(BLADE_ENGINE_CSRMAP));
+
+ value = sa_dev_read_u32(sa_dev, sa_get_pci_bar(sa_dev), offset);
+
+ TRACE(DL_HW, "PCICFG Read. offset:0x%04x value:0x%08x (%s)",
+ offset, value, dbg_name);
+
+ return value;
+}
+
+/*!
+
+@brief
+ This routine writes to a register located within the pci cfg
+ space for a given function object.
+
+@param
+ sa_dev - Context for this set of register space
+
+@param
+ Offset - The Offset (in bytes) to write to within
+ the function's pci cfg space.
+
+@param
+ Value - The value to write to the register.
+
+@return
+
+@note
+ IRQL: any
+
+*/
+STATIC INLINE
+ void
+BePciCfgWrite(IN PSA_DEV sa_dev,
+ IN u32 offset, IN u32 value, IN const c8 *dbg_name)
+{
+
+ ASSERT(offset < sizeof(BLADE_ENGINE_CSRMAP));
+
+ TRACE(DL_HW, "PCICFG Write. offset:0x%04x value:0x%08x (%s)",
+ offset, value, dbg_name);
+
+ sa_dev_write_u32(sa_dev, sa_get_pci_bar(sa_dev), offset, value);
+
+}
+
+#endif /* __BEREGISTER_H__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/main_ll.c benet/linux-2.6.24.2/drivers/message/beclib/main_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/main_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/main_ll.c 2008-02-14 15:23:07.803206496 +0530
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*!
+@brief
+ System-invoked entry point for system DLL.
+ This routine gets called once per system instantiation, is
+ responsible for registering the the driver's entry points.
+ Initialization and configuration occur elsewhere.
+@return
+ SA_SUCCESS if ok.
+@note
+ IRQL: PASSIVE_LEVEL
+ We cannot touch registers in this routine
+*/
+BESTATUS be_initialize_library(void)
+{
+ SA_TRACE(DL_NOTE, "Built on " __DATE__ " " __TIME__);
+
+ sa_trace_set_debug_level_string(DL_HW, "hw");
+
+ return BE_SUCCESS;
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/chipobj_ll.c benet/linux-2.6.24.2/drivers/message/beclib/chipobj_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/chipobj_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/chipobj_ll.c 2008-02-14 15:23:07.804206344 +0530
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+BESTATUS be_chip_create(OUT PBE_CHIP_OBJECT chip)
+{
+ BESTATUS status = BE_SUCCESS;
+ SA_TRACE_ENTRY();
+
+ ASSERT(chip);
+ SA_ZERO_MEM(chip);
+
+ TRACE(DL_INFO, "Create chip object. object:0x%p", chip);
+
+ chip->magic = BE_CHIP_MAGIC;
+ chip->ref_count = 0;
+
+ sa_initialize_list_head(&chip->function_list_head);
+
+ be_lock_init(&chip->lock);
+ /*be_blocking_lock_init (&chip->blocking_lock); */
+
+ return status;
+}
+
+void be_chip_destroy(PBE_CHIP_OBJECT chip)
+{
+ SA_TRACE_ENTRY();
+ CHIP_ASSERT(chip);
+ ASSERT(chip->ref_count == 0);
+
+ SA_ZERO_MEM(chip);
+ TRACE(DL_INFO, "destroying chip %p", chip);
+}
+
+BESTATUS
+be_chip_insert_function_object(IN PBE_CHIP_OBJECT chip_object,
+ IN PBE_FUNCTION_OBJECT function_object)
+{
+ SA_TRACE_ENTRY();
+
+ CHIP_ASSERT(chip_object);
+ FUNCTION_ASSERT(function_object);
+
+ TRACE(DL_INFO, "Insert function into chip object.");
+
+ ASSERT(function_object->parent_chip == NULL ||
+ function_object->parent_chip == chip_object);
+ function_object->parent_chip = chip_object;
+
+ be_chip_lock(chip_object);
+
+ chip_object->ref_count++;
+ sa_insert_tail_list(&chip_object->function_list_head,
+ &function_object->function_list);
+
+ be_chip_unlock(chip_object);
+
+ return BE_SUCCESS;
+}
+
+void
+be_chip_remove_function_object(IN PBE_CHIP_OBJECT chip_object,
+ IN PBE_FUNCTION_OBJECT function_object)
+{
+ SA_TRACE_ENTRY();
+
+ CHIP_ASSERT(chip_object);
+ FUNCTION_ASSERT(function_object);
+
+ function_object->parent_chip = NULL;
+
+ be_chip_lock(chip_object);
+
+ ASSERT(chip_object->ref_count > 0);
+ ASSERT(!sa_is_list_empty(&chip_object->function_list_head));
+
+ chip_object->ref_count--;
+ sa_remove_entry_list(&function_object->function_list);
+
+ be_chip_unlock(chip_object);
+}
+
+/*!
+
+@brief
+ This routine serializes access to resources maintained
+ through a chip object.
+
+@param
+ ChipObject - The chip object to acquire the lock for.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void be_chip_lock(IN PBE_CHIP_OBJECT chip_object)
+{
+ be_lock_acquire(&chip_object->lock);
+}
+
+/*!
+@brief
+ This routine removes serialization done by ChipObjectLock.
+@param
+ ChipObject - The chip object to drop the lock for.
+@return
+@note
+ IRQL < DISPATCH_LEVEL
+*/
+void be_chip_unlock(IN PBE_CHIP_OBJECT chip_object)
+{
+ be_lock_release(&chip_object->lock);
+}
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
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^ permalink raw reply
* [PATHCH 6/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:33 UTC (permalink / raw)
To: netdev
beclib functions that implement function object.
---------------------------------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/funcobj_ll.c benet/linux-2.6.24.2/drivers/message/beclib/funcobj_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/funcobj_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/funcobj_ll.c 2008-02-14 15:23:07.806206040 +0530
@@ -0,0 +1,2339 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+#ifdef FUNCTION_ISCSI
+/*
+ *============================================================================
+ * F I L E S C O P E
+ *============================================================================
+ */
+
+/*!
+@brief
+ This routine allocates iscsi ooo buffers & then registers them
+ with the controller.
+@param function_object - the iscsi function object to create these for
+@param page_count - number of pages to allocate for i_sc_si ooo buffers
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+*/
+BESTATUS
+be_function_iscsi_ooo_buffers_post(PBE_FUNCTION_OBJECT function_object,
+ u32 page_count, PSA_SGL sgl)
+{
+ BESTATUS status = BE_SUCCESS;
+ IOCTL_COMMON_ISCSI_CFG_POST_OOO_BUFFERS *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ u32 num_pages = 0;
+ u32 page_offset = 0;
+ u32 i;
+
+ be_lock_wrb_post(function_object);
+
+ ASSERT(sa_sgl_get_offset(sgl) == 0); /* need page aligned buffers */
+ ASSERT(page_count <= sa_sgl_get_page_count(sgl));
+
+ /* sw tracking */
+ function_object->config.num_ooo += page_count;
+
+ TRACE(DL_INFO, "post ooo buffers. num:%d", page_count);
+
+ /*
+ * Post numerous ioctls to keep each one small enuf to be embedded in
+ * the WRB.
+ */
+ do {
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /*
+ * Prepares an embedded ioctl, including
+ * request/response sizes.
+ */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object,
+ wrb, COMMON_ISCSI_CFG_POST_OOO_BUFFERS);
+
+ num_pages = MIN(page_count, SA_NUMBER_OF_FIELD(
+ IOCTL_COMMON_ISCSI_CFG_POST_OOO_BUFFERS,
+ params.request.pages));
+ ioctl->params.request.num_pages = num_pages;
+
+ /* Create a page list for the IOCTL. */
+ for (i = 0; i < ioctl->params.request.num_pages; i++) {
+ u64 pa = sa_sgl_get_page(sgl, page_offset + i);
+ ioctl->params.request.pages[i].lo = sa_lo(pa);
+ ioctl->params.request.pages[i].hi = sa_hi(pa);
+ }
+
+ page_offset += num_pages;
+ page_count -= num_pages;
+
+ ioctl->params.request.final = (page_count == 0 ? 1 : 0);
+
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR,
+ "MCC to add iscsi ooo buffers failed.");
+ goto error;
+ }
+
+ } while (page_count > 0);
+
+error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+@brief
+ This routine allocates iSCSI ooo buffers & then registers them
+ with the controller.
+@param
+ FunctionObject - The iSCSI function object to create these for
+@param
+ PageCount - Number of pages to allocate for iSCSI ooo buffers
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+*/
+BESTATUS
+be_function_iscsi_ooo_buffers_remove(PBE_FUNCTION_OBJECT function_object)
+{
+ BESTATUS status = BE_SUCCESS;
+ IOCTL_COMMON_ISCSI_CFG_REMOVE_OOO_BUFFERS *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+
+ be_lock_wrb_post(function_object);
+
+ /* sw tracking */
+ function_object->config.num_ooo = 0;
+ TRACE(DL_INFO, "remove ooo buffers.");
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_ISCSI_CFG_REMOVE_OOO_BUFFERS);
+
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "MCC to remove iscsi ooo buffers failed.");
+ goto error;
+ }
+
+error:
+
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+#endif
+
+/*!
+
+@brief
+ This allocates an initializes a function object based on the information
+ provided by upper layer drivers.
+
+@param
+ BarLocations - Location & information on PCI BARs contained
+ by this PCI function
+@param
+ Upcall - Dispatch table of calls into the upper layer drivers
+@param
+ ppFunctionObject - New function object
+
+@return
+ Returns BE_SUCCESS on success and an appropriate BESTATUS on failure.
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+ A function object represents a single BladeEngine (logical) PCI function.
+ That is a function object either represents
+ the networking side of BladeEngine or the iSCSI side of BladeEngine. Each
+ function object has a chip object that is shared by up to 1 other function
+ object.
+
+ This routine will also detect and create an appropriate PD object for the
+ PCI function as needed.
+
+*/
+BESTATUS
+be_function_create(IN SA_DEV *sa_dev,
+ IN u32 function_type,
+ IN PSA_SGL mailbox,
+ OUT PBE_FUNCTION_OBJECT function_object)
+{
+ BESTATUS status;
+
+ SA_TRACE_ENTRY();
+
+ ASSERT(sa_dev);
+ ASSERT(function_object); /* not a magic assert */
+ ASSERT(function_type <= 2);
+
+ TRACE(DL_INFO,
+ "Create function object. type:%s sa_dev:0x%p object:0x%p",
+ (function_type == BE_FUNCTION_TYPE_ISCSI ? "iSCSI" :
+ (function_type == BE_FUNCTION_TYPE_NETWORK ? "Network" :
+ "Arm")), sa_dev, function_object);
+
+ sa_zero_mem(function_object, sizeof(*function_object));
+
+ function_object->magic = BE_FUNCTION_MAGIC;
+ function_object->ref_count = 0;
+ function_object->type = function_type;
+ function_object->sa_dev = sa_dev;
+
+ be_lock_init(&function_object->lock);
+
+ sa_init_spinlock(&function_object->cq_lock);
+ sa_init_spinlock(&function_object->post_lock);
+ sa_init_spinlock(&function_object->mcc_context_lock);
+
+ sa_initialize_list_head(&function_object->links.pd_list_head);
+ sa_initialize_list_head(&function_object->links.cq_list_head);
+ sa_initialize_list_head(&function_object->links.eq_list_head);
+ sa_initialize_list_head(&function_object->links.cxn_list_head);
+ sa_initialize_list_head(&function_object->links.eth_sq_list_head);
+ sa_initialize_list_head(&function_object->links.eth_rq_list_head);
+
+ if (be_function_is_iscsi(function_object)) {
+ sa_initialize_list_head(&function_object->links.iscsi.
+ wrbq_list_head);
+ sa_initialize_list_head(&function_object->links.iscsi.
+ defq_list_head);
+
+ function_object->pci_function_number = 0;
+ } else {
+
+ sa_initialize_list_head(&function_object->links.networking.
+ dq_list_head);
+ sa_initialize_list_head(&function_object->links.networking.
+ sq_list_head);
+ sa_initialize_list_head(&function_object->links.networking.
+ rq_list_head);
+
+ function_object->pci_function_number = 1;
+ }
+
+ function_object->config.rss_type = RSS_ENABLE_NONE;
+
+ function_object->emulate = FALSE;
+ TRACE(DL_NOTE, "Non-emulation mode");
+ status = be_drive_POST(function_object);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "BladeEngine POST failed.");
+ goto error;
+ }
+
+ /* Initialize the mailbox */
+ status = be_mpu_init_mailbox(function_object, mailbox);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "Failed to initialize mailbox.");
+ goto error;
+ }
+ /*
+ * Cache the firmware config for ASSERTs in beclib and later
+ * driver queries.
+ */
+ status = be_function_internal_query_firmware_config(function_object,
+ &function_object->fw_config);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "Failed to query firmware config.");
+ goto error;
+ }
+
+error:
+
+ if (status != BE_SUCCESS) {
+ /* No cleanup necessary */
+ TRACE(DL_ERR, "Failed to create function.");
+ SA_ZERO_MEM(function_object);
+ }
+
+ return status;
+}
+
+/*!
+@brief
+ This routine drops the reference count on a given function object. Once
+ the reference count falls to zero, the function object is destroyed and all
+ resources held are freed.
+
+@param
+ FunctionObject - The function object to drop the reference to.
+*/
+BESTATUS be_function_destroy(IN PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+
+ TRACE(DL_INFO, "Destroy function_object. Object:0x%p",
+ function_object);
+
+ if (be_function_is_iscsi(function_object)) {
+ ASSERT(sa_is_list_empty
+ (&function_object->links.cxn_list_head));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.iscsi.wrbq_list_head));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.iscsi.defq_list_head));
+ ASSERT(function_object->config.num_ooo == 0);
+ ASSERT(function_object->config.num_sgl == 0);
+ } else {
+ ASSERT(be_function_is_networking(function_object));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.cxn_list_head));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.networking.sq_list_head));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.networking.rq_list_head));
+ ASSERT(sa_is_list_empty
+ (&function_object->links.networking.dq_list_head));
+ ASSERT(function_object->config.num_multicast == 0);
+ ASSERT(function_object->config.rss_type ==
+ RSS_ENABLE_NONE);
+ }
+
+ ASSERT(function_object->config.num_template == 0);
+ ASSERT(function_object->config.num_jell == 0);
+ ASSERT(function_object->config.num_zero == 0);
+ ASSERT(sa_is_list_empty(&function_object->links.eth_sq_list_head));
+ ASSERT(sa_is_list_empty(&function_object->links.eth_rq_list_head));
+ ASSERT(function_object->config.num_vlan == 0);
+ ASSERT(function_object->links.mcc == NULL);
+ ASSERT(sa_is_list_empty(&function_object->links.cq_list_head));
+ ASSERT(sa_is_list_empty(&function_object->links.eq_list_head));
+ ASSERT(function_object->config.num_page_table == 0);
+
+ /* Superfluous additional ref count. */
+ ASSERT(function_object->ref_count == 0);
+
+ return BE_SUCCESS;
+}
+
+/* Create chip object. */
+BESTATUS be_chip_object_create(PBE_CHIP_OBJECT chip)
+{
+ BESTATUS status = 0;
+ boolean chip_created = FALSE;
+
+ status = be_chip_create(chip);
+ if (status != BE_SUCCESS) {
+ goto Error;
+ }
+
+ chip_created = TRUE;
+
+Error:
+
+ if (status != BE_SUCCESS) {
+
+ /* Cleanup everything in case of failure. */
+
+ if (chip_created) {
+ be_chip_destroy(chip);
+ }
+
+ }
+
+ return status;
+
+}
+
+/* Create function object. */
+BESTATUS be_function_object_create(
+ SA_DEV *sa_dev,/* previously created device */
+ u32 function_type, /* e.g FUNCTION_TYPE_ISCSI */
+ PSA_SGL mailbox_sgl, PBE_FUNCTION_OBJECT function_object,
+ PBE_CHIP_OBJECT chip) /* object to initialize */
+{
+ BESTATUS status = 0;
+ boolean function_created = FALSE;
+
+ status = be_function_create(sa_dev, function_type, mailbox_sgl,
+ function_object);
+ if (status != BE_SUCCESS) {
+ goto Error;
+ }
+
+ function_created = TRUE;
+
+ status = be_chip_insert_function_object(chip, function_object);
+
+Error:
+
+ if (status != BE_SUCCESS) {
+
+ /* Cleanup everything in case of failure. */
+
+ if (function_created) {
+ be_function_destroy(function_object);
+ }
+ }
+
+ return status;
+
+}
+
+/*
+ * Create both function and chip object with one call. The lower level
+ * API will rarely use more than one function object.
+ */
+BESTATUS be_function_and_chip_create(
+ SA_DEV *sa_dev, /* previously created device */
+ u32 function_type, /* e.g FUNCTION_TYPE_ISCSI */
+ PSA_SGL mailbox_sgl, PSA_SGL emulation_sgl,
+ PBE_FUNCTION_OBJECT function_object, PBE_CHIP_OBJECT chip)
+{
+ BESTATUS status = 0;
+ boolean function_created = FALSE, chip_created = FALSE;
+
+ status =
+ be_function_create(sa_dev, function_type, mailbox_sgl,
+ function_object);
+ if (status != BE_SUCCESS) {
+ goto Error;
+ }
+
+ function_created = TRUE;
+
+ status = be_chip_create(chip);
+ if (status != BE_SUCCESS) {
+ goto Error;
+ }
+
+ chip_created = TRUE;
+
+ status = be_chip_insert_function_object(chip, function_object);
+
+Error:
+
+ if (status != BE_SUCCESS) {
+
+ /* Cleanup everything in case of failure. */
+
+ if (chip_created) {
+ be_chip_destroy(chip);
+ }
+
+ if (function_created) {
+ be_function_destroy(function_object);
+ }
+ }
+
+ return status;
+
+}
+
+BESTATUS
+be_function_and_chip_destroy(PBE_FUNCTION_OBJECT function_object,
+ PBE_CHIP_OBJECT chip)
+{
+ TRACE(DL_INFO, "Destroy function & chip.");
+
+ be_chip_remove_function_object(chip, function_object);
+
+ be_chip_destroy(chip);
+
+ be_function_destroy(function_object);
+
+ return BE_SUCCESS;
+}
+
+BESTATUS
+be_function_object_destroy(PBE_FUNCTION_OBJECT function_object,
+ PBE_CHIP_OBJECT chip)
+{
+ TRACE(DL_INFO, "Destroy function & chip.");
+
+ (void)be_mpu_uninit_mailbox(function_object);
+
+ be_chip_remove_function_object(chip, function_object);
+
+ be_function_destroy(function_object);
+
+ return BE_SUCCESS;
+}
+
+BESTATUS be_chip_object_destroy(PBE_CHIP_OBJECT chip)
+{
+ TRACE(DL_INFO, "Destroy function & chip.");
+
+ be_chip_destroy(chip);
+
+ return BE_SUCCESS;
+}
+
+BESTATUS be_function_cleanup(PBE_FUNCTION_OBJECT function_object)
+{
+ PSA_LIST_ENTRY list_entry;
+ BESTATUS status = 0;
+ BE_CQ_OBJECT *cq = NULL;
+ BE_EQ_OBJECT *eq = NULL;
+#ifdef FUNCTION_NIC
+ BE_ETHSQ_OBJECT *eth_sq = NULL;
+ BE_ETHRQ_OBJECT *eth_rq = NULL;
+#endif
+ u32 isr;
+ PCICFG_HOST_TIMER_INT_CTRL_CSR ctrl;
+
+ FUNCTION_ASSERT(function_object);
+
+ TRACE(DL_INFO, "function cleanup. function:%d",
+ be_function_get_function_number(function_object));
+
+#ifdef FUNCTION_ISCSI
+
+ if (be_function_is_iscsi(function_object)) {
+ /*BE_ISCSI_CONNECTION_OBJECT *iscsi_cxn = NULL; */
+ BE_ISCSI_WRB_QUEUE_OBJECT *iscsi_wrbq = NULL;
+ BE_DEFAULT_PDU_QUEUE_OBJECT *iscsi_defq = NULL;
+
+ /* Assert that all connections are terminated. */
+ ASSERT(sa_is_list_empty
+ (&function_object->links.cxn_list_head));
+
+ /* Destroy all WRB queues. */
+ while (!sa_is_list_empty
+ (&function_object->links.iscsi.wrbq_list_head)) {
+ list_entry =
+ sa_list_head(&function_object->links.iscsi.
+ wrbq_list_head);
+ iscsi_wrbq =
+ SA_CONTAINING_RECORD(list_entry,
+ BE_ISCSI_WRB_QUEUE_OBJECT,
+ wrbq_list);
+
+ status = be_iscsi_wrb_queue_destroy(iscsi_wrbq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /* Destroy the default PDU queues */
+ while (!sa_is_list_empty
+ (&function_object->links.iscsi.defq_list_head)) {
+ list_entry =
+ sa_list_head(&function_object->links.iscsi.
+ defq_list_head);
+ iscsi_defq =
+ SA_CONTAINING_RECORD(list_entry,
+ BE_DEFAULT_PDU_QUEUE_OBJECT,
+ func_list);
+
+ status = be_iscsi_defq_destroy(iscsi_defq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /* Out-of-order buffers */
+ if (function_object->config.num_ooo > 0) {
+ status =
+ be_function_iscsi_ooo_buffers_remove
+ (function_object);
+ ASSERT(status == BE_SUCCESS);
+ }
+ /* SGLs */
+ if (function_object->config.num_sgl > 0) {
+ status =
+ be_iscsi_remove_sgl_pages(function_object);
+ ASSERT(status == BE_SUCCESS);
+ }
+ }
+#endif
+
+#ifdef FUNCTION_NIC
+
+ if (!be_function_is_iscsi(function_object)) {
+
+ /* Multicast */
+ if (function_object->config.num_multicast > 0) {
+ status =
+ be_rxf_multicast_config(function_object, FALSE,
+ 0, NULL, NULL, NULL,
+ NULL);
+ ASSERT(status == BE_SUCCESS);
+ }
+ /* RSS Disable */
+ if (function_object->config.rss_type != RSS_ENABLE_NONE) {
+ status =
+ be_rxf_rss_config(function_object,
+ RSS_ENABLE_NONE, 0, NULL, 0,
+ 0, NULL, 0, NULL, NULL, NULL,
+ NULL);
+ ASSERT(status == BE_SUCCESS);
+ }
+ }
+#endif
+
+#ifdef FUNCTION_NIC
+ /* ETX */
+ while (!sa_is_list_empty(&function_object->links.eth_sq_list_head)) {
+ list_entry =
+ sa_list_head(&function_object->links.eth_sq_list_head);
+ eth_sq =
+ SA_CONTAINING_RECORD(list_entry, BE_ETHSQ_OBJECT,
+ list);
+
+ status = be_eth_sq_destroy(eth_sq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /* ERX */
+ while (!sa_is_list_empty(&function_object->links.eth_rq_list_head)) {
+
+ list_entry =
+ sa_list_head(&function_object->links.eth_rq_list_head);
+ eth_rq =
+ SA_CONTAINING_RECORD(list_entry, BE_ETHRQ_OBJECT,
+ list);
+
+ status = be_eth_rq_destroy(eth_rq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /* VLAN */
+ if (function_object->config.num_vlan > 0) {
+ status =
+ be_rxf_vlan_config(function_object, FALSE, 0, NULL,
+ NULL, NULL, NULL);
+ ASSERT(status == BE_SUCCESS);
+ }
+#endif
+
+ /*
+ * MCC Queue -- Switches to mailbox mode. May want to destroy
+ * all but the MCC CQ before this call if polling CQ is much better
+ * performance than polling mailbox register.
+ */
+ if (function_object->links.mcc) {
+ status = be_mcc_ring_destroy(function_object->links.mcc);
+ }
+ /* CQs */
+ while (!sa_is_list_empty(&function_object->links.cq_list_head)) {
+ list_entry =
+ sa_list_head(&function_object->links.cq_list_head);
+ cq = SA_CONTAINING_RECORD(list_entry, BE_CQ_OBJECT,
+ cq_list);
+
+ status = be_cq_destroy(cq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /* EQs */
+ while (!sa_is_list_empty(&function_object->links.eq_list_head)) {
+ list_entry =
+ sa_list_head(&function_object->links.eq_list_head);
+ eq = SA_CONTAINING_RECORD(list_entry, BE_EQ_OBJECT,
+ eq_list);
+
+ status = be_eq_destroy(eq);
+ ASSERT(status == BE_SUCCESS);
+ }
+
+ /*
+ * If interrupts are disabled, clear any CEV interrupt assertions that
+ * fired after we stopped processing EQs.
+ */
+ ctrl.dw = PCICFG1_READ(function_object, host_timer_int_ctrl);
+ if (!ctrl.hostintr) {
+ if (be_function_is_networking(function_object)) {
+ isr = CSR_READ(function_object, cev.isr1);
+ } else {
+ isr = CSR_READ(function_object, cev.isr0);
+ }
+ } else {
+ /* This should never happen... */
+ TRACE(DL_ERR,
+ "Calling function_cleanup with interrupts enabled.");
+ }
+
+ /* Function object destroy */
+ status =
+ be_function_object_destroy(function_object,
+ function_object->parent_chip);
+ ASSERT(status == BE_SUCCESS);
+
+ return status;
+}
+
+/*!
+
+@brief
+ This routine adds a event queue object to a function object to allow
+ for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ EqObject - Event queue object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_eq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_EQ_OBJECT eq_object)
+{
+ FUNCTION_ASSERT(function_object);
+ EQ_ASSERT(eq_object);
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.eq_list_head,
+ &eq_object->eq_list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes a event queue object from a function object and
+ drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ EqObject - Event queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_eq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_EQ_OBJECT eq_object)
+{
+ FUNCTION_ASSERT(function_object);
+ EQ_ASSERT(eq_object);
+
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(&eq_object->eq_list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+
+}
+
+/*!
+
+@brief
+ This routine adds a completion queue object to a function object to allow
+ for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ CqObject - Completion queue object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_cq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_CQ_OBJECT cq_object)
+{
+ FUNCTION_ASSERT(function_object);
+ CQ_ASSERT(cq_object);
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.cq_list_head,
+ &cq_object->cq_list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes a completion queue object from a function object and
+ drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ CqObject - Completion queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_cq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_CQ_OBJECT cq_object)
+{
+ FUNCTION_ASSERT(function_object);
+ CQ_ASSERT(cq_object);
+
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(&cq_object->cq_list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine adds an Ethernet Send queue object to a function
+ object to allow for correct tracking and reference counting.
+
+@param
+ func_obj - function object to add the object to.
+
+@param
+ eth_sq - ethernet send queue object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_eth_sq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ETHSQ_OBJECT eth_sq)
+{
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.eth_sq_list_head,
+ ð_sq->list);
+
+ _be_function_unlock(function_object);
+
+}
+
+/*!
+
+@brief
+ This routine removes an Ethernet Send Queue object from a function object
+ and drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ EthSq - Ethernet Send Queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_eth_sq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ETHSQ_OBJECT eth_sq)
+{
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(ð_sq->list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine adds an ethernet receive queue object to a
+ function object to allow for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ EthRq - Ethernet Receive Queue object to add.
+
+@param
+ RssIndex - Rss Index that this RQ will map to. Unless this RQ is for
+ a priviledged execution environment, the RssIndex must be
+ set to RSS_ID_INDEX_DQ.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_eth_rq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ETHRQ_OBJECT eth_rq)
+{
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.eth_rq_list_head,
+ ð_rq->list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes an Ethernet receive queue object from a function object
+ and drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ EthRq - Ethernet receive queue object to remove.
+
+@param
+ RssIndex - Rss Index for the EthRq to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_eth_rq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ETHRQ_OBJECT eth_rq)
+{
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(ð_rq->list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+
+}
+
+/*!
+
+@brief
+ This routine adds a Mcc Send queue object to a function object to allow
+ for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ MccSq - Mcc Send Queue object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_mcc(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_MCC_OBJECT mcc)
+{
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(function_object->links.mcc == NULL);
+ MCC_ASSERT(mcc);
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ function_object->links.mcc = mcc;
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes an MCC Send Queue object from a function object and
+ drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ MccSq - Mcc Send Queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_mcc(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_MCC_OBJECT mcc)
+{
+ FUNCTION_ASSERT(function_object);
+
+ MCC_ASSERT(function_object->links.mcc);
+
+ MCC_ASSERT(mcc);
+
+ SA_NOT_USED(mcc);
+
+ _be_function_lock(function_object);
+
+ function_object->links.mcc = NULL;
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine adds an iSCSI default PDU queue object to a function object to
+ allow for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ DefaultPduObject - Default PDU object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_default_pdu_queue(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_DEFAULT_PDU_QUEUE_OBJECT
+ default_pdu_object)
+{
+ FUNCTION_ASSERT(function_object);
+ ASSERT(be_function_is_iscsi(function_object));
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.iscsi.defq_list_head,
+ &default_pdu_object->func_list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes an iSCSI default PDU Queue object from a function
+ object and drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ DefaultPduObject- iSCSI Default PDU Queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_default_pdu_queue(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN PBE_DEFAULT_PDU_QUEUE_OBJECT
+ default_pdu_object)
+{
+ FUNCTION_ASSERT(function_object);
+ ASSERT(be_function_is_iscsi(function_object));
+
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(&default_pdu_object->func_list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+}
+
+
+/*!
+
+@brief
+ This routine adds a event queue object to a function object to allow
+ for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ EqObject - Event queue object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_wrbq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ISCSI_WRB_QUEUE_OBJECT wrbq)
+{
+ FUNCTION_ASSERT(function_object);
+ ISCSI_WRBQ_ASSERT(wrbq);
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.iscsi.wrbq_list_head,
+ &wrbq->wrbq_list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes a event queue object from a function object and
+ drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ EqObject - Event queue object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_wrbq(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ISCSI_WRB_QUEUE_OBJECT wrbq)
+{
+ FUNCTION_ASSERT(function_object);
+ ISCSI_WRBQ_ASSERT(wrbq);
+
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(&wrbq->wrbq_list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+
+}
+
+PVOID
+be_function_prepare_embedded_ioctl(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN u32 payload_length,
+ IN u32 request_length,
+ IN u32 response_length,
+ IN u32 opcode, IN u32 subsystem)
+{
+ PIOCTL_REQUEST_HEADER header = NULL;
+
+ ASSERT(wrb);
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(payload_length <= SA_SIZEOF_FIELD(MCC_WRB, payload));
+
+ wrb->embedded = 1;
+ wrb->payload_length =
+ MIN(payload_length, SA_SIZEOF_FIELD(MCC_WRB, payload));
+
+ header = (PIOCTL_REQUEST_HEADER) &wrb->payload;
+
+ header->timeout = 0;
+ header->domain = be_function_get_pd_number(function_object);
+ header->request_length = MAX(request_length, response_length);
+ header->opcode = opcode;
+ header->subsystem = subsystem;
+
+ return header;
+}
+
+PVOID
+be_function_prepare_nonembedded_ioctl(IN PBE_FUNCTION_OBJECT
+ function_object, IN PMCC_WRB wrb,
+ IN PVOID ioctl_va, IN u64 ioctl_pa,
+ IN u32 payload_length,
+ IN u32 request_length,
+ IN u32 response_length,
+ IN u32 opcode, IN u32 subsystem)
+{
+ PIOCTL_REQUEST_HEADER header = NULL;
+
+ ASSERT(wrb);
+ ASSERT(ioctl_va);
+ FUNCTION_ASSERT(function_object);
+
+ header = (PIOCTL_REQUEST_HEADER) ioctl_va;
+
+ wrb->embedded = 0;
+ wrb->payload_length = payload_length;
+
+ /*
+ * Assume one fragment. The caller may override the SGL by
+ * rewriting the 0th length and adding more entries. They
+ * will also need to update the sge_count.
+ */
+ wrb->sge_count = 1;
+ wrb->payload.sgl[0].length = payload_length;
+ wrb->payload.sgl[0].pa_lo = sa_lo(ioctl_pa);
+ wrb->payload.sgl[0].pa_hi = sa_hi(ioctl_pa);
+
+ header->timeout = 0;
+ header->domain = be_function_get_pd_number(function_object);
+ header->request_length = MAX(request_length, response_length);
+ header->opcode = opcode;
+ header->subsystem = subsystem;
+
+ return header;
+}
+
+PMCC_WRB be_function_peek_mcc_wrb(IN PBE_FUNCTION_OBJECT function_object)
+{
+ PMCC_WRB wrb = NULL;
+ FUNCTION_ASSERT(function_object);
+
+ if (function_object->links.mcc) {
+
+ wrb = _be_mpu_peek_ring_wrb(function_object->links.mcc, FALSE);
+
+ } else {
+ wrb = (PMCC_WRB) &function_object->mailbox.va->wrb;
+ }
+
+ if (wrb) {
+ sa_memset(wrb, 0, sizeof(MCC_WRB));
+ }
+
+ return wrb;
+}
+
+/*!
+@brief
+ This routine posts an MCC WRB command to a function object's MCC send
+ queue (if avaiable) or posts the WRB to the MCC WRB mail box if a send
+ queue is not setup.
+@param
+ function_object - function object to add the object to.
+@param
+ wrb - wrb to post. This may be a va from the
+ be_function_peek_mcc_wrb function, so the
+ driver need not declare additional memory.
+@param
+ callback - address of a callback routine to invoke once the WRB
+ is completed.
+@param
+ callback_context - opaque context to be passed during the call to
+ the callback.
+@return
+ BE_SUCCESS if successfull, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL
+*/
+BESTATUS
+be_function_post_mcc_wrb(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va)
+{
+ BE_MCC_WRB_RESPONSE_COPY response_copy = { 0 };
+ return be_function_post_mcc_wrb_complete(function_object, wrb, NULL,
+ callback, callback_context, NULL, NULL,
+ optional_ioctl_va, response_copy);
+}
+
+BESTATUS
+be_function_post_mcc_wrb_with_queue_context(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK
+ callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va)
+{
+ BE_MCC_WRB_RESPONSE_COPY response_copy = { 0 };
+ return be_function_post_mcc_wrb_complete(function_object,
+ wrb, queue_context, callback, callback_context, NULL,
+ NULL, optional_ioctl_va, response_copy);
+}
+
+BESTATUS
+be_function_post_mcc_wrb_with_copy(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PVOID optional_ioctl_va,
+ IN BE_MCC_WRB_RESPONSE_COPY
+ response_copy)
+{
+ return be_function_post_mcc_wrb_complete(function_object,
+ wrb, queue_context, callback, callback_context, NULL,
+ NULL, optional_ioctl_va, response_copy);
+}
+
+BESTATUS
+be_function_post_mcc_wrb_with_internal_callback(
+ IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT queue_context,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN MCC_WRB_CQE_CALLBACK internal_callback,
+ IN PVOID internal_callback_context,
+ IN PVOID optional_ioctl_va)
+{
+ BE_MCC_WRB_RESPONSE_COPY response_copy = { 0 };
+ return be_function_post_mcc_wrb_complete(function_object, wrb,
+ queue_context, callback, callback_context,
+ internal_callback, internal_callback_context,
+ optional_ioctl_va, response_copy);
+}
+
+#if defined(SA_DEBUG)
+void be_function_debug_print_wrb(PBE_FUNCTION_OBJECT function_object,
+ PMCC_WRB wrb,
+ PVOID optional_ioctl_va,
+ PBE_MCC_WRB_CONTEXT wrb_context)
+{
+
+ PIOCTL_REQUEST_HEADER header = NULL;
+ if (wrb->embedded) {
+ header = (PIOCTL_REQUEST_HEADER) &wrb->payload;
+ } else {
+ header = (PIOCTL_REQUEST_HEADER) optional_ioctl_va;
+ }
+
+ /* Save the completed count before posting for a debug assert. */
+ wrb_context->consumed_count = function_object->stats.consumed_wrbs;
+
+ if (header) {
+ wrb_context->opcode = header->opcode;
+ wrb_context->subsystem = header->subsystem;
+
+ } else {
+ wrb_context->opcode = 0;
+ wrb_context->subsystem = 0;
+ TRACE(DL_IOCTL,
+ "Post IOCTL. emul:0 embed:0 Unknown sub/op. ctx:%p",
+ wrb_context);
+ }
+}
+#else
+#define be_function_debug_print_wrb(a_, b_, c_, d_)
+#endif
+
+BESTATUS
+be_function_post_mcc_wrb_complete(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_GENERIC_QUEUE_CONTEXT
+ queue_context,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN MCC_WRB_CQE_CALLBACK
+ internal_callback,
+ IN PVOID internal_callback_context,
+ IN PVOID optional_ioctl_va,
+ IN BE_MCC_WRB_RESPONSE_COPY
+ response_copy)
+{
+ BESTATUS status;
+ PBE_MCC_WRB_CONTEXT wrb_context = NULL;
+ FUNCTION_ASSERT(function_object);
+
+ if (queue_context) {
+
+ /* Initialize context. */
+ queue_context->context.internal_callback =
+ internal_callback;
+ queue_context->context.internal_callback_context =
+ internal_callback_context;
+ queue_context->context.callback = callback;
+ queue_context->context.callback_context = callback_context;
+ queue_context->context.copy = response_copy;
+ queue_context->context.optional_ioctl_va =
+ optional_ioctl_va;
+
+ /* Queue this request */
+ status =
+ be_function_queue_mcc_wrb(function_object,
+ queue_context);
+
+ goto Error;
+ }
+ /*
+ * Allocate a WRB context struct to hold the callback pointers,
+ * status, etc. This is required if commands complete out of order.
+ */
+ wrb_context = _be_mcc_allocate_wrb_context(function_object);
+ if (!wrb_context) {
+ TRACE(DL_WARN, "Failed to allocate MCC WRB context.");
+ status = BE_STATUS_SYSTEM_RESOURCES;
+ goto Error;
+ }
+ /* Initialize context. */
+ SA_ZERO_MEM(wrb_context);
+ wrb_context->internal_callback = internal_callback;
+ wrb_context->internal_callback_context = internal_callback_context;
+ wrb_context->callback = callback;
+ wrb_context->callback_context = callback_context;
+ wrb_context->copy = response_copy;
+ wrb_context->wrb = wrb;
+
+ /*
+ * Copy the context pointer into the WRB opaque tag field.
+ * Verify assumption of 64-bit tag with a compile time assert.
+ */
+ SA_C_ASSERT(sizeof(wrb->tag) >= sizeof(u64));
+ *((u64 *) wrb->tag) = SA_PTR_TO_U64(wrb_context);
+
+ /* Print info about this IOCTL for debug builds. */
+ be_function_debug_print_wrb(function_object, wrb,
+ optional_ioctl_va, wrb_context);
+
+ /*
+ * issue the WRB to the MPU as appropriate
+ */
+ if (function_object->links.mcc) {
+ /*
+ * we're in WRB mode, pass to the mcc layer
+ */
+ status =
+ _be_mpu_post_wrb_ring(function_object->links.
+ mcc, wrb, wrb_context);
+ } else {
+ /*
+ * we're in mailbox mode
+ */
+ status = _be_mpu_post_wrb_mailbox(function_object, wrb,
+ wrb_context);
+
+ /* mailbox mode always completes synchronously */
+ ASSERT(status != BE_STATUS_PENDING);
+ }
+
+Error:
+
+ return status;
+}
+
+void _be_function_lock(PBE_FUNCTION_OBJECT fo)
+{
+ be_lock_acquire(&fo->lock);
+}
+
+void _be_function_unlock(PBE_FUNCTION_OBJECT fo)
+{
+ be_lock_release(&fo->lock);
+}
+
+u32 be_function_get_function_number(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return function_object->pci_function_number;
+}
+
+u32 be_function_get_function_type(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return function_object->type;
+}
+
+u32 be_function_get_pd_number(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+
+ /* only PD0 supported in Linux drivers */
+ return 0;
+}
+
+boolean be_function_is_vm(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return be_function_get_pd_number(function_object) > 0;
+}
+
+/*!
+
+@brief
+ References the given object. The object is guaranteed to remain active
+ until the reference count drops to zero.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: any
+
+*/
+u32 _be_function_reference(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return sa_atomic_increment(&function_object->ref_count);
+}
+
+/*!
+@brief
+ Dereferences the given object. The object is guaranteed to remain
+ active until the reference count drops to zero.
+@param
+@return
+ returns the current reference count on the object
+@note
+ IRQL: any
+*/
+u32 _be_function_dereference(PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ return sa_atomic_decrement(&function_object->ref_count);
+}
+
+BESTATUS
+be_function_ring_destroy_async(PBE_FUNCTION_OBJECT function_object,
+ u32 id,
+ u32 ring_type,
+ MCC_WRB_CQE_CALLBACK callback,
+ PVOID callback_context,
+ MCC_WRB_CQE_CALLBACK internal_callback,
+ PVOID internal_callback_context)
+{
+
+ IOCTL_COMMON_RING_DESTROY *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ TRACE(DL_INFO, "Destroy ring id:%d type:%d", id, ring_type);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in destroy ring.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_RING_DESTROY);
+
+ ioctl->params.request.id = id;
+ ioctl->params.request.ring_type = ring_type;
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_internal_callback
+ (function_object, wrb, NULL, callback, callback_context,
+ internal_callback, internal_callback_context, ioctl);
+ if (status != BE_SUCCESS && status != BE_PENDING) {
+ TRACE(DL_ERR,
+ "Ring destroy ioctl failed. id:%d ring_type:%d", id,
+ ring_type);
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+BESTATUS
+be_function_ring_destroy(PBE_FUNCTION_OBJECT function_object, u32 id,
+ u32 ring_type)
+{
+ return be_function_ring_destroy_async(function_object, id,
+ ring_type, NULL, NULL, NULL,
+ NULL);
+}
+
+void be_sgl_to_pa_list(PSA_SGL sgl, PHYS_ADDR *pa_list, u32 max_num)
+{
+ u32 offset = sa_sgl_get_offset(sgl);
+ u32 num_pages = sa_sgl_get_page_count(sgl);
+ u32 i = 0;
+ u64 pa;
+
+ ASSERT(pa_list);
+ /* MUST BE page aligned if >1 page in ring */
+ ASSERT((offset == 0) || (num_pages == 1));
+
+ for (i = 0; i < MIN(num_pages, max_num); i++) {
+ pa = sa_sgl_get_page(sgl, i) + offset;
+ offset = 0; /* offset applies to first page only */
+
+ ASSERT(pa);
+
+ pa_list[i].lo = sa_lo(pa);
+ pa_list[i].hi = sa_hi(pa);
+ }
+}
+
+/*!
+
+@brief
+ This routine adds an iSCSI connectoin object to a function object to allow
+ for correct tracking and reference counting.
+
+@param
+ function_object - Function object to add the object to.
+
+@param
+ ConnectionObject - iSCSI Connection object to add.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_add_iscsi_connection(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_ISCSI_CONNECTION_OBJECT
+ connection_object)
+{
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(be_function_is_iscsi(function_object) == TRUE);
+
+ ISCSI_CXN_ASSERT(connection_object);
+
+ _be_function_lock(function_object);
+
+ sa_atomic_increment(&function_object->ref_count);
+ sa_insert_tail_list(&function_object->links.cxn_list_head,
+ &connection_object->connection_list);
+
+ _be_function_unlock(function_object);
+}
+
+/*!
+
+@brief
+ This routine removes an iSCSI Connection object from a function object and
+ drops the reference count for the given function object.
+
+@param
+ function_object - Function object to remove the object from.
+
+@param
+ ConnectionObject - iSCSI connection object to remove.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+void
+_be_function_remove_iscsi_connection(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN PBE_ISCSI_CONNECTION_OBJECT
+ connection_object)
+{
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(be_function_is_iscsi(function_object) == TRUE);
+
+ ISCSI_CXN_ASSERT(connection_object);
+
+ _be_function_lock(function_object);
+
+ sa_remove_entry_list(&connection_object->connection_list);
+ sa_atomic_decrement(&function_object->ref_count);
+
+ _be_function_unlock(function_object);
+
+}
+
+void be_function_lock_mcc(IN PBE_FUNCTION_OBJECT function_object)
+{
+ be_lock_wrb_post(function_object);
+}
+
+void be_function_unlock_mcc(IN PBE_FUNCTION_OBJECT function_object)
+{
+ be_unlock_wrb_post(function_object);
+}
+
+/*
+ *---------------------------------------------------------------------------
+ * Function: be_function_enable_interrupts
+ * Enables interrupts for the given PCI function.
+ * function_object -
+ * return return_type - void
+ *----------------------------------------------------------------------------
+ */
+void be_function_enable_interrupts(IN PBE_FUNCTION_OBJECT function_object)
+{
+ BE_EQ_OBJECT *eq = NULL;
+ CQ_DB cq_db;
+ PCICFG_HOST_TIMER_INT_CTRL_CSR ctrl;
+ u32 isr;
+
+ FUNCTION_ASSERT(function_object);
+
+ ctrl.dw = PCICFG1_READ(function_object, host_timer_int_ctrl);
+ if (!ctrl.hostintr) {
+
+ /*
+ * Read-clear the ISR to make sure that any EQs that
+ * fired after the host interrupt was masked are no longer
+ * asserted. If the EQs still have a producer-consumer
+ * mismatch, they will re-assert after they are armed. This
+ * handles the situation where software polls CQs and EQs
+ * with interrupts disabled.
+ */
+ if (be_function_is_networking(function_object)) {
+ isr = CSR_READ(function_object, cev.isr1);
+ } else {
+ isr = CSR_READ(function_object, cev.isr0);
+ }
+
+ /*
+ * Read-Modify-Write the control register
+ *
+ */
+ ctrl.hostintr = 1;
+ PCICFG1_WRITE_CONST(function_object, host_timer_int_ctrl,
+ ctrl.dw);
+ }
+
+ cq_db.dw = 0; /* clear entire doorbell */
+ cq_db.event = 1;
+ cq_db.rearm = 1;
+ cq_db.num_popped = 0;
+
+ /* Lock the function object while walking the EQ list. */
+ _be_function_lock(function_object);
+
+ /* Rearm each EQ. */
+ SA_FOR_EACH_LIST_ENTRY(eq, function_object->links.eq_list_head,
+ BE_EQ_OBJECT, eq_list) {
+
+ EQ_ASSERT(eq);
+
+ cq_db.qid = eq->eq_id;
+
+ PD_WRITE(function_object, cq_db, cq_db);
+ }
+
+ _be_function_unlock(function_object);
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function: be_function_disable_interrupts
+ * Disables interrupts for the given PCI function.
+ * function_object -
+ * return return_type - void
+ *----------------------------------------------------------------------------
+ */
+void be_function_disable_interrupts(IN PBE_FUNCTION_OBJECT function_object)
+{
+ PCICFG_HOST_TIMER_INT_CTRL_CSR ctrl;
+
+ FUNCTION_ASSERT(function_object);
+
+ /*
+ * Read-Modify-Write of the control register in PCI config space.
+ */
+ ctrl.dw = PCICFG1_READ(function_object, host_timer_int_ctrl);
+ if (ctrl.hostintr) {
+ ctrl.hostintr = 0;
+ PCICFG1_WRITE_CONST(function_object, host_timer_int_ctrl,
+ ctrl.dw);
+ }
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function: be_function_nop
+ * Issues a NOP command to the MCC ring. The command is completed with
+ * a successful status. This can be used to pend operations until a
+ * short time in the future, since the callback function will be
+ * invoked upon command completion. The returned status
+ * will be BE_PENDING if the command was issued successfully.
+ * function_object -
+ * callback - Callback function invoked when the NOP completes.
+ * callback_context - Passed to the callback function.
+ * return pend_status - BE_SUCCESS (0) on success. BE_PENDING
+ * (postive value) if the IOCTL completion is
+ * pending. Negative error code on failure.
+ *-----------------------------------------------------------------------
+ */
+BESTATUS
+be_function_nop(IN PBE_FUNCTION_OBJECT function_object,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_NOP_QUEUE_CONTEXT queue_context)
+{
+ BESTATUS status = BE_SUCCESS;
+ MCC_WRB *wrb = NULL;
+ IOCTL_COMMON_NOP *ioctl = NULL;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_NOP);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+Error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: be_function_get_fw_version
+ * Retrieves the firmware version on the adpater. If the callback is
+ * NULL this call executes synchronously. If the callback is not NULL,
+ * the returned status will be BE_PENDING if the command was issued
+ * successfully.
+ * function_object -
+ * fw_version - Pointer to response buffer if callback is NULL.
+ * callback - Callback function invoked when the IOCTL completes.
+ * callback_context - Passed to the callback function.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_get_fw_version(IN PBE_FUNCTION_OBJECT function_object,
+ OUT IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD
+ * fw_version, IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context)
+{
+ BESTATUS status = BE_SUCCESS;
+ MCC_WRB *wrb = NULL;
+ IOCTL_COMMON_GET_FW_VERSION *ioctl = NULL;
+
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+
+ if (!callback && !fw_version) {
+ TRACE(DL_ERR, "callback and response buffer NULL!");
+ status = BE_NOT_OK;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_GET_FW_VERSION);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_copy(function_object, wrb, NULL,
+ callback, callback_context,
+ ioctl,
+ BE_CREATE_MCC_RESPONSE_COPY(IOCTL_COMMON_GET_FW_VERSION,
+ params.response, fw_version));
+
+Error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+BESTATUS
+be_function_queue_mcc_wrb(PBE_FUNCTION_OBJECT function_object,
+ PBE_GENERIC_QUEUE_CONTEXT queue_context)
+{
+ BESTATUS status;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(queue_context);
+
+ /*
+ * issue the WRB to the MPU as appropriate
+ */
+ if (function_object->links.mcc) {
+
+ /* We're in ring mode. Queue this item. */
+ function_object->links.mcc->backlog_length++;
+ sa_insert_tail_list(&function_object->links.mcc->backlog,
+ &queue_context->context.list);
+
+ function_object->stats.queued_wrbs++;
+ function_object->stats.queue_length =
+ function_object->links.mcc->backlog_length;
+ function_object->stats.max_queue_length =
+ MAX(function_object->stats.queue_length,
+ function_object->stats.max_queue_length);
+
+ status = BE_PENDING;
+
+ } else {
+
+ status = BE_NOT_OK;
+
+ }
+
+ return status;
+}
+
+/*
+ *-------------------------------------------------------------------------
+ * Function: be_function_manage_FAT_log
+ * This routine can be used to manage the BladeEngine Fault Analysis
+ * Tool (FAT) log. This includes querying the FAT log size, retrieving
+ * the FAT log, and clearing the FAT log. The log data can be anaylzed
+ * by BladeEngine support tools to diagnose faults.
+ * Only host domains (domain 0) may issue this request.
+ * function_object -
+ * sgl - The SGL representing the FAT log buffer landing space.
+ * The SGL should be page aligned. It does not require
+ * a virtual address.
+ * num_pages - The number of pages in the SGL. A value of zero (0)
+ * implies no FAT log data transfer will take place.
+ * The num_pages is limited to 27 pages.
+ * page_offset - The page_offset specifies the starting page offset
+ * when retrieving the FAT log. For example, a value
+ * of 0 requests data starting at byte offset 0 of the
+ * FAT log. Likewise, a value of 5 requests data
+ * starting at byte offset 20480 of the FAT log.
+ * A caller may choose to issue multiple queries
+ * when the FAT log buffer size is larger
+ * than the number of pages specified.
+ * clear_log - Set to clear the log.
+ * log_size - The size of the BladeEngine FAT log in bytes.
+ * bytes_transferred - The number of FAT log data bytes transferred.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure
+ *----------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_manage_FAT_log(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 num_pages,
+ IN u32 page_offset,
+ IN boolean clear_log,
+ OUT u32 *log_size, OUT u32 *bytes_transferred)
+{
+ IOCTL_COMMON_GET_FAT *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_GET_FAT);
+
+ /* Set parameters */
+ ioctl->params.request.clear_log = clear_log;
+ ioctl->params.request.page_offset = page_offset;
+ ioctl->params.request.num_pages = num_pages;
+
+ /* Create a page list for the IOCTL. */
+ ASSERT(sa_sgl_get_page_count(sgl) >=
+ ioctl->params.request.num_pages);
+ be_sgl_to_pa_list(sgl, ioctl->params.request.buffer_addr,
+ SA_NUMBER_OF(ioctl->params.request.buffer_addr));
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "manage FAT log ioctl failed.");
+ goto error;
+ }
+
+ if (NULL != log_size) {
+ *log_size = ioctl->params.response.log_size;
+ }
+
+ if (NULL != bytes_transferred) {
+ *bytes_transferred =
+ ioctl->params.response.bytes_transferred;
+ }
+
+ error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function: be_function_query_firmware_config
+ * Queries the firmware configuration currently loaded. This
+ * configuration includes information regarding the EP processor
+ * configuration for various Upper Layer Protocols.
+ * function_object -
+ * config - The configuration parameters currently loaded by firmware.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *--------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_query_firmware_config(IN PBE_FUNCTION_OBJECT function_object,
+ OUT BE_FIRMWARE_CONFIG *config)
+{
+ FUNCTION_ASSERT(function_object);
+ ASSERT(config);
+
+ /* Copy the cached version. */
+ sa_memcpy(config, &function_object->fw_config, sizeof(*config));
+
+ return BE_SUCCESS;
+}
+
+BESTATUS
+be_function_internal_query_firmware_config(IN PBE_FUNCTION_OBJECT
+ function_object,
+ OUT BE_FIRMWARE_CONFIG *config)
+{
+ IOCTL_COMMON_FIRMWARE_CONFIG *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_FIRMWARE_CONFIG);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_copy(function_object, wrb,
+ NULL, NULL, NULL, ioctl,
+ BE_CREATE_MCC_RESPONSE_COPY(
+ IOCTL_COMMON_FIRMWARE_CONFIG,
+ params.response, config));
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *---------------------------------------------------------------------------
+ * Function: be_function_config_red
+ * This function configures global and/or ULP specific Random Early Drop (RED
+ * functionality.
+ * function_object -
+ * parameters - The RED parameters. Only parameters for the
+ * chutes owned by the current PCI function are applied.
+ * callback - Optional callback function.
+ * callback_context - Optional context for callback function.
+ * queue_context - Optional context for queueing the IOCTL.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_config_red(IN PBE_FUNCTION_OBJECT function_object,
+ IN PBE_RED_PARAMETERS parameters,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_CONFIG_RED_QUEUE_CONTEXT queue_context)
+{
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+ IOCTL_COMMON_RED_CONFIG *ioctl = NULL;
+ u32 i;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context;
+ generic_context->context.bytes = sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_RED_CONFIG);
+
+ for (i = 0; i < SA_NUMBER_OF(parameters->chute); i++) {
+ sa_memcpy(&ioctl->params.request.chute[i],
+ ¶meters->chute[i],
+ sizeof(parameters->chute[0]));
+ }
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+ error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ * Function: be_function_config_port_equalization
+ * This function configures or returns the XAUI port equalization
+ * parameters of BladeEngine.
+ * function_object -
+ * parameters - XAUI port equalization parameters.
+ * write - Set (1) to write the parameters, otherwise
+ * clear (0) to read the parameters.
+ * callback - Optional callback function.
+ * callback_context - Optional context for callback function.
+ * queue_context - Optional context for queueing the IOCTL.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_config_port_equalization(IN PBE_FUNCTION_OBJECT
+ function_object,
+ IN OUT
+ PIOCTL_COMMON_PORT_EQUALIZATION_PARAMS
+ parameters, IN boolean write,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN
+ PBE_CONFIG_PORT_EQUALIXATION_QUEUE_CONTEXT
+ queue_context)
+{
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context;
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ }
+
+ if (write) {
+ IOCTL_COMMON_SET_PORT_EQUALIZATION *ioctl;
+
+ /*
+ * Prepare an embedded ioctl, including request/response
+ * sizes.
+ */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_SET_PORT_EQUALIZATION);
+
+ sa_memcpy(&ioctl->params.request,
+ parameters, sizeof(*parameters));
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(
+ function_object,
+ wrb, generic_context, callback,
+ callback_context, ioctl);
+ } else {
+ IOCTL_COMMON_GET_PORT_EQUALIZATION *ioctl;
+
+ /*
+ * Prepare an embedded ioctl, including
+ * request/response sizes.
+ */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object,
+ wrb, COMMON_GET_PORT_EQUALIZATION);
+
+ /* This IOCTL response is copied into the parameters pointer */
+ status = be_function_post_mcc_wrb_with_copy(function_object,
+ wrb, generic_context, callback,
+ callback_context, ioctl,
+ BE_CREATE_MCC_RESPONSE_COPY(
+ IOCTL_COMMON_GET_PORT_EQUALIZATION,
+ params.
+ response,
+ parameters));
+ }
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *------------------------------------------------------------------------
+ * Function: be_function_passthru_ioctl
+ * This routine issues an embedded IOCTL in pass-through mode.
+ * function_object -
+ * payload - The embedded payload for the MCC_WRB structure.
+ * The input buffer is overwritten with response data.
+ * callback - Callback function invoked when the IOCTL completes.
+ * callback_context - Callback context passed to the callback function.
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *----------------------------------------------------------------------------
+ */
+BESTATUS
+be_function_passthru_ioctl(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT MCC_WRB_PAYLOAD *payload,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context)
+{
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PVOID ioctl = NULL;
+ PIOCTL_REQUEST_HEADER ioctl_header =
+ (PIOCTL_REQUEST_HEADER) payload;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl */
+ ioctl = be_function_prepare_embedded_ioctl(function_object,
+ wrb,
+ sizeof(MCC_WRB_PAYLOAD),
+ ioctl_header->
+ request_length,
+ ioctl_header->
+ request_length,
+ ioctl_header->opcode,
+ ioctl_header->
+ subsystem);
+
+ /* Copy in the user's IOCTL payload */
+ sa_memcpy((void *)&wrb->payload,
+ (void *)payload, sizeof(MCC_WRB_PAYLOAD));
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_copy(function_object,
+ wrb, NULL, callback, callback_context,
+ ioctl, be_create_mcc_response_copy(0,
+ sizeof (MCC_WRB_PAYLOAD), payload));
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
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review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
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^ permalink raw reply
* [PATHCH 7/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:43 UTC (permalink / raw)
To: netdev
Ether ring creation function in beclib.
---------------------------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/ethtx_ll.c benet/linux-2.6.24.2/drivers/message/beclib/ethtx_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/ethtx_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/ethtx_ll.c 2008-02-14 15:23:07.806206040 +0530
@@ -0,0 +1,561 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*
+ *---------------------------------------------------------
+ * Function: be_eth_sq_create_ex
+ * Creates an ethernet send ring - extended version with
+ * additional parameters.
+ * function_object -
+ * sgl - no virtual address required
+ * length_in_bytes -
+ * type - The type of ring to create.
+ * ulp - The requested ULP number for the ring.
+ * This should be zero based, i.e. 0,1,2. This must
+ * be valid NIC ULP based on the firmware config.
+ * All doorbells for this ring must be sent to
+ * this ULP. The first network ring allocated for
+ * each ULP are higher performance than subsequent rings.
+ * cq_object - cq object for completions
+ * ex_parameters - Additional parameters (that may increase in
+ * future revisions). These parameters are only used
+ * for certain ring types -- see
+ * BE_ETH_SQ_PARAMETERS for details.
+ * eth_sq -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------
+ */
+BESTATUS
+be_eth_sq_create_ex(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length,
+ IN u32 type,
+ IN u32 ulp,
+ IN PBE_CQ_OBJECT cq_object,
+ IN BE_ETH_SQ_PARAMETERS *ex_parameters,
+ OUT PBE_ETHSQ_OBJECT eth_sq)
+{
+ IOCTL_COMMON_ETH_TX_CREATE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ ASSERT(sgl);
+ ASSERT(eth_sq);
+ ASSERT(ex_parameters);
+
+ FUNCTION_ASSERT(function_object);
+ be_lock_wrb_post(function_object);
+
+ sa_zero_mem(eth_sq, sizeof(*eth_sq));
+
+ eth_sq->magic = BE_ETHSQ_MAGIC;
+ eth_sq->parent_function = function_object;
+ eth_sq->bid = 0xFFFFFFFF;
+ eth_sq->cq_object = cq_object;
+
+ /* Translate beclib interface to arm interface. */
+ switch (type) {
+ case BE_ETH_TX_RING_TYPE_FORWARDING:
+ type = ETH_TX_RING_TYPE_FORWARDING;
+ break;
+ case BE_ETH_TX_RING_TYPE_STANDARD:
+ type = ETH_TX_RING_TYPE_STANDARD;
+ break;
+ case BE_ETH_TX_RING_TYPE_BOUND:
+ ASSERT(ex_parameters->port < 2);
+ type = ETH_TX_RING_TYPE_BOUND;
+ break;
+ default:
+ TRACE(DL_ERR, "Invalid eth tx ring type:%d", type);
+ return BE_NOT_OK;
+ break;
+ }
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in create EQ.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* NIC must be supported by the current config. */
+ ASSERT(function_object->fw_config.nic_ulp_mask);
+
+ /*
+ * The ulp parameter must select a valid NIC ULP
+ * for the current config.
+ */
+ ASSERT((1 << ulp) & function_object->fw_config.nic_ulp_mask);
+
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_ETH_TX_CREATE);
+
+ /* Only used for ETH_TX_RING_TYPE_BOUND */
+ ioctl->header.request.port_number = ex_parameters->port;
+ ioctl->params.request.context.pd_id =
+ be_function_get_pd_number(function_object);
+ ioctl->params.request.context.tx_ring_size =
+ be_ring_length_to_encoding(length, sizeof(ETH_WRB));
+ ioctl->params.request.context.cq_id_send = cq_object->cq_id;
+ ioctl->params.request.context.func =
+ be_function_get_function_number(function_object);
+ ioctl->params.request.type = type;
+ ioctl->params.request.ulp_num = (1 << ulp);
+
+ ioctl->params.request.num_pages = sa_ceiling(length, SA_PAGE_SIZE);
+ ASSERT(sa_sgl_get_page_count(sgl) >=
+ ioctl->params.request.num_pages);
+
+ /* Create a page list for the IOCTL. */
+ be_sgl_to_pa_list(sgl,
+ ioctl->params.request.pages,
+ SA_NUMBER_OF(ioctl->params.request.pages));
+
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "MCC to create etx queue failed.");
+ goto Error;
+ }
+ /* save the butler ID */
+ eth_sq->bid = ioctl->params.response.cid;
+
+ /* add a reference to the corresponding CQ */
+ be_cq_object_reference(cq_object);
+
+ /* add this object to the function object */
+ _be_function_add_eth_sq(function_object, eth_sq);
+
+ TRACE(DL_INFO,
+ "eth sq created. function:%d pd:%d bid:%d bytes:%d cq_id:%d",
+ be_function_get_function_number(function_object),
+ be_function_get_pd_number(function_object), eth_sq->bid,
+ length, be_cq_get_id(cq_object));
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+
+}
+
+/*!
+
+@brief
+ this routine creates an ethernet send queue
+
+@param
+ function_object - handle to a function object
+@param
+ send_queue_va - base VA for a the ethernet send ring
+@param
+ ring_size_power_of_two - number of entries in the
+ ring (power of two). 32K = 0, 1 = rsvd,
+ 2 = 1, 3 = 4 ....
+@param
+ cq_object - internal CQ handle returned.
+@param
+ pp_eth_sq - internal eth sq handle returned.
+
+@return
+ BE_SUCCESS if successfull, , otherwise a useful error code is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+ this function allocates an eth_sq object
+
+*/
+BESTATUS be_eth_sq_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl, IN u32 length, IN u32 type,
+ IN u32 ulp, /* 0,1,2 ulp id for the request ring */
+ IN PBE_CQ_OBJECT cq_object,
+ OUT PBE_ETHSQ_OBJECT eth_sq)
+{
+ BE_ETH_SQ_PARAMETERS ex_parameters = { 0 };
+
+ return be_eth_sq_create_ex(function_object,
+ sgl,
+ length,
+ type,
+ ulp, cq_object, &ex_parameters, eth_sq);
+}
+
+/*!
+
+@brief
+ This routine returns the RID for an Etx SQ
+
+@param
+ EthSq - EthSq Handle returned from EthSqCreate
+
+@return
+ The RID for an Etx SQ
+
+@note
+
+*/
+u32 be_eth_sq_get_id(IN PBE_ETHSQ_OBJECT eth_sq)
+{
+ ETHSQ_ASSERT(eth_sq);
+ return eth_sq->bid;
+}
+
+/*!
+
+@brief
+ This routine destroys an ethernet send queue
+
+@param
+ EthSq - EthSq Handle returned from EthSqCreate
+
+@return
+ This function always return BE_SUCCESS.
+
+@note
+ This function frees memory allocated by EthSqCreate for the EthSq Object.
+
+*/
+BESTATUS be_eth_sq_destroy(IN PBE_ETHSQ_OBJECT eth_sq)
+{
+ BESTATUS status = 0;
+
+ ETHSQ_ASSERT(eth_sq);
+
+ /* Send ioctl to destroy the queue. */
+ status =
+ be_function_ring_destroy(eth_sq->parent_function, eth_sq->bid,
+ IOCTL_RING_TYPE_ETH_TX);
+ ASSERT(status == 0);
+
+ /* Derefence any associated CQs. */
+ be_cq_object_dereference(eth_sq->cq_object);
+
+ /* Remove from function */
+ _be_function_remove_eth_sq(eth_sq->parent_function, eth_sq);
+
+ /* Clear tracking object */
+ sa_zero_mem(eth_sq, sizeof(*eth_sq));
+
+ return status;
+}
+
+/*!
+
+@brief
+ This routine attempts to set the transmit flow control parameters.
+
+@param
+ FunctionObject - Handle to a function object
+
+@param
+ txfc_enable - transmit flow control enable - true for
+ enable, false for disable
+
+@param
+ rxfc_enable - receive flow control enable - true for
+ enable, false for disable
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS error
+ code is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+
+ This function always fails in non-privileged machine context.
+*/
+BESTATUS
+be_eth_set_flow_control(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean txfc_enable, IN boolean rxfc_enable)
+{
+ IOCTL_COMMON_SET_FLOW_CONTROL *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_SET_FLOW_CONTROL);
+
+ ioctl->params.request.rx_flow_control = rxfc_enable;
+ ioctl->params.request.tx_flow_control = txfc_enable;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "set flow control ioctl failed.");
+ goto error;
+ }
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*!
+
+@brief
+ This routine attempts to get the transmit flow control parameters.
+
+@param
+ FunctionObject - Handle to a function object
+
+@param
+ txfc_enable - transmit flow control enable - true for
+ enable, false for disable
+
+@param
+ rxfc_enable - receive flow control enable - true for enable,
+ false for disable
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS error code
+ is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+
+ This function always fails in non-privileged machine context.
+*/
+BESTATUS
+be_eth_get_flow_control(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean *txfc_enable, IN boolean *rxfc_enable)
+{
+ IOCTL_COMMON_GET_FLOW_CONTROL *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_GET_FLOW_CONTROL);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "get flow control ioctl failed.");
+ goto error;
+ }
+
+ *txfc_enable = ioctl->params.response.tx_flow_control;
+ *rxfc_enable = ioctl->params.response.rx_flow_control;
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *---------------------------------------------------------
+ * Function: be_eth_set_qos
+ * This function sets the ethernet transmit Quality of Service (QoS)
+ * characteristics of BladeEngine for the domain. All ethernet
+ * transmit rings of the domain will evenly share the bandwidth.
+ * The exeception to sharing is the host primary (super) ethernet
+ * transmit ring as well as the host ethernet forwarding ring
+ * for missed offload data.
+ * function_object -
+ * max_bps - the maximum bits per second in units of
+ * 10 Mbps (valid 0-100)
+ * max_pps - the maximum packets per second in units
+ * of 1 Kpps (0 indicates no limit)
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------
+ */
+BESTATUS
+be_eth_set_qos(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 max_bps, IN u32 max_pps)
+{
+ IOCTL_COMMON_SET_QOS *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_SET_QOS);
+
+ /* Set fields in ioctl */
+ ioctl->params.request.max_bits_per_second_NIC = max_bps;
+ ioctl->params.request.max_packets_per_second_NIC = max_pps;
+ ioctl->params.request.valid_flags = QOS_BITS_NIC | QOS_PKTS_NIC;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "network set qos ioctl failed.");
+ }
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *---------------------------------------------------------
+ * Function: be_eth_get_qos
+ * This function retrieves the ethernet transmit Quality of Service (QoS)
+ * characteristics for the domain.
+ * function_object -
+ * max_bps - the maximum bits per second in units of
+ * 10 Mbps (valid 0-100)
+ * max_pps - the maximum packets per second in units of
+ * 1 Kpps (0 indicates no limit)
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------
+ */
+BESTATUS
+be_eth_get_qos(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 *max_bps, IN u32 *max_pps)
+{
+ IOCTL_COMMON_GET_QOS *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_GET_QOS);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "network get qos ioctl failed.");
+ goto error;
+ }
+
+ *max_bps = ioctl->params.response.max_bits_per_second_NIC;
+ *max_pps = ioctl->params.response.max_packets_per_second_NIC;
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*
+ *---------------------------------------------------------
+ * Function: be_eth_set_frame_size
+ * This function sets the ethernet maximum frame size. The previous
+ * values are returned.
+ * function_object -
+ * tx_frame_size - maximum transmit frame size in bytes
+ * rx_frame_size - maximum receive frame size in bytes
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *---------------------------------------------------------
+ */
+BESTATUS
+be_eth_set_frame_size(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT u32 *tx_frame_size,
+ IN OUT u32 *rx_frame_size)
+{
+ IOCTL_COMMON_SET_FRAME_SIZE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_SET_FRAME_SIZE);
+ ioctl->params.request.max_tx_frame_size = *tx_frame_size;
+ ioctl->params.request.max_rx_frame_size = *rx_frame_size;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "network set frame size ioctl failed.");
+ goto error;
+ }
+
+ *tx_frame_size = ioctl->params.response.chip_max_tx_frame_size;
+ *rx_frame_size = ioctl->params.response.chip_max_rx_frame_size;
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/ethrx_ll.c benet/linux-2.6.24.2/drivers/message/beclib/ethrx_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/ethrx_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/ethrx_ll.c 2008-02-14 15:23:07.807205888 +0530
@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*!
+
+@brief
+ This routine creates a Ethernet receive ring.
+
+@param
+ function_object - handle to a function object
+@param
+ rq_base_va - base VA for the default receive ring. this must be
+ exactly 8K in length and continguous physical memory.
+@param
+ cq_object - handle to a previously created CQ to be associated
+ with the RQ.
+@param
+ pp_eth_rq - pointer to an opqaue handle where an eth
+ receive object is returned.
+@return
+ BE_SUCCESS if successfull, , otherwise a useful
+ BESTATUS error code is returned.
+@note
+ IRQL: < DISPATCH_LEVEL
+ this function allocates a PBE_ETHRQ_OBJECT object.
+ there must be no more than 1 of these per function object, unless the
+ function object supports RSS (is networking and on the host).
+ the rq_base_va must point to a buffer of exactly 8K.
+ the erx::host_cqid (or host_stor_cqid) register and erx::ring_page registers
+ will be updated as appropriate on return
+*/
+BESTATUS
+be_eth_rq_create(PBE_FUNCTION_OBJECT function_object,
+ PSA_SGL sgl,
+ PBE_CQ_OBJECT cq_object,
+ PBE_CQ_OBJECT bcmc_cq_object, PBE_ETHRQ_OBJECT eth_rq)
+{
+ BESTATUS status = 0;
+ MCC_WRB *wrb = NULL;
+ IOCTL_COMMON_ETH_RX_CREATE *ioctl = NULL;
+
+ /* MPU will set the */
+ ASSERT(sgl);
+ ASSERT(eth_rq);
+
+ FUNCTION_ASSERT(function_object);
+ CQ_ASSERT(cq_object);
+
+ be_lock_wrb_post(function_object);
+
+ eth_rq->magic = BE_ETHRQ_MAGIC;
+ eth_rq->parent_function = function_object;
+ eth_rq->cq_object = cq_object;
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_ETH_RX_CREATE);
+
+ ioctl->params.request.num_pages = 2; /* required length */
+ ioctl->params.request.cq_id = be_cq_get_id(cq_object);
+
+ if (bcmc_cq_object) {
+ /* Only pd 0 host & storage can receive broadcast/multicast. */
+ if (be_function_get_pd_number(function_object) != 0) {
+ TRACE(DL_WARN,
+ "bcmc_cq_object ignored for pd_number:%d",
+ be_function_get_pd_number(function_object));
+ }
+ ioctl->params.request.bcmc_cq_id =
+ be_cq_get_id(bcmc_cq_object);
+ } else {
+ ioctl->params.request.bcmc_cq_id = 0xFFFF;
+ }
+
+ /* Create a page list for the IOCTL. */
+ be_sgl_to_pa_list(sgl,
+ ioctl->params.request.pages,
+ SA_NUMBER_OF(ioctl->params.request.pages));
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "ioctl to map eth rxq frags failed.");
+ goto Error;
+ }
+ /* Save the ring ID for cleanup. */
+ eth_rq->rid = ioctl->params.response.id;
+
+ be_cq_object_reference(cq_object);
+
+ _be_function_add_eth_rq(function_object, eth_rq);
+
+ TRACE(DL_INFO,
+ "eth rq created. function:%d pd:%d bytes:%d bcmc_id:%d cq_id:%d",
+ be_function_get_function_number(function_object),
+ be_function_get_pd_number(function_object),
+ sa_sgl_get_page_count(sgl) * SA_PAGE_SIZE,
+ (bcmc_cq_object ? be_cq_get_id(bcmc_cq_object) : -1),
+ be_cq_get_id(cq_object));
+
+Error:
+
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+
+@brief
+ This routine returns the RID for an Ethernet receive queue
+
+@param
+ EthRq - Ethernet receive queue handle returned from EthRqCreate
+
+@return
+ Returns BE_SUCCESS on success and an appropriate BESTATUS on failure.
+
+@note
+ IRQL: <= DISPATCH_LEVEL
+*/
+u32 be_eth_rq_get_id(IN PBE_ETHRQ_OBJECT rq)
+{
+ ETHRQ_ASSERT(rq);
+ return rq->rid;
+}
+
+/*!
+
+@brief
+ This routine destroys an Ethernet receive queue
+
+@param
+ eth_rq - ethernet receive queue handle returned from eth_rq_create
+
+@return
+ Returns BE_SUCCESS on success and an appropriate BESTATUS on failure.
+
+@note
+ This function frees resourcs allocated by EthRqCreate.
+ The erx::host_cqid (or host_stor_cqid) register and erx::ring_page registers
+ will be updated as appropriate on return
+ IRQL: < DISPATCH_LEVEL
+*/
+
+void be_eth_rq_destroy_internal_callback(PVOID context, BESTATUS status,
+ MCC_WRB *wrb)
+{
+ PBE_ETHRQ_OBJECT eth_rq = (PBE_ETHRQ_OBJECT) context;
+ ETHRQ_ASSERT(eth_rq);
+
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR,
+ "Destroy eth rq failed in internal callback.\n");
+ } else {
+ /* Dereference any CQs associated with this queue. */
+ be_cq_object_dereference(eth_rq->cq_object);
+
+ /* Remove from the function object. */
+ _be_function_remove_eth_rq(eth_rq->parent_function,
+ eth_rq);
+ }
+
+ return;
+}
+
+BESTATUS
+be_eth_rq_destroy_async(IN PBE_ETHRQ_OBJECT eth_rq,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context)
+{
+ BESTATUS status = BE_SUCCESS;
+ ETHRQ_ASSERT(eth_rq);
+
+ /* Send ioctl to destroy the RQ. */
+ status = be_function_ring_destroy_async(eth_rq->parent_function,
+ eth_rq->rid,
+ IOCTL_RING_TYPE_ETH_RX,
+ callback,
+ callback_context,
+ be_eth_rq_destroy_internal_callback,
+ eth_rq);
+
+ return status;
+}
+
+BESTATUS be_eth_rq_destroy(IN PBE_ETHRQ_OBJECT eth_rq)
+{
+ return be_eth_rq_destroy_async(eth_rq, NULL, NULL);
+}
+
+/*
+ *---------------------------------------------------------------------------
+ * Function: be_eth_rq_destroy_options
+ * Destroys an ethernet receive ring with finer granularity options
+ * than the standard be_eth_rq_destroy() API function.
+ * eth_rq -
+ * flush - Set to 1 to flush the ring, set to 0 to bypass the flush
+ * callback - Callback function on completion
+ * callback_context - Callback context
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *----------------------------------------------------------------------------
+ */
+BESTATUS
+be_eth_rq_destroy_options(IN PBE_ETHRQ_OBJECT eth_rq,
+ IN boolean flush,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context)
+{
+ IOCTL_COMMON_RING_DESTROY *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = BE_SUCCESS;
+ PBE_FUNCTION_OBJECT function_object = NULL;
+
+ ETHRQ_ASSERT(eth_rq);
+
+ function_object = eth_rq->parent_function;
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ TRACE(DL_INFO, "Destroy eth_rq ring id:%d, flush:%d", eth_rq->rid,
+ flush);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in destroy eth_rq ring.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_RING_DESTROY);
+
+ ioctl->params.request.id = eth_rq->rid;
+ ioctl->params.request.ring_type = IOCTL_RING_TYPE_ETH_RX;
+ ioctl->params.request.bypass_flush = ((0 == flush) ? 1 : 0);
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_internal_callback
+ (function_object, wrb, NULL, callback, callback_context,
+ be_eth_rq_destroy_internal_callback, eth_rq, ioctl);
+
+ if (status != BE_SUCCESS && status != BE_PENDING) {
+ TRACE(DL_ERR,
+ "eth_rq ring destroy ioctl failed. id:%d, flush:%d",
+ eth_rq->rid, flush);
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+
+@brief
+ This routine queries the frag size for erx.
+
+@param
+ function_object - handle to a function object
+
+@param
+ frag_size_bytes - erx frag size in bytes that is/was set.
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS error
+ code is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+
+*/
+BESTATUS
+be_eth_rq_get_frag_size(IN PBE_FUNCTION_OBJECT function_object,
+ OUT u32 *frag_size_bytes)
+{
+ IOCTL_ETH_GET_RX_FRAG_SIZE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ ASSERT(frag_size_bytes);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ return BE_STATUS_NO_MCC_WRB;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ ETH_GET_RX_FRAG_SIZE);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, /* context */
+ ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "get frag size ioctl failed.");
+ goto error;
+ }
+
+ *frag_size_bytes =
+ 1 << ioctl->params.response.actual_fragsize_log2;
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
+
+/*!
+
+@brief
+ This routine attempts to set the frag size for erx. If the frag size is
+ already set, the attempt fails and the current frag size is returned.
+
+@param
+ FunctionObject - Handle to a function object
+
+@param
+ FragSizeEncoded - Encoded erx frag size to attempt to set to.
+
+@param
+ FragSizeBytes - Erx frag size in bytes that is/was set.
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS error
+ code is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+
+ This function always fails in non-privileged machine context.
+*/
+BESTATUS
+be_eth_rq_set_frag_size(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 new_frag_size_bytes,
+ OUT u32 *current_frag_size_bytes)
+{
+ IOCTL_ETH_SET_RX_FRAG_SIZE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ ASSERT(current_frag_size_bytes);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ ETH_SET_RX_FRAG_SIZE);
+
+ ASSERT(new_frag_size_bytes >= 128 &&
+ new_frag_size_bytes <= 16 * 1024);
+
+ /* This is the log2 of the fragsize. This is not the exact
+ * ERX encoding. */
+ ioctl->params.request.new_fragsize_log2 =
+ sa_log2(new_frag_size_bytes);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object, wrb, NULL,
+ NULL, /* context */
+ ioctl);
+
+ if (status != 0) {
+ TRACE(DL_ERR, "set frag size ioctl failed.");
+ goto error;
+ }
+
+ *current_frag_size_bytes =
+ 1 << ioctl->params.response.actual_fragsize_log2;
+
+error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/rxf_ll.c benet/linux-2.6.24.2/drivers/message/beclib/rxf_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/rxf_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/rxf_ll.c 2008-02-14 15:32:13.489249608 +0530
@@ -0,0 +1,1008 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*!
+
+@brief
+ This routine adds, removes, or reads a WoL magic packet.
+
+@param
+ FunctionObject - Function object handle.
+
+@param
+ Mac1 - Set to TRUE if this function will operate on
+ the MAC 1 Magic Packet.
+
+@param
+ Operation - Operation to perform.
+
+@param
+ Pattern - Pattern to set, or the pattern returned.
+
+@param
+ PatternMask - Pattern mask to set, or the pattern mask returned.
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+
+*/
+BESTATUS be_rxf_wake_on_lan_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean enable_port0, IN boolean enable_port1,
+ IN boolean magic_packet_enable, IN u32 index,
+ IN PVOID pattern, IN PVOID pattern_mask,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_WAKE_ON_LAN_QUEUE_CONTEXT queue_context
+ )
+{
+ IOCTL_ETH_ACPI_CONFIG *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = BE_SUCCESS;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+
+ /* Valid range for index is 0-3. */
+ ASSERT(index < 4);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ ETH_ACPI_CONFIG);
+
+ ioctl->params.request.index = index;
+ ioctl->params.request.port0 = enable_port0;
+ ioctl->params.request.port1 = enable_port1;
+ ioctl->params.request.magic_packet = magic_packet_enable;
+
+ if (enable_port0 || enable_port1) {
+
+ if (pattern) {
+ sa_memcpy(ioctl->params.request.byte_pattern,
+ pattern,
+ sizeof(ioctl->params.request.
+ byte_pattern));
+ }
+ if (pattern_mask) {
+ sa_memcpy(ioctl->params.request.bit_mask,
+ pattern_mask,
+ sizeof(ioctl->params.request.bit_mask));
+ }
+ /* Track which indicies are enabled/disabled */
+ function_object->config.wol_bitmask |= (1 << index);
+ } else {
+
+ /* Track which indicies are enabled/disabled */
+ function_object->config.wol_bitmask &= ~(1 << index);
+ }
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+ if (status < 0) {
+ TRACE(DL_ERR, "wake-on-lan ioctl failed.");
+ goto Error;
+ }
+
+ Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+@brief
+ This routine gets or sets a mac address for a domain
+ given the port and mac.
+@param
+ FunctionObject - Function object handle.
+@param
+ Port1 - Set to TRUE if this function will set/get the Port 1
+ address. Only the host may set this to TRUE.
+@param
+ Mac1 - Set to TRUE if this function will set/get the
+ MAC 1 address. Only the host may set this to TRUE.
+@param
+ Write - Set to TRUE if this function should write the mac address.
+@param
+ MacAddress - Buffer of the mac address to read or write.
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+@note
+ IRQL: < DISPATCH_LEVEL
+*/
+BESTATUS be_rxf_mac_address_read_write(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean port1, /* VM must always set to false */
+ IN boolean mac1, /* VM must always set to false */
+ IN boolean mgmt, IN boolean write,
+ IN boolean permanent, IN OUT PSA_MAC_ADDRESS mac_address,
+ IN MCC_WRB_CQE_CALLBACK callback, /* optional */
+ IN PVOID callback_context) /* optional */
+{
+ BESTATUS status = BE_SUCCESS;
+ union {
+ IOCTL_COMMON_NTWK_MAC_QUERY *query;
+ IOCTL_COMMON_NTWK_MAC_SET *set;
+ } ioctl = {
+ 0};
+ MCC_WRB *wrb = NULL;
+ u32 type = 0;
+
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ ASSERT(mac_address);
+
+ ASSERT(port1 == FALSE
+ || be_function_is_vm(function_object) == FALSE);
+ ASSERT(mac1 == FALSE
+ || be_function_is_vm(function_object) == FALSE);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ TRACE(DL_ERR, "MCC wrb peek failed.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+
+ if (mgmt) {
+ type = MAC_ADDRESS_TYPE_MANAGEMENT;
+ } else if (be_function_is_vm(function_object) &&
+ be_function_is_networking(function_object)) {
+ type = MAC_ADDRESS_TYPE_PD;
+ } else {
+ if (be_function_is_networking(function_object)) {
+ type = MAC_ADDRESS_TYPE_NETWORK;
+ } else {
+ type = MAC_ADDRESS_TYPE_STORAGE;
+ }
+ }
+
+ if (write) {
+ /* Prepares an embedded ioctl, including
+ * request/response sizes.
+ */
+ ioctl.set = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object,
+ wrb, COMMON_NTWK_MAC_SET);
+
+ ioctl.set->params.request.invalidate = 0;
+ ioctl.set->params.request.mac1 = (mac1 ? 1 : 0);
+ ioctl.set->params.request.port = (port1 ? 1 : 0);
+ ioctl.set->params.request.type = type;
+
+ /* Copy the mac address to set. */
+ ioctl.set->params.request.mac.SizeOfStructure =
+ sizeof(ioctl.set->params.request.mac);
+ sa_memcpy(ioctl.set->params.request.mac.MACAddress,
+ mac_address, sizeof(*mac_address));
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb(function_object,
+ wrb,
+ callback,
+ callback_context,
+ ioctl.set);
+
+ } else {
+
+ /*
+ * Prepares an embedded ioctl, including
+ * request/response sizes.
+ */
+ ioctl.query =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object,
+ wrb, COMMON_NTWK_MAC_QUERY);
+
+ ioctl.query->params.request.mac1 = (mac1 ? 1 : 0);
+ ioctl.query->params.request.port = (port1 ? 1 : 0);
+ ioctl.query->params.request.type = type;
+ ioctl.query->params.request.permanent = permanent;
+
+ /* Post the Ioctl (with a copy for the response) */
+ status = be_function_post_mcc_wrb_with_copy(function_object,
+ wrb, NULL, /* queue context */
+ callback,
+ callback_context,
+ ioctl.query,
+ BE_CREATE_MCC_RESPONSE_COPY
+ (IOCTL_COMMON_NTWK_MAC_QUERY,
+ params.
+ response.mac.
+ MACAddress,
+ mac_address));
+ }
+
+ if (status < 0) {
+ TRACE(DL_ERR, "mac set/query failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+@brief
+ This routine writes data to context memory.
+@param
+ FunctionObject - Function object handle.
+@param
+ McHashTable - Set to the 128-bit multicast address hash table.
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+@note
+ IRQL: < DISPATCH_LEVEL
+*/
+
+BESTATUS be_rxf_multicast_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean promiscuous, IN u32 num,
+ IN SA_MAC_ADDRESS *mac_table,
+ IN MCC_WRB_CQE_CALLBACK callback, /* optional */
+ IN PVOID callback_context,
+ IN PBE_MULTICAST_QUEUE_CONTEXT queue_context)
+{
+ BESTATUS status = BE_SUCCESS;
+ IOCTL_COMMON_NTWK_MULTICAST_SET *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(num <=
+ SA_NUMBER_OF_FIELD(IOCTL_COMMON_NTWK_MULTICAST_SET,
+ params.request.mac));
+
+ if (num > SA_NUMBER_OF_FIELD(
+ IOCTL_COMMON_NTWK_MULTICAST_SET, params.request.mac)) {
+ TRACE(DL_ERR, "Too many multicast addresses. BE supports %d.",
+ SA_NUMBER_OF_FIELD(IOCTL_COMMON_NTWK_MULTICAST_SET,
+ params.request.mac));
+ return BE_NOT_OK;
+ }
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context =
+ (PBE_GENERIC_QUEUE_CONTEXT) queue_context;
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_NTWK_MULTICAST_SET);
+
+ TRACE(DL_INFO,
+ "multicast config. function:%d promiscuous:%d num:%d",
+ be_function_get_function_number(function_object),
+ promiscuous, num);
+
+ ioctl->params.request.promiscuous = promiscuous;
+ if (!promiscuous) {
+
+ ioctl->params.request.num_mac = num;
+
+ if (num > 0) {
+ u32 i = 0;
+
+ ASSERT(mac_table);
+ sa_memcpy(ioctl->params.request.mac, mac_table,
+ 6 * num);
+ for (i = 0; i < num; i++) {
+ TRACE(DL_VERBOSE,
+ " multicast address[%d]: "
+ SA_MAC_FORMAT, i,
+ SA_MAC_ARGS(mac_table[i]));
+ }
+ }
+ /* track number of addresses */
+ function_object->config.num_multicast = num;
+ } else {
+ /* track number of addresses */
+ function_object->config.num_multicast = 0xFF; /* infinite */
+ }
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+ if (status < 0) {
+ TRACE(DL_ERR, "multicast ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+@brief
+ This routine adds or removes a vlan tag from the rxf table.
+@param
+ FunctionObject - Function object handle.
+@param
+ VLanTag - VLan tag to add or remove.
+@param
+ Add - Set to TRUE if this will add a vlan tag
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+@note
+ IRQL: < DISPATCH_LEVEL
+*/
+BESTATUS be_rxf_vlan_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean promiscuous, IN u32 num,
+ IN u16 *vlan_tag_array,
+ IN MCC_WRB_CQE_CALLBACK callback, /* optional */
+ IN PVOID callback_context,
+ IN PBE_VLAN_QUEUE_CONTEXT queue_context) /* optional */
+{
+ BESTATUS status = BE_SUCCESS;
+ IOCTL_COMMON_NTWK_VLAN_CONFIG *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(num <=
+ SA_NUMBER_OF_FIELD(IOCTL_COMMON_NTWK_VLAN_CONFIG,
+ params.request.vlan_tag));
+ if (num >
+ SA_NUMBER_OF_FIELD(IOCTL_COMMON_NTWK_VLAN_CONFIG,
+ params.request.vlan_tag)) {
+ TRACE(DL_ERR, "Too many VLAN tags.");
+ return BE_NOT_OK;
+ }
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_NTWK_VLAN_CONFIG);
+
+ TRACE(DL_INFO, "vlan config. function:%d promiscuous:%d num:%d",
+ be_function_get_function_number(function_object),
+ promiscuous, num);
+
+ ioctl->params.request.promiscuous = promiscuous;
+ if (!promiscuous) {
+
+ ioctl->params.request.num_vlan = num;
+
+ if (num > 0) {
+ ASSERT(vlan_tag_array);
+ sa_memcpy(ioctl->params.request.vlan_tag,
+ vlan_tag_array,
+ num * sizeof(vlan_tag_array[0]));
+ }
+ /* Track number of tags */
+ function_object->config.num_vlan = num;
+
+ } else {
+ /* promiscuous mode, tracking number is set inifinite */
+ function_object->config.num_vlan = 0xFF;
+ }
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+ if (status < 0) {
+ TRACE(DL_ERR, "vlan ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+@brief
+ This routine assigns a CPU number to an RSS table.
+@param
+ FunctionObject - Function object handle.
+@param
+ RssEntry - The RSS entry (bucket) to assign this CPU to.
+@param
+ Cpu - The CPU number that incomming packets that hash to
+ the RssEntry bucket index will be directed to.
+@return
+ BE_SUCCESS if successfull, otherwise a useful BESTATUS is returned.
+
+@note
+ IRQL: < DISPATCH_LEVEL
+*/
+BESTATUS be_rxf_rss_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 rss_type, /* use enumeration ENABLE_RSS_ENUM */
+ IN u32 num_cq, /* 2, 3, or 4 */
+ IN u32 *cq_id_array, /* Array of num_cq id values */
+ IN u32 default_cq_id, /* non-RSS default CQ ID */
+ IN u32 flush_mask, /* mask of CQs to flush */
+ IN PVOID hash, /* 16 bytes */
+ IN u32 cpu_table_length, /* bytes (power of 2 from 2 to 128) */
+ IN u8 *cpu_table, /* 2 to 128 bytes */
+ IN MCC_WRB_CQE_CALLBACK callback, /* optional */
+ IN PVOID callback_context,
+ IN PBE_RSS_QUEUE_CONTEXT queue_context) /* optional */
+{
+ BESTATUS status = BE_SUCCESS;
+ IOCTL_ETH_RSS_CONFIG *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_wrb_post(function_object);
+
+ ASSERT(!be_function_is_vm(function_object));
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ ETH_RSS_CONFIG);
+
+ ioctl->params.request.enable_rss = rss_type;
+ ioctl->params.request.cq_flush_mask = flush_mask;
+
+ if (cq_id_array) {
+ ioctl->params.request.cqid0 = cq_id_array[0];
+ ioctl->params.request.cqid1 = cq_id_array[1];
+ ioctl->params.request.cqid2 = cq_id_array[2];
+ ioctl->params.request.cqid3 = cq_id_array[3];
+ }
+
+ if (rss_type != RSS_ENABLE_NONE) {
+ ASSERT(num_cq >= 1 && num_cq <= 4);
+ ASSERT(cq_id_array);
+ ASSERT(hash);
+ }
+
+ if (hash) {
+ sa_memcpy(ioctl->params.request.hash, hash,
+ sizeof(ioctl->params.request.hash));
+ }
+ /*
+ * Double check the table. Each entry should be 0 to
+ * num_cq-1 corresponding to the index in the cq_id_array to use.
+ */
+ if (cpu_table_length > 0) {
+
+ ASSERT(cpu_table);
+ ASSERT(cpu_table_length <=
+ sizeof(ioctl->params.request.cpu_table));
+
+ ioctl->params.request.cpu_table_size_log2 =
+ sa_log2(cpu_table_length);
+ ASSERT(ioctl->params.request.cpu_table_size_log2 > 0
+ && ioctl->params.request.cpu_table_size_log2 <= 7);
+
+ sa_memcpy(ioctl->params.request.cpu_table, cpu_table,
+ cpu_table_length);
+ }
+
+ TRACE(DL_INFO, "RSS hash. 0x%08x 0x%08x 0x%08x 0x%08x",
+ ioctl->params.request.hash[0],
+ ioctl->params.request.hash[1],
+ ioctl->params.request.hash[2],
+ ioctl->params.request.hash[3]);
+
+ TRACE(DL_INFO,
+ "RSS table. log2(len):%d 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
+ " 0x%02x 0x%02x 0x%02x",
+ ioctl->params.request.cpu_table_size_log2,
+ ioctl->params.request.cpu_table[0],
+ ioctl->params.request.cpu_table[1],
+ ioctl->params.request.cpu_table[2],
+ ioctl->params.request.cpu_table[3],
+ ioctl->params.request.cpu_table[4],
+ ioctl->params.request.cpu_table[5],
+ ioctl->params.request.cpu_table[6],
+ ioctl->params.request.cpu_table[7]);
+
+ /* software tracking */
+ function_object->config.rss_type = rss_type;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb, generic_context, callback,
+ callback_context, ioctl);
+ if (status < 0) {
+ TRACE(DL_ERR, "rss ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+BESTATUS be_rxf_link_status(IN PBE_FUNCTION_OBJECT function_object,
+ OUT BE_LINK_STATUS *link_status,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_LINK_STATUS_QUEUE_CONTEXT queue_context) /* optional */
+{
+ IOCTL_COMMON_NTWK_LINK_STATUS_QUERY *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ ASSERT(link_status);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_NTWK_LINK_STATUS_QUERY);
+
+ /* Post or queue the Ioctl */
+ status = be_function_post_mcc_wrb_with_copy(function_object, wrb,
+ generic_context, /* Queue context */
+ callback,
+ callback_context,
+ ioctl,
+ BE_CREATE_MCC_RESPONSE_COPY
+ (IOCTL_COMMON_NTWK_LINK_STATUS_QUERY,
+ params.response,
+ link_status));
+
+ if (status < 0) {
+ TRACE(DL_ERR, "link status ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+BESTATUS
+be_rxf_query_eth_statistics(IN PBE_FUNCTION_OBJECT function_object,
+ IN IOCTL_ETH_GET_STATISTICS *va_for_ioctl,
+ IN u64 pa_for_ioctl,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_ETH_STATS_QUEUE_CONTEXT queue_context)
+{
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ ASSERT(va_for_ioctl);
+ ASSERT(pa_for_ioctl);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+
+ TRACE(DL_INFO,
+ "Query eth stats. ioctl va:%p pa:0x%08x_%08x",
+ va_for_ioctl, sa_hi(pa_for_ioctl), sa_lo(pa_for_ioctl));
+
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ va_for_ioctl =
+ BE_FUNCTION_PREPARE_NONEMBEDDED_IOCTL(function_object, wrb,
+ va_for_ioctl, pa_for_ioctl, ETH_GET_STATISTICS);
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb, generic_context, callback, callback_context,
+ va_for_ioctl);
+
+ if (status < 0) {
+ TRACE(DL_ERR, "eth stats ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+BESTATUS
+be_rxf_promiscuous(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean enable_port0,
+ IN boolean enable_port1,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_PROMISCUOUS_QUEUE_CONTEXT queue_context)
+{
+ IOCTL_ETH_PROMISCUOUS *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ ETH_PROMISCUOUS);
+
+ ioctl->params.request.port0_promiscuous = enable_port0;
+ ioctl->params.request.port1_promiscuous = enable_port1;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb, generic_context, callback, callback_context,
+ ioctl);
+
+ if (status < 0) {
+ TRACE(DL_ERR, "promiscuous ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*
+ *------------------------------------------------------------------
+ * Function: be_rxf_force_failover
+ * Forces failure of all traffic to the specified MAC port.
+ * Use the be_rxf_link_status to query to active port. Automatic
+ * failover feature of BladeEngine is implicitly disabled with this call.
+ * function_object -
+ * port - Port to use, 0 or 1.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated
+ * BE_QUEUE_CONTEXT struct. If the MCC WRB ring is
+ * full, this structure is used to queue the operation.
+ * It will be posted to the MCC ring when space
+ * becomes available. All queued commands will be
+ * posted to the ring in the order they are received.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *--------------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_force_failover(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 port,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_FORCE_FAILOVER_QUEUE_CONTEXT queue_context)
+{
+ IOCTL_COMMON_FORCE_FAILOVER *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_FORCE_FAILOVER);
+
+ ASSERT(port == 0 || port == 1);
+ ioctl->params.request.move_to_port = port;
+ ioctl->params.request.failover_config = FAILOVER_CONFIG_OFF;
+
+ /* Post the Ioctl */
+ status = be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+ if (status < 0) {
+ TRACE(DL_ERR, "force failover ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*
+ *--------------------------------------------------------------------------
+ * Function: be_rxf_manage_autofailover
+ * Enables or disables BladeEngine automatic port failover.
+ * function_object -
+ * enable - Set to 1 to enable the feature. Set to 0 to disable
+ * the feature.
+ * callback - Optional callback function. When the command
+ * completes the callback function will be called
+ * with the callback context.
+ * callback_context - Optional callback context.
+ * queue_context - Optional. Pointer to a previously allocated
+ * BE_QUEUE_CONTEXT struct. If the MCC WRB ring is full,
+ * this structure is used to queue the operation. It
+ * will be posted to the MCC ring when space
+ * becomes available. All queued commands will
+ * be posted to the ring in the order they are received.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *-----------------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_manage_autofailover(IN PBE_FUNCTION_OBJECT function_object,
+ IN boolean enable,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_FORCE_FAILOVER_QUEUE_CONTEXT
+ queue_context)
+{
+ IOCTL_COMMON_FORCE_FAILOVER *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_FORCE_FAILOVER);
+
+ if (enable) {
+ ioctl->params.request.failover_config = FAILOVER_CONFIG_ON;
+ } else {
+ ioctl->params.request.failover_config =
+ FAILOVER_CONFIG_OFF;
+ }
+ ioctl->params.request.move_to_port = FAILOVER_PORT_NONE;
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+ if (status < 0) {
+ TRACE(DL_ERR, "manage autofailover ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*
+ *-------------------------------------------------------------------------
+ * Function: be_rxf_filter_config
+ * Configures BladeEngine ethernet receive filter settings.
+ * function_object -
+ * settings - Pointer to the requested filter settings.
+ * The response from BladeEngine will be placed back
+ * in this structure.
+ * callback - optional
+ * callback_context - optional
+ * queue_context - Optional. Pointer to a previously allocated struct.
+ * If the MCC WRB ring is full, this structure is
+ * used to queue the operation. It will be posted
+ * to the MCC ring when space becomes available. All
+ * queued commands will be posted to the ring in
+ * the order they are received. It is always valid
+ * to pass a pointer to a generic
+ * BE_GENERIC_QUEUE_CONTEXT. However, the specific
+ * context structs are generally smaller than
+ * the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *---------------------------------------------------------------------------
+ */
+BESTATUS
+be_rxf_filter_config(IN PBE_FUNCTION_OBJECT function_object,
+ IN OUT NTWK_RX_FILTER_SETTINGS *settings,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_RXF_FILTER_QUEUE_CONTEXT queue_context)
+{
+ IOCTL_COMMON_NTWK_RX_FILTER *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+
+ ASSERT(settings);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context; /* Indicate to queue */
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl = BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_NTWK_RX_FILTER);
+ sa_memcpy(&ioctl->params.request, settings, sizeof(*settings));
+
+ /* Post or queue the Ioctl */
+ status = be_function_post_mcc_wrb_with_copy(function_object,
+ wrb, generic_context, /* Queue context */
+ callback,
+ callback_context,
+ ioctl,
+ BE_CREATE_MCC_RESPONSE_COPY
+ (IOCTL_COMMON_NTWK_RX_FILTER,
+ params.response,
+ settings));
+
+ if (status < 0) {
+ TRACE(DL_ERR, "RXF/ERX filter config ioctl failed.");
+ goto Error;
+ }
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
___________________________________________________________________________________
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^ permalink raw reply
* [PATHCH 8/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:43 UTC (permalink / raw)
To: netdev
Event queue, completion queue and management
processor ring creation functions in
beclib.
--------------------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/eq_ll.c benet/linux-2.6.24.2/drivers/message/beclib/eq_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/eq_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/eq_ll.c 2008-02-14 15:23:07.809205584 +0530
@@ -0,0 +1,751 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*
+ *============================================================================
+ * F I L E S C O P E
+ *============================================================================
+ */
+
+/*!
+
+@brief
+ This routine serializes access to resources maintained through an EQ object.
+
+@param
+ eq_object - The event queue object to acquire the lock for.
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+
+STATIC void _be_eq_lock(IN PBE_EQ_OBJECT eq_object)
+{
+ SA_NOT_USED(eq_object);
+ /*
+ * BUG - Work around storport driver dispatch issues.
+ *SA_ASSERT_BLOCKING ();
+ *be_lock_acquire (&eq_object->lock);
+ */
+}
+
+/*!
+
+@brief
+ This routine removes serialization done by EqObjectLock.
+@param
+ eq_object - the event queue object to drop the lock for.
+@return
+@note
+ IRQL < DISPATCH_LEVEL
+*/
+STATIC void _be_eq_unlock(IN PBE_EQ_OBJECT eq_object)
+{
+ SA_NOT_USED(eq_object);
+ /*be_lock_release (&eq_object->lock); */
+}
+
+STATIC
+ INLINE
+ PBE_EQ_OBJECT
+_be_eq_id_to_object(IN PBE_FUNCTION_OBJECT function_object, IN u32 eq_id)
+{
+ PBE_EQ_OBJECT eq_cur;
+ PBE_EQ_OBJECT eq_ret = NULL;
+
+ _be_function_lock(function_object);
+
+ SA_FOR_EACH_LIST_ENTRY(eq_cur, function_object->links.eq_list_head,
+ BE_EQ_OBJECT, eq_list) {
+ if (be_eq_get_id(eq_cur) == eq_id) {
+
+ eq_ret = eq_cur;
+ break;
+ }
+ }
+
+ _be_function_unlock(function_object);
+
+ return eq_ret;
+}
+
+/*
+ *============================================================================
+ * P U B L I C R O U T I N E S
+ *============================================================================
+ */
+
+/*!
+
+@brief
+ This routine creates an event queue based on the client completion
+ queue configuration information.
+
+@param
+ FunctionObject - Handle to a function object
+@param
+ EqBaseVa - Base VA for a the EQ ring
+@param
+ SizeEncoding - The encoded size for the EQ entries. This value is
+ either CEV_EQ_SIZE_4 or CEV_EQ_SIZE_16
+@param
+ NumEntries - CEV_CQ_CNT_* values.
+@param
+ Watermark - Enables watermark based coalescing. This parameter
+ must be of the type CEV_WMARK_* if watermarks
+ are enabled. If watermarks to to be disabled
+ this value should be-1.
+@param
+ TimerDelay - If a timer delay is enabled this value should be the
+ time of the delay in 8 microsecond units. If
+ delays are not used this parameter should be
+ set to -1.
+@param
+ ppEqObject - Internal EQ Handle returned.
+
+@return
+ BE_SUCCESS if successfull,, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+ If the FunctionObject represents an ISCSI function, then the EQID
+ returned will be between 0-31.
+*/
+BESTATUS be_eq_create_internal(PBE_FUNCTION_OBJECT function_object,
+ PSA_SGL sgl, u32 eqe_size, u32 num_entries,
+ u32 watermark, /* CEV_WMARK_* or -1 */
+ u32 timer_delay, /* in 8us units, or -1 */
+ boolean fake_eq, PBE_EQ_OBJECT eq_object)
+{
+ BESTATUS status = BE_SUCCESS;
+ u32 num_entries_encoding, eqe_size_encoding, length;
+ IOCTL_COMMON_EQ_CREATE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+
+ ASSERT(sgl);
+ ASSERT(eq_object);
+
+ FUNCTION_ASSERT(function_object);
+
+ /*
+ * To avoid assuming the enumeration values are constant,
+ * I'm using a switch statement instead of calculating this
+ * with sa_log2.
+ */
+ switch (num_entries) {
+ case 256:
+ num_entries_encoding = CEV_EQ_CNT_256;
+ break;
+ case 512:
+ num_entries_encoding = CEV_EQ_CNT_512;
+ break;
+ case 1024:
+ num_entries_encoding = CEV_EQ_CNT_1024;
+ break;
+ case 2048:
+ num_entries_encoding = CEV_EQ_CNT_2048;
+ break;
+ case 4096:
+ num_entries_encoding = CEV_EQ_CNT_4096;
+ break;
+ default:
+ ASSERT(0);
+ return BE_STATUS_INVALID_PARAMETER;
+ }
+
+ /*
+ * To avoid assuming the enumeration values are constant,
+ * I'm using a switch statement instead of calculating
+ * this with sa_log2.
+ */
+ switch (eqe_size) {
+ case 4:
+ eqe_size_encoding = CEV_EQ_SIZE_4;
+ break;
+ case 16:
+ eqe_size_encoding = CEV_EQ_SIZE_16;
+ break;
+ default:
+ ASSERT(0);
+ return BE_STATUS_INVALID_PARAMETER;
+ }
+
+ if ((eqe_size == 4 && num_entries < 1024) ||
+ (eqe_size == 16 && num_entries == 4096)) {
+ TRACE(DL_ERR, "Bad EQ size. eqe_size:%d num_entries:%d",
+ eqe_size, num_entries);
+ ASSERT(0);
+ return BE_STATUS_INVALID_PARAMETER;
+ }
+
+ sa_zero_mem(eq_object, sizeof(*eq_object));
+
+ eq_object->magic = BE_EQ_MAGIC;
+ eq_object->ref_count = 0;
+ eq_object->parent_function = function_object;
+ eq_object->eq_id = 0xFFFFFFFF;
+
+ be_lock_init(&eq_object->lock);
+
+ sa_initialize_list_head(&eq_object->cq_list_head);
+
+ length = num_entries * eqe_size;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in create EQ.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_EQ_CREATE);
+
+ ioctl->params.request.num_pages =
+ SA_PAGES_SPANNED(sa_sgl_get_offset(sgl), length);
+
+ /* init the context */
+ ioctl->params.request.context.Func =
+ be_function_get_function_number(function_object);
+ ioctl->params.request.context.valid = TRUE;
+ ioctl->params.request.context.Size = eqe_size_encoding;
+ ioctl->params.request.context.PD =
+ be_function_get_pd_number(function_object);
+ ioctl->params.request.context.Count = num_entries_encoding;
+ /* Let the caller ARM the EQ with the doorbell. */
+ ioctl->params.request.context.Armed = FALSE;
+ ioctl->params.request.context.EventVect =
+ be_function_get_function_number(function_object) * 32;
+
+ if (fake_eq) {
+ ioctl->params.request.context.Cidx = 0;
+ ioctl->params.request.context.Pidx = 2;
+ ioctl->params.request.context.EPIdx = 2;
+ }
+
+ if (watermark != -1) {
+ ioctl->params.request.context.WME = TRUE;
+ ioctl->params.request.context.Watermark = watermark;
+ ASSERT(watermark <= CEV_WMARK_240);
+ } else {
+ ioctl->params.request.context.WME = FALSE;
+ }
+
+ if (timer_delay != -1) {
+ ioctl->params.request.context.TMR = TRUE;
+
+ ASSERT(timer_delay <= 250); /* max value according to EAS */
+ timer_delay = MIN(timer_delay, 250);
+
+ ioctl->params.request.context.Delay = timer_delay;
+
+ } else {
+ ioctl->params.request.context.TMR = FALSE;
+ }
+
+ /* Create a page list for the IOCTL. */
+ be_sgl_to_pa_list(sgl,
+ ioctl->params.request.pages,
+ SA_NUMBER_OF(ioctl->params.request.pages));
+
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "MCC to create EQ failed.");
+ goto Error;
+ }
+ /* Get the EQ id. The MPU allocates the IDs. */
+ eq_object->eq_id = ioctl->params.response.eq_id;
+
+ /* insert tracking object */
+ _be_function_add_eq(function_object, eq_object);
+
+ TRACE(DL_INFO,
+ "eq created. function:%d pd:%d eqid:%d bytes:%d eqeBytes:%d"
+ " wm:%d td:%d",
+ be_function_get_function_number(function_object),
+ be_function_get_pd_number(function_object), eq_object->eq_id,
+ num_entries * eqe_size, eqe_size, watermark, timer_delay);
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+BESTATUS be_eq_create(PBE_FUNCTION_OBJECT function_object, PSA_SGL
+ sgl, u32 eqe_size, u32 num_entries,
+ u32 watermark, /* CEV_WMARK_* or -1 */
+ u32 timer_delay, /* in 8us units, or -1 */
+ PBE_EQ_OBJECT eq_object)
+{
+ return be_eq_create_internal(function_object,
+ sgl,
+ eqe_size,
+ num_entries,
+ watermark,
+ timer_delay, FALSE, eq_object);
+}
+
+BESTATUS be_eq_fake_create(PBE_FUNCTION_OBJECT function_object,
+ u32 timer_delay, /* in 8us units, or -1 */
+ PBE_EQ_OBJECT eq_object)
+{
+ SA_SGL sgl;
+
+ sa_sgl_create_contiguous((PVOID) 0xbad0000,
+ (SA_PHYSICAL_ADDRESS) 0xbad00000,
+ SA_PAGE_SIZE, &sgl);
+
+ return be_eq_create_internal(function_object,
+ &sgl,
+ sizeof(EQ_ENTRY),
+ 4096 / sizeof(EQ_ENTRY),
+ 0xFFFFFFFF,
+ timer_delay, TRUE, eq_object);
+}
+
+/*!
+
+@brief
+ Returns the EQ ID for EQ. This is the ID the chip references the queue as.
+
+@param
+ EqObject - EQ Handle returned from EqObjectCreate.
+
+@return
+ EQ ID
+@note
+ IRQL: any
+
+*/
+u32 be_eq_get_id(IN PBE_EQ_OBJECT eq_object)
+{
+ EQ_ASSERT(eq_object);
+ return eq_object->eq_id;
+}
+
+/*!
+
+@brief
+ Sets the current callback to be invoked when a EQ entry is made available.
+ This need only be set if the owner of this EQ does not recieve the EQ
+ completions directly. i.e. it does not service interrupts.
+
+@param
+ eq_object - EQ handle returned from eq_object_create.
+
+@param
+ callback - function to invoke when the EQ needs processing.
+
+@param
+ context - opaque context to pass to callback.
+
+@return
+ ptr to the previous callback.
+
+@note
+ IRQL: any
+
+ this routine is currently not synchronized w/ the DPC that may run the EQ.
+ therefore it is the callers responcibility to ensure the EQ will not
+ interrupt while this routine is executing.
+*/
+EQ_CALLBACK
+be_eq_set_callback(IN PBE_EQ_OBJECT eq_object,
+ IN EQ_CALLBACK callback, IN PVOID context)
+{
+ EQ_CALLBACK old_callback;
+
+ EQ_ASSERT(eq_object);
+
+ old_callback = eq_object->callback;
+
+ eq_object->callback = callback;
+ eq_object->callback_context = context;
+
+ return old_callback;
+}
+
+/*!
+
+@brief
+ This routine handles EQ processing on EQs that were 'unrecognized' by upper
+ level drivers. The only EQs that should be processed by this routine are
+ * iWARP EQ
+ The iWARP EQ will be delegated further for handling by the
+ iWARP device driver
+
+@param
+ FunctionObject - Handle to a function object
+@param
+ EqId - The Eq that has just completed processing
+
+@return
+
+@note
+ IRQL: DISPATCH_LEVEL only
+
+ This routine should be called immediately when a EQ from a ULD is not
+ recognized.
+*/
+void
+be_eq_delegate_processing(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 eq_id)
+{
+ PBE_EQ_OBJECT eq_object;
+
+ FUNCTION_ASSERT(function_object);
+
+ eq_object = _be_eq_id_to_object(function_object, eq_id);
+
+ if (eq_object) {
+
+ eq_object->callback(function_object, eq_object,
+ eq_object->callback_context);
+
+ } else {
+
+ TRACE(DL_WARN, "eq_id %d not found for delegation", eq_id);
+ }
+
+}
+
+/*!
+
+@brief
+ This routine adds a CQ as a dependent object on the given EQ. This will
+ cause the reference count to be incrmented and the CQ to be placed on
+ the EQ's list of active CQ objects.
+
+@param
+ eq_object - EQ handle returned from eq_object_create.
+@param
+ cq_object - CQ handle that is dependent on this EQ
+
+@return
+ EQ ID
+@note
+ IRQL: < DISPATCH_LEVEL
+
+*/
+void _be_eq_add_cq(IN PBE_EQ_OBJECT eq_object, IN PBE_CQ_OBJECT cq_object)
+{
+ EQ_ASSERT(eq_object);
+
+ CQ_ASSERT(cq_object);
+
+ _be_eq_lock(eq_object);
+
+ be_eq_reference(eq_object);
+
+ sa_insert_tail_list(&eq_object->cq_list_head,
+ &cq_object->cqlist_for_eq);
+
+ _be_eq_unlock(eq_object);
+}
+
+/*!
+
+@brief
+ References the given object. The object is guaranteed to remain active until
+ the reference count drops to zero.
+
+@param
+ eq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: any
+
+*/
+u32 be_eq_reference(PBE_EQ_OBJECT eq_object)
+{
+ EQ_ASSERT(eq_object);
+ return sa_atomic_increment(&eq_object->ref_count);
+}
+
+/*!
+
+@brief
+ Dereferences the given object. The object is guaranteed to remain
+ active until the reference count drops to zero.
+
+@param
+ eq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: any
+
+*/
+u32 be_eq_dereference(PBE_EQ_OBJECT eq_object)
+{
+ EQ_ASSERT(eq_object);
+ return sa_atomic_decrement(&eq_object->ref_count);
+}
+
+/*!
+@brief
+ This routine removes a CQ as a dependent object on the given EQ. This will
+ cause the reference count to be decrmented and the CQ to be removed from
+ the EQ's list of active CQ objects.
+@param
+ eq_object - EQ handle returned from eq_object_create.
+@param
+ cq_object - CQ handle that was dependent on this EQ
+@return
+ EQ ID
+@note
+ IRQL: < DISPATCH_LEVEL
+*/
+void
+_be_eq_remove_cq(IN PBE_EQ_OBJECT eq_object, IN PBE_CQ_OBJECT cq_object)
+{
+ EQ_ASSERT(eq_object);
+ CQ_ASSERT(cq_object);
+
+ be_eq_dereference(eq_object);
+
+ _be_eq_lock(eq_object);
+ sa_remove_entry_list(&cq_object->cqlist_for_eq);
+ _be_eq_unlock(eq_object);
+}
+
+/*!
+@brief
+ Deferences the given object. Once the object's reference count drops to
+ zero, the object is destroyed and all resources that are held by this
+ object are released. The on-chip context is also destroyed along with
+ the queue ID, and any mappings made into the UT.
+@param
+ eq_object - EQ handle returned from eq_object_create.
+@return
+ BE_SUCCESS if successfull, , otherwise a useful error code is returned.
+@note
+ IRQL: IRQL < DISPATCH_LEVEL
+*/
+BESTATUS be_eq_destroy(PBE_EQ_OBJECT eq_object)
+{
+ BESTATUS status = 0;
+
+ EQ_ASSERT(eq_object);
+
+ ASSERT(eq_object->ref_count == 0);
+ /* no CQs should reference this EQ now */
+ ASSERT(sa_is_list_empty(&eq_object->cq_list_head));
+
+ /* Send ioctl to destroy the EQ. */
+ status =
+ be_function_ring_destroy(eq_object->parent_function,
+ eq_object->eq_id, IOCTL_RING_TYPE_EQ);
+ ASSERT(status == 0);
+
+ /* remove from the function */
+ _be_function_remove_eq(eq_object->parent_function, eq_object);
+
+ /* zero tracking object */
+ sa_zero_mem(eq_object, sizeof(BE_EQ_OBJECT));
+
+ return BE_SUCCESS;
+}
+
+/*
+ *---------------------------------------------------------------------------
+ * Function: be_eq_modify_delay
+ * Changes the EQ delay for a group of EQs.
+ * num_eq - The number of EQs in the eq_array to adjust.
+ * This also is the number of delay values in
+ * the eq_delay_array.
+ * eq_array - Array of BE_EQ_OBJECT pointers to adjust.
+ * eq_delay_array - Array of "num_eq" timer delays in units
+ * of microseconds. The be_eq_query_delay_range
+ * ioctl returns the resolution and range of
+ * legal EQ delays.
+ * callback -
+ * callback_context -
+ * queue_context - Optional. Pointer to a previously allocated
+ * struct. If the MCC WRB ring is full, this
+ * structure is used to queue the operation. It
+ * will be posted to the MCC ring when space
+ * becomes available. All queued commands will
+ * be posted to the ring in the order they are
+ * received. It is always valid to pass a pointer to
+ * a generic BE_GENERIC_QUEUE_CONTEXT. However,
+ * the specific context structs
+ * are generally smaller than the generic struct.
+ * return pend_status - BE_SUCCESS (0) on success.
+ * BE_PENDING (postive value) if the IOCTL
+ * completion is pending. Negative error code on failure.
+ *-------------------------------------------------------------------------
+ */
+BESTATUS
+be_eq_modify_delay(IN PBE_FUNCTION_OBJECT function_object,
+ IN u32 num_eq,
+ IN BE_EQ_OBJECT **eq_array,
+ IN u32 *eq_delay_array,
+ IN MCC_WRB_CQE_CALLBACK callback,
+ IN PVOID callback_context,
+ IN PBE_EQ_MODIFY_DELAY_QUEUE_CONTEXT queue_context)
+{
+ IOCTL_COMMON_MODIFY_EQ_DELAY *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+ PBE_GENERIC_QUEUE_CONTEXT generic_context = NULL;
+ u32 i;
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ if (queue_context && callback) {
+ wrb = (MCC_WRB *) &queue_context->wrb_header;
+ generic_context = (PBE_GENERIC_QUEUE_CONTEXT)
+ queue_context;
+ generic_context->context.bytes =
+ sizeof(*queue_context);
+ } else {
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_MODIFY_EQ_DELAY);
+
+ ASSERT(num_eq > 0);
+ ASSERT(num_eq <= SA_NUMBER_OF(ioctl->params.request.delay));
+ ioctl->params.request.num_eq = num_eq;
+ for (i = 0; i < num_eq; i++) {
+ ioctl->params.request.delay[i].eq_id =
+ be_eq_get_id(eq_array[i]);
+ ioctl->params.request.delay[i].delay_in_microseconds =
+ eq_delay_array[i];
+ }
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb_with_queue_context(function_object,
+ wrb,
+ generic_context,
+ callback,
+ callback_context,
+ ioctl);
+
+Error:
+ be_unlock_wrb_post(function_object);
+
+ return status;
+
+}
+
+/*
+ *--------------------------------------------------------------------------
+ * Function: be_eq_query_delay_range
+ * Queries the resolution and range allowed for EQ delay.
+ * This is a constant set by the firmware, so it may be queried
+ * one time at system boot. It is the same for all EQs.
+ * This is a synchronous IOCTL.
+ * function_object - Previously created function object
+ * eq_delay_resolution - Resolution of EQ delay in microseconds.
+ * eq_delay_max - Max value of EQ delay in microseconds.
+ * return status - BE_SUCCESS (0) on success. Negative
+ * error code on failure.
+ *--------------------------------------------------------------------------
+ */
+BESTATUS
+be_eq_query_delay_range(IN PBE_FUNCTION_OBJECT function_object,
+ OUT u32 *eq_delay_resolution,
+ OUT u32 *eq_delay_max)
+{
+ IOCTL_COMMON_MODIFY_EQ_DELAY *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ BESTATUS status = 0;
+
+ FUNCTION_ASSERT(function_object);
+
+ ASSERT(eq_delay_resolution);
+ ASSERT(eq_delay_max);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_MODIFY_EQ_DELAY);
+
+ /* init the context */
+ ioctl->params.request.num_eq = 0;
+
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "Query EQ delay range failed.");
+ goto Error;
+ }
+
+ *eq_delay_resolution =
+ ioctl->params.response.delay_resolution_in_microseconds;
+ *eq_delay_max = ioctl->params.response.delay_max_in_microseconds;
+
+ TRACE(DL_INFO, "eq delay. function:%d pd:%d resolution:%d max:%d",
+ be_function_get_function_number(function_object),
+ be_function_get_pd_number(function_object),
+ *eq_delay_resolution, *eq_delay_max);
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/cq_ll.c benet/linux-2.6.24.2/drivers/message/beclib/cq_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/cq_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/cq_ll.c 2008-02-14 15:23:07.810205432 +0530
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*
+ * Completion Queue Objects
+ */
+
+/*!
+@brief
+ This routines searches for a CqId that is bound to a
+ specified function object.
+@param
+ function_object - function object the CQ should be bound to.
+@param
+ cq_id - cq_id to find
+@return
+ A pointer to the CQ_OBJECT that represents this CqId. NULL if not found
+@note
+ IRQL: <= DISPATCH_LEVEL
+*/
+STATIC
+ INLINE
+ PBE_CQ_OBJECT
+be_cq_id_to_object(PBE_FUNCTION_OBJECT function_object, u32 cq_id)
+{
+ PBE_CQ_OBJECT cq_cur;
+ PBE_CQ_OBJECT cq_ret = NULL;
+
+ _be_function_lock(function_object);
+
+ SA_FOR_EACH_LIST_ENTRY(cq_cur, function_object->links.cq_list_head,
+ BE_CQ_OBJECT, cq_list) {
+ if (be_cq_get_id(cq_cur) == cq_id) {
+
+ cq_ret = cq_cur;
+ break;
+ }
+ }
+
+ _be_function_unlock(function_object);
+
+ if (!cq_ret) {
+ TRACE(DL_ERR, "Failed to locate cq_id:%d for processing.",
+ cq_id);
+ }
+
+ return cq_ret;
+}
+
+/*
+ *============================================================================
+ * P U B L I C R O U T I N E S
+ *============================================================================
+ */
+
+/*!
+
+@brief
+ This routine creates a completion queue based on the client completion
+ queue configuration information.
+
+
+@param
+ FunctionObject - Handle to a function object
+@param
+ CqBaseVa - Base VA for a the CQ ring
+@param
+ NumEntries - CEV_CQ_CNT_* values
+@param
+ solEventEnable - 0 = All CQEs can generate Events if CQ is eventable
+ 1 = only CQEs with solicited bit set are eventable
+@param
+ eventable - Eventable CQ, generates interrupts.
+@param
+ nodelay - 1 = Force interrupt, relevent if CQ eventable.
+ Interrupt is asserted immediately after EQE
+ write is confirmed, regardless of EQ Timer
+ or watermark settings.
+@param
+ wme - Enable watermark based coalescing
+@param
+ wmThresh - High watermark(CQ fullness at which event
+ or interrupt should be asserted). These are the
+ CEV_WATERMARK encoded values.
+@param
+ EqObject - EQ Handle to assign to this CQ
+@param
+ ppCqObject - Internal CQ Handle returned.
+
+@return
+ BE_SUCCESS if successfull, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+BESTATUS be_cq_create(PBE_FUNCTION_OBJECT function_object,
+ PSA_SGL sgl, u32 length, boolean solicited_eventable,
+ boolean no_delay, u32 wm_thresh,
+ PBE_EQ_OBJECT eq_object, OUT PBE_CQ_OBJECT cq_object)
+{
+ BESTATUS status = BE_SUCCESS;
+ u32 num_entries_encoding;
+ u32 num_entries = length / sizeof(ISCSI_CQ_ENTRY);
+ IOCTL_COMMON_CQ_CREATE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+
+ ASSERT(sgl);
+ ASSERT(cq_object);
+ ASSERT(length % sizeof(ISCSI_CQ_ENTRY) == 0);
+
+ FUNCTION_ASSERT(function_object);
+
+ switch (num_entries) {
+ case 256:
+ num_entries_encoding = CEV_CQ_CNT_256;
+ break;
+ case 512:
+ num_entries_encoding = CEV_CQ_CNT_512;
+ break;
+ case 1024:
+ num_entries_encoding = CEV_CQ_CNT_1024;
+ break;
+ default:
+ ASSERT(0);
+ return BE_STATUS_INVALID_PARAMETER;
+ }
+
+ /*
+ * All cq entries all the same size. Use iSCSI version
+ * as a test for the proper sgl length.
+ */
+ sa_zero_mem(cq_object, sizeof(*cq_object));
+
+ cq_object->magic = BE_CQ_MAGIC;
+ cq_object->ref_count = 0;
+ cq_object->parent_function = function_object;
+ cq_object->eq_object = eq_object;
+ cq_object->num_entries = num_entries;
+ /* save for MCC cq processing */
+ cq_object->va = sa_sgl_get_base_va(sgl);
+
+ /* map into UT. */
+ length = num_entries * sizeof(ISCSI_CQ_ENTRY);
+
+ be_lock_wrb_post(function_object);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in create EQ.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto Error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_CQ_CREATE);
+
+ ioctl->params.request.num_pages =
+ SA_PAGES_SPANNED(sa_sgl_get_offset(sgl), length);
+
+ /* context */
+ ioctl->params.request.context.valid = TRUE;
+ ioctl->params.request.context.Func =
+ be_function_get_function_number(function_object);
+ ioctl->params.request.context.Eventable = (eq_object != NULL);
+ ioctl->params.request.context.Armed = TRUE;
+ ioctl->params.request.context.EQID =
+ eq_object ? eq_object->eq_id : 0;
+ ioctl->params.request.context.Count = num_entries_encoding;
+ ioctl->params.request.context.PD =
+ be_function_get_pd_number(function_object);
+ ioctl->params.request.context.NoDelay = no_delay;
+ ioctl->params.request.context.SolEvent = solicited_eventable;
+ ioctl->params.request.context.WME = (wm_thresh != 0xFFFFFFFF);
+ ioctl->params.request.context.Watermark =
+ (ioctl->params.request.context.WME ? wm_thresh : 0);
+
+ /* Create a page list for the IOCTL. */
+ be_sgl_to_pa_list(sgl,
+ ioctl->params.request.pages,
+ SA_NUMBER_OF(ioctl->params.request.pages));
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "MCC to create CQ failed.");
+ goto Error;
+ }
+ /* Remember the CQ id. */
+ cq_object->cq_id = ioctl->params.response.cq_id;
+
+ /* insert this cq into eq_object reference */
+ if (eq_object) {
+ _be_eq_add_cq(eq_object, cq_object);
+ }
+ /* insert this cq into function_object */
+ _be_function_add_cq(function_object, cq_object);
+
+ TRACE(DL_INFO,
+ "cq created. function:%d pd:%d cqid:%d bytes:%d eqid:%d"
+ " se:%d nd:%d wm:%d",
+ be_function_get_function_number(function_object),
+ be_function_get_pd_number(function_object), cq_object->cq_id,
+ num_entries * sizeof(ISCSI_CQ_ENTRY),
+ eq_object ? be_eq_get_id(eq_object) : -1,
+ (u32) solicited_eventable, (u32) no_delay, wm_thresh);
+
+Error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+/*!
+
+@brief
+ Returns the CQ ID for CQ. This is the ID the chip references the queue as.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@return
+ CQ ID
+@note
+ IRQL: any
+
+*/
+u32 be_cq_get_id(PBE_CQ_OBJECT cq_object)
+{
+ CQ_ASSERT(cq_object);
+ return cq_object->cq_id;
+}
+
+/*!
+
+@brief
+ Sets the current callback to be invoked when a CQ entry is made available.
+ This need only be set if the owner of this CQ does not recieve the CQ
+ completions directly. i.e. it does not service interrupts.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@param
+ callback - function to invoke when the CQ needs processing.
+
+@param
+ context - opaque context to pass to callback.
+
+@return
+ ptr to the previous callback.
+
+@note
+ IRQL: any
+
+ this routine is currently not synchronized w/ the DPC that may run the CQ.
+ therefore it is the callers responsibility to ensure the CQ will not
+ interrupt while this routine is executing.
+*/
+CQ_CALLBACK
+be_cq_object_set_callback(PBE_CQ_OBJECT cq_object,
+ CQ_CALLBACK callback, PVOID context)
+{
+ CQ_CALLBACK old_callback;
+
+ CQ_ASSERT(cq_object);
+
+ old_callback = cq_object->callback;
+
+ cq_object->callback = callback;
+ cq_object->callback_context = context;
+
+ return old_callback;
+}
+
+/*!
+
+@brief
+ This routine handles CQ processing on CQs that were 'unrecognized' by upper
+ level drivers. The only CQs that should be processed by this routine are
+ MCC CQ and iWARP CQ and of these, only the MCC CQ will be processed
+ in this routine. The iWARP CQ will be delegated further for handling
+ by the iWARP device driver
+
+@param
+ function_object - handle to a function object
+@param
+ cq_id - the cq that has just completed processing
+
+@return
+
+
+@note
+ IRQL: DISPATCH_LEVEL only
+
+ this routine should be called immediately when a CQ from a ULD is not
+ recognized.
+*/
+void
+be_cq_object_delegate_processing(PBE_FUNCTION_OBJECT function_object,
+ u32 cq_id)
+{
+ PBE_CQ_OBJECT cq_object;
+
+ FUNCTION_ASSERT(function_object);
+
+ cq_object = be_cq_id_to_object(function_object, cq_id);
+
+ if (cq_object) {
+
+ ASSERT(cq_object->callback);
+ cq_object->callback(function_object, cq_object,
+ cq_object->callback_context);
+
+ } else {
+
+ TRACE(DL_WARN, "cq_id %d not found for delegation", cq_id);
+ }
+
+}
+
+/*!
+
+@brief
+ References the given object. The object is guaranteed to remain active until
+ the reference count drops to zero.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: any
+
+*/
+u32 be_cq_object_reference(PBE_CQ_OBJECT cq_object)
+{
+ CQ_ASSERT(cq_object);
+ return sa_atomic_increment(&cq_object->ref_count);
+}
+
+/*!
+
+@brief
+ Dereferences the given object. The object is guaranteed to
+ remain active until the reference count drops to zero.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: any
+
+*/
+u32 be_cq_object_dereference(PBE_CQ_OBJECT cq_object)
+{
+ CQ_ASSERT(cq_object);
+ return sa_atomic_decrement(&cq_object->ref_count);
+}
+
+/*!
+
+@brief
+ Deferences the given object. Once the object's reference count drops to
+ zero, the object is destroyed and all resources that are held by this object
+ are released. The on-chip context is also destroyed along with the queue
+ ID, and any mappings made into the UT.
+
+@param
+ cq_object - CQ handle returned from cq_object_create.
+
+@return
+ returns the current reference count on the object
+
+@note
+ IRQL: IRQL < DISPATCH_LEVEL
+*/
+BESTATUS be_cq_destroy(PBE_CQ_OBJECT cq_object)
+{
+ BESTATUS status = 0;
+
+ CQ_ASSERT(cq_object);
+ FUNCTION_ASSERT(cq_object->parent_function);
+
+ /* Nothing should reference this CQ at this point. */
+ ASSERT(cq_object->ref_count == 0);
+
+ /* Send ioctl to destroy the CQ. */
+ status =
+ be_function_ring_destroy(cq_object->parent_function,
+ cq_object->cq_id, IOCTL_RING_TYPE_CQ);
+ ASSERT(status == 0);
+
+ /* Remove reference if this is an eventable CQ. */
+ if (cq_object->eq_object)
+ _be_eq_remove_cq(cq_object->eq_object, cq_object);
+
+ /* Remove from the function object. */
+ _be_function_remove_cq(cq_object->parent_function, cq_object);
+
+ /* Zero the software tracking object. */
+ sa_zero_mem(cq_object, sizeof(*cq_object));
+
+ return BE_SUCCESS;
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/mpu_ll.c benet/linux-2.6.24.2/drivers/message/beclib/mpu_ll.c
--- orig/linux-2.6.24.2/drivers/message/beclib/mpu_ll.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/mpu_ll.c 2008-02-14 15:32:53.337191800 +0530
@@ -0,0 +1,1559 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ *
+ */
+#include "pch.h"
+
+/*
+ *============================================================================
+ * F I L E S C O P E
+ *============================================================================
+ */
+
+void
+_be_mcc_free_wrb_buffers(PBE_MCC_OBJECT mcc,
+ PBE_MCC_WRB_CONTEXT wrb_context);
+
+/*!
+
+@brief
+ This routine converts from a BladeEngine Mcc wrb completion status to
+ a standard NT status;
+
+@param
+ MccStatus - BE Mcc WRB completion status to convert
+
+@return
+ An NT status
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+STATIC BESTATUS be_mcc_wrb_status_to_bestatus(IN u32 mcc_status)
+{
+ /* TODO -- Fix this if we want better status codes. */
+ switch (mcc_status) {
+ case MGMT_STATUS_SUCCESS:
+ return SA_SUCCESS;
+ default:
+ return BE_NOT_OK;
+ }
+}
+
+/*!
+@brief
+ This routine waits for a previously posted mailbox WRB to be completed.
+ Specifically it waits for the mailbox to say that it's ready to accept
+ more data by setting the LSB of the mailbox pd register to 1.
+
+@param
+ pcontroller - The function object to post this data to
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+*/
+STATIC void be_mcc_mailbox_wait(IN PBE_FUNCTION_OBJECT function_object)
+{
+ MPU_MAILBOX_DB mailbox_db;
+ u32 i = 0;
+ u32 tl;
+
+ FUNCTION_ASSERT(function_object);
+
+ if (function_object->emulate) {
+ /* No waiting for mailbox in emulated mode. */
+ return;
+ }
+
+ mailbox_db.dw = PD_READ(function_object, mcc_bootstrap_db);
+
+ tl = sa_trace_set_level(sa_trace_get_level() & ~DL_HW);
+ while (mailbox_db.ready == FALSE) {
+ if ((++i & 0x3FFFF) == 0) {
+ TRACE(DL_WARN,
+ "Waiting for mailbox ready for %dk polls.",
+ i / 1000);
+ }
+
+ sa_dev_stall(function_object->sa_dev, 1);
+
+ mailbox_db.dw = PD_READ(function_object, mcc_bootstrap_db);
+ }
+ sa_trace_set_level(tl);
+
+}
+
+/*!
+
+@brief
+ This routine tells the MCC mailbox that there is data to processed
+ in the mailbox. It does this by setting the physical address for the
+ mailbox location and clearing the LSB. This routine returns immediately
+ and does not wait for the WRB to be processed.
+
+
+@param
+ pcontroller - The function object to post this data to
+
+@return
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+STATIC void be_mcc_mailbox_notify(IN PBE_FUNCTION_OBJECT function_object)
+{
+ MPU_MAILBOX_DB mailbox_db;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(function_object->mailbox.pa);
+ ASSERT(function_object->mailbox.va);
+
+ /* If emulated, do not ring the mailbox */
+ if (function_object->emulate) {
+ TRACE(DL_WARN, "MPU disabled. Skipping mailbox notify.");
+ return;
+ }
+
+ function_object->stats.mailbox_wrbs++;
+
+ /* form the higher bits in the address */
+ mailbox_db.dw = 0; /* init */
+ mailbox_db.hi = 1;
+ mailbox_db.ready = 0;
+ SA_C_ASSERT(BE_BIT_SIZE(MPU_MAILBOX_DB, address) == 30);
+ mailbox_db.address =
+ (u32) sa_upper_bits64(function_object->mailbox.pa, 30);
+
+ /* Wait for the MPU to be ready */
+ be_mcc_mailbox_wait(function_object);
+
+ /* Ring doorbell 1st time */
+ PD_WRITE(function_object, mcc_bootstrap_db, mailbox_db);
+
+ /* Wait for 1st write to be acknowledged. */
+ be_mcc_mailbox_wait(function_object);
+
+ /* form the lower bits in the address */
+ mailbox_db.hi = 0;
+ mailbox_db.ready = 0;
+ mailbox_db.address =
+ (u32) sa_bit_range64(function_object->mailbox.pa, 4, 30);
+
+ /* Ring doorbell 2nd time */
+ PD_WRITE(function_object, mcc_bootstrap_db, mailbox_db);
+}
+
+/*!
+@brief
+ This routine tells the MCC mailbox that there is data to processed
+ in the mailbox. It does this by setting the physical address for the
+ mailbox location and clearing the LSB. This routine spins until the
+ MPU writes a 1 into the LSB indicating that the data has been received
+ and is ready to be processed.
+
+@param
+ pcontroller - The function object to post this data to
+@return
+@note
+ IRQL < DISPATCH_LEVEL
+*/
+STATIC
+ void
+be_mcc_mailbox_notify_and_wait(IN PBE_FUNCTION_OBJECT function_object)
+{
+ /*
+ * Notify it
+ */
+ be_mcc_mailbox_notify(function_object);
+
+ /*
+ * Now wait for completion of WRB
+ */
+ be_mcc_mailbox_wait(function_object);
+}
+
+void
+be_mcc_process_cqe(PBE_FUNCTION_OBJECT function_object, PMCC_CQ_ENTRY cqe)
+{
+
+ PBE_MCC_WRB_CONTEXT wrb_context = NULL;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(cqe);
+
+ /*
+ * A command completed. Commands complete out-of-order.
+ * Determine which command completed from the TAG.
+ */
+ SA_C_ASSERT(sizeof(cqe->mcc_tag) >= sizeof(u64));
+ wrb_context =
+ (PBE_MCC_WRB_CONTEXT) SA_U64_TO_PTR(*((u64 *) cqe->mcc_tag));
+
+ ASSERT(wrb_context);
+
+#ifdef SA_DEBUG
+ /*
+ * Assert that at least one WRB was consumed since we posted this one.
+ * If this assert fires, it indicates that a WRB was completed
+ * before it was consumed.
+ */
+ if (wrb_context->ring_wrb) {
+ ASSERT(C_GT
+ (function_object->stats.consumed_wrbs,
+ wrb_context->consumed_count));
+ }
+#endif
+
+ /*
+ * Perform a response copy if requested.
+ * Only copy data if the IOCTL is successful.
+ */
+ if (cqe->completion_status == MGMT_STATUS_SUCCESS &&
+ wrb_context->copy.length > 0) {
+ ASSERT(wrb_context->wrb);
+ ASSERT(wrb_context->wrb->embedded);
+ ASSERT(wrb_context->copy.va);
+ ASSERT(wrb_context->copy.ioctl_offset +
+ wrb_context->copy.length <= SA_SIZEOF_FIELD(MCC_WRB,
+ payload));
+ sa_memcpy(wrb_context->copy.va,
+ (u8 *) &wrb_context->wrb->payload +
+ wrb_context->copy.ioctl_offset,
+ wrb_context->copy.length);
+ }
+
+ /* internal callback */
+ if (wrb_context->internal_callback) {
+ wrb_context->internal_callback(wrb_context->
+ internal_callback_context,
+ be_mcc_wrb_status_to_bestatus
+ (cqe->completion_status),
+ wrb_context->wrb);
+ }
+
+ /* callback */
+ if (wrb_context->callback) {
+ wrb_context->callback(wrb_context->callback_context,
+ be_mcc_wrb_status_to_bestatus(cqe->completion_status),
+ wrb_context->wrb);
+ }
+ /* Free the context structure */
+ _be_mcc_free_wrb_context(function_object, wrb_context);
+}
+
+void be_drive_mcc_wrb_queue(IN PBE_MCC_OBJECT mcc)
+{
+ PBE_FUNCTION_OBJECT function_object = NULL;
+ BESTATUS status = BE_PENDING;
+ PBE_GENERIC_QUEUE_CONTEXT queue_context;
+ PSA_LIST_ENTRY entry;
+ MCC_WRB *wrb;
+ MCC_WRB *queue_wrb;
+ u32 length;
+
+ MCC_ASSERT(mcc);
+
+ function_object = mcc->parent_function;
+
+ be_lock_wrb_post(function_object);
+
+ if (mcc->driving_backlog) {
+ be_unlock_wrb_post(function_object);
+ return;
+ }
+ /* Acquire the flag to limit 1 thread to redrive posts. */
+ mcc->driving_backlog = 1;
+
+ while (!sa_is_list_empty(&mcc->backlog)) {
+
+ wrb = _be_mpu_peek_ring_wrb(mcc, TRUE); /* Driving the queue */
+ if (!wrb) {
+ break; /* No space in the ring yet. */
+ }
+ /* Get the next queued entry to process. */
+ entry = sa_remove_head_list(&mcc->backlog);
+ ASSERT(entry);
+ queue_context =
+ SA_CONTAINING_RECORD(entry, BE_GENERIC_QUEUE_CONTEXT,
+ context.list);
+ function_object->links.mcc->backlog_length--;
+
+ /*
+ * Compute the required length of the WRB.
+ * Since the queue element may be smaller than
+ * the complete WRB, copy only the required number of bytes.
+ */
+ queue_wrb = (MCC_WRB *) &queue_context->wrb_header;
+ if (queue_wrb->embedded) {
+ length =
+ sizeof(BE_MCC_WRB_HEADER) +
+ queue_wrb->payload_length;
+ } else {
+ ASSERT(queue_wrb->sge_count == 1); /* only 1 frag. */
+ length = sizeof(BE_MCC_WRB_HEADER) +
+ queue_wrb->sge_count * sizeof(MCC_SGE);
+ }
+
+ /*
+ * Truncate the length based on the size of the
+ * queue element. Some elements that have output parameters
+ * can be smaller than the payload_length field would
+ * indicate. We really only need to copy the request
+ * parameters, not the response.
+ */
+ ASSERT(queue_context->context.bytes >=
+ SA_FIELD_OFFSET(BE_GENERIC_QUEUE_CONTEXT,
+ wrb_header));
+ length =
+ MIN(length,
+ queue_context->context.bytes -
+ SA_FIELD_OFFSET(BE_GENERIC_QUEUE_CONTEXT,
+ wrb_header));
+
+ /* Copy the queue element WRB into the ring. */
+ sa_memcpy(wrb, &queue_context->wrb_header, length);
+
+ /* Post the wrb. This should not fail assuming we have
+ * enough context structs. */
+ status = be_function_post_mcc_wrb_complete(function_object,
+ wrb, NULL, /* Do not queue */
+ queue_context->context.
+ callback,
+ queue_context->context.
+ callback_context,
+ queue_context->context.
+ internal_callback,
+ queue_context->context.
+ internal_callback_context,
+ queue_context->context.
+ optional_ioctl_va,
+ queue_context->context.copy);
+
+ if (status == BE_SUCCESS) {
+
+ /*
+ * Synchronous completion. Since it was queued,
+ * we will invoke the callback.
+ * To the user, this is an asynchronous request.
+ */
+ be_unlock_wrb_post(function_object);
+
+ ASSERT(queue_context->context.callback);
+
+ queue_context->context.callback(queue_context->context.
+ callback_context,
+ BE_SUCCESS, NULL);
+
+ be_lock_wrb_post(function_object);
+
+ } else if (status != BE_PENDING) {
+ /*
+ * Another resource failed. Should never happen
+ * if we have sufficient MCC_WRB_CONTEXT structs.
+ * Return to head of the queue.
+ */
+ TRACE(DL_WARN,
+ "beclib : failed to post a queued WRB. 0x%x",
+ status);
+ sa_insert_head_list(&mcc->backlog,
+ &queue_context->context.list);
+ function_object->links.mcc->backlog_length++;
+ break;
+ }
+ }
+
+ function_object->stats.queue_length =
+ function_object->links.mcc->backlog_length;
+
+ /* Free the flag to limit 1 thread to redrive posts. */
+ mcc->driving_backlog = 0;
+
+ be_unlock_wrb_post(function_object);
+}
+
+/* This function asserts that the WRB was consumed in order. */
+#ifdef SA_DEBUG
+u32 be_mcc_wrb_consumed_in_order(PBE_MCC_OBJECT mcc, PMCC_CQ_ENTRY cqe)
+{
+ PBE_FUNCTION_OBJECT function_object = mcc->parent_function;
+ PBE_MCC_WRB_CONTEXT wrb_context = NULL;
+ u32 wrb_index;
+ u32 wrb_consumed_in_order;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(cqe);
+
+ /*
+ * A command completed. Commands complete out-of-order.
+ * Determine which command completed from the TAG.
+ */
+ SA_C_ASSERT(sizeof(cqe->mcc_tag) >= sizeof(u64));
+ wrb_context =
+ (PBE_MCC_WRB_CONTEXT) SA_U64_TO_PTR(*((u64 *) cqe->mcc_tag));
+
+ ASSERT(wrb_context);
+
+ wrb_index =
+ (u32) (((SA_PTR_TO_U64(wrb_context->ring_wrb) -
+ SA_PTR_TO_U64(mcc->sq.ring.va))) / sizeof(MCC_WRB));
+ ASSERT(wrb_index < sa_ring_num(&mcc->sq.ring));
+
+ wrb_consumed_in_order = (u32) (wrb_index == mcc->consumed_index);
+ mcc->consumed_index =
+ sa_addc(mcc->consumed_index, 1, sa_ring_num(&mcc->sq.ring));
+
+ return wrb_consumed_in_order;
+}
+#endif
+
+BESTATUS be_mcc_process_cq(IN PBE_MCC_OBJECT mcc, IN boolean rearm)
+{
+ PBE_FUNCTION_OBJECT function_object = NULL;
+ PMCC_CQ_ENTRY cqe;
+ CQ_DB db;
+ PSA_RING cq_ring = &mcc->cq.ring;
+ PSA_RING mcc_ring = &mcc->sq.ring;
+ u32 num_processed = 0;
+ u32 consumed = 0;
+
+ function_object = mcc->parent_function;
+ FUNCTION_ASSERT(function_object);
+
+ be_lock_cq_process(function_object);
+
+ function_object->stats.processed_cq++;
+
+ /*
+ * Verify that only one thread is processing the CQ at once.
+ * We cannot hold the lock while processing the CQ due to
+ * the callbacks into the OS. Therefore, this flag is used
+ * to control it. If any of the threads want to
+ * rearm the CQ, we need to honor that.
+ */
+ if (mcc->processing != 0) {
+ mcc->rearm = mcc->rearm || rearm;
+ goto Error;
+ } else {
+ mcc->processing = 1; /* lock processing for this thread. */
+ mcc->rearm = rearm; /* set our rearm setting */
+ }
+
+ be_unlock_cq_process(function_object);
+
+ cqe = sa_ring_current(cq_ring);
+ while (cqe->valid) {
+
+ function_object->stats.cq_entries++;
+
+ if (num_processed >= 8) {
+ /* coalesce doorbells, but free space in cq
+ * ring while processing. */
+ db.dw = 0; /* clear */
+ db.qid = cq_ring->id;
+ db.rearm = FALSE; /* Rearm at the end! */
+ db.event = FALSE;
+ db.num_popped = num_processed;
+ num_processed = 0;
+
+ PD_WRITE(function_object, cq_db, db);
+ }
+
+ if (cqe->async_event) {
+ /* This is an asynchronous event. */
+ ASYNC_EVENT_TRAILER *async_trailer =
+ (ASYNC_EVENT_TRAILER *)
+ ((u8 *) cqe + sizeof(MCC_CQ_ENTRY) -
+ sizeof(ASYNC_EVENT_TRAILER));
+
+ /* The async_event bit must be in the same
+ * location in both structs. */
+ SA_C_ASSERT(BE_WORD_OFFSET
+ (MCC_CQ_ENTRY,
+ async_event) * 32 +
+ BE_BIT_OFFSET(MCC_CQ_ENTRY,
+ async_event) ==
+ BE_BIT_OFFSET(ASYNC_EVENT_TRAILER,
+ async_event) +
+ 8 * (sizeof(MCC_CQ_ENTRY) -
+ sizeof(ASYNC_EVENT_TRAILER)));
+
+ ASSERT(async_trailer->async_event == 1);
+ ASSERT(async_trailer->valid == 1);
+
+ function_object->stats.async_events++;
+
+ /* Call the async event handler if it is installed. */
+ if (mcc->async_callback) {
+ TRACE(DL_INFO,
+ "Async event. Type:0x%x Code:0x%x",
+ async_trailer->event_type,
+ async_trailer->event_code);
+ mcc->async_callback(mcc->async_context,
+ (u32) async_trailer->
+ event_code,
+ (PVOID) cqe);
+ } else {
+ TRACE(DL_WARN,
+ "No async callback for event."
+ " Type:0x%x Code:0x%x",
+ async_trailer->event_type,
+ async_trailer->event_code);
+ function_object->stats.
+ ignored_async_events++;
+ }
+
+ } else {
+ /* This is a completion entry. */
+
+ /* No vm forwarding in this driver. */
+ ASSERT(cqe->hpi_buffer_completion == 0);
+
+ if (cqe->consumed) {
+ /*
+ * A command on the MCC ring was consumed.
+ * Update the consumer index.
+ * These occur in order.
+ */
+ ASSERT(be_mcc_wrb_consumed_in_order
+ (mcc, cqe));
+ consumed++;
+ function_object->stats.consumed_wrbs++;
+ }
+
+ if (cqe->completed) {
+ /* A command completed. Use tag to
+ * determine which command. */
+ be_mcc_process_cqe(function_object, cqe);
+ function_object->stats.completed_wrbs++;
+ }
+ }
+
+ /* Reset the CQE */
+ cqe->valid = FALSE;
+ num_processed++;
+
+ TRACE(DL_IOCTL, " update the cidx now cidx=%x",
+ cq_ring->cidx);
+ /* Update our tracking for the CQ ring. */
+ cqe = sa_ring_next(cq_ring);
+ }
+
+ TRACE(DL_INFO, "num_processed:0x%x, and consumed:0x%x",
+ num_processed, consumed);
+ /*
+ * Grab the CQ lock to synchronize the "rearm" setting for
+ * the doorbell, and for clearing the "processing" flag.
+ */
+ be_lock_cq_process(function_object);
+
+ /*
+ * Rearm the cq. This is done based on the global mcc->rearm
+ * flag which combines the rearm parameter from the current
+ * call to process_cq and any other threads
+ * that tried to process the CQ while this one was active.
+ * This handles the situation where a sync. ioctl was processing
+ * the CQ while the interrupt/dpc tries to process it.
+ * The sync process gets to continue -- but it is now
+ * responsible for the rearming.
+ */
+ if (num_processed > 0 || mcc->rearm == TRUE) {
+ db.dw = 0; /* clear */
+ db.qid = cq_ring->id;
+ db.rearm = mcc->rearm;
+ db.event = FALSE;
+ db.num_popped = num_processed;
+
+ PD_WRITE(function_object, cq_db, db);
+ }
+ /*
+ * Update the consumer index after ringing the CQ doorbell.
+ * We don't want another thread to post more WRBs before we
+ * have CQ space available.
+ */
+ sa_ring_consume_multiple(mcc_ring, consumed);
+
+ /* Clear the processing flag. */
+ mcc->processing = 0;
+
+Error:
+
+ be_unlock_cq_process(function_object);
+
+ /*
+ * Use the local variable to detect if the current thread
+ * holds the WRB post lock. If rearm is FALSE, this is
+ * either a synchronous command, or the upper layer driver is polling
+ * from a thread. We do not drive the queue from that
+ * context since the driver may hold the
+ * wrb post lock already.
+ */
+ if (rearm) {
+ be_drive_mcc_wrb_queue(mcc);
+ } else {
+ function_object->pend_queue_driving = 1;
+ }
+
+ return BE_SUCCESS;
+}
+
+/*
+ *============================================================================
+ * P U B L I C R O U T I N E S
+ *============================================================================
+ */
+
+/*!
+
+@brief
+ This routine creates an MCC object. This object contains an MCC send queue
+ and a CQ private to the MCC.
+
+@param
+ pcontroller - Handle to a function object
+
+@param
+ EqObject - EQ object that will be used to dispatch this MCC
+
+@param
+ ppMccObject - Pointer to an internal Mcc Object returned.
+
+@return
+ BE_SUCCESS if successfull,, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+*/
+BESTATUS
+be_mcc_ring_create(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL sgl,
+ IN u32 length,
+ IN PBE_MCC_WRB_CONTEXT context_array,
+ IN u32 num_context_entries,
+ IN PBE_CQ_OBJECT cq, IN PBE_MCC_OBJECT mcc)
+{
+ BESTATUS status = 0;
+
+ IOCTL_COMMON_MCC_CREATE *ioctl = NULL;
+ MCC_WRB *wrb = NULL;
+ u32 num_entries_encoded;
+ PVOID va = NULL;
+ u32 i;
+
+ if (length < sizeof(MCC_WRB) * 2) {
+ TRACE(DL_ERR, "Invalid MCC ring length:%d", length);
+ return BE_NOT_OK;
+ }
+ /*
+ * Reduce the actual ring size to be less than the number
+ * of context entries. This ensures that we run out of
+ * ring WRBs first so the queuing works correctly. We never
+ * queue based on context structs.
+ */
+ if (num_context_entries + 1 < length / sizeof(MCC_WRB) - 1) {
+
+ u32 max_length =
+ (num_context_entries + 2) * sizeof(MCC_WRB);
+
+ length = sa_gt_power2(max_length) / 2;
+ ASSERT(length <= max_length);
+
+ TRACE(DL_WARN,
+ "MCC ring length reduced based on context entries."
+ " length:%d wrbs:%d context_entries:%d",
+ length,
+ length / sizeof(MCC_WRB), num_context_entries);
+ }
+
+ be_lock_wrb_post(function_object);
+
+ num_entries_encoded =
+ be_ring_length_to_encoding(length, sizeof(MCC_WRB));
+
+ /* Init MCC object. */
+ SA_ZERO_MEM(mcc);
+ mcc->magic = BE_MCC_MAGIC;
+ mcc->parent_function = function_object;
+ mcc->cq_object = cq;
+
+ sa_initialize_list_head(&mcc->backlog);
+
+ wrb = be_function_peek_mcc_wrb(function_object);
+ if (!wrb) {
+ ASSERT(wrb);
+ TRACE(DL_ERR, "No free MCC WRBs in create EQ.");
+ status = BE_STATUS_NO_MCC_WRB;
+ goto error;
+ }
+ /* Prepares an embedded ioctl, including request/response sizes. */
+ ioctl =
+ BE_FUNCTION_PREPARE_EMBEDDED_IOCTL(function_object, wrb,
+ COMMON_MCC_CREATE);
+
+ ioctl->params.request.num_pages = sa_ceiling(length, SA_PAGE_SIZE);
+ ASSERT(ioctl->params.request.num_pages <=
+ sa_sgl_get_page_count(sgl));
+
+ /*
+ * Program MCC ring context
+ */
+ ioctl->params.request.context.pdid =
+ be_function_get_pd_number(function_object);
+ ioctl->params.request.context.invalid = FALSE;
+ ioctl->params.request.context.ring_size = num_entries_encoded;
+ ioctl->params.request.context.cq_id = be_cq_get_id(cq);
+
+ /* Create a page list for the IOCTL. */
+ be_sgl_to_pa_list(sgl, ioctl->params.request.pages,
+ SA_NUMBER_OF(ioctl->params.request.pages));
+
+ /* Post the Ioctl */
+ status =
+ be_function_post_mcc_wrb(function_object, wrb, NULL, NULL,
+ ioctl);
+ if (status != BE_SUCCESS) {
+ TRACE(DL_ERR, "MCC to create CQ failed.");
+ goto error;
+ }
+ /*
+ * Create a linked list of context structures
+ */
+ mcc->wrb_context.base = context_array;
+ mcc->wrb_context.num = num_context_entries;
+ sa_initialize_list_head(&mcc->wrb_context.list_head);
+ sa_zero_mem(context_array,
+ sizeof(BE_MCC_WRB_CONTEXT) * num_context_entries);
+ for (i = 0; i < mcc->wrb_context.num; i++) {
+ sa_insert_tail_list(&mcc->wrb_context.list_head,
+ &context_array[i].next);
+ }
+
+ /*
+ *
+ * Create an SA_RING for tracking WRB hw ring
+ */
+ va = sa_sgl_get_base_va(sgl);
+ ASSERT(va);
+ sa_ring_create(&mcc->sq.ring,
+ length / sizeof(MCC_WRB), sizeof(MCC_WRB), va);
+ mcc->sq.ring.id = ioctl->params.response.id; /* save the butler id! */
+
+ /*
+ * Init a SA_RING for tracking the MCC CQ.
+ */
+ ASSERT(cq->va);
+ sa_ring_create(&mcc->cq.ring, cq->num_entries,
+ sizeof(ISCSI_CQ_ENTRY), cq->va);
+ mcc->cq.ring.id = be_cq_get_id(cq);
+
+ /* Force zeroing of CQ. */
+ sa_zero_mem(cq->va, cq->num_entries * sizeof(ISCSI_CQ_ENTRY));
+
+ /* Initialize debug index. */
+ mcc->consumed_index = 0;
+
+ be_cq_object_reference(cq);
+ _be_function_add_mcc(function_object, mcc);
+
+ TRACE(DL_INFO,
+ "MCC ring created. id:%d bytes:%d cq_id:%d cq_entries:%d"
+ " num_context:%d",
+ ioctl->params.response.id,
+ length,
+ be_cq_get_id(cq), cq->num_entries, num_context_entries);
+
+error:
+ be_unlock_wrb_post(function_object);
+ return status;
+}
+
+u32 be_mcc_get_id(PBE_MCC_OBJECT mcc)
+{
+ MCC_ASSERT(mcc);
+ return mcc->sq.ring.id;
+}
+
+/*!
+
+@brief
+ This routine destroys an MCC send queue
+
+@param
+ MccObject - Internal Mcc Object to be destroyed.
+
+@return
+ BE_SUCCESS if successfull,, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL
+
+ The caller of this routine must ensure that no other WRB may be posted
+ until this routine returns.
+
+*/
+BESTATUS be_mcc_ring_destroy(IN PBE_MCC_OBJECT mcc)
+{
+ BESTATUS status = 0;
+
+ MCC_ASSERT(mcc);
+
+ ASSERT(mcc->processing == 0);
+
+ /*
+ * Remove the ring from the function object.
+ * This transitions back to mailbox mode.
+ */
+ _be_function_remove_mcc(mcc->parent_function, mcc);
+
+ /* Send ioctl to destroy the queue. (Using the mailbox.) */
+ status =
+ be_function_ring_destroy(mcc->parent_function, mcc->sq.ring.id,
+ IOCTL_RING_TYPE_MCC);
+ ASSERT(status == 0);
+
+ /* Release the SQ reference to the CQ */
+ be_cq_object_dereference(mcc->cq_object);
+
+ return status;
+}
+
+STATIC void
+mcc_wrb_sync_callback(IN PVOID context,
+ IN BESTATUS completion_status, IN PMCC_WRB wrb)
+{
+ PBE_MCC_WRB_CONTEXT wrb_context = (PBE_MCC_WRB_CONTEXT) context;
+
+ SA_NOT_USED(wrb);
+
+ ASSERT(wrb_context);
+
+ *wrb_context->users_final_status = completion_status;
+}
+
+/*!
+
+@brief
+ This routine posts a command to the MCC send queue
+
+@param
+ MccObject - Internal Mcc Object to be destroyed.
+
+@param
+ wrb - wrb to post.
+
+
+@param
+ CompletionCallback - Address of a callback routine to invoke once the WRB
+ is completed.
+
+@param
+ CompletionCallbackContext - Opaque context to be passed during the call to
+ the CompletionCallback.
+
+@return
+ BE_SUCCESS if successfull,, otherwise a useful error code is returned.
+
+@note
+ IRQL < DISPATCH_LEVEL if CompletionCallback is not NULL
+ IRQL <=DISPATCH_LEVEL if CompletionCallback is NULL
+
+ If this routine is called with CompletionCallback != NULL the
+ call is considered to be asynchronous and will return as soon
+ as the WRB is posted to the MCC with BE_PENDING.
+
+ If CompletionCallback is NULL, then this routine will not return until
+ a completion for this MCC command has been processed.
+ If called at DISPATCH_LEVEL the CompletionCallback must be NULL.
+
+ This routine should only be called if the MPU has been boostraped past
+ mailbox mode.
+
+
+*/
+BESTATUS
+_be_mpu_post_wrb_ring(IN PBE_MCC_OBJECT mcc,
+ IN PMCC_WRB wrb, IN PBE_MCC_WRB_CONTEXT wrb_context)
+{
+
+ PMCC_WRB ring_wrb = NULL;
+ BESTATUS status = BE_PENDING;
+ volatile BESTATUS final_status = BE_PENDING;
+ MCC_WRB_CQE_CALLBACK callback = NULL;
+ MCC_DB mcc_db;
+
+ MCC_ASSERT(mcc);
+ ASSERT(sa_ring_num_empty(&mcc->sq.ring) > 0);
+
+ /*
+ * Input wrb is most likely the next wrb in the ring, since the client
+ * can peek at the address.
+ */
+ ring_wrb = sa_ring_producer_ptr(&mcc->sq.ring);
+ if (wrb != ring_wrb) {
+ /* If not equal, copy it into the ring. */
+ sa_memcpy(ring_wrb, wrb, sizeof(MCC_WRB));
+ }
+ /* Minimal verification of posted WRB. */
+ ASSERT(wrb->embedded || wrb->sge_count > 0);
+
+ SA_DBG_ONLY(wrb_context->ring_wrb = ring_wrb;)
+
+ if (ring_wrb->embedded) {
+ /* embedded commands will have the response within the WRB. */
+ wrb_context->wrb = ring_wrb;
+ } else {
+ /*
+ * non-embedded commands will not have the response
+ * within the WRB, and they may complete out-of-order.
+ * The WRB will not be valid to inspect
+ * during the completion.
+ */
+ wrb_context->wrb = NULL;
+ }
+
+ callback = wrb_context->callback;
+
+ if (callback == NULL) {
+ /* Assign our internal callback if this is a
+ * synchronous call. */
+ wrb_context->callback = mcc_wrb_sync_callback;
+ wrb_context->callback_context = wrb_context;
+ wrb_context->users_final_status = &final_status;
+
+ mcc->parent_function->stats.synchronous_wrbs++;
+ }
+ /* Increment producer index */
+ sa_ring_produce(&mcc->sq.ring);
+
+ mcc_db.dw = 0; /* initialize */
+ mcc_db.rid = mcc->sq.ring.id;
+ mcc_db.numPosted = 1;
+
+ mcc->parent_function->stats.posted_wrbs++;
+
+ PD_WRITE(mcc->parent_function, mpu_mcc_db, mcc_db); /* Ring doorbell */
+ TRACE(DL_INFO, "pidx: %x and cidx: %x.", mcc->sq.ring.pidx,
+ mcc->sq.ring.cidx);
+
+ if (callback == NULL) {
+
+ i32 polls = 0; /* At >= 1 us per poll */
+
+ /* Wait until this command completes, polling the CQ. */
+ do {
+
+ TRACE(DL_INFO,
+ "IOCTL submitted in the poll mode.");
+ /* Do not rearm CQ in this context. */
+ be_mcc_process_cq(mcc, FALSE);
+
+ if (final_status == BE_PENDING) {
+ if ((++polls & 0x7FFFF) == 0) {
+ TRACE(DL_WARN,
+ "Warning : polling MCC CQ for %d"
+ "ms.", polls / 1000);
+ }
+
+ sa_dev_stall(mcc->parent_function->sa_dev, 1);
+ }
+
+ } while (final_status == BE_PENDING);
+
+ status = final_status;
+ }
+
+ return status;
+}
+
+PMCC_WRB
+_be_mpu_peek_ring_wrb(IN PBE_MCC_OBJECT mcc, boolean driving_queue)
+{
+ MCC_ASSERT(mcc);
+
+ /* If we have queued items, do not allow a post to bypass the queue. */
+ if (!driving_queue && !sa_is_list_empty(&mcc->backlog)) {
+ return NULL;
+ }
+
+ if (sa_ring_num_empty(&mcc->sq.ring) <= 0) {
+ return NULL;
+ }
+
+ return (PMCC_WRB) sa_ring_producer_ptr(&mcc->sq.ring);
+}
+
+BESTATUS
+be_mpu_init_mailbox(IN PBE_FUNCTION_OBJECT function_object,
+ IN PSA_SGL mailbox)
+{
+ FUNCTION_ASSERT(function_object);
+ ASSERT(mailbox);
+
+ function_object->mailbox.va = sa_sgl_get_base_va(mailbox);
+ function_object->mailbox.pa =
+ sa_sgl_get_page(mailbox, 0) + sa_sgl_get_offset(mailbox);
+ function_object->mailbox.length =
+ MIN(SA_PAGE_SIZE - sa_sgl_get_offset(mailbox),
+ sa_sgl_get_byte_count(mailbox));
+
+ ASSERT((SA_PTR_TO_U32(function_object->mailbox.va) & 0xf) == 0);
+ ASSERT((SA_PTR_TO_U32(function_object->mailbox.pa) & 0xf) == 0);
+ /*
+ * Issue the WRB to set MPU endianness
+ */
+ {
+ u8 *endian_check = (u8 *) &function_object->mailbox.va->wrb;
+ *endian_check++ = 0xFF; /* byte 0 */
+ *endian_check++ = 0x12; /* byte 1 */
+ *endian_check++ = 0x34; /* byte 2 */
+ *endian_check++ = 0xFF; /* byte 3 */
+ *endian_check++ = 0xFF; /* byte 4 */
+ *endian_check++ = 0x56; /* byte 5 */
+ *endian_check++ = 0x78; /* byte 6 */
+ *endian_check++ = 0xFF; /* byte 7 */
+ }
+
+ be_mcc_mailbox_notify_and_wait(function_object);
+
+ return BE_SUCCESS;
+}
+
+BESTATUS be_mpu_uninit_mailbox(IN PBE_FUNCTION_OBJECT function_object)
+{
+ FUNCTION_ASSERT(function_object);
+ ASSERT(function_object->mailbox.va);
+ ASSERT((SA_PTR_TO_U32(function_object->mailbox.va) & 0xf) == 0);
+ ASSERT((SA_PTR_TO_U32(function_object->mailbox.pa) & 0xf) == 0);
+ /*
+ * Issue the WRB to indicate mailbox teardown
+ */
+ {
+ u8 *mbox_unint = (u8 *) &function_object->mailbox.va->wrb;
+ *mbox_unint++ = 0xFF; /* byte 0 */
+ *mbox_unint++ = 0xAA; /* byte 1 */
+ *mbox_unint++ = 0xBB; /* byte 2 */
+ *mbox_unint++ = 0xFF; /* byte 3 */
+ *mbox_unint++ = 0xFF; /* byte 4 */
+ *mbox_unint++ = 0xCC; /* byte 5 */
+ *mbox_unint++ = 0xDD; /* byte 6 */
+ *mbox_unint++ = 0xFF; /* byte 7 */
+ }
+
+ be_mcc_mailbox_notify_and_wait(function_object);
+
+ return BE_SUCCESS;
+}
+
+void be_mpu_cleanup_mailbox(PBE_FUNCTION_OBJECT function_object)
+{
+
+ FUNCTION_ASSERT(function_object);
+ /*function_object->mailbox.sgl = NULL; */
+ function_object->mailbox.va = NULL;
+ function_object->mailbox.pa = 0ULL;
+ function_object->mailbox.length = 0UL;
+}
+
+/*!
+@brief
+ This routine posts a command to the MCC mailbox.
+@param
+ FuncObj - Function Object to post the WRB on behalf of.
+@param
+ wrb - wrb to post.
+@param
+ CompletionCallback - Address of a callback routine to invoke once the WRB
+ is completed.
+@param
+ CompletionCallbackContext - Opaque context to be passed during the call to
+ the CompletionCallback.
+@return
+ BE_SUCCESS if successfull,, otherwise a useful error code is returned.
+@note
+ IRQL <=DISPATCH_LEVEL if CompletionCallback is NULL
+
+ This routine will block until a completion for this MCC command has been
+ processed. If called at DISPATCH_LEVEL the CompletionCallback must be NULL.
+
+ This routine should only be called if the MPU has not been boostraped past
+ mailbox mode.
+*/
+BESTATUS
+_be_mpu_post_wrb_mailbox(IN PBE_FUNCTION_OBJECT function_object,
+ IN PMCC_WRB wrb,
+ IN PBE_MCC_WRB_CONTEXT wrb_context)
+{
+ PMCC_MAILBOX mailbox = NULL;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(function_object->links.mcc == NULL);
+
+ mailbox = function_object->mailbox.va;
+ ASSERT(mailbox);
+
+ if ((PMCC_WRB) &mailbox->wrb != wrb) {
+ SA_ZERO_MEM(mailbox);
+ sa_memcpy(&mailbox->wrb, wrb, sizeof(MCC_WRB));
+ }
+ /* The callback can inspect the final WRB to get output parameters. */
+ wrb_context->wrb = &mailbox->wrb;
+
+ be_mcc_mailbox_notify_and_wait(function_object);
+
+ /* A command completed. Use tag to determine which command. */
+ be_mcc_process_cqe(function_object, &mailbox->cq);
+
+ return be_mcc_wrb_status_to_bestatus(mailbox->cq.
+ completion_status);
+}
+
+PBE_MCC_WRB_CONTEXT
+_be_mcc_allocate_wrb_context(PBE_FUNCTION_OBJECT function_object)
+{
+ PBE_MCC_WRB_CONTEXT context = NULL;
+ SA_IRQ irq;
+
+ FUNCTION_ASSERT(function_object);
+
+ sa_acquire_spinlock(&function_object->mcc_context_lock, &irq);
+
+ if (!function_object->mailbox.default_context_allocated) {
+ /* Use the single default context that we
+ * always have allocated. */
+ function_object->mailbox.default_context_allocated = TRUE;
+ context = &function_object->mailbox.default_context;
+ } else if (function_object->links.mcc) {
+ /* Get a context from the free list. If any are available. */
+ if (!sa_is_list_empty
+ (&function_object->links.mcc->wrb_context.list_head)) {
+ PSA_LIST_ENTRY list_entry =
+ sa_remove_head_list(&function_object->links.
+ mcc->wrb_context.
+ list_head);
+ context =
+ SA_CONTAINING_RECORD(list_entry,
+ BE_MCC_WRB_CONTEXT, next);
+ }
+ }
+
+ sa_release_spinlock(&function_object->mcc_context_lock, &irq);
+
+ return context;
+}
+
+void
+_be_mcc_free_wrb_context(PBE_FUNCTION_OBJECT function_object,
+ PBE_MCC_WRB_CONTEXT context)
+{
+ SA_IRQ irq;
+
+ FUNCTION_ASSERT(function_object);
+ ASSERT(context);
+
+ /*
+ * Zero during free to try and catch any bugs where the context
+ * is accessed after a free.
+ */
+ sa_zero_mem(context, sizeof(context));
+
+ sa_acquire_spinlock(&function_object->mcc_context_lock, &irq);
+
+ if (context == &function_object->mailbox.default_context) {
+ /* Free the default context. */
+ ASSERT(function_object->mailbox.default_context_allocated);
+ function_object->mailbox.default_context_allocated = FALSE;
+ } else {
+ /* Add to free list. */
+ ASSERT(function_object->links.mcc);
+ sa_insert_tail_list(&function_object->links.mcc->
+ wrb_context.list_head, &context->next);
+ }
+
+ sa_release_spinlock(&function_object->mcc_context_lock, &irq);
+}
+
+BESTATUS
+be_mcc_add_async_event_callback(IN BE_MCC_OBJECT *mcc_object,
+ IN MCC_ASYNC_EVENT_CALLBACK callback,
+ IN PVOID callback_context)
+{
+ MCC_ASSERT(mcc_object);
+
+ /* Lock against anyone trying to change the callback/context pointers
+ * while being used. */
+ be_lock_cq_process(mcc_object->parent_function);
+
+ /* Assign the async callback. */
+ mcc_object->async_context = callback_context;
+ mcc_object->async_callback = callback;
+
+ be_unlock_cq_process(mcc_object->parent_function);
+
+ return BE_SUCCESS;
+}
+
+#define MPU_EP_CONTROL 0
+#define MPU_EP_SEMAPHORE 0xac
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_wait_for_POST_complete
+ * Waits until the BladeEngine POST completes (either in error or success).
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-------------------------------------------------------------------
+ */
+BESTATUS be_wait_for_POST_complete(IN PBE_FUNCTION_OBJECT function_object)
+{
+ MGMT_HBA_POST_STATUS_STRUCT postStatus;
+ BESTATUS status;
+
+ const u32 us_per_loop = 1000; /* 1000us */
+ const u32 print_frequency_loops = 1000000 / us_per_loop;
+ const u32 max_loops = 60 * print_frequency_loops;
+ u32 loops = 0;
+
+ /*
+ * Wait for arm fw indicating it is done or a fatal error happened.
+ * Note: POST can take some time to complete depending on configuration
+ * settings (consider ARM attempts to acquire an IP address
+ * over DHCP!!!).
+ *
+ */
+ do {
+ postStatus.dw =
+ BeCsrRead(function_object->sa_dev, MPU_EP_SEMAPHORE, NULL);
+ if (0 == (loops % print_frequency_loops)) {
+ /* Print current status */
+ TRACE(DL_INFO, "POST status = 0x%x (stage = 0x%x)",
+ postStatus.dw, postStatus.stage);
+ }
+ sa_dev_stall(function_object->sa_dev, us_per_loop);
+ } while ((postStatus.error != 1) &&
+ (postStatus.stage != POST_STAGE_ARMFW_READY) &&
+ (++loops < max_loops));
+
+ if (postStatus.error == 1) {
+ TRACE(DL_ERR, "POST error! Status = 0x%x (stage = 0x%x)",
+ postStatus.dw, postStatus.stage);
+ status = BE_NOT_OK;
+ } else if (postStatus.stage != POST_STAGE_ARMFW_READY) {
+ TRACE(DL_ERR,
+ "POST time-out! Status = 0x%x (stage = 0x%x)",
+ postStatus.dw, postStatus.stage);
+ status = BE_NOT_OK;
+ } else {
+ status = BE_SUCCESS;
+ }
+
+ return status;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_kickoff_and_wait_for_POST
+ * Interacts with the BladeEngine management processor to initiate POST, and
+ * subsequently waits until POST completes (either in error or success).
+ * The caller must acquire the reset semaphore before initiating POST
+ * to prevent multiple drivers interacting with the management processor.
+ * Once POST is complete the caller must release the reset semaphore.
+ * Callers who only want to wait for POST complete may call
+ * be_wait_for_POST_complete.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-------------------------------------------------------------------
+ */
+BESTATUS
+be_kickoff_and_wait_for_POST(IN PBE_FUNCTION_OBJECT function_object)
+{
+ MGMT_HBA_POST_STATUS_STRUCT postStatus;
+ BESTATUS status;
+
+ const u32 us_per_loop = 1000; /* 1000us */
+ const u32 print_frequency_loops = 1000000 / us_per_loop;
+ const u32 max_loops = 5 * print_frequency_loops;
+ u32 loops = 0;
+
+ /* Wait for arm fw awaiting host ready or a fatal error happened. */
+ TRACE(DL_INFO, "Wait for BladeEngine ready to POST");
+ do {
+ postStatus.dw =
+ BeCsrRead(function_object->sa_dev, MPU_EP_SEMAPHORE, NULL);
+ if (0 == (loops % print_frequency_loops)) {
+ /* Print current status */
+ TRACE(DL_INFO, "POST status = 0x%x (stage = 0x%x)",
+ postStatus.dw, postStatus.stage);
+ }
+ sa_dev_stall(function_object->sa_dev, us_per_loop);
+ } while ((postStatus.error != 1) &&
+ (postStatus.stage < POST_STAGE_AWAITING_HOST_RDY) &&
+ (++loops < max_loops));
+
+ if (postStatus.error == 1) {
+ TRACE(DL_ERR,
+ "Pre-POST error! Status = 0x%x (stage = 0x%x)",
+ postStatus.dw, postStatus.stage);
+ status = BE_NOT_OK;
+ } else if (postStatus.stage == POST_STAGE_AWAITING_HOST_RDY) {
+ BeCsrWrite(function_object->sa_dev, MPU_EP_SEMAPHORE,
+ POST_STAGE_HOST_RDY, NULL);
+
+ /* Wait for POST to complete */
+ status = be_wait_for_POST_complete(function_object);
+ } else {
+ /*
+ * Either a timeout waiting for host ready signal or POST has
+ * moved ahead without requiring a host ready signal.
+ * Might as well give POST a chance to complete
+ * (or timeout again).
+ */
+ status = be_wait_for_POST_complete(function_object);
+ }
+
+ return status;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_pci_soft_reset
+ * This function is called to issue a BladeEngine soft reset.
+ * Callers should acquire the soft reset semaphore before calling this
+ * function. Additionaly, callers should ensure they cannot be pre-empted
+ * while the routine executes. Upon completion of this routine, callers
+ * should release the reset semaphore. This routine implicitly waits
+ * for BladeEngine POST to complete.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-------------------------------------------------------------------
+ */
+BESTATUS be_pci_soft_reset(PBE_FUNCTION_OBJECT function_object)
+{
+ PCICFG_SOFT_RESET_CSR pciSoftReset;
+ PCICFG_ONLINE0_CSR pciOnline0;
+ PCICFG_ONLINE1_CSR pciOnline1;
+ EP_CONTROL_CSR epControlCsr;
+ BESTATUS status = BE_SUCCESS;
+ u32 i;
+
+ TRACE(DL_NOTE, "PCI reset...");
+
+ /* Issue soft reset #1 to get BladeEngine into a known state. */
+ pciSoftReset.dw = PCICFG0_READ(function_object, soft_reset);
+ pciSoftReset.softreset = 1;
+ PCICFG0_WRITE(function_object, soft_reset, pciSoftReset);
+
+ /*
+ * wait til soft reset is deasserted - hardware
+ * deasserts after some time.
+ */
+ i = 0;
+ while (pciSoftReset.softreset && (i++ < 1024)) {
+ sa_dev_stall(function_object->sa_dev, 50);
+ pciSoftReset.dw =
+ PCICFG0_READ(function_object, soft_reset);
+ };
+ if (pciSoftReset.softreset != 0) {
+ TRACE(DL_ERR,
+ "Soft-reset #1 did not deassert as expected.");
+ status = BE_NOT_OK;
+ goto Error_label;
+ }
+ /* Mask everything */
+ PCICFG0_WRITE_CONST(function_object, ue_status_low_mask,
+ 0xFFFFFFFF);
+ PCICFG0_WRITE_CONST(function_object, ue_status_hi_mask,
+ 0xFFFFFFFF);
+
+ /*
+ * Set everything offline except MPU IRAM (it is offline with
+ * the soft-reset, but soft-reset does not reset the PCICFG registers!)
+ */
+ pciOnline0.dw = 0;
+ pciOnline1.dw = 0;
+ pciOnline1.mpu_iram_online = 1;
+ PCICFG0_WRITE(function_object, online0, pciOnline0);
+ PCICFG0_WRITE(function_object, online1, pciOnline1);
+
+ sa_dev_stall(function_object->sa_dev, 50000); /* delay 5ms */
+
+ /* Issue soft reset #2. */
+ pciSoftReset.softreset = 1;
+ PCICFG0_WRITE(function_object, soft_reset, pciSoftReset);
+
+ /*
+ * wait til soft reset is deasserted - hardware
+ * deasserts after some time.
+ */
+ i = 0;
+ while (pciSoftReset.softreset && (i++ < 1024)) {
+ sa_dev_stall(function_object->sa_dev, 50);
+ pciSoftReset.dw =
+ PCICFG0_READ(function_object, soft_reset);
+ };
+ if (pciSoftReset.softreset != 0) {
+ TRACE(DL_ERR,
+ "Soft-reset #2 did not deassert as expected.");
+ status = BE_NOT_OK;
+ goto Error_label;
+ }
+
+ sa_dev_stall(function_object->sa_dev, 50000); /* delay 5ms */
+
+ /* Take MPU out of reset. */
+
+ /*epControlCsr.dw = CSR_READ(function_object, mpu.ep.ep_control); */
+ epControlCsr.dw =
+ BeCsrRead(function_object->sa_dev, MPU_EP_CONTROL, NULL);
+ epControlCsr.CPU_reset = 0;
+ /*CSR_WRITE(function_object, mpu.ep.ep_control, epControlCsr); */
+ BeCsrWrite(function_object->sa_dev, MPU_EP_CONTROL,
+ epControlCsr.dw, NULL);
+
+ /* Kickoff BE POST and wait for completion */
+ status = be_kickoff_and_wait_for_POST(function_object);
+
+Error_label:
+ return status;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_acquire_reset_semaphore
+ * Acquires the reset semaphore. If success is returned, the
+ * caller owns the reset semaphore. Otherwise the caller does not
+ * own the reset semaphore. Callers must acquire the reset semaphore
+ * before inducing a BladeEngine runtime reset. Callers must
+ * also release the reset semaphore once they are done with a
+ * soft reset. Release of the reset semaphore is accomplished with
+ * be_release_reset_semaphore.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-------------------------------------------------------------------
+ */
+BESTATUS be_acquire_reset_semaphore(IN PBE_FUNCTION_OBJECT function_object)
+{
+ ASSERT(FALSE == function_object->own_semaphore);
+ if (FALSE == function_object->own_semaphore) {
+ if (0 == PCICFG0_READ(function_object, semaphore[2])) {
+ /* This driver now owns the resource */
+ function_object->own_semaphore = TRUE;
+ return BE_SUCCESS;
+ } else {
+ /* Some other driver owns the resource */
+ return BE_NOT_OK;
+ }
+ }
+
+ return BE_SUCCESS;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_release_reset_semaphore
+ * Releases the reset semaphore. Callers must release the reset
+ * semaphore once they are done with a soft reset.
+ * function_object -
+ * return return_type -
+ *-------------------------------------------------------------------
+ */
+void be_release_reset_semaphore(IN PBE_FUNCTION_OBJECT function_object)
+{
+ ASSERT(TRUE == function_object->own_semaphore);
+
+ if (TRUE == function_object->own_semaphore) {
+ PCICFG0_WRITE_CONST(function_object, semaphore[2], 0);
+ function_object->own_semaphore = FALSE;
+ }
+
+ return;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_pci_reset_required
+ * This private function is called to detect if a host entity is
+ * required to issue a PCI soft reset and subsequently drive
+ * BladeEngine POST. Scenarios where this is required:
+ * 1) BIOS-less configuration
+ * 2) Hot-swap/plug/power-on
+ * function_object -
+ * return TRUE if a reset is required, FALSE otherwise
+ *-------------------------------------------------------------------
+ */
+boolean be_pci_reset_required(IN PBE_FUNCTION_OBJECT function_object)
+{
+ MGMT_HBA_POST_STATUS_STRUCT postStatus;
+ boolean doReset = FALSE;
+
+ /*
+ * Read the POST status register
+ *postStatus.dw = CSR_READ(function_object, mpu.ep.ep_semaphore);
+ */
+ postStatus.dw =
+ BeCsrRead(function_object->sa_dev, MPU_EP_SEMAPHORE, NULL);
+
+ if (postStatus.stage <= POST_STAGE_AWAITING_HOST_RDY) {
+ /*
+ * If BladeEngine is waiting for host ready indication,
+ * we want to do a PCI reset.
+ */
+ doReset = TRUE;
+ }
+
+ return doReset;
+}
+
+/*
+ *-------------------------------------------------------------------
+ * Function: be_drive_POST
+ * This function is called to drive BladeEngine POST. The
+ * caller should ensure they cannot be pre-empted while this routine executes.
+ * function_object -
+ * return status - BE_SUCCESS (0) on success. Negative error code on failure.
+ *-------------------------------------------------------------------
+ */
+BESTATUS be_drive_POST(IN PBE_FUNCTION_OBJECT function_object)
+{
+ BESTATUS status;
+
+ if (FALSE != be_pci_reset_required(function_object)) {
+ /* PCI reset is needed (implicitly starts and waits for POST) */
+ status = be_pci_soft_reset(function_object);
+ } else {
+ /* No PCI reset is needed, start POST */
+ status = be_kickoff_and_wait_for_POST(function_object);
+ }
+
+ return status;
+}
___________________________________________________________________________________
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^ permalink raw reply
* [PATHCH 9/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:43 UTC (permalink / raw)
To: netdev
System abstraction function for Linux. beclib uses these helper routines / macros to do OS dependent functions.
--------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/sa/setypes.h benet/linux-2.6.24.2/drivers/message/beclib/sa/setypes.h
--- orig/linux-2.6.24.2/drivers/message/beclib/sa/setypes.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/sa/setypes.h 2008-02-14 15:23:07.812205128 +0530
@@ -0,0 +1,70 @@
+
+/*
+ * These are the data types used in management apps that we are
+maintaining for
+ * legacy/personal preference reasons.
+ */
+
+#ifndef __setypes_h__
+#define __setypes_h__
+/*
+ *----- data types used in SA ----
+ * Signed integers.
+ */
+typedef signed char i8;
+typedef signed short i16;
+typedef signed int i32;
+typedef signed long long i64;
+
+/* Narrow and wide characters. */
+typedef char c8;
+typedef u16 c16;
+
+/* Native size_t for interfacing to libraries. */ typedef size_t
+SA_SIZE_T, *PSA_SIZE_T;
+
+typedef int boolean;
+
+/* Common pointer to a void notation. */ typedef void *PVOID;
+
+/*
+ * Explicitly sized booleans -- useful for packing a struct while still
+ * indicating that the value is treated as TRUE or FALSE.
+ */
+typedef u8 bool8;
+typedef u16 bool16;
+typedef u32 bool32;
+
+/* Define boolean types if necessary. */ #ifndef TRUE #define TRUE (1)
+#endif
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#if !defined(NULL)
+#define NULL ((void *) 0)
+#endif
+
+/* Physical address definition */
+typedef u64 SA_PHYSICAL_ADDRESS, *PSA_PHYSICAL_ADDRESS;
+
+#define SA_EXTERN_C extern "C"
+#define INLINE inline
+#define STATIC static
+#define SA_STDCALL
+#define STDCALL
+#define SA_CDECL
+#define SA_FASTCALL
+
+#ifndef FASTCALL
+#define FASTCALL
+#endif
+
+#define IN
+#define OUT
+#define INOUT
+
+#endif
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/sa/sa.c benet/linux-2.6.24.2/drivers/message/beclib/sa/sa.c
--- orig/linux-2.6.24.2/drivers/message/beclib/sa/sa.c 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/sa/sa.c 2008-02-14 15:23:07.812205128 +0530
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * system abstraction functions / macros for Linux */ #include "sa.h"
+#include <asm/io.h>
+#include <linux/delay.h>
+
+/* Table lookup for number of bits set in each byte. */
+u8 sa_bits_in_byte_table[256] = {
+ 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4,
+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6,
+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7,
+ 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 };
+
+unsigned int trace_level;
+
+
+SA_STATUS sa_dev_create(SA_DEV_BAR_LOCATIONS *bars, u32 num_bars,
+ SA_DEV_OS_HANDLE os_handle, SA_DEV *dev) {
+ SA_NOT_USED(os_handle); /* Not used in Linux */
+ ASSERT(dev);
+ ASSERT(bars);
+
+ /* Zero the struct */
+ SA_ZERO_MEM(dev);
+
+ /* Copy the bar info */
+ dev->magic = SA_DEV_MAGIC;
+ dev->num_bars = num_bars;
+ sa_memcpy(dev->bars, bars,
+ sizeof(SA_DEV_BAR_LOCATIONS) * num_bars);
+
+ /* Figure out the csr/pd/pci bar numbers. */
+ _sa_cache_bar_nums(dev);
+
+ return SA_SUCCESS;
+}
+
+void sa_dev_destroy(SA_DEV *dev)
+{
+ SA_DEV_ASSERT(dev);
+ SA_ZERO_MEM(dev);
+}
+
+u8 sa_dev_read_u8(SA_DEV *dev, u32 bar, u32 offset) {
+ u8 *real_offset = 0;
+ u8 value = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ value = readb((void *)real_offset);
+ return value;
+}
+
+u16 sa_dev_read_u16(SA_DEV *dev, u32 bar, u32 offset) {
+ u8 *real_offset = 0;
+ u16 value = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ value = readw((void *)real_offset);
+ return value;
+}
+
+u32 sa_dev_read_u32(SA_DEV *dev, u32 bar, u32 offset) {
+ u8 *real_offset = 0;
+ u32 value = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ value = readl((void *)real_offset);
+ return value;
+}
+
+void sa_dev_write_u8(SA_DEV *dev, u32 bar, u32 offset, u8 value) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ writeb(value, (void *)real_offset);
+}
+
+void sa_dev_write_u16(SA_DEV *dev, u32 bar, u32 offset, u16 value) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ writew(value, (void *)real_offset);
+}
+
+void sa_dev_write_u32(SA_DEV *dev, u32 bar, u32 offset, u32 value) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset < dev->bars[bar].length);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ writel(value, (void *)real_offset);
+}
+
+SA_STATUS
+sa_dev_read_buffer_u8(SA_DEV *dev,
+ u32 bar, u32 offset, u8 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_fromio(buffer, (void *)real_offset, count);
+
+ return SA_SUCCESS;
+}
+
+SA_STATUS
+sa_dev_read_buffer_u16(SA_DEV *dev,
+ u32 bar, u32 offset, u16 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count * sizeof(u16) < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_fromio(buffer, (void *)real_offset, count * sizeof(u16));
+
+ return SA_SUCCESS;
+}
+
+SA_STATUS
+dev_read_buffer_u32(SA_DEV *dev,
+ u32 bar, u32 offset, u32 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count * sizeof(u32) < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_fromio(buffer, (void *)real_offset, count * sizeof(u32));
+
+ return SA_SUCCESS;
+}
+
+SA_STATUS
+sa_dev_write_buffer_u8(SA_DEV *dev,
+ u32 bar, u32 offset, u8 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_toio((void *)real_offset, buffer, count);
+
+ return SA_SUCCESS;
+}
+
+SA_STATUS
+sa_dev_write_buffer_u16(SA_DEV *dev,
+ u32 bar, u32 offset, u16 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count * sizeof(u16) < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_toio((void *)real_offset, buffer, count * sizeof(u16));
+
+ return SA_SUCCESS;
+}
+
+SA_STATUS
+sa_dev_write_buffer_u32(SA_DEV *dev,
+ u32 bar, u32 offset, u32 *buffer, u32 count) {
+ u8 *real_offset = 0;
+
+ SA_DEV_ASSERT(dev);
+ ASSERT(bar < dev->num_bars);
+ ASSERT(offset + count * sizeof(u32) < dev->bars[bar].length);
+ ASSERT(count > 0);
+ ASSERT(buffer);
+
+ real_offset = (u8 *) dev->bars[bar].base_va + offset;
+ memcpy_toio((void *)real_offset, buffer, count * sizeof(u32));
+
+ return SA_SUCCESS;
+}
+
+void sa_dev_stall(SA_DEV *dev, u32 us_to_stall) {
+ udelay(us_to_stall);
+}
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/sa/sa.h benet/linux-2.6.24.2/drivers/message/beclib/sa/sa.h
--- orig/linux-2.6.24.2/drivers/message/beclib/sa/sa.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/sa/sa.h 2008-02-14 15:23:07.813204976 +0530
@@ -0,0 +1,1004 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * system abstraction functions / macros for Linux */ #ifndef __sa_h__
+#define __sa_h__
+
+#include <asm/io.h>
+#include <linux/list.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <asm/semaphore.h>
+
+/*----- Platform specific defines for Linux -------*/ #define SA_OS
+"linux"
+#define SA_LINUX
+
+#define SA_KERNEL
+#define SA_LINUX_KERNEL
+#define SA_LINUXK
+
+#define SA_CPP_HEADER
+#define SA_CPP_TRAILER
+
+/*
+ *--------- Assert related --------
+ * a way to force compilation error
+ */
+#define SA_C_ASSERT(_expression_) { \
+ typedef u8 __COMPILE_TIME_ASSERT_NAME__[(_expression_) ? 1 : -1]; \ }
+
+#ifdef SA_DEBUG
+
+#define ASSERT(c) if (!(c)) \
+ BUG();
+
+#define SA_DBG_CSTR(_str_) (_str_)
+#define SA_DBG_ONLY(_anything_) _anything_
+
+#else
+
+#define ASSERT(c)
+#define BREAKPOINT()
+#define SA_BREAKPOINT_MSG(_str_)
+#define SA_DBG_CSTR(_str_) ""
+#define SA_DBG_ONLY(_anything_)
+
+#endif
+
+#define SA_ASSERT ASSERT
+
+#define SA_COMPILETIME_NAMED_TYPEDEF_ASSERT(_name_, _expression_) \
+ typedef u8 _name_##__COMPILE_TIME_ASSERT__[(_expression_)?1: -1] \
+
+#define SA_GLOBAL_C_ASSERT SA_COMPILETIME_NAMED_TYPEDEF_ASSERT
+
+/*--------- Trace log related --------*/
+
+/* debug levels */
+typedef enum _SA_DEBUG_LEVELS {
+ DL_ALWAYS = 0, /* cannot be masked */
+
+ DL_ERR = 0x1, /* errors that should never happen */
+ DL_WARN = 0x2, /* something is questionable.
+ recoverable errors */
+ DL_NOTE = 0x4, /* infrequent, important debug info */
+ DL_INFO = 0x8, /* debug information */
+
+ DL_VERBOSE = 0x10, /* detailed information, such as
+ buffer traces */
+ DL_ENTRY = 0x20, /* function entry */
+ DL_EXIT = 0x40, /* function exit */
+ DL_RSVD1 = 0x80,
+
+ SA_DL_MIN_VALUE = 0x1, /* this is the min value used */
+ SA_DL_MAX_VALUE = 0x80 /* this is the higheset value used */
+} SA_DEBUG_LEVELS, *PSA_DEBUG_LEVELS;
+
+/* Bit mask describing events of interest to be traced */ extern
+unsigned int trace_level;
+
+#define SA_TRACE(lm, fmt, args...) { \
+ if (trace_level & lm) { \
+ printk(KERN_NOTICE "BE: %s:%d \n" fmt, \
+ __FILE__ , __LINE__ , ## args); \
+ } \
+ }
+
+#define TRACE SA_TRACE
+#define SA_TRACE_ENTRY() SA_TRACE(DL_ENTRY, "Entry - \n")
+#define SA_TRACE_EXIT() SA_TRACE(DL_EXIT , "Exit - \n")
+
+static inline unsigned int sa_trace_set_level(unsigned int l) {
+ unsigned int old_level = trace_level;
+ trace_level = l;
+ return (old_level);
+}
+
+#define sa_trace_get_level() trace_level
+#define sa_trace_set_debug_level_string(lm, s) /* nothing */
+
+#include "setypes.h"
+
+/*----- power of 2 functions -----*/
+static inline u32 sa_required_bits(u32 x) {
+ u32 hi = 31, lo = 0;
+ u32 guess = 16;
+
+ if (x == 0)
+ return 0;
+ if (x & 0x80000000)
+ return 32;
+
+ /* Binary search */
+ while (hi > lo) {
+ if ((x >> guess) > 0) {
+ /* x is more than i bits in length */
+ lo = guess;
+ guess = (hi + guess + 1) >> 1;
+ } else {
+ hi = guess - 1;
+ guess = (lo + guess) >> 1;
+ }
+ }
+
+ return hi + 1;
+}
+
+/*
+ * Returns the log base 2 for a number, always rounding down.
+ * sa_log2 example input->output
+ * 0->4294967295, 1->0, 2->1, 3->1, 4->2, 5->2, 6->2, 7->2, 8->3, 9->3
+*/ static inline u32 sa_log2(u32 x) {
+ return sa_required_bits(x) - 1;
+}
+
+/*
+ * "greater than power of 2"
+ * Returns the next higher power of 2 -- even if input is a power of 2.
+ * input->output
+ * 0->1, 1->2, 2->4, 3->4, 4->8, 5->8, 6->8, 7->8, 8->16, 9->16 */
+static inline u32 sa_gt_power2(u32 x) {
+ x = sa_required_bits(x);
+
+ if (x >= 32)
+ /* error -- cannot represent this number in 32 bits */
+ return (u32) 0xFFFFFFFF;
+
+ return (1 << x);
+}
+
+/*
+ *----- status codes returned by SA functions -----
+ * Status code datatype
+ */
+typedef i32 SA_STATUS, *PSA_STATUS;
+
+/* Error codes */
+#define SA_STATUS_SUCCESS (0x00000000L)
+#define SA_SUCCESS SA_STATUS_SUCCESS /* abbreviation */
+
+#define SA_STATUS_PENDING (0x20070001L)
+#define SA_STATUS_NOT_OK (0xE0070002L)
+#define SA_NOT_OK SA_STATUS_NOT_OK /* abbreviation */
+#define SA_STATUS_NO_SYSTEM_RESOURCES (0xE0070003L)
+#define SA_STATUS_NO_CHIP_RESOURCES (0xE0070004L)
+#define SA_STATUS_BUSY (0xE0070006L)
+
+#define SA_STATUS_INVALID_PARAMETER (0xE0000007L)
+#define SA_STATUS_INVALID_ADDRESS (0xE000000CL)
+#define SA_STATUS_NOT_SUPPORTED (0xE000000DL)
+
+#define SA_STATUS_ACCESS_DENIED (0xE000000EL)
+
+#define SA_STATUS_TIMEOUT (0xE000100FL)
+#define SA_STATUS_ALERTED (0xE0001010L)
+
+/*-------- Basic defines -------*/
+#define SA_PAGE_SHIFT 12
+#define SA_PAGE_SIZE 4096 /* BUG */
+
+/* Standard MIN and MAX macros */
+#define MIN(_a_, _b_) (((_a_) < (_b_)) ? (_a_) : (_b_)) #define
+MAX(_a_, _b_) (((_a_) > (_b_)) ? (_a_) : (_b_))
+
+/*
+ * Returns number of pages spanned by the size of data
+ * starting at the given address.
+ */
+#define SA_PAGES_SPANNED(_address, _size) \
+ ((u32)(((SA_PTR_TO_INT(_address) & (SA_PAGE_SIZE - 1)) + \
+ (_size) + (SA_PAGE_SIZE - 1)) >> SA_PAGE_SHIFT))
+
+/*
+ * number of elements in an array
+ * e.g. u32 array[128];
+ * SA_NUMBER_OF(array) == 128
+ */
+#define SA_NUMBER_OF(_x_) (sizeof(_x_)/sizeof((_x_)[0]))
+
+/*
+ * Appropriate casts to avoid compiler warnings about casting between
+ * integers and pointers.
+ */
+#define SA_PTR_TO_INT(_p_) ((SA_SIZE_T)(_p_)) #define
+SA_PTR_TO_U32(_p_) ((u32)SA_PTR_TO_INT(_p_)) #define SA_PTR_TO_U64(_p_)
+((u64)SA_PTR_TO_INT(_p_))
+
+#define SA_PTR_TO_INT(_p_) ((SA_SIZE_T)(_p_)) #define
+SA_U64_TO_PTR(_u_) ((PVOID)(SA_SIZE_T)(_u_)) #define SA_U32_TO_PTR(_u_)
+((PVOID)(SA_SIZE_T)(_u_)) #define SA_PAGE_OFFSET(_addr_)
+(SA_PTR_TO_INT(_addr_) & (SA_PAGE_SIZE-1))
+
+/* Returns the next higher page aligned address. */ static inline PVOID
+SA_PAGE_ALIGN(PVOID _addr_) {
+ u32 addr = SA_PTR_TO_U32(_addr_);
+ if (addr & (SA_PAGE_SIZE - 1)) {
+ addr = (addr & ~(SA_PAGE_SIZE - 1)) + SA_PAGE_SIZE;
+ return SA_U32_TO_PTR(addr);
+ }
+ return _addr_;
+}
+
+/* Conversion from 64 bit values to hi and lo 32-bit values. */ static
+inline u32 sa_hi(u64 quad) {
+ return (u32) (quad >> 32);
+}
+static inline u32 sa_lo(u64 quad)
+{
+ return (u32) (quad);
+}
+
+static inline u64 sa_make_u64(u32 hi, u32 lo) {
+ return (((u64) hi) << 32) | lo;
+}
+
+static inline u32 sa_pvoid_hi(PVOID p)
+{
+ return sa_hi(SA_PTR_TO_U64(p));
+}
+
+static inline u32 sa_pvoid_lo(PVOID p)
+{
+ return sa_lo(SA_PTR_TO_U64(p));
+}
+
+static inline PVOID sa_make_pvoid(u32 hi, u32 lo) {
+ return SA_U64_TO_PTR(sa_make_u64(hi, lo)); }
+
+/* Returns byte offset of field within given struct type. */
+#define SA_FIELD_OFFSET(_type_, _field_) \
+ (SA_PTR_TO_U32((u8 *)&(((_type_ *)0)->_field_)))
+
+/* Returns byte size of given field with a structure. */ #define
+SA_SIZEOF_FIELD(_type_, _field_) \
+ sizeof(((_type_ *)0)->_field_)
+
+/* Returns the number of items in the field array. */
+#define SA_NUMBER_OF_FIELD(_type_, _field_) \
+ (SA_SIZEOF_FIELD(_type_, _field_)/sizeof((((_type_ *)0)->_field_[0])))
+
+/* Explicitly acknowledges that an input parameter is ignored. */
+#define SA_UNREFERENCED_PARAMETER(_p_) ((_p_) = (_p_))
+#define SA_NOT_USED SA_UNREFERENCED_PARAMETER /* abbreviation */
+
+/* Returns x/y plus 1 if there is a remainder. */ static inline u32
+sa_ceiling(u32 x, u32 y) {
+ ASSERT(y > 0);
+ return (x + y - 1) / y;
+}
+
+/*
+ * Round Up Increment
+ * Returns number to add to x to round up to next multiple
+ * of y. If x is multiple of y it returns 0.
+ */
+static inline u32 sa_round_up_inc(u32 x, u32 y) {
+ u32 z;
+ ASSERT(y > 0);
+ z = x % y;
+ return (z > 0 ? y - z : 0);
+}
+
+/*
+ * Returns x rounded to next multiple of y. If x is a multiple
+ * of y, it returns x.
+ */
+static inline u32 sa_round_up(u32 x, u32 y) {
+ return x + sa_round_up_inc(x, y);
+}
+
+/*
+ * circular subtract.
+ * Returns a - b assuming a circular number system, where a and b are
+ * in range (0, maxValue-1). If a==b, zero is returned so the
+ * highest value possible with this subtraction is maxValue-1.
+ */
+static inline u32 sa_subc(u32 a, u32 b, u32 max) {
+ ASSERT(a <= max && b <= max);
+ ASSERT(max > 0);
+ return (a >= b ? (a - b) : (max - b + a)); }
+
+static inline u32 sa_addc(u32 a, u32 b, u32 max) {
+ ASSERT(a < max);
+ ASSERT(max > 0);
+ return ((max - a > b) ? (a + b) : (b + a - max)); }
+
+#define C_LT(a, b) ((i32)((a)-(b)) < 0)
+#define C_LE(a, b) ((i32)((a)-(b)) <= 0)
+#define C_GT(a, b) ((i32)((a)-(b)) > 0)
+#define C_GE(a, b) ((i32)((a)-(b)) >= 0)
+
+/*------ List manipulation functions and macros ----*/
+
+/*
+ * Calculate the address of the base of the structure given its type,
+and an
+ * address of a field within the structure.
+ */
+#define SA_CONTAINING_RECORD(_address_, _type_, _field_) \
+ ((_type_ *)((u8 *)(_address_) - (u8 *)(&((_type_ *)0)->_field_)))
+
+typedef struct list_head SA_LIST_ENTRY; typedef struct list_head
+*PSA_LIST_ENTRY;
+
+#define SA_FOR_EACH_LIST_ENTRY(_LE, _LH, _TYPE, _LF) \
+ for ((_LE) = SA_CONTAINING_RECORD((_LH).next, _TYPE, _LF.next); \
+ &(_LE)->_LF != &(_LH); \
+ (_LE) = SA_CONTAINING_RECORD((_LE)->_LF.next, \
+ _TYPE, _LF.next))
+
+
+
+#define sa_initialize_list_head INIT_LIST_HEAD
+#define sa_is_list_empty list_empty
+#define IsListEmpty list_empty
+#define sa_remove_entry_list list_del
+#define sa_insert_tail_list(H, E) list_add_tail(E, H)
+#define InsertTailList(H, E) list_add_tail(E, H)
+#define sa_insert_head_list(H, E) list_add(E, H)
+#define RemoveHeadList sa_remove_head_list
+
+static
+inline PSA_LIST_ENTRY sa_list_head(IN PSA_LIST_ENTRY head) {
+ if (head->next == head)
+ return ((PSA_LIST_ENTRY) 0);
+ else
+ return (head->next);
+}
+
+static
+inline PSA_LIST_ENTRY sa_remove_head_list(IN PSA_LIST_ENTRY head) {
+ PSA_LIST_ENTRY entry = head->next;
+
+ list_del((struct list_head *)entry);
+ return (entry);
+}
+
+static
+inline PSA_LIST_ENTRY sa_remove_tail_list(IN PSA_LIST_ENTRY head) {
+ PSA_LIST_ENTRY entry = head->prev;
+
+ list_del((struct list_head *)entry);
+ return (entry);
+}
+
+/*------- Memory Allocation / copy related ------*/
+
+typedef struct _SA_SGL {
+ u32 length;
+ PVOID va;
+ u64 pa;
+} SA_SGL, *PSA_SGL;
+
+/*
+ * simple compile time assert to verify the length of the input string.
+ * The gcc compiler optimizes the entire thing to a constant with -02.
+ */
+#define SA_TAG(__four_char_string__) ({ \
+ SA_GLOBAL_C_ASSERT(tag_must_be_4_char, \
+ sizeof(__four_char_string__) == 5); \
+ (((u32)(__four_char_string__[3])<<24) | \
+ ((u32)(__four_char_string__[2])<<16) | \
+ ((u32)(__four_char_string__[1])<<8) | \
+ ((u32)(__four_char_string__[0]))); \
+})
+#define SA_ZERO_MEM(_ptr_) sa_zero_mem((_ptr_), sizeof(*(_ptr_)))
+
+static inline u32 sa_sgl_get_byte_count(IN PSA_SGL sgl) {
+ ASSERT(sgl);
+ return sgl->length;
+}
+
+static inline u32 sa_sgl_get_page_count(PSA_SGL sgl) {
+ ASSERT(sgl);
+ return SA_PAGES_SPANNED(sgl->va, sgl->length); }
+
+static inline PVOID sa_sgl_get_base_va(IN PSA_SGL sgl) {
+ ASSERT(sgl);
+ return sgl->va;
+}
+
+static inline u32 sa_sgl_get_offset(PSA_SGL sgl) {
+ ASSERT(sgl);
+ return SA_PAGE_OFFSET(sgl->va);
+}
+
+static inline SA_PHYSICAL_ADDRESS
+sa_sgl_get_page(IN PSA_SGL sgl, IN u32 page_index) {
+ SA_PHYSICAL_ADDRESS pa;
+
+ ASSERT(sgl);
+ ASSERT(page_index < sa_sgl_get_page_count(sgl));
+
+ if (page_index == 0) {
+ pa = virt_to_phys(sgl->va);
+ pa &= ~(SA_PAGE_SIZE - 1); /* next lower pa */
+ } else {
+ u64 va = SA_PTR_TO_U64(sgl->va) & ~(SA_PAGE_SIZE - 1);
+ va += page_index * SA_PAGE_SIZE; /* offset to correct page */
+ pa = virt_to_phys(SA_U64_TO_PTR(va));
+ }
+
+ ASSERT(pa);
+
+ /* must return page aligned address. */
+ ASSERT(SA_PAGE_ALIGN(SA_U64_TO_PTR(pa)) == SA_U64_TO_PTR(pa));
+ return cpu_to_le64(pa);
+}
+
+/*
+ * Optimized as the kernel version for the given platform.
+ *static inline void*
+ */
+static inline void *sa_zero_mem(void *ptr, u32 bytes) {
+ return memset(ptr, 0, (SA_SIZE_T) bytes); }
+
+static inline void *sa_memset(PVOID ptr, u32 value, u32 bytes) {
+ return memset(ptr, value, (SA_SIZE_T) bytes); }
+
+static inline void *sa_memcpy(PVOID dest, const void *src, u32 bytes) {
+ return memcpy(dest, src, (SA_SIZE_T) bytes); }
+
+/* Returns value of dest. */
+static inline void *sa_memmove(PVOID dest, const void *src, u32 bytes)
+{
+ return (void *)memmove(dest, src, (SA_SIZE_T) bytes); }
+
+static inline i32 sa_memcmp(const void *a, const void *b, u32 bytes) {
+ return memcmp(a, b, (SA_SIZE_T) bytes); }
+
+/*----- Device I/O related ---------*/
+
+typedef enum {
+ SA_BAR_TYPE_INVALID = 0,
+
+ SA_BAR_TYPE_BOOT,
+ SA_BAR_TYPE_CSR,
+ SA_BAR_TYPE_PD,
+ SA_BAR_TYPE_PCI,
+
+ SA_BAR_TYPE_MAX
+} SA_DEV_BAR_TYPE;
+
+/*
+ * MemOrIOMapped has the following two values
+ * for reference purpose
+ */
+typedef enum {
+ SA_IO_MAPPED = 0x01,
+ SA_MEM_MAPPED = 0x02
+} SA_DEV_MAPPED_TYPE;
+
+typedef struct _SA_DEV_BAR_LOCATIONS {
+ void *base_va; /* Virtual Address */
+ u64 base_pa; /* Physical Address */
+ u32 length; /* Length of register space */
+
+ SA_DEV_MAPPED_TYPE mem_or_io_mapped; /* io or memory mapped */
+ SA_DEV_BAR_TYPE type; /* What is this BAR used for. */
+
+} SA_DEV_BAR_LOCATIONS, *PSA_DEV_BAR_LOCATIONS;
+
+typedef u64 SA_DEV_BUS_ADDRESS, *PSA_DEV_BUS_ADDRESS;
+
+/*
+ * The device object uses a "magic" field to help catch memory
+ * corruption bugs. It is initialized to the magic number defined here
+ * and ASSERTS verify this number in all other functions.
+ */
+#define SA_DEV_MAGIC (0x12345678)
+#define SA_DEV_ASSERT(_pdev_) ASSERT ((_pdev_)->magic == SA_DEV_MAGIC)
+#define SA_DEV_MAX_BARS (8)
+/*
+ * Context structure passed to create the device object. This is the
+ * device extension for the storage miniport.
+ */
+typedef PVOID SA_DEV_OS_HANDLE, *PSA_DEV_OS_HANDLE;
+/*
+ * Device Object
+ */
+typedef struct _SA_DEV {
+ u32 magic;
+ u32 num_bars;
+ SA_DEV_BAR_LOCATIONS bars[SA_DEV_MAX_BARS];
+ u32 csr_bar_num, pd_bar_num, pci_bar_num; } SA_DEV, *PSA_DEV;
+
+/*
+ * This assumes that each type defines the members "bars" and "num_bars"
+ * Returns the bar number, or ~0 if the given type doesn't exist.
+ */
+static inline u32 sa_get_bar_num(SA_DEV *dev, SA_DEV_BAR_TYPE type) {
+ u32 i;
+ for (i = 0; i < dev->num_bars; i++) {
+ if (type == dev->bars[i].type) {
+ return i;
+ }
+ }
+
+ return ~(u32) 0;
+}
+
+/* Internal function. */
+static inline void _sa_cache_bar_nums(SA_DEV *dev) {
+ dev->csr_bar_num = sa_get_bar_num(dev, SA_BAR_TYPE_CSR);
+ dev->pd_bar_num = sa_get_bar_num(dev, SA_BAR_TYPE_PD);
+ dev->pci_bar_num = sa_get_bar_num(dev, SA_BAR_TYPE_PCI); }
+
+/* Assume these values are cached in the sa_dev. */ static inline u32
+sa_get_csr_bar(SA_DEV *dev) {
+ return dev->csr_bar_num;
+}
+
+static inline u32 sa_get_pd_bar(SA_DEV *dev) {
+ return dev->pd_bar_num;
+}
+
+static inline u32 sa_get_pci_bar(SA_DEV *dev) {
+ return dev->pci_bar_num;
+}
+
+SA_STATUS
+sa_dev_create(SA_DEV_BAR_LOCATIONS *, u32, SA_DEV_OS_HANDLE, SA_DEV *);
+void sa_dev_destroy(SA_DEV *);
+
+u32 sa_dev_read_u32(SA_DEV *dev, u32 bar, u32 offset); void
+sa_dev_write_u32(SA_DEV *dev, u32 bar, u32 offset, u32 value); void
+sa_dev_stall(SA_DEV *dev, u32 us_to_stall);
+
+/*
+ *------- ring manipulation related ------
+ * This structure stores information about a ring shared between
+hardware
+ * and software. Each ring is allocated by the driver in the uncached
+ * extension and mapped into BladeEngine's unified table. BEKLIB
+manages
+ * creation and destruction of the rings in hardware. It returns the
+ * corresponding HANDLE to the ring.
+ */
+typedef struct _SA_RING {
+ u32 pages; /* queue size in pages */
+ u32 id; /* queue id assigned by beklib */
+ u32 num; /* number of elements in queue */
+ u32 cidx; /* consumer index */
+ u32 pidx; /* producer index -- not used by most rings */
+ u32 itemSize; /* size in bytes of one object */
+
+ PVOID va; /* The virtual address of the ring.
+ This should be last to allow 32 & 64
+ bit debugger extensions to work. */
+
+} SA_RING, *PSA_RING;
+
+#define SA_RING_FOREACH_ITEM(_pRing_, _pItem_, _type_,_code_) \
+{ \
+ u32 ring_num_pending = sa_ring_num_pending((_pRing_)); \
+ u32 ring_index; \
+ for (ring_index = 0; ring_index < ring_num_pending; ring_index++) { \
+ _pItem_ = (_type_)((u8 *)(_pRing_)->va + \
+ (_pRing_)->itemSize * \
+ (((_pRing_)->cidx + ring_index) % (_pRing_)->num)); \
+ ASSERT(sizeof (*(_pItem_)) == (_pRing_)->itemSize); \
+ _code_ \
+ } \
+} \
+
+static
+inline void sa_ring_create(PSA_RING ring,
+ u32 num, u32 itemSize, PVOID va) {
+ ASSERT(ring);
+ sa_zero_mem(ring, sizeof(SA_RING));
+ ring->num = num;
+ ring->pages = sa_ceiling(num * itemSize, SA_PAGE_SIZE);
+ ring->itemSize = itemSize;
+ ring->va = va;
+}
+
+static inline void sa_ring_set_id(PSA_RING ring, u32 id) {
+ ASSERT(ring);
+ ring->id = id;
+}
+
+static inline u32 sa_ring_num(PSA_RING ring) {
+ ASSERT(ring);
+ return ring->num;
+}
+
+static inline PVOID sa_ring_va(PSA_RING ring) {
+ ASSERT(ring);
+ return ring->va;
+}
+
+static inline void sa_ring_clear(PSA_RING ring) {
+ ASSERT(ring);
+ ring->pidx = ring->cidx = 0;
+}
+
+/*
+ *
+-----------------------------------------------------------------------
+ * Interface for 2 index rings. i.e. consumer/producer rings
+ *
+-----------------------------------------------------------------------
+---
+ */
+
+/* Returns TRUE if ring is empty */
+static inline boolean sa_ring_is_empty(PSA_RING ring) {
+ ASSERT(ring);
+ return (ring->pidx == ring->cidx);
+}
+
+/* Define the power2 version equivalent */ #define
+sa_ring_power2_is_empty sa_ring_is_empty
+
+/* Returns number items pending on ring. */ static inline u32
+sa_ring_num_pending(PSA_RING ring) {
+ ASSERT(ring);
+ if (ring->num == 0) {
+ return 0;
+ }
+ return sa_subc(ring->pidx, ring->cidx, ring->num); }
+
+/* Returns number items free on ring. */ static inline u32
+sa_ring_num_empty(PSA_RING ring) {
+ ASSERT(ring);
+ return ring->num - 1 - sa_ring_num_pending(ring); }
+
+/* Returns TRUE if ring is full */
+static inline boolean sa_ring_is_full(PSA_RING ring) {
+ ASSERT(ring);
+ return sa_ring_num_pending(ring) == (ring->num - 1); }
+
+/* Consume 1 item */
+static inline void sa_ring_consume(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(!sa_ring_is_empty(ring));
+ ring->cidx = sa_addc(ring->cidx, 1, ring->num); }
+
+/* Produce 1 item */
+static inline void sa_ring_produce(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(!sa_ring_is_full(ring));
+ ring->pidx = sa_addc(ring->pidx, 1, ring->num); }
+
+/* Consume count items */
+static inline void sa_ring_consume_multiple(PSA_RING ring, u32 count) {
+ ASSERT(ring);
+ ASSERT(sa_ring_num_pending(ring) >= count);
+ ring->cidx = sa_addc(ring->cidx, count, ring->num); }
+
+static inline PVOID sa_ring_item(PSA_RING ring, u32 index) {
+ ASSERT(ring);
+ ASSERT(index < ring->num);
+ ASSERT(ring->itemSize > 0);
+ return (u8 *) ring->va + index * ring->itemSize; }
+
+#define sa_ring_power2_item sa_ring_item
+
+/* Ptr to produce item */
+static inline PVOID sa_ring_producer_ptr(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(!sa_ring_is_full(ring));
+ return sa_ring_item(ring, ring->pidx); }
+
+#define sa_ring_power2_producer_ptr sa_ring_producer_ptr
+
+/*
+ * Returns a pointer to the current location in the ring.
+ * This is used for rings with 1 index.
+ */
+static inline PVOID sa_ring_current(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(ring->pidx == 0); /* not used */
+
+ return sa_ring_item(ring, ring->cidx); }
+
+/* Ptr to consume item */
+static inline PVOID sa_ring_consumer_ptr(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(!sa_ring_is_empty(ring));
+ return sa_ring_item(ring, ring->cidx); }
+
+#define sa_ring_power2_current sa_ring_current
+
+/*
+ * Increment index for rings with only 1 index.
+ * This is used for rings with 1 index.
+ */
+static inline PVOID sa_ring_next(PSA_RING ring) {
+ ASSERT(ring);
+ ASSERT(ring->num > 0);
+ ASSERT(ring->pidx == 0); /* not used */
+
+ ring->cidx = sa_addc(ring->cidx, 1, ring->num);
+ return sa_ring_current(ring);
+}
+
+/*
+ * Each bit is 1 byte in array maps.
+ */
+typedef u8 AMAP_BIT;
+typedef AMAP_BIT BE_BIT;
+
+/* Returns 0-31 representing bit offset within a DWORD of a bitfield. */
+#define AMAP_BIT_OFFSET(_struct_, _register_) \
+ (((SA_SIZE_T)&(((BE_ ## _struct_ ## _AMAP *)0)->_register_))%32)
+
+
+/* Returns 0-n representing byte offset of bitfield with the structure. */
+#define AMAP_BYTE_OFFSET(_struct_, _register_) \
+ (((SA_SIZE_T)&(((BE_ ## _struct_ ## _AMAP *)0)->_register_))/8)
+
+/* Returns 0-n representing DWORD offset of bitfield within the
+structure. */ #define AMAP_WORD_OFFSET(_struct_, _register_) \
+ (AMAP_BYTE_OFFSET(_struct_, _register_)/4)
+
+/*-------- spinlock / mutex related -------*/
+
+typedef spinlock_t SA_REAL_SPINLOCK, *PSA_REAL_SPINLOCK; typedef
+spinlock_t SA_SPINLOCK, *PSA_SPINLOCK; typedef struct semaphore
+SA_FAST_MUTEX, *PSA_FAST_MUTEX; typedef struct semaphore SA_EVENT,
+*PSA_EVENT; typedef u64 SA_IRQ, *PSA_IRQ;
+
+#define sa_init_spinlock sa_init_spinlock_real
+#define sa_acquire_spinlock sa_acquire_spinlock_real
+#define sa_release_spinlock sa_release_spinlock_real
+#define sa_acquire_spinlock_noirq sa_acquire_spinlock_noirq_real
+#define sa_release_spinlock_noirq sa_release_spinlock_noirq_real
+#define sa_is_spin_lock_held sa_is_spin_lock_held_real
+#define sa_is_spinlock_not_held sa_is_spinlock_not_held_real
+
+void sa_init_spinlock_real(IN PSA_REAL_SPINLOCK); void
+sa_acquire_spinlock_real(IN PSA_REAL_SPINLOCK, OUT PSA_IRQ); void
+sa_release_spinlock_real(IN PSA_REAL_SPINLOCK, IN PSA_IRQ); void
+sa_initialize_fast_mutex(IN PSA_FAST_MUTEX);
+
+static inline u32 sa_atomic_decrement(u32 *value) {
+ atomic_dec((atomic_t *) value);
+ return *value;
+}
+
+/* Returns resulting value. */
+static inline u32 sa_atomic_increment(u32 *value) {
+ atomic_inc((atomic_t *) value);
+ return *value;
+}
+
+/* Atomically does this: *v += i; */
+#define sa_atomic_add(i, v) atomic_add (i, (atomic_t *)v)
+
+/* Atomically does this: *v -= i; */
+#define sa_atomic_sub(i, v) atomic_sub(i, (atomic_t *)v)
+
+#define sa_init_spinlock_real(s) spin_lock_init(s)
+#define sa_acquire_spinlock_real(s, i) spin_lock_irqsave(s, *i)
+#define sa_acquire_spinlock_noirq_real(s) spin_lock (s)
+#define sa_release_spinlock_real(s, i) spin_unlock_irqrestore(s, *i);
+#define sa_release_spinlock_noirq_real(s) spin_unlock(spinlock)
+#define sa_is_spin_lock_held_real(s) spin_is_locked (s);
+#define sa_is_spinlock_not_held_real(s) (!(spin_is_locked (lock))
+
+/* Returns size of bitfield in bits. */ #define AMAP_BIT_SIZE(_struct_,
+_register_) \
+ sizeof(((BE_ ## _struct_ ## _AMAP *)0)->_register_)
+
+/*
+ * Masks the bits (before shifting!) and then shifts to correct offset.
+ * contextMemory.dw[1] = AMAP_SET_BITS (struct, field1, 123) |
+ * AMAP_SET_BITS (struct, field2, 456):
+ * Remember this does not clear bits!
+ */
+static inline u32 amap_set_bits(u32 mask, u32 offset, u32 new_value) {
+ return (mask & new_value) << offset;
+}
+
+/*
+ * Returns the a bit mask for the register that is NOT shifted into location.
+ * That means return values always look like: 0x1, 0xFF, 0x7FF, etc...
+ */
+static inline u32 amap_mask(u32 bit_size) {
+ return (bit_size == 32 ? 0xFFFFFFFF : (1 << bit_size) - 1); }
+
+#define AMAP_SET_BITS(_struct_, _register_, _new_value_) \
+ amap_set_bits(AMAP_BIT_MASK(_struct_, _register_), \
+ AMAP_BIT_OFFSET(_struct_, _register_), _new_value_)
+
+#define AMAP_BIT_MASK(_struct_, _register_) \
+ amap_mask (AMAP_BIT_SIZE (_struct_, _register_))
+
+#define BE_BIT_OFFSET AMAP_BIT_OFFSET
+#define BE_WORD_OFFSET AMAP_WORD_OFFSET
+#define BE_BIT_SIZE AMAP_BIT_SIZE
+#define BE_BYTE_OFFSET AMAP_BYTE_OFFSET
+#define BE_SET_BITS AMAP_SET_BITS
+
+/*------- MAC address related -------*/
+
+#define SA_MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
+
+#define SA_MAC_ADDRESS_SIZE (6)
+typedef struct _SA_MAC_ADDRESS {
+ u8 bytes[SA_MAC_ADDRESS_SIZE];
+} __attribute__ ((packed)) SA_MAC_ADDRESS, *PSA_MAC_ADDRESS;
+
+#define SA_MAC_ARGS(_mac_address_) \
+ (u32)((_mac_address_).bytes[0]), \
+ (u32)((_mac_address_).bytes[1]), \
+ (u32)((_mac_address_).bytes[2]), \
+ (u32)((_mac_address_).bytes[3]), \
+ (u32)((_mac_address_).bytes[4]), \
+ (u32)((_mac_address_).bytes[5])
+
+/*
+ * Creates a SGL for a physically contiguous chunk of memory.
+ * The sgl struct must be previously allocated.
+ */
+static inline SA_STATUS
+sa_sgl_create_contiguous(PVOID va, SA_PHYSICAL_ADDRESS pa,
+ u32 length, PSA_SGL sgl)
+{
+
+ sgl->va = va;
+ sgl->pa = pa;
+ sgl->length = length;
+ return (SA_SUCCESS);
+}
+
+#define sa_sgl_destroy_contiguous(sgl) SA_ZERO_MEM (sgl)
+
+/*
+ *------ bit manipulation macros / functions -----
+ * Checks for truncation of the value when assigning to a bitfield that
+ * may have fewer bits. e.g.
+ * struct { u32 hi : 1; } me;
+ * SA_SET_BITFIELD(me.hi, 2);
+ */
+#define SA_SET_BITFIELD(_bitfield_, _value_) \
+ do {\
+ (_bitfield_) = (_value_); \
+ ASSERT((_bitfield_) == (_value_)) \
+ } while (0) \
+
+static
+inline u32 sa_bit_range(u32 value, u32 bit_offset, u32 num_bits) {
+ ASSERT(bit_offset <= sizeof(value) * 8);
+ ASSERT(num_bits <= sizeof(value) * 8);
+ return (value >> bit_offset) & ((1UL << num_bits) - 1); }
+
+static
+inline u64 sa_bit_range64(u64 value, u32 bit_offset, u32 num_bits) {
+ ASSERT(bit_offset <= sizeof(value) * 8);
+ ASSERT(num_bits <= sizeof(value) * 8);
+ return (value >> bit_offset) & ((1ULL << num_bits) - 1); }
+
+static inline u32 sa_upper_bits(u32 value, u32 num_bits) {
+ ASSERT(num_bits <= sizeof(value) * 8);
+ return sa_bit_range(value, sizeof(value) * 8 - num_bits, num_bits); }
+
+static inline u64 sa_upper_bits64(u64 value, u32 num_bits) {
+ ASSERT(num_bits <= sizeof(value) * 8);
+ return sa_bit_range64(value, sizeof(value) * 8 - num_bits,
+ num_bits);
+}
+
+/* The bit vector structure. */
+typedef struct _SA_BIT_VECTOR {
+ u32 magic;
+ u32 numBits;
+ u32 numDwords;
+ u32 numSet;
+ u32 *bits;
+} SA_BIT_VECTOR, *PSA_BIT_VECTOR;
+
+#endif /* __sa_h__ */
___________________________________________________________________________________
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^ permalink raw reply
* [PATHCH 10/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:44 UTC (permalink / raw)
To: netdev
F/W header files.
---------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_opcodes.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_opcodes.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_opcodes.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_opcodes.h 2008-02-14 15:23:07.815204672 +0530
@@ -0,0 +1,812 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_opcodes_amap_h__
+#define __ioctl_opcodes_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/*
+ * --- IOCTL_SUBSYSTEMS ---
+ * The IOCTLs are grouped into the following subsystems. The subsystem
+ * code along with the opcode uniquely identify a particular IOCTL.
+ */
+#define IOCTL_SUBSYSTEM_RSVD (0) /* This subsystem is reserved. It is */
+ /* never used. */
+#define IOCTL_SUBSYSTEM_COMMON (1) /* IOCTLs in this group are common to */
+ /*
+ * all subsystems. See
+ * COMMON_SUBSYSTEM_OPCODES for opcodes
+ * and Common Host Configuration IOCTLs
+ * for the IOCTL descriptions.
+ */
+#define IOCTL_SUBSYSTEM_COMMON_ISCSI (2) /* IOCTLs in this group are */
+ /*
+ * common to Initiator and Target. See
+ * COMMON_ISCSI_SUBSYSTEM_OPCODES and
+ * Common iSCSI Initiator and Target
+ * IOCTLs for the IOCTL descriptions.
+ */
+#define IOCTL_SUBSYSTEM_ETH (3) /* This subsystem is used to
+ execute Ethernet commands. */
+
+#define IOCTL_SUBSYSTEM_TPM (4) /* This subsystem is used
+ to execute TPM commands. */
+#define IOCTL_SUBSYSTEM_PXE_UNDI (5) /* This subsystem is used
+ * to execute PXE
+ * and UNDI specific commands.
+ */
+
+#define IOCTL_SUBSYSTEM_ISCSI_INI (6) /* This subsystem is used to
+ execute ISCSI Initiator
+ specific commands.
+ */
+#define IOCTL_SUBSYSTEM_ISCSI_TGT (7) /* This subsystem is used
+ to execute iSCSI Target
+ specific commands.between
+ PTL and ARM firmware.
+ */
+#define IOCTL_SUBSYSTEM_MILI_PTL (8) /* This subsystem is used to
+ execute iSCSI Target specific
+ commands.between MILI
+ and PTL. */
+#define IOCTL_SUBSYSTEM_MILI_TMD (9) /* This subsystem is used to
+ execute iSCSI Target specific
+ commands between MILI
+ and TMD. */
+#define IOCTL_SUBSYSTEM_PROXY (11) /* This subsystem is used
+ to execute proxied commands
+ within the host at the
+ explicit request of a
+ non priviledged domain.
+ This 'subsystem' is entirely
+ virtual from the controller
+ and firmware perspective as
+ it is implemented in host
+ drivers.
+ */
+
+/*
+ * --- COMMON_SUBSYSTEM_OPCODES ---
+ * These opcodes are common to both networking and storage PCI
+ * functions. They are used to reserve resources and configure
+ * BladeEngine. These opcodes all use the IOCTL_SUBSYSTEM_COMMON
+ * subsystem code.
+ */
+#define OPCODE_COMMON_NTWK_MAC_QUERY (1)
+#define SUBSYSTEM_COMMON_NTWK_MAC_QUERY (1)
+#define SUBSYSTEM_COMMON_NTWK_MAC_SET (1)
+#define SUBSYSTEM_COMMON_NTWK_MULTICAST_SET (1)
+#define SUBSYSTEM_COMMON_NTWK_VLAN_CONFIG (1)
+#define SUBSYSTEM_COMMON_NTWK_LINK_STATUS_QUERY (1)
+#define SUBSYSTEM_COMMON_READ_FLASHROM (1)
+#define SUBSYSTEM_COMMON_WRITE_FLASHROM (1)
+#define SUBSYSTEM_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE (1)
+#define SUBSYSTEM_COMMON_ADD_PAGE_TABLES (1)
+#define SUBSYSTEM_COMMON_REMOVE_PAGE_TABLES (1)
+#define SUBSYSTEM_COMMON_RING_DESTROY (1)
+#define SUBSYSTEM_COMMON_CQ_CREATE (1)
+#define SUBSYSTEM_COMMON_EQ_CREATE (1)
+#define SUBSYSTEM_COMMON_ETH_RX_CREATE (1)
+#define SUBSYSTEM_COMMON_ETH_TX_CREATE (1)
+#define SUBSYSTEM_COMMON_ISCSI_DEFQ_CREATE (1)
+#define SUBSYSTEM_COMMON_ISCSI_WRBQ_CREATE (1)
+#define SUBSYSTEM_COMMON_MCC_CREATE (1)
+#define SUBSYSTEM_COMMON_JELL_CONFIG (1)
+#define SUBSYSTEM_COMMON_FORCE_FAILOVER (1)
+#define SUBSYSTEM_COMMON_ADD_TEMPLATE_HEADER_BUFFERS (1)
+#define SUBSYSTEM_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS (1)
+#define SUBSYSTEM_COMMON_POST_ZERO_BUFFER (1)
+#define SUBSYSTEM_COMMON_GET_QOS (1)
+#define SUBSYSTEM_COMMON_SET_QOS (1)
+#define SUBSYSTEM_COMMON_TCP_GET_STATISTICS (1)
+#define SUBSYSTEM_COMMON_SEEPROM_READ (1)
+#define SUBSYSTEM_COMMON_TCP_STATE_QUERY (1)
+#define SUBSYSTEM_COMMON_GET_CNTL_ATTRIBUTES (1)
+#define SUBSYSTEM_COMMON_NOP (1)
+#define SUBSYSTEM_COMMON_NTWK_RX_FILTER (1)
+#define SUBSYSTEM_COMMON_GET_FW_VERSION (1)
+#define SUBSYSTEM_COMMON_SET_FLOW_CONTROL (1)
+#define SUBSYSTEM_COMMON_GET_FLOW_CONTROL (1)
+#define SUBSYSTEM_COMMON_SET_TCP_PARAMETERS (1)
+#define SUBSYSTEM_COMMON_SET_FRAME_SIZE (1)
+#define SUBSYSTEM_COMMON_GET_FAT (1)
+#define SUBSYSTEM_COMMON_MODIFY_EQ_DELAY (1)
+#define SUBSYSTEM_COMMON_FIRMWARE_CONFIG (1)
+#define SUBSYSTEM_COMMON_ENABLE_DISABLE_DOMAINS (1)
+#define SUBSYSTEM_COMMON_GET_DOMAIN_CONFIG (1)
+#define SUBSYSTEM_COMMON_SET_VLD_CONFIG (1)
+#define SUBSYSTEM_COMMON_GET_VLD_CONFIG (1)
+#define SUBSYSTEM_COMMON_GET_PORT_EQUALIZATION (1)
+#define SUBSYSTEM_COMMON_SET_PORT_EQUALIZATION (1)
+#define SUBSYSTEM_COMMON_RED_CONFIG (1)
+#define OPCODE_COMMON_NTWK_MAC_SET (2)
+#define OPCODE_COMMON_NTWK_MULTICAST_SET (3)
+#define OPCODE_COMMON_NTWK_VLAN_CONFIG (4)
+#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY (5)
+#define OPCODE_COMMON_READ_FLASHROM (6)
+#define OPCODE_COMMON_WRITE_FLASHROM (7)
+#define OPCODE_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE (8)
+#define OPCODE_COMMON_ADD_PAGE_TABLES (9)
+#define OPCODE_COMMON_REMOVE_PAGE_TABLES (10)
+#define OPCODE_COMMON_RING_DESTROY (11)
+#define OPCODE_COMMON_CQ_CREATE (12)
+#define OPCODE_COMMON_EQ_CREATE (13)
+#define OPCODE_COMMON_ETH_RX_CREATE (14)
+#define OPCODE_COMMON_ETH_TX_CREATE (15)
+#define OPCODE_COMMON_NET_RESERVED0 (16) /* Reserved */
+#define OPCODE_COMMON_NET_RESERVED1 (17) /* Reserved */
+#define OPCODE_COMMON_NET_RESERVED2 (18) /* Reserved */
+#define OPCODE_COMMON_ISCSI_DEFQ_CREATE (19)
+#define OPCODE_COMMON_ISCSI_WRBQ_CREATE (20)
+#define OPCODE_COMMON_MCC_CREATE (21)
+#define OPCODE_COMMON_JELL_CONFIG (22)
+#define OPCODE_COMMON_FORCE_FAILOVER (23)
+#define OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS (24)
+#define OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS (25)
+#define OPCODE_COMMON_POST_ZERO_BUFFER (26)
+#define OPCODE_COMMON_GET_QOS (27)
+#define OPCODE_COMMON_SET_QOS (28)
+#define OPCODE_COMMON_TCP_GET_STATISTICS (29)
+#define OPCODE_COMMON_SEEPROM_READ (30)
+#define OPCODE_COMMON_TCP_STATE_QUERY (31)
+#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES (32)
+#define OPCODE_COMMON_NOP (33)
+#define OPCODE_COMMON_NTWK_RX_FILTER (34)
+#define OPCODE_COMMON_GET_FW_VERSION (35)
+#define OPCODE_COMMON_SET_FLOW_CONTROL (36)
+#define OPCODE_COMMON_GET_FLOW_CONTROL (37)
+#define OPCODE_COMMON_SET_TCP_PARAMETERS (38)
+#define OPCODE_COMMON_SET_FRAME_SIZE (39)
+#define OPCODE_COMMON_GET_FAT (40)
+#define OPCODE_COMMON_MODIFY_EQ_DELAY (41)
+#define OPCODE_COMMON_FIRMWARE_CONFIG (42)
+#define OPCODE_COMMON_ENABLE_DISABLE_DOMAINS (43)
+#define OPCODE_COMMON_GET_DOMAIN_CONFIG (44)
+#define OPCODE_COMMON_SET_VLD_CONFIG (45)
+#define OPCODE_COMMON_GET_VLD_CONFIG (46)
+#define OPCODE_COMMON_GET_PORT_EQUALIZATION (47)
+#define OPCODE_COMMON_SET_PORT_EQUALIZATION (48)
+#define OPCODE_COMMON_RED_CONFIG (49)
+
+/*
+ * --- COMMON_ISCSI_SUBSYSTEM_OPCODES ---
+ * IOCTLs used to configure discovery and networking parameters in
+ * iSCSI Initiator and Target modes. These opcodes all use the
+ * IOCTL_SUBSYSTEM_COMMON_ISCSI subsystem code.
+ */
+#define OPCODE_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS (1)
+#define SUBSYSTEM_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS (2)
+#define OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_POST_SGL_PAGES (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_POST_OOO_BUFFERS (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_REMOVE_OOO_BUFFERS (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_PING (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_GET_NIC_CONFIG (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_GET_ARP_TABLE (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_SET_ARP_TABLE (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_GET_ROUTE_TABLE (2)
+#define SUBSYSTEM_COMMON_ISCSI_NTWK_SET_ROUTE_TABLE (2)
+#define SUBSYSTEM_COMMON_ISCSI_DISCOVERY_GET_PARAMETERS (2)
+#define SUBSYSTEM_COMMON_ISCSI_DISCOVERY_SET_PARAMETERS (2)
+#define SUBSYSTEM_COMMON_ISCSI_STATS_GET_NODE_ATTRIBUTES (2)
+#define SUBSYSTEM_COMMON_ISCSI_STATS_GET_NIC_STATISTICS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DOWNLOAD_XML (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DELETE_XML (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_RX_STATS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_TX_STATS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ADD_CERTIFICATE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DEL_CERTIFICATE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ADD_PRIVATE_KEY (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DEL_PRIVATE_KEY (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ADD_PASSPHRASE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DEL_PASSPHRASE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ENABLE_DISABLE_FLASH_ENCRYPTION (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_GROUP_NAMES (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_SINGLE_GROUP_NAME (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ADD_GROUP (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_DELETE_GROUP (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_QMSTATS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_MMSTATS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_STATE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_CLEAR_PSK_CACHE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_PSK (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_SET_GUID (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_SET_PSK (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_SET_TUNNEL_MODE_OUTER_ADDRESS (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_GET_SECURITY_CAPABILITIES (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_SET_GROUP_PSK (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ADD_ROOT_CERTIFICATE (2)
+#define SUBSYSTEM_COMMON_ISCSI_IPSEC_ENABLE_DISABLE (2)
+#define SUBSYSTEM_COMMON_ISCSI_CLEANUP (2)
+#define SUBSYSTEM_COMMON_ISCSI_ADD_8BYTE_LUN (2)
+#define SUBSYSTEM_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_CLEAR_EVENT_LOG (2)
+#define SUBSYSTEM_COMMON_ISCSI_CFG_READ_EVENT_LOG (2)
+#define OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES (3)
+#define OPCODE_COMMON_ISCSI_CFG_POST_OOO_BUFFERS (4)
+#define OPCODE_COMMON_ISCSI_CFG_REMOVE_OOO_BUFFERS (5)
+#define OPCODE_COMMON_ISCSI_NTWK_PING (6)
+#define OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG (7)
+#define OPCODE_COMMON_ISCSI_NTWK_GET_ARP_TABLE (8)
+#define OPCODE_COMMON_ISCSI_NTWK_SET_ARP_TABLE (9)
+#define OPCODE_COMMON_ISCSI_NTWK_GET_ROUTE_TABLE (10)
+#define OPCODE_COMMON_ISCSI_NTWK_SET_ROUTE_TABLE (11)
+#define OPCODE_COMMON_ISCSI_DISCOVERY_GET_PARAMETERS (12)
+#define OPCODE_COMMON_ISCSI_DISCOVERY_SET_PARAMETERS (13)
+#define OPCODE_COMMON_ISCSI_STATS_GET_NODE_ATTRIBUTES (14)
+#define OPCODE_COMMON_ISCSI_STATS_GET_NIC_STATISTICS (15)
+#define OPCODE_COMMON_ISCSI_IPSEC_DOWNLOAD_XML (16)
+#define OPCODE_COMMON_ISCSI_IPSEC_DELETE_XML (17)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_RX_STATS (18)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_TX_STATS (19)
+#define OPCODE_COMMON_ISCSI_IPSEC_ADD_CERTIFICATE (20)
+#define OPCODE_COMMON_ISCSI_IPSEC_DEL_CERTIFICATE (21)
+#define OPCODE_COMMON_ISCSI_IPSEC_ADD_PRIVATE_KEY (22)
+#define OPCODE_COMMON_ISCSI_IPSEC_DEL_PRIVATE_KEY (23)
+#define OPCODE_COMMON_ISCSI_IPSEC_ADD_PASSPHRASE (24)
+#define OPCODE_COMMON_ISCSI_IPSEC_DEL_PASSPHRASE (25)
+#define OPCODE_COMMON_ISCSI_IPSEC_ENABLE_DISABLE_FLASH_ENCRYPTION (26)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_GROUP_NAMES (27)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_SINGLE_GROUP_NAME (28)
+#define OPCODE_COMMON_ISCSI_IPSEC_ADD_GROUP (29)
+#define OPCODE_COMMON_ISCSI_IPSEC_DELETE_GROUP (30)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_QMSTATS (31)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_MMSTATS (32)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_STATE (33)
+#define OPCODE_COMMON_ISCSI_IPSEC_CLEAR_PSK_CACHE (34)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_PSK (35)
+#define OPCODE_COMMON_ISCSI_IPSEC_SET_GUID (36)
+#define OPCODE_COMMON_ISCSI_IPSEC_SET_PSK (37)
+#define OPCODE_COMMON_ISCSI_IPSEC_SET_TUNNEL_MODE_OUTER_ADDRESS (38)
+#define OPCODE_COMMON_ISCSI_IPSEC_GET_SECURITY_CAPABILITIES (39)
+#define OPCODE_COMMON_ISCSI_IPSEC_SET_GROUP_PSK (40)
+#define OPCODE_COMMON_ISCSI_IPSEC_ADD_ROOT_CERTIFICATE (41)
+#define OPCODE_COMMON_ISCSI_IPSEC_ENABLE_DISABLE (42)
+#define OPCODE_COMMON_ISCSI_CLEANUP (43)
+#define OPCODE_COMMON_ISCSI_ADD_8BYTE_LUN (44)
+#define OPCODE_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA (45)
+#define OPCODE_COMMON_ISCSI_CFG_CLEAR_EVENT_LOG (46)
+#define OPCODE_COMMON_ISCSI_CFG_READ_EVENT_LOG (47)
+
+/*
+ * --- ISCSI_INI_SUBSYSTEM_OPCODES ---
+ * Opcodes applicable to the IOCTL_SUBSYSTEM_ISCSI_INI subsystem.
+ */
+#define OPCODE_ISCSI_INI_NTWK_GET_TCPIP_CONFIG (1)
+#define OPCODE_ISCSI_INI_NTWK_SET_TCPIP_CONFIG (2)
+#define OPCODE_ISCSI_INI_NTWK_GET_DHCP_STATUS (3)
+#define OPCODE_ISCSI_INI_CFG_GET_CNTL_ATTRIBUTES (4)
+#define OPCODE_ISCSI_INI_CFG_GET_HBA_COUNT (5)
+#define SUBSYSTEM_ISCSI_INI_NTWK_GET_TCPIP_CONFIG (6)
+#define SUBSYSTEM_ISCSI_INI_NTWK_SET_TCPIP_CONFIG (6)
+#define SUBSYSTEM_ISCSI_INI_NTWK_GET_DHCP_STATUS (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_GET_CNTL_ATTRIBUTES (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_GET_HBA_COUNT (6)
+#define OPCODE_ISCSI_INI_CFG_GET_HBA_NAME (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_GET_HBA_NAME (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_SET_HBA_NAME (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_SET_HBA_TIME (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_GET_CHAP_SECRET (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_SET_CHAP_SECRET (6)
+#define SUBSYSTEM_ISCSI_INI_CFG_GET_HBA_STATUS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_ALL_SESSIONS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_SESSION_LIST (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_A_SESSION (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_ALL_CONNECTIONS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_CONFIGURATION (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_SET_CONFIGURATION (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_CONFIGURATION_LIST (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_MODIFY_SESSION_LOGINKEYS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_MODIFY_CONNECTION_LOGINKEYS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_ADD_CONNECTION_TO_SESSION (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_CLOSE_CONNECTION (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_LOGIN_TARGET (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_LOGOUT_TARGET (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_ALL_PLOGIN_TGTNAME_PORTAL (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_QUERY_A_PERSISTENT_LOGIN (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_QUERY_PERSISTENT_LOGINS (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_ADD_PERSISTENT_LOGIN (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_DELETE_PERSISTENT_LOGIN (6)
+#define SUBSYSTEM_ISCSI_INI_SESSION_GET_ALL_SESSION_ID (6)
+#define SUBSYSTEM_ISCSI_INI_DISCOVERY_GET_ALL_DISCOVERED_TARGET_ID (6)
+#define SUBSYSTEM_ISCSI_INI_DISCOVERY_REPORT_ALL_TARGETS (6)
+#define SUBSYSTEM_ISCSI_INI_DISCOVERY_REPORT_A_TARGET (6)
+#define SUBSYSTEM_ISCSI_INI_DISCOVERY_SEND_TARGETS (6)
+#define SUBSYSTEM_ISCSI_INI_RETRIEVE_PARSED_TARGET_INFO (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_REOPEN_A_SESSION (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_REOPEN_ALL_SESSIONS (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_REOPEN_A_CONN (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_DEL_ALL_NONPERSISTENT_SESSIONS (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_STORE_NONPERSISTENT_SESSIONS (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_LOGIN_ALL_SESSIONS (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_OFFLOAD_SESSION (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_INVALIDATE_CONNECTION (6)
+#define SUBSYSTEM_ISCSI_INI_DRIVER_OFFLOAD_CONN (6)
+#define SUBSYSTEM_ISCSI_INI_BTL_MAPPING_QUERY_OS_BT_INUSE (6)
+#define SUBSYSTEM_ISCSI_INI_BTL_MAPPING_MAX_OS_SUPPORTED_BTL (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_INSTANCE_STATISTICS (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_LOGIN_STATISTICS (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_SESSION_ATTRIBUTES (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_A_SESSION_STATISTICS (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_CONN_STATISTICS_PER_SESSION (6)
+#define SUBSYSTEM_ISCSI_INI_STATS_GET_IPSEC_STATISTICS (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_GET_BOOT_TARGET (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_SET_BOOT_TARGET (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_GET_BOOT_LUN (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_SET_BOOT_LUN (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_READ_WRITE (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_GET_BIOS_CONFIGURATION (6)
+#define SUBSYSTEM_ISCSI_INI_BOOT_SET_BIOS_CONFIGURATION (6)
+#define SUBSYSTEM_ISCSI_INI_SCSI_PASS_THRU (6)
+#define OPCODE_ISCSI_INI_CFG_SET_HBA_NAME (7)
+#define OPCODE_ISCSI_INI_CFG_SET_HBA_TIME (8)
+#define OPCODE_ISCSI_INI_CFG_GET_CHAP_SECRET (9)
+#define OPCODE_ISCSI_INI_CFG_SET_CHAP_SECRET (10)
+#define OPCODE_ISCSI_INI_CFG_GET_HBA_STATUS (11)
+#define OPCODE_ISCSI_INI_SESSION_GET_ALL_SESSIONS (12)
+#define OPCODE_ISCSI_INI_SESSION_GET_SESSION_LIST (13)
+#define OPCODE_ISCSI_INI_SESSION_GET_A_SESSION (14)
+#define OPCODE_ISCSI_INI_SESSION_GET_ALL_CONNECTIONS (15)
+#define OPCODE_ISCSI_INI_SESSION_GET_CONFIGURATION (16)
+#define OPCODE_ISCSI_INI_SESSION_SET_CONFIGURATION (17)
+#define OPCODE_ISCSI_INI_SESSION_GET_CONFIGURATION_LIST (18)
+#define OPCODE_ISCSI_INI_SESSION_MODIFY_SESSION_LOGINKEYS (19)
+#define OPCODE_ISCSI_INI_SESSION_MODIFY_CONNECTION_LOGINKEYS (20)
+#define OPCODE_ISCSI_INI_SESSION_ADD_CONNECTION_TO_SESSION (21)
+#define OPCODE_ISCSI_INI_SESSION_CLOSE_CONNECTION (22)
+#define OPCODE_ISCSI_INI_SESSION_LOGIN_TARGET (23)
+#define OPCODE_ISCSI_INI_SESSION_LOGOUT_TARGET (24)
+#define OPCODE_ISCSI_INI_SESSION_GET_ALL_PLOGIN_TGTNAME_PORTAL (25)
+#define OPCODE_ISCSI_INI_SESSION_QUERY_A_PERSISTENT_LOGIN (26)
+#define OPCODE_ISCSI_INI_SESSION_QUERY_PERSISTENT_LOGINS (27)
+#define OPCODE_ISCSI_INI_SESSION_ADD_PERSISTENT_LOGIN (28)
+#define OPCODE_ISCSI_INI_SESSION_DELETE_PERSISTENT_LOGIN (29)
+#define OPCODE_ISCSI_INI_SESSION_GET_ALL_SESSION_ID (30)
+#define OPCODE_ISCSI_INI_DISCOVERY_GET_ALL_DISCOVERED_TARGET_ID (31)
+#define OPCODE_ISCSI_INI_DISCOVERY_REPORT_ALL_TARGETS (32)
+#define OPCODE_ISCSI_INI_DISCOVERY_REPORT_A_TARGET (33)
+#define OPCODE_ISCSI_INI_DISCOVERY_SEND_TARGETS (34)
+#define OPCODE_ISCSI_INI_RETRIEVE_PARSED_TARGET_INFO (35)
+#define OPCODE_ISCSI_INI_DRIVER_REOPEN_A_SESSION (36)
+#define OPCODE_ISCSI_INI_DRIVER_REOPEN_ALL_SESSIONS (37)
+#define OPCODE_ISCSI_INI_DRIVER_REOPEN_A_CONN (38)
+#define OPCODE_ISCSI_INI_DRIVER_DEL_ALL_NONPERSISTENT_SESSIONS (39)
+#define OPCODE_ISCSI_INI_DRIVER_STORE_NONPERSISTENT_SESSIONS (40)
+#define OPCODE_ISCSI_INI_DRIVER_LOGIN_ALL_SESSIONS (41)
+#define OPCODE_ISCSI_INI_DRIVER_OFFLOAD_SESSION (42)
+#define OPCODE_ISCSI_INI_DRIVER_INVALIDATE_CONNECTION (43)
+#define OPCODE_ISCSI_INI_DRIVER_OFFLOAD_CONN (44)
+#define OPCODE_ISCSI_INI_BTL_MAPPING_QUERY_OS_BT_INUSE (45)
+#define OPCODE_ISCSI_INI_BTL_MAPPING_MAX_OS_SUPPORTED_BTL (46)
+#define OPCODE_ISCSI_INI_STATS_GET_INSTANCE_STATISTICS (47)
+#define OPCODE_ISCSI_INI_STATS_GET_LOGIN_STATISTICS (48)
+#define OPCODE_ISCSI_INI_STATS_GET_SESSION_ATTRIBUTES (49)
+#define OPCODE_ISCSI_INI_STATS_GET_A_SESSION_STATISTICS (50)
+#define OPCODE_ISCSI_INI_STATS_GET_CONN_STATISTICS_PER_SESSION (51)
+#define OPCODE_ISCSI_INI_STATS_GET_IPSEC_STATISTICS (52)
+#define OPCODE_ISCSI_INI_BOOT_GET_BOOT_TARGET (53)
+#define OPCODE_ISCSI_INI_BOOT_SET_BOOT_TARGET (54)
+#define OPCODE_ISCSI_INI_BOOT_GET_BOOT_LUN (55)
+#define OPCODE_ISCSI_INI_BOOT_SET_BOOT_LUN (56)
+#define OPCODE_ISCSI_INI_BOOT_READ_WRITE (57)
+#define OPCODE_ISCSI_INI_BOOT_GET_BIOS_CONFIGURATION (58)
+#define OPCODE_ISCSI_INI_BOOT_SET_BIOS_CONFIGURATION (59)
+#define OPCODE_ISCSI_INI_SCSI_PASS_THRU (60)
+
+
+/*
+ * --- ISCSI_TGT_SUBSYSTEM_OPCODES ---
+ * Opcodes in the IOCTL_SUBSYSTEM_ISCSI_TGT subsystem.
+ */
+#define OPCODE_ISCSI_TGT_START_LISTEN_SERVER (1)
+#define OPCODE_ISCSI_TGT_STOP_LISTEN_SERVER (2)
+#define OPCODE_ISCSI_TGT_GET_CONNECTION_INFO (3)
+#define OPCODE_ISCSI_TGT_CONNECTION_REJECT (4)
+#define OPCODE_ISCSI_TGT_OFFLOAD_CONNECTION (5)
+#define OPCODE_ISCSI_TGT_ISNS_SEND_PACKET (6)
+#define SUBSYSTEM_ISCSI_TGT_START_LISTEN_SERVER (7)
+#define SUBSYSTEM_ISCSI_TGT_STOP_LISTEN_SERVER (7)
+#define SUBSYSTEM_ISCSI_TGT_GET_CONNECTION_INFO (7)
+#define SUBSYSTEM_ISCSI_TGT_CONNECTION_REJECT (7)
+#define SUBSYSTEM_ISCSI_TGT_OFFLOAD_CONNECTION (7)
+#define SUBSYSTEM_ISCSI_TGT_ISNS_SEND_PACKET (7)
+#define OPCODE_ISCSI_TGT_INVALIDATE_CONNECTION (7)
+#define SUBSYSTEM_ISCSI_TGT_INVALIDATE_CONNECTION (7)
+#define SUBSYSTEM_ISCSI_TGT_ADD_IP_ADDR (7)
+#define SUBSYSTEM_ISCSI_TGT_DELETE_IP_ADDR (7)
+#define SUBSYSTEM_ISCSI_TGT_LIST_IP_ADDR (7)
+#define SUBSYSTEM_ISCSI_TGT_START_ESI_LISTEN (7)
+#define SUBSYSTEM_ISCSI_TGT_STOP_ESI_LISTEN (7)
+#define SUBSYSTEM_ISCSI_TGT_SLP_REGISTER (7)
+#define SUBSYSTEM_ISCSI_TGT_SLP_DEREGISTER (7)
+#define OPCODE_ISCSI_TGT_ADD_IP_ADDR (8)
+#define OPCODE_ISCSI_TGT_DELETE_IP_ADDR (9)
+#define OPCODE_ISCSI_TGT_LIST_IP_ADDR (10)
+#define OPCODE_ISCSI_TGT_START_ESI_LISTEN (11)
+#define OPCODE_ISCSI_TGT_STOP_ESI_LISTEN (12)
+#define OPCODE_ISCSI_TGT_SLP_REGISTER (13)
+#define OPCODE_ISCSI_TGT_SLP_DEREGISTER (14)
+
+
+/*
+ * --- MILI_PTL_SUBSYSTEM_OPCODES ---
+ * Opcodes in the IOCTL_SUBSYSTEM_MILI_PTL subsystem.
+ */
+#define OPCODE_MILI_PTL_CREATE_PORTAL (1)
+#define OPCODE_MILI_PTL_DELETE_PORTAL (2)
+#define OPCODE_MILI_PTL_CREATE_PORTAL_GROUP (3)
+#define OPCODE_MILI_PTL_DELETE_PORTAL_GROUP (4)
+#define OPCODE_MILI_PTL_ADD_PORTAL_TO_PORTAL_GROUP (5)
+#define OPCODE_MILI_PTL_DELETE_PORTAL_FROM_PORTAL_GROUP (6)
+#define OPCODE_MILI_PTL_ADD_TARGET (7)
+#define SUBSYSTEM_MILI_PTL_CREATE_PORTAL (8)
+#define SUBSYSTEM_MILI_PTL_DELETE_PORTAL (8)
+#define SUBSYSTEM_MILI_PTL_CREATE_PORTAL_GROUP (8)
+#define SUBSYSTEM_MILI_PTL_DELETE_PORTAL_GROUP (8)
+#define SUBSYSTEM_MILI_PTL_ADD_PORTAL_TO_PORTAL_GROUP (8)
+#define SUBSYSTEM_MILI_PTL_DELETE_PORTAL_FROM_PORTAL_GROUP (8)
+#define SUBSYSTEM_MILI_PTL_ADD_TARGET (8)
+#define OPCODE_MILI_PTL_DELETE_TARGET (8)
+#define SUBSYSTEM_MILI_PTL_DELETE_TARGET (8)
+#define SUBSYSTEM_MILI_PTL_ADD_PORTAL_GROUP_TO_TARGET (8)
+#define SUBSYSTEM_MILI_PTL_DELETE_PORTAL_GROUP_FROM_TARGET (8)
+#define SUBSYSTEM_MILI_PTL_SET_TARGET_LOGIN_PARAMS (8)
+#define SUBSYSTEM_MILI_PTL_START_LISTEN_SERVER (8)
+#define SUBSYSTEM_MILI_PTL_STOP_LISTEN_SERVER (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_INSTANCE_ATTRIBUTES (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_INSTANCE_SSN_ERROR_STATS (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_TARGET_ATTRIBUTES (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_TARGET_LOGIN_LOGOUT_STATS (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_SESSION_ATTRIBUTES_AND_STATS (8)
+#define SUBSYSTEM_MILI_PTL_MIB_GET_ISCSI_CONNECTION_ATTRIBUTES_AND_STATS (8)
+#define SUBSYSTEM_MILI_PTL_GET_ISCSI_SESSION_LIST (8)
+#define SUBSYSTEM_MILI_PTL_KILL_SESSION (8)
+#define OPCODE_MILI_PTL_ADD_PORTAL_GROUP_TO_TARGET (9)
+#define OPCODE_MILI_PTL_DELETE_PORTAL_GROUP_FROM_TARGET (10)
+#define OPCODE_MILI_PTL_SET_TARGET_LOGIN_PARAMS (11)
+#define OPCODE_MILI_PTL_START_LISTEN_SERVER (12)
+#define OPCODE_MILI_PTL_STOP_LISTEN_SERVER (13)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_INSTANCE_ATTRIBUTES (14)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_INSTANCE_SSN_ERROR_STATS (15)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_TARGET_ATTRIBUTES (16)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_TARGET_LOGIN_LOGOUT_STATS (17)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_SESSION_ATTRIBUTES_AND_STATS (18)
+#define OPCODE_MILI_PTL_MIB_GET_ISCSI_CONNECTION_ATTRIBUTES_AND_STATS (19)
+#define OPCODE_MILI_PTL_GET_ISCSI_SESSION_LIST (20)
+#define OPCODE_MILI_PTL_KILL_SESSION (21)
+
+/*
+ * --- MILI_TMD_SUBSYSTEM_OPCODES ---
+ * Opcodes in the IOCTL_SUBSYSTEM_MILI_TMD subsystem.
+ */
+#define OPCODE_MILI_TMD_ADD_TARGET (1)
+#define OPCODE_MILI_TMD_DELETE_TARGET (2)
+#define OPCODE_MILI_TMD_UPDATE_TARGET_AUTH_PARAMS (3)
+#define OPCODE_MILI_TMD_ADD_INITIATOR (4)
+#define OPCODE_MILI_TMD_DELETE_INITIATOR (5)
+#define OPCODE_MILI_TMD_UPDATE_INITIATOR_AUTH_PARAMS (6)
+#define OPCODE_MILI_TMD_BIND_INITIATOR_TO_TARGET (7)
+#define OPCODE_MILI_TMD_DELETE_IT_BINDING (8)
+#define SUBSYSTEM_MILI_TMD_ADD_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_DELETE_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_UPDATE_TARGET_AUTH_PARAMS (9)
+#define SUBSYSTEM_MILI_TMD_ADD_INITIATOR (9)
+#define SUBSYSTEM_MILI_TMD_DELETE_INITIATOR (9)
+#define SUBSYSTEM_MILI_TMD_UPDATE_INITIATOR_AUTH_PARAMS (9)
+#define SUBSYSTEM_MILI_TMD_BIND_INITIATOR_TO_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_DELETE_IT_BINDING (9)
+#define OPCODE_MILI_TMD_ACTIVATE_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_ACTIVATE_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_DEACTIVATE_TARGET (9)
+#define SUBSYSTEM_MILI_TMD_SET_INITIATOR_QOS (9)
+#define OPCODE_MILI_TMD_DEACTIVATE_TARGET (10)
+#define OPCODE_MILI_TMD_SET_INITIATOR_QOS (11)
+
+
+/*
+ * --- ETH_SUBSYSTEM_OPCODES ---
+ * These opcodes are used for configuring the Ethernet interfaces. These
+ * opcodes all use the IOCTL_SUBSYSTEM_ETH subsystem code.
+ */
+#define OPCODE_ETH_RSS_CONFIG (1)
+#define OPCODE_ETH_ACPI_CONFIG (2)
+#define SUBSYSTEM_ETH_RSS_CONFIG (3)
+#define SUBSYSTEM_ETH_ACPI_CONFIG (3)
+#define OPCODE_ETH_PROMISCUOUS (3)
+#define SUBSYSTEM_ETH_PROMISCUOUS (3)
+#define SUBSYSTEM_ETH_GET_STATISTICS (3)
+#define SUBSYSTEM_ETH_GET_RX_FRAG_SIZE (3)
+#define SUBSYSTEM_ETH_SET_RX_FRAG_SIZE (3)
+#define OPCODE_ETH_GET_STATISTICS (4)
+#define OPCODE_ETH_GET_RX_FRAG_SIZE (5)
+#define OPCODE_ETH_SET_RX_FRAG_SIZE (6)
+
+
+/*
+ * --- TPM_SUBSYSTEM_OPCODES ---
+ * These opcodes are used for configuring TCP protocol Module functionality.
+ * These opcodes all use the IOCTL_SUBSYSTEM_COMMON_ISCSI subsystem code.
+ */
+#define OPCODE_TPM_CONNECTION_OFFLOAD (1)
+#define OPCODE_TPM_CONNECTION_UPLOAD (2)
+#define OPCODE_TPM_CONNECTION_UPDATE (3)
+#define SUBSYSTEM_TPM_CONNECTION_OFFLOAD (4)
+#define SUBSYSTEM_TPM_CONNECTION_UPLOAD (4)
+#define SUBSYSTEM_TPM_CONNECTION_UPDATE (4)
+#define OPCODE_TPM_GET_STATISTICS (4)
+#define SUBSYSTEM_TPM_GET_STATISTICS (4)
+#define SUBSYSTEM_TPM_CONNECTION_QUERY (4)
+#define OPCODE_TPM_CONNECTION_QUERY (5)
+
+/*
+ * --- PXE_UNDI_SUBSYSTEM_OPCODES ---
+ * These opcodes are used for configuring PXE and UNDI functionality.
+ * These opcodes use the IOCTL_SUBSYSTEM_PXE_UNDI subsystem code.
+ */
+#define OPCODE_PXE_UNDI_CONTROL (1)
+#define OPCODE_PXE_UNDI_TRANSMIT (2)
+#define OPCODE_PXE_UNDI_RECEIVE (3)
+#define OPCODE_PXE_UNDI_GET_STATISTICS (4)
+#define SUBSYSTEM_PXE_UNDI_CONTROL (5)
+#define SUBSYSTEM_PXE_UNDI_TRANSMIT (5)
+#define SUBSYSTEM_PXE_UNDI_RECEIVE (5)
+#define SUBSYSTEM_PXE_UNDI_GET_STATISTICS (5)
+
+
+/*
+ * --- MCC_STATUS_CODE ---
+ * These are the global status codes used by all subsystems
+ */
+#define MCC_STATUS_SUCCESS (0) /* Indicates a successful
+ completion of the command */
+#define MCC_STATUS_INSUFFICIENT_PRIVILEGES (1) /* The client does not have
+ sufficient privileges to
+ execute the command */
+#define MCC_STATUS_INVALID_PARAMETER (2) /* A parameter in the command
+ was invalid. The extended
+ status contains the index
+ of the parameter */
+#define MCC_STATUS_INSUFFICIENT_RESOURCES (3) /* There are insufficient
+ chip resources to execute
+ the command */
+#define MCC_STATUS_QUEUE_FLUSHING (4) /* The command is completing
+ because the queue was
+ getting flushed */
+#define MCC_STATUS_DMA_FAILED (5) /* The command is completing
+ with a DMA error */
+
+/*
+ * --- MGMT_ERROR_CODES ---
+ * Error Codes returned in the status field of the IOCTL response header
+ */
+#define MGMT_STATUS_SUCCESS (0) /* The IOCTL completed
+ without errors */
+#define MGMT_STATUS_FAILED (1) /* Error status in the Status
+ field of the
+ IOCTL_RESPONSE_HEADER */
+#define MGMT_STATUS_ILLEGAL_REQUEST (2) /* Invalid IOCTL opcode */
+#define MGMT_STATUS_ILLEGAL_FIELD (3) /* Invalid parameter in
+ the IOCTL payload */
+/* The buffer provided by MILI is insufficient for Firmware/OSM to
+ * return IOCTL output. Firmware/OSM sets the buffer size requirement in
+ * the required_data_length field. Note: required_data_length must
+ * be larger than expected_data_length.
+ */
+#define MGMT_STATUS_INSUFFICIENT_BUFFER (4)
+/* This domain is not permitted to execute such request Applicable to
+ * BE-VM only
+ * */
+#define MGMT_STATUS_UNAUTHORIZED_REQUEST (5) /* This domain is not
+ permitted to */
+#define MGMT_STATUS_INVALID_ISNS_ADDRESS (10)
+#define MGMT_STATUS_INVALID_IPADDR (11)
+#define MGMT_STATUS_INVALID_GATEWAY (12)
+#define MGMT_STATUS_INVALID_SUBNETMASK (13)
+#define MGMT_STATUS_INVALID_PREFERRED_DNS (14)
+#define MGMT_STATUS_INVALID_ALTERNATE_DNS (15)
+#define MGMT_STATUS_INVALID_TARGET_IPADDR (16)
+#define MGMT_STATUS_UNRESOLVED_DNS_NAME (17)
+#define MGMT_STATUS_INVALID_ISCSI_INI_NAME (18)
+#define MGMT_STATUS_INVALID_ISCSI_INI_ALIAS (19)
+#define MGMT_STATUS_TGTTBL_FULL (20)
+#define MGMT_STATUS_LUNTBL_FULL (21)
+#define MGMT_STATUS_IPSEC_NOT_SUPPORTED (22)
+#define MGMT_STATUS_FLASHROM_SAVE_FAILED (23)
+#define MGMT_STATUS_FLASHROM_RESTORE_FAILED (24)
+#define MGMT_STATUS_INVALID_TCPPORT (25)
+#define MGMT_STATUS_ICCBINDEX_ALLOC_FAILED (26)
+#define MGMT_STATUS_IOCTLHANDLE_ALLOC_FAILED (27)
+#define MGMT_STATUS_INVALID_PHY_ADDR_FROM_OSM (28) /* Invalid physical
+ address from OSM */
+#define MGMT_STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM (29)
+#define MGMT_STATUS_ASSERT_FAILED (30)
+#define MGMT_STATUS_INVALID_SESSION (31) /* Invalid SESSION id */
+#define MGMT_STATUS_INVALID_CONNECTION (32) /* Invalid connection id */
+#define MGMT_STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT (33)
+#define MGMT_STATUS_BTL_TGTID_EXCEEDS_OSM_LIMIT (34)
+#define MGMT_STATUS_BTL_PATH_TGTID_OCCUPIED (35) /* In the OSM target
+ table the slot of the
+ specified Path and
+ TargetID is already
+ occupied by another
+ target. */
+#define MGMT_STATUS_BTL_NO_FREE_SLOT_PATH (36) /* OSM can't locate a free
+ slot in it's target table
+ for the specified path ID
+ */
+#define MGMT_STATUS_BTL_NO_FREE_SLOT_TGTID (37) /* OSM can't locate a free
+ slot in it's target table
+ for the specified target ID
+ */
+#define MGMT_STATUS_OSM_DEVSLOT_NOT_FOUND (38) /* OSM can't locate the entry
+ in it's target table for
+ the specified iSCSI
+ SESSION/target
+ */
+#define MGMT_STATUS_FLASHROM_READ_FAILED (39)
+#define MGMT_STATUS_POLL_IOCTL_TIMEOUT (40) /* Polling IOCTL is timeout */
+#define MGMT_STATUS_ERROR_ACITISCSI (41) /* Error returned from
+ ACIT-ISCSI module */
+#define MGMT_STATUS_ERROR_ACITMAIN (42) /* Error returned from
+ ACIT-Main module */
+/*
+ * This error indicates that ioctl buffer size is too big for either the
+ * OSM or OS to handle. In Windows, after MILI allocates the
+ * buffer, OS will forward the IOCTL request to the driver
+ * IF the IOCTL buffer size is less than / equal to the
+ * maximum IO size. When the OSM detects this situation,
+ * OSM set this status in the IOCTL header.
+ */
+#define MGMT_STATUS_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT (43)
+#define MGMT_STATUS_REBOOT_REQUIRED (44)
+#define MGMT_STATUS_INSUFFICIENT_TIMEOUT (45)
+#define MGMT_STATUS_IPADDR_NOT_SET (46)
+#define MGMT_STATUS_IPADDR_DUP_DETECTED (47)
+#define MGMT_STATUS_CANT_REMOVE_LAST_CONNECTION (48)
+#define MGMT_STATUS_TARGET_NOT_FOUND (48)
+#define MGMT_STATUS_TARGET_BUSY (49)
+#define MGMT_STATUS_TGT_ERR_LISTEN_SOCKET (50)
+#define MGMT_STATUS_TGT_ERR_BIND_SOCKET (51)
+#define MGMT_STATUS_TGT_ERR_NO_SOCKET (52)
+#define MGMT_STATUS_TGT_ERR_PORTAL_NOT_FOUND (53)
+#define MGMT_STATUS_TGT_ERR_IP_ADDR_MAX_REACHED (54)
+#define MGMT_STATUS_TGT_ERR_ISNS_COMM_FAILED (55)
+#define MGMT_STATUS_CANNOT_DELETE_BOOT_TARGET (56)
+#define MGMT_STATUS_TGT_PORTAL_MODE_IN_LISTEN (57)
+
+
+/*
+ * --- MGMT_ADDL_STATUS ---
+ * Values for the Additional Status field of IOCTL_RESPONSE_BUFFER. This field
+ */
+#define MGMT_ADDI_STATUS_NO_STATUS (0)
+#define MGMT_ADDI_STATUS_INVALID_IPTYPE (1)
+#define MGMT_ADDI_STATUS_IPV6_UNSUPPORTED (2)
+#define MGMT_ADDI_STATUS_DNSTEXT_TOO_LONG (3)
+#define MGMT_ADDI_STATUS_INVALID_INTR_ININAME (4)
+#define MGMT_ADDI_STATUS_INVALID_TGT_ININAME (5)
+#define MGMT_ADDI_STATUS_INVALID_ISNS_ININAME (6)
+#define MGMT_ADDI_STATUS_INVALID_INTR_ALIAS (7)
+#define MGMT_ADDI_STATUS_INVALID_TGT_ALIAS (8)
+#define MGMT_ADDI_STATUS_TARGET_HANDLE_NOT_FOUND (9)
+#define MGMT_ADDI_STATUS_SESSION_HANDLE_NOT_FOUND (10)
+#define MGMT_ADDI_STATUS_CONNECTION_HANDLE_NOT_FOUND (11)
+#define MGMT_ADDI_STATUS_PORTALGROUP_HANDLE_NOT_FOUND (12)
+#define MGMT_ADDI_STATUS_PORTAL_HANDLE_NOT_FOUND (13)
+#define MGMT_ADDI_STATUS_INVALID_INTR_PORT (14)
+#define MGMT_ADDI_STATUS_INVALID_TGT_PORT (15)
+#define MGMT_ADDI_STATUS_ACTIVE_SESSIONS_PRESENT (16)
+#define MGMT_ADDI_STATUS_SESSION_ALREADY_OPENED (17)
+#define MGMT_ADDI_STATUS_SESSION_ALREADY_CLOSED (18)
+#define MGMT_ADDI_STATUS_DEST_HOST_UNREACHABLE (19)
+#define MGMT_ADDI_STATUS_LOGIN_IN_PROGRESS (20)
+#define MGMT_ADDI_STATUS_TCP_CONNECT_FAILED (21)
+#define MGMT_ADDI_STATUS_INSUFFICIENT_RESOURCES (22)
+#define MGMT_ADDI_STATUS_LINK_DOWN (23)
+#define MGMT_ADDI_STATUS_DHCP_ERROR (24)
+#define MGMT_ADDI_STATUS_CONNECTION_OFFLOADED (25)
+#define MGMT_ADDI_STATUS_CONNECTION_NOT_OFFLOADED (26)
+#define MGMT_ADDI_STATUS_CONNECTION_UPLOAD_IN_PROGRESS (27)
+#define MGMT_ADDI_STATUS_REQUEST_REJECTED (28) /* Used to communicate
+ a flush or upload/close
+ request on a connection
+ was rejected by protocol
+ firmware.
+ */
+#define MGMT_ADDI_STATUS_INVALID_SUBSYSTEM (29)
+#define MGMT_ADDI_STATUS_INVALID_OPCODE (30)
+#define MGMT_ADDI_STATUS_INVALID_MAXCONNECTION_PARAM (31)
+#define MGMT_ADDI_STATUS_INVALID_KEY (32)
+#define MGMT_ADDI_STATUS_PORTAL_GROUP_BOUND_TO_TARGET (33)
+#define MGMT_ADDI_STATUS_PORTALS_BOUND_TO_PORTAL_GROUP (34) /* Unbind Portals
+ from Portal Group
+ before deleting */
+/* The domain number in the IOCTL header
+* is invalid or out-of-range. The domain number passed-in to the IOCTL
+* must be <= to the number of domains enabled by the manufacturer.Check the
+* response data from IOCTL_COMMON_GET_CNTL_ATTRIBUTES to
+* determine the actual number of domains supported
+*/
+#define MGMT_ADDI_STATUS_INVALID_DOMAIN (35)
+#define MGMT_ADDL_STATUS_TGT_CONN_RST (36)
+#define MGMT_ADDL_STATUS_TGT_INVALID_CONN_HANDLE (37)
+#define MGMT_ADDL_STATUS_TGT_INVALID_CID (38)
+#define MGMT_ADDL_STATUS_TGT_INVALID_CQID (39)
+#define MGMT_ADDL_STATUS_TGT_INVALID_CHUTE (40)
+#define MGMT_ADDL_STATUS_CONN_RST (41)
+#define MGMT_ADDL_STATUS_DUPLICATE_KEY (42)
+#define MGMT_ADDI_STATUS_LOGIN_INITIATOR_ERROR (43)
+#define MGMT_ADDI_STATUS_LOGIN_AUTHENTICATION_ERROR (44)
+#define MGMT_ADDI_STATUS_LOGIN_AUTHORIZATION_ERROR (45)
+#define MGMT_ADDI_STATUS_LOGIN_NOT_FOUND (46)
+#define MGMT_ADDI_STATUS_LOGIN_TARGET_REMOVED (47)
+#define MGMT_ADDI_STATUS_LOGIN_UNSUPPORTED_VERSION (48)
+#define MGMT_ADDI_STATUS_LOGIN_TOO_MANY_CONNECTIONS (49)
+#define MGMT_ADDI_STATUS_LOGIN_MISSING_PARAMETER (50)
+#define MGMT_ADDI_STATUS_LOGIN_NO_SESSION_SPANNING (51)
+#define MGMT_ADDI_STATUS_LOGIN_SESSION_TYPE_NOT_SUPPORTED (52)
+#define MGMT_ADDI_STATUS_LOGIN_SESSION_DOES_NOT_EXIST (53)
+#define MGMT_ADDI_STATUS_LOGIN_INVALID_DURING_LOGIN (54)
+#define MGMT_ADDI_STATUS_LOGIN_TARGET_ERROR (55)
+#define MGMT_ADDI_STATUS_LOGIN_SERVICE_UNAVAILABLE (56)
+#define MGMT_ADDI_STATUS_LOGIN_OUT_OF_RESOURCES (57)
+#define MGMT_ADDI_STATUS_SAME_CHAP_SECRET (58)
+#define MGMT_ADDI_STATUS_INVALID_SECRET_LENGTH (59)
+#define MGMT_ADDI_STATUS_DUPLICATE_ENTRY (60) /* an entry with same
+ attribtues already exists
+ with a different key */
+#define MGMT_ADDI_STATUS_INITIATOR_HANDLE_NOT_FOUND (61)
+#define MGMT_ADDI_STATUS_ITBINDING_HANDLE_NOT_FOUND (62)
+#define MGMT_ADDI_STATUS_SETTINGS_MODIFIED_REBOOT_REQD (63)
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_opcodes_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_defs.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_defs.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_defs.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_defs.h 2008-02-14 15:23:07.816204520 +0530
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_defs_amap_h__
+#define __ioctl_defs_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- IOCTLDEF_DEFINED_ENUMS --- */
+#define MGMT_MAX_CONNECTIONS_PER_SESSION (1)
+#define MGMT_MAX_INITIATOR_PORTALS (1)
+#define MGMT_MAX_NIC_PORTS (2)
+#define MGMT_MAX_ISCSI_PORTS (2)
+#define MGMT_MAX_PORTALS_PER_PG (4)
+#define MGMT_IPV4_ADDRESS_LEN (4)
+#define MGMT_IPV4_SUBNET_MASK_LEN (4)
+#define MGMT_MAX_DNS_SERVER (5)
+#define MGMT_MAX_MULTICAST_TIMEOUT_ENTRIES (5)
+#define MGMT_ISID_LENGTH (6)
+#define MGMT_MAX_SCSI_CHANNELS (8)
+#define MGMT_MAX_BOOTABLE_LUN (8)
+#define MGMT_LUN_SIZE (8)
+#define MGMT_IOCTL_MIN_SRB_TIMEOUT_VALUE (10)
+#define MGMT_DIGEST_KEY_LEN (12)
+#define MGMT_CHAP_SECRET_MIN_LEN (12)
+#define MGMT_MAX_ROUTE_ENTRIES (16)
+#define MGMT_CHAP_SECRET_LEN (16)
+#define MGMT_IPV6_ADDRESS_LEN (16)
+#define MGMT_IPV6_SUBNET_MASK_LEN (16)
+#define MGMT_MAX_CDB_LEN (16)
+#define MGMT_SENSE_BUFFER_LEN (18)
+#define MGMT_MAX_SG_COUNT (19)
+#define MGMT_SECURITY_KEY_LEN (30)
+#define MGMT_ISCSI_ALIAS_LEN (32)
+#define MGMT_MAX_MANUFACTURER_STRING (32)
+#define MGMT_MAX_MODEL_NUMBER_STRING (32)
+#define MGMT_MAX_CTLR_SERIALNO_STRING (32)
+#define MGMT_MAX_FLASHROM_VERSION_STRING (32)
+#define MGMT_MAX_FW_VERSION_STRING (32)
+#define MGMT_MAX_IP_VERSION_STRING (32)
+#define MGMT_MAX_ISCSI_VERSION_STRING (32)
+#define MGMT_MAX_BIOS_VERSION_STRING (32)
+#define MGMT_MAX_REDBOOT_VERSION_STRING (32)
+#define MGMT_MAX_DRV_VERSION_STRING (32)
+#define MGMT_MAX_INITIATOR_ALLOWED (32)
+#define MGMT_MAX_TGT_IP_SUPPORTED (32)
+#define MGMT_MAX_TARGETS_ALLOWED_USING_DISCOVERY (64)
+#define MGMT_MAX_ARP_ENTRIES (64)
+#define MGMT_DNS_NAME_LEN (64)
+#define MGMT_MAX_CTLR_DESCRIPTION_STRING (64)
+#define MGMT_MAX_PORTAL_GROUPS (128)
+#define MGMT_ISCSI_NAME_LEN (224)
+#define MGMT_ISNS_PORTAL_SYM_NAME_LEN (256)
+#define MGMT_CHAP_NAME_LEN (256)
+#define MGMT_SEND_TARGET_TEXTKEY (256)
+#define MGMT_MAX_SCOPE_LIST_LENGTH (256)
+#define MGMT_MAX_QUERY_LIST_LENGTH (256)
+#define MGMT_PRESHARED_KEYSIZE (256)
+#define MGMT_IPSEC_ID_SIZE (256)
+#define MGMT_MAX_TARGETS_ALLOWED (512)
+#define MGMT_MAX_LUNS (512)
+#define MGMT_MAX_HOST_TABLE (512)
+#define MGMT_MAX_ISCSI_SESSIONS_ALLOWED (512)
+#define MGMT_MAX_CONNECTIONS (512)
+#define MGMT_MAX_PORTALS (1024)
+#define MAX_SEEPROM_SIZE (1024)
+#define MGMT_MAX_IOCTL_PAYLOAD_SIZE (73728)
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_defs_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/host_struct.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/host_struct.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/host_struct.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/host_struct.h 2008-02-14 15:23:07.816204520 +0530
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __host_struct_amap_h__
+#define __host_struct_amap_h__
+#include "setypes.h"
+#include "headers.h"
+#include "be_cm.h"
+#include "be_common.h"
+#include "descriptors.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- EQ_COMPLETION_MAJOR_CODE_ENUM --- */
+#define EQ_MAJOR_CODE_COMPLETION (0) /* Completion event on a */
+ /* completion queue. */
+#define EQ_MAJOR_CODE_ETH (1) /* Affiliated Ethernet Event. */
+#define EQ_MAJOR_CODE_RESERVED (2) /* Reserved */
+#define EQ_MAJOR_CODE_RDMA (3) /* Affiliated RDMA Event. */
+#define EQ_MAJOR_CODE_ISCSI (4) /* Affiliated ISCSI Event */
+#define EQ_MAJOR_CODE_UNAFFILIATED (5) /* Unaffiliated Event */
+
+/* --- EQ_COMPLETION_MINOR_CODE_ENUM --- */
+#define EQ_MINOR_CODE_COMPLETION (0) /* Completion event on a */
+ /* completion queue. */
+#define EQ_MINOR_CODE_OTHER (1) /* Other Event (TBD). */
+
+/*
+ * --- ETH_EVENT_CODE ---
+ * These codes are returned by the MPU when one of these events has
+ * occurred, and the event is configured to report to an Event
+ * Queue when an event is detected.
+ */
+#define ETH_EQ_LINK_STATUS (0) /* Link status change event was */
+ /* detected. */
+#define ETH_EQ_WATERMARK (1) /* A watermark event was detected. */
+#define ETH_EQ_MAGIC_PKT (2) /* A magic packet event was detected. */
+#define ETH_EQ_ACPI_PKT0 (3) /* An ACPI interesting packet was */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT1 (3) /* An ACPI interesting packet was */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT2 (3) /* An ACPI interesting packet was */
+ /* detected. */
+#define ETH_EQ_ACPI_PKT3 (3) /* An ACPI interesting packet was */
+ /* detected. */
+
+/*
+ * --- ETH_TX_COMPL_STATUS_ENUM ---
+ * Status codes contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_VALID (0)
+#define ETH_COMP_ERROR (1)
+#define ETH_COMP_INVALID (15)
+
+/*
+ * --- ETH_TX_COMPL_PORT_ENUM ---
+ * Port indicator contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_PORT0 (0)
+#define ETH_COMP_PORT1 (1)
+#define ETH_COMP_MGMT (2)
+
+/*
+ * --- ETH_TX_COMPL_CT_ENUM ---
+ * Completion type indicator contained in Ethernet TX completion descriptors.
+ */
+#define ETH_COMP_ETH (0)
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __host_struct_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_common.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_common.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_common.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_common.h 2008-02-14 15:23:07.817204368 +0530
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __be_common_amap_h__
+#define __be_common_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/* Physical Address. */
+typedef struct {
+ BE_BIT lo[32]; /* DWORD 0 */
+ BE_BIT hi[32]; /* DWORD 1 */
+} SG_PACK BE_PHYS_ADDR_AMAP;
+typedef struct {
+ u32 dw[2];
+} PHYS_ADDR_AMAP, *PPHYS_ADDR_AMAP;
+
+/* Virtual Address. */
+typedef struct {
+ BE_BIT lo[32]; /* DWORD 0 */
+ BE_BIT hi[32]; /* DWORD 1 */
+} SG_PACK BE_VIRT_ADDR_AMAP;
+typedef struct {
+ u32 dw[2];
+} VIRT_ADDR_AMAP, *PVIRT_ADDR_AMAP;
+
+/* Scatter gather element. */
+typedef struct {
+ BE_BIT addr_hi[32]; /* DWORD 0 */
+ BE_BIT addr_lo[32]; /* DWORD 1 */
+ BE_BIT rsvd0[32]; /* DWORD 2 */
+ BE_BIT len[16]; /* DWORD 3 */
+ BE_BIT rsvd1[16]; /* DWORD 3 */
+} SG_PACK BE_SGE_AMAP;
+typedef struct {
+ u32 dw[4];
+} SGE_AMAP, *PSGE_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __be_common_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ep.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ep.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ep.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ep.h 2008-02-14 15:23:07.817204368 +0530
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ep_amap_h__
+#define __ep_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/* General Control and Status Register. */
+typedef struct {
+ BE_BIT m0_RxPbuf; /* DWORD 0 */
+ BE_BIT m1_RxPbuf; /* DWORD 0 */
+ BE_BIT m2_RxPbuf; /* DWORD 0 */
+ BE_BIT ff_en; /* DWORD 0 */
+ BE_BIT rsvd0[27]; /* DWORD 0 */
+ BE_BIT CPU_reset; /* DWORD 0 */
+} SG_PACK BE_EP_CONTROL_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} EP_CONTROL_CSR_AMAP, *PEP_CONTROL_CSR_AMAP;
+
+/* Semaphore Register. */
+typedef struct {
+ BE_BIT value[32]; /* DWORD 0 */
+} SG_PACK BE_EP_SEMAPHORE_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} EP_SEMAPHORE_CSR_AMAP, *PEP_SEMAPHORE_CSR_AMAP;
+
+/* Embedded Processor Specific Registers. */
+typedef struct {
+ BE_EP_CONTROL_CSR_AMAP ep_control;
+ BE_BIT rsvd0[32]; /* DWORD 1 */
+ BE_BIT rsvd1[32]; /* DWORD 2 */
+ BE_BIT rsvd2[32]; /* DWORD 3 */
+ BE_BIT rsvd3[32]; /* DWORD 4 */
+ BE_BIT rsvd4[32]; /* DWORD 5 */
+ BE_BIT rsvd5[8][128]; /* DWORD 6 */
+ BE_BIT rsvd6[32]; /* DWORD 38 */
+ BE_BIT rsvd7[32]; /* DWORD 39 */
+ BE_BIT rsvd8[32]; /* DWORD 40 */
+ BE_BIT rsvd9[32]; /* DWORD 41 */
+ BE_BIT rsvd10[32]; /* DWORD 42 */
+ BE_EP_SEMAPHORE_CSR_AMAP ep_semaphore;
+ BE_BIT rsvd11[32]; /* DWORD 44 */
+ BE_BIT rsvd12[19][32]; /* DWORD 45 */
+} SG_PACK BE_EP_CSRMAP_AMAP;
+typedef struct {
+ u32 dw[64];
+} EP_CSRMAP_AMAP, *PEP_CSRMAP_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ep_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/descriptors.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/descriptors.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/descriptors.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/descriptors.h 2008-02-14 15:23:07.818204216 +0530
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __descriptors_amap_h__
+#define __descriptors_amap_h__
+#include "setypes.h"
+#include "headers.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/*
+ * --- IPC_NODE_ID_ENUM ---
+ * IPC processor id values
+ */
+#define TPOST_NODE_ID (0) /* TPOST ID */
+#define TPRE_NODE_ID (1) /* TPRE ID */
+#define TXULP0_NODE_ID (2) /* TXULP0 ID */
+#define TXULP1_NODE_ID (3) /* TXULP1 ID */
+#define TXULP2_NODE_ID (4) /* TXULP2 ID */
+#define RXULP0_NODE_ID (5) /* RXULP0 ID */
+#define RXULP1_NODE_ID (6) /* RXULP1 ID */
+#define RXULP2_NODE_ID (7) /* RXULP2 ID */
+#define MPU_NODE_ID (15) /* MPU ID */
+
+/*
+ * --- MAC_ID_ENUM ---
+ * Meaning of the mac_id field in rxpp_eth_d
+ */
+#define PORT0_HOST_MAC0 (0) /* PD 0, Port 0, host networking, MAC 0. */
+#define PORT0_HOST_MAC1 (1) /* PD 0, Port 0, host networking, MAC 1. */
+#define PORT0_STORAGE_MAC0 (2) /* PD 0, Port 0, host storage, MAC 0. */
+#define PORT0_STORAGE_MAC1 (3) /* PD 0, Port 0, host storage, MAC 1. */
+#define PORT1_HOST_MAC0 (4) /* PD 0, Port 1 host networking, MAC 0. */
+#define PORT1_HOST_MAC1 (5) /* PD 0, Port 1 host networking, MAC 1. */
+#define PORT1_STORAGE_MAC0 (6) /* PD 0, Port 1 host storage, MAC 0. */
+#define PORT1_STORAGE_MAC1 (7) /* PD 0, Port 1 host storage, MAC 1. */
+#define FIRST_VM_MAC (8) /* PD 1 MAC. Protection domains have IDs */
+ /* from 0x8-0x26, one per PD. */
+#define LAST_VM_MAC (38) /* PD 31 MAC. */
+#define MGMT_MAC (39) /* Management port MAC. */
+#define MARBLE_MAC0 (59) /* Used for flushing function 0 receive */
+ /*
+ * queues before re-using a torn-down
+ * receive ring. the DA =
+ * 00-00-00-00-00-00, and the MSB of the
+ * SA = 00
+ */
+#define MARBLE_MAC1 (60) /* Used for flushing function 1 receive */
+ /*
+ * queues before re-using a torn-down
+ * receive ring. the DA =
+ * 00-00-00-00-00-00, and the MSB of the
+ * SA != 00
+ */
+#define NULL_MAC (61) /* Promiscuous mode, indicates no match */
+#define MCAST_MAC (62) /* Multicast match. */
+#define BCAST_MATCH (63) /* Broadcast match. */
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __descriptors_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_cm.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_cm.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_cm.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/be_cm.h 2008-02-14 15:23:07.818204216 +0530
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __be_cm_amap_h__
+#define __be_cm_amap_h__
+#include "setypes.h"
+#include "headers.h"
+#include "be_common.h"
+#include "common_context.h"
+#include "etx_context.h"
+#include "mpu_context.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/*
+ * --- CEV_WATERMARK_ENUM ---
+ * CQ/EQ Watermark Encodings. Encoded as number of free entries in
+ * Queue when Watermark is reached.
+ */
+#define CEV_WMARK_0 (0) /* Watermark when Queue full */
+#define CEV_WMARK_16 (1) /* Watermark at 16 free entries */
+#define CEV_WMARK_32 (2) /* Watermark at 32 free entries */
+#define CEV_WMARK_48 (3) /* Watermark at 48 free entries */
+#define CEV_WMARK_64 (4) /* Watermark at 64 free entries */
+#define CEV_WMARK_80 (5) /* Watermark at 80 free entries */
+#define CEV_WMARK_96 (6) /* Watermark at 96 free entries */
+#define CEV_WMARK_112 (7) /* Watermark at 112 free entries */
+#define CEV_WMARK_128 (8) /* Watermark at 128 free entries */
+#define CEV_WMARK_144 (9) /* Watermark at 144 free entries */
+#define CEV_WMARK_160 (10) /* Watermark at 160 free entries */
+#define CEV_WMARK_176 (11) /* Watermark at 176 free entries */
+#define CEV_WMARK_192 (12) /* Watermark at 192 free entries */
+#define CEV_WMARK_208 (13) /* Watermark at 208 free entries */
+#define CEV_WMARK_224 (14) /* Watermark at 224 free entries */
+#define CEV_WMARK_240 (15) /* Watermark at 240 free entries */
+
+/*
+ * --- CQ_CNT_ENUM ---
+ * Completion Queue Count Encodings.
+ */
+#define CEV_CQ_CNT_256 (0) /* CQ has 256 entries */
+#define CEV_CQ_CNT_512 (1) /* CQ has 512 entries */
+#define CEV_CQ_CNT_1024 (2) /* CQ has 1024 entries */
+
+/*
+ * --- EQ_CNT_ENUM ---
+ * Event Queue Count Encodings.
+ */
+#define CEV_EQ_CNT_256 (0) /* EQ has 256 entries (16-byte EQEs only) */
+#define CEV_EQ_CNT_512 (1) /* EQ has 512 entries (16-byte EQEs only) */
+#define CEV_EQ_CNT_1024 (2) /* EQ has 1024 entries (4-byte or */
+ /* 16-byte EQEs only) */
+#define CEV_EQ_CNT_2048 (3) /* EQ has 2048 entries (4-byte or */
+ /* 16-byte EQEs only) */
+#define CEV_EQ_CNT_4096 (4) /* EQ has 4096 entries (4-byte EQEs only) */
+
+/*
+ * --- EQ_SIZE_ENUM ---
+ * Event Queue Entry Size Encoding.
+ */
+#define CEV_EQ_SIZE_4 (0) /* EQE is 4 bytes */
+#define CEV_EQ_SIZE_16 (1) /* EQE is 16 bytes */
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __be_cm_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/headers.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/headers.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/headers.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/headers.h 2008-02-14 15:23:07.819204064 +0530
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __headers_amap_h__
+#define __headers_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/*
+ * --- ISCSI_OPCODE ---
+ * ISCSI Message Opcode Definitions Vendor Specific Initiator
+ * 0x1c-0x1e Vendor Specific Target 0x3c-0x3e
+ */
+#define ISCSI_OPCODE_NOP_OUT (0)
+#define ISCSI_OPCODE_SCSI_CMD (1)
+#define ISCSI_OPCODE_SCSI_TASK_MGMT (2)
+#define ISCSI_OPCODE_LOGIN (3)
+#define ISCSI_OPCODE_TEXT (4)
+#define ISCSI_OPCODE_SCSI_DATA_OUT (5)
+#define ISCSI_OPCODE_LOGOUT (6)
+#define ISCSI_OPCODE_SNACK (16)
+#define ISCSI_OPCODE_NOP_IN (32)
+#define ISCSI_OPCODE_NOPIN (32)
+#define ISCSI_OPCODE_SCSI_RESPONSE (33)
+#define ISCSI_OPCODE_RESPONSE (33)
+#define ISCSI_OPCODE_SCSI_TASK_MGMT_RESPONSE (34)
+#define ISCSI_OPCODE_LOGIN_RESPONSE (35)
+#define ISCSI_OPCODE_TEXT_RESPONSE (36)
+#define ISCSI_OPCODE_SCSI_DATA_IN (37)
+#define ISCSI_OPCODE_DATAIN (37)
+#define ISCSI_OPCODE_LOGOUT_RESPONSE (38)
+#define ISCSI_OPCODE_R2T (49)
+#define ISCSI_OPCODE_RTT (49)
+#define ISCSI_OPCODE_ASYNC_MSG (50)
+#define ISCSI_OPCODE_REJECT (63)
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __headers_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_top.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_top.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_top.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_top.h 2008-02-14 15:23:07.819204064 +0530
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_top_amap_h__
+#define __ioctl_top_amap_h__
+#include "setypes.h"
+#include "asyncmesg.h"
+#include "ioctl_opcodes.h"
+#include "ioctl_defs.h"
+#include "ioctl_types.h"
+#include "ioctl_mcc.h"
+#include "ioctl_common.h"
+#include "ioctl_eth.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_top_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_types.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_types.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_types.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_types.h 2008-02-14 15:23:07.820203912 +0530
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_types_amap_h__
+#define __ioctl_types_amap_h__
+#include "setypes.h"
+#include "ioctl_defs.h"
+#include "host_struct.h"
+#include "post_codes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/*
+ * --- IPVERSIONS ---
+ * Defintion for IPVersion in IP_ADDRESS_SUBNET_FORMAT and IP_ADDRESS_FORMAT
+ */
+#define IPVERSION_V4 (0)
+#define IPVERSION_V6 (1)
+
+
+/* --- MGMT_TGT_TMF_METHODS --- */
+#define MGMT_TMF_METHOD_LU_RESET (5)
+#define MGMT_TMF_METHOD_TGT_WARM_RESET (6)
+#define MGMT_TMF_METHOD_TGT_COLD_RESET (7)
+
+/*
+ * --- MGMT_TMF_METHODS ---
+ * Other TMF methods specified in RFC3720, not currently supported
+ */
+#define MGMT_TMF_METHOD_ABORT_TASK (1)
+#define MGMT_TMF_METHOD_ABORT_TASK_SET (2)
+#define MGMT_TMF_METHOD_CLEAR_ACA (3)
+#define MGMT_TMF_METHOD_CLEAR_TASK_SET (4)
+#define MGMT_TMF_METHOD_TASK_REASSIGN (8)
+
+/*
+ * --- LOGIN_TARGET_PARAMS_FLAGS ---
+ * Bit definition of login_flags in LOGIN_TARGET_PARAMS_IN
+ */
+#define MGMT_LOGIN_FLAG_NO_IPSEC (0)
+#define MGMT_LOGIN_FLAG_REQUIRE_IPSEC (1)
+#define MGMT_LOGIN_FLAG_MULTIPATH_ENABLED (2)
+
+/* --- MGMT_SESSION_STATUS --- */
+#define MGMT_SESSION_STATUS_OPENED (1) /* Session login success */
+#define MGMT_SESSION_STATUS_OPENNING (2) /* Should be ignored by
+ application */
+#define MGMT_SESSION_STATUS_LUN_REPORTING (4) /* Should be ignored by
+ application */
+#define MGMT_SESSION_STATUS_LUN_REPORTED (8) /* Should be ignored by
+ application */
+#define MGMT_SESSION_STATUS_CLOSING (16) /* Should be ignored by
+ application */
+#define MGMT_SESSION_STATUS_CLOSED (32) /* Session logged out success */
+#define MGMT_SESSION_STATUS_CLOSED_IN_RECOVERY (64) /* Should be ignored
+ by application */
+#define MGMT_SESSION_STATUS_IN_DEVICE_RESET (128) /* Should be ignored
+ by application */
+#define MGMT_SESSION_STATUS_OPEN_FAILED (256) /* Login failed */
+#define MGMT_SESSION_STATUS_SENDTARGET_FAILED (512) /* SendTarget command
+ failed */
+#define MGMT_SESSION_STATUS_REPORTLUN_FAILED (1024) /* REPORT_LUN command
+ failed */
+#define MGMT_SESSION_STATUS_CLOSE_FAILED (2048) /* Logout failed */
+#define MGMT_SESSION_STATUS_IN_RETRY (4096) /* This session is in
+ retry queue */
+#define MGMT_SESSION_STATUS_DELETED (8192) /* This session marked as
+ deleted */
+
+/* --- MGMT_SESSION_FLAGS --- */
+#define MGMT_SESSION_FLAG_NON_PERSISTENT (1)
+#define MGMT_SESSION_FLAG_PERSISTENT (2)
+/* Either MGMT_SESSION_FLAG_BOOTABLE_PRIMARY or
+ * MGMT_SESSION_FLAG_BOOTABLE_SECONDARY should be set
+ */
+#define MGMT_SESSION_FLAG_BOOTABLE_PRIMARY (4)
+#define MGMT_SESSION_FLAG_BOOTABLE_SECONDARY (8)
+#define MGMT_SESSION_FLAG_RESERVED (16)
+#define MGMT_SESSION_FLAG_DISCOVERY (16)
+#define MGMT_SESSION_FLAG_INFORMATIONAL (32)
+#define MGMT_SESSION_FLAG_DATA_SESSION (64)
+#define MGMT_SESSION_FLAG_LIST_SESSION (128) /* if set to 1, all targets
+ are returned else only logged
+ in targets are returned
+ */
+
+/*
+ * --- SESSION_TYPE ---
+ * Session Type
+ */
+#define MGMT_SESSION_TYPE_DISCOVERY_SESSION (16) /* Discovery session
+ LUNs are NOT exposed
+ to the host OS */
+#define MGMT_SESSION_TYPE_INFORMATIONAL_SESSION (32) /* Informational
+ session LUNs are NOT
+ exposed to the host
+ OS */
+#define MGMT_SESSION_TYPE_DATA_SESSION (64) /* Data session. LUNs are
+ exposed to the host OS
+ */
+#define MGMT_SESSION_TYPE_BOOT_SESSION (128) /* Boot session */
+#define MGMT_SESSION_TYPE_MASK_SESSION_TYPE (240)
+
+/*
+ * --- MGMT_SESSION_OWNER ---
+ * Application should ignore these bits. These bits are used by
+ * the host driver.
+ */
+#define MGMT_SESSION_FLAG_DRIVER_OWNED (4096) /* This indicates session
+ owned by the driver
+ */
+#define MGMT_SESSION_FLAG_FIRMWARE_OWNED (8192) /* This indicates session
+ owned by the firmware */
+
+/*
+ * --- MGMT_CONN_STATUS ---
+ * Bit definition in connection_status in MGMT_CONN_INFO
+ */
+#define MGMT_CONN_STATUS_OPENED (1) /* TCP connection is opened. All */
+ /*
+ * MGMT_CONN_STATUS_ISCSI_LOGIN_STATE
+ * valid ONLY if
+ * MGMT_CONN_STATUS_OPENED is 1
+ */
+#define MGMT_CONN_STATUS_OPENNING (2) /* Should be ignored by
+ application */
+#define MGMT_CONN_STATUS_REDIRECTED (4) /* The iSCSI login is
+ redirected. */
+#define MGMT_CONN_STATUS_REDIRECTED_PERM (8) /* Valid only if */
+ /*
+ * MGMT_CONN_STATUS_REDIRECTED
+ * bit is 1 When this bit is set,
+ * the iSCSI login is redirected
+ * permanently else the iSCSI
+ * login is redirected
+ * temporarily
+ */
+#define MGMT_CONN_STATUS_ISCSI_LOGIN_STATE_INI (16) /* 1: Initial login
+ state as defined
+ in iSCSI spec */
+#define MGMT_CONN_STATUS_ISCSI_LOGIN_STATE_SEC (32) /* 1: Security login
+ state as defined in
+ iSCSI spec */
+#define MGMT_CONN_STATUS_ISCSI_LOGIN_STATE_OPR (64) /* 1: Operational
+ login state as defined
+ in iSCSI spec */
+#define MGMT_CONN_STATUS_ISCSI_LOGIN_STATE_FULL (128) /* 1: Full login state
+ as defined in iSCSI
+ spec */
+#define MGMT_CONN_STATUS_CLOSING (256) /* Should be ignored by
+ application */
+#define MGMT_CONN_STATUS_CLOSED (512) /* Connection logged out
+ success */
+#define MGMT_CONN_STATUS_CLOSED_IN_RECOVERY (1024) /* TCP connection is
+ closed for recovery
+ purpose */
+#define MGMT_CONN_STATUS_OPEN_FAILED (2048) /* Login failed */
+#define MGMT_CONN_STATUS_CLOSE_FAILED (4096) /* Logout failed */
+
+/*
+ * --- MGMT_CONNECTION_OWNER ---
+ * Application should ignore these bits. These bits are used
+ * by the host driver.
+ */
+#define MGMT_CONN_FLAG_DRIVER_OWNED (4096) /* This indicates connection
+ owned by the driver */
+#define MGMT_CONN_FLAG_FIRMWARE_OWNED (8192) /* This indicates connection
+ owned by the firmware */
+
+/*
+ * --- MGMT_CONN_LOGIN_OPTIONS_FLAG ---
+ * Bitmap definitions for "flags" in MGMT_CONN_LOGIN_OPTIONS
+ */
+#define MGMT_CONN_LOGIN_OPTIONS_FLAG_IPSEC_ENABLED (1)
+#define MGMT_CONN_LOGIN_OPTIONS_FLAG_DIGEST_CRC32 (2)
+#define MGMT_CONN_LOGIN_OPTIONS_FLAG_LEADING (4)
+
+/*
+ * --- MGMT_SESSION_LOGIN_OPTIONS_FLAGS ---
+ * Bitmap defintions for flags in MGMT_SESSION_LOGIN_OPTIONS
+ */
+#define MGMT_SESSION_LOGIN_OPTIONS_FLAG_INIT_R2T (1) /* Initial R2T -
+ 0: disabled
+ 1: enabled */
+#define MGMT_SESSION_LOGIN_OPTIONS_FLAG_IMMEDIATE_DATA (2) /* ImmediateData -
+ 0: disabled
+ 1: enabled */
+#define MGMT_SESSION_LOGIN_OPTIONS_FLAG_DPDU_INORDER (4) /* Data PDU In order -
+ 0: disabled
+ 1: enabled */
+#define MGMT_SESSION_LOGIN_OPTIONS_FLAG_DSEQ_INORDER (8) /* Data Sequence
+ In order -
+ 0: disabled
+ 1: enabled */
+
+/* --- DEFAULT_MAX_BURST_LENGTH_DEFINE --- */
+#define DEFAULT_MAX_BURST_LENGTH (262144)
+
+/* --- DEFAULT_MAX_OUTSTANDING_R2T_DEFINE --- */
+#define DEFAULT_MAX_OUTSTANDING_R2T (1)
+
+
+/*
+ * --- MGMT_DEV_ADDR_MODE ---
+ * Definition of device addressing mode
+ */
+#define MGMT_DEV_ADDR_MODE_PERIPHERAL (0)
+#define MGMT_DEV_ADDR_MODE_FLAT_SPACE (1)
+#define MGMT_DEV_ADDR_MODE_LOGICAL_UNIT (2)
+#define MGMT_DEV_ADDR_MODE_EXTENDED_LOGICAL_UNIT (3)
+#define MGMT_DEV_ADDR_MODE_CUSTOM (4)
+
+/* --- MGMT_UNASSIGNED_OS_BTL_VALUE_ENUM --- */
+#define MGMT_UNASSIGNED_OS_BTL_VALUE (65535) /* No OS BTL value is
+ assigned */
+/*
+ * --- MGMT_SLP_PARAMS_FLAG ---
+ * Bitmap definition for flags in MGMT_SLP_PARAMS
+ */
+#define MGMT_SLP_PARAMS_FLAG_DISABLE (0) /* SLP Discovery disabled */
+#define MGMT_SLP_PARAMS_FLAG_MULTICAST (0) /* Multicast */
+#define MGMT_SLP_PARAMS_FLAG_NOSECURITY (0) /* Security disabled */
+#define MGMT_SLP_PARAMS_FLAG_ENABLE (1) /* SLP Discovery enabled */
+#define MGMT_SLP_PARAMS_FLAG_BROADCAST (2) /* Broadcast */
+#define MGMT_SLP_PARAMS_FLAG_SECURITY (4) /* Security enabled */
+
+/*
+ * --- MGMT_ISNS_FLAG_CONFIG ---
+ * Definition of flags in MGMT_ISNS_PARAMS
+ */
+#define MGMT_ISNS_FLAG_CONFIG_DISABLE (0) /* iSNS Discovery disabled */
+#define MGMT_ISNS_FLAG_CONFIG_ENABLE (1) /* iSNS Discovery enabled */
+/* The iSNS server settings are configured manually. If this bit is
+* set, the following must not be set - MGMT_ISNS_FLAG_CONFIG_VIA_HEARTBEAT -
+* MGMT_ISNS_FLAG_CONFIG_VIA_DHCP - MGMT_ISNS_FLAG_CONFIG_VIA_SLP
+*/
+#define MGMT_ISNS_FLAG_CONFIG_MANUAL (16)
+/* The iSNS server settings are configured via heartbeat mechanism.
+* If this bit is set, the following must not be set -
+* MGMT_ISNS_FLAG_CONFIG_MANUAL - MGMT_ISNS_FLAG_CONFIG_VIA_DHCP -
+* MGMT_ISNS_FLAG_CONFIG_VIA_SLP
+*/
+#define MGMT_ISNS_FLAG_CONFIG_VIA_HEARTBEAT (32)
+/* The iSNS server settings are configured via DHCP If this bit is
+* set, the following must not be set - MGMT_ISNS_FLAG_CONFIG_MANUAL -
+* MGMT_ISNS_FLAG_CONFIG_VIA_HEARTBEAT - MGMT_ISNS_FLAG_CONFIG_VIA_SLP
+*/
+#define MGMT_ISNS_FLAG_CONFIG_VIA_DHCP (64)
+#define MGMT_ISNS_FLAG_CONFIG_VIA_SLP (128)
+
+/* --- IOCTL_TYPES_DEFINED_ENUMS --- */
+#define MGMT_ISNS_MAX_SERVER_COUNT (4)
+#define MGMT_ISNS_WELL_KNOWN_TCP_PORT (3205)
+#define MGMT_ISNS_WELL_KNOWN_UDP_PORT (3205)
+
+/* --- ISNS_SERVER_DISCOVERY_MODES --- */
+#define ISNS_SERVER_DISCOVERY_MODE_DHCP (1) /* Use DHCP to locate iSNS
+ servers */
+#define ISNS_SERVER_DISCOVERY_MODE_SLP (2) /* Use SLP to discover iSNS
+ Servers */
+
+
+/*
+ * --- MGMT_DHCP_FLAGS ---
+ * Bit field definition of dhcp_flags in MGMT_TCPIP_CONFIGURATION
+ */
+#define MGMT_DHCP_FLAG_DISABLE_DHCP (0)
+#define MGMT_DHCP_FLAG_FORCED_RELEASED (1)
+#define MGMT_DHCP_FLAG_FORCED_RENEW (2)
+#define MGMT_DHCP_FLAG_ENABLE_DHCP (4) /* enable DHCP */
+
+/*
+ * --- MGMT_SUPPORTED_IPVERSIONS ---
+ * Bit definition of support_ipversions
+ */
+#define MGMT_SUPPORTED_IPVERSION_BIT_V4 (1) /* 0=IPV4 is not supported,
+ 1=IPV4 is supported */
+#define MGMT_SUPPORTED_IPVERSION_BIT_V6 (2) /* 0=IPV6 is not supported,
+ 1=IPV6 is supported */
+
+/*
+ * --- MGMT_TCPIPCONFIG_RSVD_FLAG ---
+ * Bit definition of reserved_flags in MGMT_TCPIP_CONFIGURATION
+ */
+/* When set to 0, after the firmware change the HBA IP address, the
+* firmware does NOT need to reconnect all the sessions
+* that is currently closed due to session recovery.
+*/
+#define MGMT_TCPIPCONFIG_RSVD_FLAG_DONOT_RECONNECT_CLOSED_SESSIONS (0)
+/* Only applicable in IOCTL_SET_TCPIP_CONFIG operation. It is not
+ * applicable in IOCTL_GET_TCPIP_CONFIG . When set, after the
+ * firmware change the HBA IP address, the firmware needs to
+ * reconnect all the sessions that is currently closed due
+ * to session recovery. * This only applicable to sessions that has
+ * the status with MGMT_SESSION_STATUS_CL * OSED_IN_RECOVERY = 1.
+ */
+#define MGMT_TCPIPCONFIG_RSVD_FLAG_RECONNECT_CLOSED_SESSIONS (1)
+
+/*
+ * --- MGMT_PORT_SPEED ---
+ * Definition of speed and max_speed in MGMT_NIC_PORT_INFO
+ */
+#define MGMT_PORT_SPEED_NOT_AVAILABLE (0)
+#define MGMT_PORT_SPEED_TEN_BASE_T (1)
+#define MGMT_PORT_SPEED_HUNDRED_BASE_T (2)
+#define MGMT_PORT_SPEED_GIGABIT (3)
+#define MGMT_PORT_SPEED_TEN_GIGABIT (4)
+
+/*
+ * --- MGMT_LINK_STATE ---
+ * Definition of link_state in MGMT_NIC_PORT_INFO
+ */
+#define MGMT_LINK_STATE_DOWN (0)
+#define MGMT_LINK_STATE_UP (1)
+
+/*
+ * --- MGMT_HBA_SUPPORT ---
+ * Bit map definition for functionalities_supported in MGMT_HBA_ATTRIBUTES
+ */
+#define MGMT_HBA_SUPPORT_PRESHARED_KEY_CACHE (1)
+#define MGMT_HBA_SUPPORT_ISCSI_AUTHENTICATION_CACHE (2)
+#define MGMT_HBA_SUPPORT_IPSEC_TUNNEL_MODE (4)
+#define MGMT_HBA_SUPPORT_CHAP_VIA_RADIUS (8)
+#define MGMT_HBA_SUPPORT_ISNS_DISCOVERY (16)
+#define MGMT_HBA_SUPPORT_SLP_DISCOVERY (32)
+#define MGMT_HBA_SUPPORT_BIDISCSICMDS (64)
+#define MGMT_HBA_SUPPORT_DNS (128)
+
+/*
+ * --- MGMT_HBA_STATUS ---
+ * Definitions for hba_status in MGMT_HBA_ATTRIBUTES
+ */
+#define MGMT_HBA_STATUS_WORKING (0) /* The ARM is currently running
+ the primary firmware image */
+#define MGMT_HBA_STATUS_DEGRADED (1) /* The ARM is currently
+ running the secondary firmware
+ image. */
+#define MGMT_HBA_STATUS_CRITICAL (2)
+#define MGMT_HBA_STATUS_FAILED (3)
+
+/* --- VLD_STATUS_ENUM --- */
+#define VLD_DISABLED (0)
+#define VLD_ENABLED (1)
+
+/* --- ASIC_REV_ENUM --- */
+#define ASIC_REV_A0 (0)
+#define ASIC_REV_A1 (1)
+
+
+/*
+ * --- MGMT_HBA_IF_TYPES ---
+ * Controller Attributes
+ */
+#define MGMT_HBA_IF_TYPE_INITIATOR (1)
+#define MGMT_HBA_IF_TYPE_TARGET (2)
+
+
+/*
+ * --- FLASHROM_OFFSET ---
+ * Offsets for all components on Flash.
+ */
+#define FLASH_LPCISM_REGISTERS (0)
+#define FLASH_REDBOOT_START (32768)
+#define FLASH_REDBOOT_SPARE (262144)
+#define FLASH_FAT_START (524288)
+#define FLASH_UFI_COPYRIGHT_DIR (786432)
+#define FLASH_DEBUG_PRINT_START (917504)
+#define FLASH_PRIMARY_IMAGE_START (1048576)
+#define FLASH_BACKUP_IMAGE_START (3670016)
+#define FLASH_CFG_INI_START (6291456)
+#define FLASH_CFG_IPSEC_XML_START (7077888)
+#define FLASH_CFG_IPSEC_CERT_START (7208960)
+#define FLASH_BIOS_START (7340032)
+#define FLASH_BIOS_CTRL_S_START (7372800)
+#define FLASH_PXE_BIOS_START (7602176)
+#define FLASH_EVENTLOG_START (7864320)
+#define FLASH_REDBOOT_CONFIG (8126464)
+#define FLASH_REDBOOT_DIRECTORY (8257536)
+
+/* --- FLASHROM_FIRMWARE_DEFINES --- */
+#define FLASH_IMAGE_ENTRY (262144) /* Entry point of firmware image */
+#define FLASH_CFG_INI_CONFIG_SIZE (786432) /* Initiator Config Size is
+ 1M - 256K */
+#define FLASH_IMAGE_MAX_SIZE (3145728) /* Maximum firmware image size */
+
+/* --- FLASHROM_FIS_DEFINES --- */
+#define FIS_PRIMARY_IMAGE_INDEX (3)
+#define FIS_BACKUP_IMAGE_INDEX (4)
+#define FIS_DIR_ENTRY_SIZE (256)
+#define FIS_DIR_SIZE (1280)
+#define FIS_CONFIG_SIZE (4096)
+
+/* --- FLASHROM_EVENTLOG_DEFINES --- */
+#define FLASH_EVENTLOG_SECTOR_CNT (2)
+
+/* --- FLASHROM_FAT_DEFINES --- */
+#define FLASH_FAT_SIZE (262144)
+
+
+/* --- FLASHROM_UFI_DEFINES --- */
+#define FLASH_UFI_SIGNATURE_SIZE (32)
+#define FLASH_UFI_HEADER_SIZE (96)
+#define FLASH_UFI_BIN_SIZE (8388608)
+/* --- IMAGE_ENTRY_TYPE --- */
+#define IMAGE_OPTION_ROM (32) /* contains iscsi+pxe bios */
+#define IMAGE_MGMT_FIRMWARE (160)
+#define IMAGE_FIRMWARE_COMP (161)
+#define IMAGE_FIRMWARE_BACKUP (176)
+#define IMAGE_FIRMWARE_BACKUP_COMP (177) /* contains backup firmware
+ compressed */
+#define IMAGE_BOOT_CODE (224)
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_types_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_common.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_common.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_common.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_common.h 2008-02-14 15:23:07.821203760 +0530
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_common_amap_h__
+#define __ioctl_common_amap_h__
+#include "setypes.h"
+#include "ioctl_types.h"
+#include "ioctl_hdr.h"
+#include "ioctl_defs.h"
+#include "host_struct.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- PHY_LINK_DUPLEX_ENUM --- */
+#define PHY_LINK_DUPLEX_NONE (0)
+#define PHY_LINK_DUPLEX_HALF (1)
+#define PHY_LINK_DUPLEX_FULL (2)
+
+/* --- PHY_LINK_SPEED_ENUM --- */
+#define PHY_LINK_SPEED_ZERO (0) /* No link. */
+#define PHY_LINK_SPEED_10MBPS (1) /* 10 Mbps */
+#define PHY_LINK_SPEED_100MBPS (2) /* 100 Mbps */
+#define PHY_LINK_SPEED_1GBPS (3) /* 1 Gbps */
+#define PHY_LINK_SPEED_10GBPS (4) /* 10 Gbps */
+
+/* --- PHY_LINK_FAULT_ENUM --- */
+#define PHY_LINK_FAULT_NONE (0) /* No fault status available
+ or detected */
+#define PHY_LINK_FAULT_LOCAL (1) /* Local fault detected */
+#define PHY_LINK_FAULT_REMOTE (2) /* Remote fault detected */
+
+/* --- BE_ULP_MASK --- */
+#define BE_ULP0_MASK (1)
+#define BE_ULP1_MASK (2)
+#define BE_ULP2_MASK (4)
+
+/* --- NTWK_ACTIVE_PORT --- */
+#define NTWK_PORT_A (0) /* Port A is currently active */
+#define NTWK_PORT_B (1) /* Port B is currently active */
+#define NTWK_NO_ACTIVE_PORT (15) /* Both ports have lost link */
+
+/* --- NTWK_LINK_TYPE --- */
+#define NTWK_LINK_TYPE_PHYSICAL (0) /* The associated link up/down event
+ * applies to the BladeEngine's
+ * Physical Ports
+ */
+#define NTWK_LINK_TYPE_VIRTUAL (1) /* A Virtual link up/down event is
+ * being reported by the BladeExchange.
+ * This applies only when the VLD is
+ * feature enabled
+ */
+
+/*
+ * --- IOCTL_MAC_TYPE_ENUM ---
+ * This enum defines the types of MAC addresses in the RXF MAC Address Table.
+ */
+#define MAC_ADDRESS_TYPE_STORAGE (0) /* Storage MAC Address */
+#define MAC_ADDRESS_TYPE_NETWORK (1) /* Network MAC Address */
+#define MAC_ADDRESS_TYPE_PD (2) /* Protection Domain
+ MAC Address */
+#define MAC_ADDRESS_TYPE_MANAGEMENT (3) /* Managment MAC Address */
+
+SG_STATIC_INLINE const char *ioctl_mac_type_enum_get_name(u32 enum_value)
+{
+ switch (enum_value) {
+ case MAC_ADDRESS_TYPE_STORAGE:
+ return "MAC_ADDRESS_TYPE_STORAGE";
+ case MAC_ADDRESS_TYPE_NETWORK:
+ return "MAC_ADDRESS_TYPE_NETWORK";
+ case MAC_ADDRESS_TYPE_PD:
+ return "MAC_ADDRESS_TYPE_PD";
+ case MAC_ADDRESS_TYPE_MANAGEMENT:
+ return "MAC_ADDRESS_TYPE_MANAGEMENT";
+ default:
+ break;
+ }
+ return ""; /* undefined enum value */
+};
+
+/* --- IOCTL_RING_TYPE_ENUM --- */
+#define IOCTL_RING_TYPE_ETH_RX (1) /* Ring created with */
+ /* IOCTL_COMMON_ETH_RX_CREATE. */
+#define IOCTL_RING_TYPE_ETH_TX (2) /* Ring created with */
+ /* IOCTL_COMMON_ETH_TX_CREATE. */
+#define IOCTL_RING_TYPE_ISCSI_WRBQ (3) /* Ring created with */
+ /* IOCTL_COMMON_ISCSI_WRBQ_CREATE. */
+#define IOCTL_RING_TYPE_ISCSI_DEFQ (4) /* Ring created with */
+ /* IOCTL_COMMON_ISCSI_DEFQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_WRBQ (5) /* Ring created with */
+ /* IOCTL_COMMON_TPM_WRBQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_DEFQ (6) /* Ring created with */
+ /* IOCTL_COMMONTPM_TDEFQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_RQ (7) /* Ring created with */
+ /* IOCTL_COMMON_TPM_RQ_CREATE. */
+#define IOCTL_RING_TYPE_MCC (8) /* Ring created with */
+ /* IOCTL_COMMON_MCC_CREATE. */
+#define IOCTL_RING_TYPE_CQ (9) /* Ring created with */
+ /* IOCTL_COMMON_CQ_CREATE. */
+#define IOCTL_RING_TYPE_EQ (10) /* Ring created with */
+ /* IOCTL_COMMON_EQ_CREATE. */
+#define IOCTL_RING_TYPE_QP (11) /* Ring created with */
+ /* IOCTL_RDMA_QP_CREATE. */
+
+/* --- ETH_TX_RING_TYPE_ENUM --- */
+#define ETH_TX_RING_TYPE_FORWARDING (1) /* Eth ring for forwarding
+ packets */
+#define ETH_TX_RING_TYPE_STANDARD (2) /* Eth ring for sending network */
+#define ETH_TX_RING_TYPE_BOUND (3) /* Eth ring bound to the port */
+ /* packets. */
+ /*
+ * specified in the IOCTL
+ * header.port_number field. Rings of
+ * this type are NOT subject to the
+ * failover logic implemented in the
+ * BladeEngine.
+ */
+
+/* --- IOCTL_COMMON_QOS_TYPE_ENUM --- */
+#define QOS_BITS_NIC (1) /* The max_bits_per_second_NIC field is valid. */
+#define QOS_PKTS_NIC (2) /* The max_packets_per_second_NIC field valid. */
+#define QOS_IOPS_ISCSI (4) /* The max_ios_per_second_iSCSI field is valid. */
+#define QOS_VLAN_TAG (8) /* The domain_VLAN_tag field is valid. */
+#define QOS_FABRIC_ID (16) /* The fabric_domain_ID field is valid. */
+#define QOS_OEM_PARAMS (32) /* The qos_params_oem field is valid. */
+#define QOS_TPUT_ISCSI (64) /* The max_bytes_per_second_iSCSI field valid. */
+/*
+ * --- FAILOVER_CONFIG_ENUM ---
+ * Failover configuration setting used in IOCTL_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_CONFIG_NO_CHANGE (0) /* No change to automatic port failover */
+ /* setting. */
+#define FAILOVER_CONFIG_ON (1) /* Automatic port failover on link down */
+ /* is enabled. */
+#define FAILOVER_CONFIG_OFF (2) /* Automatic port failover on link down */
+ /* is disabled. */
+
+/*
+ * --- FAILOVER_PORT_ENUM ---
+ * Failover port setting used in IOCTL_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_PORT_A (0) /* Selects port A. */
+#define FAILOVER_PORT_B (1) /* Selects port B. */
+#define FAILOVER_PORT_NONE (15) /* No port change requested. */
+
+/*
+ * --- MGMT_FLASHROM_OPCODE ---
+ * Flash ROM operation code
+ */
+#define MGMT_FLASHROM_OPCODE_FLASH (1) /* Commit downloaded data to
+ Flash ROM */
+#define MGMT_FLASHROM_OPCODE_SAVE (2) /* Save downloaded data to
+ ARM's DDR - do not flash */
+#define MGMT_FLASHROM_OPCODE_CLEAR (3) /* Erase specified component
+ from Flash ROM */
+#define MGMT_FLASHROM_OPCODE_REPORT (4) /* Read specified component
+ from Flash ROM */
+#define MGMT_FLASHROM_OPCODE_IMAGE_INFO (5) /* Returns size of a component */
+
+/*
+ * --- MGMT_FLASHROM_OPTYPE ---
+ * Flash ROM operation type
+ */
+#define MGMT_FLASHROM_OPTYPE_CODE_FIRMWARE (0) /* Includes ARM firmware,
+ IPSec (optional) and
+ EP firmware */
+#define MGMT_FLASHROM_OPTYPE_CODE_REDBOOT (1)
+#define MGMT_FLASHROM_OPTYPE_CODE_BIOS (2)
+#define MGMT_FLASHROM_OPTYPE_CODE_PXE_BIOS (3)
+#define MGMT_FLASHROM_OPTYPE_CODE_CTRLS (4)
+#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC (5)
+#define MGMT_FLASHROM_OPTYPE_CFG_INI (6)
+#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET_SPECIFIED (7) /* TBD */
+
+
+/*
+ * --- FLASHROM_TYPE ---
+ * Flash ROM manufacturers supported in the f/w
+ */
+#define INTEL (0)
+#define SPANSION (1)
+#define MICRON (2)
+
+/* --- DDR_CAS_TYPE --- */
+#define CAS_3 (0)
+#define CAS_4 (1)
+#define CAS_5 (2)
+
+/* --- DDR_SIZE_TYPE --- */
+#define SIZE_256MB (0)
+#define SIZE_512MB (1)
+
+/* --- DDR_MODE_TYPE --- */
+#define DDR_NO_ECC (0)
+#define DDR_ECC (1)
+
+/* --- INTERFACE_10GB_TYPE --- */
+#define CX4_TYPE (0)
+#define XFP_TYPE (1)
+
+/* --- BE_CHIP_MAX_MTU --- */
+#define CHIP_MAX_MTU (9000)
+
+/* --- XAUI_STATE_ENUM --- */
+#define XAUI_STATE_ENABLE (0) /* This MUST be the default value for */
+ /*
+ * all requests which set/change
+ * equalization parameter.
+ */
+#define XAUI_STATE_DISABLE (255) /* The XAUI for both ports may be */
+ /*
+ * disabled for EMI tests. There is no
+ * provision for turning off individual
+ * ports.
+ */
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+#endif /* __ioctl_common_amap_h__ */
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
intended recipient of this message, please immediately advise the sender by reply email message and
delete all copies of this message and any attachment(s). Thank you.
^ permalink raw reply
* [PATHCH 11/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:44 UTC (permalink / raw)
To: netdev
F/W header files.
------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu_context.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu_context.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu_context.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu_context.h 2008-02-14 15:23:07.821203760 +0530
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __mpu_context_amap_h__
+#define __mpu_context_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __mpu_context_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_eth.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_eth.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_eth.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_eth.h 2008-02-14 15:23:07.822203608 +0530
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_eth_amap_h__
+#define __ioctl_eth_amap_h__
+#include "setypes.h"
+#include "ioctl_hdr.h"
+#include "ioctl_types.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/* --- RXF_STATS_INTERESTING_OFFSETS --- */
+#define P0_RECVD_TOTAL_BYTES_LSD_DWORD_OFFSET (0)
+#define P0_RECVD_TOTAL_BYTES_MSD_DWORD_OFFSET (1)
+#define P0_XMIT_BYTES_LSD_DWORD_OFFSET (40)
+#define P0_XMIT_BYTES_MSD_DWORD_OFFSET (41)
+#define P1_RECVD_TOTAL_BYTES_LSD_DWORD_OFFSET (59)
+#define P1_RECVD_TOTAL_BYTES_MSD_DWORD_OFFSET (60)
+#define P1_XMIT_BYTES_LSD_DWORD_OFFSET (99)
+#define P1_XMIT_BYTES_MSD_DWORD_OFFSET (100)
+
+/*
+ * --- ENABLE_RSS_ENUM ---
+ * Enable RSS enum.
+ */
+#define RSS_ENABLE_NONE (0) /* No RSS */
+#define RSS_ENABLE_IPV4 (1) /* IPV4 HASH only (i.e. only IP */
+ /* source/dest two-tuple) */
+#define RSS_ENABLE_TCP_IPV4 (2) /* TCP IPV4 HASH only
+ (i.e. only TCP/IP four-tuple) */
+#define RSS_ENABLE_IPV4_OR_TCP_IPV4 (3) /* IPV4 or TCP IPV4 HASH (i.e. if */
+ /*
+ * TCP/IP, then use four-tuple, else if
+ * IP use two-tuple)
+ */
+
+/*
+ * --- RSS_FLUSH_CQ_ENUM ---
+ * Flush CQ enum.
+ */
+#define RSS_FLUSH_CQ_DEFAULT (1) /* Flush default host networking CQ */
+#define RSS_FLUSH_CQ_PROC0 (2) /* Flush RSS CQ for processor 0 */
+#define RSS_FLUSH_CQ_PROC1 (4) /* Flush RSS CQ for processor 1 */
+#define RSS_FLUSH_CQ_PROC2 (8) /* Flush RSS CQ for processor 2 */
+#define RSS_FLUSH_CQ_PROC3 (16) /* Flush RSS CQ for processor 3 */
+
+
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_eth_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/etx_context.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/etx_context.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/etx_context.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/etx_context.h 2008-02-14 15:23:07.822203608 +0530
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __etx_context_amap_h__
+#define __etx_context_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* ETX ring context structure. */
+typedef struct {
+ BE_BIT tx_cidx[11]; /* DWORD 0 */
+ BE_BIT rsvd0[5]; /* DWORD 0 */
+ BE_BIT rsvd1[16]; /* DWORD 0 */
+ BE_BIT tx_pidx[11]; /* DWORD 1 */
+ BE_BIT rsvd2; /* DWORD 1 */
+ BE_BIT tx_ring_size[4]; /* DWORD 1 */
+ BE_BIT pd_id[5]; /* DWORD 1 */
+ BE_BIT pd_id_not_valid; /* DWORD 1 */
+ BE_BIT cq_id_send[10]; /* DWORD 1 */
+ BE_BIT rsvd3[32]; /* DWORD 2 */
+ BE_BIT rsvd4[32]; /* DWORD 3 */
+ BE_BIT cur_bytes[32]; /* DWORD 4 */
+ BE_BIT max_bytes[32]; /* DWORD 5 */
+ BE_BIT time_stamp[32]; /* DWORD 6 */
+ BE_BIT rsvd5[11]; /* DWORD 7 */
+ BE_BIT func; /* DWORD 7 */
+ BE_BIT rsvd6[20]; /* DWORD 7 */
+ BE_BIT cur_txd_count[32]; /* DWORD 8 */
+ BE_BIT max_txd_count[32]; /* DWORD 9 */
+ BE_BIT rsvd7[32]; /* DWORD 10 */
+ BE_BIT rsvd8[32]; /* DWORD 11 */
+ BE_BIT rsvd9[32]; /* DWORD 12 */
+ BE_BIT rsvd10[32]; /* DWORD 13 */
+ BE_BIT rsvd11[32]; /* DWORD 14 */
+ BE_BIT rsvd12[32]; /* DWORD 15 */
+} SG_PACK BE_ETX_CONTEXT_AMAP;
+typedef struct {
+ u32 dw[16];
+} ETX_CONTEXT_AMAP, *PETX_CONTEXT_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __etx_context_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/cev.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/cev.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/cev.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/cev.h 2008-02-14 15:23:07.823203456 +0530
@@ -0,0 +1,275 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __cev_amap_h__
+#define __cev_amap_h__
+#include "setypes.h"
+#include "ep.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/*
+ * Host Interrupt Status Register 0. The first of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ0 through EQ31.
+ */
+typedef struct {
+ BE_BIT interrupt0; /* DWORD 0 */
+ BE_BIT interrupt1; /* DWORD 0 */
+ BE_BIT interrupt2; /* DWORD 0 */
+ BE_BIT interrupt3; /* DWORD 0 */
+ BE_BIT interrupt4; /* DWORD 0 */
+ BE_BIT interrupt5; /* DWORD 0 */
+ BE_BIT interrupt6; /* DWORD 0 */
+ BE_BIT interrupt7; /* DWORD 0 */
+ BE_BIT interrupt8; /* DWORD 0 */
+ BE_BIT interrupt9; /* DWORD 0 */
+ BE_BIT interrupt10; /* DWORD 0 */
+ BE_BIT interrupt11; /* DWORD 0 */
+ BE_BIT interrupt12; /* DWORD 0 */
+ BE_BIT interrupt13; /* DWORD 0 */
+ BE_BIT interrupt14; /* DWORD 0 */
+ BE_BIT interrupt15; /* DWORD 0 */
+ BE_BIT interrupt16; /* DWORD 0 */
+ BE_BIT interrupt17; /* DWORD 0 */
+ BE_BIT interrupt18; /* DWORD 0 */
+ BE_BIT interrupt19; /* DWORD 0 */
+ BE_BIT interrupt20; /* DWORD 0 */
+ BE_BIT interrupt21; /* DWORD 0 */
+ BE_BIT interrupt22; /* DWORD 0 */
+ BE_BIT interrupt23; /* DWORD 0 */
+ BE_BIT interrupt24; /* DWORD 0 */
+ BE_BIT interrupt25; /* DWORD 0 */
+ BE_BIT interrupt26; /* DWORD 0 */
+ BE_BIT interrupt27; /* DWORD 0 */
+ BE_BIT interrupt28; /* DWORD 0 */
+ BE_BIT interrupt29; /* DWORD 0 */
+ BE_BIT interrupt30; /* DWORD 0 */
+ BE_BIT interrupt31; /* DWORD 0 */
+} SG_PACK BE_CEV_ISR0_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} CEV_ISR0_CSR_AMAP, *PCEV_ISR0_CSR_AMAP;
+
+/*
+ * Host Interrupt Status Register 1. The second of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ32 through EQ63.
+ */
+typedef struct {
+ BE_BIT interrupt32; /* DWORD 0 */
+ BE_BIT interrupt33; /* DWORD 0 */
+ BE_BIT interrupt34; /* DWORD 0 */
+ BE_BIT interrupt35; /* DWORD 0 */
+ BE_BIT interrupt36; /* DWORD 0 */
+ BE_BIT interrupt37; /* DWORD 0 */
+ BE_BIT interrupt38; /* DWORD 0 */
+ BE_BIT interrupt39; /* DWORD 0 */
+ BE_BIT interrupt40; /* DWORD 0 */
+ BE_BIT interrupt41; /* DWORD 0 */
+ BE_BIT interrupt42; /* DWORD 0 */
+ BE_BIT interrupt43; /* DWORD 0 */
+ BE_BIT interrupt44; /* DWORD 0 */
+ BE_BIT interrupt45; /* DWORD 0 */
+ BE_BIT interrupt46; /* DWORD 0 */
+ BE_BIT interrupt47; /* DWORD 0 */
+ BE_BIT interrupt48; /* DWORD 0 */
+ BE_BIT interrupt49; /* DWORD 0 */
+ BE_BIT interrupt50; /* DWORD 0 */
+ BE_BIT interrupt51; /* DWORD 0 */
+ BE_BIT interrupt52; /* DWORD 0 */
+ BE_BIT interrupt53; /* DWORD 0 */
+ BE_BIT interrupt54; /* DWORD 0 */
+ BE_BIT interrupt55; /* DWORD 0 */
+ BE_BIT interrupt56; /* DWORD 0 */
+ BE_BIT interrupt57; /* DWORD 0 */
+ BE_BIT interrupt58; /* DWORD 0 */
+ BE_BIT interrupt59; /* DWORD 0 */
+ BE_BIT interrupt60; /* DWORD 0 */
+ BE_BIT interrupt61; /* DWORD 0 */
+ BE_BIT interrupt62; /* DWORD 0 */
+ BE_BIT interrupt63; /* DWORD 0 */
+} SG_PACK BE_CEV_ISR1_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} CEV_ISR1_CSR_AMAP, *PCEV_ISR1_CSR_AMAP;
+/*
+ * Host Interrupt Status Register 2. The third of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ64 through EQ95.
+ */
+typedef struct {
+ BE_BIT interrupt64; /* DWORD 0 */
+ BE_BIT interrupt65; /* DWORD 0 */
+ BE_BIT interrupt66; /* DWORD 0 */
+ BE_BIT interrupt67; /* DWORD 0 */
+ BE_BIT interrupt68; /* DWORD 0 */
+ BE_BIT interrupt69; /* DWORD 0 */
+ BE_BIT interrupt70; /* DWORD 0 */
+ BE_BIT interrupt71; /* DWORD 0 */
+ BE_BIT interrupt72; /* DWORD 0 */
+ BE_BIT interrupt73; /* DWORD 0 */
+ BE_BIT interrupt74; /* DWORD 0 */
+ BE_BIT interrupt75; /* DWORD 0 */
+ BE_BIT interrupt76; /* DWORD 0 */
+ BE_BIT interrupt77; /* DWORD 0 */
+ BE_BIT interrupt78; /* DWORD 0 */
+ BE_BIT interrupt79; /* DWORD 0 */
+ BE_BIT interrupt80; /* DWORD 0 */
+ BE_BIT interrupt81; /* DWORD 0 */
+ BE_BIT interrupt82; /* DWORD 0 */
+ BE_BIT interrupt83; /* DWORD 0 */
+ BE_BIT interrupt84; /* DWORD 0 */
+ BE_BIT interrupt85; /* DWORD 0 */
+ BE_BIT interrupt86; /* DWORD 0 */
+ BE_BIT interrupt87; /* DWORD 0 */
+ BE_BIT interrupt88; /* DWORD 0 */
+ BE_BIT interrupt89; /* DWORD 0 */
+ BE_BIT interrupt90; /* DWORD 0 */
+ BE_BIT interrupt91; /* DWORD 0 */
+ BE_BIT interrupt92; /* DWORD 0 */
+ BE_BIT interrupt93; /* DWORD 0 */
+ BE_BIT interrupt94; /* DWORD 0 */
+ BE_BIT interrupt95; /* DWORD 0 */
+} SG_PACK BE_CEV_ISR2_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} CEV_ISR2_CSR_AMAP, *PCEV_ISR2_CSR_AMAP;
+
+/*
+ * Host Interrupt Status Register 3. The fourth of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ96 through EQ127.
+ */
+typedef struct {
+ BE_BIT interrupt96; /* DWORD 0 */
+ BE_BIT interrupt97; /* DWORD 0 */
+ BE_BIT interrupt98; /* DWORD 0 */
+ BE_BIT interrupt99; /* DWORD 0 */
+ BE_BIT interrupt100; /* DWORD 0 */
+ BE_BIT interrupt101; /* DWORD 0 */
+ BE_BIT interrupt102; /* DWORD 0 */
+ BE_BIT interrupt103; /* DWORD 0 */
+ BE_BIT interrupt104; /* DWORD 0 */
+ BE_BIT interrupt105; /* DWORD 0 */
+ BE_BIT interrupt106; /* DWORD 0 */
+ BE_BIT interrupt107; /* DWORD 0 */
+ BE_BIT interrupt108; /* DWORD 0 */
+ BE_BIT interrupt109; /* DWORD 0 */
+ BE_BIT interrupt110; /* DWORD 0 */
+ BE_BIT interrupt111; /* DWORD 0 */
+ BE_BIT interrupt112; /* DWORD 0 */
+ BE_BIT interrupt113; /* DWORD 0 */
+ BE_BIT interrupt114; /* DWORD 0 */
+ BE_BIT interrupt115; /* DWORD 0 */
+ BE_BIT interrupt116; /* DWORD 0 */
+ BE_BIT interrupt117; /* DWORD 0 */
+ BE_BIT interrupt118; /* DWORD 0 */
+ BE_BIT interrupt119; /* DWORD 0 */
+ BE_BIT interrupt120; /* DWORD 0 */
+ BE_BIT interrupt121; /* DWORD 0 */
+ BE_BIT interrupt122; /* DWORD 0 */
+ BE_BIT interrupt123; /* DWORD 0 */
+ BE_BIT interrupt124; /* DWORD 0 */
+ BE_BIT interrupt125; /* DWORD 0 */
+ BE_BIT interrupt126; /* DWORD 0 */
+ BE_BIT interrupt127; /* DWORD 0 */
+} SG_PACK BE_CEV_ISR3_CSR_AMAP;
+typedef struct {
+ u32 dw[1];
+} CEV_ISR3_CSR_AMAP, *PCEV_ISR3_CSR_AMAP;
+
+/* Completions and Events block Registers. */
+typedef struct {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[32]; /* DWORD 1 */
+ BE_BIT rsvd2[32]; /* DWORD 2 */
+ BE_BIT rsvd3[32]; /* DWORD 3 */
+ BE_CEV_ISR0_CSR_AMAP isr0;
+ BE_CEV_ISR1_CSR_AMAP isr1;
+ BE_CEV_ISR2_CSR_AMAP isr2;
+ BE_CEV_ISR3_CSR_AMAP isr3;
+ BE_BIT rsvd4[32]; /* DWORD 8 */
+ BE_BIT rsvd5[32]; /* DWORD 9 */
+ BE_BIT rsvd6[32]; /* DWORD 10 */
+ BE_BIT rsvd7[32]; /* DWORD 11 */
+ BE_BIT rsvd8[32]; /* DWORD 12 */
+ BE_BIT rsvd9[32]; /* DWORD 13 */
+ BE_BIT rsvd10[32]; /* DWORD 14 */
+ BE_BIT rsvd11[32]; /* DWORD 15 */
+ BE_BIT rsvd12[32]; /* DWORD 16 */
+ BE_BIT rsvd13[32]; /* DWORD 17 */
+ BE_BIT rsvd14[32]; /* DWORD 18 */
+ BE_BIT rsvd15[32]; /* DWORD 19 */
+ BE_BIT rsvd16[32]; /* DWORD 20 */
+ BE_BIT rsvd17[32]; /* DWORD 21 */
+ BE_BIT rsvd18[32]; /* DWORD 22 */
+ BE_BIT rsvd19[32]; /* DWORD 23 */
+ BE_BIT rsvd20[32]; /* DWORD 24 */
+ BE_BIT rsvd21[32]; /* DWORD 25 */
+ BE_BIT rsvd22[32]; /* DWORD 26 */
+ BE_BIT rsvd23[32]; /* DWORD 27 */
+ BE_BIT rsvd24[32]; /* DWORD 28 */
+ BE_BIT rsvd25[32]; /* DWORD 29 */
+ BE_BIT rsvd26[32]; /* DWORD 30 */
+ BE_BIT rsvd27[32]; /* DWORD 31 */
+ BE_BIT rsvd28[32]; /* DWORD 32 */
+ BE_BIT rsvd29[32]; /* DWORD 33 */
+ BE_BIT rsvd30[192]; /* DWORD 34 */
+ BE_BIT rsvd31[192]; /* DWORD 40 */
+ BE_BIT rsvd32[160]; /* DWORD 46 */
+ BE_BIT rsvd33[160]; /* DWORD 51 */
+ BE_BIT rsvd34[160]; /* DWORD 56 */
+ BE_BIT rsvd35[96]; /* DWORD 61 */
+ BE_BIT rsvd36[192][32]; /* DWORD 64 */
+} SG_PACK BE_CEV_CSRMAP_AMAP;
+typedef struct {
+ u32 dw[256];
+} CEV_CSRMAP_AMAP, *PCEV_CSRMAP_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __cev_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/asyncmesg.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/asyncmesg.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/asyncmesg.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/asyncmesg.h 2008-02-14 15:23:07.824203304 +0530
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __asyncmesg_amap_h__
+#define __asyncmesg_amap_h__
+#include "setypes.h"
+#include "ioctl_common.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- ASYNC_EVENT_CODES --- */
+#define ASYNC_EVENT_CODE_LINK_STATE (1)
+#define ASYNC_EVENT_CODE_ISCSI (2)
+
+/* --- ASYNC_LINK_STATES --- */
+#define ASYNC_EVENT_LINK_DOWN (0) /* Link Down on a port */
+#define ASYNC_EVENT_LINK_UP (1) /* Link Up on a port */
+
+/*
+ * The last 4 bytes of the async events have this common format. It allows
+ * the driver to distinguish [link]MCC_CQ_ENTRY[/link] structs from
+ * asynchronous events. Both arrive on the same completion queue. This
+ * structure also contains the common fields used to decode the async event.
+ *
+ */
+typedef struct {
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ BE_BIT event_code[8]; /* DWORD 0 */
+ BE_BIT event_type[8]; /* DWORD 0 */
+ BE_BIT rsvd1[6]; /* DWORD 0 */
+ BE_BIT async_event; /* DWORD 0 */
+ BE_BIT valid; /* DWORD 0 */
+} SG_PACK BE_ASYNC_EVENT_TRAILER_AMAP;
+typedef struct {
+ u32 dw[1];
+} ASYNC_EVENT_TRAILER_AMAP, *PASYNC_EVENT_TRAILER_AMAP;
+
+/* --- ASYNC_ISCSI_EVENTS --- */
+/* iSCSI discovery services found a */
+/* new Target for this Initiator */
+#define ASYNC_ISCSI_EVENT_NEW_TARGET_DISCOVERED (4)
+#define ASYNC_ISCSI_EVENT_NEW_ISCSI_CONNECTION_ESTABLISHED (5)
+/* The firmware's background task (re) established a session for this
+ * initiator. In VM mode, this is the only mode in which new targets/LUNs
+ * can be added to a guest domain
+ * */
+#define ASYNC_ISCSI_EVENT_NEW_ISCSI_CONNECTION_ESTABLISHED (5)
+#define ASYNC_ISCSI_EVENT_NEW_TCP_CONNECTION_ESTABLISHED (7)
+/*
+ * Target mode ONLY - an initiator has opened a connection on the listen port
+ */
+#define ASYNC_ISCSI_EVENT_NEW_TCP_CONNECTION_ACCEPTED (16)
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __asyncmesg_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/mpu.h 2008-02-14 15:23:07.824203304 +0530
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __mpu_amap_h__
+#define __mpu_amap_h__
+#include "setypes.h"
+#include "ep.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/* Provide control parameters for the Managment Processor Unit. */
+typedef struct {
+ BE_EP_CSRMAP_AMAP ep;
+ BE_BIT rsvd0[128]; /* DWORD 64 */
+ BE_BIT rsvd1[32]; /* DWORD 68 */
+ BE_BIT rsvd2[192]; /* DWORD 69 */
+ BE_BIT rsvd3[192]; /* DWORD 75 */
+ BE_BIT rsvd4[32]; /* DWORD 81 */
+ BE_BIT rsvd5[32]; /* DWORD 82 */
+ BE_BIT rsvd6[32]; /* DWORD 83 */
+ BE_BIT rsvd7[32]; /* DWORD 84 */
+ BE_BIT rsvd8[32]; /* DWORD 85 */
+ BE_BIT rsvd9[32]; /* DWORD 86 */
+ BE_BIT rsvd10[32]; /* DWORD 87 */
+ BE_BIT rsvd11[32]; /* DWORD 88 */
+ BE_BIT rsvd12[32]; /* DWORD 89 */
+ BE_BIT rsvd13[32]; /* DWORD 90 */
+ BE_BIT rsvd14[32]; /* DWORD 91 */
+ BE_BIT rsvd15[32]; /* DWORD 92 */
+ BE_BIT rsvd16[32]; /* DWORD 93 */
+ BE_BIT rsvd17[32]; /* DWORD 94 */
+ BE_BIT rsvd18[32]; /* DWORD 95 */
+ BE_BIT rsvd19[32]; /* DWORD 96 */
+ BE_BIT rsvd20[32]; /* DWORD 97 */
+ BE_BIT rsvd21[32]; /* DWORD 98 */
+ BE_BIT rsvd22[32]; /* DWORD 99 */
+ BE_BIT rsvd23[32]; /* DWORD 100 */
+ BE_BIT rsvd24[32]; /* DWORD 101 */
+ BE_BIT rsvd25[32]; /* DWORD 102 */
+ BE_BIT rsvd26[32]; /* DWORD 103 */
+ BE_BIT rsvd27[32]; /* DWORD 104 */
+ BE_BIT rsvd28[96]; /* DWORD 105 */
+ BE_BIT rsvd29[32]; /* DWORD 108 */
+ BE_BIT rsvd30[32]; /* DWORD 109 */
+ BE_BIT rsvd31[32]; /* DWORD 110 */
+ BE_BIT rsvd32[32]; /* DWORD 111 */
+ BE_BIT rsvd33[32]; /* DWORD 112 */
+ BE_BIT rsvd34[96]; /* DWORD 113 */
+ BE_BIT rsvd35[32]; /* DWORD 116 */
+ BE_BIT rsvd36[32]; /* DWORD 117 */
+ BE_BIT rsvd37[32]; /* DWORD 118 */
+ BE_BIT rsvd38[32]; /* DWORD 119 */
+ BE_BIT rsvd39[32]; /* DWORD 120 */
+ BE_BIT rsvd40[32]; /* DWORD 121 */
+ BE_BIT rsvd41[134][32]; /* DWORD 122 */
+} SG_PACK BE_MPU_CSRMAP_AMAP;
+typedef struct {
+ u32 dw[256];
+} MPU_CSRMAP_AMAP, *PMPU_CSRMAP_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __mpu_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/doorbells.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/doorbells.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/doorbells.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/doorbells.h 2008-02-14 15:23:07.825203152 +0530
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __doorbells_amap_h__
+#define __doorbells_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* The TX/RDMA send queue doorbell. */
+typedef struct {
+ BE_BIT cid[11]; /* DWORD 0 */
+ BE_BIT rsvd0[5]; /* DWORD 0 */
+ BE_BIT numPosted[14]; /* DWORD 0 */
+ BE_BIT rsvd1[2]; /* DWORD 0 */
+} SG_PACK BE_SQ_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} SQ_DB_AMAP, *PSQ_DB_AMAP;
+
+/* The receive queue doorbell. */
+typedef struct {
+ BE_BIT rq[10]; /* DWORD 0 */
+ BE_BIT rsvd0[13]; /* DWORD 0 */
+ BE_BIT Invalidate; /* DWORD 0 */
+ BE_BIT numPosted[8]; /* DWORD 0 */
+} SG_PACK BE_RQ_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} RQ_DB_AMAP, *PRQ_DB_AMAP;
+
+/*
+ * The CQ/EQ doorbell. Software MUST set reserved fields in this
+ * descriptor to zero, otherwise (CEV) hardware will not execute the
+ * doorbell (flagging a bad_db_qid error instead).
+ */
+typedef struct {
+ BE_BIT qid[10]; /* DWORD 0 */
+ BE_BIT rsvd0[4]; /* DWORD 0 */
+ BE_BIT rearm; /* DWORD 0 */
+ BE_BIT event; /* DWORD 0 */
+ BE_BIT num_popped[13]; /* DWORD 0 */
+ BE_BIT rsvd1[3]; /* DWORD 0 */
+} SG_PACK BE_CQ_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} CQ_DB_AMAP, *PCQ_DB_AMAP;
+
+typedef struct {
+ BE_BIT qid[10]; /* DWORD 0 */
+ BE_BIT rsvd0[6]; /* DWORD 0 */
+ BE_BIT numPosted[11]; /* DWORD 0 */
+ BE_BIT mss_cnt[5]; /* DWORD 0 */
+} SG_PACK BE_TPM_RQ_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} TPM_RQ_DB_AMAP, *PTPM_RQ_DB_AMAP;
+
+/*
+ * Post WRB Queue Doorbell Register used by the host Storage stack
+ * to notify the controller of a posted Work Request Block
+ */
+typedef struct {
+ BE_BIT wrb_cid[10]; /* DWORD 0 */
+ BE_BIT rsvd0[6]; /* DWORD 0 */
+ BE_BIT wrb_index[8]; /* DWORD 0 */
+ BE_BIT numberPosted[8]; /* DWORD 0 */
+} SG_PACK BE_WRB_POST_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} WRB_POST_DB_AMAP, *PWRB_POST_DB_AMAP;
+
+/*
+ * Update Default PDU Queue Doorbell Register used to communicate
+ * to the controller that the driver has stopped processing the queue
+ * and where in the queue it stopped, this is
+ * a CQ Entry Type. Used by storage driver.
+ */
+typedef struct {
+ BE_BIT qid[10]; /* DWORD 0 */
+ BE_BIT rsvd0[4]; /* DWORD 0 */
+ BE_BIT rearm; /* DWORD 0 */
+ BE_BIT event; /* DWORD 0 */
+ BE_BIT cqproc[14]; /* DWORD 0 */
+ BE_BIT rsvd1[2]; /* DWORD 0 */
+} SG_PACK BE_DEFAULT_PDU_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} DEFAULT_PDU_DB_AMAP, *PDEFAULT_PDU_DB_AMAP;
+
+/* Management Command and Controller default fragment ring */
+typedef struct {
+ BE_BIT rid[11]; /* DWORD 0 */
+ BE_BIT rsvd0[5]; /* DWORD 0 */
+ BE_BIT numPosted[14]; /* DWORD 0 */
+ BE_BIT rsvd1[2]; /* DWORD 0 */
+} SG_PACK BE_MCC_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} MCC_DB_AMAP, *PMCC_DB_AMAP;
+
+/*
+ * Used for bootstrapping the Host interface. This register is
+ * used for driver communication with the MPU when no MCC Rings exist.
+ * The software must write this register twice to post any MCC
+ * command. First, it writes the register with hi=1 and the upper bits of
+ * the physical address for the MCC_MAILBOX structure. Software must poll
+ * the ready bit until this is acknowledged. Then, sotware writes the
+ * register with hi=0 with the lower bits in the address. It must
+ * poll the ready bit until the MCC command is complete. Upon completion,
+ * the MCC_MAILBOX will contain a valid completion queue entry.
+ */
+typedef struct {
+ BE_BIT ready; /* DWORD 0 */
+ BE_BIT hi; /* DWORD 0 */
+ BE_BIT address[30]; /* DWORD 0 */
+} SG_PACK BE_MPU_MAILBOX_DB_AMAP;
+typedef struct {
+ u32 dw[1];
+} MPU_MAILBOX_DB_AMAP, *PMPU_MAILBOX_DB_AMAP;
+
+/*
+ * This is the protection domain doorbell register map. Note that
+ * while this map shows doorbells for all Blade Engine supported
+ * protocols, not all of these may be valid in a given function or
+ * protection domain. It is the responsibility of the application
+ * accessing the doorbells to know which are valid. Each doorbell
+ * occupies 32 bytes of space, but unless otherwise specified,
+ * only the first 4 bytes should be written. There are 32 instances
+ * of these doorbells for the host and 31 virtual machines respectively.
+ * The host and VMs will only map the doorbell pages belonging to its
+ * protection domain. It will not be able to touch the doorbells for
+ * another VM. The doorbells are the only registers directly accessible
+ * by a virtual machine. Similarly, there are 511 additional
+ * doorbells for RDMA protection domains. PD 0 for RDMA shares
+ * the same physical protection domain doorbell page as ETH/iSCSI.
+ *
+ */
+typedef struct {
+ BE_BIT rsvd0[512]; /* DWORD 0 */
+ BE_SQ_DB_AMAP rdma_sq_db;
+ BE_BIT rsvd1[7][32]; /* DWORD 17 */
+ BE_WRB_POST_DB_AMAP iscsi_wrb_post_db;
+ BE_BIT rsvd2[7][32]; /* DWORD 25 */
+ BE_SQ_DB_AMAP etx_sq_db;
+ BE_BIT rsvd3[7][32]; /* DWORD 33 */
+ BE_RQ_DB_AMAP rdma_rq_db;
+ BE_BIT rsvd4[7][32]; /* DWORD 41 */
+ BE_DEFAULT_PDU_DB_AMAP iscsi_default_pdu_db;
+ BE_BIT rsvd5[7][32]; /* DWORD 49 */
+ BE_TPM_RQ_DB_AMAP tpm_rq_db;
+ BE_BIT rsvd6[7][32]; /* DWORD 57 */
+ BE_RQ_DB_AMAP erx_rq_db;
+ BE_BIT rsvd7[7][32]; /* DWORD 65 */
+ BE_CQ_DB_AMAP cq_db;
+ BE_BIT rsvd8[7][32]; /* DWORD 73 */
+ BE_MCC_DB_AMAP mpu_mcc_db;
+ BE_BIT rsvd9[7][32]; /* DWORD 81 */
+ BE_MPU_MAILBOX_DB_AMAP mcc_bootstrap_db;
+ BE_BIT rsvd10[935][32]; /* DWORD 89 */
+} SG_PACK BE_PROTECTION_DOMAIN_DBMAP_AMAP;
+typedef struct {
+ u32 dw[1024];
+} PROTECTION_DOMAIN_DBMAP_AMAP, *PPROTECTION_DOMAIN_DBMAP_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __doorbells_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_mcc.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_mcc.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_mcc.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_mcc.h 2008-02-14 15:23:07.825203152 +0530
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_mcc_amap_h__
+#define __ioctl_mcc_amap_h__
+#include "setypes.h"
+#include "ioctl_defs.h"
+#include "ioctl_opcodes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/*
+ * Where applicable, a WRB, may contain a list of Scatter-gather elements.
+ * Each element supports a 64 bit address and a 32bit length field.
+ */
+typedef struct {
+ BE_BIT pa_lo[32]; /* DWORD 0 */
+ BE_BIT pa_hi[32]; /* DWORD 1 */
+ BE_BIT length[32]; /* DWORD 2 */
+} SG_PACK BE_MCC_SGE_AMAP;
+typedef struct {
+ u32 dw[3];
+} MCC_SGE_AMAP, *PMCC_SGE_AMAP;
+
+/*
+ * The design of an [link]MCC_SGE[/link] allows up to 19 elements to be
+ * embedded in a WRB, supporting 64KB data transfers (assuming a 4KB page size).
+ */
+typedef union {
+ BE_MCC_SGE_AMAP sgl[19];
+ BE_BIT embedded[59][32]; /* DWORD 0 */
+} SG_PACK BE_MCC_WRB_PAYLOAD_AMAP;
+typedef struct {
+ u32 dw[59];
+} MCC_WRB_PAYLOAD_AMAP, *PMCC_WRB_PAYLOAD_AMAP;
+
+/*
+ * This is the structure of the MCC Command WRB for commands
+ * sent to the Management Processing Unit (MPU). See section
+ * for usage in embedded and non-embedded modes.
+ */
+typedef struct {
+ BE_BIT embedded; /* DWORD 0 */
+ BE_BIT rsvd0[2]; /* DWORD 0 */
+ BE_BIT sge_count[5]; /* DWORD 0 */
+ BE_BIT rsvd1[16]; /* DWORD 0 */
+ BE_BIT special[8]; /* DWORD 0 */
+ BE_BIT payload_length[32]; /* DWORD 1 */
+ BE_BIT tag[2][32]; /* DWORD 2 */
+ BE_BIT rsvd2[32]; /* DWORD 4 */
+ BE_MCC_WRB_PAYLOAD_AMAP payload;
+} SG_PACK BE_MCC_WRB_AMAP;
+typedef struct {
+ u32 dw[64];
+} MCC_WRB_AMAP, *PMCC_WRB_AMAP;
+
+/* This is the structure of the MCC Completion queue entry */
+typedef struct {
+ BE_BIT completion_status[16]; /* DWORD 0 */
+ BE_BIT extended_status[16]; /* DWORD 0 */
+ BE_BIT mcc_tag[2][32]; /* DWORD 1 */
+ BE_BIT rsvd0[27]; /* DWORD 3 */
+ BE_BIT consumed; /* DWORD 3 */
+ BE_BIT completed; /* DWORD 3 */
+ BE_BIT hpi_buffer_completion; /* DWORD 3 */
+ BE_BIT async_event; /* DWORD 3 */
+ BE_BIT valid; /* DWORD 3 */
+} SG_PACK BE_MCC_CQ_ENTRY_AMAP;
+typedef struct {
+ u32 dw[4];
+} MCC_CQ_ENTRY_AMAP, *PMCC_CQ_ENTRY_AMAP;
+
+/* Mailbox structures used by the MPU during bootstrap */
+typedef struct {
+ BE_MCC_WRB_AMAP wrb;
+ BE_MCC_CQ_ENTRY_AMAP cq;
+} SG_PACK BE_MCC_MAILBOX_AMAP;
+typedef struct {
+ u32 dw[68];
+} MCC_MAILBOX_AMAP, *PMCC_MAILBOX_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_mcc_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_hdr.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_hdr.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_hdr.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/ioctl_hdr.h 2008-02-14 15:23:07.826203000 +0530
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_hdr_amap_h__
+#define __ioctl_hdr_amap_h__
+#include "setypes.h"
+#include "ioctl_defs.h"
+#include "ioctl_opcodes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_hdr_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/regmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/regmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/regmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/regmap.h 2008-02-14 15:23:07.826203000 +0530
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __regmap_amap_h__
+#define __regmap_amap_h__
+#include "setypes.h"
+#include "ep.h"
+#include "cev.h"
+#include "mpu.h"
+#include "doorbells.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+
+/*
+ * This is the control and status register map for BladeEngine, showing
+ * the relative size and offset of each sub-module. The CSR registers
+ * are identical for the network and storage PCI functions. The
+ * CSR map is shown below, followed by details of each block,
+ * in sub-sections. The sub-sections begin with a description
+ * of CSRs that are instantiated in multiple blocks.
+ */
+typedef struct {
+ BE_MPU_CSRMAP_AMAP mpu;
+ BE_BIT rsvd0[8192]; /* DWORD 256 */
+ BE_BIT rsvd1[8192]; /* DWORD 512 */
+ BE_CEV_CSRMAP_AMAP cev;
+ BE_BIT rsvd2[8192]; /* DWORD 1024 */
+ BE_BIT rsvd3[8192]; /* DWORD 1280 */
+ BE_BIT rsvd4[8192]; /* DWORD 1536 */
+ BE_BIT rsvd5[8192]; /* DWORD 1792 */
+ BE_BIT rsvd6[8192]; /* DWORD 2048 */
+ BE_BIT rsvd7[8192]; /* DWORD 2304 */
+ BE_BIT rsvd8[8192]; /* DWORD 2560 */
+ BE_BIT rsvd9[8192]; /* DWORD 2816 */
+ BE_BIT rsvd10[8192]; /* DWORD 3072 */
+ BE_BIT rsvd11[8192]; /* DWORD 3328 */
+ BE_BIT rsvd12[8192]; /* DWORD 3584 */
+ BE_BIT rsvd13[8192]; /* DWORD 3840 */
+ BE_BIT rsvd14[8192]; /* DWORD 4096 */
+ BE_BIT rsvd15[8192]; /* DWORD 4352 */
+ BE_BIT rsvd16[8192]; /* DWORD 4608 */
+ BE_BIT rsvd17[8192]; /* DWORD 4864 */
+ BE_BIT rsvd18[8192]; /* DWORD 5120 */
+ BE_BIT rsvd19[8192]; /* DWORD 5376 */
+ BE_BIT rsvd20[8192]; /* DWORD 5632 */
+ BE_BIT rsvd21[8192]; /* DWORD 5888 */
+ BE_BIT rsvd22[8192]; /* DWORD 6144 */
+ BE_BIT rsvd23[17152][32]; /* DWORD 6400 */
+} SG_PACK BE_BLADE_ENGINE_CSRMAP_AMAP;
+typedef struct {
+ u32 dw[23552];
+} BLADE_ENGINE_CSRMAP_AMAP, *PBLADE_ENGINE_CSRMAP_AMAP;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __regmap_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/common_context.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/common_context.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/common_context.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/common_context.h 2008-02-14 15:23:07.827202848 +0530
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __common_context_amap_h__
+#define __common_context_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- RING_CONTEXT_SIZE_ENUM --- */
+#define RING_CONTEXT_SIZE_32K (0) /* 32768 entries */
+#define RING_CONTEXT_SIZE_0 (1) /* Invalid/reserved */
+#define RING_CONTEXT_SIZE_2 (2) /* 2 entries */
+#define RING_CONTEXT_SIZE_4 (3) /* 4 entries */
+#define RING_CONTEXT_SIZE_8 (4) /* 8 entries */
+#define RING_CONTEXT_SIZE_16 (5) /* 16 entries */
+#define RING_CONTEXT_SIZE_32 (6) /* 32 entries */
+#define RING_CONTEXT_SIZE_64 (7) /* 64 entries */
+#define RING_CONTEXT_SIZE_128 (8) /* 128 entries */
+#define RING_CONTEXT_SIZE_256 (9) /* 256 entries */
+#define RING_CONTEXT_SIZE_512 (10) /* 512 entries */
+#define RING_CONTEXT_SIZE_1K (11) /* 1024 entries */
+#define RING_CONTEXT_SIZE_2K (12) /* 2048 entries */
+#define RING_CONTEXT_SIZE_4K (13) /* 4096 entries */
+#define RING_CONTEXT_SIZE_8K (14) /* 8192 entries */
+#define RING_CONTEXT_SIZE_16K (15) /* 16384 entries */
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __common_context_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/post_codes.h benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/post_codes.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/amap/post_codes.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/amap/post_codes.h 2008-02-14 15:23:07.827202848 +0530
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __post_codes_amap_h__
+#define __post_codes_amap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_STATIC_INLINE
+#define SG_STATIC_INLINE static inline
+#endif
+/* --- MGMT_HBA_POST_STAGE_ENUM --- */
+#define POST_STAGE_POWER_ON_RESET (0) /* State after a cold or warm boot. */
+#define POST_STAGE_AWAITING_HOST_RDY (1) /* ARM boot code awaiting a
+ go-ahed from the host. */
+#define POST_STAGE_HOST_RDY (2) /* Host has given go-ahed to ARM. */
+#define POST_STAGE_BE_RESET (3) /* Host wants to reset chip, this is a chip
+ workaround */
+#define POST_STAGE_SEEPROM_CS_START (256) /* SEEPROM checksum
+ test start. */
+#define POST_STAGE_SEEPROM_CS_DONE (257) /* SEEPROM checksum test
+ done. */
+#define POST_STAGE_DDR_CONFIG_START (512) /* DDR configuration start. */
+#define POST_STAGE_DDR_CONFIG_DONE (513) /* DDR configuration done. */
+#define POST_STAGE_DDR_CALIBRATE_START (768) /* DDR calibration start. */
+#define POST_STAGE_DDR_CALIBRATE_DONE (769) /* DDR calibration done. */
+#define POST_STAGE_DDR_TEST_START (1024) /* DDR memory test start. */
+#define POST_STAGE_DDR_TEST_DONE (1025) /* DDR memory test done. */
+#define POST_STAGE_REDBOOT_INIT_START (1536) /* Redboot starts execution. */
+#define POST_STAGE_REDBOOT_INIT_DONE (1537) /* Redboot done execution. */
+#define POST_STAGE_FW_IMAGE_LOAD_START (1792) /* Firmware image load to
+ DDR start. */
+#define POST_STAGE_FW_IMAGE_LOAD_DONE (1793) /* Firmware image load
+ to DDR done. */
+#define POST_STAGE_ARMFW_START (2048) /* ARMfw runtime code
+ starts execution. */
+#define POST_STAGE_DHCP_QUERY_START (2304) /* DHCP server query start. */
+#define POST_STAGE_DHCP_QUERY_DONE (2305) /* DHCP server query done. */
+#define POST_STAGE_BOOT_TARGET_DISCOVERY_START (2560) /* Boot Target
+ Discovery Start. */
+#define POST_STAGE_BOOT_TARGET_DISCOVERY_DONE (2561) /* Boot Target
+ Discovery Done. */
+#define POST_STAGE_RC_OPTION_SET (2816) /* Remote configuration
+ option is set in SEEPROM */
+#define POST_STAGE_SWITCH_LINK (2817) /* Wait for link up on switch */
+#define POST_STAGE_SEND_ICDS_MESSAGE (2818) /* Send the ICDS message
+ to switch */
+#define POST_STAGE_PERFROM_TFTP (2819) /* Download xml using TFTP */
+#define POST_STAGE_PARSE_XML (2820) /* Parse XML file */
+#define POST_STAGE_DOWNLOAD_IMAGE (2821) /* Download IMAGE from
+ TFTP server */
+#define POST_STAGE_FLASH_IMAGE (2822) /* Flash the IMAGE */
+#define POST_STAGE_RC_DONE (2823) /* Remote configuration
+ complete */
+#define POST_STAGE_REBOOT_SYSTEM (2824) /* Upgrade IMAGE done,
+ reboot required */
+#define POST_STAGE_MAC_ADDRESS (3072) /* MAC Address Check */
+#define POST_STAGE_ARMFW_READY (49152) /* ARMfw is done with POST
+ and ready. */
+#define POST_STAGE_ARMFW_UE (61440) /* ARMfw has asserted an
+ unrecoverable error. The
+ lower 3 hex digits of the
+ stage code identify the
+ unique error code.
+ */
+
+
+/* --- MGMT_HBA_POST_DUMMY_BITS_ENUM --- */
+#define POST_BIT_ISCSI_LOADED (26)
+#define POST_BIT_OPTROM_INST (27)
+#define POST_BIT_BAD_IP_ADDR (28)
+#define POST_BIT_NO_IP_ADDR (29)
+#define POST_BIT_BACKUP_FW (30)
+#define POST_BIT_ERROR (31)
+
+/* --- MGMT_HBA_POST_DUMMY_VALUES_ENUM --- */
+#define POST_ISCSI_DRIVER_LOADED (67108864)
+#define POST_OPTROM_INSTALLED (134217728)
+#define POST_ISCSI_IP_ADDRESS_CONFLICT (268435456)
+#define POST_ISCSI_NO_IP_ADDRESS (536870912)
+#define POST_BACKUP_FW_LOADED (1073741824)
+#define POST_FATAL_ERROR (2147483648)
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __post_codes_amap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/be_gen_id_ranges.h benet/linux-2.6.24.2/drivers/message/beclib/fw/be_gen_id_ranges.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/be_gen_id_ranges.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/be_gen_id_ranges.h 2008-02-14 15:23:07.828202696 +0530
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2005 - 2007 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*!
+@file
+ be_gen_id_ranges.h
+
+@brief
+ Provides ID ranges and conversion macros between the types of ID numbers.
+
+*/
+#ifndef __be_gen_id_ranges_h__
+#define __be_gen_id_ranges_h__
+
+#ifndef BE_CONFIG
+#pragma message("WARNING: configuration not defined. Assuming BE_CONFIG=0"
+ " by default.")
+#define BE_CONFIG 0
+#endif
+
+#ifndef BE_GEN_ASSERT
+ #error "Error: BE_GEN_ASSERT not defined."
+#endif
+
+#ifndef BE_GEN_STATIC_INLINE
+ #error "Error: BE_GEN_STATIC_INLINE not defined."
+#endif
+
+
+/*/////////////////////////////////////////////////////////////////////// */
+/*
+ * For each BE_CONFIG value, define the CID ranges for the ULP protocol
+ * firmware.
+ *
+ * The BE_CONFIG definitions must match the description of the
+ * configuration under the fw\config\readme.txt file.
+ * The MAX_* literals must all be multiples of 32!!! This is an implementation
+ * restriction in the software that makes use of these literals for bitvector
+ * classes. Having a non-32 multiple MAX_* literal will cause an compile-time
+ * assert! At some point in the future this restriction may be removed (along
+ * with this comment blurb). Note: if the desired range is not an even multiple
+ * of 32, the developer must ensure the extra/invalid bits are not used.
+ */
+/*//////////////////////////////////////////////////////////////////// */
+
+#if (BE_CONFIG == 0)
+
+ /* --- CID_START_ENUM --- */
+ #define ISCSI_CID_START (0) /* Start of connection
+ ID range for ISCSI */
+ #define DEFPDU_CID_START (0) /* Start of connection
+ ID range for iSCSI
+ default pdu queue */
+ #define ETX_CID_START (1024) /* Start of connection
+ ID range for ETX */
+ #define RDMA_CID_START (0) /* Start of connection
+ ID range for RDMA */
+
+ /* --- MAX_CIDS_ENUM --- */
+ #define MAX_DEFPDU_CIDS (32) /* Maximum number of
+ iSCSI DEF pdu cids */
+ #define MAX_ETX_CIDS (64) /* Maximum number of ETX
+ connections */
+ #define MAX_ISCSI_CIDS (512) /* Maximum number of
+ ISCSI connections */
+ #define MAX_ISCSI_CIDS_CT (512) /* Maximum number of
+ ISCSI connections
+ per chute */
+ #define MAX_RDMA_CIDS (0) /* Maximum number of
+ RDMA connections */
+
+#elif (BE_CONFIG == 1)
+
+ /* --- CID_START_ENUM --- */
+ #define ISCSI_CID_START (0) /* Start of connection
+ ID range for ISCSI */
+ #define DEFPDU_CID_START (0) /* Start of connection
+ ID range for iSCSI
+ default pdu queue */
+ #define RDMA_CID_START (64) /* Start of connection
+ ID range for RDMA */
+ #define ETX_CID_START (1024) /* Start of connection
+ ID range for ETX */
+
+ /* --- MAX_CIDS_ENUM --- */
+ #define MAX_DEFPDU_CIDS (32) /* Maximum number of
+ iSCSI DEF pdu cids */
+ #define MAX_ISCSI_CIDS (64) /* Maximum number
+ of ISCSI connections */
+ #define MAX_ISCSI_CIDS_CT (64) /* Maximum number
+ of ISCSI connections
+ per chute */
+ #define MAX_ETX_CIDS (64) /* Maximum number of
+ ETX connections */
+ #define MAX_RDMA_CIDS (512) /* Maximum number
+ of RDMA connections */
+
+#elif (BE_CONFIG == 2)
+
+ /* --- CID_START_ENUM --- */
+ #define DEFPDU_CID_START (0) /* Start of connection
+ ID range for iSCSI
+ default pdu queue */
+ #define ISCSI_TGT_CID_START (448) /* Start of connection
+ ID range for ISCSI */
+ #define ISCSI_CID_START (ISCSI_TGT_CID_START)
+ #define ETX_CID_START (1024) /* Start of connection
+ ID range for ETX */
+ #define RDMA_CID_START (0) /* Start of connection
+ ID range for RDMA */
+
+ /* --- MAX_CIDS_ENUM --- */
+ #define MAX_DEFPDU_CIDS (32) /* Maximum number of
+ iSCSI DEF pdu cids */
+ #define MAX_ETX_CIDS (64) /* Maximum number of
+ ETX cids */
+ #define MAX_ISCSI_TGT_CIDS (512) /* Maximum number
+ of ISCSI connections */
+ #define MAX_ISCSI_CIDS (MAX_ISCSI_TGT_CIDS)
+ #define MAX_ISCSI_CIDS_CT (256) /* Maximum number of
+ ISCSI connections
+ per chute */
+ #define MAX_RDMA_CIDS (0) /* Maximum number of
+ RDMA connections */
+
+#elif (BE_CONFIG == 3)
+
+ /* --- CID_START_ENUM --- */
+ #define DEFPDU_CID_START (0) /* Start of connection
+ ID range for iSCSI
+ default pdu queue */
+ #define ISCSI_TGT_CID_START (0) /* Start of connection
+ ID range for ISCSI */
+ #define ISCSI_CID_START (ISCSI_TGT_CID_START)
+ #define ETX_CID_START (1024) /* Start of connection
+ ID range for ETX */
+ #define RDMA_CID_START (1024) /* Start of connection
+ ID range for RDMA */
+
+ /* --- MAX_CIDS_ENUM --- */
+ #define MAX_DEFPDU_CIDS (32) /* Maximum number
+ of iSCSI DEF pdu cids */
+ #define MAX_ETX_CIDS (64) /* Maximum number
+ of ETX cids */
+ #define MAX_ISCSI_TGT_CIDS (1024) /* Maximum number
+ of ISCSI connections
+ supported. */
+ #define MAX_ISCSI_CIDS (MAX_ISCSI_TGT_CIDS)
+ #define MAX_ISCSI_CIDS_CT (512) /* Maximum number of
+ ISCSI connections per
+ chute */
+ #define MAX_RDMA_CIDS (0) /* Maximum number of
+ RDMA connections */
+
+#elif (BE_CONFIG == 4)
+
+ /* --- CID_START_ENUM --- */
+ #define ISCSI_CID_START (0) /* Start of connection
+ ID range for ISCSI */
+ #define DEFPDU_CID_START (0) /* Start of connection
+ ID range for iSCSI
+ default pdu queue */
+ #define ETX_CID_START (1024) /* Start of connection
+ ID range for ETX */
+ #define RDMA_CID_START (0) /* Start of connection
+ ID range for RDMA */
+
+ /* --- MAX_CIDS_ENUM --- */
+ #define MAX_DEFPDU_CIDS (32) /* Maximum number of
+ iSCSI DEF pdu cids */
+ #define MAX_ETX_CIDS (64) /* Maximum number of
+ ETX connections */
+ #define MAX_ISCSI_CIDS (512) /* Maximum number of
+ ISCSI connections */
+ #define MAX_ISCSI_CIDS_CT (256) /* Maximum number of
+ ISCSI connections per
+ chute */
+ #define MAX_RDMA_CIDS (0) /* Maximum number of
+ RDMA connections */
+
+
+#else
+ #error Error: Invalid configuration (BE_CONFIG unrecognized).
+#endif
+
+
+/* Define the ethernet CIDs used for iSCSI OOO packet replay. Currently
+ * the maximum number of iSCSI chutes/ulps is 2. Each iSCSI chute
+ * requries one reserved CID number. We have chosen the following
+ * format for these literals:
+ * a) ISCSI_OOO_CID - used for replay from iSCSI chute A (rxulp0),
+ * must be an even number
+ * b) ISCSI_OOO_CID1 - used for replay from iSCSI chute B (rxulp1),
+ * must be adjacent to
+ * chute A's CID, only applicable on dual-chute iSCSI
+ */
+#define ISCSI_OOO_CID (1086)
+#define ISCSI_OOO_CID1 (1087)
+
+
+/* Define the ethernet CIDs that have higher priority over normal
+ * ethernet transmit rings. Each etx ULP requires one reserved super
+ * CID number. Currently the maximum number of ethernet chutes is 2.
+ * We have chosen the following format for these literals:
+ * a) ETX_SUPER_CID_ULP2 - used for etx with txulp2
+ * b) ETX_SUPER_CID_ULP1 - used for etx with txulp1
+ *
+ */
+#define ETX_SUPER_CID_ULP2 (ETX_CID_START)
+#define ETX_SUPER_CID_ULP1 (ETX_CID_START + 1)
+
+#endif /* __be_gen_id_ranges_h__ */
+
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
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^ permalink raw reply
* [PATHCH 12/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:54 UTC (permalink / raw)
To: netdev
F/W header files.
-------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_types_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_types_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_types_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_types_bmap.h 2008-02-14 15:23:07.829202544 +0530
@@ -0,0 +1,521 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_types_bmap_h__
+#define __ioctl_types_bmap_h__
+#include "setypes.h"
+#include "host_struct_bmap.h"
+#include "post_codes_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+/* MAC address format */
+typedef struct _MAC_ADDRESS_FORMAT {
+ u16 SizeOfStructure;
+ u8 MACAddress[6];
+} SG_PACK MAC_ADDRESS_FORMAT, *PMAC_ADDRESS_FORMAT;
+
+/* IP address format - handles both IPv4 and IPv6 */
+typedef struct _IP_ADDRESS_FORMAT {
+ u16 SizeOfStructure;
+ u8 Reserved;
+ u8 IPVersion;
+ u8 IPAddress[16];
+ u32 rsvd0;
+} SG_PACK IP_ADDRESS_FORMAT, *PIP_ADDRESS_FORMAT;
+
+/* IP address and Subnet Mask format */
+typedef struct _IP_ADDRESS_SUBNET_FORMAT {
+ u16 SizeOfStructure;
+ u8 Reserved;
+ u8 IPVersion;
+ u8 IPAddress[16];
+ u8 SubNetMask[16];
+ u32 rsvd0;
+} SG_PACK IP_ADDRESS_SUBNET_FORMAT, *PIP_ADDRESS_SUBNET_FORMAT;
+
+/* WWN (Fibre Channel) Format */
+typedef struct _WWN_ADDRESS_FORMAT {
+ u16 SizeOfStructure;
+ u16 Reserved;
+ u8 WWN[8];
+ u32 rsvd0;
+} SG_PACK WWN_ADDRESS_FORMAT, *PWWN_ADDRESS_FORMAT;
+
+/* URL or World Wide Unique ID Format */
+typedef struct _URL_ADDRESS_FORMAT {
+ u16 SizeOfStructure;
+ u16 Reserved;
+ u8 URL[256];
+ u32 rsvd0;
+} SG_PACK URL_ADDRESS_FORMAT, *PURL_ADDRESS_FORMAT;
+
+typedef struct _MGMT_CHAP_NAME_SECRET {
+ u8 chap_name[256];
+ u8 secret[16];
+} SG_PACK MGMT_CHAP_NAME_SECRET, *PMGMT_CHAP_NAME_SECRET;
+
+typedef struct _MGMT_CHAP_FORMAT {
+ u32 flags;
+ u8 intr_chap_name[256];
+ u8 intr_secret[16];
+ u8 target_chap_name[256];
+ u8 target_secret[16];
+} SG_PACK MGMT_CHAP_FORMAT, *PMGMT_CHAP_FORMAT;
+
+typedef union _MGMT_CHAP_SRP_FORMAT {
+ MGMT_CHAP_FORMAT chap;
+} SG_PACK MGMT_CHAP_SRP_FORMAT, *PMGMT_CHAP_SRP_FORMAT;
+
+typedef struct _MGMT_AUTH_METHOD_FORMAT {
+ u8 auth_method_type;
+ u8 padding[3];
+ MGMT_CHAP_SRP_FORMAT chap_srp_format;
+} SG_PACK MGMT_AUTH_METHOD_FORMAT, *PMGMT_AUTH_METHOD_FORMAT;
+
+typedef struct _MGMT_CONN_LOGIN_OPTIONS {
+ u8 flags;
+ u8 header_digest;
+ u8 data_digest;
+ u8 rsvd0;
+ u32 max_recv_datasegment_len_ini;
+ u32 max_recv_datasegment_len_tgt;
+ u32 tcp_mss;
+ u32 tcp_window_size;
+ MGMT_AUTH_METHOD_FORMAT auth_data;
+} SG_PACK MGMT_CONN_LOGIN_OPTIONS, *PMGMT_CONN_LOGIN_OPTIONS;
+
+typedef struct _MGMT_SESSION_LOGIN_OPTIONS {
+ u8 flags;
+ u8 error_recovery_level;
+ u16 rsvd0;
+ u32 first_burst_length;
+ u32 max_burst_length;
+ u16 max_connections;
+ u16 max_outstanding_r2t;
+ u16 default_time2wait;
+ u16 default_time2retain;
+} SG_PACK MGMT_SESSION_LOGIN_OPTIONS, *PMGMT_SESSION_LOGIN_OPTIONS;
+
+typedef struct _MGMT_TARGET_LOGIN_OPTIONS {
+ MGMT_SESSION_LOGIN_OPTIONS sess_login_opts;
+ u8 conn_flags;
+ u8 data_digest;
+ u8 header_digest;
+ u8 rsvd0;
+ u32 max_recv_datasegment_len_tgt;
+} SG_PACK MGMT_TARGET_LOGIN_OPTIONS, *PMGMT_TARGET_LOGIN_OPTIONS;
+
+typedef struct _MGMT_LOGIN_OPTIONS {
+ MGMT_SESSION_LOGIN_OPTIONS sess_login_opts;
+ MGMT_CONN_LOGIN_OPTIONS conn_login_opts;
+} SG_PACK MGMT_LOGIN_OPTIONS, *PMGMT_LOGIN_OPTIONS;
+
+typedef struct _MGMT_CONN_INFO {
+ u32 connection_handle;
+ u32 connection_status;
+ u16 src_port;
+ u16 dest_port;
+ u16 dest_port_redirected;
+ u16 cid;
+ u32 estimated_throughput;
+ IP_ADDRESS_FORMAT src_ipaddr;
+ IP_ADDRESS_FORMAT dest_ipaddr;
+ IP_ADDRESS_FORMAT dest_ipaddr_redirected;
+ MGMT_CONN_LOGIN_OPTIONS negotiated_login_options;
+} SG_PACK MGMT_CONN_INFO, *PMGMT_CONN_INFO;
+
+typedef struct _MGMT_SESSION_INFO {
+ u32 session_handle;
+ u32 status;
+ u8 isid[6];
+ u16 tsih;
+ u32 session_flags;
+ u16 conn_count;
+ u16 pad;
+ u8 target_name[224];
+ u8 initiator_iscsiname[224];
+ MGMT_SESSION_LOGIN_OPTIONS negotiated_login_options;
+ MGMT_CONN_INFO conn_list[1];
+} SG_PACK MGMT_SESSION_INFO, *PMGMT_SESSION_INFO;
+
+typedef struct _CONNECTION_DATA {
+ u32 connection_handle;
+ u32 conn_status;
+ u32 conn_iscsi_cid;
+ u32 estimated_throughput;
+} SG_PACK CONNECTION_DATA, *PCONNECTION_DATA;
+
+typedef struct _MGMT_CONN_LB_INFO {
+ u32 session_handle;
+ u16 conn_count;
+ u16 pad;
+ CONNECTION_DATA conn_list[1];
+} SG_PACK MGMT_CONN_LB_INFO, *PMGMT_CONN_LB_INFO;
+
+typedef struct _MGMT_LUN_MAPPING {
+ u8 lun[8];
+ u16 os_lun;
+ u8 boot_order;
+ u8 pad1;
+ u32 pad2;
+} SG_PACK MGMT_LUN_MAPPING, *PMGMT_LUN_MAPPING;
+
+typedef struct _MGMT_BTL_MAPPING {
+ u32 session_handle;
+ u32 session_status;
+ u32 session_flags;
+ u8 dev_addr_mode;
+ u8 flags;
+ u16 os_bus;
+ u16 os_target;
+ u16 lun_count;
+ MGMT_LUN_MAPPING lun_mapping[1];
+} SG_PACK MGMT_BTL_MAPPING, *PMGMT_BTL_MAPPING;
+
+typedef struct _MGMT_OS_BT {
+ u16 os_bus;
+ u16 os_target;
+ u32 session_handle;
+} SG_PACK MGMT_OS_BT, *PMGMT_OS_BT;
+
+typedef struct _MGMT_PORTAL {
+ IP_ADDRESS_FORMAT ip_address;
+ u16 port_number;
+ u16 flags;
+} SG_PACK MGMT_PORTAL, *PMGMT_PORTAL;
+
+typedef struct _MGMT_PERSISTENT_LOGIN {
+ u8 target_name[224];
+ u32 target_id;
+ u32 flags;
+ u32 iscsi_security_flags;
+ MGMT_PORTAL portal;
+ MGMT_LOGIN_OPTIONS specified_login_options;
+ MGMT_BTL_MAPPING btl_mapping;
+} SG_PACK MGMT_PERSISTENT_LOGIN, *PMGMT_PERSISTENT_LOGIN;
+
+typedef struct _MGMT_TGTID_PORTAL {
+ u32 target_id;
+ MGMT_PORTAL portal;
+} SG_PACK MGMT_TGTID_PORTAL, *PMGMT_TGTID_PORTAL;
+
+typedef struct _MGMT_SLP_PARAMS {
+ u16 flags;
+ u16 rsvd0;
+ u8 scopes[256];
+ u8 querylist[256];
+ u32 multicast_maxwait;
+ u32 multicast_timeout[5];
+ u32 multicast_ttl;
+} SG_PACK MGMT_SLP_PARAMS, *PMGMT_SLP_PARAMS;
+
+typedef struct _MGMT_ISNS_SERVER {
+ IP_ADDRESS_FORMAT ipaddr;
+ u16 tcp_port;
+ u16 udp_port;
+} SG_PACK MGMT_ISNS_SERVER, *PMGMT_ISNS_SERVER;
+
+typedef union _MGMT_ISNS_ENTITY {
+ u8 initiator_iscsiname[224];
+ u8 isns_entity_name[224];
+} SG_PACK MGMT_ISNS_ENTITY, *PMGMT_ISNS_ENTITY;
+
+typedef struct _MGMT_ISNS_PARAMS {
+ u16 flags;
+ u16 rsvd0;
+ MGMT_ISNS_ENTITY entity;
+ u32 srv_count;
+ MGMT_ISNS_SERVER srv_list[4];
+} SG_PACK MGMT_ISNS_PARAMS, *PMGMT_ISNS_PARAMS;
+
+typedef struct _MGMT_PORTAL_ENTRY {
+ MGMT_PORTAL portal;
+ u32 iscsi_security_flags;
+ u32 preshared_keysize;
+ u8 preshared_key[256];
+ u8 isns_sym_name[256];
+} SG_PACK MGMT_PORTAL_ENTRY, *PMGMT_PORTAL_ENTRY;
+
+typedef struct _MGMT_PORTAL_GROUP {
+ u16 pg_tag;
+ u16 portal_count;
+ MGMT_PORTAL_ENTRY portal_list[1];
+} SG_PACK MGMT_PORTAL_GROUP, *PMGMT_PORTAL_GROUP;
+
+typedef struct _MGMT_TARGET_INFO {
+ u32 target_id;
+ u8 target_name[224];
+ u8 target_alias[32];
+ u32 pg_count;
+ MGMT_PORTAL_GROUP pg_list[1];
+} SG_PACK MGMT_TARGET_INFO, *PMGMT_TARGET_INFO;
+
+typedef struct _MGMT_DNS_SERVERS {
+ IP_ADDRESS_FORMAT preferred_dns_server;
+ IP_ADDRESS_FORMAT alternate_dns_server;
+} SG_PACK MGMT_DNS_SERVERS, *PMGMT_DNS_SERVERS;
+
+typedef MGMT_DNS_SERVERS DNS_SERVERS;
+
+typedef struct _IP_ADDRESS_VLAN_FORMAT {
+ IP_ADDRESS_SUBNET_FORMAT ip_address_subnet;
+ u8 vlan_priority_valid;
+ u8 rsvd0;
+ u16 vlan_priority;
+} SG_PACK IP_ADDRESS_VLAN_FORMAT, *PIP_ADDRESS_VLAN_FORMAT;
+
+typedef struct _TCPIP_CONFIGURATION {
+ DNS_SERVERS dns_servers;
+ IP_ADDRESS_FORMAT default_gateway_address;
+ u8 use_link_local_address;
+ u8 dhcp_flags;
+ u8 use_dhcp_for_dns;
+ u8 supported_ipversions;
+ u8 rsvd0;
+ u8 rsvd1;
+ u8 rsvd2;
+ u8 ipaddress_count;
+ IP_ADDRESS_VLAN_FORMAT ipaddress_vlan_list[1];
+} SG_PACK TCPIP_CONFIGURATION, *PTCPIP_CONFIGURATION;
+
+typedef struct _MGMT_NIC_PORT_INFO {
+ u32 speed;
+ u32 max_speed;
+ u32 link_state;
+ u32 max_frame_size;
+ MAC_ADDRESS_FORMAT mac_address;
+} SG_PACK MGMT_NIC_PORT_INFO, *PMGMT_NIC_PORT_INFO;
+
+typedef struct _MGMT_HBA_ATTRIBUTES {
+ u8 flashrom_version_string[32];
+ u8 manufacturer_name[32];
+ u8 rsvd0[28];
+ u32 default_extended_timeout;
+ u8 controller_model_number[32];
+ u8 controller_description[64];
+ u8 controller_serial_number[32];
+ u8 ip_version_string[32];
+ u8 firmware_version_string[32];
+ u8 bios_version_string[32];
+ u8 redboot_version_string[32];
+ u8 driver_version_string[32];
+ u8 fw_on_flash_version_string[32];
+ u32 functionalities_supported;
+ u16 max_cdblength;
+ u8 asic_revision;
+ u8 generational_guid[16];
+ u8 hba_port_count;
+ u16 default_link_down_timeout;
+ u8 iscsi_ver_min_max;
+ u8 multifunction_device;
+ u8 cache_vaild;
+ u8 hba_status;
+ u8 max_domains_supported;
+ u8 VLD_status;
+ u32 firmware_post_status;
+ u32 hba_mtu;
+} SG_PACK MGMT_HBA_ATTRIBUTES, *PMGMT_HBA_ATTRIBUTES;
+
+typedef struct _MGMT_CONTROLLER_ATTRIBUTES {
+ MGMT_HBA_ATTRIBUTES hba_attribs;
+ u16 pci_vendor_id;
+ u16 pci_device_id;
+ u16 pci_sub_vendor_id;
+ u16 pci_sub_system_id;
+ u8 pci_bus_number;
+ u8 pci_device_number;
+ u8 pci_function_number;
+ u8 interface_type;
+ u64 unique_identifier;
+} SG_PACK MGMT_CONTROLLER_ATTRIBUTES, *PMGMT_CONTROLLER_ATTRIBUTES;
+
+typedef struct _FIS_DIR_ENTRY {
+ u8 name[16];
+ u32 flash_addr;
+ u32 mem_addr;
+ u32 length;
+ u32 entry;
+ u32 data_length;
+} SG_PACK FIS_DIR_ENTRY, *PFIS_DIR_ENTRY;
+
+typedef struct _IMAGE_INFO_T {
+ u32 ImageId;
+ u32 ImageOffset;
+ u32 ImageLength;
+ u32 ImageChecksum;
+ u32 ImageVersion;
+} SG_PACK IMAGE_INFO_T, *PIMAGE_INFO_T;
+
+typedef struct _CONTROLLER_ID_T {
+ u32 Vendor;
+ u32 Device;
+ u32 SubVendor;
+ u32 SubDevice;
+} SG_PACK CONTROLLER_ID_T, *PCONTROLLER_ID_T;
+
+typedef struct _FILE_HEADER_T {
+ u8 FH_Signature[32];
+ u32 FH_Checksum;
+ u32 FH_Antidote;
+ CONTROLLER_ID_T FH_ContrlId;
+ u32 FH_FileLen;
+ u32 FH_ChunkNum;
+ u32 FH_TotalChunks;
+ u32 FH_NumOfImgs;
+ u32 FH_Build;
+} SG_PACK FILE_HEADER_T, *PFILE_HEADER_T;
+
+typedef struct _FLASHDIR_HEADER_TYPE {
+ u32 flashdir_format_rev;
+ u32 flashwide_checksum;
+ u32 flashwide_antidote;
+ u32 build_number;
+ u8 UFIIdentifierString[64];
+ u32 active_entry_mask;
+ u32 valid_entry_mask;
+ u32 original_content_mask;
+ u32 rsvd0;
+ u32 rsvd1;
+ u32 rsvd2;
+ u32 rsvd3;
+ u32 rsvd4;
+} SG_PACK FLASHDIR_HEADER_TYPE, *PFLASHDIR_HEADER_TYPE;
+
+/* Entry Type Definitions */
+typedef struct _FLASHDIR_ENTRY_TYPE {
+ u32 entry_type;
+ u32 offset;
+ u32 pad_size;
+ u32 image_size;
+ u32 entry_checksum;
+ u32 entry_point;
+ u32 future_use1;
+ u32 future_use2;
+ u8 version_data[32];
+} SG_PACK FLASHDIR_ENTRY_TYPE, *PFLASHDIR_ENTRY_TYPE;
+
+/* Definition of the directory as a whole */
+typedef struct _FLASHDIR_TYPE {
+ u8 flashdir_cookie[32];
+ FLASHDIR_HEADER_TYPE flashdir_header;
+ FLASHDIR_ENTRY_TYPE flashdir_entry[32];
+} SG_PACK FLASHDIR_TYPE, *PFLASHDIR_TYPE;
+
+typedef struct _MGMT_BUS_ADDRESS32 {
+ u32 address_lo;
+ u32 address_hi;
+} SG_PACK MGMT_BUS_ADDRESS32, *PMGMT_BUS_ADDRESS32;
+
+typedef struct _MGMT_BUS_ADDRESS64 {
+ u64 address;
+} SG_PACK MGMT_BUS_ADDRESS64, *PMGMT_BUS_ADDRESS64;
+
+typedef union _IOCTL_TYPES_ANON_168_U {
+ MGMT_BUS_ADDRESS32 a32;
+ MGMT_BUS_ADDRESS64 a64;
+} SG_PACK IOCTL_TYPES_ANON_168_U, *PIOCTL_TYPES_ANON_168_U;
+
+typedef struct _MGMT_BUS_ADDRESS {
+ IOCTL_TYPES_ANON_168_U u;
+} SG_PACK MGMT_BUS_ADDRESS, *PMGMT_BUS_ADDRESS;
+
+typedef struct _MGMT_SG_ELEMENT {
+ MGMT_BUS_ADDRESS address;
+ u32 length;
+ u32 offset;
+} SG_PACK MGMT_SG_ELEMENT, *PMGMT_SG_ELEMENT;
+
+typedef struct _MGMT_SG_TABLE {
+ u32 sg_count;
+ u32 rsvd0;
+ MGMT_SG_ELEMENT sg_list[1];
+} SG_PACK MGMT_SG_TABLE, *PMGMT_SG_TABLE;
+
+/* Template header used in the offload IOCTLs. */
+typedef union _MPU_TEMPLATE_HEADER {
+ u32 rsvd0[14]; /* DWORDS 0 to 13 */
+ u32 rsvd1[15]; /* DWORDS 14 to 28 */
+ u32 rsvd2[16]; /* DWORDS 29 to 44 */
+ u32 rsvd3[17]; /* DWORDS 45 to 61 */
+ u32 rsvd4[32];
+} SG_PACK MPU_TEMPLATE_HEADER, *PMPU_TEMPLATE_HEADER;
+
+typedef struct _IOCTL_TYPES_ANON_169_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:28; /* DWORD 0 */
+} SG_PACK IOCTL_TYPES_ANON_169_RSVD, *PIOCTL_TYPES_ANON_169_RSVD;
+
+/*
+ * This structure defines a single offloaded connection entry in the
+ * Offload Connection Table.
+ */
+typedef struct _MPU_OFFLOAD_CXN_ENTRY {
+ u32 srcAddr; /* DWORD 0 */
+ u32 dstAddr; /* DWORD 1 */
+ u32 srcPort:16; /* DWORD 2 */
+ u32 dstPort:16; /* DWORD 2 */
+ u32 ct:2; /* DWORD 3 */
+ u32 rsvd0:29; /* DWORD 3 */
+ u32 valid:1; /* DWORD 3 */
+} SG_PACK MPU_OFFLOAD_CXN_ENTRY, *PMPU_OFFLOAD_CXN_ENTRY;
+
+typedef struct _ARP_TABLE_ENTRY {
+ IP_ADDRESS_FORMAT ip_address;
+ MAC_ADDRESS_FORMAT mac_address;
+ u32 arp_flags;
+ u32 rsvd0;
+} SG_PACK ARP_TABLE_ENTRY, *PARP_TABLE_ENTRY;
+
+typedef struct _ROUTE_TABLE_ENTRY {
+ IP_ADDRESS_SUBNET_FORMAT ip_address_subnet;
+ IP_ADDRESS_FORMAT next_hop;
+} SG_PACK ROUTE_TABLE_ENTRY, *PROUTE_TABLE_ENTRY;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_types_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/etx_context_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/etx_context_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/etx_context_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/etx_context_bmap.h 2008-02-14 15:23:07.829202544 +0530
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __etx_context_bmap_h__
+#define __etx_context_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* ETX ring context structure. */
+typedef struct _ETX_CONTEXT {
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 tx_cidx:11; /* DWORD 0 */
+ u32 cq_id_send:10; /* DWORD 1 */
+ u32 pd_id_not_valid:1; /* DWORD 1 */
+ u32 pd_id:5; /* DWORD 1 */
+ u32 tx_ring_size:4; /* DWORD 1 */
+ u32 rsvd2:1; /* DWORD 1 */
+ u32 tx_pidx:11; /* DWORD 1 */
+ u32 rsvd3[1]; /* DWORDS 2 to 2 */
+ u32 rsvd4[1]; /* DWORDS 3 to 3 */
+ u32 cur_bytes; /* DWORD 4 */
+ u32 max_bytes; /* DWORD 5 */
+ u32 time_stamp; /* DWORD 6 */
+ u32 rsvd6:20; /* DWORD 7 */
+ u32 func:1; /* DWORD 7 */
+ u32 rsvd5:11; /* DWORD 7 */
+ u32 cur_txd_count; /* DWORD 8 */
+ u32 max_txd_count; /* DWORD 9 */
+ u32 rsvd7[1]; /* DWORDS 10 to 10 */
+ u32 rsvd8[1]; /* DWORDS 11 to 11 */
+ u32 rsvd9[1]; /* DWORDS 12 to 12 */
+ u32 rsvd10[1]; /* DWORDS 13 to 13 */
+ u32 rsvd11[1]; /* DWORDS 14 to 14 */
+ u32 rsvd12[1]; /* DWORDS 15 to 15 */
+} SG_PACK ETX_CONTEXT, *PETX_CONTEXT;
+
+#else
+ /* ETX ring context structure. */
+typedef struct _ETX_CONTEXT {
+ u32 tx_cidx:11; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 tx_pidx:11; /* DWORD 1 */
+ u32 rsvd2:1; /* DWORD 1 */
+ u32 tx_ring_size:4; /* DWORD 1 */
+ u32 pd_id:5; /* DWORD 1 */
+ u32 pd_id_not_valid:1; /* DWORD 1 */
+ u32 cq_id_send:10; /* DWORD 1 */
+ u32 rsvd3[1]; /* DWORDS 2 to 2 */
+ u32 rsvd4[1]; /* DWORDS 3 to 3 */
+ u32 cur_bytes; /* DWORD 4 */
+ u32 max_bytes; /* DWORD 5 */
+ u32 time_stamp; /* DWORD 6 */
+ u32 rsvd5:11; /* DWORD 7 */
+ u32 func:1; /* DWORD 7 */
+ u32 rsvd6:20; /* DWORD 7 */
+ u32 cur_txd_count; /* DWORD 8 */
+ u32 max_txd_count; /* DWORD 9 */
+ u32 rsvd7[1]; /* DWORDS 10 to 10 */
+ u32 rsvd8[1]; /* DWORDS 11 to 11 */
+ u32 rsvd9[1]; /* DWORDS 12 to 12 */
+ u32 rsvd10[1]; /* DWORDS 13 to 13 */
+ u32 rsvd11[1]; /* DWORDS 14 to 14 */
+ u32 rsvd12[1]; /* DWORDS 15 to 15 */
+} SG_PACK ETX_CONTEXT, *PETX_CONTEXT;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __etx_context_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/host_struct_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/host_struct_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/host_struct_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/host_struct_bmap.h 2008-02-14 15:23:07.830202392 +0530
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __host_struct_bmap_h__
+#define __host_struct_bmap_h__
+#include "setypes.h"
+#include "be_cm_bmap.h"
+#include "be_common_bmap.h"
+#include "descriptors_bmap.h"
+#include "iscsi_initiator_host_struct_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Queue Entry Definition for all 4 byte event queue types. */
+typedef struct _EQ_ENTRY {
+ u32 ResourceID:16; /* DWORD 0 */
+ u32 MinorCode:12; /* DWORD 0 */
+ u32 MajorCode:3; /* DWORD 0 */
+ u32 Valid:1; /* DWORD 0 */
+} SG_PACK EQ_ENTRY, *PEQ_ENTRY;
+
+#else
+ /* Queue Entry Definition for all 4 byte event queue types. */
+typedef struct _EQ_ENTRY {
+ u32 Valid:1; /* DWORD 0 */
+ u32 MajorCode:3; /* DWORD 0 */
+ u32 MinorCode:12; /* DWORD 0 */
+ u32 ResourceID:16; /* DWORD 0 */
+} SG_PACK EQ_ENTRY, *PEQ_ENTRY;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Work request block that the driver issues to the chip for Ethernet
+ * transmissions. All control fields must be valid in each WRB for
+ * a message. The controller, as specified by the flags, optionally
+ * writes an entry to the Completion Ring and generate an event.
+ *
+ */
+typedef struct _ETH_WRB {
+ u32 frag_pa_hi; /* DWORD 0 */
+ u32 frag_pa_lo; /* DWORD 1 */
+ u32 lso_mss:14; /* DWORD 2 */
+ u32 hash_val:3; /* DWORD 2 */
+ u32 dbg:3; /* DWORD 2 */
+ u32 vlan:1; /* DWORD 2 */
+ u32 last:1; /* DWORD 2 */
+ u32 lso:1; /* DWORD 2 */
+ u32 tcpcs:1; /* DWORD 2 */
+ u32 udpcs:1; /* DWORD 2 */
+ u32 ipcs:1; /* DWORD 2 */
+ u32 mgmt:1; /* DWORD 2 */
+ u32 ipsec:1; /* DWORD 2 */
+ u32 forward:1; /* DWORD 2 */
+ u32 crc:1; /* DWORD 2 */
+ u32 event:1; /* DWORD 2 */
+ u32 complete:1; /* DWORD 2 */
+ u32 vlan_tag:16; /* DWORD 3 */
+ u32 frag_len:16; /* DWORD 3 */
+} SG_PACK ETH_WRB, *PETH_WRB;
+
+#else
+ /*
+ * Work request block that the driver issues to the chip for Ethernet
+ * transmissions. All control fields must be valid in each WRB for
+ * a message. The controller, as specified by the flags, optionally
+ * writes an entry to the Completion Ring and generate an event.
+ *
+ */
+typedef struct _ETH_WRB {
+ u32 frag_pa_hi; /* DWORD 0 */
+ u32 frag_pa_lo; /* DWORD 1 */
+ u32 complete:1; /* DWORD 2 */
+ u32 event:1; /* DWORD 2 */
+ u32 crc:1; /* DWORD 2 */
+ u32 forward:1; /* DWORD 2 */
+ u32 ipsec:1; /* DWORD 2 */
+ u32 mgmt:1; /* DWORD 2 */
+ u32 ipcs:1; /* DWORD 2 */
+ u32 udpcs:1; /* DWORD 2 */
+ u32 tcpcs:1; /* DWORD 2 */
+ u32 lso:1; /* DWORD 2 */
+ u32 last:1; /* DWORD 2 */
+ u32 vlan:1; /* DWORD 2 */
+ u32 dbg:3; /* DWORD 2 */
+ u32 hash_val:3; /* DWORD 2 */
+ u32 lso_mss:14; /* DWORD 2 */
+ u32 frag_len:16; /* DWORD 3 */
+ u32 vlan_tag:16; /* DWORD 3 */
+} SG_PACK ETH_WRB, *PETH_WRB;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* This is an Ethernet transmit completion descriptor */
+typedef struct _ETH_TX_COMPL {
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 lso:1; /* DWORD 0 */
+ u32 nwh_bytes:8; /* DWORD 0 */
+ u32 user_bytes:16; /* DWORD 0 */
+ u32 status:4; /* DWORD 1 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 port:2; /* DWORD 1 */
+ u32 ct:2; /* DWORD 1 */
+ u32 wrb_index:16; /* DWORD 1 */
+ u32 valid:1; /* DWORD 2 */
+ u32 hash_val:4; /* DWORD 2 */
+ u32 ringid:11; /* DWORD 2 */
+ u32 rsvd2:16; /* DWORD 2 */
+ u32 rsvd3[1]; /* DWORDS 3 to 3 */
+} SG_PACK ETH_TX_COMPL, *PETH_TX_COMPL;
+
+#else
+ /* This is an Ethernet transmit completion descriptor */
+typedef struct _ETH_TX_COMPL {
+ u32 user_bytes:16; /* DWORD 0 */
+ u32 nwh_bytes:8; /* DWORD 0 */
+ u32 lso:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 wrb_index:16; /* DWORD 1 */
+ u32 ct:2; /* DWORD 1 */
+ u32 port:2; /* DWORD 1 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 status:4; /* DWORD 1 */
+ u32 rsvd2:16; /* DWORD 2 */
+ u32 ringid:11; /* DWORD 2 */
+ u32 hash_val:4; /* DWORD 2 */
+ u32 valid:1; /* DWORD 2 */
+ u32 rsvd3[1]; /* DWORDS 3 to 3 */
+} SG_PACK ETH_TX_COMPL, *PETH_TX_COMPL;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Ethernet Receive Buffer descriptor */
+typedef struct _ETH_RX_D {
+ u32 fragpa_hi; /* DWORD 0 */
+ u32 fragpa_lo; /* DWORD 1 */
+} SG_PACK ETH_RX_D, *PETH_RX_D;
+
+#else
+ /* Ethernet Receive Buffer descriptor */
+typedef struct _ETH_RX_D {
+ u32 fragpa_hi; /* DWORD 0 */
+ u32 fragpa_lo; /* DWORD 1 */
+} SG_PACK ETH_RX_D, *PETH_RX_D;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* This is an Ethernet Receive Completion Descriptor */
+typedef struct _ETH_RX_COMPL {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 port:1; /* DWORD 0 */
+ u32 pktsize:14; /* DWORD 0 */
+ u32 vlan_tag:16; /* DWORD 0 */
+ u32 numfrags:3; /* DWORD 1 */
+ u32 ipsec:1; /* DWORD 1 */
+ u32 ct:2; /* DWORD 1 */
+ u32 fragndx:10; /* DWORD 1 */
+ u32 vtm:1; /* DWORD 1 */
+ u32 vtp:1; /* DWORD 1 */
+ u32 macdst:6; /* DWORD 1 */
+ u32 udpcksm:1; /* DWORD 1 */
+ u32 tcpcksm:1; /* DWORD 1 */
+ u32 ipcksm:1; /* DWORD 1 */
+ u32 udpf:1; /* DWORD 1 */
+ u32 tcpf:1; /* DWORD 1 */
+ u32 ipf:1; /* DWORD 1 */
+ u32 rsshp:1; /* DWORD 1 */
+ u32 err:1; /* DWORD 1 */
+ u32 valid:1; /* DWORD 2 */
+ u32 rsvd1:31; /* DWORD 2 */
+ u32 rsshash; /* DWORD 3 */
+} SG_PACK ETH_RX_COMPL, *PETH_RX_COMPL;
+
+#else
+ /* This is an Ethernet Receive Completion Descriptor */
+typedef struct _ETH_RX_COMPL {
+ u32 vlan_tag:16; /* DWORD 0 */
+ u32 pktsize:14; /* DWORD 0 */
+ u32 port:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 err:1; /* DWORD 1 */
+ u32 rsshp:1; /* DWORD 1 */
+ u32 ipf:1; /* DWORD 1 */
+ u32 tcpf:1; /* DWORD 1 */
+ u32 udpf:1; /* DWORD 1 */
+ u32 ipcksm:1; /* DWORD 1 */
+ u32 tcpcksm:1; /* DWORD 1 */
+ u32 udpcksm:1; /* DWORD 1 */
+ u32 macdst:6; /* DWORD 1 */
+ u32 vtp:1; /* DWORD 1 */
+ u32 vtm:1; /* DWORD 1 */
+ u32 fragndx:10; /* DWORD 1 */
+ u32 ct:2; /* DWORD 1 */
+ u32 ipsec:1; /* DWORD 1 */
+ u32 numfrags:3; /* DWORD 1 */
+ u32 rsvd1:31; /* DWORD 2 */
+ u32 valid:1; /* DWORD 2 */
+ u32 rsshash; /* DWORD 3 */
+} SG_PACK ETH_RX_COMPL, *PETH_RX_COMPL;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __host_struct_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/doorbells_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/doorbells_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/doorbells_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/doorbells_bmap.h 2008-02-14 15:23:07.830202392 +0530
@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __doorbells_bmap_h__
+#define __doorbells_bmap_h__
+#include "setypes.h"
+#include "pcicfg_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* The TX/RDMA send queue doorbell. */
+typedef struct _SQ_DB {
+ union {
+ struct {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 numPosted:14; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 cid:11; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK SQ_DB, *PSQ_DB;
+
+SG_C_ASSERT(__sizeof__SQ_DB, sizeof(SQ_DB) == 4);
+
+#else
+ /* The TX/RDMA send queue doorbell. */
+typedef struct _SQ_DB {
+ union {
+ struct {
+ u32 cid:11; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 numPosted:14; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK SQ_DB, *PSQ_DB;
+
+SG_C_ASSERT(__sizeof__SQ_DB, sizeof(SQ_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* The receive queue doorbell. */
+typedef struct _RQ_DB {
+ union {
+ struct {
+ u32 numPosted:8; /* DWORD 0 */
+ u32 Invalidate:1; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 rq:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK RQ_DB, *PRQ_DB;
+
+SG_C_ASSERT(__sizeof__RQ_DB, sizeof(RQ_DB) == 4);
+
+#else
+ /* The receive queue doorbell. */
+typedef struct _RQ_DB {
+ union {
+ struct {
+ u32 rq:10; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 Invalidate:1; /* DWORD 0 */
+ u32 numPosted:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK RQ_DB, *PRQ_DB;
+
+SG_C_ASSERT(__sizeof__RQ_DB, sizeof(RQ_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * The CQ/EQ doorbell. Software MUST set reserved fields in this descriptor
+ * to zero, otherwise (CEV) hardware will not execute the doorbell
+ * (flagging a bad_db_qid error instead).
+ */
+typedef struct _CQ_DB {
+ union {
+ struct {
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 num_popped:13; /* DWORD 0 */
+ u32 event:1; /* DWORD 0 */
+ u32 rearm:1; /* DWORD 0 */
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 qid:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CQ_DB, *PCQ_DB;
+
+SG_C_ASSERT(__sizeof__CQ_DB, sizeof(CQ_DB) == 4);
+
+#else
+ /*
+ * The CQ/EQ doorbell. Software MUST set reserved fields in this descriptor
+ * to zero, otherwise (CEV) hardware will not execute the doorbell
+ * (flagging a bad_db_qid error instead).
+ */
+typedef struct _CQ_DB {
+ union {
+ struct {
+ u32 qid:10; /* DWORD 0 */
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 rearm:1; /* DWORD 0 */
+ u32 event:1; /* DWORD 0 */
+ u32 num_popped:13; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CQ_DB, *PCQ_DB;
+
+SG_C_ASSERT(__sizeof__CQ_DB, sizeof(CQ_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+typedef struct _TPM_RQ_DB {
+ union {
+ struct {
+ u32 mss_cnt:5; /* DWORD 0 */
+ u32 numPosted:11; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 qid:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK TPM_RQ_DB, *PTPM_RQ_DB;
+
+SG_C_ASSERT(__sizeof__TPM_RQ_DB, sizeof(TPM_RQ_DB) == 4);
+
+#else
+typedef struct _TPM_RQ_DB {
+ union {
+ struct {
+ u32 qid:10; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 numPosted:11; /* DWORD 0 */
+ u32 mss_cnt:5; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK TPM_RQ_DB, *PTPM_RQ_DB;
+
+SG_C_ASSERT(__sizeof__TPM_RQ_DB, sizeof(TPM_RQ_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Post WRB Queue Doorbell Register used by the host Storage stack to
+ * notify the controller of a posted Work Request Block
+ */
+typedef struct _WRB_POST_DB {
+ union {
+ struct {
+ u32 numberPosted:8; /* DWORD 0 */
+ u32 wrb_index:8; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 wrb_cid:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK WRB_POST_DB, *PWRB_POST_DB;
+
+SG_C_ASSERT(__sizeof__WRB_POST_DB, sizeof(WRB_POST_DB) == 4);
+
+#else
+ /*
+ * Post WRB Queue Doorbell Register used by the host Storage stack to
+ * notify the controller of a posted Work Request Block
+ */
+typedef struct _WRB_POST_DB {
+ union {
+ struct {
+ u32 wrb_cid:10; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 wrb_index:8; /* DWORD 0 */
+ u32 numberPosted:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK WRB_POST_DB, *PWRB_POST_DB;
+
+SG_C_ASSERT(__sizeof__WRB_POST_DB, sizeof(WRB_POST_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Update Default PDU Queue Doorbell Register used to communicate to
+ * the controller that the driver has stopped processing the queue
+ * and where in the queue it stopped, this is a CQ Entry Type. Used
+ * by storage driver.
+ */
+typedef struct _DEFAULT_PDU_DB {
+ union {
+ struct {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 cqproc:14; /* DWORD 0 */
+ u32 event:1; /* DWORD 0 */
+ u32 rearm:1; /* DWORD 0 */
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 qid:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK DEFAULT_PDU_DB, *PDEFAULT_PDU_DB;
+
+SG_C_ASSERT(__sizeof__DEFAULT_PDU_DB, sizeof(DEFAULT_PDU_DB) == 4);
+
+#else
+ /*
+ * Update Default PDU Queue Doorbell Register used to communicate to
+ * the controller that the driver has stopped processing the queue
+ * and where in the queue it stopped, this is a CQ Entry Type. Used
+ * by storage driver.
+ */
+typedef struct _DEFAULT_PDU_DB {
+ union {
+ struct {
+ u32 qid:10; /* DWORD 0 */
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 rearm:1; /* DWORD 0 */
+ u32 event:1; /* DWORD 0 */
+ u32 cqproc:14; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK DEFAULT_PDU_DB, *PDEFAULT_PDU_DB;
+
+SG_C_ASSERT(__sizeof__DEFAULT_PDU_DB, sizeof(DEFAULT_PDU_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Management Command and Controller default fragment ring */
+typedef struct _MCC_DB {
+ union {
+ struct {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 numPosted:14; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 rid:11; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MCC_DB, *PMCC_DB;
+
+SG_C_ASSERT(__sizeof__MCC_DB, sizeof(MCC_DB) == 4);
+
+#else
+ /* Management Command and Controller default fragment ring */
+typedef struct _MCC_DB {
+ union {
+ struct {
+ u32 rid:11; /* DWORD 0 */
+ u32 rsvd0:5; /* DWORD 0 */
+ u32 numPosted:14; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MCC_DB, *PMCC_DB;
+
+SG_C_ASSERT(__sizeof__MCC_DB, sizeof(MCC_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Used for bootstrapping the Host interface. This register is used
+ * for driver communication with the MPU when no MCC Rings exist.
+ * The software must write this register twice to post any MCC
+ * command. First, it writes the register with hi=1 and the upper
+ * bits of the physical address for the MCC_MAILBOX structure. Software
+ * must poll the ready bit until this is acknowledged. Then, sotware
+ * writes the register with hi=0 with the lower bits in the address.
+ * It must poll the ready bit until the MCC command is complete.
+ * Upon completion, the MCC_MAILBOX will contain a valid completion
+ * queue entry.
+ */
+typedef struct _MPU_MAILBOX_DB {
+ union {
+ struct {
+ u32 address:30; /* DWORD 0 */
+ u32 hi:1; /* DWORD 0 */
+ u32 ready:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MPU_MAILBOX_DB, *PMPU_MAILBOX_DB;
+
+SG_C_ASSERT(__sizeof__MPU_MAILBOX_DB, sizeof(MPU_MAILBOX_DB) == 4);
+
+#else
+ /*
+ * Used for bootstrapping the Host interface. This register is used
+ * for driver communication with the MPU when no MCC Rings exist.
+ * The software must write this register twice to post any MCC command.
+ * First, it writes the register with hi=1 and the upper bits of
+ * the physical address for the MCC_MAILBOX structure. Software must
+ * poll the ready bit until this is acknowledged. Then, sotware writes
+ * the register with hi=0 with the lower bits in the address. It
+ * must poll the ready bit until the MCC command is complete. Upon
+ * completion, the MCC_MAILBOX will contain a valid completion queue
+ * entry.
+ */
+typedef struct _MPU_MAILBOX_DB {
+ union {
+ struct {
+ u32 ready:1; /* DWORD 0 */
+ u32 hi:1; /* DWORD 0 */
+ u32 address:30; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MPU_MAILBOX_DB, *PMPU_MAILBOX_DB;
+
+SG_C_ASSERT(__sizeof__MPU_MAILBOX_DB, sizeof(MPU_MAILBOX_DB) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This is the protection domain doorbell register map. Note that while
+ * this map shows doorbells for all Blade Engine supported protocols,
+ * not all of these may be valid in a given function or protection
+ * domain. It is the responsibility of the application accessing
+ * the doorbells to know which are valid. Each doorbell occupies
+ * 32 bytes of space, but unless otherwise specified, only the first
+ * 4 bytes should be written. </p> There are 32 instances of these
+ * doorbells for the host and 31 virtual machines respectively. The
+ * host and VMs will only map the doorbell pages belonging to its
+ * protection domain. It will not be able to touch the doorbells
+ * for another VM. The doorbells are the only registers directly
+ * accessible by a virtual machine. Similarly, there are 511 additional
+ * doorbells for RDMA protection domains. PD 0 for RDMA shares the
+ * same physical protection domain doorbell page as ETH/iSCSI. </p>
+ */
+typedef struct _PROTECTION_DOMAIN_DBMAP {
+ union {
+ struct {
+ u32 rsvd0[16]; /* DWORDS 0 to 15 */
+ SQ_DB rdma_sq_db;
+ u32 rsvd1[7]; /* DWORDS 17 to 23 */
+ WRB_POST_DB iscsi_wrb_post_db;
+ u32 rsvd2[7]; /* DWORDS 25 to 31 */
+ SQ_DB etx_sq_db;
+ u32 rsvd3[7]; /* DWORDS 33 to 39 */
+ RQ_DB rdma_rq_db;
+ u32 rsvd4[7]; /* DWORDS 41 to 47 */
+ DEFAULT_PDU_DB iscsi_default_pdu_db;
+ u32 rsvd5[7]; /* DWORDS 49 to 55 */
+ TPM_RQ_DB tpm_rq_db;
+ u32 rsvd6[7]; /* DWORDS 57 to 63 */
+ RQ_DB erx_rq_db;
+ u32 rsvd7[7]; /* DWORDS 65 to 71 */
+ CQ_DB cq_db;
+ u32 rsvd8[7]; /* DWORDS 73 to 79 */
+ MCC_DB mpu_mcc_db;
+ u32 rsvd9[7]; /* DWORDS 81 to 87 */
+ MPU_MAILBOX_DB mcc_bootstrap_db;
+ u32 rsvd10[935]; /* DWORDS 89 to 1023 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1024]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PROTECTION_DOMAIN_DBMAP, *PPROTECTION_DOMAIN_DBMAP;
+
+SG_C_ASSERT(__sizeof__PROTECTION_DOMAIN_DBMAP,
+ sizeof(PROTECTION_DOMAIN_DBMAP) == 4096);
+
+#else
+ /*
+ * This is the protection domain doorbell register map. Note that
+ * while this map shows doorbells for all Blade Engine supported
+ * protocols, not all of these may be valid in a given function
+ * or protection domain. It is the responsibility of the application
+ * accessing the doorbells to know which are valid. Each doorbell
+ * occupies 32 bytes of space, but unless otherwise specified, only
+ * the first 4 bytes should be written. There are 32 instances of
+ * these doorbells for the host and 31 virtual machines respectively.
+ * The host and VMs will only map the doorbell pages belonging to
+ * its protection domain. It will not be able to touch the doorbells
+ * for another VM. The doorbells are the only registers directly
+ * accessible by a virtual machine. Similarly, there are 511 additional
+ * doorbells for RDMA protection domains. PD 0 for RDMA shares the
+ * same physical protection domain doorbell page as ETH/iSCSI.
+ */
+typedef struct _PROTECTION_DOMAIN_DBMAP {
+ union {
+ struct {
+ u32 rsvd0[16]; /* DWORDS 0 to 15 */
+ SQ_DB rdma_sq_db;
+ u32 rsvd1[7]; /* DWORDS 17 to 23 */
+ WRB_POST_DB iscsi_wrb_post_db;
+ u32 rsvd2[7]; /* DWORDS 25 to 31 */
+ SQ_DB etx_sq_db;
+ u32 rsvd3[7]; /* DWORDS 33 to 39 */
+ RQ_DB rdma_rq_db;
+ u32 rsvd4[7]; /* DWORDS 41 to 47 */
+ DEFAULT_PDU_DB iscsi_default_pdu_db;
+ u32 rsvd5[7]; /* DWORDS 49 to 55 */
+ TPM_RQ_DB tpm_rq_db;
+ u32 rsvd6[7]; /* DWORDS 57 to 63 */
+ RQ_DB erx_rq_db;
+ u32 rsvd7[7]; /* DWORDS 65 to 71 */
+ CQ_DB cq_db;
+ u32 rsvd8[7]; /* DWORDS 73 to 79 */
+ MCC_DB mpu_mcc_db;
+ u32 rsvd9[7]; /* DWORDS 81 to 87 */
+ MPU_MAILBOX_DB mcc_bootstrap_db;
+ u32 rsvd10[935]; /* DWORDS 89 to 1023 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1024]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PROTECTION_DOMAIN_DBMAP, *PPROTECTION_DOMAIN_DBMAP;
+
+SG_C_ASSERT(__sizeof__PROTECTION_DOMAIN_DBMAP,
+ sizeof(PROTECTION_DOMAIN_DBMAP) == 4096);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __doorbells_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_bmap.h 2008-02-14 15:23:07.831202240 +0530
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __mpu_bmap_h__
+#define __mpu_bmap_h__
+#include "setypes.h"
+#include "ep_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Provide control parameters for the Managment Processor Unit. */
+typedef struct _MPU_CSRMAP {
+ EP_CSRMAP ep;
+ u32 rsvd0[4]; /* DWORDS 64 to 67 */
+ u32 rsvd1[1]; /* DWORDS 68 to 68 */
+ u32 rsvd2[6]; /* DWORDS 69 to 74 */
+ u32 rsvd3[6]; /* DWORDS 75 to 80 */
+ u32 rsvd4[1]; /* DWORDS 81 to 81 */
+ u32 rsvd5[1]; /* DWORDS 82 to 82 */
+ u32 rsvd6[1]; /* DWORDS 83 to 83 */
+ u32 rsvd7[1]; /* DWORDS 84 to 84 */
+ u32 rsvd8[1]; /* DWORDS 85 to 85 */
+ u32 rsvd9[1]; /* DWORDS 86 to 86 */
+ u32 rsvd10[1]; /* DWORDS 87 to 87 */
+ u32 rsvd11[1]; /* DWORDS 88 to 88 */
+ u32 rsvd12[1]; /* DWORDS 89 to 89 */
+ u32 rsvd13[1]; /* DWORDS 90 to 90 */
+ u32 rsvd14[1]; /* DWORDS 91 to 91 */
+ u32 rsvd15[1]; /* DWORDS 92 to 92 */
+ u32 rsvd16[1]; /* DWORDS 93 to 93 */
+ u32 rsvd17[1]; /* DWORDS 94 to 94 */
+ u32 rsvd18[1]; /* DWORDS 95 to 95 */
+ u32 rsvd19[1]; /* DWORDS 96 to 96 */
+ u32 rsvd20[1]; /* DWORDS 97 to 97 */
+ u32 rsvd21[1]; /* DWORDS 98 to 98 */
+ u32 rsvd22[1]; /* DWORDS 99 to 99 */
+ u32 rsvd23[1]; /* DWORDS 100 to 100 */
+ u32 rsvd24[1]; /* DWORDS 101 to 101 */
+ u32 rsvd25[1]; /* DWORDS 102 to 102 */
+ u32 rsvd26[1]; /* DWORDS 103 to 103 */
+ u32 rsvd27[1]; /* DWORDS 104 to 104 */
+ u32 rsvd28[3]; /* DWORDS 105 to 107 */
+ u32 rsvd29[1]; /* DWORDS 108 to 108 */
+ u32 rsvd30[1]; /* DWORDS 109 to 109 */
+ u32 rsvd31[1]; /* DWORDS 110 to 110 */
+ u32 rsvd32[1]; /* DWORDS 111 to 111 */
+ u32 rsvd33[1]; /* DWORDS 112 to 112 */
+ u32 rsvd34[3]; /* DWORDS 113 to 115 */
+ u32 rsvd35[1]; /* DWORDS 116 to 116 */
+ u32 rsvd36[1]; /* DWORDS 117 to 117 */
+ u32 rsvd37[1]; /* DWORDS 118 to 118 */
+ u32 rsvd38[1]; /* DWORDS 119 to 119 */
+ u32 rsvd39[1]; /* DWORDS 120 to 120 */
+ u32 rsvd40[1]; /* DWORDS 121 to 121 */
+ u32 rsvd41[134]; /* DWORDS 122 to 255 */
+} SG_PACK MPU_CSRMAP, *PMPU_CSRMAP;
+
+#else
+ /* Provide control parameters for the Managment Processor Unit. */
+typedef struct _MPU_CSRMAP {
+ EP_CSRMAP ep;
+ u32 rsvd0[4]; /* DWORDS 64 to 67 */
+ u32 rsvd1[1]; /* DWORDS 68 to 68 */
+ u32 rsvd2[6]; /* DWORDS 69 to 74 */
+ u32 rsvd3[6]; /* DWORDS 75 to 80 */
+ u32 rsvd4[1]; /* DWORDS 81 to 81 */
+ u32 rsvd5[1]; /* DWORDS 82 to 82 */
+ u32 rsvd6[1]; /* DWORDS 83 to 83 */
+ u32 rsvd7[1]; /* DWORDS 84 to 84 */
+ u32 rsvd8[1]; /* DWORDS 85 to 85 */
+ u32 rsvd9[1]; /* DWORDS 86 to 86 */
+ u32 rsvd10[1]; /* DWORDS 87 to 87 */
+ u32 rsvd11[1]; /* DWORDS 88 to 88 */
+ u32 rsvd12[1]; /* DWORDS 89 to 89 */
+ u32 rsvd13[1]; /* DWORDS 90 to 90 */
+ u32 rsvd14[1]; /* DWORDS 91 to 91 */
+ u32 rsvd15[1]; /* DWORDS 92 to 92 */
+ u32 rsvd16[1]; /* DWORDS 93 to 93 */
+ u32 rsvd17[1]; /* DWORDS 94 to 94 */
+ u32 rsvd18[1]; /* DWORDS 95 to 95 */
+ u32 rsvd19[1]; /* DWORDS 96 to 96 */
+ u32 rsvd20[1]; /* DWORDS 97 to 97 */
+ u32 rsvd21[1]; /* DWORDS 98 to 98 */
+ u32 rsvd22[1]; /* DWORDS 99 to 99 */
+ u32 rsvd23[1]; /* DWORDS 100 to 100 */
+ u32 rsvd24[1]; /* DWORDS 101 to 101 */
+ u32 rsvd25[1]; /* DWORDS 102 to 102 */
+ u32 rsvd26[1]; /* DWORDS 103 to 103 */
+ u32 rsvd27[1]; /* DWORDS 104 to 104 */
+ u32 rsvd28[3]; /* DWORDS 105 to 107 */
+ u32 rsvd29[1]; /* DWORDS 108 to 108 */
+ u32 rsvd30[1]; /* DWORDS 109 to 109 */
+ u32 rsvd31[1]; /* DWORDS 110 to 110 */
+ u32 rsvd32[1]; /* DWORDS 111 to 111 */
+ u32 rsvd33[1]; /* DWORDS 112 to 112 */
+ u32 rsvd34[3]; /* DWORDS 113 to 115 */
+ u32 rsvd35[1]; /* DWORDS 116 to 116 */
+ u32 rsvd36[1]; /* DWORDS 117 to 117 */
+ u32 rsvd37[1]; /* DWORDS 118 to 118 */
+ u32 rsvd38[1]; /* DWORDS 119 to 119 */
+ u32 rsvd39[1]; /* DWORDS 120 to 120 */
+ u32 rsvd40[1]; /* DWORDS 121 to 121 */
+ u32 rsvd41[134]; /* DWORDS 122 to 255 */
+} SG_PACK MPU_CSRMAP, *PMPU_CSRMAP;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __mpu_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/asyncmesg_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/asyncmesg_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/asyncmesg_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/asyncmesg_bmap.h 2008-02-14 15:23:07.831202240 +0530
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __asyncmesg_bmap_h__
+#define __asyncmesg_bmap_h__
+#include "setypes.h"
+#include "ioctl_common_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+/*
+ * The last 4 bytes of the async events have this common format. It
+ * allows the driver to distinguish MCC_CQ_ENTRY structs from asynchronous
+ * events. Both arrive on the same completion queue. This structure
+ * also contains the common fields used to decode the async event.
+ *
+ */
+typedef struct _ASYNC_EVENT_TRAILER {
+ u32 rsvd0:8; /* DWORD 0 */
+ u32 event_code:8; /* DWORD 0 */
+ u32 event_type:8; /* DWORD 0 */
+ u32 rsvd1:6; /* DWORD 0 */
+ u32 async_event:1; /* DWORD 0 */
+ u32 valid:1; /* DWORD 0 */
+} SG_PACK ASYNC_EVENT_TRAILER, *PASYNC_EVENT_TRAILER;
+
+/*
+ * Note Applicable in Initiator, Target and NIC modes. A link state
+ * async event is seen by all device drivers as soon they create an
+ * MCC ring. Thereafter, anytime the link status changes the drivers
+ * will receive a link state async event. Notifications continue to
+ * be sent until a driver destroys its MCC ring. A link down event is
+ * reported when either port loses link. A link up event is reported
+ * when either port regains link. When BE's failover mechanism is enabled,
+ * a link down on the active port causes traffic to be diverted to the
+ * standby port by the BE's RM firmware (assuming the standby port has
+ * link). In this case, the standy port assumes the active status. Note:
+ * when link is restored on the failed port, traffic continues on the
+ * currently active port. The ARM firmware does not attempt to 'fail
+ * back' traffic to the restored port.
+ */
+typedef struct _ASYNC_EVENT_LINK_STATE {
+ u8 port0_link_status;
+ u8 port1_link_status;
+ u8 active_port;
+ u8 rsvd0;
+ u8 port0_duplex;
+ u8 port0_speed;
+ u8 port1_duplex;
+ u8 port1_speed;
+ u8 port0_fault;
+ u8 port1_fault;
+ u8 rsvd1[2];
+ ASYNC_EVENT_TRAILER trailer;
+} SG_PACK ASYNC_EVENT_LINK_STATE, *PASYNC_EVENT_LINK_STATE;
+
+/*
+ * The (Initiator) firmware has discovered new Targets through the iSCSI
+ * disovery services. Note Applicable in Initiator mode only.
+ */
+typedef struct _ASYNC_EVENT_NEW_ISCSI_TARGET_DISCOVERED {
+ u32 session_handle;
+ u32 rsvd0[2]; /* DWORDS 1 to 2 */
+ ASYNC_EVENT_TRAILER trailer;
+} SG_PACK ASYNC_EVENT_NEW_ISCSI_TARGET_DISCOVERED,
+ *PASYNC_EVENT_NEW_ISCSI_TARGET_DISCOVERED;
+
+/*
+ * The (Initiator) firmware has established a new iSCSI connection with
+ * a target. The driver can use the session and connection handles
+ * to offload this connection. Note Applicable in Initiator mode only.
+ *
+ */
+typedef struct _ASYNC_EVENT_NEW_ISCSI_CONNECTION_ESTABLISHED {
+ u16 connection_handle;
+ u16 rsvd0;
+ u32 session_handle;
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ ASYNC_EVENT_TRAILER trailer;
+} SG_PACK ASYNC_EVENT_NEW_ISCSI_CONNECTION_ESTABLISHED,
+ *PASYNC_EVENT_NEW_ISCSI_CONNECTION_ESTABLISHED;
+
+/*
+ * The (Initiator) firmware has established a new TCP connection for
+ * a Target which was configured to use multiple connections-per-session.
+ * The driver can use the session and connection IDs to issue a call
+ * to IOCTL_ISCSI_INI_DRIVER_REOPEN_A_SESSION. Note Applicable in Initiator
+ * mode only.
+ */
+typedef struct _ASYNC_EVENT_NEW_TCP_CONNECTION_ESTABLISHED {
+ u16 connection_handle;
+ u16 rsvd0;
+ u32 session_handle;
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ ASYNC_EVENT_TRAILER trailer;
+} SG_PACK ASYNC_EVENT_NEW_TCP_CONNECTION_ESTABLISHED,
+ *PASYNC_EVENT_NEW_TCP_CONNECTION_ESTABLISHED;
+
+/*
+ * A new TCP connection has been accepted on the listen port. The Target
+ * driver is expected to issue IOCTL_ISCSI_TGT_GET_CONNECTION_INFO to
+ * get the source/destination IP Address and port numbers for this connection.
+ * Note Applicable in Target mode only.
+ */
+typedef struct _ASYNC_EVENT_NEW_TCP_CONNECTION_ACCEPTED {
+ u32 connection_handle;
+ u32 rsvd0[2]; /* DWORDS 1 to 2 */
+ ASYNC_EVENT_TRAILER trailer;
+} SG_PACK ASYNC_EVENT_NEW_TCP_CONNECTION_ACCEPTED,
+ *PASYNC_EVENT_NEW_TCP_CONNECTION_ACCEPTED;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __asyncmesg_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_common_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_common_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_common_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_common_bmap.h 2008-02-14 15:23:07.832202088 +0530
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __be_common_bmap_h__
+#define __be_common_bmap_h__
+#include "setypes.h"
+#include "pcicfg_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Physical Address. */
+typedef struct _PHYS_ADDR {
+ union {
+ struct {
+ u32 lo; /* DWORD 0 */
+ u32 hi; /* DWORD 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PHYS_ADDR, *PPHYS_ADDR;
+
+SG_C_ASSERT(__sizeof__PHYS_ADDR, sizeof(PHYS_ADDR) == 8);
+
+#else
+ /* Physical Address. */
+typedef struct _PHYS_ADDR {
+ union {
+ struct {
+ u32 lo; /* DWORD 0 */
+ u32 hi; /* DWORD 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PHYS_ADDR, *PPHYS_ADDR;
+
+SG_C_ASSERT(__sizeof__PHYS_ADDR, sizeof(PHYS_ADDR) == 8);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Virtual Address. */
+typedef struct _VIRT_ADDR {
+ union {
+ struct {
+ u32 lo; /* DWORD 0 */
+ u32 hi; /* DWORD 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK VIRT_ADDR, *PVIRT_ADDR;
+
+SG_C_ASSERT(__sizeof__VIRT_ADDR, sizeof(VIRT_ADDR) == 8);
+
+#else
+ /* Virtual Address. */
+typedef struct _VIRT_ADDR {
+ union {
+ struct {
+ u32 lo; /* DWORD 0 */
+ u32 hi; /* DWORD 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK VIRT_ADDR, *PVIRT_ADDR;
+
+SG_C_ASSERT(__sizeof__VIRT_ADDR, sizeof(VIRT_ADDR) == 8);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Scatter gather element. */
+typedef struct _SGE {
+ union {
+ struct {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+ u32 rsvd0[1]; /* DWORDS 2 to 2 */
+ u32 rsvd1:16; /* DWORD 3 */
+ u32 len:16; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK SGE, *PSGE;
+
+SG_C_ASSERT(__sizeof__SGE, sizeof(SGE) == 16);
+
+#else
+ /* Scatter gather element. */
+typedef struct _SGE {
+ union {
+ struct {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+ u32 rsvd0[1]; /* DWORDS 2 to 2 */
+ u32 len:16; /* DWORD 3 */
+ u32 rsvd1:16; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK SGE, *PSGE;
+
+SG_C_ASSERT(__sizeof__SGE, sizeof(SGE) == 16);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __be_common_bmap_h__ */
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
intended recipient of this message, please immediately advise the sender by reply email message and
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^ permalink raw reply
* [PATHCH 13/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:55 UTC (permalink / raw)
To: netdev
F/W header files.
------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h 2008-02-14 15:23:07.833201936 +0530
@@ -0,0 +1,1398 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_common_bmap_h__
+#define __ioctl_common_bmap_h__
+#include "setypes.h"
+#include "ioctl_types_bmap.h"
+#include "ioctl_hdr_bmap.h"
+#include "host_struct_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+typedef struct _BE_LINK_STATUS {
+ u8 mac0_duplex;
+ u8 mac0_speed;
+ u8 mac1_duplex;
+ u8 mac1_speed;
+ u8 mgmt_mac_duplex;
+ u8 mgmt_mac_speed;
+ u8 active_port;
+ u8 rsvd0;
+ u8 mac0_fault;
+ u8 mac1_fault;
+ u16 rsvd1;
+} SG_PACK BE_LINK_STATUS, *PBE_LINK_STATUS;
+
+typedef struct _IOCTL_COMMON_ANON_170_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_170_REQUEST, *PIOCTL_COMMON_ANON_170_REQUEST;
+
+typedef union _LINK_STATUS_QUERY_PARAMS {
+ BE_LINK_STATUS response;
+ IOCTL_COMMON_ANON_170_REQUEST request;
+} SG_PACK LINK_STATUS_QUERY_PARAMS, *PLINK_STATUS_QUERY_PARAMS;
+
+/*
+ * Queries the the link status for all ports. The valid values below
+ * DO NOT indicate that a particular duplex or speed is supported by
+ * BladeEngine. These enumerations simply list all possible duplexes
+ * and speeds for any port. Consult BladeEngine product documentation
+ * for the supported parameters.
+ */
+typedef struct _IOCTL_COMMON_NTWK_LINK_STATUS_QUERY {
+ IOCTL_HEADER header;
+ LINK_STATUS_QUERY_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_LINK_STATUS_QUERY,
+ *PIOCTL_COMMON_NTWK_LINK_STATUS_QUERY;
+
+typedef struct _IOCTL_COMMON_ANON_171_REQUEST {
+ u8 type;
+ u8 port;
+ u8 mac1;
+ u8 permanent;
+} SG_PACK IOCTL_COMMON_ANON_171_REQUEST, *PIOCTL_COMMON_ANON_171_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_172_RESPONSE {
+ MAC_ADDRESS_FORMAT mac;
+} SG_PACK IOCTL_COMMON_ANON_172_RESPONSE, *PIOCTL_COMMON_ANON_172_RESPONSE;
+
+typedef union _NTWK_MAC_QUERY_PARAMS {
+ IOCTL_COMMON_ANON_171_REQUEST request;
+ IOCTL_COMMON_ANON_172_RESPONSE response;
+} SG_PACK NTWK_MAC_QUERY_PARAMS, *PNTWK_MAC_QUERY_PARAMS;
+
+/* Queries one MAC address. */
+typedef struct _IOCTL_COMMON_NTWK_MAC_QUERY {
+ IOCTL_HEADER header;
+ NTWK_MAC_QUERY_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MAC_QUERY, *PIOCTL_COMMON_NTWK_MAC_QUERY;
+
+typedef struct _MAC_SET_PARAMS_IN {
+ u8 type;
+ u8 port;
+ u8 mac1;
+ u8 invalidate;
+ MAC_ADDRESS_FORMAT mac;
+} SG_PACK MAC_SET_PARAMS_IN, *PMAC_SET_PARAMS_IN;
+
+typedef struct _MAC_SET_PARAMS_OUT {
+ u32 rsvd0;
+} SG_PACK MAC_SET_PARAMS_OUT, *PMAC_SET_PARAMS_OUT;
+
+typedef union _MAC_SET_PARAMS {
+ MAC_SET_PARAMS_IN request;
+ MAC_SET_PARAMS_OUT response;
+} SG_PACK MAC_SET_PARAMS, *PMAC_SET_PARAMS;
+
+/* Sets a MAC address. */
+typedef struct _IOCTL_COMMON_NTWK_MAC_SET {
+ IOCTL_HEADER header;
+ MAC_SET_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MAC_SET, *PIOCTL_COMMON_NTWK_MAC_SET;
+
+/* MAC address list. */
+typedef struct _NTWK_MULTICAST_MAC_LIST {
+ u8 byte[6];
+} SG_PACK NTWK_MULTICAST_MAC_LIST, *PNTWK_MULTICAST_MAC_LIST;
+
+typedef struct _IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD {
+ u16 num_mac;
+ u8 promiscuous;
+ u8 rsvd0;
+ NTWK_MULTICAST_MAC_LIST mac[32];
+} SG_PACK IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD,
+ *PIOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD;
+
+typedef struct _IOCTL_COMMON_ANON_174_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_174_RESPONSE, *PIOCTL_COMMON_ANON_174_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_173_PARAMS {
+ IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD request;
+ IOCTL_COMMON_ANON_174_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_173_PARAMS, *PIOCTL_COMMON_ANON_173_PARAMS;
+
+/*
+ * Sets multicast address hash. The MPU will merge the MAC address lists
+ * from all clients, including the networking and storage functions.
+ * This ioctl may fail if the final merged list of MAC addresses exceeds
+ * 32 entries.
+ */
+typedef struct _IOCTL_COMMON_NTWK_MULTICAST_SET {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_173_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MULTICAST_SET,
+ *PIOCTL_COMMON_NTWK_MULTICAST_SET;
+
+typedef struct _IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD {
+ u16 num_vlan;
+ u8 promiscuous;
+ u8 rsvd0;
+ u16 vlan_tag[32];
+} SG_PACK IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD,
+ *PIOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD;
+
+typedef struct _IOCTL_COMMON_ANON_176_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_176_RESPONSE, *PIOCTL_COMMON_ANON_176_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_175_PARAMS {
+ IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD request;
+ IOCTL_COMMON_ANON_176_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_175_PARAMS, *PIOCTL_COMMON_ANON_175_PARAMS;
+
+/*
+ * Sets VLAN tag filter. The MPU will merge the VLAN tag list from all
+ * clients, including the networking and storage functions. This ioctl
+ * may fail if the final vlan_tag array (from all functions) is longer
+ * than 32 entries.
+ */
+typedef struct _IOCTL_COMMON_NTWK_VLAN_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_175_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_VLAN_CONFIG, *PIOCTL_COMMON_NTWK_VLAN_CONFIG;
+
+typedef struct _IOCTL_COMMON_ANON_178_REQUEST {
+ u16 num_pages;
+ u16 type;
+ PHYS_ADDR scratch_pa;
+ VIRT_ADDR sratch_va;
+ VIRT_ADDR pages_va;
+ PHYS_ADDR pages[16];
+} SG_PACK IOCTL_COMMON_ANON_178_REQUEST, *PIOCTL_COMMON_ANON_178_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_179_RESPONSE {
+ u32 num_used;
+} SG_PACK IOCTL_COMMON_ANON_179_RESPONSE, *PIOCTL_COMMON_ANON_179_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_177_PARAMS {
+ IOCTL_COMMON_ANON_178_REQUEST request;
+ IOCTL_COMMON_ANON_179_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_177_PARAMS, *PIOCTL_COMMON_ANON_177_PARAMS;
+
+/*
+ * Posts template headers buffers. These should be posted before any
+ * connections are offloaded. Each buffer holds 32 template headers
+ * at 128 bytes each. This may be issued multiple times to post the
+ * template header buffers in smaller pieces. This allows the driver
+ * to delay allocating template header buffers until the connections
+ * are actually used. Only protection domain 0 may post template header
+ * buffers.
+ */
+typedef struct _IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_177_PARAMS params;
+} SG_PACK IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
+ *PIOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS;
+
+typedef struct _IOCTL_COMMON_ANON_181_REQUEST {
+ u16 type;
+ u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_181_REQUEST, *PIOCTL_COMMON_ANON_181_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_182_RESPONSE {
+ u32 num_removed;
+} SG_PACK IOCTL_COMMON_ANON_182_RESPONSE, *PIOCTL_COMMON_ANON_182_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_180_PARAMS {
+ IOCTL_COMMON_ANON_181_REQUEST request;
+ IOCTL_COMMON_ANON_182_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_180_PARAMS, *PIOCTL_COMMON_ANON_180_PARAMS;
+
+/*
+ * Frees all template header buffers for the given type. Only protection
+ * domain 0 may issue this request. The IOCTL may fail if any rings
+ * which use these template headers are still in use.
+ */
+typedef struct _IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_180_PARAMS params;
+} SG_PACK IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
+ *PIOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS;
+
+typedef struct _IOCTL_COMMON_ANON_184_REQUEST {
+ u16 num;
+ u8 shared;
+ u8 rsvd0;
+ VIRT_ADDR va;
+ PHYS_ADDR page_tables[26];
+} SG_PACK IOCTL_COMMON_ANON_184_REQUEST, *PIOCTL_COMMON_ANON_184_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_185_RESPONSE {
+ u16 num_added;
+ u16 num_total;
+ u16 num_free;
+ u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_185_RESPONSE, *PIOCTL_COMMON_ANON_185_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_183_PARAMS {
+ IOCTL_COMMON_ANON_184_REQUEST request;
+ IOCTL_COMMON_ANON_185_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_183_PARAMS, *PIOCTL_COMMON_ANON_183_PARAMS;
+
+/*
+ * Posts page tables for the UT. This command may be issued multiple
+ * times to add page tables to the chip.
+ */
+typedef struct _IOCTL_COMMON_ADD_PAGE_TABLES {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_183_PARAMS params;
+} SG_PACK IOCTL_COMMON_ADD_PAGE_TABLES, *PIOCTL_COMMON_ADD_PAGE_TABLES;
+
+typedef struct _IOCTL_COMMON_ANON_187_REQUEST {
+ u16 num;
+ u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_187_REQUEST, *PIOCTL_COMMON_ANON_187_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_188_RESPONSE {
+ u16 actual_num;
+ u16 total_num;
+ PHYS_ADDR page_tables[27];
+} SG_PACK IOCTL_COMMON_ANON_188_RESPONSE, *PIOCTL_COMMON_ANON_188_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_186_PARAMS {
+ IOCTL_COMMON_ANON_187_REQUEST request;
+ IOCTL_COMMON_ANON_188_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_186_PARAMS, *PIOCTL_COMMON_ANON_186_PARAMS;
+
+/*
+ * Removes free page tables from the chip. Only page tables that are
+ * unused may be removed. Page tables may not be removed in the same
+ * order as they are posted. This ioctl returns a list of physical
+ * addresses for the page tables that were removed.
+ */
+typedef struct _IOCTL_COMMON_REMOVE_PAGE_TABLES {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_186_PARAMS params;
+} SG_PACK IOCTL_COMMON_REMOVE_PAGE_TABLES,
+ *PIOCTL_COMMON_REMOVE_PAGE_TABLES;
+
+typedef struct _RING_DESTROY_REQUEST {
+ u16 ring_type;
+ u16 id;
+ u8 bypass_flush;
+ u8 rsvd0;
+ u16 rsvd1;
+} SG_PACK RING_DESTROY_REQUEST, *PRING_DESTROY_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_190_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_190_RESPONSE, *PIOCTL_COMMON_ANON_190_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_189_PARAMS {
+ RING_DESTROY_REQUEST request;
+ IOCTL_COMMON_ANON_190_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_189_PARAMS, *PIOCTL_COMMON_ANON_189_PARAMS;
+/*
+ * IOCTL for destroying any ring. The connection(s) using the ring should
+ * be quiesced before destroying the ring.
+ */
+typedef struct _IOCTL_COMMON_RING_DESTROY {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_189_PARAMS params;
+} SG_PACK IOCTL_COMMON_RING_DESTROY, *PIOCTL_COMMON_RING_DESTROY;
+
+typedef struct _IOCTL_COMMON_ANON_192_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ CQ_CONTEXT context;
+ PHYS_ADDR pages[4];
+} SG_PACK IOCTL_COMMON_ANON_192_REQUEST, *PIOCTL_COMMON_ANON_192_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_193_RESPONSE {
+ u16 cq_id;
+} SG_PACK IOCTL_COMMON_ANON_193_RESPONSE, *PIOCTL_COMMON_ANON_193_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_191_PARAMS {
+ IOCTL_COMMON_ANON_192_REQUEST request;
+ IOCTL_COMMON_ANON_193_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_191_PARAMS, *PIOCTL_COMMON_ANON_191_PARAMS;
+
+/*
+ * IOCTL for creating a completion queue. A Completion Queue must span
+ * at least 1 page and at most 4 pages. Each completion queue entry
+ * is 16 bytes regardless of CQ entry format. Thus the ring must be
+ * at least 256 entries deep (corresponding to 1 page) and can be at
+ * most 1024 entries deep (corresponding to 4 pages). The number of
+ * pages posted must contain the CQ ring size as encoded in the context.
+ *
+ */
+typedef struct _IOCTL_COMMON_CQ_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_191_PARAMS params;
+} SG_PACK IOCTL_COMMON_CQ_CREATE, *PIOCTL_COMMON_CQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_195_REQUEST {
+ u16 num_pages;
+ u16 new_cq_len;
+ u32 cq_threshold;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_195_REQUEST, *PIOCTL_COMMON_ANON_195_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_196_RESPONSE {
+ u16 pidx_old;
+} SG_PACK IOCTL_COMMON_ANON_196_RESPONSE, *PIOCTL_COMMON_ANON_196_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_194_PARAMS {
+ IOCTL_COMMON_ANON_195_REQUEST request;
+ IOCTL_COMMON_ANON_196_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_194_PARAMS, *PIOCTL_COMMON_ANON_194_PARAMS;
+
+/*
+ * IOCTL to modify select attributes of a completion queue without needing
+ * to destroy and create a new one.
+ */
+typedef struct _IOCTL_COMMON_CQ_MODIFY {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_194_PARAMS params;
+} SG_PACK IOCTL_COMMON_CQ_MODIFY, *PIOCTL_COMMON_CQ_MODIFY;
+
+typedef struct _IOCTL_COMMON_ANON_198_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ EQ_CONTEXT context;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_198_REQUEST, *PIOCTL_COMMON_ANON_198_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_199_RESPONSE {
+ u16 eq_id;
+} SG_PACK IOCTL_COMMON_ANON_199_RESPONSE, *PIOCTL_COMMON_ANON_199_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_197_PARAMS {
+ IOCTL_COMMON_ANON_198_REQUEST request;
+ IOCTL_COMMON_ANON_199_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_197_PARAMS, *PIOCTL_COMMON_ANON_197_PARAMS;
+
+/*
+ * IOCTL for creating a event queue. An Event Queue must span at least
+ * 1 page and at most 8 pages. The number of pages posted must contain
+ * the EQ ring. The ring is defined by the size of the EQ entries (encoded
+ * in the context) and the number of EQ entries (also encoded in the
+ * context).
+ */
+typedef struct _IOCTL_COMMON_EQ_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_197_PARAMS params;
+} SG_PACK IOCTL_COMMON_EQ_CREATE, *PIOCTL_COMMON_EQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_201_REQUEST {
+ u16 cq_id;
+ u16 bcmc_cq_id;
+ u16 num_pages;
+ u16 rsvd0;
+ PHYS_ADDR pages[2];
+} SG_PACK IOCTL_COMMON_ANON_201_REQUEST, *PIOCTL_COMMON_ANON_201_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_202_RESPONSE {
+ u16 id;
+} SG_PACK IOCTL_COMMON_ANON_202_RESPONSE, *PIOCTL_COMMON_ANON_202_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_200_PARAMS {
+ IOCTL_COMMON_ANON_201_REQUEST request;
+ IOCTL_COMMON_ANON_202_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_200_PARAMS, *PIOCTL_COMMON_ANON_200_PARAMS;
+
+/*
+ * IOCTL for creating Ethernet receive ring. An ERX ring contains ETH_RX_D
+ * entries (8 bytes each). An ERX ring must be 1024 entries deep
+ * (corresponding to 2 pages).
+ */
+typedef struct _IOCTL_COMMON_ETH_RX_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_200_PARAMS params;
+} SG_PACK IOCTL_COMMON_ETH_RX_CREATE, *PIOCTL_COMMON_ETH_RX_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_204_REQUEST {
+ u16 num_pages;
+ u8 ulp_num;
+ u8 type;
+ ETX_CONTEXT context;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_204_REQUEST, *PIOCTL_COMMON_ANON_204_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_205_RESPONSE {
+ u16 cid;
+ u8 ulp_num;
+ u8 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_205_RESPONSE, *PIOCTL_COMMON_ANON_205_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_203_PARAMS {
+ IOCTL_COMMON_ANON_204_REQUEST request;
+ IOCTL_COMMON_ANON_205_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_203_PARAMS, *PIOCTL_COMMON_ANON_203_PARAMS;
+
+/*
+ * IOCTL for creating an Ethernet transmit ring. An ETX ring contains
+ * ETH_WRB entries (16 bytes each). An ETX ring must be at least 256
+ * entries deep (corresponding to 1 page) and at most 2k entries deep
+ * (corresponding to 8 pages).
+ */
+typedef struct _IOCTL_COMMON_ETH_TX_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_203_PARAMS params;
+} SG_PACK IOCTL_COMMON_ETH_TX_CREATE, *PIOCTL_COMMON_ETH_TX_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_207_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ ISCSI_DEFAULT_PDU_CONTEXT context;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_207_REQUEST, *PIOCTL_COMMON_ANON_207_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_208_RESPONSE {
+ u16 id;
+} SG_PACK IOCTL_COMMON_ANON_208_RESPONSE, *PIOCTL_COMMON_ANON_208_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_206_PARAMS {
+ IOCTL_COMMON_ANON_207_REQUEST request;
+ IOCTL_COMMON_ANON_208_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_206_PARAMS, *PIOCTL_COMMON_ANON_206_PARAMS;
+
+/*
+ * IOCTL for creating iSCSI default PDU ring. Use opcode
+ * OPCODE_COMMON_ISCSI_DEFQ_CREATE.
+ * An iSCSI default PDU ring must be at least 512 entries deep (corresponding
+ * to 1 page) and at most 4k entries deep (corresponding to 8 pages).
+ *
+ */
+typedef struct _IOCTL_COMMON_ISCSI_DEFQ_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_206_PARAMS params;
+} SG_PACK IOCTL_COMMON_ISCSI_DEFQ_CREATE, *PIOCTL_COMMON_ISCSI_DEFQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_210_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_210_REQUEST, *PIOCTL_COMMON_ANON_210_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_211_RESPONSE {
+ u16 cid;
+} SG_PACK IOCTL_COMMON_ANON_211_RESPONSE, *PIOCTL_COMMON_ANON_211_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_209_PARAMS {
+ IOCTL_COMMON_ANON_210_REQUEST request;
+ IOCTL_COMMON_ANON_211_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_209_PARAMS, *PIOCTL_COMMON_ANON_209_PARAMS;
+
+/*
+ * IOCTL for creating iSCSI WRB ring. An iSCSI WRB (transmit) ring must
+ * be at least 128 entries deep (corresponding to 1 page) and at most
+ * 2k entries deep (corresponding to 4 pages). When the connection
+ * is offloaded, the encoded ring size in the context must result in
+ * a ring fitting within the number of pages posted with this IOCTL.
+ *
+ */
+typedef struct _IOCTL_COMMON_ISCSI_WRBQ_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_209_PARAMS params;
+} SG_PACK IOCTL_COMMON_ISCSI_WRBQ_CREATE, *PIOCTL_COMMON_ISCSI_WRBQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_213_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ u32 rsvd1[16]; /* DWORDS 1 to 16 */
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_213_REQUEST, *PIOCTL_COMMON_ANON_213_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_214_RESPONSE {
+ u16 id;
+} SG_PACK IOCTL_COMMON_ANON_214_RESPONSE, *PIOCTL_COMMON_ANON_214_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_212_PARAMS {
+ IOCTL_COMMON_ANON_213_REQUEST request;
+ IOCTL_COMMON_ANON_214_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_212_PARAMS, *PIOCTL_COMMON_ANON_212_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_216_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_216_REQUEST, *PIOCTL_COMMON_ANON_216_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_217_RESPONSE {
+ u16 cid;
+} SG_PACK IOCTL_COMMON_ANON_217_RESPONSE, *PIOCTL_COMMON_ANON_217_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_215_PARAMS {
+ IOCTL_COMMON_ANON_216_REQUEST request;
+ IOCTL_COMMON_ANON_217_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_215_PARAMS, *PIOCTL_COMMON_ANON_215_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_222_REQUEST {
+ u16 num_pages;
+ u16 rsvd0;
+ MCC_RING_CONTEXT context;
+ PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_222_REQUEST, *PIOCTL_COMMON_ANON_222_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_223_RESPONSE {
+ u16 id;
+} SG_PACK IOCTL_COMMON_ANON_223_RESPONSE, *PIOCTL_COMMON_ANON_223_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_221_PARAMS {
+ IOCTL_COMMON_ANON_222_REQUEST request;
+ IOCTL_COMMON_ANON_223_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_221_PARAMS, *PIOCTL_COMMON_ANON_221_PARAMS;
+
+/*
+ * IOCTL for creating the MCC ring. An MCC ring must be at least 16
+ * entries deep (corresponding to 1 page) and at most 128 entries deep
+ * (corresponding to 8 pages).
+ */
+typedef struct _IOCTL_COMMON_MCC_CREATE {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_221_PARAMS params;
+} SG_PACK IOCTL_COMMON_MCC_CREATE, *PIOCTL_COMMON_MCC_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_225_REQUEST {
+ PHYS_ADDR page;
+} SG_PACK IOCTL_COMMON_ANON_225_REQUEST, *PIOCTL_COMMON_ANON_225_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_226_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_226_RESPONSE, *PIOCTL_COMMON_ANON_226_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_224_PARAMS {
+ IOCTL_COMMON_ANON_225_REQUEST request;
+ IOCTL_COMMON_ANON_226_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_224_PARAMS, *PIOCTL_COMMON_ANON_224_PARAMS;
+
+/*
+ * Posts a physical address pointing to a single byte of zero data that
+ * may be DMA'd.
+ */
+typedef struct _IOCTL_COMMON_POST_ZERO_BUFFER {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_224_PARAMS params;
+} SG_PACK IOCTL_COMMON_POST_ZERO_BUFFER, *PIOCTL_COMMON_POST_ZERO_BUFFER;
+
+typedef struct _IOCTL_COMMON_ANON_228_REQUEST {
+ u8 free_jell;
+ u8 ddr;
+ u8 done;
+ u8 rsvd0;
+ u16 page_offset;
+ u16 num_pages;
+ PHYS_ADDR pages[26];
+} SG_PACK IOCTL_COMMON_ANON_228_REQUEST, *PIOCTL_COMMON_ANON_228_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_229_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_229_RESPONSE, *PIOCTL_COMMON_ANON_229_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_227_PARAMS {
+ IOCTL_COMMON_ANON_228_REQUEST request;
+ IOCTL_COMMON_ANON_229_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_227_PARAMS, *PIOCTL_COMMON_ANON_227_PARAMS;
+
+/*
+ * Configures the JELL -- the journal entry linked list required for
+ * any TCP offload. This may also free a previously configured JELL.
+ *
+ */
+typedef struct _IOCTL_COMMON_JELL_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_227_PARAMS params;
+} SG_PACK IOCTL_COMMON_JELL_CONFIG, *PIOCTL_COMMON_JELL_CONFIG;
+
+typedef struct _GET_QOS_IN {
+ u32 qos_params_rsvd;
+} SG_PACK GET_QOS_IN, *PGET_QOS_IN;
+
+typedef struct _GET_QOS_OUT {
+ u32 max_bits_per_second_NIC;
+ u32 max_packets_per_second_NIC;
+ u32 max_ios_per_second_iSCSI;
+ u32 max_bytes_per_second_iSCSI;
+ u16 domain_VLAN_tag;
+ u16 fabric_domain_ID;
+ u32 qos_params_oem[4];
+} SG_PACK GET_QOS_OUT, *PGET_QOS_OUT;
+
+typedef union _GET_QOS_PARAMS {
+ GET_QOS_IN request;
+ GET_QOS_OUT response;
+} SG_PACK GET_QOS_PARAMS, *PGET_QOS_PARAMS;
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs. */
+typedef struct _IOCTL_COMMON_GET_QOS {
+ IOCTL_HEADER header;
+ GET_QOS_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_QOS, *PIOCTL_COMMON_GET_QOS;
+
+typedef struct _SET_QOS_IN {
+ u32 valid_flags;
+ u32 max_bits_per_second_NIC;
+ u32 max_packets_per_second_NIC;
+ u32 max_ios_per_second_iSCSI;
+ u32 max_bytes_per_second_iSCSI;
+ u16 domain_VLAN_tag;
+ u16 fabric_domain_ID;
+ u32 qos_params_oem[4];
+} SG_PACK SET_QOS_IN, *PSET_QOS_IN;
+
+typedef struct _SET_QOS_OUT {
+ u32 qos_params_rsvd;
+} SG_PACK SET_QOS_OUT, *PSET_QOS_OUT;
+
+typedef union _SET_QOS_PARAMS {
+ SET_QOS_IN request;
+ SET_QOS_OUT response;
+} SG_PACK SET_QOS_PARAMS, *PSET_QOS_PARAMS;
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs. */
+typedef struct _IOCTL_COMMON_SET_QOS {
+ IOCTL_HEADER header;
+ SET_QOS_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_QOS, *PIOCTL_COMMON_SET_QOS;
+
+typedef struct _SET_FRAME_SIZE_IN {
+ u32 max_tx_frame_size;
+ u32 max_rx_frame_size;
+} SG_PACK SET_FRAME_SIZE_IN, *PSET_FRAME_SIZE_IN;
+
+typedef struct _SET_FRAME_SIZE_OUT {
+ u32 chip_max_tx_frame_size;
+ u32 chip_max_rx_frame_size;
+} SG_PACK SET_FRAME_SIZE_OUT, *PSET_FRAME_SIZE_OUT;
+
+typedef union _SET_FRAME_SIZE_PARAMS {
+ SET_FRAME_SIZE_IN request;
+ SET_FRAME_SIZE_OUT response;
+} SG_PACK SET_FRAME_SIZE_PARAMS, *PSET_FRAME_SIZE_PARAMS;
+
+/* Set frame size IOCTL. Only host domain may issue this IOCTL. */
+typedef struct _IOCTL_COMMON_SET_FRAME_SIZE {
+ IOCTL_HEADER header;
+ SET_FRAME_SIZE_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_FRAME_SIZE, *PIOCTL_COMMON_SET_FRAME_SIZE;
+
+typedef struct _FORCE_FAILOVER_IN {
+ u32 move_to_port;
+ u32 failover_config;
+} SG_PACK FORCE_FAILOVER_IN, *PFORCE_FAILOVER_IN;
+
+typedef struct _IOCTL_COMMON_ANON_231_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_231_RESPONSE, *PIOCTL_COMMON_ANON_231_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_230_PARAMS {
+ FORCE_FAILOVER_IN request;
+ IOCTL_COMMON_ANON_231_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_230_PARAMS, *PIOCTL_COMMON_ANON_230_PARAMS;
+
+/*
+ * Use this IOCTL to control failover in BladeEngine. It may be used
+ * to failback to a restored port or to forcibly move traffic from
+ * one port to another. It may also be used to enable or disable the
+ * automatic failover feature. This IOCTL can only be issued by domain
+ * 0.
+ */
+typedef struct _IOCTL_COMMON_FORCE_FAILOVER {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_230_PARAMS params;
+} SG_PACK IOCTL_COMMON_FORCE_FAILOVER, *PIOCTL_COMMON_FORCE_FAILOVER;
+
+typedef struct _QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT {
+ u32 max_ioctl_buffer_size;
+} SG_PACK QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT,
+ *PQUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT;
+
+/*
+ * IOCTL_QUERY_MAX_IOCTL_BUFFER_SIZE MILI uses this IOCTL to find out
+ * the maximum buffer size that can be accepted by the host OS or the
+ * OSM. During MILI initialization, MILI should send this IOCTL to
+ * find out the maximum IOCTL buffer size allowed. For all the IOCTLs
+ * in the future, MILI should not allocate a buffer larger than this
+ * value. In Windows, the OS doesn't deliver the IOCTL request when
+ * the buffer size allocated by MILI is larger than the maximum I/O
+ * size allowed by OSM.
+ */
+typedef struct _IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE {
+ IOCTL_HEADER header;
+ QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT response;
+} SG_PACK IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE,
+ *PIOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE;
+
+typedef struct _FLASHROM_PARAMS {
+ u32 op_code;
+ u32 op_type;
+ u32 data_buffer_size;
+ u32 offset;
+ u8 data_buffer[4];
+} SG_PACK FLASHROM_PARAMS, *PFLASHROM_PARAMS;
+
+typedef struct _IOCTL_COMMON_FLASHROM {
+ IOCTL_HEADER header;
+ FLASHROM_PARAMS params;
+} SG_PACK IOCTL_COMMON_FLASHROM, *PIOCTL_COMMON_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM IOCTL_COMMON_READ_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM *PIOCTL_COMMON_READ_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM IOCTL_COMMON_WRITE_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM *PIOCTL_COMMON_WRITE_FLASHROM;
+
+typedef struct _FLASH_ROM_INFO {
+ u8 manuf_code;
+ u8 device_code;
+ u8 id[3];
+ u8 device_size;
+ u8 device_interface[2];
+ u8 buffer_size[2];
+ u8 is_block_oriented;
+ u8 num_regions[2];
+ u8 region_size[2];
+} SG_PACK FLASH_ROM_INFO, *PFLASH_ROM_INFO;
+
+typedef struct _SEEPROM_DATA {
+ u32 jmp_addr_for_ISM;
+ u8 seeprom_version[2];
+ u8 supported_modes;
+ u8 max_domains_supported;
+ u8 storage_MAC0_port0[6];
+ u8 storage_MAC1_port0[6];
+ u8 storage_MAC0_port1[6];
+ u8 storage_MAC1_port1[6];
+ u8 ntwk_MAC0_port0[6];
+ u8 ntwk_MAC1_port0[6];
+ u8 ntwk_MAC0_port1[6];
+ u8 ntwk_MAC1_port1[6];
+ u8 ntwk_MAC_VMs[186];
+ u8 mgmt_MAC[6];
+ u8 flash_ROM_type;
+ u8 flash_ROM_size;
+ FLASH_ROM_INFO flash_cfi_data;
+ u8 DDR_type;
+ u8 DDR_size;
+ u8 DDR_mode;
+ u8 xml_config;
+ u8 interface_10Gb_type;
+ u16 max_iscsi_sessions;
+ u8 rsvd0[44];
+ u8 rsvd1[4];
+ u32 emph_lev_sel_port0;
+ u32 emph_lev_sel_port1;
+ u8 xaui_vo_sel;
+ u8 xaui_state;
+ u16 rsvd2;
+ u32 xaui_eq_vector;
+ u32 hba_mtu;
+ u8 vld_mode;
+ u8 pad[171];
+ u8 ism_code[508];
+ u32 digest;
+} SG_PACK SEEPROM_DATA, *PSEEPROM_DATA;
+
+typedef struct _SEEPROM_READ_PARAMS_OUT {
+ SEEPROM_DATA seeprom_data;
+} SG_PACK SEEPROM_READ_PARAMS_OUT, *PSEEPROM_READ_PARAMS_OUT;
+
+typedef union _SEEPROM_READ_PARAMS {
+ SEEPROM_READ_PARAMS_OUT response;
+} SG_PACK SEEPROM_READ_PARAMS, *PSEEPROM_READ_PARAMS;
+
+/*
+ * Use this IOCTL to retrieve BE HBA/instance specific information
+ * - Functionality (or combinations of functions) supported (NIC/iSCSI/VM/RDMA
+ * etc.) - Manufacturer assigned MAC addresses for the various functions
+ * - Flash ROM type and size
+ */
+typedef struct _IOCTL_COMMON_SEEPROM_READ {
+ IOCTL_HEADER header;
+ SEEPROM_READ_PARAMS params;
+} SG_PACK IOCTL_COMMON_SEEPROM_READ, *PIOCTL_COMMON_SEEPROM_READ;
+
+typedef struct _BE_TCP_STATS {
+ u32 rsvd0[256]; /* DWORDS 0 to 255 */
+ u32 rsvd1[256]; /* DWORDS 256 to 511 */
+} SG_PACK BE_TCP_STATS, *PBE_TCP_STATS;
+
+typedef struct _IOCTL_COMMON_ANON_232_REQUEST {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+} SG_PACK IOCTL_COMMON_ANON_232_REQUEST, *PIOCTL_COMMON_ANON_232_REQUEST;
+
+typedef union _TCP_GET_STATISTICS_PARAMS {
+ BE_TCP_STATS response;
+ IOCTL_COMMON_ANON_232_REQUEST request;
+} SG_PACK TCP_GET_STATISTICS_PARAMS, *PTCP_GET_STATISTICS_PARAMS;
+
+typedef struct _IOCTL_COMMON_TCP_GET_STATISTICS {
+ IOCTL_HEADER header;
+ TCP_GET_STATISTICS_PARAMS params;
+} SG_PACK IOCTL_COMMON_TCP_GET_STATISTICS,
+ *PIOCTL_COMMON_TCP_GET_STATISTICS;
+
+typedef struct _IOCTL_COMMON_ANON_234_RESPONSE {
+ u32 rsvd0[32]; /* DWORDS 0 to 31 */
+} SG_PACK IOCTL_COMMON_ANON_234_RESPONSE, *PIOCTL_COMMON_ANON_234_RESPONSE;
+
+typedef struct _IOCTL_COMMON_ANON_235_REQUEST {
+ u32 cid;
+} SG_PACK IOCTL_COMMON_ANON_235_REQUEST, *PIOCTL_COMMON_ANON_235_REQUEST;
+
+typedef union _IOCTL_COMMON_ANON_233_PARAMS {
+ IOCTL_COMMON_ANON_234_RESPONSE response;
+ IOCTL_COMMON_ANON_235_REQUEST request;
+} SG_PACK IOCTL_COMMON_ANON_233_PARAMS, *PIOCTL_COMMON_ANON_233_PARAMS;
+
+/* Queries the TCP state of a given connection. */
+typedef struct _IOCTL_COMMON_TCP_STATE_QUERY {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_233_PARAMS params;
+} SG_PACK IOCTL_COMMON_TCP_STATE_QUERY, *PIOCTL_COMMON_TCP_STATE_QUERY;
+
+typedef struct _IOCTL_COMMON_ANON_237_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_237_REQUEST, *PIOCTL_COMMON_ANON_237_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_238_RESPONSE {
+ MGMT_CONTROLLER_ATTRIBUTES cntl_attributes_info;
+} SG_PACK IOCTL_COMMON_ANON_238_RESPONSE, *PIOCTL_COMMON_ANON_238_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_236_PARAMS {
+ IOCTL_COMMON_ANON_237_REQUEST request;
+ IOCTL_COMMON_ANON_238_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_236_PARAMS, *PIOCTL_COMMON_ANON_236_PARAMS;
+
+/*
+ * This ioctl queries the controller information from the Flash ROM.
+ * This is required for management applications and BIOS to display
+ * this information to the users.
+ */
+typedef struct _IOCTL_COMMON_GET_CNTL_ATTRIBUTES {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_236_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_CNTL_ATTRIBUTES,
+ *PIOCTL_COMMON_GET_CNTL_ATTRIBUTES;
+
+typedef struct _IOCTL_COMMON_ANON_240_REQUEST {
+ u64 context;
+} SG_PACK IOCTL_COMMON_ANON_240_REQUEST, *PIOCTL_COMMON_ANON_240_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_241_RESPONSE {
+ u64 context;
+} SG_PACK IOCTL_COMMON_ANON_241_RESPONSE, *PIOCTL_COMMON_ANON_241_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_239_PARAMS {
+ IOCTL_COMMON_ANON_240_REQUEST request;
+ IOCTL_COMMON_ANON_241_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_239_PARAMS, *PIOCTL_COMMON_ANON_239_PARAMS;
+
+/*
+ * This ioctl can be used by clients as a no-operation request. Typical
+ * uses for drivers are as a heartbeat mechanism, or deferred processing
+ * catalyst. The ARM will always complete this IOCTL with a good completion.
+ * The 64-bit parameter is not touched by the ARM processor.
+ */
+typedef struct _IOCTL_COMMON_NOP {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_239_PARAMS params;
+} SG_PACK IOCTL_COMMON_NOP, *PIOCTL_COMMON_NOP;
+
+typedef struct _NTWK_RX_FILTER_SETTINGS {
+ u8 promiscuous;
+ u8 ip_cksum;
+ u8 tcp_cksum;
+ u8 udp_cksum;
+ u8 pass_err;
+ u8 pass_ckerr;
+ u8 strip_crc;
+ u8 mcast_en;
+ u8 bcast_en;
+ u8 mcast_promiscuous_en;
+ u8 unicast_en;
+ u8 vlan_promiscuous;
+} SG_PACK NTWK_RX_FILTER_SETTINGS, *PNTWK_RX_FILTER_SETTINGS;
+
+typedef union _IOCTL_COMMON_ANON_242_PARAMS {
+ NTWK_RX_FILTER_SETTINGS request;
+ NTWK_RX_FILTER_SETTINGS response;
+} SG_PACK IOCTL_COMMON_ANON_242_PARAMS, *PIOCTL_COMMON_ANON_242_PARAMS;
+
+/*
+ * This IOCTL is used to modify the ethernet receive filter configuration.
+ * Only domain 0 network function drivers may issue this IOCTL. The
+ * applied configuration is returned in the response payload. Note:
+ * Some receive packet filter settings are global on BladeEngine and
+ * can affect both the storage and network function clients that the
+ * BladeEngine hardware and firmware serve. Additionaly, depending
+ * on the revision of BladeEngine, some ethernet receive filter settings
+ * are dependent on others. If a dependency exists between settings
+ * for the BladeEngine revision, and the IOCTL request settings do
+ * not meet the dependency requirement, the invalid settings will not
+ * be applied despite the IOCTL succeeding. For example: a driver may
+ * request to enable broadcast packets, but not enable multicast packets.
+ * On early revisions of BladeEngine, there may be no distinction between
+ * broadcast and multicast filters, so broadcast could not be enabled
+ * without enabling multicast. In this scenario, the IOCTL would still
+ * succeed, but the response payload would indicate the previously
+ * configured broadcast and multicast setting.
+ */
+typedef struct _IOCTL_COMMON_NTWK_RX_FILTER {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_242_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_RX_FILTER, *PIOCTL_COMMON_NTWK_RX_FILTER;
+
+typedef struct _IOCTL_COMMON_ANON_244_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_244_REQUEST, *PIOCTL_COMMON_ANON_244_REQUEST;
+
+typedef struct _IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD {
+ u8 firmware_version_string[32];
+ u8 fw_on_flash_version_string[32];
+} SG_PACK IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD,
+ *PIOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD;
+
+typedef union _IOCTL_COMMON_ANON_243_PARAMS {
+ IOCTL_COMMON_ANON_244_REQUEST request;
+ IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD response;
+} SG_PACK IOCTL_COMMON_ANON_243_PARAMS, *PIOCTL_COMMON_ANON_243_PARAMS;
+
+/* This IOCTL retrieves the firmware version. */
+typedef struct _IOCTL_COMMON_GET_FW_VERSION {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_243_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FW_VERSION, *PIOCTL_COMMON_GET_FW_VERSION;
+
+typedef struct _IOCTL_COMMON_ANON_246_REQUEST {
+ u16 tx_flow_control;
+ u16 rx_flow_control;
+} SG_PACK IOCTL_COMMON_ANON_246_REQUEST, *PIOCTL_COMMON_ANON_246_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_247_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_247_RESPONSE, *PIOCTL_COMMON_ANON_247_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_245_PARAMS {
+ IOCTL_COMMON_ANON_246_REQUEST request;
+ IOCTL_COMMON_ANON_247_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_245_PARAMS, *PIOCTL_COMMON_ANON_245_PARAMS;
+
+/*
+ * This IOCTL is used to program BladeEngine flow control behavior.
+ * Only the host networking driver is allowed to use this IOCTL.
+ */
+typedef struct _IOCTL_COMMON_SET_FLOW_CONTROL {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_245_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_FLOW_CONTROL, *PIOCTL_COMMON_SET_FLOW_CONTROL;
+
+typedef struct _IOCTL_COMMON_ANON_249_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_249_REQUEST, *PIOCTL_COMMON_ANON_249_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_250_RESPONSE {
+ u16 tx_flow_control;
+ u16 rx_flow_control;
+} SG_PACK IOCTL_COMMON_ANON_250_RESPONSE, *PIOCTL_COMMON_ANON_250_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_248_PARAMS {
+ IOCTL_COMMON_ANON_249_REQUEST request;
+ IOCTL_COMMON_ANON_250_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_248_PARAMS, *PIOCTL_COMMON_ANON_248_PARAMS;
+
+/* This IOCTL is used to read BladeEngine flow control settings. */
+typedef struct _IOCTL_COMMON_GET_FLOW_CONTROL {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_248_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FLOW_CONTROL, *PIOCTL_COMMON_GET_FLOW_CONTROL;
+
+typedef struct _BE_DRIVER_TCP_PARAMETERS {
+ u32 fin_wait2_ms;
+ u32 push_timer_ms;
+ u32 delayed_ack_ms;
+ u32 idle_ms;
+ u32 sws_prevention_ms;
+ u32 dup_ack_threshold;
+ u32 max_warning_count;
+ u32 max_rxmt_count;
+ u32 ack_frequency;
+ u32 rsvd0[2];
+} SG_PACK BE_DRIVER_TCP_PARAMETERS, *PBE_DRIVER_TCP_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_252_REQUEST {
+ u32 ulp_mask;
+ BE_DRIVER_TCP_PARAMETERS tcp_params;
+} SG_PACK IOCTL_COMMON_ANON_252_REQUEST, *PIOCTL_COMMON_ANON_252_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_253_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_253_RESPONSE, *PIOCTL_COMMON_ANON_253_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_251_PARAMS {
+ IOCTL_COMMON_ANON_252_REQUEST request;
+ IOCTL_COMMON_ANON_253_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_251_PARAMS, *PIOCTL_COMMON_ANON_251_PARAMS;
+
+/*
+ * This IOCTL sets the global TCP parameters for offloaded connections.
+ * Only host device drivers are allowed to set these.
+ */
+typedef struct _IOCTL_COMMON_SET_TCP_PARAMETERS {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_251_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_TCP_PARAMETERS,
+ *PIOCTL_COMMON_SET_TCP_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_255_REQUEST {
+ u8 clear_log;
+ u8 num_pages;
+ u16 page_offset;
+ PHYS_ADDR buffer_addr[27];
+} SG_PACK IOCTL_COMMON_ANON_255_REQUEST, *PIOCTL_COMMON_ANON_255_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_256_RESPONSE {
+ u32 log_size;
+ u32 bytes_transferred;
+} SG_PACK IOCTL_COMMON_ANON_256_RESPONSE, *PIOCTL_COMMON_ANON_256_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_254_PARAMS {
+ IOCTL_COMMON_ANON_255_REQUEST request;
+ IOCTL_COMMON_ANON_256_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_254_PARAMS, *PIOCTL_COMMON_ANON_254_PARAMS;
+
+/*
+ * This IOCTL retrieves a Fault Analaysis Tool (FAT) log. The log data
+ * can be anaylzed by BladeEngine support tools to diagnose faults.
+ * Only host domains may issue this IOCTL.
+ */
+typedef struct _IOCTL_COMMON_GET_FAT {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_254_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FAT, *PIOCTL_COMMON_GET_FAT;
+
+typedef struct _ENABLE_DISABLE_DOMAINS_PARAMS_IN {
+ u8 domain_function;
+ u8 enable_disable;
+ u16 rsvd0;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS_IN,
+ *PENABLE_DISABLE_DOMAINS_PARAMS_IN;
+
+typedef struct _ENABLE_DISABLE_DOMAINS_PARAMS_OUT {
+ u32 rsvd0;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS_OUT,
+ *PENABLE_DISABLE_DOMAINS_PARAMS_OUT;
+
+typedef union _ENABLE_DISABLE_DOMAINS_PARAMS {
+ ENABLE_DISABLE_DOMAINS_PARAMS_IN request;
+ ENABLE_DISABLE_DOMAINS_PARAMS_OUT response;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS, *PENABLE_DISABLE_DOMAINS_PARAMS;
+
+/*
+ * This IOCTL enables or disables a domain for NIC or iSCSI functionality.
+ * If a particular domain is enabled, management utilities like SMCLP
+ * expose a logicalHBA to the user allowing the QoS, iSCSI (iqn) name
+ * etc to be set for that domain. The domain number is specified in
+ * the IOCTL_HEADER. This IOCTL can only originate from domain 0. <break>
+ * This IOCTL may return one of the following status values in the response
+ * - MGMT_STATUS_SUCCESS - MGMT_STATUS_FAILED with additional status
+ * set to MGMT_ADDI_STATUS_INVALID_DOMAIN
+ */
+typedef struct _IOCTL_COMMON_ENABLE_DISABLE_DOMAINS {
+ IOCTL_HEADER header;
+ ENABLE_DISABLE_DOMAINS_PARAMS params;
+} SG_PACK IOCTL_COMMON_ENABLE_DISABLE_DOMAINS,
+ *PIOCTL_COMMON_ENABLE_DISABLE_DOMAINS;
+
+typedef struct _GET_DOMAIN_CONFIG_PARAMS_IN {
+ u8 domain_function;
+ u8 enable_disable;
+ u16 rsvd0;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS_IN, *PGET_DOMAIN_CONFIG_PARAMS_IN;
+
+typedef struct _GET_DOMAIN_CONFIG_PARAMS_OUT {
+ u32 domain_bitmap;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS_OUT, *PGET_DOMAIN_CONFIG_PARAMS_OUT;
+
+typedef union _GET_DOMAIN_CONFIG_PARAMS {
+ GET_DOMAIN_CONFIG_PARAMS_IN request;
+ GET_DOMAIN_CONFIG_PARAMS_OUT response;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS, *PGET_DOMAIN_CONFIG_PARAMS;
+
+/*
+ * This IOCTL returns a bitmap indicating the current status of the
+ * NIC or iSCSI functionality for all the domains supported on a given
+ * BladeEngine. The domain number in the IOCTL header is ignored. This
+ * IOCTL can only originate from domain 0. This IOCTL will always return
+ * MGMT_STATUS_SUCCESS
+ */
+typedef struct _IOCTL_COMMON_GET_DOMAIN_CONFIG {
+ IOCTL_HEADER header;
+ GET_DOMAIN_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_DOMAIN_CONFIG, *PIOCTL_COMMON_GET_DOMAIN_CONFIG;
+
+typedef struct _SET_VLD_CONFIG_PARAMS_IN {
+ u8 enable_disable;
+ u8 rsvd0;
+ u16 rsvd1;
+} SG_PACK SET_VLD_CONFIG_PARAMS_IN, *PSET_VLD_CONFIG_PARAMS_IN;
+
+typedef struct _SET_VLD_CONFIG_PARAMS_OUT {
+ u32 rsvd0;
+} SG_PACK SET_VLD_CONFIG_PARAMS_OUT, *PSET_VLD_CONFIG_PARAMS_OUT;
+
+typedef union _SET_VLD_CONFIG_PARAMS {
+ SET_VLD_CONFIG_PARAMS_IN request;
+ SET_VLD_CONFIG_PARAMS_OUT response;
+} SG_PACK SET_VLD_CONFIG_PARAMS, *PSET_VLD_CONFIG_PARAMS;
+
+/*
+ * Enable/Disable Virtual Link Down (VLD) if this feature is enabled
+ * on your BladeEngine. Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to determine
+ * whether VLD can be enabled. This IOCTL can only originate from domain
+ * 0. The VLD setting applies to the entire BladeEngine and affects
+ * all NIC/iSCSI drivers.
+ */
+typedef struct _IOCTL_COMMON_SET_VLD_CONFIG {
+ IOCTL_HEADER header;
+ SET_VLD_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_VLD_CONFIG, *PIOCTL_COMMON_SET_VLD_CONFIG;
+
+typedef struct _GET_VLD_CONFIG_PARAMS_IN {
+ u32 rsvd0;
+} SG_PACK GET_VLD_CONFIG_PARAMS_IN, *PGET_VLD_CONFIG_PARAMS_IN;
+
+typedef struct _GET_VLD_CONFIG_PARAMS_OUT {
+ u8 enable_disable;
+ u8 rsvd0;
+ u16 rsvd1;
+} SG_PACK GET_VLD_CONFIG_PARAMS_OUT, *PGET_VLD_CONFIG_PARAMS_OUT;
+
+typedef union _GET_VLD_CONFIG_PARAMS {
+ GET_VLD_CONFIG_PARAMS_IN request;
+ GET_VLD_CONFIG_PARAMS_OUT response;
+} SG_PACK GET_VLD_CONFIG_PARAMS, *PGET_VLD_CONFIG_PARAMS;
+
+/*
+ * Use this IOCTL to determine whether Virtual Link Down (VLD) is currently
+ * enabled or disabled. Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to determine
+ * whether VLD can be enabled/disabled. This IOCTL can only originate
+ * from domain 0. The VLD setting applies to the entire BladeEngine
+ * and affects all NIC/iSCSI drivers.
+ */
+typedef struct _IOCTL_COMMON_GET_VLD_CONFIG {
+ IOCTL_HEADER header;
+ GET_VLD_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_VLD_CONFIG, *PIOCTL_COMMON_GET_VLD_CONFIG;
+
+typedef struct _EQ_DELAY_PARAMS {
+ u32 eq_id;
+ u32 delay_in_microseconds;
+} SG_PACK EQ_DELAY_PARAMS, *PEQ_DELAY_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_257_REQUEST {
+ u32 num_eq;
+ u32 rsvd0;
+ EQ_DELAY_PARAMS delay[16];
+} SG_PACK IOCTL_COMMON_ANON_257_REQUEST, *PIOCTL_COMMON_ANON_257_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_258_RESPONSE {
+ u32 delay_resolution_in_microseconds;
+ u32 delay_max_in_microseconds;
+} SG_PACK IOCTL_COMMON_ANON_258_RESPONSE, *PIOCTL_COMMON_ANON_258_RESPONSE;
+
+typedef union _MODIFY_EQ_DELAY_PARAMS {
+ IOCTL_COMMON_ANON_257_REQUEST request;
+ IOCTL_COMMON_ANON_258_RESPONSE response;
+} SG_PACK MODIFY_EQ_DELAY_PARAMS, *PMODIFY_EQ_DELAY_PARAMS;
+
+/* This IOCTL changes the EQ delay for a given set of EQs. */
+typedef struct _IOCTL_COMMON_MODIFY_EQ_DELAY {
+ IOCTL_HEADER header;
+ MODIFY_EQ_DELAY_PARAMS params;
+} SG_PACK IOCTL_COMMON_MODIFY_EQ_DELAY, *PIOCTL_COMMON_MODIFY_EQ_DELAY;
+
+typedef struct _IOCTL_COMMON_ANON_260_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_260_REQUEST, *PIOCTL_COMMON_ANON_260_REQUEST;
+
+typedef struct _BE_FIRMWARE_CONFIG {
+ u16 be_config_number;
+ u16 asic_revision;
+ u32 nic_ulp_mask;
+ u32 tulp_mask;
+ u32 iscsi_ulp_mask;
+ u32 rdma_ulp_mask;
+ u32 rsvd0[4];
+ u32 eth_tx_id_start;
+ u32 eth_tx_id_count;
+ u32 eth_rx_id_start;
+ u32 eth_rx_id_count;
+ u32 tpm_wrbq_id_start;
+ u32 tpm_wrbq_id_count;
+ u32 tpm_defq_id_start;
+ u32 tpm_defq_id_count;
+ u32 iscsi_wrbq_id_start;
+ u32 iscsi_wrbq_id_count;
+ u32 iscsi_defq_id_start;
+ u32 iscsi_defq_id_count;
+ u32 rdma_qp_id_start;
+ u32 rdma_qp_id_count;
+ u32 rsvd1[8];
+} SG_PACK BE_FIRMWARE_CONFIG, *PBE_FIRMWARE_CONFIG;
+
+typedef union _IOCTL_COMMON_ANON_259_PARAMS {
+ IOCTL_COMMON_ANON_260_REQUEST request;
+ BE_FIRMWARE_CONFIG response;
+} SG_PACK IOCTL_COMMON_ANON_259_PARAMS, *PIOCTL_COMMON_ANON_259_PARAMS;
+
+/*
+ * This IOCTL queries the current firmware configuration parameters.
+ * The static configuration type is defined by be_config_number. This
+ * differentiates different BladeEngine builds, such as iSCSI Initiator
+ * versus iSCSI Target. For a given static configuration, the Upper
+ * Layer Protocol (ULP) processors may be reconfigured to support different
+ * protocols. Each ULP processor supports one or more protocols. The
+ * masks indicate which processors are configured for each protocol.
+ * For a given static configuration, the number of TCP connections
+ * supported for each protocol may vary. The *_id_start and *_id_count
+ * variables define a linear range of IDs that are available for each
+ * supported protocol. The *_id_count may be used by the driver to allocate
+ * the appropriate number of connection resources. The *_id_start may
+ * be used to map the arbitrary range of IDs to a zero-based range
+ * of indices.
+ */
+typedef struct _IOCTL_COMMON_FIRMWARE_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_259_PARAMS params;
+} SG_PACK IOCTL_COMMON_FIRMWARE_CONFIG, *PIOCTL_COMMON_FIRMWARE_CONFIG;
+
+typedef struct _IOCTL_COMMON_PORT_EQUALIZATION_PARAMS {
+ u32 emph_lev_sel_port0;
+ u32 emph_lev_sel_port1;
+ u8 xaui_vo_sel;
+ u8 xaui_state;
+ u16 rsvd0;
+ u32 xaui_eq_vector;
+} SG_PACK IOCTL_COMMON_PORT_EQUALIZATION_PARAMS,
+ *PIOCTL_COMMON_PORT_EQUALIZATION_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_262_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_262_REQUEST, *PIOCTL_COMMON_ANON_262_REQUEST;
+
+typedef union _IOCTL_COMMON_ANON_261_PARAMS {
+ IOCTL_COMMON_ANON_262_REQUEST request;
+ IOCTL_COMMON_PORT_EQUALIZATION_PARAMS response;
+} SG_PACK IOCTL_COMMON_ANON_261_PARAMS, *PIOCTL_COMMON_ANON_261_PARAMS;
+
+/*
+ * This IOCTL can be used to read XAUI equalization parameters. The
+ * ARM firmware applies default equalization parameters during initialization.
+ * These parameters may be customer-specific when derived from the
+ * SEEPROM. See SEEPROM_DATA for equalization specific fields.
+ */
+typedef struct _IOCTL_COMMON_GET_PORT_EQUALIZATION {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_261_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_PORT_EQUALIZATION,
+ *PIOCTL_COMMON_GET_PORT_EQUALIZATION;
+
+typedef struct _IOCTL_COMMON_ANON_264_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_264_RESPONSE, *PIOCTL_COMMON_ANON_264_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_263_PARAMS {
+ IOCTL_COMMON_PORT_EQUALIZATION_PARAMS request;
+ IOCTL_COMMON_ANON_264_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_263_PARAMS, *PIOCTL_COMMON_ANON_263_PARAMS;
+
+/*
+ * This IOCTL can be used to set XAUI equalization parameters. The ARM
+ * firmware applies default equalization parameters during initialization.
+ * These parameters may be customer-specific when derived from the
+ * SEEPROM. See SEEPROM_DATA for equalization specific fields.
+ */
+typedef struct _IOCTL_COMMON_SET_PORT_EQUALIZATION {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_263_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_PORT_EQUALIZATION,
+ *PIOCTL_COMMON_SET_PORT_EQUALIZATION;
+
+typedef struct _BE_RED_CHUTE_PARAMETERS {
+ u8 enable;
+ u8 w1;
+ u8 w2;
+ u8 slope;
+ u8 mtu_integer;
+ u8 mtu_exponent;
+ u16 rsvd0;
+ u16 min_pbuf;
+ u16 max_pbuf;
+} SG_PACK BE_RED_CHUTE_PARAMETERS, *PBE_RED_CHUTE_PARAMETERS;
+
+typedef struct _BE_RED_PARAMETERS {
+ BE_RED_CHUTE_PARAMETERS chute[3];
+} SG_PACK BE_RED_PARAMETERS, *PBE_RED_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_266_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_266_RESPONSE, *PIOCTL_COMMON_ANON_266_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_265_PARAMS {
+ BE_RED_PARAMETERS request;
+ IOCTL_COMMON_ANON_266_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_265_PARAMS, *PIOCTL_COMMON_ANON_265_PARAMS;
+
+/*
+ * This IOCTL configures the Random Early Discard (RED) functionality
+ * for the PCI function. Only the chutes owned by the given PCI function
+ * are configured. The other chutes are ignored.
+ */
+typedef struct _IOCTL_COMMON_RED_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_COMMON_ANON_265_PARAMS params;
+} SG_PACK IOCTL_COMMON_RED_CONFIG, *PIOCTL_COMMON_RED_CONFIG;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_common_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h 2008-02-14 15:23:07.834201784 +0530
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ep_bmap_h__
+#define __ep_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* General Control and Status Register. */
+typedef struct _EP_CONTROL_CSR {
+ union {
+ struct {
+ u32 CPU_reset:1; /* DWORD 0 */
+ u32 rsvd0:27; /* DWORD 0 */
+ u32 ff_en:1; /* DWORD 0 */
+ u32 m2_RxPbuf:1; /* DWORD 0 */
+ u32 m1_RxPbuf:1; /* DWORD 0 */
+ u32 m0_RxPbuf:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_CONTROL_CSR, *PEP_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__EP_CONTROL_CSR, sizeof(EP_CONTROL_CSR) == 4);
+
+#else
+ /* General Control and Status Register. */
+typedef struct _EP_CONTROL_CSR {
+ union {
+ struct {
+ u32 m0_RxPbuf:1; /* DWORD 0 */
+ u32 m1_RxPbuf:1; /* DWORD 0 */
+ u32 m2_RxPbuf:1; /* DWORD 0 */
+ u32 ff_en:1; /* DWORD 0 */
+ u32 rsvd0:27; /* DWORD 0 */
+ u32 CPU_reset:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_CONTROL_CSR, *PEP_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__EP_CONTROL_CSR, sizeof(EP_CONTROL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Semaphore Register. */
+typedef struct _EP_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 value; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_SEMAPHORE_CSR, *PEP_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__EP_SEMAPHORE_CSR, sizeof(EP_SEMAPHORE_CSR) == 4);
+
+#else
+ /* Semaphore Register. */
+typedef struct _EP_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 value; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_SEMAPHORE_CSR, *PEP_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__EP_SEMAPHORE_CSR, sizeof(EP_SEMAPHORE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Embedded Processor Specific Registers. */
+typedef struct _EP_CSRMAP {
+ union {
+ struct {
+ EP_CONTROL_CSR ep_control;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ u32 rsvd3[1]; /* DWORDS 4 to 4 */
+ u32 rsvd4[1]; /* DWORDS 5 to 5 */
+ u32 rsvd5[32]; /* DWORDS 6 to 37 */
+ u32 rsvd6[1]; /* DWORDS 38 to 38 */
+ u32 rsvd7[1]; /* DWORDS 39 to 39 */
+ u32 rsvd8[1]; /* DWORDS 40 to 40 */
+ u32 rsvd9[1]; /* DWORDS 41 to 41 */
+ u32 rsvd10[1]; /* DWORDS 42 to 42 */
+ EP_SEMAPHORE_CSR ep_semaphore;
+ u32 rsvd11[1]; /* DWORDS 44 to 44 */
+ u32 rsvd12[19]; /* DWORDS 45 to 63 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[64]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_CSRMAP, *PEP_CSRMAP;
+
+SG_C_ASSERT(__sizeof__EP_CSRMAP, sizeof(EP_CSRMAP) == 256);
+
+#else
+ /* Embedded Processor Specific Registers. */
+typedef struct _EP_CSRMAP {
+ union {
+ struct {
+ EP_CONTROL_CSR ep_control;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ u32 rsvd3[1]; /* DWORDS 4 to 4 */
+ u32 rsvd4[1]; /* DWORDS 5 to 5 */
+ u32 rsvd5[32]; /* DWORDS 6 to 37 */
+ u32 rsvd6[1]; /* DWORDS 38 to 38 */
+ u32 rsvd7[1]; /* DWORDS 39 to 39 */
+ u32 rsvd8[1]; /* DWORDS 40 to 40 */
+ u32 rsvd9[1]; /* DWORDS 41 to 41 */
+ u32 rsvd10[1]; /* DWORDS 42 to 42 */
+ EP_SEMAPHORE_CSR ep_semaphore;
+ u32 rsvd11[1]; /* DWORDS 44 to 44 */
+ u32 rsvd12[19]; /* DWORDS 45 to 63 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[64]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK EP_CSRMAP, *PEP_CSRMAP;
+
+SG_C_ASSERT(__sizeof__EP_CSRMAP, sizeof(EP_CSRMAP) == 256);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ep_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h 2008-02-14 15:23:07.834201784 +0530
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __cev_bmap_h__
+#define __cev_bmap_h__
+#include "setypes.h"
+#include "ep_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Host Interrupt Status Register 0. The first of four application interrupt
+ * status registers. This register contains the interrupts for Event
+ * Queues EQ0 through EQ31.
+ */
+typedef struct _CEV_ISR0_CSR {
+ union {
+ struct {
+ u32 interrupt31:1; /* DWORD 0 */
+ u32 interrupt30:1; /* DWORD 0 */
+ u32 interrupt29:1; /* DWORD 0 */
+ u32 interrupt28:1; /* DWORD 0 */
+ u32 interrupt27:1; /* DWORD 0 */
+ u32 interrupt26:1; /* DWORD 0 */
+ u32 interrupt25:1; /* DWORD 0 */
+ u32 interrupt24:1; /* DWORD 0 */
+ u32 interrupt23:1; /* DWORD 0 */
+ u32 interrupt22:1; /* DWORD 0 */
+ u32 interrupt21:1; /* DWORD 0 */
+ u32 interrupt20:1; /* DWORD 0 */
+ u32 interrupt19:1; /* DWORD 0 */
+ u32 interrupt18:1; /* DWORD 0 */
+ u32 interrupt17:1; /* DWORD 0 */
+ u32 interrupt16:1; /* DWORD 0 */
+ u32 interrupt15:1; /* DWORD 0 */
+ u32 interrupt14:1; /* DWORD 0 */
+ u32 interrupt13:1; /* DWORD 0 */
+ u32 interrupt12:1; /* DWORD 0 */
+ u32 interrupt11:1; /* DWORD 0 */
+ u32 interrupt10:1; /* DWORD 0 */
+ u32 interrupt9:1; /* DWORD 0 */
+ u32 interrupt8:1; /* DWORD 0 */
+ u32 interrupt7:1; /* DWORD 0 */
+ u32 interrupt6:1; /* DWORD 0 */
+ u32 interrupt5:1; /* DWORD 0 */
+ u32 interrupt4:1; /* DWORD 0 */
+ u32 interrupt3:1; /* DWORD 0 */
+ u32 interrupt2:1; /* DWORD 0 */
+ u32 interrupt1:1; /* DWORD 0 */
+ u32 interrupt0:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR0_CSR, *PCEV_ISR0_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR0_CSR, sizeof(CEV_ISR0_CSR) == 4);
+
+#else
+ /*
+ * Host Interrupt Status Register 0. The first of four application interrupt
+ * status registers. This register contains the interrupts for Event
+ * Queues EQ0 through EQ31.
+ */
+typedef struct _CEV_ISR0_CSR {
+ union {
+ struct {
+ u32 interrupt0:1; /* DWORD 0 */
+ u32 interrupt1:1; /* DWORD 0 */
+ u32 interrupt2:1; /* DWORD 0 */
+ u32 interrupt3:1; /* DWORD 0 */
+ u32 interrupt4:1; /* DWORD 0 */
+ u32 interrupt5:1; /* DWORD 0 */
+ u32 interrupt6:1; /* DWORD 0 */
+ u32 interrupt7:1; /* DWORD 0 */
+ u32 interrupt8:1; /* DWORD 0 */
+ u32 interrupt9:1; /* DWORD 0 */
+ u32 interrupt10:1; /* DWORD 0 */
+ u32 interrupt11:1; /* DWORD 0 */
+ u32 interrupt12:1; /* DWORD 0 */
+ u32 interrupt13:1; /* DWORD 0 */
+ u32 interrupt14:1; /* DWORD 0 */
+ u32 interrupt15:1; /* DWORD 0 */
+ u32 interrupt16:1; /* DWORD 0 */
+ u32 interrupt17:1; /* DWORD 0 */
+ u32 interrupt18:1; /* DWORD 0 */
+ u32 interrupt19:1; /* DWORD 0 */
+ u32 interrupt20:1; /* DWORD 0 */
+ u32 interrupt21:1; /* DWORD 0 */
+ u32 interrupt22:1; /* DWORD 0 */
+ u32 interrupt23:1; /* DWORD 0 */
+ u32 interrupt24:1; /* DWORD 0 */
+ u32 interrupt25:1; /* DWORD 0 */
+ u32 interrupt26:1; /* DWORD 0 */
+ u32 interrupt27:1; /* DWORD 0 */
+ u32 interrupt28:1; /* DWORD 0 */
+ u32 interrupt29:1; /* DWORD 0 */
+ u32 interrupt30:1; /* DWORD 0 */
+ u32 interrupt31:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR0_CSR, *PCEV_ISR0_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR0_CSR, sizeof(CEV_ISR0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Host Interrupt Status Register 1. The second of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ32 through EQ63.
+ */
+typedef struct _CEV_ISR1_CSR {
+ union {
+ struct {
+ u32 interrupt63:1; /* DWORD 0 */
+ u32 interrupt62:1; /* DWORD 0 */
+ u32 interrupt61:1; /* DWORD 0 */
+ u32 interrupt60:1; /* DWORD 0 */
+ u32 interrupt59:1; /* DWORD 0 */
+ u32 interrupt58:1; /* DWORD 0 */
+ u32 interrupt57:1; /* DWORD 0 */
+ u32 interrupt56:1; /* DWORD 0 */
+ u32 interrupt55:1; /* DWORD 0 */
+ u32 interrupt54:1; /* DWORD 0 */
+ u32 interrupt53:1; /* DWORD 0 */
+ u32 interrupt52:1; /* DWORD 0 */
+ u32 interrupt51:1; /* DWORD 0 */
+ u32 interrupt50:1; /* DWORD 0 */
+ u32 interrupt49:1; /* DWORD 0 */
+ u32 interrupt48:1; /* DWORD 0 */
+ u32 interrupt47:1; /* DWORD 0 */
+ u32 interrupt46:1; /* DWORD 0 */
+ u32 interrupt45:1; /* DWORD 0 */
+ u32 interrupt44:1; /* DWORD 0 */
+ u32 interrupt43:1; /* DWORD 0 */
+ u32 interrupt42:1; /* DWORD 0 */
+ u32 interrupt41:1; /* DWORD 0 */
+ u32 interrupt40:1; /* DWORD 0 */
+ u32 interrupt39:1; /* DWORD 0 */
+ u32 interrupt38:1; /* DWORD 0 */
+ u32 interrupt37:1; /* DWORD 0 */
+ u32 interrupt36:1; /* DWORD 0 */
+ u32 interrupt35:1; /* DWORD 0 */
+ u32 interrupt34:1; /* DWORD 0 */
+ u32 interrupt33:1; /* DWORD 0 */
+ u32 interrupt32:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR1_CSR, *PCEV_ISR1_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR1_CSR, sizeof(CEV_ISR1_CSR) == 4);
+
+#else
+ /*
+ * Host Interrupt Status Register 1. The second of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ32 through EQ63.
+ */
+typedef struct _CEV_ISR1_CSR {
+ union {
+ struct {
+ u32 interrupt32:1; /* DWORD 0 */
+ u32 interrupt33:1; /* DWORD 0 */
+ u32 interrupt34:1; /* DWORD 0 */
+ u32 interrupt35:1; /* DWORD 0 */
+ u32 interrupt36:1; /* DWORD 0 */
+ u32 interrupt37:1; /* DWORD 0 */
+ u32 interrupt38:1; /* DWORD 0 */
+ u32 interrupt39:1; /* DWORD 0 */
+ u32 interrupt40:1; /* DWORD 0 */
+ u32 interrupt41:1; /* DWORD 0 */
+ u32 interrupt42:1; /* DWORD 0 */
+ u32 interrupt43:1; /* DWORD 0 */
+ u32 interrupt44:1; /* DWORD 0 */
+ u32 interrupt45:1; /* DWORD 0 */
+ u32 interrupt46:1; /* DWORD 0 */
+ u32 interrupt47:1; /* DWORD 0 */
+ u32 interrupt48:1; /* DWORD 0 */
+ u32 interrupt49:1; /* DWORD 0 */
+ u32 interrupt50:1; /* DWORD 0 */
+ u32 interrupt51:1; /* DWORD 0 */
+ u32 interrupt52:1; /* DWORD 0 */
+ u32 interrupt53:1; /* DWORD 0 */
+ u32 interrupt54:1; /* DWORD 0 */
+ u32 interrupt55:1; /* DWORD 0 */
+ u32 interrupt56:1; /* DWORD 0 */
+ u32 interrupt57:1; /* DWORD 0 */
+ u32 interrupt58:1; /* DWORD 0 */
+ u32 interrupt59:1; /* DWORD 0 */
+ u32 interrupt60:1; /* DWORD 0 */
+ u32 interrupt61:1; /* DWORD 0 */
+ u32 interrupt62:1; /* DWORD 0 */
+ u32 interrupt63:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR1_CSR, *PCEV_ISR1_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR1_CSR, sizeof(CEV_ISR1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Host Interrupt Status Register 2. The third of four application interrupt
+ * status registers. This register contains the interrupts for Event
+ * Queues EQ64 through EQ95.
+ */
+typedef struct _CEV_ISR2_CSR {
+ union {
+ struct {
+ u32 interrupt95:1; /* DWORD 0 */
+ u32 interrupt94:1; /* DWORD 0 */
+ u32 interrupt93:1; /* DWORD 0 */
+ u32 interrupt92:1; /* DWORD 0 */
+ u32 interrupt91:1; /* DWORD 0 */
+ u32 interrupt90:1; /* DWORD 0 */
+ u32 interrupt89:1; /* DWORD 0 */
+ u32 interrupt88:1; /* DWORD 0 */
+ u32 interrupt87:1; /* DWORD 0 */
+ u32 interrupt86:1; /* DWORD 0 */
+ u32 interrupt85:1; /* DWORD 0 */
+ u32 interrupt84:1; /* DWORD 0 */
+ u32 interrupt83:1; /* DWORD 0 */
+ u32 interrupt82:1; /* DWORD 0 */
+ u32 interrupt81:1; /* DWORD 0 */
+ u32 interrupt80:1; /* DWORD 0 */
+ u32 interrupt79:1; /* DWORD 0 */
+ u32 interrupt78:1; /* DWORD 0 */
+ u32 interrupt77:1; /* DWORD 0 */
+ u32 interrupt76:1; /* DWORD 0 */
+ u32 interrupt75:1; /* DWORD 0 */
+ u32 interrupt74:1; /* DWORD 0 */
+ u32 interrupt73:1; /* DWORD 0 */
+ u32 interrupt72:1; /* DWORD 0 */
+ u32 interrupt71:1; /* DWORD 0 */
+ u32 interrupt70:1; /* DWORD 0 */
+ u32 interrupt69:1; /* DWORD 0 */
+ u32 interrupt68:1; /* DWORD 0 */
+ u32 interrupt67:1; /* DWORD 0 */
+ u32 interrupt66:1; /* DWORD 0 */
+ u32 interrupt65:1; /* DWORD 0 */
+ u32 interrupt64:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR2_CSR, *PCEV_ISR2_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR2_CSR, sizeof(CEV_ISR2_CSR) == 4);
+
+#else
+ /*
+ * Host Interrupt Status Register 2. The third of four application interrupt
+ * status registers. This register contains the interrupts for Event
+ * Queues EQ64 through EQ95.
+ */
+typedef struct _CEV_ISR2_CSR {
+ union {
+ struct {
+ u32 interrupt64:1; /* DWORD 0 */
+ u32 interrupt65:1; /* DWORD 0 */
+ u32 interrupt66:1; /* DWORD 0 */
+ u32 interrupt67:1; /* DWORD 0 */
+ u32 interrupt68:1; /* DWORD 0 */
+ u32 interrupt69:1; /* DWORD 0 */
+ u32 interrupt70:1; /* DWORD 0 */
+ u32 interrupt71:1; /* DWORD 0 */
+ u32 interrupt72:1; /* DWORD 0 */
+ u32 interrupt73:1; /* DWORD 0 */
+ u32 interrupt74:1; /* DWORD 0 */
+ u32 interrupt75:1; /* DWORD 0 */
+ u32 interrupt76:1; /* DWORD 0 */
+ u32 interrupt77:1; /* DWORD 0 */
+ u32 interrupt78:1; /* DWORD 0 */
+ u32 interrupt79:1; /* DWORD 0 */
+ u32 interrupt80:1; /* DWORD 0 */
+ u32 interrupt81:1; /* DWORD 0 */
+ u32 interrupt82:1; /* DWORD 0 */
+ u32 interrupt83:1; /* DWORD 0 */
+ u32 interrupt84:1; /* DWORD 0 */
+ u32 interrupt85:1; /* DWORD 0 */
+ u32 interrupt86:1; /* DWORD 0 */
+ u32 interrupt87:1; /* DWORD 0 */
+ u32 interrupt88:1; /* DWORD 0 */
+ u32 interrupt89:1; /* DWORD 0 */
+ u32 interrupt90:1; /* DWORD 0 */
+ u32 interrupt91:1; /* DWORD 0 */
+ u32 interrupt92:1; /* DWORD 0 */
+ u32 interrupt93:1; /* DWORD 0 */
+ u32 interrupt94:1; /* DWORD 0 */
+ u32 interrupt95:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR2_CSR, *PCEV_ISR2_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR2_CSR, sizeof(CEV_ISR2_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Host Interrupt Status Register 3. The fourth of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ96 through EQ127.
+ */
+typedef struct _CEV_ISR3_CSR {
+ union {
+ struct {
+ u32 interrupt127:1; /* DWORD 0 */
+ u32 interrupt126:1; /* DWORD 0 */
+ u32 interrupt125:1; /* DWORD 0 */
+ u32 interrupt124:1; /* DWORD 0 */
+ u32 interrupt123:1; /* DWORD 0 */
+ u32 interrupt122:1; /* DWORD 0 */
+ u32 interrupt121:1; /* DWORD 0 */
+ u32 interrupt120:1; /* DWORD 0 */
+ u32 interrupt119:1; /* DWORD 0 */
+ u32 interrupt118:1; /* DWORD 0 */
+ u32 interrupt117:1; /* DWORD 0 */
+ u32 interrupt116:1; /* DWORD 0 */
+ u32 interrupt115:1; /* DWORD 0 */
+ u32 interrupt114:1; /* DWORD 0 */
+ u32 interrupt113:1; /* DWORD 0 */
+ u32 interrupt112:1; /* DWORD 0 */
+ u32 interrupt111:1; /* DWORD 0 */
+ u32 interrupt110:1; /* DWORD 0 */
+ u32 interrupt109:1; /* DWORD 0 */
+ u32 interrupt108:1; /* DWORD 0 */
+ u32 interrupt107:1; /* DWORD 0 */
+ u32 interrupt106:1; /* DWORD 0 */
+ u32 interrupt105:1; /* DWORD 0 */
+ u32 interrupt104:1; /* DWORD 0 */
+ u32 interrupt103:1; /* DWORD 0 */
+ u32 interrupt102:1; /* DWORD 0 */
+ u32 interrupt101:1; /* DWORD 0 */
+ u32 interrupt100:1; /* DWORD 0 */
+ u32 interrupt99:1; /* DWORD 0 */
+ u32 interrupt98:1; /* DWORD 0 */
+ u32 interrupt97:1; /* DWORD 0 */
+ u32 interrupt96:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR3_CSR, *PCEV_ISR3_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR3_CSR, sizeof(CEV_ISR3_CSR) == 4);
+
+#else
+ /*
+ * Host Interrupt Status Register 3. The fourth of four application
+ * interrupt status registers. This register contains the interrupts
+ * for Event Queues EQ96 through EQ127.
+ */
+typedef struct _CEV_ISR3_CSR {
+ union {
+ struct {
+ u32 interrupt96:1; /* DWORD 0 */
+ u32 interrupt97:1; /* DWORD 0 */
+ u32 interrupt98:1; /* DWORD 0 */
+ u32 interrupt99:1; /* DWORD 0 */
+ u32 interrupt100:1; /* DWORD 0 */
+ u32 interrupt101:1; /* DWORD 0 */
+ u32 interrupt102:1; /* DWORD 0 */
+ u32 interrupt103:1; /* DWORD 0 */
+ u32 interrupt104:1; /* DWORD 0 */
+ u32 interrupt105:1; /* DWORD 0 */
+ u32 interrupt106:1; /* DWORD 0 */
+ u32 interrupt107:1; /* DWORD 0 */
+ u32 interrupt108:1; /* DWORD 0 */
+ u32 interrupt109:1; /* DWORD 0 */
+ u32 interrupt110:1; /* DWORD 0 */
+ u32 interrupt111:1; /* DWORD 0 */
+ u32 interrupt112:1; /* DWORD 0 */
+ u32 interrupt113:1; /* DWORD 0 */
+ u32 interrupt114:1; /* DWORD 0 */
+ u32 interrupt115:1; /* DWORD 0 */
+ u32 interrupt116:1; /* DWORD 0 */
+ u32 interrupt117:1; /* DWORD 0 */
+ u32 interrupt118:1; /* DWORD 0 */
+ u32 interrupt119:1; /* DWORD 0 */
+ u32 interrupt120:1; /* DWORD 0 */
+ u32 interrupt121:1; /* DWORD 0 */
+ u32 interrupt122:1; /* DWORD 0 */
+ u32 interrupt123:1; /* DWORD 0 */
+ u32 interrupt124:1; /* DWORD 0 */
+ u32 interrupt125:1; /* DWORD 0 */
+ u32 interrupt126:1; /* DWORD 0 */
+ u32 interrupt127:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_ISR3_CSR, *PCEV_ISR3_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR3_CSR, sizeof(CEV_ISR3_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Completions and Events block Registers. */
+typedef struct _CEV_CSRMAP {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ u32 rsvd2[1]; /* DWORDS 2 to 2 */
+ u32 rsvd3[1]; /* DWORDS 3 to 3 */
+ CEV_ISR0_CSR isr0;
+ CEV_ISR1_CSR isr1;
+ CEV_ISR2_CSR isr2;
+ CEV_ISR3_CSR isr3;
+ u32 rsvd4[1]; /* DWORDS 8 to 8 */
+ u32 rsvd5[1]; /* DWORDS 9 to 9 */
+ u32 rsvd6[1]; /* DWORDS 10 to 10 */
+ u32 rsvd7[1]; /* DWORDS 11 to 11 */
+ u32 rsvd8[1]; /* DWORDS 12 to 12 */
+ u32 rsvd9[1]; /* DWORDS 13 to 13 */
+ u32 rsvd10[1]; /* DWORDS 14 to 14 */
+ u32 rsvd11[1]; /* DWORDS 15 to 15 */
+ u32 rsvd12[1]; /* DWORDS 16 to 16 */
+ u32 rsvd13[1]; /* DWORDS 17 to 17 */
+ u32 rsvd14[1]; /* DWORDS 18 to 18 */
+ u32 rsvd15[1]; /* DWORDS 19 to 19 */
+ u32 rsvd16[1]; /* DWORDS 20 to 20 */
+ u32 rsvd17[1]; /* DWORDS 21 to 21 */
+ u32 rsvd18[1]; /* DWORDS 22 to 22 */
+ u32 rsvd19[1]; /* DWORDS 23 to 23 */
+ u32 rsvd20[1]; /* DWORDS 24 to 24 */
+ u32 rsvd21[1]; /* DWORDS 25 to 25 */
+ u32 rsvd22[1]; /* DWORDS 26 to 26 */
+ u32 rsvd23[1]; /* DWORDS 27 to 27 */
+ u32 rsvd24[1]; /* DWORDS 28 to 28 */
+ u32 rsvd25[1]; /* DWORDS 29 to 29 */
+ u32 rsvd26[1]; /* DWORDS 30 to 30 */
+ u32 rsvd27[1]; /* DWORDS 31 to 31 */
+ u32 rsvd28[1]; /* DWORDS 32 to 32 */
+ u32 rsvd29[1]; /* DWORDS 33 to 33 */
+ u32 rsvd30[6]; /* DWORDS 34 to 39 */
+ u32 rsvd31[6]; /* DWORDS 40 to 45 */
+ u32 rsvd32[5]; /* DWORDS 46 to 50 */
+ u32 rsvd33[5]; /* DWORDS 51 to 55 */
+ u32 rsvd34[5]; /* DWORDS 56 to 60 */
+ u32 rsvd35[3]; /* DWORDS 61 to 63 */
+ u32 rsvd36[192]; /* DWORDS 64 to 255 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[256]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_CSRMAP, *PCEV_CSRMAP;
+
+SG_C_ASSERT(__sizeof__CEV_CSRMAP, sizeof(CEV_CSRMAP) == 1024);
+
+#else
+ /* Completions and Events block Registers. */
+typedef struct _CEV_CSRMAP {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ u32 rsvd2[1]; /* DWORDS 2 to 2 */
+ u32 rsvd3[1]; /* DWORDS 3 to 3 */
+ CEV_ISR0_CSR isr0;
+ CEV_ISR1_CSR isr1;
+ CEV_ISR2_CSR isr2;
+ CEV_ISR3_CSR isr3;
+ u32 rsvd4[1]; /* DWORDS 8 to 8 */
+ u32 rsvd5[1]; /* DWORDS 9 to 9 */
+ u32 rsvd6[1]; /* DWORDS 10 to 10 */
+ u32 rsvd7[1]; /* DWORDS 11 to 11 */
+ u32 rsvd8[1]; /* DWORDS 12 to 12 */
+ u32 rsvd9[1]; /* DWORDS 13 to 13 */
+ u32 rsvd10[1]; /* DWORDS 14 to 14 */
+ u32 rsvd11[1]; /* DWORDS 15 to 15 */
+ u32 rsvd12[1]; /* DWORDS 16 to 16 */
+ u32 rsvd13[1]; /* DWORDS 17 to 17 */
+ u32 rsvd14[1]; /* DWORDS 18 to 18 */
+ u32 rsvd15[1]; /* DWORDS 19 to 19 */
+ u32 rsvd16[1]; /* DWORDS 20 to 20 */
+ u32 rsvd17[1]; /* DWORDS 21 to 21 */
+ u32 rsvd18[1]; /* DWORDS 22 to 22 */
+ u32 rsvd19[1]; /* DWORDS 23 to 23 */
+ u32 rsvd20[1]; /* DWORDS 24 to 24 */
+ u32 rsvd21[1]; /* DWORDS 25 to 25 */
+ u32 rsvd22[1]; /* DWORDS 26 to 26 */
+ u32 rsvd23[1]; /* DWORDS 27 to 27 */
+ u32 rsvd24[1]; /* DWORDS 28 to 28 */
+ u32 rsvd25[1]; /* DWORDS 29 to 29 */
+ u32 rsvd26[1]; /* DWORDS 30 to 30 */
+ u32 rsvd27[1]; /* DWORDS 31 to 31 */
+ u32 rsvd28[1]; /* DWORDS 32 to 32 */
+ u32 rsvd29[1]; /* DWORDS 33 to 33 */
+ u32 rsvd30[6]; /* DWORDS 34 to 39 */
+ u32 rsvd31[6]; /* DWORDS 40 to 45 */
+ u32 rsvd32[5]; /* DWORDS 46 to 50 */
+ u32 rsvd33[5]; /* DWORDS 51 to 55 */
+ u32 rsvd34[5]; /* DWORDS 56 to 60 */
+ u32 rsvd35[3]; /* DWORDS 61 to 63 */
+ u32 rsvd36[192]; /* DWORDS 64 to 255 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[256]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK CEV_CSRMAP, *PCEV_CSRMAP;
+
+SG_C_ASSERT(__sizeof__CEV_CSRMAP, sizeof(CEV_CSRMAP) == 1024);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __cev_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h 2008-02-14 15:23:07.835201632 +0530
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __be_cm_bmap_h__
+#define __be_cm_bmap_h__
+#include "setypes.h"
+#include "be_common_bmap.h"
+#include "iscsi_common_host_struct_bmap.h"
+#include "etx_context_bmap.h"
+#include "mpu_context_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Completion Queue Context Table Entry. Contains the state of a CQ.
+ * Located in RAM within the CEV block.
+ */
+typedef struct _CQ_CONTEXT {
+ u32 Eventable:1; /* DWORD 0 */
+ u32 SolEvent:1; /* DWORD 0 */
+ u32 valid:1; /* DWORD 0 */
+ u32 Count:2; /* DWORD 0 */
+ u32 EPIdx:11; /* DWORD 0 */
+ u32 NoDelay:1; /* DWORD 0 */
+ u32 Watermark:4; /* DWORD 0 */
+ u32 Cidx:11; /* DWORD 0 */
+ u32 Armed:1; /* DWORD 1 */
+ u32 Stalled:1; /* DWORD 1 */
+ u32 WME:1; /* DWORD 1 */
+ u32 Func:1; /* DWORD 1 */
+ u32 EQID:7; /* DWORD 1 */
+ u32 PD:10; /* DWORD 1 */
+ u32 Pidx:11; /* DWORD 1 */
+} SG_PACK CQ_CONTEXT, *PCQ_CONTEXT;
+
+#else
+ /*
+ * Completion Queue Context Table Entry. Contains the state of a CQ.
+ * Located in RAM within the CEV block.
+ */
+typedef struct _CQ_CONTEXT {
+ u32 Cidx:11; /* DWORD 0 */
+ u32 Watermark:4; /* DWORD 0 */
+ u32 NoDelay:1; /* DWORD 0 */
+ u32 EPIdx:11; /* DWORD 0 */
+ u32 Count:2; /* DWORD 0 */
+ u32 valid:1; /* DWORD 0 */
+ u32 SolEvent:1; /* DWORD 0 */
+ u32 Eventable:1; /* DWORD 0 */
+ u32 Pidx:11; /* DWORD 1 */
+ u32 PD:10; /* DWORD 1 */
+ u32 EQID:7; /* DWORD 1 */
+ u32 Func:1; /* DWORD 1 */
+ u32 WME:1; /* DWORD 1 */
+ u32 Stalled:1; /* DWORD 1 */
+ u32 Armed:1; /* DWORD 1 */
+} SG_PACK CQ_CONTEXT, *PCQ_CONTEXT;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Event Queue Context Table Entry. Contains the state of an EQ. Located
+ * in RAM in the CEV block.
+ */
+typedef struct _EQ_CONTEXT {
+ u32 Size:1; /* DWORD 0 */
+ u32 rsvd1:1; /* DWORD 0 */
+ u32 valid:1; /* DWORD 0 */
+ u32 EPIdx:13; /* DWORD 0 */
+ u32 Func:1; /* DWORD 0 */
+ u32 rsvd0:2; /* DWORD 0 */
+ u32 Cidx:13; /* DWORD 0 */
+ u32 Armed:1; /* DWORD 1 */
+ u32 Stalled:1; /* DWORD 1 */
+ u32 SolEvent:1; /* DWORD 1 */
+ u32 Count:3; /* DWORD 1 */
+ u32 PD:10; /* DWORD 1 */
+ u32 rsvd2:3; /* DWORD 1 */
+ u32 Pidx:13; /* DWORD 1 */
+ u32 rsvd6:1; /* DWORD 2 */
+ u32 TMR:1; /* DWORD 2 */
+ u32 rsvd5:6; /* DWORD 2 */
+ u32 Delay:8; /* DWORD 2 */
+ u32 rsvd4:2; /* DWORD 2 */
+ u32 EventVect:6; /* DWORD 2 */
+ u32 rsvd3:3; /* DWORD 2 */
+ u32 WME:1; /* DWORD 2 */
+ u32 Watermark:4; /* DWORD 2 */
+ u32 rsvd7[1]; /* DWORDS 3 to 3 */
+} SG_PACK EQ_CONTEXT, *PEQ_CONTEXT;
+
+#else
+ /*
+ * Event Queue Context Table Entry. Contains the state of an EQ. Located
+ * in RAM in the CEV block.
+ */
+typedef struct _EQ_CONTEXT {
+ u32 Cidx:13; /* DWORD 0 */
+ u32 rsvd0:2; /* DWORD 0 */
+ u32 Func:1; /* DWORD 0 */
+ u32 EPIdx:13; /* DWORD 0 */
+ u32 valid:1; /* DWORD 0 */
+ u32 rsvd1:1; /* DWORD 0 */
+ u32 Size:1; /* DWORD 0 */
+ u32 Pidx:13; /* DWORD 1 */
+ u32 rsvd2:3; /* DWORD 1 */
+ u32 PD:10; /* DWORD 1 */
+ u32 Count:3; /* DWORD 1 */
+ u32 SolEvent:1; /* DWORD 1 */
+ u32 Stalled:1; /* DWORD 1 */
+ u32 Armed:1; /* DWORD 1 */
+ u32 Watermark:4; /* DWORD 2 */
+ u32 WME:1; /* DWORD 2 */
+ u32 rsvd3:3; /* DWORD 2 */
+ u32 EventVect:6; /* DWORD 2 */
+ u32 rsvd4:2; /* DWORD 2 */
+ u32 Delay:8; /* DWORD 2 */
+ u32 rsvd5:6; /* DWORD 2 */
+ u32 TMR:1; /* DWORD 2 */
+ u32 rsvd6:1; /* DWORD 2 */
+ u32 rsvd7[1]; /* DWORDS 3 to 3 */
+} SG_PACK EQ_CONTEXT, *PEQ_CONTEXT;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __be_cm_bmap_h__ */
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
intended recipient of this message, please immediately advise the sender by reply email message and
delete all copies of this message and any attachment(s). Thank you.
^ permalink raw reply
* [PATHCH 14/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 2:56 UTC (permalink / raw)
To: netdev
F/W header files.
------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_initiator_host_struct_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_initiator_host_struct_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_initiator_host_struct_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_initiator_host_struct_bmap.h 2008-02-14 15:23:07.836201480 +0530
@@ -0,0 +1,642 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__iscsi_initiator_host_struct_bmap_h__
+#define __iscsi_initiator_host_struct_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+ /* iSCSI Completion Queue Entry definition for cmd/cxn level
+completions */ typedef struct _ISCSI_CQ_ENTRY {
+ union {
+ struct {
+ u32 status:4; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 sts_type:1; /* DWORD 0 */
+ u32 wrb_index:15; /* DWORD 0 */
+ u32 iMaxCmdSNOffset:8; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 iFlags:7; /* DWORD 1 */
+ u32 iResponse:8; /* DWORD 1 */
+ u32 iStatus:8; /* DWORD 1 */
+ u32 iExpCmdSN; /* DWORD 2 */
+ u32 Valid:1; /* DWORD 3 */
+ u32 iResidualCnt:31; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_CQ_ENTRY, *PISCSI_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_CQ_ENTRY, sizeof(ISCSI_CQ_ENTRY) == 16);
+
+#else
+ /* iSCSI Completion Queue Entry definition for cmd/cxn level
+completions */ typedef struct _ISCSI_CQ_ENTRY {
+ union {
+ struct {
+ u32 wrb_index:15; /* DWORD 0 */
+ u32 sts_type:1; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 status:4; /* DWORD 0 */
+ u32 iStatus:8; /* DWORD 1 */
+ u32 iResponse:8; /* DWORD 1 */
+ u32 iFlags:7; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 iMaxCmdSNOffset:8; /* DWORD 1 */
+ u32 iExpCmdSN; /* DWORD 2 */
+ u32 iResidualCnt:31; /* DWORD 3 */
+ u32 Valid:1; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_CQ_ENTRY, *PISCSI_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_CQ_ENTRY, sizeof(ISCSI_CQ_ENTRY) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD {
+ u32 rsvd1:22; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:22; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_102_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD {
+ u32 rsvd1:7; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:7; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_103_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD {
+ union {
+ struct {
+ u32 rsvd1:31; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD) == 4);
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD {
+ union {
+ struct {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_104_RSVD) == 4); #endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * iSCSI Completion Queue Entry Definition for default (aka unsolicited)
+ * pdu completions
+ */
+typedef struct _ISCSI_DEFAULT_PDU_CQ_ENTRY {
+ union {
+ struct {
+ u32 status:4; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 dataPlacementLength:16; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 rsvd0:23; /* DWORD 1 */
+ u32 rsvd2[1]; /* DWORDS 2 to 2 */
+ u32 Valid:1; /* DWORD 3 */
+ u32 pduBytesRcvd:31; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_DEFAULT_PDU_CQ_ENTRY, *PISCSI_DEFAULT_PDU_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_DEFAULT_PDU_CQ_ENTRY,
+ sizeof(ISCSI_DEFAULT_PDU_CQ_ENTRY) == 16);
+
+#else
+ /*
+ * iSCSI Completion Queue Entry Definition for default (aka unsolicited)
+ * pdu completions
+ */
+typedef struct _ISCSI_DEFAULT_PDU_CQ_ENTRY {
+ union {
+ struct {
+ u32 dataPlacementLength:16; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 status:4; /* DWORD 0 */
+ u32 rsvd0:23; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 rsvd2[1]; /* DWORDS 2 to 2 */
+ u32 pduBytesRcvd:31; /* DWORD 3 */
+ u32 Valid:1; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_DEFAULT_PDU_CQ_ENTRY, *PISCSI_DEFAULT_PDU_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_DEFAULT_PDU_CQ_ENTRY,
+ sizeof(ISCSI_DEFAULT_PDU_CQ_ENTRY) == 16); #endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_105_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD {
+ u32 rsvd1:22; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:22; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_106_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD {
+ u32 rsvd1:7; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:7; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_107_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD {
+ union {
+ struct {
+ u32 rsvd1:31; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD) == 4);
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD {
+ union {
+ struct {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_108_RSVD) == 4); #endif
+
+#if defined(__BIG_ENDIAN)
+ /* iSCSI Completion Queue Entry definition for driver msg
+completions */ typedef struct _ISCSI_DRIVER_MSG_CQ_ENTRY {
+ union {
+ struct {
+ u32 status:4; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 wrb_index:15; /* DWORD 0 */
+ u32 rsvd2:8; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 rsvd1:23; /* DWORD 1 */
+ u32 rsvd3[1]; /* DWORDS 2 to 2 */
+ u32 Valid:1; /* DWORD 3 */
+ u32 pduBytesRcvd:31; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_DRIVER_MSG_CQ_ENTRY, *PISCSI_DRIVER_MSG_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_DRIVER_MSG_CQ_ENTRY,
+ sizeof(ISCSI_DRIVER_MSG_CQ_ENTRY) == 16);
+
+#else
+ /* iSCSI Completion Queue Entry definition for driver msg
+completions */ typedef struct _ISCSI_DRIVER_MSG_CQ_ENTRY {
+ union {
+ struct {
+ u32 wrb_index:15; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 cid:10; /* DWORD 0 */
+ u32 cq_type:2; /* DWORD 0 */
+ u32 status:4; /* DWORD 0 */
+ u32 rsvd1:23; /* DWORD 1 */
+ u32 s:1; /* DWORD 1 */
+ u32 rsvd2:8; /* DWORD 1 */
+ u32 rsvd3[1]; /* DWORDS 2 to 2 */
+ u32 pduBytesRcvd:31; /* DWORD 3 */
+ u32 Valid:1; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_DRIVER_MSG_CQ_ENTRY, *PISCSI_DRIVER_MSG_CQ_ENTRY;
+
+SG_C_ASSERT(__sizeof__ISCSI_DRIVER_MSG_CQ_ENTRY,
+ sizeof(ISCSI_DRIVER_MSG_CQ_ENTRY) == 16); #endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD {
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_109_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD {
+ u32 rsvd1:7; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:7; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_110_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD {
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_111_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD {
+ union {
+ struct {
+ u32 rsvd1:31; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD) == 4); #else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD {
+ union {
+ struct {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD,
+ sizeof(ISCSI_INITIATOR_HOST_STRUCT_ANON_112_RSVD) == 4); #endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * [table name="iSCSIWRBInitiator" col="4" delimit=":" caption="iSCSI
+ * Initiator WRB flag details."] iSCSI PDU type : WR : DSP : DMSG
+ * : iSCSI Write command with/without Immediate/unsolicited data
+ * : 1 : 1 : 0 : iSCSI Read command: 0 : 0 : 0 : Text request without
+ * data: 0 : 0 : 0 : Text request with data: 1 : 1 : 0 : Logout
+ * request: 0 : 0 : 0 : NOP OUT with ping data with acknowledgement:
+ * 1 : 1 : 0 : NOP OUT without ping data with acknowledgement: 0
+ * : 0 : 0 : NOP OUT without acknowledgement: 0 : 0 : 1 : NOP OUT
+ * in response to NOP IN from iSCSI target: 0 : 0 : 1 : Task Management
+ * function request: 0 : 0 : 0 : [/table] Note: The logout and
+ * task management response will be notified to host driver by Rx
+ * ULP as part of default ring processing. It is host driver responsibility
+ * to wait for response or time out for these commands to cleanup
+ * related data structures.
+ */
+typedef struct _ISCSI_INITIATOR_WRB {
+ union {
+ struct {
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 invld:1; /* DWORD 0 */
+ u32 dsp:1; /* DWORD 0 */
+ u32 abort:1; /* DWORD 0 */
+ u32 dmsg:1; /* DWORD 0 */
+ u32 wrbindex:8; /* DWORD 0 */
+ u32 wr:1; /* DWORD 0 */
+ u32 lt:1; /* DWORD 0 */
+ u32 lun:14; /* DWORD 0 */
+ u32 rsvd2:4; /* DWORD 1 */
+ u32 sgl_icd_Index:12; /* DWORD 1 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 ptr2NextWrb:8; /* DWORD 1 */
+ u32 cmdsn; /* DWORD 2 */
+ u32 rsvd3:20; /* DWORD 3 */
+ u32 abort_sgl_icd_Index:12; /* DWORD 3 */
+ u32 addr_hi; /* DWORD 4 */
+ u32 addr_lo; /* DWORD 5 */
+ u32 rsvd4[1]; /* DWORDS 6 to 6 */
+ u32 ExpDataXfrLen:24; /* DWORD 7 */
+ u32 len:8; /* DWORD 7 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[8]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_WRB, *PISCSI_INITIATOR_WRB;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_WRB,
+ sizeof(ISCSI_INITIATOR_WRB) == 32); #else
+ /*
+ * [table name="iSCSIWRBInitiator" col="4" delimit=":" caption="iSCSI
+ * Initiator WRB flag details."] iSCSI PDU type : WR : DSP : DMSG
+ * : iSCSI Write command with/without Immediate/unsolicited data
+ * : 1 : 1 : 0 : iSCSI Read command: 0 : 0 : 0 : Text request without
+ * data: 0 : 0 : 0 : Text request with data: 1 : 1 : 0 : Logout
+ * request: 0 : 0 : 0 : NOP OUT with ping data with acknowledgement:
+ * 1 : 1 : 0 : NOP OUT without ping data with acknowledgement: 0
+ * : 0 : 0 : NOP OUT without acknowledgement: 0 : 0 : 1 : NOP OUT
+ * in response to NOP IN from iSCSI target: 0 : 0 : 1 : Task Management
+ * function request: 0 : 0 : 0 : [/table] Note: The logout and
+ * task management response will be notified to host driver by Rx
+ * ULP as part of default ring processing. It is host driver responsibility
+ * to wait for response or time out for these commands to cleanup
+ * related data structures.
+ */
+typedef struct _ISCSI_INITIATOR_WRB {
+ union {
+ struct {
+ u32 lun:14; /* DWORD 0 */
+ u32 lt:1; /* DWORD 0 */
+ u32 wr:1; /* DWORD 0 */
+ u32 wrbindex:8; /* DWORD 0 */
+ u32 dmsg:1; /* DWORD 0 */
+ u32 abort:1; /* DWORD 0 */
+ u32 dsp:1; /* DWORD 0 */
+ u32 invld:1; /* DWORD 0 */
+ u32 rsvd0:4; /* DWORD 0 */
+ u32 ptr2NextWrb:8; /* DWORD 1 */
+ u32 rsvd1:8; /* DWORD 1 */
+ u32 sgl_icd_Index:12; /* DWORD 1 */
+ u32 rsvd2:4; /* DWORD 1 */
+ u32 cmdsn; /* DWORD 2 */
+ u32 abort_sgl_icd_Index:12; /* DWORD 3 */
+ u32 rsvd3:20; /* DWORD 3 */
+ u32 addr_hi; /* DWORD 4 */
+ u32 addr_lo; /* DWORD 5 */
+ u32 rsvd4[1]; /* DWORDS 6 to 6 */
+ u32 len:8; /* DWORD 7 */
+ u32 ExpDataXfrLen:24; /* DWORD 7 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[8]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_INITIATOR_WRB, *PISCSI_INITIATOR_WRB;
+
+SG_C_ASSERT(__sizeof__ISCSI_INITIATOR_WRB,
+ sizeof(ISCSI_INITIATOR_WRB) == 32); #endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_113_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD {
+ u32 rsvd1:5; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:5; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_114_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD {
+ u32 rsvd1:7; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD;
+
+#else
+
+typedef struct _ISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:7; /* DWORD 0 */
+} SG_PACK ISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD,
+ *PISCSI_INITIATOR_HOST_STRUCT_ANON_115_RSVD;
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* DEPRECATE */
+typedef struct _ISCSI_WRB {
+ union {
+ struct {
+ u32 driverMessage:1; /* DWORD 0 */
+ u32 rw_cmd:1; /* DWORD 0 */
+ u32 rsvd1:6; /* DWORD 0 */
+ u32 wrbIndex:8; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 invalidate:1; /* DWORD 0 */
+ u32 opcode:6; /* DWORD 0 */
+ u32 targetLUN:8; /* DWORD 0 */
+ u32 unsolicited_length:16; /* DWORD 1 */
+ u32 rsvd2:8; /* DWORD 1 */
+ u32 ptr2NextWrb:8; /* DWORD 1 */
+ u32 cmd_sn; /* DWORD 2 */
+ u32 exp_stat_sn; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_WRB, *PISCSI_WRB;
+
+SG_C_ASSERT(__sizeof__ISCSI_WRB, sizeof(ISCSI_WRB) == 16);
+
+#else
+ /* DEPRECATE */
+typedef struct _ISCSI_WRB {
+ union {
+ struct {
+ u32 targetLUN:8; /* DWORD 0 */
+ u32 opcode:6; /* DWORD 0 */
+ u32 invalidate:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 wrbIndex:8; /* DWORD 0 */
+ u32 rsvd1:6; /* DWORD 0 */
+ u32 rw_cmd:1; /* DWORD 0 */
+ u32 driverMessage:1; /* DWORD 0 */
+ u32 ptr2NextWrb:8; /* DWORD 1 */
+ u32 rsvd2:8; /* DWORD 1 */
+ u32 unsolicited_length:16; /* DWORD 1 */
+ u32 cmd_sn; /* DWORD 2 */
+ u32 exp_stat_sn; /* DWORD 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK ISCSI_WRB, *PISCSI_WRB;
+
+SG_C_ASSERT(__sizeof__ISCSI_WRB, sizeof(ISCSI_WRB) == 16); #endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __iscsi_initiator_host_struct_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/descriptors_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/descriptors_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/descriptors_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/descriptors_bmap.h 2008-02-14 15:23:07.836201480 +0530
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__descriptors_bmap_h__ #define __descriptors_bmap_h__ #include
+"setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * After a packet is written to the appropriate FIFO, the receive filter
+ * will write an 128bit pseudo-header with the results of the parsing
+ * and checking. This pseudo header is used by the Receive Packet
+ * Processor to determine what command descriptor to generate, and
+ * where to send it
+ */
+typedef struct _RXFILT_D {
+ u32 s:1; /* DWORD 0 */
+ u32 ipsec:1; /* DWORD 0 */
+ u32 dest_id:10; /* DWORD 0 */
+ u32 err:1; /* DWORD 0 */
+ u32 udpcksm:1; /* DWORD 0 */
+ u32 tcpcksm:1; /* DWORD 0 */
+ u32 ipcksm:1; /* DWORD 0 */
+ u32 vtm:1; /* DWORD 0 */
+ u32 l3type:2; /* DWORD 0 */
+ u32 snap:1; /* DWORD 0 */
+ u32 tho:1; /* DWORD 0 */
+ u32 port:1; /* DWORD 0 */
+ u32 vtp:1; /* DWORD 0 */
+ u32 mac_id:6; /* DWORD 0 */
+ u32 ba:1; /* DWORD 0 */
+ u32 ma:1; /* DWORD 0 */
+ u32 ua:1; /* DWORD 0 */
+ u32 ct:2; /* DWORD 1 */
+ u32 len:14; /* DWORD 1 */
+ u32 vtag:16; /* DWORD 1 */
+ u32 mpacrc; /* DWORD 2 */
+ u32 rss_hash; /* DWORD 3 */
+} SG_PACK RXFILT_D, *PRXFILT_D;
+
+#else
+ /*
+ * After a packet is written to the appropriate FIFO, the receive filter
+ * will write an 128bit pseudo-header with the results of the parsing
+ * and checking. This pseudo header is used by the Receive Packet
+ * Processor to determine what command descriptor to generate, and
+ * where to send it
+ */
+typedef struct _RXFILT_D {
+ u32 ua:1; /* DWORD 0 */
+ u32 ma:1; /* DWORD 0 */
+ u32 ba:1; /* DWORD 0 */
+ u32 mac_id:6; /* DWORD 0 */
+ u32 vtp:1; /* DWORD 0 */
+ u32 port:1; /* DWORD 0 */
+ u32 tho:1; /* DWORD 0 */
+ u32 snap:1; /* DWORD 0 */
+ u32 l3type:2; /* DWORD 0 */
+ u32 vtm:1; /* DWORD 0 */
+ u32 ipcksm:1; /* DWORD 0 */
+ u32 tcpcksm:1; /* DWORD 0 */
+ u32 udpcksm:1; /* DWORD 0 */
+ u32 err:1; /* DWORD 0 */
+ u32 dest_id:10; /* DWORD 0 */
+ u32 ipsec:1; /* DWORD 0 */
+ u32 s:1; /* DWORD 0 */
+ u32 vtag:16; /* DWORD 1 */
+ u32 len:14; /* DWORD 1 */
+ u32 ct:2; /* DWORD 1 */
+ u32 mpacrc; /* DWORD 2 */
+ u32 rss_hash; /* DWORD 3 */
+} SG_PACK RXFILT_D, *PRXFILT_D;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __descriptors_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/regmap_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/regmap_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/regmap_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/regmap_bmap.h 2008-02-14 15:23:07.837201328 +0530
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef __regmap_bmap_h__
+#define __regmap_bmap_h__ #include "setypes.h"
+#include "pcicfg_bmap.h"
+#include "ep_bmap.h"
+#include "cev_bmap.h"
+#include "mpu_bmap.h"
+#include "doorbells_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+typedef struct _REGMAP_ANON_110_RSVD {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[255]; /* DWORDS 1 to 255 */
+} SG_PACK REGMAP_ANON_110_RSVD, *PREGMAP_ANON_110_RSVD;
+
+#else
+
+typedef struct _REGMAP_ANON_110_RSVD {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[255]; /* DWORDS 1 to 255 */
+} SG_PACK REGMAP_ANON_110_RSVD, *PREGMAP_ANON_110_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This is the control and status register map for BladeEngine, showing
+ * the relative size and offset of each sub-module. The CSR registers
+ * are identical for the network and storage PCI functions. The
+ * CSR map is shown below, followed by details of each block,
+ * in sub-sections. The sub-sections begin with a description
+ * of CSRs that are instantiated in multiple blocks.
+ */
+typedef struct _BLADE_ENGINE_CSRMAP {
+ MPU_CSRMAP mpu;
+ u32 rsvd0[256]; /* DWORDS 256 to 511 */
+ u32 rsvd1[256]; /* DWORDS 512 to 767 */
+ CEV_CSRMAP cev;
+ u32 rsvd2[256]; /* DWORDS 1024 to 1279 */
+ u32 rsvd3[256]; /* DWORDS 1280 to 1535 */
+ u32 rsvd4[256]; /* DWORDS 1536 to 1791 */
+ u32 rsvd5[256]; /* DWORDS 1792 to 2047 */
+ u32 rsvd6[256]; /* DWORDS 2048 to 2303 */
+ u32 rsvd7[256]; /* DWORDS 2304 to 2559 */
+ u32 rsvd8[256]; /* DWORDS 2560 to 2815 */
+ u32 rsvd9[256]; /* DWORDS 2816 to 3071 */
+ u32 rsvd10[256]; /* DWORDS 3072 to 3327 */
+ u32 rsvd11[256]; /* DWORDS 3328 to 3583 */
+ u32 rsvd12[256]; /* DWORDS 3584 to 3839 */
+ u32 rsvd13[256]; /* DWORDS 3840 to 4095 */
+ u32 rsvd14[256]; /* DWORDS 4096 to 4351 */
+ u32 rsvd15[256]; /* DWORDS 4352 to 4607 */
+ u32 rsvd16[256]; /* DWORDS 4608 to 4863 */
+ u32 rsvd17[256]; /* DWORDS 4864 to 5119 */
+ u32 rsvd18[256]; /* DWORDS 5120 to 5375 */
+ u32 rsvd19[256]; /* DWORDS 5376 to 5631 */
+ u32 rsvd20[256]; /* DWORDS 5632 to 5887 */
+ u32 rsvd21[256]; /* DWORDS 5888 to 6143 */
+ u32 rsvd22[256]; /* DWORDS 6144 to 6399 */
+ u32 rsvd23[17152]; /* DWORDS 6400 to 23551 */
+} SG_PACK BLADE_ENGINE_CSRMAP, *PBLADE_ENGINE_CSRMAP;
+
+#else
+ /*
+ * This is the control and status register map for BladeEngine, showing
+ * the relative size and offset of each sub-module. The CSR registers
+ * are identical for the network and storage PCI functions. The
+ * CSR map is shown below, followed by details of each block,
+ * in sub-sections. The sub-sections begin with a description
+ * of CSRs that are instantiated in multiple blocks.
+ */
+typedef struct _BLADE_ENGINE_CSRMAP {
+ MPU_CSRMAP mpu;
+ u32 rsvd0[256]; /* DWORDS 256 to 511 */
+ u32 rsvd1[256]; /* DWORDS 512 to 767 */
+ CEV_CSRMAP cev;
+ u32 rsvd2[256]; /* DWORDS 1024 to 1279 */
+ u32 rsvd3[256]; /* DWORDS 1280 to 1535 */
+ u32 rsvd4[256]; /* DWORDS 1536 to 1791 */
+ u32 rsvd5[256]; /* DWORDS 1792 to 2047 */
+ u32 rsvd6[256]; /* DWORDS 2048 to 2303 */
+ u32 rsvd7[256]; /* DWORDS 2304 to 2559 */
+ u32 rsvd8[256]; /* DWORDS 2560 to 2815 */
+ u32 rsvd9[256]; /* DWORDS 2816 to 3071 */
+ u32 rsvd10[256]; /* DWORDS 3072 to 3327 */
+ u32 rsvd11[256]; /* DWORDS 3328 to 3583 */
+ u32 rsvd12[256]; /* DWORDS 3584 to 3839 */
+ u32 rsvd13[256]; /* DWORDS 3840 to 4095 */
+ u32 rsvd14[256]; /* DWORDS 4096 to 4351 */
+ u32 rsvd15[256]; /* DWORDS 4352 to 4607 */
+ u32 rsvd16[256]; /* DWORDS 4608 to 4863 */
+ u32 rsvd17[256]; /* DWORDS 4864 to 5119 */
+ u32 rsvd18[256]; /* DWORDS 5120 to 5375 */
+ u32 rsvd19[256]; /* DWORDS 5376 to 5631 */
+ u32 rsvd20[256]; /* DWORDS 5632 to 5887 */
+ u32 rsvd21[256]; /* DWORDS 5888 to 6143 */
+ u32 rsvd22[256]; /* DWORDS 6144 to 6399 */
+ u32 rsvd23[17152]; /* DWORDS 6400 to 23551 */
+} SG_PACK BLADE_ENGINE_CSRMAP, *PBLADE_ENGINE_CSRMAP;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * The Blade Engine storage function (PCI function 0) requires
+ * 32 doorbell pages (up to 32 protection domains).
+ */
+typedef struct _BLADE_ENGINE_PCI0_DBMAP {
+ PROTECTION_DOMAIN_DBMAP pci_func0_protection_domain_dbmap;
+ u32 rsvd0[31744]; /* DWORDS 1024 to 32767 */
+} SG_PACK BLADE_ENGINE_PCI0_DBMAP, *PBLADE_ENGINE_PCI0_DBMAP;
+
+#else
+ /*
+ * The Blade Engine storage function (PCI function 0) requires
+ * 32 doorbell pages (up to 32 protection domains).
+ */
+typedef struct _BLADE_ENGINE_PCI0_DBMAP {
+ PROTECTION_DOMAIN_DBMAP pci_func0_protection_domain_dbmap;
+ u32 rsvd0[31744]; /* DWORDS 1024 to 32767 */
+} SG_PACK BLADE_ENGINE_PCI0_DBMAP, *PBLADE_ENGINE_PCI0_DBMAP;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * The Blade Engine network function (PCI function 1) requires
+ * 543 doorbell pages (up to 32 for protection domain pages and
+ * an additional 511 specific to RDMA).
+ */
+typedef struct _BLADE_ENGINE_PCI1_DBMAP {
+ PROTECTION_DOMAIN_DBMAP pci_func1_protection_domain_dbmap;
+ u32 rsvd0[31744]; /* DWORDS 1024 to 32767 */
+ PROTECTION_DOMAIN_DBMAP
+ pci_func1_protection_domain_dbmap_rdma[511];
+} SG_PACK BLADE_ENGINE_PCI1_DBMAP, *PBLADE_ENGINE_PCI1_DBMAP;
+
+#else
+ /*
+ * The Blade Engine network function (PCI function 1) requires
+ * 543 doorbell pages (up to 32 for protection domain pages and
+ * an additional 511 specific to RDMA).
+ */
+typedef struct _BLADE_ENGINE_PCI1_DBMAP {
+ PROTECTION_DOMAIN_DBMAP pci_func1_protection_domain_dbmap;
+ u32 rsvd0[31744]; /* DWORDS 1024 to 32767 */
+ PROTECTION_DOMAIN_DBMAP
+ pci_func1_protection_domain_dbmap_rdma[511];
+} SG_PACK BLADE_ENGINE_PCI1_DBMAP, *PBLADE_ENGINE_PCI1_DBMAP;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __regmap_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_hdr_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_hdr_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_hdr_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_hdr_bmap.h 2008-02-14 15:23:07.837201328 +0530
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__ioctl_hdr_bmap_h__ #define __ioctl_hdr_bmap_h__ #include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+typedef struct _IOCTL_REQUEST_HEADER {
+ u8 opcode;
+ u8 subsystem;
+ u8 port_number;
+ u8 domain;
+ u32 timeout;
+ u32 request_length;
+ u32 rsvd0;
+} SG_PACK IOCTL_REQUEST_HEADER, *PIOCTL_REQUEST_HEADER;
+
+typedef struct _IOCTL_RESPONSE_HEADER {
+ u8 opcode;
+ u8 subsystem;
+ u8 rsvd0;
+ u8 domain;
+ u8 status;
+ u8 additional_status;
+ u16 rsvd1;
+ u32 response_length;
+ u32 actual_response_length;
+} SG_PACK IOCTL_RESPONSE_HEADER, *PIOCTL_RESPONSE_HEADER;
+
+/*
+ * The firmware/driver overwrites the input IOCTL_REQUEST_HEADER with
+ * the output IOCTL_RESPONSE_HEADER.
+ */
+typedef union _IOCTL_HEADER {
+ IOCTL_REQUEST_HEADER request;
+ IOCTL_RESPONSE_HEADER response;
+} SG_PACK IOCTL_HEADER, *PIOCTL_HEADER;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_hdr_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_top_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_top_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_top_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_top_bmap.h 2008-02-14 15:23:07.837201328 +0530
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__ioctl_top_bmap_h__ #define __ioctl_top_bmap_h__ #include "setypes.h"
+#include "asyncmesg_bmap.h"
+#include "ioctl_types_bmap.h"
+#include "ioctl_mcc_bmap.h"
+#include "ioctl_common_bmap.h"
+#include "ioctl_eth_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_top_bmap_h__ */
___________________________________________________________________________________
This message, together with any attachment(s), contains confidential and proprietary information of
ServerEngines Corporation and is intended only for the designated recipient(s) named above. Any unauthorized
review, printing, retention, copying, disclosure or distribution is strictly prohibited. If you are not the
intended recipient of this message, please immediately advise the sender by reply email message and
delete all copies of this message and any attachment(s). Thank you.
^ permalink raw reply
* [PATHCH 15/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 3:13 UTC (permalink / raw)
To: netdev
F/W header files.
-------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h 2008-02-14 15:23:07.839201024 +0530
@@ -0,0 +1,2333 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __pcicfg_bmap_h__
+#define __pcicfg_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Vendor and Device ID Register. */
+typedef struct _PCICFG_ID_CSR {
+ union {
+ struct {
+ u32 deviceid:16; /* DWORD 0 */
+ u32 vendorid:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ID_CSR, *PPCICFG_ID_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ID_CSR, sizeof(PCICFG_ID_CSR) == 4);
+
+#else
+ /* Vendor and Device ID Register. */
+typedef struct _PCICFG_ID_CSR {
+ union {
+ struct {
+ u32 vendorid:16; /* DWORD 0 */
+ u32 deviceid:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ID_CSR, *PPCICFG_ID_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ID_CSR, sizeof(PCICFG_ID_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* IO Bar Register. */
+typedef struct _PCICFG_IOBAR_CSR {
+ union {
+ struct {
+ u32 iobar:24; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 iospace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_IOBAR_CSR, *PPCICFG_IOBAR_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_IOBAR_CSR, sizeof(PCICFG_IOBAR_CSR) == 4);
+
+#else
+ /* IO Bar Register. */
+typedef struct _PCICFG_IOBAR_CSR {
+ union {
+ struct {
+ u32 iospace:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 iobar:24; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_IOBAR_CSR, *PPCICFG_IOBAR_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_IOBAR_CSR, sizeof(PCICFG_IOBAR_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 0 Register. */
+typedef struct _PCICFG_MEMBAR0_CSR {
+ union {
+ struct {
+ u32 membar0:18; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR0_CSR, *PPCICFG_MEMBAR0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR0_CSR, sizeof(PCICFG_MEMBAR0_CSR) == 4);
+
+#else
+ /* Memory BAR 0 Register. */
+typedef struct _PCICFG_MEMBAR0_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 membar0:18; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR0_CSR, *PPCICFG_MEMBAR0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR0_CSR, sizeof(PCICFG_MEMBAR0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 1 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR1_LO_CSR {
+ union {
+ struct {
+ u32 membar1lo:15; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_LO_CSR, *PPCICFG_MEMBAR1_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_LO_CSR,
+ sizeof(PCICFG_MEMBAR1_LO_CSR) == 4);
+
+#else
+ /* Memory BAR 1 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR1_LO_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 membar1lo:15; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_LO_CSR, *PPCICFG_MEMBAR1_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_LO_CSR,
+ sizeof(PCICFG_MEMBAR1_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 1 - High Address Register. */
+typedef struct _PCICFG_MEMBAR1_HI_CSR {
+ union {
+ struct {
+ u32 membar1hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_HI_CSR, *PPCICFG_MEMBAR1_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_HI_CSR,
+ sizeof(PCICFG_MEMBAR1_HI_CSR) == 4);
+
+#else
+ /* Memory BAR 1 - High Address Register. */
+typedef struct _PCICFG_MEMBAR1_HI_CSR {
+ union {
+ struct {
+ u32 membar1hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_HI_CSR, *PPCICFG_MEMBAR1_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_HI_CSR,
+ sizeof(PCICFG_MEMBAR1_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 2 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR2_LO_CSR {
+ union {
+ struct {
+ u32 membar2lo:11; /* DWORD 0 */
+ u32 rsvd0:17; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_LO_CSR, *PPCICFG_MEMBAR2_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_LO_CSR,
+ sizeof(PCICFG_MEMBAR2_LO_CSR) == 4);
+
+#else
+ /* Memory BAR 2 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR2_LO_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:17; /* DWORD 0 */
+ u32 membar2lo:11; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_LO_CSR, *PPCICFG_MEMBAR2_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_LO_CSR,
+ sizeof(PCICFG_MEMBAR2_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 2 - High Address Register. */
+typedef struct _PCICFG_MEMBAR2_HI_CSR {
+ union {
+ struct {
+ u32 membar2hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_HI_CSR, *PPCICFG_MEMBAR2_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_HI_CSR,
+ sizeof(PCICFG_MEMBAR2_HI_CSR) == 4);
+
+#else
+ /* Memory BAR 2 - High Address Register. */
+typedef struct _PCICFG_MEMBAR2_HI_CSR {
+ union {
+ struct {
+ u32 membar2hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_HI_CSR, *PPCICFG_MEMBAR2_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_HI_CSR,
+ sizeof(PCICFG_MEMBAR2_HI_CSR) == 4);
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Subsystem Vendor and ID (Function 0) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F0_CSR {
+ union {
+ struct {
+ u32 subsys_id:16; /* DWORD 0 */
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F0_CSR, *PPCICFG_SUBSYSTEM_ID_F0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F0_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F0_CSR) == 4);
+
+#else
+ /* Subsystem Vendor and ID (Function 0) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F0_CSR {
+ union {
+ struct {
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ u32 subsys_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F0_CSR, *PPCICFG_SUBSYSTEM_ID_F0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F0_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Subsystem Vendor and ID (Function 1) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F1_CSR {
+ union {
+ struct {
+ u32 subsys_id:16; /* DWORD 0 */
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F1_CSR, *PPCICFG_SUBSYSTEM_ID_F1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F1_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F1_CSR) == 4);
+
+#else
+ /* Subsystem Vendor and ID (Function 1) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F1_CSR {
+ union {
+ struct {
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ u32 subsys_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F1_CSR, *PPCICFG_SUBSYSTEM_ID_F1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F1_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Semaphore Register. */
+typedef struct _PCICFG_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 rsvd0:31; /* DWORD 0 */
+ u32 locked:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SEMAPHORE_CSR, *PPCICFG_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SEMAPHORE_CSR,
+ sizeof(PCICFG_SEMAPHORE_CSR) == 4);
+
+#else
+ /* Semaphore Register. */
+typedef struct _PCICFG_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 locked:1; /* DWORD 0 */
+ u32 rsvd0:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SEMAPHORE_CSR, *PPCICFG_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SEMAPHORE_CSR,
+ sizeof(PCICFG_SEMAPHORE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Soft Reset Register. */
+typedef struct _PCICFG_SOFT_RESET_CSR {
+ union {
+ struct {
+ u32 nec_ll_rcvdetect_i:8; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 softreset:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SOFT_RESET_CSR, *PPCICFG_SOFT_RESET_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SOFT_RESET_CSR,
+ sizeof(PCICFG_SOFT_RESET_CSR) == 4);
+
+#else
+ /* Soft Reset Register. */
+typedef struct _PCICFG_SOFT_RESET_CSR {
+ union {
+ struct {
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 softreset:1; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 nec_ll_rcvdetect_i:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SOFT_RESET_CSR, *PPCICFG_SOFT_RESET_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SOFT_RESET_CSR,
+ sizeof(PCICFG_SOFT_RESET_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Status (Low) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_ue_status:1; /* DWORD 0 */
+ u32 axgmac1_ue_status:1; /* DWORD 0 */
+ u32 axgmac0_ue_status:1; /* DWORD 0 */
+ u32 mbox_stor_ue_status:1; /* DWORD 0 */
+ u32 mbox_netw_ue_status:1; /* DWORD 0 */
+ u32 host_gpio_ue_status:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_status:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_status:1; /* DWORD 0 */
+ u32 host1_ue_status:1; /* DWORD 0 */
+ u32 txulp2_ue_status:1; /* DWORD 0 */
+ u32 wdma_ue_status:1; /* DWORD 0 */
+ u32 uc_ue_status:1; /* DWORD 0 */
+ u32 txulp1_ue_status:1; /* DWORD 0 */
+ u32 txulp0_ue_status:1; /* DWORD 0 */
+ u32 txips_ue_status:1; /* DWORD 0 */
+ u32 tpre_ue_status:1; /* DWORD 0 */
+ u32 tpost_ue_status:1; /* DWORD 0 */
+ u32 tim_ue_status:1; /* DWORD 0 */
+ u32 rxulp2_ue_status:1; /* DWORD 0 */
+ u32 rxulp1_ue_status:1; /* DWORD 0 */
+ u32 rxulp0_ue_status:1; /* DWORD 0 */
+ u32 rxips_ue_status:1; /* DWORD 0 */
+ u32 rxf_ue_status:1; /* DWORD 0 */
+ u32 rdma_ue_status:1; /* DWORD 0 */
+ u32 ptc_ue_status:1; /* DWORD 0 */
+ u32 ndma_ue_status:1; /* DWORD 0 */
+ u32 mpu_ue_status:1; /* DWORD 0 */
+ u32 host_ue_status:1; /* DWORD 0 */
+ u32 erx_ue_status:1; /* DWORD 0 */
+ u32 dbuf_ue_status:1; /* DWORD 0 */
+ u32 ctx_ue_status:1; /* DWORD 0 */
+ u32 cev_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_CSR, *PPCICFG_UE_STATUS_LOW_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Status (Low) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_CSR {
+ union {
+ struct {
+ u32 cev_ue_status:1; /* DWORD 0 */
+ u32 ctx_ue_status:1; /* DWORD 0 */
+ u32 dbuf_ue_status:1; /* DWORD 0 */
+ u32 erx_ue_status:1; /* DWORD 0 */
+ u32 host_ue_status:1; /* DWORD 0 */
+ u32 mpu_ue_status:1; /* DWORD 0 */
+ u32 ndma_ue_status:1; /* DWORD 0 */
+ u32 ptc_ue_status:1; /* DWORD 0 */
+ u32 rdma_ue_status:1; /* DWORD 0 */
+ u32 rxf_ue_status:1; /* DWORD 0 */
+ u32 rxips_ue_status:1; /* DWORD 0 */
+ u32 rxulp0_ue_status:1; /* DWORD 0 */
+ u32 rxulp1_ue_status:1; /* DWORD 0 */
+ u32 rxulp2_ue_status:1; /* DWORD 0 */
+ u32 tim_ue_status:1; /* DWORD 0 */
+ u32 tpost_ue_status:1; /* DWORD 0 */
+ u32 tpre_ue_status:1; /* DWORD 0 */
+ u32 txips_ue_status:1; /* DWORD 0 */
+ u32 txulp0_ue_status:1; /* DWORD 0 */
+ u32 txulp1_ue_status:1; /* DWORD 0 */
+ u32 uc_ue_status:1; /* DWORD 0 */
+ u32 wdma_ue_status:1; /* DWORD 0 */
+ u32 txulp2_ue_status:1; /* DWORD 0 */
+ u32 host1_ue_status:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_status:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_status:1; /* DWORD 0 */
+ u32 host_gpio_ue_status:1; /* DWORD 0 */
+ u32 mbox_netw_ue_status:1; /* DWORD 0 */
+ u32 mbox_stor_ue_status:1; /* DWORD 0 */
+ u32 axgmac0_ue_status:1; /* DWORD 0 */
+ u32 axgmac1_ue_status:1; /* DWORD 0 */
+ u32 mpu_intpend_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_CSR, *PPCICFG_UE_STATUS_LOW_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Status (High) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_ue_status:1; /* DWORD 0 */
+ u32 arm_ue_status:1; /* DWORD 0 */
+ u32 xaui_ue_status:1; /* DWORD 0 */
+ u32 txp_ue_status:1; /* DWORD 0 */
+ u32 txpb_ue_status:1; /* DWORD 0 */
+ u32 rxpp_ue_status:1; /* DWORD 0 */
+ u32 rr_ue_status:1; /* DWORD 0 */
+ u32 pmem_ue_status:1; /* DWORD 0 */
+ u32 pctl1_ue_status:1; /* DWORD 0 */
+ u32 pctl0_ue_status:1; /* DWORD 0 */
+ u32 pcs1online_ue_status:1; /* DWORD 0 */
+ u32 pcs0online_ue_status:1; /* DWORD 0 */
+ u32 mpu_iram_ue_status:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_status:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_status:1; /* DWORD 0 */
+ u32 jtag_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_CSR, *PPCICFG_UE_STATUS_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Status (High) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_CSR {
+ union {
+ struct {
+ u32 jtag_ue_status:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_status:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_status:1; /* DWORD 0 */
+ u32 mpu_iram_ue_status:1; /* DWORD 0 */
+ u32 pcs0online_ue_status:1; /* DWORD 0 */
+ u32 pcs1online_ue_status:1; /* DWORD 0 */
+ u32 pctl0_ue_status:1; /* DWORD 0 */
+ u32 pctl1_ue_status:1; /* DWORD 0 */
+ u32 pmem_ue_status:1; /* DWORD 0 */
+ u32 rr_ue_status:1; /* DWORD 0 */
+ u32 rxpp_ue_status:1; /* DWORD 0 */
+ u32 txpb_ue_status:1; /* DWORD 0 */
+ u32 txp_ue_status:1; /* DWORD 0 */
+ u32 xaui_ue_status:1; /* DWORD 0 */
+ u32 arm_ue_status:1; /* DWORD 0 */
+ u32 ipc_ue_status:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_CSR, *PPCICFG_UE_STATUS_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Mask (Low) Register.<BR> Each bit, when set to
+ * one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_MASK_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_ue_mask:1; /* DWORD 0 */
+ u32 axgmac1_ue_mask:1; /* DWORD 0 */
+ u32 axgmac0_ue_mask:1; /* DWORD 0 */
+ u32 mbox_stor_ue_mask:1; /* DWORD 0 */
+ u32 mbox_netw_ue_mask:1; /* DWORD 0 */
+ u32 host_gpio_ue_mask:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 host1_ue_mask:1; /* DWORD 0 */
+ u32 txulp2_ue_mask:1; /* DWORD 0 */
+ u32 wdma_ue_mask:1; /* DWORD 0 */
+ u32 uc_ue_mask:1; /* DWORD 0 */
+ u32 txulp1_ue_mask:1; /* DWORD 0 */
+ u32 txulp0_ue_mask:1; /* DWORD 0 */
+ u32 txips_ue_mask:1; /* DWORD 0 */
+ u32 tpre_ue_mask:1; /* DWORD 0 */
+ u32 tpost_ue_mask:1; /* DWORD 0 */
+ u32 tim_ue_mask:1; /* DWORD 0 */
+ u32 rxulp2_ue_mask:1; /* DWORD 0 */
+ u32 rxulp1_ue_mask:1; /* DWORD 0 */
+ u32 rxulp0_ue_mask:1; /* DWORD 0 */
+ u32 rxips_ue_mask:1; /* DWORD 0 */
+ u32 rxf_ue_mask:1; /* DWORD 0 */
+ u32 rdma_ue_mask:1; /* DWORD 0 */
+ u32 ptc_ue_mask:1; /* DWORD 0 */
+ u32 ndma_ue_mask:1; /* DWORD 0 */
+ u32 mpu_ue_mask:1; /* DWORD 0 */
+ u32 host_ue_mask:1; /* DWORD 0 */
+ u32 erx_ue_mask:1; /* DWORD 0 */
+ u32 dbuf_ue_mask:1; /* DWORD 0 */
+ u32 ctx_ue_mask:1; /* DWORD 0 */
+ u32 cev_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_MASK_CSR, *PPCICFG_UE_STATUS_LOW_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_MASK_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Mask (Low) Register.<BR> Each bit, when set to
+ * one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_MASK_CSR {
+ union {
+ struct {
+ u32 cev_ue_mask:1; /* DWORD 0 */
+ u32 ctx_ue_mask:1; /* DWORD 0 */
+ u32 dbuf_ue_mask:1; /* DWORD 0 */
+ u32 erx_ue_mask:1; /* DWORD 0 */
+ u32 host_ue_mask:1; /* DWORD 0 */
+ u32 mpu_ue_mask:1; /* DWORD 0 */
+ u32 ndma_ue_mask:1; /* DWORD 0 */
+ u32 ptc_ue_mask:1; /* DWORD 0 */
+ u32 rdma_ue_mask:1; /* DWORD 0 */
+ u32 rxf_ue_mask:1; /* DWORD 0 */
+ u32 rxips_ue_mask:1; /* DWORD 0 */
+ u32 rxulp0_ue_mask:1; /* DWORD 0 */
+ u32 rxulp1_ue_mask:1; /* DWORD 0 */
+ u32 rxulp2_ue_mask:1; /* DWORD 0 */
+ u32 tim_ue_mask:1; /* DWORD 0 */
+ u32 tpost_ue_mask:1; /* DWORD 0 */
+ u32 tpre_ue_mask:1; /* DWORD 0 */
+ u32 txips_ue_mask:1; /* DWORD 0 */
+ u32 txulp0_ue_mask:1; /* DWORD 0 */
+ u32 txulp1_ue_mask:1; /* DWORD 0 */
+ u32 uc_ue_mask:1; /* DWORD 0 */
+ u32 wdma_ue_mask:1; /* DWORD 0 */
+ u32 txulp2_ue_mask:1; /* DWORD 0 */
+ u32 host1_ue_mask:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 host_gpio_ue_mask:1; /* DWORD 0 */
+ u32 mbox_netw_ue_mask:1; /* DWORD 0 */
+ u32 mbox_stor_ue_mask:1; /* DWORD 0 */
+ u32 axgmac0_ue_mask:1; /* DWORD 0 */
+ u32 axgmac1_ue_mask:1; /* DWORD 0 */
+ u32 mpu_intpend_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_MASK_CSR, *PPCICFG_UE_STATUS_LOW_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_MASK_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Mask (High) Register.<BR> Each bit, when set
+ * to one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_MASK_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_ue_mask:1; /* DWORD 0 */
+ u32 arm_ue_mask:1; /* DWORD 0 */
+ u32 xaui_ue_mask:1; /* DWORD 0 */
+ u32 txp_ue_mask:1; /* DWORD 0 */
+ u32 txpb_ue_mask:1; /* DWORD 0 */
+ u32 rxpp_ue_mask:1; /* DWORD 0 */
+ u32 rr_ue_mask:1; /* DWORD 0 */
+ u32 pmem_ue_mask:1; /* DWORD 0 */
+ u32 pctl1_ue_mask:1; /* DWORD 0 */
+ u32 pctl0_ue_mask:1; /* DWORD 0 */
+ u32 pcs1online_ue_mask:1; /* DWORD 0 */
+ u32 pcs0online_ue_mask:1; /* DWORD 0 */
+ u32 mpu_iram_ue_mask:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_mask:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_mask:1; /* DWORD 0 */
+ u32 jtag_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_MASK_CSR, *PPCICFG_UE_STATUS_HI_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_MASK_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Mask (High) Register.<BR> Each bit, when set
+ * to one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_MASK_CSR {
+ union {
+ struct {
+ u32 jtag_ue_mask:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_mask:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_mask:1; /* DWORD 0 */
+ u32 mpu_iram_ue_mask:1; /* DWORD 0 */
+ u32 pcs0online_ue_mask:1; /* DWORD 0 */
+ u32 pcs1online_ue_mask:1; /* DWORD 0 */
+ u32 pctl0_ue_mask:1; /* DWORD 0 */
+ u32 pctl1_ue_mask:1; /* DWORD 0 */
+ u32 pmem_ue_mask:1; /* DWORD 0 */
+ u32 rr_ue_mask:1; /* DWORD 0 */
+ u32 rxpp_ue_mask:1; /* DWORD 0 */
+ u32 txpb_ue_mask:1; /* DWORD 0 */
+ u32 txp_ue_mask:1; /* DWORD 0 */
+ u32 xaui_ue_mask:1; /* DWORD 0 */
+ u32 arm_ue_mask:1; /* DWORD 0 */
+ u32 ipc_ue_mask:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_MASK_CSR, *PPCICFG_UE_STATUS_HI_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_MASK_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE0_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_online:1; /* DWORD 0 */
+ u32 axgmac1_online:1; /* DWORD 0 */
+ u32 axgmac0_online:1; /* DWORD 0 */
+ u32 mbox_stor_online:1; /* DWORD 0 */
+ u32 mbox_netw_online:1; /* DWORD 0 */
+ u32 host_gpio_online:1; /* DWORD 0 */
+ u32 p1_ob_link_online:1; /* DWORD 0 */
+ u32 p0_ob_link_online:1; /* DWORD 0 */
+ u32 host1_online:1; /* DWORD 0 */
+ u32 txulp2_online:1; /* DWORD 0 */
+ u32 wdma_online:1; /* DWORD 0 */
+ u32 uc_online:1; /* DWORD 0 */
+ u32 txulp1_online:1; /* DWORD 0 */
+ u32 txulp0_online:1; /* DWORD 0 */
+ u32 txips_online:1; /* DWORD 0 */
+ u32 tpre_online:1; /* DWORD 0 */
+ u32 tpost_online:1; /* DWORD 0 */
+ u32 tim_online:1; /* DWORD 0 */
+ u32 rxulp2_online:1; /* DWORD 0 */
+ u32 rxulp1_online:1; /* DWORD 0 */
+ u32 rxulp0_online:1; /* DWORD 0 */
+ u32 rxips_online:1; /* DWORD 0 */
+ u32 rxf_online:1; /* DWORD 0 */
+ u32 rdma_online:1; /* DWORD 0 */
+ u32 ptc_online:1; /* DWORD 0 */
+ u32 ndma_online:1; /* DWORD 0 */
+ u32 mpu_online:1; /* DWORD 0 */
+ u32 host_online:1; /* DWORD 0 */
+ u32 erx_online:1; /* DWORD 0 */
+ u32 dbuf_online:1; /* DWORD 0 */
+ u32 ctx_online:1; /* DWORD 0 */
+ u32 cev_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE0_CSR, *PPCICFG_ONLINE0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE0_CSR, sizeof(PCICFG_ONLINE0_CSR) == 4);
+
+#else
+ /*
+ * Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE0_CSR {
+ union {
+ struct {
+ u32 cev_online:1; /* DWORD 0 */
+ u32 ctx_online:1; /* DWORD 0 */
+ u32 dbuf_online:1; /* DWORD 0 */
+ u32 erx_online:1; /* DWORD 0 */
+ u32 host_online:1; /* DWORD 0 */
+ u32 mpu_online:1; /* DWORD 0 */
+ u32 ndma_online:1; /* DWORD 0 */
+ u32 ptc_online:1; /* DWORD 0 */
+ u32 rdma_online:1; /* DWORD 0 */
+ u32 rxf_online:1; /* DWORD 0 */
+ u32 rxips_online:1; /* DWORD 0 */
+ u32 rxulp0_online:1; /* DWORD 0 */
+ u32 rxulp1_online:1; /* DWORD 0 */
+ u32 rxulp2_online:1; /* DWORD 0 */
+ u32 tim_online:1; /* DWORD 0 */
+ u32 tpost_online:1; /* DWORD 0 */
+ u32 tpre_online:1; /* DWORD 0 */
+ u32 txips_online:1; /* DWORD 0 */
+ u32 txulp0_online:1; /* DWORD 0 */
+ u32 txulp1_online:1; /* DWORD 0 */
+ u32 uc_online:1; /* DWORD 0 */
+ u32 wdma_online:1; /* DWORD 0 */
+ u32 txulp2_online:1; /* DWORD 0 */
+ u32 host1_online:1; /* DWORD 0 */
+ u32 p0_ob_link_online:1; /* DWORD 0 */
+ u32 p1_ob_link_online:1; /* DWORD 0 */
+ u32 host_gpio_online:1; /* DWORD 0 */
+ u32 mbox_netw_online:1; /* DWORD 0 */
+ u32 mbox_stor_online:1; /* DWORD 0 */
+ u32 axgmac0_online:1; /* DWORD 0 */
+ u32 axgmac1_online:1; /* DWORD 0 */
+ u32 mpu_intpend_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE0_CSR, *PPCICFG_ONLINE0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE0_CSR, sizeof(PCICFG_ONLINE0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE1_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_online:1; /* DWORD 0 */
+ u32 arm_online:1; /* DWORD 0 */
+ u32 xaui_online:1; /* DWORD 0 */
+ u32 txp_online:1; /* DWORD 0 */
+ u32 txpb_online:1; /* DWORD 0 */
+ u32 rxpp_online:1; /* DWORD 0 */
+ u32 rr_online:1; /* DWORD 0 */
+ u32 pmem_online:1; /* DWORD 0 */
+ u32 pctl1_online:1; /* DWORD 0 */
+ u32 pctl0_online:1; /* DWORD 0 */
+ u32 pcs1online_online:1; /* DWORD 0 */
+ u32 pcs0online_online:1; /* DWORD 0 */
+ u32 mpu_iram_online:1; /* DWORD 0 */
+ u32 mgmt_mac_online:1; /* DWORD 0 */
+ u32 lpcmemhost_online:1; /* DWORD 0 */
+ u32 jtag_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE1_CSR, *PPCICFG_ONLINE1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE1_CSR, sizeof(PCICFG_ONLINE1_CSR) == 4);
+
+#else
+ /*
+ * Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE1_CSR {
+ union {
+ struct {
+ u32 jtag_online:1; /* DWORD 0 */
+ u32 lpcmemhost_online:1; /* DWORD 0 */
+ u32 mgmt_mac_online:1; /* DWORD 0 */
+ u32 mpu_iram_online:1; /* DWORD 0 */
+ u32 pcs0online_online:1; /* DWORD 0 */
+ u32 pcs1online_online:1; /* DWORD 0 */
+ u32 pctl0_online:1; /* DWORD 0 */
+ u32 pctl1_online:1; /* DWORD 0 */
+ u32 pmem_online:1; /* DWORD 0 */
+ u32 rr_online:1; /* DWORD 0 */
+ u32 rxpp_online:1; /* DWORD 0 */
+ u32 txpb_online:1; /* DWORD 0 */
+ u32 txp_online:1; /* DWORD 0 */
+ u32 xaui_online:1; /* DWORD 0 */
+ u32 arm_online:1; /* DWORD 0 */
+ u32 ipc_online:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE1_CSR, *PPCICFG_ONLINE1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE1_CSR, sizeof(PCICFG_ONLINE1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Host Timer Register. */
+typedef struct _PCICFG_HOST_TIMER_INT_CTRL_CSR {
+ union {
+ struct {
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 hostintr:1; /* DWORD 0 */
+ u32 hosttimer:24; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_HOST_TIMER_INT_CTRL_CSR, *PPCICFG_HOST_TIMER_INT_CTRL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_HOST_TIMER_INT_CTRL_CSR,
+ sizeof(PCICFG_HOST_TIMER_INT_CTRL_CSR) == 4);
+
+#else
+ /* Host Timer Register. */
+typedef struct _PCICFG_HOST_TIMER_INT_CTRL_CSR {
+ union {
+ struct {
+ u32 hosttimer:24; /* DWORD 0 */
+ u32 hostintr:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_HOST_TIMER_INT_CTRL_CSR, *PPCICFG_HOST_TIMER_INT_CTRL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_HOST_TIMER_INT_CTRL_CSR,
+ sizeof(PCICFG_HOST_TIMER_INT_CTRL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Scratchpad Register (for software use). */
+typedef struct _PCICFG_SCRATCHPAD_CSR {
+ union {
+ struct {
+ u32 scratchpad; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SCRATCHPAD_CSR, *PPCICFG_SCRATCHPAD_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SCRATCHPAD_CSR,
+ sizeof(PCICFG_SCRATCHPAD_CSR) == 4);
+
+#else
+ /* Scratchpad Register (for software use). */
+typedef struct _PCICFG_SCRATCHPAD_CSR {
+ union {
+ struct {
+ u32 scratchpad; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SCRATCHPAD_CSR, *PPCICFG_SCRATCHPAD_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SCRATCHPAD_CSR,
+ sizeof(PCICFG_SCRATCHPAD_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Capabilities Register. */
+typedef struct _PCICFG_PCIE_CAP_CSR {
+ union {
+ struct {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 devport:4; /* DWORD 0 */
+ u32 capver:4; /* DWORD 0 */
+ u32 nextcap:8; /* DWORD 0 */
+ u32 capid:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CAP_CSR, *PPCICFG_PCIE_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CAP_CSR,
+ sizeof(PCICFG_PCIE_CAP_CSR) == 4);
+
+#else
+ /* PCI Express Capabilities Register. */
+typedef struct _PCICFG_PCIE_CAP_CSR {
+ union {
+ struct {
+ u32 capid:8; /* DWORD 0 */
+ u32 nextcap:8; /* DWORD 0 */
+ u32 capver:4; /* DWORD 0 */
+ u32 devport:4; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CAP_CSR, *PPCICFG_PCIE_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CAP_CSR,
+ sizeof(PCICFG_PCIE_CAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Device Capabilities Register. */
+typedef struct _PCICFG_PCIE_DEVCAP_CSR {
+ union {
+ struct {
+ u32 rsvd3:4; /* DWORD 0 */
+ u32 pwr_scale:2; /* DWORD 0 */
+ u32 pwr_value:8; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 l1_lat:3; /* DWORD 0 */
+ u32 lo_lat:3; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 payload:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_DEVCAP_CSR, *PPCICFG_PCIE_DEVCAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_DEVCAP_CSR,
+ sizeof(PCICFG_PCIE_DEVCAP_CSR) == 4);
+
+#else
+ /* PCI Express Device Capabilities Register. */
+typedef struct _PCICFG_PCIE_DEVCAP_CSR {
+ union {
+ struct {
+ u32 payload:3; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 lo_lat:3; /* DWORD 0 */
+ u32 l1_lat:3; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 pwr_value:8; /* DWORD 0 */
+ u32 pwr_scale:2; /* DWORD 0 */
+ u32 rsvd3:4; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_DEVCAP_CSR, *PPCICFG_PCIE_DEVCAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_DEVCAP_CSR,
+ sizeof(PCICFG_PCIE_DEVCAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Device Control/Status Registers. */
+typedef struct _PCICFG_PCIE_CONTROL_STATUS_CSR {
+ union {
+ struct {
+ u32 rsvd1:10; /* DWORD 0 */
+ u32 TransPending:1; /* DWORD 0 */
+ u32 AuxPwrDetect:1; /* DWORD 0 */
+ u32 UnsuppReqDetect:1; /* DWORD 0 */
+ u32 FatalErrDetect:1; /* DWORD 0 */
+ u32 NonFatalErrDetect:1; /* DWORD 0 */
+ u32 CorrErrDetect:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 Max_Read_Req_Size:3; /* DWORD 0 */
+ u32 EnableNoSnoop:1; /* DWORD 0 */
+ u32 AuxPwrPMEnable:1; /* DWORD 0 */
+ u32 PhantomFnEnable:1; /* DWORD 0 */
+ u32 ExtendTagFieldEnable:1; /* DWORD 0 */
+ u32 Max_Payload_Size:3; /* DWORD 0 */
+ u32 EnableRelaxOrder:1; /* DWORD 0 */
+ u32 UnsuppReqReportEn:1; /* DWORD 0 */
+ u32 FatalErrReportEn:1; /* DWORD 0 */
+ u32 NonFatalErrReportEn:1; /* DWORD 0 */
+ u32 CorrErrReportEn:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CONTROL_STATUS_CSR, *PPCICFG_PCIE_CONTROL_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CONTROL_STATUS_CSR,
+ sizeof(PCICFG_PCIE_CONTROL_STATUS_CSR) == 4);
+
+#else
+ /* PCI Express Device Control/Status Registers. */
+typedef struct _PCICFG_PCIE_CONTROL_STATUS_CSR {
+ union {
+ struct {
+ u32 CorrErrReportEn:1; /* DWORD 0 */
+ u32 NonFatalErrReportEn:1; /* DWORD 0 */
+ u32 FatalErrReportEn:1; /* DWORD 0 */
+ u32 UnsuppReqReportEn:1; /* DWORD 0 */
+ u32 EnableRelaxOrder:1; /* DWORD 0 */
+ u32 Max_Payload_Size:3; /* DWORD 0 */
+ u32 ExtendTagFieldEnable:1; /* DWORD 0 */
+ u32 PhantomFnEnable:1; /* DWORD 0 */
+ u32 AuxPwrPMEnable:1; /* DWORD 0 */
+ u32 EnableNoSnoop:1; /* DWORD 0 */
+ u32 Max_Read_Req_Size:3; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 CorrErrDetect:1; /* DWORD 0 */
+ u32 NonFatalErrDetect:1; /* DWORD 0 */
+ u32 FatalErrDetect:1; /* DWORD 0 */
+ u32 UnsuppReqDetect:1; /* DWORD 0 */
+ u32 AuxPwrDetect:1; /* DWORD 0 */
+ u32 TransPending:1; /* DWORD 0 */
+ u32 rsvd1:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CONTROL_STATUS_CSR, *PPCICFG_PCIE_CONTROL_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CONTROL_STATUS_CSR,
+ sizeof(PCICFG_PCIE_CONTROL_STATUS_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Link Capabilities Register. */
+typedef struct _PCICFG_PCIE_LINK_CAP_CSR {
+ union {
+ struct {
+ u32 PortNum:8; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 L1ExitLat:3; /* DWORD 0 */
+ u32 L0sExitLat:3; /* DWORD 0 */
+ u32 ASPMSupport:2; /* DWORD 0 */
+ u32 MaxLinkWidth:6; /* DWORD 0 */
+ u32 MaxLinkSpeed:4; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_CAP_CSR, *PPCICFG_PCIE_LINK_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_CAP_CSR,
+ sizeof(PCICFG_PCIE_LINK_CAP_CSR) == 4);
+
+#else
+ /* PCI Express Link Capabilities Register. */
+typedef struct _PCICFG_PCIE_LINK_CAP_CSR {
+ union {
+ struct {
+ u32 MaxLinkSpeed:4; /* DWORD 0 */
+ u32 MaxLinkWidth:6; /* DWORD 0 */
+ u32 ASPMSupport:2; /* DWORD 0 */
+ u32 L0sExitLat:3; /* DWORD 0 */
+ u32 L1ExitLat:3; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 PortNum:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_CAP_CSR, *PPCICFG_PCIE_LINK_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_CAP_CSR,
+ sizeof(PCICFG_PCIE_LINK_CAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Link Status Register. */
+typedef struct _PCICFG_PCIE_LINK_STATUS_CSR {
+ union {
+ struct {
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 SlotClkConfig:1; /* DWORD 0 */
+ u32 LinkTrain:1; /* DWORD 0 */
+ u32 LinkTrainErr:1; /* DWORD 0 */
+ u32 NegLinkWidth:6; /* DWORD 0 */
+ u32 LinkSpeed:4; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 ExtendSync:1; /* DWORD 0 */
+ u32 CommonClkConfig:1; /* DWORD 0 */
+ u32 RetrainLink:1; /* DWORD 0 */
+ u32 LinkDisable:1; /* DWORD 0 */
+ u32 ReadCmplBndry:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 ASPMCtl:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_STATUS_CSR, *PPCICFG_PCIE_LINK_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_STATUS_CSR,
+ sizeof(PCICFG_PCIE_LINK_STATUS_CSR) == 4);
+
+#else
+ /* PCI Express Link Status Register. */
+typedef struct _PCICFG_PCIE_LINK_STATUS_CSR {
+ union {
+ struct {
+ u32 ASPMCtl:2; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 ReadCmplBndry:1; /* DWORD 0 */
+ u32 LinkDisable:1; /* DWORD 0 */
+ u32 RetrainLink:1; /* DWORD 0 */
+ u32 CommonClkConfig:1; /* DWORD 0 */
+ u32 ExtendSync:1; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 LinkSpeed:4; /* DWORD 0 */
+ u32 NegLinkWidth:6; /* DWORD 0 */
+ u32 LinkTrainErr:1; /* DWORD 0 */
+ u32 LinkTrain:1; /* DWORD 0 */
+ u32 SlotClkConfig:1; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_STATUS_CSR, *PPCICFG_PCIE_LINK_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_STATUS_CSR,
+ sizeof(PCICFG_PCIE_LINK_STATUS_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI Configuration Register. */
+typedef struct _PCICFG_MSI_CSR {
+ union {
+ struct {
+ u32 en:1; /* DWORD 0 */
+ u32 funcmask:1; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 tablesize:11; /* DWORD 0 */
+ u32 nextptr:8; /* DWORD 0 */
+ u32 capid:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSI_CSR, *PPCICFG_MSI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSI_CSR, sizeof(PCICFG_MSI_CSR) == 4);
+
+#else
+ /* PCI Express MSI Configuration Register. */
+typedef struct _PCICFG_MSI_CSR {
+ union {
+ struct {
+ u32 capid:8; /* DWORD 0 */
+ u32 nextptr:8; /* DWORD 0 */
+ u32 tablesize:11; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 funcmask:1; /* DWORD 0 */
+ u32 en:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSI_CSR, *PPCICFG_MSI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSI_CSR, sizeof(PCICFG_MSI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* MSI-X Table Offset Register. */
+typedef struct _PCICFG_MSIX_TABLE_CSR {
+ union {
+ struct {
+ u32 offset:29; /* DWORD 0 */
+ u32 tablebir:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_TABLE_CSR, *PPCICFG_MSIX_TABLE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_TABLE_CSR,
+ sizeof(PCICFG_MSIX_TABLE_CSR) == 4);
+
+#else
+ /* MSI-X Table Offset Register. */
+typedef struct _PCICFG_MSIX_TABLE_CSR {
+ union {
+ struct {
+ u32 tablebir:3; /* DWORD 0 */
+ u32 offset:29; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_TABLE_CSR, *PPCICFG_MSIX_TABLE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_TABLE_CSR,
+ sizeof(PCICFG_MSIX_TABLE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* MSI-X PBA Offset Register. */
+typedef struct _PCICFG_MSIX_PBA_CSR {
+ union {
+ struct {
+ u32 offset:29; /* DWORD 0 */
+ u32 pbabir:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_PBA_CSR, *PPCICFG_MSIX_PBA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_PBA_CSR,
+ sizeof(PCICFG_MSIX_PBA_CSR) == 4);
+
+#else
+ /* MSI-X PBA Offset Register. */
+typedef struct _PCICFG_MSIX_PBA_CSR {
+ union {
+ struct {
+ u32 pbabir:3; /* DWORD 0 */
+ u32 offset:29; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_PBA_CSR, *PPCICFG_MSIX_PBA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_PBA_CSR,
+ sizeof(PCICFG_MSIX_PBA_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Vector Control Register. */
+typedef struct _PCICFG_MSIX_VECTOR_CONTROL_CSR {
+ union {
+ struct {
+ u32 rsvd0:31; /* DWORD 0 */
+ u32 vector_control:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_VECTOR_CONTROL_CSR, *PPCICFG_MSIX_VECTOR_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_VECTOR_CONTROL_CSR,
+ sizeof(PCICFG_MSIX_VECTOR_CONTROL_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Vector Control Register. */
+typedef struct _PCICFG_MSIX_VECTOR_CONTROL_CSR {
+ union {
+ struct {
+ u32 vector_control:1; /* DWORD 0 */
+ u32 rsvd0:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_VECTOR_CONTROL_CSR, *PPCICFG_MSIX_VECTOR_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_VECTOR_CONTROL_CSR,
+ sizeof(PCICFG_MSIX_VECTOR_CONTROL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Data Register. */
+typedef struct _PCICFG_MSIX_MSG_DATA_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 data:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_DATA_CSR, *PPCICFG_MSIX_MSG_DATA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_DATA_CSR,
+ sizeof(PCICFG_MSIX_MSG_DATA_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Data Register. */
+typedef struct _PCICFG_MSIX_MSG_DATA_CSR {
+ union {
+ struct {
+ u32 data:16; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_DATA_CSR, *PPCICFG_MSIX_MSG_DATA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_DATA_CSR,
+ sizeof(PCICFG_MSIX_MSG_DATA_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Address Register - High Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_HI_CSR {
+ union {
+ struct {
+ u32 addr; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_HI_CSR, *PPCICFG_MSIX_MSG_ADDR_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_HI_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_HI_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Address Register - High Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_HI_CSR {
+ union {
+ struct {
+ u32 addr; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_HI_CSR, *PPCICFG_MSIX_MSG_ADDR_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_HI_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Address Register - Low Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_LO_CSR {
+ union {
+ struct {
+ u32 addr:30; /* DWORD 0 */
+ u32 rsvd0:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_LO_CSR, *PPCICFG_MSIX_MSG_ADDR_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_LO_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_LO_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Address Register - Low Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_LO_CSR {
+ union {
+ struct {
+ u32 rsvd0:2; /* DWORD 0 */
+ u32 addr:30; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_LO_CSR, *PPCICFG_MSIX_MSG_ADDR_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_LO_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_18_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_18_RSVD, *PPCICFG_ANON_18_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_18_RSVD,
+ sizeof(PCICFG_ANON_18_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_18_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_18_RSVD, *PPCICFG_ANON_18_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_18_RSVD,
+ sizeof(PCICFG_ANON_18_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_19_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_19_RSVD, *PPCICFG_ANON_19_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_19_RSVD,
+ sizeof(PCICFG_ANON_19_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_19_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_19_RSVD, *PPCICFG_ANON_19_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_19_RSVD,
+ sizeof(PCICFG_ANON_19_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_20_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[25]; /* DWORDS 1 to 25 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[26]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_20_RSVD, *PPCICFG_ANON_20_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_20_RSVD,
+ sizeof(PCICFG_ANON_20_RSVD) == 104);
+
+#else
+
+typedef struct _PCICFG_ANON_20_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[25]; /* DWORDS 1 to 25 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[26]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_20_RSVD, *PPCICFG_ANON_20_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_20_RSVD,
+ sizeof(PCICFG_ANON_20_RSVD) == 104);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_21_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1919]; /* DWORDS 1 to 1919 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1920]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_21_RSVD, *PPCICFG_ANON_21_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_21_RSVD,
+ sizeof(PCICFG_ANON_21_RSVD) == 7680);
+
+#else
+
+typedef struct _PCICFG_ANON_21_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1919]; /* DWORDS 1 to 1919 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1920]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_21_RSVD, *PPCICFG_ANON_21_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_21_RSVD,
+ sizeof(PCICFG_ANON_21_RSVD) == 7680);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_22_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_22_MESSAGE, *PPCICFG_ANON_22_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_22_MESSAGE,
+ sizeof(PCICFG_ANON_22_MESSAGE) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_22_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_22_MESSAGE, *PPCICFG_ANON_22_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_22_MESSAGE,
+ sizeof(PCICFG_ANON_22_MESSAGE) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_23_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_23_RSVD, *PPCICFG_ANON_23_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_23_RSVD,
+ sizeof(PCICFG_ANON_23_RSVD) == 3584);
+
+#else
+
+typedef struct _PCICFG_ANON_23_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_23_RSVD, *PPCICFG_ANON_23_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_23_RSVD,
+ sizeof(PCICFG_ANON_23_RSVD) == 3584);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * These PCI Configuration Space registers are for the Storage Function
+ * of BladeEngine (Function 0). In the memory map of the registers
+ * below their table, registers that are physically common to Functions
+ * 0 and 1 are highlighted in pink.<BR> under the mnemonic column.
+ *
+ */
+typedef struct _PCICFG0_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F0_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[1]; /* DWORDS 60 to 60 */
+ u32 rsvd24[1]; /* DWORDS 61 to 61 */
+ u32 rsvd25[1]; /* DWORDS 62 to 62 */
+ u32 rsvd26[1]; /* DWORDS 63 to 63 */
+ u32 rsvd27[1]; /* DWORDS 64 to 64 */
+ u32 rsvd28[1]; /* DWORDS 65 to 65 */
+ u32 rsvd29[1]; /* DWORDS 66 to 66 */
+ u32 rsvd30[1]; /* DWORDS 67 to 67 */
+ u32 rsvd31[1]; /* DWORDS 68 to 68 */
+ u32 rsvd32[1]; /* DWORDS 69 to 69 */
+ u32 rsvd33[1]; /* DWORDS 70 to 70 */
+ u32 rsvd34[1]; /* DWORDS 71 to 71 */
+ u32 rsvd35[1]; /* DWORDS 72 to 72 */
+ u32 rsvd36[1]; /* DWORDS 73 to 73 */
+ u32 rsvd37[1]; /* DWORDS 74 to 74 */
+ u32 rsvd38[1]; /* DWORDS 75 to 75 */
+ u32 rsvd39[1]; /* DWORDS 76 to 76 */
+ u32 rsvd40[1]; /* DWORDS 77 to 77 */
+ u32 rsvd41[1]; /* DWORDS 78 to 78 */
+ u32 rsvd42[1]; /* DWORDS 79 to 79 */
+ u32 rsvd43[1]; /* DWORDS 80 to 80 */
+ u32 rsvd44[1]; /* DWORDS 81 to 81 */
+ u32 rsvd45[1]; /* DWORDS 82 to 82 */
+ u32 rsvd46[1]; /* DWORDS 83 to 83 */
+ u32 rsvd47[1]; /* DWORDS 84 to 84 */
+ u32 rsvd48[1]; /* DWORDS 85 to 85 */
+ u32 rsvd49[1]; /* DWORDS 86 to 86 */
+ u32 rsvd50[1]; /* DWORDS 87 to 87 */
+ u32 rsvd51[1]; /* DWORDS 88 to 88 */
+ u32 rsvd52[1]; /* DWORDS 89 to 89 */
+ u32 rsvd53[1]; /* DWORDS 90 to 90 */
+ u32 rsvd54[1]; /* DWORDS 91 to 91 */
+ u32 rsvd55[1]; /* DWORDS 92 to 92 */
+ u32 rsvd56[26]; /* DWORDS 93 to 118 */
+ u32 rsvd57[1]; /* DWORDS 119 to 119 */
+ u32 rsvd58[1]; /* DWORDS 120 to 120 */
+ u32 rsvd59[1]; /* DWORDS 121 to 121 */
+ u32 rsvd60[1]; /* DWORDS 122 to 122 */
+ u32 rsvd61[1]; /* DWORDS 123 to 123 */
+ u32 rsvd62[1]; /* DWORDS 124 to 124 */
+ u32 rsvd63[1]; /* DWORDS 125 to 125 */
+ u32 rsvd64[1]; /* DWORDS 126 to 126 */
+ u32 rsvd65[1]; /* DWORDS 127 to 127 */
+ u32 rsvd66[1920]; /* DWORDS 128 to 2047 */
+ PCICFG_ANON_22_MESSAGE message[32];
+ u32 rsvd67[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd68[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd69[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG0_CSRMAP, *PPCICFG0_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG0_CSRMAP, sizeof(PCICFG0_CSRMAP) == 16384);
+
+#else
+ /*
+ * These PCI Configuration Space registers are for the Storage Function
+ * of BladeEngine (Function 0). In the memory map of the registers
+ * below their table, registers that are physically common to Functions
+ * 0 and 1 are highlighted in pink.<BR> under the mnemonic column.
+ *
+ */
+typedef struct _PCICFG0_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F0_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[1]; /* DWORDS 60 to 60 */
+ u32 rsvd24[1]; /* DWORDS 61 to 61 */
+ u32 rsvd25[1]; /* DWORDS 62 to 62 */
+ u32 rsvd26[1]; /* DWORDS 63 to 63 */
+ u32 rsvd27[1]; /* DWORDS 64 to 64 */
+ u32 rsvd28[1]; /* DWORDS 65 to 65 */
+ u32 rsvd29[1]; /* DWORDS 66 to 66 */
+ u32 rsvd30[1]; /* DWORDS 67 to 67 */
+ u32 rsvd31[1]; /* DWORDS 68 to 68 */
+ u32 rsvd32[1]; /* DWORDS 69 to 69 */
+ u32 rsvd33[1]; /* DWORDS 70 to 70 */
+ u32 rsvd34[1]; /* DWORDS 71 to 71 */
+ u32 rsvd35[1]; /* DWORDS 72 to 72 */
+ u32 rsvd36[1]; /* DWORDS 73 to 73 */
+ u32 rsvd37[1]; /* DWORDS 74 to 74 */
+ u32 rsvd38[1]; /* DWORDS 75 to 75 */
+ u32 rsvd39[1]; /* DWORDS 76 to 76 */
+ u32 rsvd40[1]; /* DWORDS 77 to 77 */
+ u32 rsvd41[1]; /* DWORDS 78 to 78 */
+ u32 rsvd42[1]; /* DWORDS 79 to 79 */
+ u32 rsvd43[1]; /* DWORDS 80 to 80 */
+ u32 rsvd44[1]; /* DWORDS 81 to 81 */
+ u32 rsvd45[1]; /* DWORDS 82 to 82 */
+ u32 rsvd46[1]; /* DWORDS 83 to 83 */
+ u32 rsvd47[1]; /* DWORDS 84 to 84 */
+ u32 rsvd48[1]; /* DWORDS 85 to 85 */
+ u32 rsvd49[1]; /* DWORDS 86 to 86 */
+ u32 rsvd50[1]; /* DWORDS 87 to 87 */
+ u32 rsvd51[1]; /* DWORDS 88 to 88 */
+ u32 rsvd52[1]; /* DWORDS 89 to 89 */
+ u32 rsvd53[1]; /* DWORDS 90 to 90 */
+ u32 rsvd54[1]; /* DWORDS 91 to 91 */
+ u32 rsvd55[1]; /* DWORDS 92 to 92 */
+ u32 rsvd56[26]; /* DWORDS 93 to 118 */
+ u32 rsvd57[1]; /* DWORDS 119 to 119 */
+ u32 rsvd58[1]; /* DWORDS 120 to 120 */
+ u32 rsvd59[1]; /* DWORDS 121 to 121 */
+ u32 rsvd60[1]; /* DWORDS 122 to 122 */
+ u32 rsvd61[1]; /* DWORDS 123 to 123 */
+ u32 rsvd62[1]; /* DWORDS 124 to 124 */
+ u32 rsvd63[1]; /* DWORDS 125 to 125 */
+ u32 rsvd64[1]; /* DWORDS 126 to 126 */
+ u32 rsvd65[1]; /* DWORDS 127 to 127 */
+ u32 rsvd66[1920]; /* DWORDS 128 to 2047 */
+ PCICFG_ANON_22_MESSAGE message[32];
+ u32 rsvd67[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd68[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd69[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG0_CSRMAP, *PPCICFG0_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG0_CSRMAP, sizeof(PCICFG0_CSRMAP) == 16384);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_24_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_24_RSVD, *PPCICFG_ANON_24_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_24_RSVD,
+ sizeof(PCICFG_ANON_24_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_24_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_24_RSVD, *PPCICFG_ANON_24_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_24_RSVD,
+ sizeof(PCICFG_ANON_24_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_25_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_25_RSVD, *PPCICFG_ANON_25_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_25_RSVD,
+ sizeof(PCICFG_ANON_25_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_25_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_25_RSVD, *PPCICFG_ANON_25_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_25_RSVD,
+ sizeof(PCICFG_ANON_25_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_26_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_26_RSVD, *PPCICFG_ANON_26_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_26_RSVD,
+ sizeof(PCICFG_ANON_26_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_26_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_26_RSVD, *PPCICFG_ANON_26_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_26_RSVD,
+ sizeof(PCICFG_ANON_26_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_27_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_27_RSVD, *PPCICFG_ANON_27_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_27_RSVD,
+ sizeof(PCICFG_ANON_27_RSVD) == 8);
+
+#else
+
+typedef struct _PCICFG_ANON_27_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_27_RSVD, *PPCICFG_ANON_27_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_27_RSVD,
+ sizeof(PCICFG_ANON_27_RSVD) == 8);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_28_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[3]; /* DWORDS 1 to 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_28_RSVD, *PPCICFG_ANON_28_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_28_RSVD,
+ sizeof(PCICFG_ANON_28_RSVD) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_28_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[3]; /* DWORDS 1 to 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_28_RSVD, *PPCICFG_ANON_28_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_28_RSVD,
+ sizeof(PCICFG_ANON_28_RSVD) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_29_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[36]; /* DWORDS 1 to 36 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[37]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_29_RSVD, *PPCICFG_ANON_29_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_29_RSVD,
+ sizeof(PCICFG_ANON_29_RSVD) == 148);
+
+#else
+
+typedef struct _PCICFG_ANON_29_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[36]; /* DWORDS 1 to 36 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[37]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_29_RSVD, *PPCICFG_ANON_29_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_29_RSVD,
+ sizeof(PCICFG_ANON_29_RSVD) == 148);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_30_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1930]; /* DWORDS 1 to 1930 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1931]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_30_RSVD, *PPCICFG_ANON_30_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_30_RSVD,
+ sizeof(PCICFG_ANON_30_RSVD) == 7724);
+
+#else
+
+typedef struct _PCICFG_ANON_30_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1930]; /* DWORDS 1 to 1930 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1931]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_30_RSVD, *PPCICFG_ANON_30_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_30_RSVD,
+ sizeof(PCICFG_ANON_30_RSVD) == 7724);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_31_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_31_MESSAGE, *PPCICFG_ANON_31_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_31_MESSAGE,
+ sizeof(PCICFG_ANON_31_MESSAGE) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_31_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_31_MESSAGE, *PPCICFG_ANON_31_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_31_MESSAGE,
+ sizeof(PCICFG_ANON_31_MESSAGE) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_32_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_32_RSVD, *PPCICFG_ANON_32_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_32_RSVD,
+ sizeof(PCICFG_ANON_32_RSVD) == 3584);
+
+#else
+
+typedef struct _PCICFG_ANON_32_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_32_RSVD, *PPCICFG_ANON_32_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_32_RSVD,
+ sizeof(PCICFG_ANON_32_RSVD) == 3584);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This PCI configuration space register map is for the Networking Function
+ * of BladeEngine (Function 1). For more detailed descriptions of
+ * the fields below click the link under the mnemonic column. Registers
+ * highlighted in pink color are physically shared between both
+ * Functions (0 and 1).
+ */
+typedef struct _PCICFG1_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F1_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[2]; /* DWORDS 60 to 61 */
+ u32 rsvd24[1]; /* DWORDS 62 to 62 */
+ u32 rsvd25[1]; /* DWORDS 63 to 63 */
+ u32 rsvd26[1]; /* DWORDS 64 to 64 */
+ u32 rsvd27[1]; /* DWORDS 65 to 65 */
+ u32 rsvd28[1]; /* DWORDS 66 to 66 */
+ u32 rsvd29[1]; /* DWORDS 67 to 67 */
+ u32 rsvd30[1]; /* DWORDS 68 to 68 */
+ u32 rsvd31[1]; /* DWORDS 69 to 69 */
+ u32 rsvd32[1]; /* DWORDS 70 to 70 */
+ u32 rsvd33[1]; /* DWORDS 71 to 71 */
+ u32 rsvd34[1]; /* DWORDS 72 to 72 */
+ u32 rsvd35[1]; /* DWORDS 73 to 73 */
+ u32 rsvd36[1]; /* DWORDS 74 to 74 */
+ u32 rsvd37[4]; /* DWORDS 75 to 78 */
+ u32 rsvd38[1]; /* DWORDS 79 to 79 */
+ u32 rsvd39[37]; /* DWORDS 80 to 116 */
+ u32 rsvd40[1931]; /* DWORDS 117 to 2047 */
+ PCICFG_ANON_31_MESSAGE message[32];
+ u32 rsvd41[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd42[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd43[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG1_CSRMAP, *PPCICFG1_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG1_CSRMAP, sizeof(PCICFG1_CSRMAP) == 16384);
+
+#else
+ /*
+ * This PCI configuration space register map is for the Networking Function
+ * of BladeEngine (Function 1). For more detailed descriptions of
+ * the fields below click the link under the mnemonic column. Registers
+ * highlighted in pink color are physically shared between both
+ * Functions (0 and 1).
+ */
+typedef struct _PCICFG1_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F1_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[2]; /* DWORDS 60 to 61 */
+ u32 rsvd24[1]; /* DWORDS 62 to 62 */
+ u32 rsvd25[1]; /* DWORDS 63 to 63 */
+ u32 rsvd26[1]; /* DWORDS 64 to 64 */
+ u32 rsvd27[1]; /* DWORDS 65 to 65 */
+ u32 rsvd28[1]; /* DWORDS 66 to 66 */
+ u32 rsvd29[1]; /* DWORDS 67 to 67 */
+ u32 rsvd30[1]; /* DWORDS 68 to 68 */
+ u32 rsvd31[1]; /* DWORDS 69 to 69 */
+ u32 rsvd32[1]; /* DWORDS 70 to 70 */
+ u32 rsvd33[1]; /* DWORDS 71 to 71 */
+ u32 rsvd34[1]; /* DWORDS 72 to 72 */
+ u32 rsvd35[1]; /* DWORDS 73 to 73 */
+ u32 rsvd36[1]; /* DWORDS 74 to 74 */
+ u32 rsvd37[4]; /* DWORDS 75 to 78 */
+ u32 rsvd38[1]; /* DWORDS 79 to 79 */
+ u32 rsvd39[37]; /* DWORDS 80 to 116 */
+ u32 rsvd40[1931]; /* DWORDS 117 to 2047 */
+ PCICFG_ANON_31_MESSAGE message[32];
+ u32 rsvd41[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd42[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd43[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG1_CSRMAP, *PPCICFG1_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG1_CSRMAP, sizeof(PCICFG1_CSRMAP) == 16384);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __pcicfg_bmap_h__ */
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* [PATHCH 16/16] ServerEngines 10Gb NIC driver
From: Subbu Seetharaman @ 2008-02-17 3:36 UTC (permalink / raw)
To: netdev
F/W header files.
-----------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_common_host_struct_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_common_host_struct_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_common_host_struct_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/iscsi_common_host_struct_bmap.h 2008-02-14 15:23:07.840200872 +0530
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__iscsi_common_host_struct_bmap_h__
+#define __iscsi_common_host_struct_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD {
+ u32 rsvd1:10; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:10; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_37_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD {
+ u32 rsvd1:15; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:15; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_38_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Scatter gather element */
+typedef struct _ISCSI_SGE {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+ u32 last_sge:1; /* DWORD 2 */
+ u32 rsvd0:11; /* DWORD 2 */
+ u32 sge_offset:20; /* DWORD 2 */
+ u32 rsvd1:16; /* DWORD 3 */
+ u32 len:16; /* DWORD 3 */
+} SG_PACK ISCSI_SGE, *PISCSI_SGE;
+
+#else
+ /* Scatter gather element */
+typedef struct _ISCSI_SGE {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+ u32 sge_offset:20; /* DWORD 2 */
+ u32 rsvd0:11; /* DWORD 2 */
+ u32 last_sge:1; /* DWORD 2 */
+ u32 len:16; /* DWORD 3 */
+ u32 rsvd1:16; /* DWORD 3 */
+} SG_PACK ISCSI_SGE, *PISCSI_SGE;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Scatter gather element to DMA OOO segments */ typedef struct
+_ISCSI_OOO_SGE {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+} SG_PACK ISCSI_OOO_SGE, *PISCSI_OOO_SGE;
+
+#else
+ /* Scatter gather element to DMA OOO segments */ typedef struct
+_ISCSI_OOO_SGE {
+ u32 addr_hi; /* DWORD 0 */
+ u32 addr_lo; /* DWORD 1 */
+} SG_PACK ISCSI_OOO_SGE, *PISCSI_OOO_SGE;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_39_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* RRmsg sent from ARM to iSCSI TXULP and carried as body of IPC
+ * between EPs */
+typedef struct _ISCSI_RRMSG {
+ u32 invalidate_ref_handle:16; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 chuteid:1; /* DWORD 0 */
+ u32 defpdu_invld:1; /* DWORD 0 */
+ u32 sgl_icd_Index:11; /* DWORD 0 */
+ u32 partialBytesSent:24; /* DWORD 1 */
+ u32 upload:1; /* DWORD 1 */
+ u32 rstonneed:1; /* DWORD 1 */
+ u32 invld_resp:1; /* DWORD 1 */
+ u32 wr:1; /* DWORD 1 */
+ u32 iscsicon_rst:1; /* DWORD 1 */
+ u32 icd_free:1; /* DWORD 1 */
+ u32 icd_invld:1; /* DWORD 1 */
+ u32 iscsicon_invld:1; /* DWORD 1 */
+} SG_PACK ISCSI_RRMSG, *PISCSI_RRMSG;
+
+#else
+ /* RRmsg sent from ARM to iSCSI TXULP and carried as body of IPC
+ * between EPs */
+typedef struct _ISCSI_RRMSG {
+ u32 sgl_icd_Index:11; /* DWORD 0 */
+ u32 defpdu_invld:1; /* DWORD 0 */
+ u32 chuteid:1; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 invalidate_ref_handle:16; /* DWORD 0 */
+ u32 iscsicon_invld:1; /* DWORD 1 */
+ u32 icd_invld:1; /* DWORD 1 */
+ u32 icd_free:1; /* DWORD 1 */
+ u32 iscsicon_rst:1; /* DWORD 1 */
+ u32 wr:1; /* DWORD 1 */
+ u32 invld_resp:1; /* DWORD 1 */
+ u32 rstonneed:1; /* DWORD 1 */
+ u32 upload:1; /* DWORD 1 */
+ u32 partialBytesSent:24; /* DWORD 1 */
+} SG_PACK ISCSI_RRMSG, *PISCSI_RRMSG;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Full 8 byte LUN. */
+typedef struct _ISCSI_LUN {
+ u8 bytes[8];
+} SG_PACK ISCSI_LUN, *PISCSI_LUN;
+
+#else
+ /* Full 8 byte LUN. */
+typedef struct _ISCSI_LUN {
+ u8 bytes[8];
+} SG_PACK ISCSI_LUN, *PISCSI_LUN;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_40_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD {
+ u32 rsvd1:7; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:7; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_41_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD;
+
+#else
+
+typedef struct _ISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+} SG_PACK ISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD,
+ *PISCSI_COMMON_HOST_STRUCT_ANON_42_RSVD;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* ISCSI Default PDU Context latest */ typedef struct
+_ISCSI_DEFAULT_PDU_CONTEXT {
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 ring_size:4; /* DWORD 0 */
+ u32 ring_state:4; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 dbuf_cindex:13; /* DWORD 0 */
+ u32 cq_id_recv:10; /* DWORD 1 */
+ u32 rx_pdid_not_valid:1; /* DWORD 1 */
+ u32 rx_pdid:5; /* DWORD 1 */
+ u32 rsvd2:3; /* DWORD 1 */
+ u32 dbuf_pindex:13; /* DWORD 1 */
+ u32 rsvd3:16; /* DWORD 2 */
+ u32 default_buffer_size:16; /* DWORD 2 */
+ u32 rsvd4[1]; /* DWORDS 3 to 3 */
+} SG_PACK ISCSI_DEFAULT_PDU_CONTEXT, *PISCSI_DEFAULT_PDU_CONTEXT;
+
+#else
+ /* ISCSI Default PDU Context latest */ typedef struct
+_ISCSI_DEFAULT_PDU_CONTEXT {
+ u32 dbuf_cindex:13; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 ring_state:4; /* DWORD 0 */
+ u32 ring_size:4; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 dbuf_pindex:13; /* DWORD 1 */
+ u32 rsvd2:3; /* DWORD 1 */
+ u32 rx_pdid:5; /* DWORD 1 */
+ u32 rx_pdid_not_valid:1; /* DWORD 1 */
+ u32 cq_id_recv:10; /* DWORD 1 */
+ u32 default_buffer_size:16; /* DWORD 2 */
+ u32 rsvd3:16; /* DWORD 2 */
+ u32 rsvd4[1]; /* DWORDS 3 to 3 */
+} SG_PACK ISCSI_DEFAULT_PDU_CONTEXT, *PISCSI_DEFAULT_PDU_CONTEXT;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This is the ring context structure for iSCSI only, because of its
+ * special linked list structure. The HLL and h are used only by
+ * btlr to track the list. When receiving a driver request, that
+ * is, the driver request bit is set in the TCPSCH_PROC_IQ_DATA
+ * descriptor from TCP Scheduler, iSCSI TXULP will double check the
+ * wrb_pend to make sure it is greater than zero, and then use the
+ * wrb_addr as the address of pending WRB and use it to generate
+ * CRA for UC request. After completing the current WRB, the iSCSI
+ * RXULP will send the ptr2NxtWRB to the CEV.
+ */
+typedef struct _RING_CONTEXT_ISCSI {
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 hll:8; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 h:1; /* DWORD 0 */
+ u32 rsvd2:10; /* DWORD 1 */
+ u32 o:1; /* DWORD 1 */
+ u32 pdid:5; /* DWORD 1 */
+ u32 wrb_pend:8; /* DWORD 1 */
+ u32 wrb_addr:8; /* DWORD 1 */
+} SG_PACK RING_CONTEXT_ISCSI, *PRING_CONTEXT_ISCSI;
+
+#else
+ /*
+ * This is the ring context structure for iSCSI only, because of its
+ * special linked list structure. The HLL and h are used only by
+ * btlr to track the list. When receiving a driver request, that
+ * is, the driver request bit is set in the TCPSCH_PROC_IQ_DATA
+ * descriptor from TCP Scheduler, iSCSI TXULP will double check the
+ * wrb_pend to make sure it is greater than zero, and then use the
+ * wrb_addr as the address of pending WRB and use it to generate
+ * CRA for UC request. After completing the current WRB, the iSCSI
+ * RXULP will send the ptr2NxtWRB to the CEV.
+ */
+typedef struct _RING_CONTEXT_ISCSI {
+ u32 h:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 hll:8; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 wrb_addr:8; /* DWORD 1 */
+ u32 wrb_pend:8; /* DWORD 1 */
+ u32 pdid:5; /* DWORD 1 */
+ u32 o:1; /* DWORD 1 */
+ u32 rsvd2:10; /* DWORD 1 */
+} SG_PACK RING_CONTEXT_ISCSI, *PRING_CONTEXT_ISCSI;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This is the ring context structure for iSCSI only, because of its
+ * special linked list structure. The HLL and h are used only by
+ * btlr to track the list. When receiving a driver request, that
+ * is, the driver request bit is set in the TCPSCH_PROC_IQ_DATA
+ * descriptor from TCP Scheduler, iSCSI TXULP will double check the
+ * wrb_pend to make sure it is greater than zero, and then use the
+ * wrb_addr as the address of pending WRB and use it to generate
+ * CRA for UC request. After completing the current WRB, the iSCSI
+ * RXULP will send the ptr2NxtWRB to the CEV.
+ */
+typedef struct _RING_CONTEXT_ISCSI_BE2 {
+ u32 r2t_cidx:10; /* DWORD 0 */
+ u32 fetch_r2t:1; /* DWORD 0 */
+ u32 fetch_wrb:1; /* DWORD 0 */
+ u32 tx_ring_size:4; /* DWORD 0 */
+ u32 hll:8; /* DWORD 0 */
+ u32 wrb_addr:8; /* DWORD 0 */
+ u32 ctx_valid:1; /* DWORD 1 */
+ u32 pdid:9; /* DWORD 1 */
+ u32 pci_func_id:8; /* DWORD 1 */
+ u32 rsvd0:5; /* DWORD 1 */
+ u32 h:1; /* DWORD 1 */
+ u32 wrb_pend:8; /* DWORD 1 */
+} SG_PACK RING_CONTEXT_ISCSI_BE2, *PRING_CONTEXT_ISCSI_BE2;
+
+#else
+ /*
+ * This is the ring context structure for iSCSI only, because of its
+ * special linked list structure. The HLL and h are used only by
+ * btlr to track the list. When receiving a driver request, that
+ * is, the driver request bit is set in the TCPSCH_PROC_IQ_DATA
+ * descriptor from TCP Scheduler, iSCSI TXULP will double check the
+ * wrb_pend to make sure it is greater than zero, and then use the
+ * wrb_addr as the address of pending WRB and use it to generate
+ * CRA for UC request. After completing the current WRB, the iSCSI
+ * RXULP will send the ptr2NxtWRB to the CEV.
+ */
+typedef struct _RING_CONTEXT_ISCSI_BE2 {
+ u32 wrb_addr:8; /* DWORD 0 */
+ u32 hll:8; /* DWORD 0 */
+ u32 tx_ring_size:4; /* DWORD 0 */
+ u32 fetch_wrb:1; /* DWORD 0 */
+ u32 fetch_r2t:1; /* DWORD 0 */
+ u32 r2t_cidx:10; /* DWORD 0 */
+ u32 wrb_pend:8; /* DWORD 1 */
+ u32 h:1; /* DWORD 1 */
+ u32 rsvd0:5; /* DWORD 1 */
+ u32 pci_func_id:8; /* DWORD 1 */
+ u32 pdid:9; /* DWORD 1 */
+ u32 ctx_valid:1; /* DWORD 1 */
+} SG_PACK RING_CONTEXT_ISCSI_BE2, *PRING_CONTEXT_ISCSI_BE2;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __iscsi_common_host_struct_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_context_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_context_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_context_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/mpu_context_bmap.h 2008-02-14 15:23:07.841200720 +0530
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__mpu_context_bmap_h__ #define __mpu_context_bmap_h__ #include
+"setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Management command and control ring context. The MPUs BTLR_CTRL1
+ * CSR controls the writeback behavior of the producer and consumer
+ * index values.
+ */
+typedef struct _MCC_RING_CONTEXT {
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 cq_id:11; /* DWORD 0 */
+ u32 ring_size:4; /* DWORD 0 */
+ u32 con_index:16; /* DWORD 0 */
+ u32 invalid:1; /* DWORD 1 */
+ u32 pdid:15; /* DWORD 1 */
+ u32 prod_index:16; /* DWORD 1 */
+ u32 rsvd1:25; /* DWORD 2 */
+ u32 cmd_pending_current:7; /* DWORD 2 */
+ u32 rsvd3:9; /* DWORD 3 */
+ u32 cmd_pending_max:7; /* DWORD 3 */
+ u32 rsvd2:5; /* DWORD 3 */
+ u32 hpi_port_cq_id:11; /* DWORD 3 */
+} SG_PACK MCC_RING_CONTEXT, *PMCC_RING_CONTEXT;
+
+#else
+ /*
+ * Management command and control ring context. The MPUs BTLR_CTRL1
+ * CSR controls the writeback behavior of the producer and consumer
+ * index values.
+ */
+typedef struct _MCC_RING_CONTEXT {
+ u32 con_index:16; /* DWORD 0 */
+ u32 ring_size:4; /* DWORD 0 */
+ u32 cq_id:11; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 prod_index:16; /* DWORD 1 */
+ u32 pdid:15; /* DWORD 1 */
+ u32 invalid:1; /* DWORD 1 */
+ u32 cmd_pending_current:7; /* DWORD 2 */
+ u32 rsvd1:25; /* DWORD 2 */
+ u32 hpi_port_cq_id:11; /* DWORD 3 */
+ u32 rsvd2:5; /* DWORD 3 */
+ u32 cmd_pending_max:7; /* DWORD 3 */
+ u32 rsvd3:9; /* DWORD 3 */
+} SG_PACK MCC_RING_CONTEXT, *PMCC_RING_CONTEXT;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __mpu_context_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_eth_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_eth_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_eth_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_eth_bmap.h 2008-02-14 15:23:07.841200720 +0530
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__ioctl_eth_bmap_h__ #define __ioctl_eth_bmap_h__ #include "setypes.h"
+#include "ioctl_hdr_bmap.h"
+#include "ioctl_types_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+typedef struct _MIB_ETH_STATISTICS_PARAMS_IN {
+ u32 rsvd0;
+} SG_PACK MIB_ETH_STATISTICS_PARAMS_IN, *PMIB_ETH_STATISTICS_PARAMS_IN;
+
+typedef struct _BE_RXF_STATS {
+ u32 p0recvdtotalbytesLSD; /* DWORD 0 */
+ u32 p0recvdtotalbytesMSD; /* DWORD 1 */
+ u32 p0recvdtotalframes; /* DWORD 2 */
+ u32 p0recvdunicastframes; /* DWORD 3 */
+ u32 p0recvdmulticastframes; /* DWORD 4 */
+ u32 p0recvdbroadcastframes; /* DWORD 5 */
+ u32 p0crcerrors; /* DWORD 6 */
+ u32 p0alignmentsymerrs; /* DWORD 7 */
+ u32 p0pauseframesrecvd; /* DWORD 8 */
+ u32 p0controlframesrecvd; /* DWORD 9 */
+ u32 p0inrangelenerrors; /* DWORD 10 */
+ u32 p0outrangeerrors; /* DWORD 11 */
+ u32 p0frametoolongerrors; /* DWORD 12 */
+ u32 p0droppedaddressmatch; /* DWORD 13 */
+ u32 p0droppedvlanmismatch; /* DWORD 14 */
+ u32 p0ipdroppedtoosmall; /* DWORD 15 */
+ u32 p0ipdroppedtooshort; /* DWORD 16 */
+ u32 p0ipdroppedhdrtoosmall; /* DWORD 17 */
+ u32 p0tcpdroppedlen; /* DWORD 18 */
+ u32 p0droppedrunt; /* DWORD 19 */
+ u32 p0recvd64; /* DWORD 20 */
+ u32 p0recvd65_127; /* DWORD 21 */
+ u32 p0recvd128_256; /* DWORD 22 */
+ u32 p0recvd256_511; /* DWORD 23 */
+ u32 p0recvd512_1023; /* DWORD 24 */
+ u32 p0recvd1518_1522; /* DWORD 25 */
+ u32 p0recvd1522_2047; /* DWORD 26 */
+ u32 p0recvd2048_4095; /* DWORD 27 */
+ u32 p0recvd4096_8191; /* DWORD 28 */
+ u32 p0recvd8192_9216; /* DWORD 29 */
+ u32 p0rcvdipcksmerrs; /* DWORD 30 */
+ u32 p0recvdtcpcksmerrs; /* DWORD 31 */
+ u32 p0recvdudpcksmerrs; /* DWORD 32 */
+ u32 p0recvdnonrsspackets; /* DWORD 33 */
+ u32 p0recvdippackets; /* DWORD 34 */
+ u32 p0recvdchute1packets; /* DWORD 35 */
+ u32 p0recvdchute2packets; /* DWORD 36 */
+ u32 p0recvdchute3packets; /* DWORD 37 */
+ u32 p0recvdipsecpackets; /* DWORD 38 */
+ u32 p0recvdmanagementpackets; /* DWORD 39 */
+ u32 p0xmitbyteslsd; /* DWORD 40 */
+ u32 p0xmitbytesmsd; /* DWORD 41 */
+ u32 p0xmitunicastframes; /* DWORD 42 */
+ u32 p0xmitmulticastframes; /* DWORD 43 */
+ u32 p0xmitbroadcastframes; /* DWORD 44 */
+ u32 p0xmitpauseframes; /* DWORD 45 */
+ u32 p0xmitcontrolframes; /* DWORD 46 */
+ u32 p0xmit64; /* DWORD 47 */
+ u32 p0xmit65_127; /* DWORD 48 */
+ u32 p0xmit128_256; /* DWORD 49 */
+ u32 p0xmit256_511; /* DWORD 50 */
+ u32 p0xmit512_1023; /* DWORD 51 */
+ u32 p0xmit1518_1522; /* DWORD 52 */
+ u32 p0xmit1522_2047; /* DWORD 53 */
+ u32 p0xmit2048_4095; /* DWORD 54 */
+ u32 p0xmit4096_8191; /* DWORD 55 */
+ u32 p0xmit8192_9216; /* DWORD 56 */
+ u32 p0rxfifooverflowdropped; /* DWORD 57 */
+ u32 p0ipseclookupfaileddropped; /* DWORD 58 */
+ u32 p1recvdtotalbytesLSD; /* DWORD 59 */
+ u32 p1recvdtotalbytesMSD; /* DWORD 60 */
+ u32 p1recvdtotalframes; /* DWORD 61 */
+ u32 p1recvdunicastframes; /* DWORD 62 */
+ u32 p1recvdmulticastframes; /* DWORD 63 */
+ u32 p1recvdbroadcastframes; /* DWORD 64 */
+ u32 p1crcerrors; /* DWORD 65 */
+ u32 p1alignmentsymerrs; /* DWORD 66 */
+ u32 p1pauseframesrecvd; /* DWORD 67 */
+ u32 p1controlframesrecvd; /* DWORD 68 */
+ u32 p1inrangelenerrors; /* DWORD 69 */
+ u32 p1outrangeerrors; /* DWORD 70 */
+ u32 p1frametoolongerrors; /* DWORD 71 */
+ u32 p1droppedaddressmatch; /* DWORD 72 */
+ u32 p1droppedvlanmismatch; /* DWORD 73 */
+ u32 p1ipdroppedtoosmall; /* DWORD 74 */
+ u32 p1ipdroppedtooshort; /* DWORD 75 */
+ u32 p1ipdroppedhdrtoosmall; /* DWORD 76 */
+ u32 p1tcpdroppedlen; /* DWORD 77 */
+ u32 p1droppedrunt; /* DWORD 78 */
+ u32 p1recvd64; /* DWORD 79 */
+ u32 p1recvd65_127; /* DWORD 80 */
+ u32 p1recvd128_256; /* DWORD 81 */
+ u32 p1recvd256_511; /* DWORD 82 */
+ u32 p1recvd512_1023; /* DWORD 83 */
+ u32 p1recvd1518_1522; /* DWORD 84 */
+ u32 p1recvd1522_2047; /* DWORD 85 */
+ u32 p1recvd2048_4095; /* DWORD 86 */
+ u32 p1recvd4096_8191; /* DWORD 87 */
+ u32 p1recvd8192_9216; /* DWORD 88 */
+ u32 p1rcvdipcksmerrs; /* DWORD 89 */
+ u32 p1recvdtcpcksmerrs; /* DWORD 90 */
+ u32 p1recvdudpcksmerrs; /* DWORD 91 */
+ u32 p1recvdnonrsspackets; /* DWORD 92 */
+ u32 p1recvdippackets; /* DWORD 93 */
+ u32 p1recvdchute1packets; /* DWORD 94 */
+ u32 p1recvdchute2packets; /* DWORD 95 */
+ u32 p1recvdchute3packets; /* DWORD 96 */
+ u32 p1recvdipsecpackets; /* DWORD 97 */
+ u32 p1recvdmanagementpackets; /* DWORD 98 */
+ u32 p1xmitbyteslsd; /* DWORD 99 */
+ u32 p1xmitbytesmsd; /* DWORD 100 */
+ u32 p1xmitunicastframes; /* DWORD 101 */
+ u32 p1xmitmulticastframes; /* DWORD 102 */
+ u32 p1xmitbroadcastframes; /* DWORD 103 */
+ u32 p1xmitpauseframes; /* DWORD 104 */
+ u32 p1xmitcontrolframes; /* DWORD 105 */
+ u32 p1xmit64; /* DWORD 106 */
+ u32 p1xmit65_127; /* DWORD 107 */
+ u32 p1xmit128_256; /* DWORD 108 */
+ u32 p1xmit256_511; /* DWORD 109 */
+ u32 p1xmit512_1023; /* DWORD 110 */
+ u32 p1xmit1518_1522; /* DWORD 111 */
+ u32 p1xmit1522_2047; /* DWORD 112 */
+ u32 p1xmit2048_4095; /* DWORD 113 */
+ u32 p1xmit4096_8191; /* DWORD 114 */
+ u32 p1xmit8192_9216; /* DWORD 115 */
+ u32 p1rxfifooverflowdropped; /* DWORD 116 */
+ u32 p1ipseclookupfaileddropped; /* DWORD 117 */
+ u32 pxdroppednopbuf; /* DWORD 118 */
+ u32 pxdroppednotxpb; /* DWORD 119 */
+ u32 pxdroppednoipsecbuf; /* DWORD 120 */
+ u32 pxdroppednoerxdescr; /* DWORD 121 */
+ u32 pxdroppednotpredescr; /* DWORD 122 */
+ u32 pxrecvdmanagementportpackets; /* DWORD 123 */
+ u32 pxrecvdmanagementportbytes; /* DWORD 124 */
+ u32 pxrecvdmanagementportpauseframes; /* DWORD 125 */
+ u32 pxrecvdmanagementporterrors; /* DWORD 126 */
+ u32 pxxmitmanagementportpackets; /* DWORD 127 */
+ u32 pxxmitmanagementportbytes; /* DWORD 128 */
+ u32 pxxmitmanagementportpause; /* DWORD 129 */
+ u32 pxxmitmanagementportrxfifooverflow; /* DWORD 130 */
+ u32 pxrecvdipsecipcksmerrs; /* DWORD 131 */
+ u32 pxrecvdtcpsecipcksmerrs; /* DWORD 132 */
+ u32 pxrecvdudpsecipcksmerrs; /* DWORD 133 */
+ u32 pxipsecrunt; /* DWORD 134 */
+ u32 pxipsecaddressmismatchdropped; /* DWORD 135 */
+ u32 pxipsecrxfifooverflowdropped; /* DWORD 136 */
+ u32 pxipsecframestoolong; /* DWORD 137 */
+ u32 pxipsectotalipframes; /* DWORD 138 */
+ u32 pxipseciptoosmall; /* DWORD 139 */
+ u32 pxipseciptooshort; /* DWORD 140 */
+ u32 pxipseciphdrtoosmall; /* DWORD 141 */
+ u32 pxipsectcphdrbad; /* DWORD 142 */
+ u32 pxrecvdipsecchute1; /* DWORD 143 */
+ u32 pxrecvdipsecchute2; /* DWORD 144 */
+ u32 pxrecvdipsecchute3; /* DWORD 145 */
+ u32 pxdropped7frags; /* DWORD 146 */
+ u32 pxdroppedfrags; /* DWORD 147 */
+ u32 pxdroppedinvalidfragring; /* DWORD 148 */
+ u32 pxnumforwardedpackets; /* DWORD 149 */
+} SG_PACK BE_RXF_STATS, *PBE_RXF_STATS;
+
+typedef union _MIB_ETH_STATISTICS_PARAMS {
+ MIB_ETH_STATISTICS_PARAMS_IN request;
+ BE_RXF_STATS response;
+} SG_PACK MIB_ETH_STATISTICS_PARAMS, *PMIB_ETH_STATISTICS_PARAMS;
+
+/*
+ * Query ethernet statistics. All domains may issue this IOCTL. The
+ * host domain drivers may optionally reset internal statistic
+counters
+ * with a query.
+ */
+typedef struct _IOCTL_ETH_GET_STATISTICS {
+ IOCTL_HEADER header;
+ MIB_ETH_STATISTICS_PARAMS params;
+} SG_PACK IOCTL_ETH_GET_STATISTICS, *PIOCTL_ETH_GET_STATISTICS;
+
+typedef struct _BE_RSS_CONFIG {
+ u16 enable_rss;
+ u16 cpu_table_size_log2;
+ u16 cqid0;
+ u16 cqid1;
+ u16 cqid2;
+ u16 cqid3;
+ u32 hash[4];
+ u8 cpu_table[128];
+ u16 cq_flush_mask;
+ u16 rsvd0;
+ u32 flush_value;
+} SG_PACK BE_RSS_CONFIG, *PBE_RSS_CONFIG;
+
+typedef struct _IOCTL_ETH_ANON_171_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_ETH_ANON_171_RESPONSE, *PIOCTL_ETH_ANON_171_RESPONSE;
+
+typedef union _IOCTL_ETH_ANON_170_PARAMS {
+ BE_RSS_CONFIG request;
+ IOCTL_ETH_ANON_171_RESPONSE response;
+} SG_PACK IOCTL_ETH_ANON_170_PARAMS, *PIOCTL_ETH_ANON_170_PARAMS;
+
+/*
+ * Configures or disables receive side scaling (RSS), which
+distributes
+ * ethernet receive completions among (up to 4) completion queues.
+ * This is in addition to the default ethernet receive completion queue.
+ * Presumably, the host driver processes each completion queue with
+ * a DPC running on a different processor. This IOCTL can only be
+issued
+ * by domain 0 network drivers.
+ */
+typedef struct _IOCTL_ETH_RSS_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_ETH_ANON_170_PARAMS params;
+} SG_PACK IOCTL_ETH_RSS_CONFIG, *PIOCTL_ETH_RSS_CONFIG;
+
+typedef struct _IOCTL_ETH_ACPI_CONFIG_PARAMS {
+ u8 index;
+ u8 port0;
+ u8 port1;
+ u8 magic_packet;
+ u8 byte_pattern[128];
+ u32 bit_mask[4];
+} SG_PACK IOCTL_ETH_ACPI_CONFIG_PARAMS, *PIOCTL_ETH_ACPI_CONFIG_PARAMS;
+
+typedef struct _IOCTL_ETH_ANON_173_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_ETH_ANON_173_RESPONSE, *PIOCTL_ETH_ANON_173_RESPONSE;
+
+typedef union _IOCTL_ETH_ANON_172_PARAMS {
+ IOCTL_ETH_ACPI_CONFIG_PARAMS request;
+ IOCTL_ETH_ANON_173_RESPONSE response;
+} SG_PACK IOCTL_ETH_ANON_172_PARAMS, *PIOCTL_ETH_ANON_172_PARAMS;
+
+/*
+ * Sets the magic packet or interesting packet byte pattern and mask
+ * * for wake-on-lan. Only host drivers are allowed to modify magic
+ * packet * settings. Only the host networking driver is allowed to
+ * modify the * interesting packet byte pattern and mask settings.
+ *
+ */
+typedef struct _IOCTL_ETH_ACPI_CONFIG {
+ IOCTL_HEADER header;
+ IOCTL_ETH_ANON_172_PARAMS params;
+} SG_PACK IOCTL_ETH_ACPI_CONFIG, *PIOCTL_ETH_ACPI_CONFIG;
+
+typedef struct _IOCTL_ETH_ANON_175_REQUEST {
+ u8 port0_promiscuous;
+ u8 port1_promiscuous;
+ u16 rsvd0;
+} SG_PACK IOCTL_ETH_ANON_175_REQUEST, *PIOCTL_ETH_ANON_175_REQUEST;
+
+typedef struct _IOCTL_ETH_ANON_176_RESPONSE {
+ u32 rsvd0;
+} SG_PACK IOCTL_ETH_ANON_176_RESPONSE, *PIOCTL_ETH_ANON_176_RESPONSE;
+
+typedef union _IOCTL_ETH_ANON_174_PARAMS {
+ IOCTL_ETH_ANON_175_REQUEST request;
+ IOCTL_ETH_ANON_176_RESPONSE response;
+} SG_PACK IOCTL_ETH_ANON_174_PARAMS, *PIOCTL_ETH_ANON_174_PARAMS;
+
+/* Enables/Disables promiscuous ethernet receive mode. */ typedef
+struct _IOCTL_ETH_PROMISCUOUS {
+ IOCTL_HEADER header;
+ IOCTL_ETH_ANON_174_PARAMS params;
+} SG_PACK IOCTL_ETH_PROMISCUOUS, *PIOCTL_ETH_PROMISCUOUS;
+
+typedef struct _IOCTL_ETH_ANON_178_REQUEST {
+ u32 new_fragsize_log2;
+} SG_PACK IOCTL_ETH_ANON_178_REQUEST, *PIOCTL_ETH_ANON_178_REQUEST;
+
+typedef struct _IOCTL_ETH_ANON_179_RESPONSE {
+ u32 actual_fragsize_log2;
+} SG_PACK IOCTL_ETH_ANON_179_RESPONSE, *PIOCTL_ETH_ANON_179_RESPONSE;
+
+typedef union _IOCTL_ETH_ANON_177_PARAMS {
+ IOCTL_ETH_ANON_178_REQUEST request;
+ IOCTL_ETH_ANON_179_RESPONSE response;
+} SG_PACK IOCTL_ETH_ANON_177_PARAMS, *PIOCTL_ETH_ANON_177_PARAMS;
+
+/*
+ * Sets the Ethernet RX fragment size. Only host (domain 0) networking
+ * drivers may issue this IOCTL. This call will fail for non-host
+ * protection domains. In this situation the MCC CQ status will
+indicate
+ * a failure due to insufficient priviledges. The response should be
+ * ignored, and the driver should use the IOCTL_ETH_GET_FRAG_SIZE to
+ * query the existing ethernet receive fragment size. It must use
+this
+ * fragment size for all fragments in the ethernet receive ring. If
+ * the IOCTL succeeds, the driver must use the frag size indicated
+ * in the IOCTL response since the requested frag size may not be
+applied
+ * until the next reboot. When the requested fragsize matches the response
+ * fragsize, this indicates the request was applied immediately.
+ */
+typedef struct _IOCTL_ETH_SET_RX_FRAG_SIZE {
+ IOCTL_HEADER header;
+ IOCTL_ETH_ANON_177_PARAMS params;
+} SG_PACK IOCTL_ETH_SET_RX_FRAG_SIZE, *PIOCTL_ETH_SET_RX_FRAG_SIZE;
+
+typedef struct _IOCTL_ETH_ANON_181_REQUEST {
+ u32 rsvd0;
+} SG_PACK IOCTL_ETH_ANON_181_REQUEST, *PIOCTL_ETH_ANON_181_REQUEST;
+
+typedef struct _IOCTL_ETH_ANON_182_RESPONSE {
+ u32 actual_fragsize_log2;
+} SG_PACK IOCTL_ETH_ANON_182_RESPONSE, *PIOCTL_ETH_ANON_182_RESPONSE;
+
+typedef union _IOCTL_ETH_ANON_180_PARAMS {
+ IOCTL_ETH_ANON_181_REQUEST request;
+ IOCTL_ETH_ANON_182_RESPONSE response;
+} SG_PACK IOCTL_ETH_ANON_180_PARAMS, *PIOCTL_ETH_ANON_180_PARAMS;
+
+/*
+ * Queries the Ethernet RX fragment size. All domains may issue this
+ * IOCTL. The driver should call this IOCTL to determine the minimum
+ * required fragment size for the ethernet RX ring buffers. Drivers
+ * may choose to use a larger size for each fragment buffer, but
+BladeEngine
+ * will use up to the configured minimum required fragsize in each ethernet
+ * receive fragment buffer. For example, if the ethernet receive fragment
+ * size is configured to 4kB, and a driver uses 8kB fragments, a 6kB
+ * ethernet packet received by BladeEngine will be split accross two
+ * of the driver's receive framgents (4kB in one fragment buffer, and
+ * 2kB in the subsequent fragment buffer).
+ */
+typedef struct _IOCTL_ETH_GET_RX_FRAG_SIZE {
+ IOCTL_HEADER header;
+ IOCTL_ETH_ANON_180_PARAMS params;
+} SG_PACK IOCTL_ETH_GET_RX_FRAG_SIZE, *PIOCTL_ETH_GET_RX_FRAG_SIZE;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_eth_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_mcc_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_mcc_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_mcc_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_mcc_bmap.h 2008-02-14 15:23:07.842200568 +0530
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__ioctl_mcc_bmap_h__ #define __ioctl_mcc_bmap_h__ #include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+/*
+ * Where applicable, a WRB, may contain a list of Scatter-gather elements.
+ * Each element supports a 64 bit address and a 32bit length field.
+ *
+ */
+typedef struct _MCC_SGE {
+ u32 pa_lo; /* DWORD 0 */
+ u32 pa_hi; /* DWORD 1 */
+ u32 length; /* DWORD 2 */
+} SG_PACK MCC_SGE, *PMCC_SGE;
+
+/*
+ * The design of an MCC_SGE allows up to 19 elements to be embedded
+ * in a WRB, supporting 64KB data transfers (assuming a 4KB page size).
+ *
+ */
+typedef union _MCC_WRB_PAYLOAD {
+ MCC_SGE sgl[19];
+ u32 embedded[59]; /* DWORDS 57 to 115 */
+} SG_PACK MCC_WRB_PAYLOAD, *PMCC_WRB_PAYLOAD;
+
+/*
+ * This is the structure of the MCC Command WRB for commands sent to
+ * the Management Processing Unit (MPU). See section IOCTL_TYPES for
+ * usage in embedded and non-embedded modes.
+ */
+typedef struct _MCC_WRB {
+ u32 embedded:1; /* DWORD 0 */
+ u32 rsvd0:2; /* DWORD 0 */
+ u32 sge_count:5; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 special:8; /* DWORD 0 */
+ u32 payload_length; /* DWORD 1 */
+ u32 tag[2]; /* DWORDS 2 to 3 */
+ u32 rsvd2[1]; /* DWORDS 4 to 4 */
+ MCC_WRB_PAYLOAD payload;
+} SG_PACK MCC_WRB, *PMCC_WRB;
+
+/* This is the structure of the MCC Completion queue entry */ typedef
+struct _MCC_CQ_ENTRY {
+ u32 completion_status:16; /* DWORD 0 */
+ u32 extended_status:16; /* DWORD 0 */
+ u32 mcc_tag[2]; /* DWORDS 1 to 2 */
+ u32 rsvd0:27; /* DWORD 3 */
+ u32 consumed:1; /* DWORD 3 */
+ u32 completed:1; /* DWORD 3 */
+ u32 hpi_buffer_completion:1; /* DWORD 3 */
+ u32 async_event:1; /* DWORD 3 */
+ u32 valid:1; /* DWORD 3 */
+} SG_PACK MCC_CQ_ENTRY, *PMCC_CQ_ENTRY;
+
+/* Mailbox structures used by the MPU during bootstrap */ typedef
+struct _MCC_MAILBOX {
+ MCC_WRB wrb;
+ MCC_CQ_ENTRY cq;
+} SG_PACK MCC_MAILBOX, *PMCC_MAILBOX;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_mcc_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/post_codes_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/post_codes_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/post_codes_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/post_codes_bmap.h 2008-02-14 15:23:07.842200568 +0530
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@serverengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127 */ #ifndef
+__post_codes_bmap_h__ #define __post_codes_bmap_h__ #include
+"setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed)) #else #define SG_PACK #endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_) #endif
+
+#if defined(__BIG_ENDIAN)
+ /* This structure defines the format of the MPU semaphore register
+ * when used for POST. */
+typedef struct _MGMT_HBA_POST_STATUS_STRUCT {
+ union {
+ struct {
+ u32 error:1; /* DWORD 0 */
+ u32 backup_fw:1; /* DWORD 0 */
+ u32 iscsi_no_ip:1; /* DWORD 0 */
+ u32 iscsi_ip_conflict:1; /* DWORD 0 */
+ u32 option_rom_installed:1; /* DWORD 0 */
+ u32 iscsi_driver_loaded:1; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 stage:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MGMT_HBA_POST_STATUS_STRUCT, *PMGMT_HBA_POST_STATUS_STRUCT;
+
+SG_C_ASSERT(__sizeof__MGMT_HBA_POST_STATUS_STRUCT,
+ sizeof(MGMT_HBA_POST_STATUS_STRUCT) == 4);
+
+#else
+ /* This structure defines the format of the MPU semaphore register
+ * when used for POST. */
+typedef struct _MGMT_HBA_POST_STATUS_STRUCT {
+ union {
+ struct {
+ u32 stage:16; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 iscsi_driver_loaded:1; /* DWORD 0 */
+ u32 option_rom_installed:1; /* DWORD 0 */
+ u32 iscsi_ip_conflict:1; /* DWORD 0 */
+ u32 iscsi_no_ip:1; /* DWORD 0 */
+ u32 backup_fw:1; /* DWORD 0 */
+ u32 error:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK MGMT_HBA_POST_STATUS_STRUCT, *PMGMT_HBA_POST_STATUS_STRUCT;
+
+SG_C_ASSERT(__sizeof__MGMT_HBA_POST_STATUS_STRUCT,
+ sizeof(MGMT_HBA_POST_STATUS_STRUCT) == 4); #endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __post_codes_bmap_h__ */
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