* [PATCH 01/20] tg3: Assign flags to fixes in start_xmit_dma_bug
From: Matt Carlson @ 2009-11-02 22:33 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch adds a flag for each bug workaround in
tg3_start_xmit_dma_bug(). This is prep work for the following patch.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 26 +++++++++++++++++++-------
drivers/net/tg3.h | 2 ++
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index ba5d3fe..da80825 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5124,7 +5124,8 @@ static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
/* Make sure new skb does not cross any 4G boundaries.
* Drop the packet if it does.
*/
- if (ret || tg3_4g_overflow_test(new_addr, new_skb->len)) {
+ if (ret || ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
+ tg3_4g_overflow_test(new_addr, new_skb->len))) {
if (!ret)
skb_dma_unmap(&tp->pdev->dev, new_skb,
DMA_TO_DEVICE);
@@ -5459,9 +5460,15 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
would_hit_hwbug = 0;
- if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
+ if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
+ tg3_4g_overflow_test(mapping, len))
+ would_hit_hwbug = 1;
+
+ if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
+ tg3_40bit_overflow_test(tp, mapping, len))
would_hit_hwbug = 1;
- else if (tg3_4g_overflow_test(mapping, len))
+
+ if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
would_hit_hwbug = 1;
tg3_set_txd(tnapi, entry, mapping, len, base_flags,
@@ -5482,10 +5489,12 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
tnapi->tx_buffers[entry].skb = NULL;
- if (tg3_4g_overflow_test(mapping, len))
+ if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
+ tg3_4g_overflow_test(mapping, len))
would_hit_hwbug = 1;
- if (tg3_40bit_overflow_test(tp, mapping, len))
+ if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
+ tg3_40bit_overflow_test(tp, mapping, len))
would_hit_hwbug = 1;
if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
@@ -12610,12 +12619,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->irq_max = 1;
-#ifdef TG3_NAPI
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
tp->irq_max = TG3_IRQ_MAX_VECS;
}
-#endif
+
+ if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
+ tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
+ tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
+ }
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index bab7940..b603810 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2759,6 +2759,8 @@ struct tg3 {
#define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000
#define TG3_FLG3_PHY_IS_FET 0x00010000
#define TG3_FLG3_ENABLE_RSS 0x00020000
+#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
+#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
struct timer_list timer;
u16 timer_counter;
--
1.6.4.4
^ permalink raw reply related
* [PATCH 07/20] tg3: Improve 5785 PCIe performance
From: Matt Carlson @ 2009-11-03 0:26 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch improves 5785 performance by allowing the write DMA engine to
request larger DMA burst sizes than it otherwise would.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 3 +++
drivers/net/tg3.h | 3 ++-
2 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 54dbe98..a43ef2b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7633,6 +7633,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
val |= WDMAC_MODE_STATUS_TAG_FIX;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
+ val |= WDMAC_MODE_BURST_ALL_DATA;
+
tw32_f(WDMAC_MODE, val);
udelay(40);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 530c36b..68431da 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1264,8 +1264,9 @@
#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
-#define WDMAC_MODE_RX_ACCEL 0x00000400
+#define WDMAC_MODE_RX_ACCEL 0x00000400
#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
+#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
#define WDMAC_STATUS 0x00004c04
#define WDMAC_STATUS_TGTABORT 0x00000004
#define WDMAC_STATUS_MSTABORT 0x00000008
--
1.6.4.4
^ permalink raw reply related
* [PATCH 06/20] tg3: Add more PCI DMA map error checking
From: Matt Carlson @ 2009-11-03 0:25 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch adds code to check the status of pci_map_single() before
allowing rx buffers to be used. It also converts the pci_map_single()
call in tg3_run_loopback() to use skb_dma_map() instead.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
---
drivers/net/tg3.c | 14 +++++++++++---
1 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 53a193e..54dbe98 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4426,6 +4426,10 @@ static int tg3_alloc_rx_skb(struct tg3_napi *tnapi, u32 opaque_key,
mapping = pci_map_single(tp->pdev, skb->data, skb_size,
PCI_DMA_FROMDEVICE);
+ if (pci_dma_mapping_error(tp->pdev, mapping)) {
+ dev_kfree_skb(skb);
+ return -EIO;
+ }
map->skb = skb;
pci_unmap_addr_set(map, mapping, mapping);
@@ -10369,7 +10373,10 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
for (i = 14; i < tx_len; i++)
tx_data[i] = (u8) (i & 0xff);
- map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
+ if (skb_dma_map(&tp->pdev->dev, skb, DMA_TO_DEVICE)) {
+ dev_kfree_skb(skb);
+ return -EIO;
+ }
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
rnapi->coal_now);
@@ -10380,7 +10387,8 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
num_pkts = 0;
- tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
+ tg3_set_txd(tnapi, tnapi->tx_prod,
+ skb_shinfo(skb)->dma_head, tx_len, 0, 1);
tnapi->tx_prod++;
num_pkts++;
@@ -10404,7 +10412,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
break;
}
- pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
+ skb_dma_unmap(&tp->pdev->dev, skb, DMA_TO_DEVICE);
dev_kfree_skb(skb);
if (tx_idx != tnapi->tx_prod)
--
1.6.4.4
^ permalink raw reply related
* [PATCH 05/20] tg3: Prevent a PCIe tx glitch
From: Matt Carlson @ 2009-11-03 0:25 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch prevents a PCIe tx glitch by allowing the transmitter to go
to a low power state.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 24 ++++++++++++++++++++++++
drivers/net/tg3.h | 26 +++++++++++++++++++++++++-
2 files changed, 49 insertions(+), 1 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 1c53250..53a193e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -6589,6 +6589,30 @@ static int tg3_chip_reset(struct tg3 *tp)
tg3_mdio_start(tp);
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
+ u8 phy_addr;
+
+ phy_addr = tp->phy_addr;
+ tp->phy_addr = TG3_PHY_PCIE_ADDR;
+
+ tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
+ TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
+ val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
+ TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
+ TG3_PCIEPHY_TX0CTRL1_NB_EN;
+ tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
+ udelay(10);
+
+ tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
+ TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
+ val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
+ TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
+ tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
+ udelay(10);
+
+ tp->phy_addr = phy_addr;
+ }
+
if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 40501cb..530c36b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1953,10 +1953,34 @@
#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
+
/* Currently this is fixed. */
+#define TG3_PHY_PCIE_ADDR 0x00
#define TG3_PHY_MII_ADDR 0x01
-/* Tigon3 specific PHY MII registers. */
+
+/*** Tigon3 specific PHY PCIE registers. ***/
+
+#define TG3_PCIEPHY_BLOCK_ADDR 0x1f
+#define TG3_PCIEPHY_XGXS_BLK1 0x0801
+#define TG3_PCIEPHY_TXB_BLK 0x0861
+#define TG3_PCIEPHY_BLOCK_SHIFT 4
+
+/* TG3_PCIEPHY_TXB_BLK */
+#define TG3_PCIEPHY_TX0CTRL1 0x15
+#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
+#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
+#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
+#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
+#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
+
+/* TG3_PCIEPHY_XGXS_BLK1 */
+#define TG3_PCIEPHY_PWRMGMT4 0x1a
+#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
+#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
+
+
+/*** Tigon3 specific PHY MII registers. ***/
#define TG3_BMCR_SPEED1000 0x0040
#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
--
1.6.4.4
^ permalink raw reply related
* [PATCH 04/20] tg3: Convert PHY_ADDR => TG3_PHY_MII_ADDR
From: Matt Carlson @ 2009-11-03 0:24 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch renames the PHY_ADDR preprocessor definition. The following
patch will identify a new member on the MDIO bus, so we want this
preprocessor definition to be a little more descriptive.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 51 +++++++++++++++++++++++++++++----------------------
drivers/net/tg3.h | 2 +-
2 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b3c5d74..1c53250 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -937,7 +937,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
u32 val;
struct phy_device *phydev;
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
case TG3_PHY_ID_BCM50610:
val = MAC_PHYCFG2_50610_LED_MODES;
@@ -1031,7 +1031,7 @@ static void tg3_mdio_start(struct tg3 *tp)
if (is_serdes)
tp->phy_addr += 7;
} else
- tp->phy_addr = PHY_ADDR;
+ tp->phy_addr = TG3_PHY_MII_ADDR;
if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
@@ -1062,7 +1062,7 @@ static int tg3_mdio_init(struct tg3 *tp)
tp->mdio_bus->read = &tg3_mdio_read;
tp->mdio_bus->write = &tg3_mdio_write;
tp->mdio_bus->reset = &tg3_mdio_reset;
- tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
+ tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
tp->mdio_bus->irq = &tp->mdio_irq[0];
for (i = 0; i < PHY_MAX_ADDR; i++)
@@ -1084,7 +1084,7 @@ static int tg3_mdio_init(struct tg3 *tp)
return i;
}
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
if (!phydev || !phydev->drv) {
printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
@@ -1311,7 +1311,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
u32 old_tx_mode = tp->tx_mode;
if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
- autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
+ autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
else
autoneg = tp->link_config.autoneg;
@@ -1348,7 +1348,7 @@ static void tg3_adjust_link(struct net_device *dev)
u8 oldflowctrl, linkmesg = 0;
u32 mac_mode, lcl_adv, rmt_adv;
struct tg3 *tp = netdev_priv(dev);
- struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
spin_lock_bh(&tp->lock);
@@ -1434,7 +1434,7 @@ static int tg3_phy_init(struct tg3 *tp)
/* Bring the PHY back to a known state. */
tg3_bmcr_reset(tp);
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
/* Attach the MAC to the PHY. */
phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
@@ -1461,7 +1461,7 @@ static int tg3_phy_init(struct tg3 *tp)
SUPPORTED_Asym_Pause);
break;
default:
- phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
+ phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
return -EINVAL;
}
@@ -1479,7 +1479,7 @@ static void tg3_phy_start(struct tg3 *tp)
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return;
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
if (tp->link_config.phy_is_low_power) {
tp->link_config.phy_is_low_power = 0;
@@ -1499,13 +1499,13 @@ static void tg3_phy_stop(struct tg3 *tp)
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return;
- phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
+ phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
}
static void tg3_phy_fini(struct tg3 *tp)
{
if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
- phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
+ phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
}
}
@@ -2474,7 +2474,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
struct phy_device *phydev;
u32 phyid, advertising;
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
tp->link_config.phy_is_low_power = 1;
@@ -9243,9 +9243,11 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
struct tg3 *tp = netdev_priv(dev);
if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+ struct phy_device *phydev;
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return -EAGAIN;
- return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+ return phy_ethtool_gset(phydev, cmd);
}
cmd->supported = (SUPPORTED_Autoneg);
@@ -9284,9 +9286,11 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
struct tg3 *tp = netdev_priv(dev);
if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+ struct phy_device *phydev;
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return -EAGAIN;
- return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+ return phy_ethtool_sset(phydev, cmd);
}
if (cmd->autoneg != AUTONEG_ENABLE &&
@@ -9469,7 +9473,7 @@ static int tg3_nway_reset(struct net_device *dev)
if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return -EAGAIN;
- r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
+ r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
} else {
u32 bmcr;
@@ -9588,7 +9592,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
u32 newadv;
struct phy_device *phydev;
- phydev = tp->mdio_bus->phy_map[PHY_ADDR];
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
if (epause->rx_pause) {
if (epause->tx_pause)
@@ -10568,9 +10572,11 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
int err;
if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+ struct phy_device *phydev;
if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
return -EAGAIN;
- return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
+ return phy_mii_ioctl(phydev, data, cmd);
}
switch(cmd) {
@@ -14135,13 +14141,14 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
tg3_bus_string(tp, str),
dev->dev_addr);
- if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
+ if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
+ struct phy_device *phydev;
+ phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
printk(KERN_INFO
"%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
- tp->dev->name,
- tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
- dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
- else
+ tp->dev->name, phydev->drv->name,
+ dev_name(&phydev->dev));
+ } else
printk(KERN_INFO
"%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
tp->dev->name, tg3_phy_string(tp),
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index eb4ed82..40501cb 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1954,7 +1954,7 @@
#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
/* Currently this is fixed. */
-#define PHY_ADDR 0x01
+#define TG3_PHY_MII_ADDR 0x01
/* Tigon3 specific PHY MII registers. */
#define TG3_BMCR_SPEED1000 0x0040
--
1.6.4.4
^ permalink raw reply related
* [PATCH 02/20] tg3: Fix 5906 transmit hangs
From: Matt Carlson @ 2009-11-03 0:23 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
The 5906 has trouble with fragments that are less than 8 bytes in size.
This patch works around the problem by pivoting the 5906's transmit
routine to tg3_start_xmit_dma_bug() and introducing a new SHORT_DMA_BUG
flag that enables code to detect and react to the problematic condition.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 26 +++++++++++++++++++-------
drivers/net/tg3.h | 1 +
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index da80825..a7a582e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5393,7 +5393,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
mss = 0;
if ((mss = skb_shinfo(skb)->gso_size) != 0) {
struct iphdr *iph;
- int tcp_opt_len, ip_tcp_len, hdr_len;
+ u32 tcp_opt_len, ip_tcp_len, hdr_len;
if (skb_header_cloned(skb) &&
pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
@@ -5424,8 +5424,10 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
IPPROTO_TCP,
0);
- if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
+ if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
+ mss |= hdr_len << 9;
+ else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
if (tcp_opt_len || iph->ihl > 5) {
int tsflags;
@@ -5460,6 +5462,9 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
would_hit_hwbug = 0;
+ if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
+ would_hit_hwbug = 1;
+
if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
tg3_4g_overflow_test(mapping, len))
would_hit_hwbug = 1;
@@ -5489,6 +5494,10 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
tnapi->tx_buffers[entry].skb = NULL;
+ if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
+ len <= 8)
+ would_hit_hwbug = 1;
+
if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
tg3_4g_overflow_test(mapping, len))
would_hit_hwbug = 1;
@@ -12625,8 +12634,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
}
if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
- tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
- tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+ tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
+ else {
+ tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
+ tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
+ }
}
if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
@@ -13987,8 +14000,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
goto err_out_iounmap;
}
- if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+ if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
dev->netdev_ops = &tg3_netdev_ops;
else
dev->netdev_ops = &tg3_netdev_ops_dma_bug;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index b603810..a5568a1 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2761,6 +2761,7 @@ struct tg3 {
#define TG3_FLG3_ENABLE_RSS 0x00020000
#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
+#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
struct timer_list timer;
u16 timer_counter;
--
1.6.4.4
^ permalink raw reply related
* [PATCH 08/20] tg3: Add AC131 power down support
From: Matt Carlson @ 2009-11-03 0:26 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
The AC131 does not respect the power down bit (bit 11) of the MII
Control Register (reg 0x0). Instead, software is required to put the
phy into standby power down mode through the shadow register set. This
patch implements support for the AC131 standby power down mode.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 20 ++++++++++++++++++++
drivers/net/tg3.h | 3 +++
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a43ef2b..003ab53 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2149,6 +2149,26 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
return;
+ } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+ u32 phytest;
+ if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
+ u32 phy;
+
+ tg3_writephy(tp, MII_ADVERTISE, 0);
+ tg3_writephy(tp, MII_BMCR,
+ BMCR_ANENABLE | BMCR_ANRESTART);
+
+ tg3_writephy(tp, MII_TG3_FET_TEST,
+ phytest | MII_TG3_FET_SHADOW_EN);
+ if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
+ phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
+ tg3_writephy(tp,
+ MII_TG3_FET_SHDW_AUXMODE4,
+ phy);
+ }
+ tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
+ }
+ return;
} else if (do_low_power) {
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 68431da..9999345 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2080,6 +2080,9 @@
#define MII_TG3_FET_SHDW_MISCCTRL 0x10
#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
+#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
+#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
+
#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
--
1.6.4.4
^ permalink raw reply related
* [PATCH 09/20] tg3: 5785: Set port mode to MII when link down
From: Matt Carlson @ 2009-11-03 0:27 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch sets the port mode to MII when the link is down for the 5785.
Setting the port mode to MII instead of GMII saves power.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 003ab53..d726da8 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1363,8 +1363,11 @@ static void tg3_adjust_link(struct net_device *dev)
if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
mac_mode |= MAC_MODE_PORT_MODE_MII;
- else
+ else if (phydev->speed == SPEED_1000 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
mac_mode |= MAC_MODE_PORT_MODE_GMII;
+ else
+ mac_mode |= MAC_MODE_PORT_MODE_MII;
if (phydev->duplex == DUPLEX_HALF)
mac_mode |= MAC_MODE_HALF_DUPLEX;
--
1.6.4.4
^ permalink raw reply related
* [PATCH 10/20] tg3: Extend loopback test timeout
From: Matt Carlson @ 2009-11-03 0:27 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch extends the loopback test timeout from 250 usec to 350 usec.
When the 5785 is paired against an AC131 phy, the older timeout is
just a little too close to the expected performance based on timings.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d726da8..7bebb47 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -10424,8 +10424,8 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
udelay(10);
- /* 250 usec to allow enough time on some 10/100 Mbps devices. */
- for (i = 0; i < 25; i++) {
+ /* 350 usec to allow enough time on some 10/100 Mbps devices. */
+ for (i = 0; i < 35; i++) {
tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
coal_now);
--
1.6.4.4
^ permalink raw reply related
* [PATCH 11/20] broadcom: Isolate phy dsp accesses
From: Matt Carlson @ 2009-11-03 0:28 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch consolidates the code that requires the SMDSP clock to be
enabled into a single function that (hopefully) makes the dependency
obvious.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 90 ++++++++++++++++++++-----------------------
1 files changed, 42 insertions(+), 48 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index f81e532..9e574ce 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -237,53 +237,78 @@ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
}
+/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
static int bcm50610_a0_workaround(struct phy_device *phydev)
{
int err;
- err = bcm54xx_auxctl_write(phydev,
- MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
- MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
- MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
- if (err < 0)
- return err;
-
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
MII_BCM54XX_EXP_EXP08_RJCT_2MHZ |
MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE);
if (err < 0)
- goto error;
+ return err;
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
if (err < 0)
- goto error;
+ return err;
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
if (err < 0)
- goto error;
+ return err;
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
MII_BCM54XX_EXP_EXP75_VDACCTRL);
if (err < 0)
- goto error;
+ return err;
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
MII_BCM54XX_EXP_EXP96_MYST);
if (err < 0)
- goto error;
+ return err;
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
MII_BCM54XX_EXP_EXP97_MYST);
+ return err;
+}
+
+static int bcm54xx_phydsp_config(struct phy_device *phydev)
+{
+ int err, err2;
+
+ /* Enable the SMDSP clock */
+ err = bcm54xx_auxctl_write(phydev,
+ MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
+ MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
+ MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
+ if (err < 0)
+ return err;
+
+ if (phydev->drv->phy_id == PHY_ID_BCM50610)
+ err = bcm50610_a0_workaround(phydev);
+
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
+ int val;
+
+ val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
+ if (val < 0)
+ goto error;
+
+ val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
+ err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
+ }
+
error:
- bcm54xx_auxctl_write(phydev,
- MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
- MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
+ /* Disable the SMDSP clock */
+ err2 = bcm54xx_auxctl_write(phydev,
+ MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
+ MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
- return err;
+ /* Return the first error reported. */
+ return err ? err : err2;
}
static int bcm54xx_config_init(struct phy_device *phydev)
@@ -308,38 +333,7 @@ static int bcm54xx_config_init(struct phy_device *phydev)
if (err < 0)
return err;
- if (phydev->drv->phy_id == PHY_ID_BCM50610) {
- err = bcm50610_a0_workaround(phydev);
- if (err < 0)
- return err;
- }
-
- if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
- int err2;
-
- err = bcm54xx_auxctl_write(phydev,
- MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
- MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
- MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
- if (err < 0)
- return err;
-
- reg = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
- if (reg < 0)
- goto error;
-
- reg |= MII_BCM54XX_EXP_EXP75_CM_OSC;
- err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, reg);
-
-error:
- err2 = bcm54xx_auxctl_write(phydev,
- MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
- MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
- if (err)
- return err;
- if (err2)
- return err2;
- }
+ bcm54xx_phydsp_config(phydev);
return 0;
}
--
1.6.4.4
^ permalink raw reply related
* [PATCH 12/20] broadcom: Fix slow link problem
From: Matt Carlson @ 2009-11-03 0:28 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
When a 50610 or 50610M is paired against particular remote partners,
link is slow to come up. This patch works around the problem.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 22 ++++++++++++++--------
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 9e574ce..1a2b2f2 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -242,12 +242,6 @@ static int bcm50610_a0_workaround(struct phy_device *phydev)
{
int err;
- err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
- MII_BCM54XX_EXP_EXP08_RJCT_2MHZ |
- MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE);
- if (err < 0)
- return err;
-
err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
@@ -287,8 +281,20 @@ static int bcm54xx_phydsp_config(struct phy_device *phydev)
if (err < 0)
return err;
- if (phydev->drv->phy_id == PHY_ID_BCM50610)
- err = bcm50610_a0_workaround(phydev);
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
+ BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
+ /* Clear bit 9 to fix a phy interop issue. */
+ err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
+ MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
+ if (err < 0)
+ goto error;
+
+ if (phydev->drv->phy_id == PHY_ID_BCM50610) {
+ err = bcm50610_a0_workaround(phydev);
+ if (err < 0)
+ goto error;
+ }
+ }
if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
int val;
--
1.6.4.4
^ permalink raw reply related
* [PATCH 13/20] tg3: Add 50610M phy ID for 5785
From: Matt Carlson @ 2009-11-03 0:29 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch adds the 50610M phy ID for 5785.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 2 ++
drivers/net/tg3.h | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 7bebb47..0aecd07 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -940,6 +940,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
case TG3_PHY_ID_BCM50610:
+ case TG3_PHY_ID_BCM50610M:
val = MAC_PHYCFG2_50610_LED_MODES;
break;
case TG3_PHY_ID_BCMAC131:
@@ -1098,6 +1099,7 @@ static int tg3_mdio_init(struct tg3 *tp)
phydev->interface = PHY_INTERFACE_MODE_GMII;
break;
case TG3_PHY_ID_BCM50610:
+ case TG3_PHY_ID_BCM50610M:
if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 9999345..d770da1 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2864,6 +2864,7 @@ struct tg3 {
#define PHY_REV_BCM5401_C0 0x6
#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
#define TG3_PHY_ID_BCM50610 0x143bd60
+#define TG3_PHY_ID_BCM50610M 0x143bd70
#define TG3_PHY_ID_BCMAC131 0x143bc70
#define TG3_PHY_ID_RTL8211C 0x001cc910
#define TG3_PHY_ID_RTL8201E 0x00008200
--
1.6.4.4
^ permalink raw reply related
* [PATCH 16/20] tg3 / broadcom: Refine AC131 APD support
From: Matt Carlson @ 2009-11-03 0:31 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
Auto power-down (APD) support is a power-saving feature. It should be
selectively enabled since it might expose MAC bugs. This patch changes
the code to enable APD only if the PHY_BRCM_AUTO_PWRDWN_ENABLE flag is
set. The tg3 driver was changed to set this bit.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 8 +++++---
drivers/net/tg3.c | 1 +
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 5d2a2e9..bddf4a4 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -561,9 +561,11 @@ static int brcm_fet_config_init(struct phy_device *phydev)
if (err < 0)
goto done;
- /* Enable auto power down */
- err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
- MII_BRCM_FET_SHDW_AS2_APDE);
+ if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
+ /* Enable auto power down */
+ err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
+ MII_BRCM_FET_SHDW_AS2_APDE);
+ }
done:
/* Disable shadow register access */
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e7128f6..592b5bf 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1114,6 +1114,7 @@ static int tg3_mdio_init(struct tg3 *tp)
case TG3_PHY_ID_RTL8201E:
case TG3_PHY_ID_BCMAC131:
phydev->interface = PHY_INTERFACE_MODE_MII;
+ phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
break;
}
--
1.6.4.4
^ permalink raw reply related
* [PATCH 14/20] broadcom: Consolidate dev_flags definitions
From: Matt Carlson @ 2009-11-03 0:30 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch moves all the dev_flags enumerations outside the broadcom.c
file to include/linux/brcmphy.h. The existing flags were not used yet
and have been re-enumerated to avoid conflicts.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 11 +----------
include/linux/brcmphy.h | 17 +++++++++++------
2 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 1a2b2f2..ace0ccc 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/phy.h>
+#include <linux/brcmphy.h>
#define PHY_ID_BCM50610 0x0143bd60
#define PHY_ID_BCM50610M 0x0143bd70
@@ -138,16 +139,6 @@
#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
-/*
- * Device flags for PHYs that can be configured for different operating
- * modes.
- */
-#define PHY_BCM_FLAGS_VALID 0x80000000
-#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
-#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
-#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
-#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
-
/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 9b64b6d..daa1480 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -1,6 +1,11 @@
-#define PHY_BRCM_WIRESPEED_ENABLE 0x00000001
-#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000002
-#define PHY_BRCM_APD_CLK125_ENABLE 0x00000004
-#define PHY_BRCM_STD_IBND_DISABLE 0x00000008
-#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00000010
-#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00000020
+#define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
+#define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
+#define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
+#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
+#define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
+#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
+#define PHY_BRCM_APD_CLK125_ENABLE 0x00000400
+#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
+#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
+#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
+#define PHY_BCM_FLAGS_VALID 0x80000000
--
1.6.4.4
^ permalink raw reply related
* [PATCH 15/20] tg3 / broadcom: Add PHY_BRCM_CLEAR_RGMII_MODE flag
From: Matt Carlson @ 2009-11-03 0:30 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
Broadcom 50610M parts changed the default definitions of the RGMII mode
shadow register. The 5785 needs the RGMII mode selection bits [4:3]
cleared.
The default value of the remaining bits in this register are zero.
Rather than unnecessarily burn an extra bit in the dev_flags member in
an attempt to enumerate all possible combinations, this patch take a
more course grained approach and labels the option as "clear all bits".
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 6 ++++++
drivers/net/tg3.c | 1 +
include/linux/brcmphy.h | 1 +
3 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index ace0ccc..5d2a2e9 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -105,6 +105,7 @@
#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
/* LED1 / ~LINKSPD[1] selector */
#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
+#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
@@ -330,6 +331,11 @@ static int bcm54xx_config_init(struct phy_device *phydev)
if (err < 0)
return err;
+ if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
+ BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
+ (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
+ bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
+
bcm54xx_phydsp_config(phydev);
return 0;
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 0aecd07..e7128f6 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1100,6 +1100,7 @@ static int tg3_mdio_init(struct tg3 *tp)
break;
case TG3_PHY_ID_BCM50610:
case TG3_PHY_ID_BCM50610M:
+ phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index daa1480..6e7ffce 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -8,4 +8,5 @@
#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
+#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
#define PHY_BCM_FLAGS_VALID 0x80000000
--
1.6.4.4
^ permalink raw reply related
* [PATCH 17/20] tg3 / broadcom: Add code to disable rxc refclk
From: Matt Carlson @ 2009-11-03 0:31 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
The 5785 does not use the RXC reference clock. Turning it off is
desirable as it saves power.
By default, the 50610 enables the RXC reference clock and the 50610M
disables it. Presumably this is one of the reasons why the hardware
architect chose one over the other.
Adding a "rx reference clock disable" flag is not the ideal way to
describe the option, as it would force the MAC using a 50610M to set
the flag. Ideally we want the flags to represent opt-in behavior that
deviates from hardware defaults. Furthermore, the lack of a
"disable" flag implies that the requester wants the rx reference clock
enabled, which doesn't necessarily follow.
By presenting the option as a passive statement (rx reference clock
unused) rather than a command, I hope to convey an opt-in option to
disable the rx reference clock that falls back to hardware defaults if
not set. A secondary benefit of this is that it keeps the
intelligence about phy defaults in the broadcom module where it belongs
and allows the broadcom module more latitude should a bug arise.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 43 +++++++++++++++++++++++++++++++++++++++++++
drivers/net/tg3.c | 3 ++-
include/linux/brcmphy.h | 2 +-
3 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index bddf4a4..7491433 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -25,6 +25,9 @@
#define BRCM_PHY_MODEL(phydev) \
((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
+#define BRCM_PHY_REV(phydev) \
+ ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
+
#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
@@ -95,11 +98,16 @@
#define BCM_LED_SRC_OFF 0xe /* Tied high */
#define BCM_LED_SRC_ON 0xf /* Tied low */
+
/*
* BCM5482: Shadow registers
* Shadow values go into bits [14:10] of register 0x1c to select a shadow
* register to access.
*/
+/* 00101: Spare Control Register 3 */
+#define BCM54XX_SHD_SCR3 0x05
+#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
+
#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
/* LED3 / ~LINKSPD[2] selector */
#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
@@ -112,6 +120,7 @@
#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
+
/*
* EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
*/
@@ -309,6 +318,37 @@ error:
return err ? err : err2;
}
+static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
+{
+ u32 val, orig;
+
+ /* Abort if we are using an untested phy. */
+ if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 ||
+ BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
+ return;
+
+ val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
+ if (val < 0)
+ return;
+
+ orig = val;
+
+ if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
+ if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
+ BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
+ BRCM_PHY_REV(phydev) >= 0x3) {
+ /* Here, bit 0 _disables_ CLK125 when set */
+ val |= BCM54XX_SHD_SCR3_DEF_CLK125;
+ } else {
+ /* Here, bit 0 _enables_ CLK125 when set */
+ val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
+ }
+ }
+
+ if (orig != val)
+ bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
+}
+
static int bcm54xx_config_init(struct phy_device *phydev)
{
int reg, err;
@@ -336,6 +376,9 @@ static int bcm54xx_config_init(struct phy_device *phydev)
(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
+ if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)
+ bcm54xx_adjust_rxrefclk(phydev);
+
bcm54xx_phydsp_config(phydev);
return 0;
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 592b5bf..369ddba 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1100,7 +1100,8 @@ static int tg3_mdio_init(struct tg3 *tp)
break;
case TG3_PHY_ID_BCM50610:
case TG3_PHY_ID_BCM50610M:
- phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE;
+ phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
+ PHY_BRCM_RX_REFCLK_UNUSED;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 6e7ffce..5943227 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -4,7 +4,7 @@
#define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
#define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
#define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
-#define PHY_BRCM_APD_CLK125_ENABLE 0x00000400
+#define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
#define PHY_BRCM_STD_IBND_DISABLE 0x00000800
#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
--
1.6.4.4
^ permalink raw reply related
* [PATCH 19/20] tg3 / broadcom: Optionally disable TXC if no link
From: Matt Carlson @ 2009-11-03 0:32 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch adds code to disable the TXC and RXC reference clocks if link
is not available.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 5 +++++
drivers/net/tg3.c | 1 +
include/linux/brcmphy.h | 1 +
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 7b10495..f63c96a 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -108,6 +108,7 @@
#define BCM54XX_SHD_SCR3 0x05
#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
+#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
/* 01010: Auto Power-Down */
#define BCM54XX_SHD_APD 0x0a
@@ -362,6 +363,9 @@ static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
else
val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
+ if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
+ val |= BCM54XX_SHD_SCR3_TRDDAPD;
+
if (orig != val)
bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
@@ -409,6 +413,7 @@ static int bcm54xx_config_init(struct phy_device *phydev)
bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
+ (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f74bf91..50bb53d 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1103,6 +1103,7 @@ static int tg3_mdio_init(struct tg3 *tp)
case TG3_PHY_ID_BCM50610M:
phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
PHY_BRCM_RX_REFCLK_UNUSED |
+ PHY_BRCM_DIS_TXCRXC_NOENRGY |
PHY_BRCM_AUTO_PWRDWN_ENABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 5943227..2b31b91 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -9,4 +9,5 @@
#define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
+#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
#define PHY_BCM_FLAGS_VALID 0x80000000
--
1.6.4.4
^ permalink raw reply related
* [PATCH 18/20] tg3 / broadcom: Add APD support for GPHYs
From: Matt Carlson @ 2009-11-03 0:32 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch adds an RXC auto power-down feature to the code that supports
the gphys.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/phy/broadcom.c | 51 ++++++++++++++++++++++++++++++++++++-------
drivers/net/tg3.c | 4 ++-
2 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 7491433..7b10495 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -107,6 +107,11 @@
/* 00101: Spare Control Register 3 */
#define BCM54XX_SHD_SCR3 0x05
#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
+#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
+
+/* 01010: Auto Power-Down */
+#define BCM54XX_SHD_APD 0x0a
+#define BCM54XX_SHD_APD_EN 0x0020
#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
/* LED3 / ~LINKSPD[2] selector */
@@ -321,9 +326,11 @@ error:
static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
{
u32 val, orig;
+ bool clk125en = true;
/* Abort if we are using an untested phy. */
- if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 ||
+ if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 ||
+ BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 ||
BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
return;
@@ -333,20 +340,45 @@ static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
orig = val;
- if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
- if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
- BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
- BRCM_PHY_REV(phydev) >= 0x3) {
- /* Here, bit 0 _disables_ CLK125 when set */
- val |= BCM54XX_SHD_SCR3_DEF_CLK125;
- } else {
+ if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
+ BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
+ BRCM_PHY_REV(phydev) >= 0x3) {
+ /*
+ * Here, bit 0 _disables_ CLK125 when set.
+ * This bit is set by default.
+ */
+ clk125en = false;
+ } else {
+ if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
/* Here, bit 0 _enables_ CLK125 when set */
val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
+ clk125en = false;
}
}
+ if (clk125en == false ||
+ (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
+ val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
+ else
+ val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
+
if (orig != val)
bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
+
+ val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
+ if (val < 0)
+ return;
+
+ orig = val;
+
+ if (clk125en == false ||
+ (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
+ val |= BCM54XX_SHD_APD_EN;
+ else
+ val &= ~BCM54XX_SHD_APD_EN;
+
+ if (orig != val)
+ bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
}
static int bcm54xx_config_init(struct phy_device *phydev)
@@ -376,7 +408,8 @@ static int bcm54xx_config_init(struct phy_device *phydev)
(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
- if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)
+ if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
+ (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev);
bcm54xx_phydsp_config(phydev);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 369ddba..f74bf91 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1097,11 +1097,13 @@ static int tg3_mdio_init(struct tg3 *tp)
switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
case TG3_PHY_ID_BCM57780:
phydev->interface = PHY_INTERFACE_MODE_GMII;
+ phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
break;
case TG3_PHY_ID_BCM50610:
case TG3_PHY_ID_BCM50610M:
phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
- PHY_BRCM_RX_REFCLK_UNUSED;
+ PHY_BRCM_RX_REFCLK_UNUSED |
+ PHY_BRCM_AUTO_PWRDWN_ENABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
--
1.6.4.4
^ permalink raw reply related
* [PATCH 20/20] tg3: Update version to 3.103
From: Matt Carlson @ 2009-11-03 0:33 UTC (permalink / raw)
To: davem; +Cc: netdev, andy
This patch updates the tg3 version to 3.103.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/tg3.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 50bb53d..47a4f09 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.102"
-#define DRV_MODULE_RELDATE "September 1, 2009"
+#define DRV_MODULE_VERSION "3.103"
+#define DRV_MODULE_RELDATE "November 2, 2009"
#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
--
1.6.4.4
^ permalink raw reply related
* Re: [PATCH net-next] iwmc3200bt: Add iwmc3200 bluetooth driver
From: Marcel Holtmann @ 2009-11-03 1:40 UTC (permalink / raw)
To: Tomas Winkler
Cc: davem, netdev, linux-bluetooth, linux-mmc, guy.cohen,
ron.rindjunsky
In-Reply-To: <1257204990-18669-1-git-send-email-tomas.winkler@intel.com>
Hi Dave,
> Add Intel Wireless MultiCom 3200 SDIO BT driver
> IWMC3200 is 4Wireless Com CHIP (GPS/BT/WiFi/WiMAX).
> wmc3200bt is derived from btsdio driver
just a heads up, this is not a net-next patch. This clearly goes via
proper review on linux-bluetooth and bluetooth-next tree first. So
please don't pull until I ack it.
Tomas, please try not to jump the gun here.
Regards
Marcel
^ permalink raw reply
* [PATCH 0/1] ARM: TI DaVinci EMAC -- Correct param for EMAC ISR from net poll controller
From: Tonyliu @ 2009-11-03 1:50 UTC (permalink / raw)
To: khilman; +Cc: davinci-linux-open-source, netdev
Summary: ARM: TI DaVinci EMAC -- Correct param for EMAC ISR from net
poll controller
Comments :
---------------------------------------------
See patch header.
Tony
^ permalink raw reply
* [PATCH 1/1] DaVinci EMAC: correct param for ISR
From: Tonyliu @ 2009-11-03 1:52 UTC (permalink / raw)
To: khilman; +Cc: davinci-linux-open-source-bounces, netdev
[-- Attachment #1: Type: text/plain, Size: 1 bytes --]
[-- Attachment #2: 0001-DaVinci-EMAC-correct-param-for-ISR.patch --]
[-- Type: text/x-patch, Size: 1050 bytes --]
>From bf855d3a1f824ab87933a64c9fc93f859b064e92 Mon Sep 17 00:00:00 2001
From: Tonyliu <Bo.Liu@windriver.com>
Date: Wed, 28 Oct 2009 11:06:48 +0800
Subject: [PATCH 1/1] DaVinci EMAC: correct param for ISR
emac_irq is declared as:
static irqreturn_t emac_irq(int irq, void *dev_id)
{
struct net_device *ndev = (struct net_device *)dev_id;
struct emac_priv *priv = netdev_priv(ndev);
...
Clearly emac_irq() needs "struct net_device *" as "void *dev_id", so correct this.
Signed-off-by: Tonyliu <Bo.Liu@windriver.com>
---
drivers/net/davinci_emac.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index a876dce..4cf80ec 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -2217,7 +2217,7 @@ void emac_poll_controller(struct net_device *ndev)
struct emac_priv *priv = netdev_priv(ndev);
emac_int_disable(priv);
- emac_irq(ndev->irq, priv);
+ emac_irq(ndev->irq, ndev);
emac_int_enable(priv);
}
#endif
--
1.5.5.4
^ permalink raw reply related
* [PATCH] sch_htb.c consume the classes's tokens bellow the HTB_CAN_SEND level
From: Changli Gao @ 2009-11-03 2:41 UTC (permalink / raw)
To: Jamal Hadi Salim; +Cc: devik, netdev, xiaosuo
sch_htb.c consume the classes's tokens bellow the HTB_CAN_SEND level.
When a class enters HTB_MAY_BORROW state, it relies on its parents to
sent packets. The parent class in HTB_CAN_SEND state only consumes
itself and its parents's tokens, but ADD tokens to the classes under its
level. It is totally wrong. It means that a class, which sends packets
in ceil rate, can also enter HTB_CAN_SEND state now and then.
Signed-off-by: Changli Gao <xiaosuo@gmail.com>
----
net/sched/sch_htb.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/net/sched/sch_htb.c b/net/sched/sch_htb.c
index 85acab9..2705702 100644
--- a/net/sched/sch_htb.c
+++ b/net/sched/sch_htb.c
@@ -629,11 +629,10 @@ static void htb_charge_class(struct htb_sched *q, struct htb_class *cl,
if (cl->level >= level) {
if (cl->level == level)
cl->xstats.lends++;
- htb_accnt_tokens(cl, bytes, diff);
} else {
cl->xstats.borrows++;
- cl->tokens += diff; /* we moved t_c; update tokens */
}
+ htb_accnt_tokens(cl, bytes, diff);
htb_accnt_ctokens(cl, bytes, diff);
cl->t_c = q->now;
^ permalink raw reply related
* RE: Subject: [PATCH 1/6] bna: Brocade 10Gb Ethernet device driver
From: Debashis Dutt @ 2009-11-03 3:05 UTC (permalink / raw)
To: Stephen Hemminger, Rasesh Mody
Cc: netdev@vger.kernel.org, Adapter Linux Open SRC Team
In-Reply-To: <20091101111954.6cd2d569@nehalam>
Hi Stephen,
Thanks for your feedback. Please
see the responses inline.
Thanks
-----Original Message-----
From: Stephen Hemminger [mailto:shemminger@vyatta.com]
Sent: Sunday, November 01, 2009 11:20 AM
To: Rasesh Mody
Cc: netdev@vger.kernel.org; Adapter Linux Open SRC Team
Subject: Re: Subject: [PATCH 1/6] bna: Brocade 10Gb Ethernet device driver
Too many configuration optons?
[Debashis]
Yes, we are working on incorporating your feedback.
On Sat, 31 Oct 2009 22:03:14 -0700
Rasesh Mody <rmody@brocade.com> wrote:
> +
> +#ifdef BNAD_NO_IP_ALIGN
> +#define BNAD_NET_IP_ALIGN 0
> +#else
> +#define BNAD_NET_IP_ALIGN NET_IP_ALIGN
> +#endif
>
Why is this device special?
[Debashis]
Will remove
> +
> +
> +#define BNAD_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
> +
Module parameters mean the hardware or the developer could not
decide how to do it right. Please reduce or eliminate most of these.
> +static uint bnad_msix = 1;
> +module_param(bnad_msix, uint, 0444);
> +MODULE_PARM_DESC(bnad_msix, "Enable MSI-X");
If msi-X is available use it, if not then don't. User can handle
this globally with kernel command line option.
> +uint bnad_small_large_rxbufs = 1;
> +module_param(bnad_small_large_rxbufs, uint, 0444);
> +MODULE_PARM_DESC(bnad_small_large_rxbufs, "Enable small/large buffer receive");
Do or do not, please no config option. The ideal case is:
normal MTU == skb
jumbo MTU = skb with fragmenets
[Debashis]
Will address this.
> +static uint bnad_rxqsets_used;
> +module_param(bnad_rxqsets_used, uint, 0444);
> +MODULE_PARM_DESC(bnad_rxqsets_used, "Number of RxQ sets to be used");
> +
> +static uint bnad_ipid_mode;
> +module_param(bnad_ipid_mode, uint, 0444);
> +MODULE_PARM_DESC(bnad_ipid_mode, "0 - Use IP ID 0x0000 - 0x7FFF for LSO; "
> + "1 - Use full range of IP ID for LSO");
Gack!
[Debashis]
Will remove this
> +uint bnad_txq_depth = BNAD_ENTRIES_PER_TXQ;
> +module_param(bnad_txq_depth, uint, 0444);
> +MODULE_PARM_DESC(bnad_txq_depth, "Maximum number of entries per TxQ");
Should be ethtool configuration not module parameters
[Debashis]
Yes, sure.
> +uint bnad_rxq_depth = BNAD_ENTRIES_PER_RXQ;
> +module_param(bnad_rxq_depth, uint, 0444);
> +MODULE_PARM_DESC(bnad_rxq_depth, "Maximum number of entries per RxQ");
> +
> +static uint bnad_vlan_strip = 1;
> +module_param(bnad_vlan_strip, uint, 0444);
> +MODULE_PARM_DESC(bnad_vlan_strip, "Let the hardware strip off VLAN header");
Just do VLAN acceleration.
[Debashis]
Yes, sure
> +static uint bnad_log_level = LOG_WARN_LEVEL;
> +module_param(bnad_log_level, uint, 0644);
> +MODULE_PARM_DESC(bnad_log_level, "Log level");
Use ethtool msg_level for this
[Debashis]
Will do.
> +static uint bnad_ioc_auto_recover = 1;
> +module_param(bnad_ioc_auto_recover, uint, 0644);
> +MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable auto recovery");
Why is this configurable?
[Debashis]
Auto-recovery is used to recover automatically from a f/w failure.
Disabling this helps preserve the state of the system/driver in case of a f/w failure
--
^ permalink raw reply
* RE: Subject: [PATCH 1/6] bna: Brocade 10Gb Ethernet device driver
From: Debashis Dutt @ 2009-11-03 3:14 UTC (permalink / raw)
To: Stephen Hemminger, Joe Perches
Cc: Rasesh Mody, netdev@vger.kernel.org, Adapter Linux Open SRC Team,
Greg Kroah-Hartman
In-Reply-To: <20091101112553.1dc0e3a9@nehalam>
Hi Stephen,
This driver is written explicitly for Linux and we are working on addressing your
comments.
Please let us know, if we need to look at some other areas.
Thanks
--Debashis
-----Original Message-----
From: Stephen Hemminger [mailto:shemminger@vyatta.com]
Sent: Sunday, November 01, 2009 11:26 AM
To: Joe Perches
Cc: Rasesh Mody; netdev@vger.kernel.org; Adapter Linux Open SRC Team; Greg Kroah-Hartman
Subject: Re: Subject: [PATCH 1/6] bna: Brocade 10Gb Ethernet device driver
On Sat, 31 Oct 2009 22:23:59 -0700
Joe Perches <joe@perches.com> wrote:
> There are an awful lot of non linux standard
> uses in this code set.
>
> Perhaps staging would be a good place to start?
>
Yup, it looks like a Windows driver port
^ permalink raw reply
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