* Re: [PATCH] ixgbe: refactor ixgbe_alloc_queues()
From: Jeff Kirsher @ 2010-10-29 7:46 UTC (permalink / raw)
To: Eric Dumazet
Cc: Tantilov, Emil S, David Miller, Waskiewicz Jr, Peter P,
Brattain, Ross B, netdev
In-Reply-To: <1288323933.2711.43.camel@edumazet-laptop>
On Thu, Oct 28, 2010 at 20:45, Eric Dumazet <eric.dumazet@gmail.com> wrote:
> Note : compiled only patch, not tested.
>
> Thanks !
>
> [PATCH] ixgbe: refactor ixgbe_alloc_queues()
>
> I noticed ring variable was initialized before allocations, and that
> memory node management was a bit ugly. We also leak memory in case of
> ring allocations error.
>
> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
> ---
> drivers/net/ixgbe/ixgbe_main.c | 69 ++++++++++++-------------------
> 1 file changed, 28 insertions(+), 41 deletions(-)
>
Thanks Eric. I will add this to my queue of patches.
--
Cheers,
Jeff
^ permalink raw reply
* Re: [RFC PATCH 1/1] vhost: TX used buffer guest signal accumulation
From: Michael S. Tsirkin @ 2010-10-29 8:03 UTC (permalink / raw)
To: Shirley Ma; +Cc: David Miller, netdev, kvm, linux-kernel
In-Reply-To: <1288294355.11251.20.camel@localhost.localdomain>
On Thu, Oct 28, 2010 at 12:32:35PM -0700, Shirley Ma wrote:
> On Thu, 2010-10-28 at 07:20 +0200, Michael S. Tsirkin wrote:
> > My concern is this can delay signalling for unlimited time.
> > Could you pls test this with guests that do not have
> > 2b5bbe3b8bee8b38bdc27dd9c0270829b6eb7eeb
> > b0c39dbdc204006ef3558a66716ff09797619778
> > that is 2.6.31 and older?
>
> The patch only induces delay signaling unlimited time when there is no
> TX packet to transmit. I thought TX signaling only noticing guest to
> release the used buffers, anything else beside this?
Right, that's it I think. For newer kernels we orphan the skb
on xmit so we don't care that much about completing them.
This does rely on an undocumented assumption about guest
behaviour though.
> I tested rhel5u5 guest (2.6.18 kernel), it works fine. I checked the two
> commits log, I don't think this patch could cause any issue w/o these
> two patches.
>
> Also I found a big TX regression for old guest and new guest. For old
> guest, I am able to get almost 11Gb/s for 2K message size, but for the
> new guest kernel, I can only get 3.5 Gb/s with the patch and same host.
> I will dig it why.
>
> thanks
> Shirley
^ permalink raw reply
* Re: [RFC PATCH 1/1] vhost: TX used buffer guest signal accumulation
From: Michael S. Tsirkin @ 2010-10-29 8:10 UTC (permalink / raw)
To: Shirley Ma; +Cc: David Miller, netdev, kvm, linux-kernel
In-Reply-To: <1288286062.11251.15.camel@localhost.localdomain>
On Thu, Oct 28, 2010 at 10:14:22AM -0700, Shirley Ma wrote:
>
> > Two ideas:
> > 1. How about writing out used, just delaying the signal?
> > This way we don't have to queue separately.
>
> This improves some performance, but not as good as delaying
> both used and signal. Since delaying used buffers combining
> multiple small copies to a large copy, which saves more CPU
> utilization and increased some BW.
Hmm. I don't yet understand. We are still doing copies into the per-vq
buffer, and the data copied is really small. Is it about cache line
bounces? Could you try figuring it out?
> > 2. How about flushing out queued stuff before we exit
> > the handle_tx loop? That would address most of
> > the spec issue.
>
> The performance is almost as same as the previous patch. I will resubmit
> the modified one, adding vhost_add_used_and_signal_n after handle_tx
> loop for processing pending queue.
>
> This patch was a part of modified macvtap zero copy which I haven't
> submitted yet. I found this helped vhost TX in general. This pending
> queue will be used by DMA done later, so I put it in vq instead of a
> local variable in handle_tx.
>
> Thanks
> Shirley
BTW why do we need another array? Isn't heads field exactly what we need
here?
^ permalink raw reply
* Re: [RFC PATCH 1/1] vhost: TX used buffer guest signal accumulation
From: Michael S. Tsirkin @ 2010-10-29 8:11 UTC (permalink / raw)
To: Shirley Ma; +Cc: Sridhar Samudrala, David Miller, netdev, kvm, linux-kernel
In-Reply-To: <1288302050.11251.26.camel@localhost.localdomain>
On Thu, Oct 28, 2010 at 02:40:50PM -0700, Shirley Ma wrote:
> On Thu, 2010-10-28 at 14:04 -0700, Sridhar Samudrala wrote:
> > It would be some change in virtio-net driver that may have improved
> > the
> > latency of small messages which in turn would have reduced the
> > bandwidth
> > as TCP could not accumulate and send large packets.
>
> I will check out any latency improvement patch in virtio_net. If that's
> the case, whether it is good to have some tunable parameter to benefit
> both BW and latency workload?
>
> Shirley
No, we need it to work well automatically somehow.
--
MST
^ permalink raw reply
* Re: [RFC PATCH 1/1] vhost: TX used buffer guest signal accumulation
From: Michael S. Tsirkin @ 2010-10-29 8:12 UTC (permalink / raw)
To: Shirley Ma; +Cc: David Miller, netdev, kvm, linux-kernel
In-Reply-To: <1288296835.11251.24.camel@localhost.localdomain>
On Thu, Oct 28, 2010 at 01:13:55PM -0700, Shirley Ma wrote:
> On Thu, 2010-10-28 at 12:32 -0700, Shirley Ma wrote:
> > Also I found a big TX regression for old guest and new guest. For old
> > guest, I am able to get almost 11Gb/s for 2K message size, but for the
> > new guest kernel, I can only get 3.5 Gb/s with the patch and same
> > host.
> > I will dig it why.
>
> The regression is from guest kernel, not from this patch. Tested 2.6.31
> kernel, it's performance is less than 2Gb/s for 2K message size already.
> I will resubmit the patch for review.
>
> I will start to test from 2.6.30 kernel to figure it when TX regression
> induced in virtio_net. Any suggestion which guest kernel I should test
> to figure out this regression?
>
> Thanks
> Shirley
git bisect 2.6.31 2.6.30
and go from here.
^ permalink raw reply
* Re: [PATCH] ixgbe: refactor ixgbe_alloc_queues()
From: Jeff Kirsher @ 2010-10-29 8:38 UTC (permalink / raw)
To: Eric Dumazet
Cc: Tantilov, Emil S, David Miller, Waskiewicz Jr, Peter P,
Brattain, Ross B, netdev
In-Reply-To: <1288323933.2711.43.camel@edumazet-laptop>
On Thu, Oct 28, 2010 at 20:45, Eric Dumazet <eric.dumazet@gmail.com> wrote:
> Note : compiled only patch, not tested.
>
> Thanks !
>
> [PATCH] ixgbe: refactor ixgbe_alloc_queues()
>
> I noticed ring variable was initialized before allocations, and that
> memory node management was a bit ugly. We also leak memory in case of
> ring allocations error.
>
> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
> ---
> drivers/net/ixgbe/ixgbe_main.c | 69 ++++++++++++-------------------
> 1 file changed, 28 insertions(+), 41 deletions(-)
>
I noticed a typo when applying the patch and I fixed it in the patch
in my queue.
The following code:
> + while (rx)
> + kfree(adapter->tx_ring[--rx]);
> +
should be:
> + while (rx)
> + kfree(adapter->rx_ring[--rx]);
> +
--
Cheers,
Jeff
^ permalink raw reply
* Re: [PATCH] ixgbe: refactor ixgbe_alloc_queues()
From: Eric Dumazet @ 2010-10-29 8:48 UTC (permalink / raw)
To: Jeff Kirsher
Cc: Tantilov, Emil S, David Miller, Waskiewicz Jr, Peter P,
Brattain, Ross B, netdev
In-Reply-To: <AANLkTinKQccHsA++PG86h5x3smJx75EB05YnHq2tGM-R@mail.gmail.com>
Le vendredi 29 octobre 2010 à 01:38 -0700, Jeff Kirsher a écrit :
>
> I noticed a typo when applying the patch and I fixed it in the patch
> in my queue.
>
> The following code:
> > + while (rx)
> > + kfree(adapter->tx_ring[--rx]);
> > +
>
> should be:
> > + while (rx)
> > + kfree(adapter->rx_ring[--rx]);
> > +
>
Good catch, thanks !
^ permalink raw reply
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To: netdev
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^ permalink raw reply
* RE: [RFC net-next] caif: code cleanup
From: Sjur BRENDELAND @ 2010-10-29 9:36 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev@vger.kernel.org, Andre Carvalho DE MATOS
In-Reply-To: <20101019095553.0b413b80@nehalam>
Hi Stephen,
> Stephen Hemminger wrote:
> >
> > Cleanup of new CAIF code.
> > * make local functions static
> > * remove code that is never used
> > * expand get_caif_conf() since wrapper is no longer needed
> > * make args to comparison functions const
> > * rename connect_req_to_link_param to keep exported names
> > consistent
>
> Thank you for your patch.
> We'll try to test this sometime next week,
> and get back to you.
Sorry for taking so long to respond.
We have passed our tests on your RFC.
I'll ack this if you send a patch.
Regards,
Sjur
^ permalink raw reply
* Re: [PATCH 0/15] RFC: create drivers/net/legacy for ISA, EISA, MCA drivers
From: David Lamparter @ 2010-10-29 9:40 UTC (permalink / raw)
To: Joe Perches; +Cc: netdev
In-Reply-To: <1288316896.1836.41.camel@Joe-Laptop>
On Thu, Oct 28, 2010 at 06:48:16PM -0700, Joe Perches wrote:
> On Thu, 2010-10-28 at 21:19 -0400, Paul Gortmaker wrote:
> > The initial target is things like ISA/EISA/MCA drivers, and with
> > that alone, we can get close to 90 files out of drivers/net.
> > Plus, by having a semi-defined description for legacy as being
> > "drivers more than 10 years old" we'll always have a destination
> > for drivers as they fall out of maintainership and use.
>
> I think legacy is "old and not sold or used much anymore".
>
> I believe you're not moving 3c59x as that's relatively
> still popular even though it's nearly 15 years old.
>
> Or maybe that was just an oversight...
The 3c59x driver also drives a few not-that-old 100MBit cards like
"3Com Corporation 3c905B 100BaseTX [Cyclone] [10b7:9055] (rev 64)"
and these are quite common still :)
-David
^ permalink raw reply
* Re: [PATCH] virtio_net: Fix queue full check
From: Rusty Russell @ 2010-10-29 9:47 UTC (permalink / raw)
To: Krishna Kumar; +Cc: davem, netdev
In-Reply-To: <20101028051036.25340.23442.sendpatchset@krkumar2.in.ibm.com>
On Thu, 28 Oct 2010 03:40:36 pm Krishna Kumar wrote:
> I get many queue full errors being wrongly reported when running
> parallel netperfs:
>
> Oct 17 10:22:40 localhost kernel: net eth0: Unexpected TX queue failure: -28
> Oct 17 10:28:22 localhost kernel: net eth0: Unexpected TX queue failure: -28
> Oct 17 10:35:58 localhost kernel: net eth0: Unexpected TX queue failure: -28
> Oct 17 10:41:06 localhost kernel: net eth0: Unexpected TX queue failure: -28
>
> I initially changed the check from -ENOMEM to -ENOSPC, but
> virtqueue_add_buf can return only -ENOSPC when it doesn't have
> space for new request. Patch removes redundant checks but
> displays the failure errno.
>
> Signed-off-by: Krishna Kumar <krkumar2@in.ibm.com>
> ---
> drivers/net/virtio_net.c | 15 ++++-----------
> 1 file changed, 4 insertions(+), 11 deletions(-)
>
> diff -ruNp org/drivers/net/virtio_net.c new/drivers/net/virtio_net.c
> --- org/drivers/net/virtio_net.c 2010-10-11 10:20:02.000000000 +0530
> +++ new/drivers/net/virtio_net.c 2010-10-21 17:37:45.000000000 +0530
> @@ -570,17 +570,10 @@ static netdev_tx_t start_xmit(struct sk_
>
> /* This can happen with OOM and indirect buffers. */
> if (unlikely(capacity < 0)) {
> - if (net_ratelimit()) {
> - if (likely(capacity == -ENOMEM)) {
> - dev_warn(&dev->dev,
> - "TX queue failure: out of memory\n");
> - } else {
> - dev->stats.tx_fifo_errors++;
> - dev_warn(&dev->dev,
> - "Unexpected TX queue failure: %d\n",
> - capacity);
> - }
> - }
> + if (net_ratelimit())
> + dev_warn(&dev->dev,
> + "TX queue failure (%d): out of memory\n",
> + capacity);
Hold on... you were getting -ENOSPC, which shouldn't happen. What makes you
think it's out of memory?
Confused,
Rusty.
^ permalink raw reply
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^ permalink raw reply
* Re: [PATCH 0/15] RFC: create drivers/net/legacy for ISA, EISA, MCA drivers
From: Maciej W. Rozycki @ 2010-10-29 10:13 UTC (permalink / raw)
To: David Lamparter; +Cc: Joe Perches, netdev
In-Reply-To: <20101029094050.GA1835290@jupiter.n2.diac24.net>
On Fri, 29 Oct 2010, David Lamparter wrote:
> > > The initial target is things like ISA/EISA/MCA drivers, and with
> > > that alone, we can get close to 90 files out of drivers/net.
> > > Plus, by having a semi-defined description for legacy as being
> > > "drivers more than 10 years old" we'll always have a destination
> > > for drivers as they fall out of maintainership and use.
> >
> > I think legacy is "old and not sold or used much anymore".
> >
> > I believe you're not moving 3c59x as that's relatively
> > still popular even though it's nearly 15 years old.
> >
> > Or maybe that was just an oversight...
>
> The 3c59x driver also drives a few not-that-old 100MBit cards like
> "3Com Corporation 3c905B 100BaseTX [Cyclone] [10b7:9055] (rev 64)"
> and these are quite common still :)
What's the difference? -- that's a change of the name only you should be
proud of! ;)
I have seen plenty of these Vortex/Boomerang/Cyclone cards in various
configurations and still have a couple myself, but I fail to recall any
that would be less than 8 years old, which is about the age of my newest
FDDI stuff (updated by the manufacturer to universal PCI and HP-branded
because of the DEC/Compaq acquisition) which has been declared "obviously
obsolete", so why shouldn't this equipment be either? ;)
Maciej
^ permalink raw reply
* [RFC PATCH 1/2] Gemini: create platform device for ethernet in Raidsonic IB-4220B
From: Michał Mirosław @ 2010-10-29 10:23 UTC (permalink / raw)
To: Hans Ulli Kroll, Russell King, linux-arm-kernel, linux-kernel,
netdev
Cc: Paulius Zaleckas, Janos Laube
In-Reply-To: <cover.1288321597.git.mirq-linux@rere.qmqm.pl>
This is cherry-picked from:
git://git.berlios.de/gemini-board ib4220
Code by Paulius Zaleckas <paulius.zaleckas@gmail.com>
and Janos Laube <janos.dev@gmail.com>.
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
arch/arm/mach-gemini/board-nas4220b.c | 53 ++++++++++++++++++++++++++++++
arch/arm/mach-gemini/common.h | 2 +
arch/arm/mach-gemini/devices.c | 52 +++++++++++++++++++++++++++++
arch/arm/mach-gemini/include/mach/gmac.h | 21 ++++++++++++
4 files changed, 128 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-gemini/include/mach/gmac.h
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 2ba096d..ca6ec5a 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -26,6 +26,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
+#include <mach/gmac.h>
#include <mach/hardware.h>
#include <mach/global_reg.h>
@@ -91,13 +92,65 @@ static struct platform_device ib4220b_key_device = {
},
};
+static struct mdio_gpio_platform_data ib4220b_mdio = {
+ .mdc = 22,
+ .mdio = 21,
+ .phy_mask = ~(1 << 1),
+};
+
+static struct platform_device ib4220b_phy_device = {
+ .name = "mdio-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &ib4220b_mdio,
+ },
+};
+
+static struct gemini_gmac_platform_data ib4220b_gmac_data = {
+ .bus_id[0] = "0:01",
+ .interface[0] = PHY_INTERFACE_MODE_RGMII,
+};
+
+static void __init gmac_ib4220b_init(void)
+{
+ unsigned int val;
+
+ val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_IO_DRIVING_CTRL);
+ val |= (0x3 << GMAC0_PADS_SHIFT) | (0x3 << GMAC1_PADS_SHIFT);
+ __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_IO_DRIVING_CTRL);
+
+ val = (0x0 << GMAC0_RXDV_SKEW_SHIFT) | (0xf << GMAC0_RXC_SKEW_SHIFT) |
+ (0x7 << GMAC0_TXEN_SKEW_SHIFT) | (0xa << GMAC0_TXC_SKEW_SHIFT) |
+ (0x0 << GMAC1_RXDV_SKEW_SHIFT) | (0xf << GMAC1_RXC_SKEW_SHIFT) |
+ (0x7 << GMAC1_TXEN_SKEW_SHIFT) | (0xa << GMAC1_TXC_SKEW_SHIFT);
+ __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_GMAC_CTRL_SKEW_CTRL);
+
+ __raw_writel(0x77777777, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_GMAC0_DATA_SKEW_CTRL);
+ __raw_writel(0x77777777, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_GMAC1_DATA_SKEW_CTRL);
+
+ val = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_ARBITRATION1_CTRL) & ~BURST_LENGTH_MASK;
+ val |= (0x20 << BURST_LENGTH_SHIFT);
+ __raw_writel(val, IO_ADDRESS(GEMINI_GLOBAL_BASE) +
+ GLOBAL_ARBITRATION1_CTRL);
+}
+
static void __init ib4220b_init(void)
{
gemini_gpio_init();
+ gmac_ib4220b_init();
+
platform_register_uart();
platform_register_pflash(SZ_16M, NULL, 0);
platform_device_register(&ib4220b_led_device);
platform_device_register(&ib4220b_key_device);
+ platform_device_register(&ib4220b_phy_device);
+ platform_register_ethernet(&ib4220b_gmac_data);
}
MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 9392834..4eafed5 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -13,6 +13,7 @@
#define __GEMINI_COMMON_H__
struct mtd_partition;
+struct gemini_gmac_platform_data;
extern void gemini_map_io(void);
extern void gemini_init_irq(void);
@@ -21,6 +22,7 @@ extern void gemini_gpio_init(void);
/* Common platform devices registration functions */
extern int platform_register_uart(void);
+extern int platform_register_ethernet(struct gemini_gmac_platform_data *pdata);
extern int platform_register_pflash(unsigned int size,
struct mtd_partition *parts,
unsigned int nr_parts);
diff --git a/arch/arm/mach-gemini/devices.c b/arch/arm/mach-gemini/devices.c
index 6b52525..ead7ab1 100644
--- a/arch/arm/mach-gemini/devices.c
+++ b/arch/arm/mach-gemini/devices.c
@@ -17,6 +17,7 @@
#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/global_reg.h>
+#include <mach/gmac.h>
static struct plat_serial8250_port serial_platform_data[] = {
{
@@ -45,6 +46,57 @@ int platform_register_uart(void)
return platform_device_register(&serial_device);
}
+
+static struct resource gmac_resources[] = {
+ {
+ .start = GEMINI_TOE_BASE,
+ .end = GEMINI_TOE_BASE + 0xffff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_GMAC0,
+ .end = IRQ_GMAC0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = IRQ_GMAC1,
+ .end = IRQ_GMAC1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 gmac_dmamask = 0xffffffffUL;
+
+static struct platform_device ethernet_device = {
+ .name = "gemini-gmac",
+ .id = 0,
+ .dev = {
+ .dma_mask = &gmac_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(gmac_resources),
+ .resource = gmac_resources,
+};
+
+int __init platform_register_ethernet(struct gemini_gmac_platform_data *pdata)
+{
+ unsigned int reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
+
+ reg &= ~(GMAC_GMII | GMAC_1_ENABLE);
+
+ if (pdata->bus_id[1])
+ reg |= GMAC_1_ENABLE;
+ else if (pdata->interface[0] == PHY_INTERFACE_MODE_GMII)
+ reg |= GMAC_GMII;
+
+ __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_MISC_CTRL);
+
+ ethernet_device.dev.platform_data = pdata;
+
+ return platform_device_register(ðernet_device);
+}
+
+
static struct resource flash_resource = {
.start = GEMINI_FLASH_BASE,
.flags = IORESOURCE_MEM,
diff --git a/arch/arm/mach-gemini/include/mach/gmac.h b/arch/arm/mach-gemini/include/mach/gmac.h
new file mode 100644
index 0000000..c6eeacc
--- /dev/null
+++ b/arch/arm/mach-gemini/include/mach/gmac.h
@@ -0,0 +1,21 @@
+/*
+ * Gemini GMAC specific defines
+ *
+ * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MACH_GMAC_H__
+#define __MACH_GMAC_H__
+
+#include <linux/phy.h>
+
+struct gemini_gmac_platform_data {
+ char *bus_id[2]; /* NULL means that this port is not used */
+ phy_interface_t interface[2];
+};
+
+#endif /* __MACH_GMAC_H__ */
--
1.7.1
^ permalink raw reply related
* [RFC PATCH 0/2] SL351x (Gemini) ethernet driver
From: Michał Mirosław @ 2010-10-29 10:23 UTC (permalink / raw)
To: Hans Ulli Kroll, Russell King, linux-arm-kernel, linux-kernel,
netdev
Cc: Paulius Zaleckas, Janos Laube
This is a driver for SL351x (Gemini) SoC ethernet peripheral.
Based on work by Paulius Zaleckas and GPLd code from Raidsonic
and other NAS vendors.
This is work in progress. Please comment and test if you can.
Patches are against 2.6.37-rc (current Linus' tree) but should
apply to 2.6.36. You probably also need patches for PATA from
git://git.berlios.de/gemini-board ib4220
Known bugs:
- repeatable bad HW calculated TCP csum
happens for only some packets in a TCP stream
looks like it doesn't like some data pattern or timing
(difference between correct and generated csum is the same
when the packet is retransmitted with changed header/TCP tstamp)
- TX DMA hangs sometimes (needs module reload when that happens)
with debugging printks disabled and HW TX csum enabled
- unsynced counters
I started to work on Paulius' code to find out why the TX DMA hangs
happen, but then I realized that complete rewrite was a better way
to understand how the hardware works and why it doesn't. As a "bonus"
this got some additional features:
- ethtool support
- 64-bit counters
- proper cleanup on ifdown/module unload
- better DMA API usage
- cleaned up code
- a lot of tx/rx debugging printks
- based on 2.6.36 DMA and netdev interfaces
TODO:
- NAPI
- MTU changing
For normal use tx-csum and tso have to be disabled:
ethtool -K eth0 tso off tx off
Tested on Raidsonic IcyBox 4220-B (dual SATA NAS).
I'm also interested in getting copies of various GPL packages for
StorLink SL3516. I already have following packages (md5sum):
89991e543eb2e473e3d380ac9a4cd8b4 GPL_source_code(Raidsonic).zip
6ba8b833c429794315f0a73ce2961bd8 Gemini_v2_6_0-n.tgz
fe87e97a33554bcab8284d25ff86e383 n299_n199_1.00.24_GPL.tar.bz2
eca8994354368304ca3b5bd1429c20bb sl-boot_1.0.9.tgz
eafd6497074fe0651459bf38c39d66bd vt4kern-1.5.tar.bz2.tar
Best Regards,
Michał Mirosław
---
Michał Mirosław (2):
Gemini: create platform device for ethernet in Raidsonic IB-4220B
Gemini: SL351x Ethernet driver
arch/arm/mach-gemini/board-nas4220b.c | 53 +
arch/arm/mach-gemini/common.h | 2 +
arch/arm/mach-gemini/devices.c | 52 +
arch/arm/mach-gemini/include/mach/gmac.h | 21 +
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/sl351x.c | 1706 ++++++++++++++++++++++++++++++
drivers/net/sl351x_hw.h | 1423 +++++++++++++++++++++++++
8 files changed, 3265 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-gemini/include/mach/gmac.h
create mode 100644 drivers/net/sl351x.c
create mode 100644 drivers/net/sl351x_hw.h
^ permalink raw reply
* [RFC PATCH 2/2] Gemini: SL351x Ethernet driver
From: Michał Mirosław @ 2010-10-29 10:23 UTC (permalink / raw)
To: Hans Ulli Kroll, Russell King, linux-arm-kernel, linux-kernel,
netdev
Cc: Paulius Zaleckas, Janos Laube
In-Reply-To: <cover.1288321597.git.mirq-linux@rere.qmqm.pl>
Driver for SL351x (Gemini) SoC ethernet peripheral. Based on work
by Paulius Zaleckas and GPLd code from Raidsonic and other NAS
vendors.
Tested on Raidsonic IcyBox 4220-B (dual SATA NAS).
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
---
drivers/net/Kconfig | 7 +
drivers/net/Makefile | 1 +
drivers/net/sl351x.c | 1706 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/sl351x_hw.h | 1423 +++++++++++++++++++++++++++++++++++++++
4 files changed, 3137 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/sl351x.c
create mode 100644 drivers/net/sl351x_hw.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9334539..da02d60 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2068,6 +2068,13 @@ config ACENIC_OMIT_TIGON_I
The safe and default value for this is N.
+config GEMINI_SL351X
+ tristate "StorLink SL351x Gigabit Ethernet support"
+ depends on ARCH_GEMINI
+ select PHYLIB
+ help
+ This driver supports StorLink SL351x (Gemini) dual Gigabit Ethernet.
+
config DL2K
tristate "DL2000/TC902x-based Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 652fc6b..9edfc06 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -257,6 +257,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/
obj-$(CONFIG_ENC28J60) += enc28j60.o
obj-$(CONFIG_ETHOC) += ethoc.o
obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_GEMINI_SL351X) += sl351x.o
obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
diff --git a/drivers/net/sl351x.c b/drivers/net/sl351x.c
new file mode 100644
index 0000000..e4e0cc8
--- /dev/null
+++ b/drivers/net/sl351x.c
@@ -0,0 +1,1706 @@
+/*
+ * Ethernet device driver for Gemini SoC (SL351x GMAC).
+ *
+ * Copyright (C) 2010, Michał Mirosław <mirq-linux@rere.qmqm.pl>
+ *
+ * Based on work by Paulius Zaleckas <paulius.zaleckas@gmail.com>
+ * and GPLd code from Raidsonic and other Gemini-based NAS vendors.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <asm/cache.h>
+#include <asm/irq.h>
+
+#include <linux/platform_device.h>
+#include <linux/etherdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/skbuff.h>
+#include <linux/phy.h>
+#include <linux/crc32.h>
+#include <linux/ethtool.h>
+#include <linux/tcp.h>
+
+#include <mach/hardware.h>
+#include <mach/global_reg.h>
+#include <mach/irqs.h>
+#include <mach/gmac.h>
+#include "sl351x_hw.h"
+
+#define DEFAULT_GMAC_RXQ_LEN_SHIFT 8
+#define DEFAULT_GMAC_TXQ_LEN_SHIFT 8
+#define DEFAULT_GMAC_FREEQ_LEN_SHIFT 8
+#define DEFAULT_RX_SKB_SIZE 1536
+#define SKB_PRIVATE_BYTES 16
+#define RX_INSERT_BYTES 2
+#define TX_MAX_FRAGS 8
+#define TX_QUEUE_NUM 1 /* max: 6 */
+#define NETIF_TSO_FEATURES \
+ (NETIF_F_TSO|NETIF_F_TSO_ECN|NETIF_F_TSO6)
+
+static int debug_level = 0;
+module_param(debug_level, int, 0600);
+MODULE_PARM_DESC(debug_level, "netif debug level mask");
+
+struct toe_private {
+ void __iomem *iomem;
+ GMAC_RXDESC_T *freeq_ring;
+ spinlock_t irq_lock;
+
+ struct net_device *netdev[2];
+ struct device *dev;
+ int irq;
+
+ unsigned int freeq_skb_size;
+ unsigned int freeq_size2;
+ dma_addr_t freeq_dma_base;
+};
+
+struct gmac_txq {
+ GMAC_TXDESC_T *ring;
+ unsigned int cptr;
+ struct sk_buff **skb;
+} ____cacheline_aligned_in_smp;;
+
+struct gmac_private {
+ void __iomem *dma_iomem;
+
+ void __iomem *rxq_rwptr;
+ GMAC_RXDESC_T *rxq_ring;
+ unsigned int rxq_size2;
+
+ struct gmac_txq txq[TX_QUEUE_NUM];
+
+ dma_addr_t rxq_dma_base;
+ dma_addr_t txq_dma_base;
+
+ unsigned int msg_enable;
+ spinlock_t config_lock;
+
+ struct rtnl_link_stats64 stats;
+ u64 rx_stats[RX_STATUS_NUM];
+ u64 hw_stats[RX_STATS_NUM];
+ u64 rx_csum_stats[RX_CHKSUM_NUM];
+ u64 tx_frag_stats[TX_MAX_FRAGS];
+ u64 tx_frags_linearized;
+ u64 tx_hw_csummed;
+};
+
+#define GMAC_STATS_NUM (RX_STATUS_NUM + RX_STATS_NUM + RX_CHKSUM_NUM + TX_MAX_FRAGS + 2)
+static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
+ "RX_STATUS_GOOD_FRAME",
+ "RX_STATUS_TOO_LONG_GOOD_CRC",
+ "RX_STATUS_RUNT_FRAME",
+ "RX_STATUS_SFD_NOT_FOUND",
+ "RX_STATUS_CRC_ERROR",
+ "RX_STATUS_TOO_LONG_BAD_CRC",
+ "RX_STATUS_ALIGNMENT_ERROR",
+ "RX_STATUS_TOO_LONG_BAD_ALIGN",
+ "RX_STATUS_RX_ERR",
+ "RX_STATUS_DA_FILTERED",
+ "RX_STATUS_BUFFER_FULL",
+ "RX_STATUS_11",
+ "RX_STATUS_12",
+ "RX_STATUS_13",
+ "RX_STATUS_14",
+ "RX_STATUS_15",
+ "GMAC_IN_DISCARDS",
+ "GMAC_IN_ERRORS",
+ "GMAC_IN_MCAST",
+ "GMAC_IN_BCAST",
+ "GMAC_IN_MAC1",
+ "GMAC_IN_MAC2",
+ "RX_CHKSUM_IP_UDP_TCP_OK",
+ "RX_CHKSUM_IP_OK_ONLY",
+ "RX_CHKSUM_NONE",
+ "RX_CHKSUM_3",
+ "RX_CHKSUM_IP_ERR_UNKNOWN",
+ "RX_CHKSUM_IP_ERR",
+ "RX_CHKSUM_TCP_UDP_ERR",
+ "RX_CHKSUM_7",
+ "TX_FRAGS[1]",
+ "TX_FRAGS[2]",
+ "TX_FRAGS[3]",
+ "TX_FRAGS[4]",
+ "TX_FRAGS[5]",
+ "TX_FRAGS[6]",
+ "TX_FRAGS[7]",
+ "TX_FRAGS[8]",
+ "TX_FRAGS_LINEARIZED",
+ "TX_HW_CSUMMED",
+};
+
+static struct gmac_private *netdev_to_gmac(struct net_device *dev)
+{
+ return netdev_priv(dev);
+}
+
+static struct toe_private *netdev_to_toe(struct net_device *dev)
+{
+ return dev->ml_priv;
+}
+
+static void __iomem *toe_reg(struct toe_private *toe, unsigned int reg)
+{
+ return toe->iomem + reg;
+}
+
+static void __iomem *gmac_dma_reg(struct net_device *dev, unsigned int reg)
+{
+ return netdev_to_gmac(dev)->dma_iomem + reg;
+}
+
+static void __iomem *gmac_ctl_reg(struct net_device *dev, unsigned int reg)
+{
+ return (void __iomem *)dev->base_addr + reg;
+}
+
+#define DEV_ADD_STATS(dev, stat, value) \
+ ((dev)->stats.stat += (value))
+#define DEV_INC_STATS(dev, stat) DEV_ADD_STATS(dev, stat, 1)
+
+static struct sk_buff *toe_get_rx_skb(GMAC_RXDESC_T *desc)
+{
+ return *(void **)(__va(desc->word2.buf_adr) - SKB_PRIVATE_BYTES);
+}
+
+static void toe_set_rx_skb(GMAC_RXDESC_T *desc, struct sk_buff *skb)
+{
+ *(void **)skb->data = skb;
+ skb_reserve(skb, SKB_PRIVATE_BYTES);
+}
+
+static void gmac_hw_start(struct net_device *dev)
+{
+ GMAC_DMA_CTRL_T dma_ctrl;
+
+ dma_ctrl.bits32 = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_CTRL_REG));
+
+ dma_ctrl.bits.rd_enable = 1;
+ dma_ctrl.bits.td_enable = 1;
+ dma_ctrl.bits.loopback = 0;
+ dma_ctrl.bits.drop_small_ack = 0;
+ dma_ctrl.bits.rd_prot = 0;
+ dma_ctrl.bits.rd_burst_size = 3;
+ dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
+ dma_ctrl.bits.rd_bus = 3;
+ dma_ctrl.bits.td_prot = 0;
+ dma_ctrl.bits.td_burst_size = 3;
+ dma_ctrl.bits.td_bus = 3;
+
+ __raw_writel(dma_ctrl.bits32, gmac_dma_reg(dev, GMAC_DMA_CTRL_REG));
+}
+
+static void gmac_hw_stop(struct net_device *dev)
+{
+ GMAC_DMA_CTRL_T dma_ctrl;
+
+ dma_ctrl.bits32 = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_CTRL_REG));
+
+ dma_ctrl.bits.rd_enable = 0;
+ dma_ctrl.bits.td_enable = 0;
+
+ __raw_writel(dma_ctrl.bits32, gmac_dma_reg(dev, GMAC_DMA_CTRL_REG));
+}
+
+static void gmac_update_config0_reg(struct net_device *dev, u32 val, u32 vmask)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&gmac->config_lock, flags);
+
+ reg = __raw_readl(gmac_ctl_reg(dev, GMAC_CONFIG0));
+ reg = (reg & ~vmask) | val;
+ __raw_writel(reg, gmac_ctl_reg(dev, GMAC_CONFIG0));
+
+ spin_unlock_irqrestore(&gmac->config_lock, flags);
+}
+
+static void gmac_enable_tx_rx(struct net_device *dev)
+{
+ gmac_update_config0_reg(dev, 0, CONFIG0_TX_RX_DISABLE);
+}
+
+static void gmac_disable_tx_rx(struct net_device *dev)
+{
+ gmac_update_config0_reg(dev, CONFIG0_TX_RX_DISABLE, CONFIG0_TX_RX_DISABLE);
+ mdelay(10); /* let GMAC consume packet */
+}
+
+static void gmac_set_flow_control(struct net_device *dev, bool tx, bool rx)
+{
+ u32 val = (tx ? CONFIG0_FLOW_TX : 0)|(rx ? CONFIG0_FLOW_RX : 0);
+
+ gmac_update_config0_reg(dev, val, CONFIG0_FLOW_CTL);
+}
+
+static void gmac_update_link_state(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ void __iomem *status_reg = gmac_ctl_reg(dev, GMAC_STATUS);
+ struct phy_device *phydev = dev->phydev;
+ GMAC_STATUS_T status, old_status;
+
+ old_status.bits32 = status.bits32 = __raw_readl(status_reg);
+
+ status.bits.link = phydev->link;
+ status.bits.duplex = phydev->duplex;
+
+ switch (phydev->speed) {
+ case 1000:
+ status.bits.speed = GMAC_SPEED_1000;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
+ status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
+ break;
+ case 100:
+ status.bits.speed = GMAC_SPEED_100;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
+ break;
+ case 10:
+ status.bits.speed = GMAC_SPEED_10;
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
+ break;
+ default:
+ dev_warn(&dev->dev, "Not supported PHY speed (%d)\n", phydev->speed);
+ }
+
+ gmac_set_flow_control(dev, phydev->pause,
+ phydev->pause ^ phydev->asym_pause);
+
+ if (old_status.bits32 == status.bits32)
+ return;
+
+ if (netif_msg_link(gmac)) {
+ phy_print_status(phydev);
+ netdev_info(dev, "link flow control: %s\n",
+ phydev->pause
+ ? (phydev->asym_pause ? "tx" : "both")
+ : (phydev->asym_pause ? "rx" : "none")
+ );
+ }
+
+ gmac_disable_tx_rx(dev);
+ __raw_writel(status.bits32, status_reg);
+ gmac_enable_tx_rx(dev);
+}
+
+static int gmac_init(struct net_device *dev)
+{
+ struct toe_private *toe = netdev_to_toe(dev);
+ struct gemini_gmac_platform_data *pdata = toe->dev->platform_data;
+ unsigned val;
+ int num = dev->dev_id;
+
+ GMAC_CONFIG0_T config0 = { .bits = {
+ .dis_tx = 1,
+ .dis_rx = 1,
+ .max_len = 2, /* magic; 512 << max_len? */
+ .ipv4_rx_chksum = 1,
+ .ipv6_rx_chksum = 1,
+ .rx_err_detect = 1,
+ .rgmm_edge = 1,
+ .port0_chk_hwq = 1,
+ .port1_chk_hwq = 1,
+ .port0_chk_toeq = 1,
+ .port1_chk_toeq = 1,
+ .port0_chk_classq = 1,
+ .port1_chk_classq = 1,
+ } };
+ GMAC_TX_WCR0_T hw_weigh = { .bits = {
+ .hw_tq3 = 1,
+ .hw_tq2 = 1,
+ .hw_tq1 = 1,
+ .hw_tq0 = 1,
+ } };
+ GMAC_TX_WCR1_T sw_weigh = { .bits = {
+ .sw_tq5 = 1,
+ .sw_tq4 = 1,
+ .sw_tq3 = 1,
+ .sw_tq2 = 1,
+ .sw_tq1 = 1,
+ .sw_tq0 = 1,
+ } };
+ GMAC_CONFIG1_T config1 = { .bits = {
+ .set_threshold = 16,
+ .rel_threshold = 24,
+ } };
+ GMAC_CONFIG2_T config2 = { .bits = {
+ .set_threshold = 16,
+ .rel_threshold = 32,
+ } };
+ GMAC_CONFIG3_T config3 = { .bits = {
+ .set_threshold = 0,
+ .rel_threshold = 0,
+ } };
+ GMAC_STATUS_T status = { .bits32 = 0 };
+
+ /* turn on supported offloads by default */
+ /* TSO_ECN untested, TX csum unreliable, TX DMA unreliable */
+ dev->features |= NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM|NETIF_F_SG;
+ dev->features |= NETIF_TSO_FEATURES;
+
+ dev->phydev = phy_connect(dev, pdata->bus_id[num],
+ &gmac_update_link_state, 0, pdata->interface[num]);
+ if (IS_ERR(dev->phydev))
+ return PTR_ERR(dev->phydev);
+
+ dev->phydev->supported &= PHY_GBIT_FEATURES|SUPPORTED_Pause;
+ dev->phydev->advertising = dev->phydev->supported;
+
+ val = __raw_readl(gmac_ctl_reg(dev, GMAC_CONFIG0));
+ config0.bits.reserved = ((GMAC_CONFIG0_T)val).bits.reserved;
+ __raw_writel(config0.bits32, gmac_ctl_reg(dev, GMAC_CONFIG0));
+ __raw_writel(config1.bits32, gmac_ctl_reg(dev, GMAC_CONFIG1));
+ __raw_writel(config2.bits32, gmac_ctl_reg(dev, GMAC_CONFIG2));
+ __raw_writel(config3.bits32, gmac_ctl_reg(dev, GMAC_CONFIG3));
+ __raw_writel(hw_weigh.bits32, gmac_dma_reg(dev, GMAC_TX_WEIGHTING_CTRL_0_REG));
+ __raw_writel(sw_weigh.bits32, gmac_dma_reg(dev, GMAC_TX_WEIGHTING_CTRL_1_REG));
+
+ /* set PHY interface type */
+ switch (dev->phydev->interface) {
+ case PHY_INTERFACE_MODE_MII:
+ status.bits.mii_rmii = GMAC_PHY_MII;
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ status.bits.mii_rmii = GMAC_PHY_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
+ break;
+ default:
+ dev_err(&dev->dev, "Unsupported MII interface\n");
+ phy_disconnect(dev->phydev);
+ return -EINVAL;
+ }
+ __raw_writel(status.bits32, gmac_ctl_reg(dev, GMAC_STATUS));
+
+ return 0;
+}
+
+static void gmac_uninit(struct net_device *dev)
+{
+ phy_disconnect(dev->phydev);
+}
+
+static int gmac_setup_txqs(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ void __iomem *rwptr_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE0_PTR_REG);
+ void __iomem *base_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE_BASE_REG);
+
+ unsigned int n_txq = dev->num_tx_queues;
+ unsigned int n_desc2 = ilog2(dev->tx_queue_len);
+ struct gmac_txq *txq = gmac->txq;
+ GMAC_TXDESC_T *desc_ring;
+ struct sk_buff **skb_tab;
+ int i;
+
+ skb_tab = kzalloc(n_txq * dev->tx_queue_len * sizeof(*skb_tab), GFP_KERNEL);
+ if (!skb_tab)
+ return -ENOMEM;
+
+ desc_ring = dma_alloc_coherent(toe->dev,
+ n_txq * dev->tx_queue_len * sizeof(*desc_ring),
+ &gmac->txq_dma_base, GFP_KERNEL);
+ if (!desc_ring) {
+ kfree(skb_tab);
+ return -ENOMEM;
+ }
+
+ BUG_ON(gmac->txq_dma_base & ~DMA_Q_BASE_MASK);
+
+ for (i = 0; i < n_txq; i++) {
+ netif_info(gmac, ifup, dev, "txq%u: ring %p (dma 0x%08x), skb %p, rwptr %p, len %lu (order %u)\n",
+ i, desc_ring, gmac->txq_dma_base, skb_tab, rwptr_reg, dev->tx_queue_len, n_desc2);
+
+ __raw_writel(0, rwptr_reg);
+ txq->ring = desc_ring;
+ txq->cptr = 0;
+ txq->skb = skb_tab;
+
+ desc_ring += dev->tx_queue_len;
+ skb_tab += dev->tx_queue_len;
+ rwptr_reg += 4;
+ }
+
+ __raw_writel(gmac->txq_dma_base | n_desc2, base_reg);
+
+ return 0;
+}
+
+static void gmac_cleanup_txqs(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ void __iomem *rwptr_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE0_PTR_REG);
+ void __iomem *base_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE_BASE_REG);
+
+ struct gmac_txq *txq = gmac->txq;
+ unsigned n_txq = dev->num_tx_queues;
+ int i, j;
+
+ for (i = 0; i < n_txq; ++i, ++txq) {
+ __raw_writel(0, rwptr_reg + 4 * i);
+ for (j = 0; j < dev->tx_queue_len; ++j)
+ if (txq->skb[j])
+ dev_kfree_skb(txq->skb[j]);
+ }
+
+ __raw_writel(0, base_reg);
+
+ kfree(gmac->txq->skb);
+ dma_free_coherent(toe->dev, n_txq * dev->tx_queue_len * sizeof(*gmac->txq->ring),
+ gmac->txq->ring, gmac->txq_dma_base);
+}
+
+static int gmac_setup_rxq(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ NONTOE_QHDR_T __iomem *qhdr = toe_reg(toe, TOE_DEFAULT_Q_HDR_BASE(dev->dev_id));
+
+ gmac->rxq_rwptr = &qhdr->word1;
+ gmac->rxq_ring = dma_alloc_coherent(toe->dev,
+ sizeof(*gmac->rxq_ring) << gmac->rxq_size2,
+ &gmac->rxq_dma_base, GFP_KERNEL);
+ if (!gmac->rxq_ring)
+ return -ENOMEM;
+
+ BUG_ON(gmac->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK);
+
+ __raw_writel(0, gmac->rxq_rwptr);
+ __raw_writel(gmac->rxq_dma_base | gmac->rxq_size2, &qhdr->word0);
+
+ netif_info(gmac, ifup, dev, "rxq: ring %p (dma 0x%08x), rwptr %p, len %u (order %u)\n",
+ gmac->rxq_ring, gmac->rxq_dma_base, gmac->rxq_rwptr,
+ 1 << gmac->rxq_size2, gmac->rxq_size2);
+ return 0;
+}
+
+static void gmac_cleanup_rxq(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+
+ NONTOE_QHDR_T __iomem *qhdr = toe_reg(toe, TOE_DEFAULT_Q_HDR_BASE(dev->dev_id));
+ void __iomem *dma_reg = &qhdr->word0;
+ void __iomem *ptr_reg = &qhdr->word1;
+ unsigned i, e, mask = __RWPTR_MASK(gmac->rxq_size2);
+ struct sk_buff *skb;
+
+ i = GET_RPTR(ptr_reg);
+ e = GET_WPTR(ptr_reg);
+ __raw_writel(0, ptr_reg);
+ __raw_writel(0, dma_reg);
+
+ for (; i != e; i = __RWPTR_NEXT(i, mask)) {
+ skb = toe_get_rx_skb(gmac->rxq_ring + i);
+
+ dma_unmap_single(toe->dev, gmac->rxq_ring[i].word2.buf_adr,
+ skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
+ kfree_skb(skb);
+ }
+
+ dma_free_coherent(toe->dev, sizeof(*gmac->rxq_ring) << gmac->rxq_size2,
+ gmac->rxq_ring, gmac->rxq_dma_base);
+}
+
+static void gmac_tx_interrupt(struct net_device *dev, unsigned txq_num)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+
+ void __iomem *ptr_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE_PTR_REG(txq_num));
+ struct netdev_queue *ntxq = netdev_get_tx_queue(dev, txq_num);
+ struct gmac_txq *txq = &gmac->txq[txq_num];
+
+ unsigned i, n, mask = dev->tx_queue_len - 1;
+ struct sk_buff *skb;
+ GMAC_TXDESC_T *tx;
+
+ netif_info(gmac, tx_done, dev, "txirq%u: %u,%u,%u\n",
+ txq_num, txq->cptr, GET_RPTR(ptr_reg), GET_WPTR(ptr_reg));
+
+ for (i = txq->cptr; i != GET_RPTR(ptr_reg); i = __RWPTR_NEXT(i, mask)) {
+ tx = &txq->ring[i];
+ skb = txq->skb[i];
+ txq->skb[i] = NULL;
+
+ BUG_ON(!skb);
+
+ dma_unmap_single(toe->dev, tx->word2.buf_adr,
+ tx->word0.bits.buffer_size, DMA_TO_DEVICE);
+
+ if (tx->word0.bits.status_tx_ok) {
+ ++ntxq->tx_packets;
+ ntxq->tx_bytes += skb->len;
+ netif_info(gmac, tx_done, dev,
+ "TX done descriptor: [%u] 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i, tx->word0.bits32, tx->word1.bits32,
+ tx->word2.bits32, tx->word3.bits32);
+ } else {
+ DEV_INC_STATS(gmac, tx_errors);
+ netif_err(gmac, tx_err, dev,
+ "TX error descriptor: [%u] 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i, tx->word0.bits32, tx->word1.bits32,
+ tx->word2.bits32, tx->word3.bits32);
+ }
+
+ n = tx->word0.bits.desc_count;
+ BUG_ON(__RWPTR_DISTANCE(i, GET_RPTR(ptr_reg), mask) < n);
+
+ while (--n) {
+ i = __RWPTR_NEXT(i, mask);
+ dma_unmap_page(toe->dev, txq->ring[i].word2.buf_adr,
+ txq->ring[i].word0.bits.buffer_size, DMA_TO_DEVICE);
+ netif_info(gmac, tx_done, dev,
+ "TX frag descriptor: [%u] 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i, txq->ring[i].word0.bits32, txq->ring[i].word1.bits32,
+ txq->ring[i].word2.bits32, txq->ring[i].word3.bits32);
+ }
+
+ dev_kfree_skb_irq(skb);
+ }
+
+ txq->cptr = i;
+ netif_tx_wake_queue(ntxq);
+}
+
+static unsigned tss_pkt_len(struct sk_buff *skb, unsigned dev_mtu)
+{
+ unsigned pktlen = (skb->protocol == htons(ETH_P_8021Q)) ? ETH_HLEN + VLAN_HLEN : ETH_HLEN;
+
+ if (!skb_is_gso(skb))
+ return pktlen + dev_mtu;
+ else
+ return pktlen +
+ (skb_transport_header(skb) - skb_network_header(skb)) +
+ tcp_hdrlen(skb) +
+ skb_shinfo(skb)->gso_size;
+}
+
+static int gmac_map_tx_bufs(struct net_device *dev, struct sk_buff *skb,
+ struct gmac_txq *txq, int desc, unsigned tss_flags)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct device *dma_dev = netdev_to_toe(dev)->dev;
+ skb_frag_t *frag;
+ dma_addr_t mapping;
+ int nfrags, w;
+
+ frag = skb_shinfo(skb)->frags;
+ nfrags = skb_shinfo(skb)->nr_frags;
+ w = desc;
+
+ mapping = dma_map_single(dma_dev, skb->data,
+ skb_headlen(skb), DMA_TO_DEVICE);
+ if (dma_mapping_error(dma_dev, mapping))
+ goto map1_error;
+
+ txq->ring[w].word0.bits32 = skb_headlen(skb);
+ txq->ring[w].word1.bits32 = skb->len | tss_flags;
+ txq->ring[w].word2.bits32 = mapping;
+ txq->ring[w].word3.bits32 = tss_pkt_len(skb, dev->mtu) | EOFIE_BIT | SOF_BIT;
+
+ netif_info(gmac, tx_queued, dev,
+ "txq%ld[%u]: 0x%08x 0x%08x 0x%08x 0x%08x, datap %p\n",
+ txq - gmac->txq, w,
+ txq->ring[w].word0.bits32, txq->ring[w].word1.bits32,
+ txq->ring[w].word2.bits32, txq->ring[w].word3.bits32,
+ skb->data);
+
+ while (nfrags--) {
+ mapping = dma_map_page(dma_dev, frag->page,
+ frag->page_offset, frag->size, DMA_TO_DEVICE);
+ if (dma_mapping_error(dma_dev, mapping))
+ goto map_error;
+
+ w = __RWPTR_NEXT(w, dev->tx_queue_len - 1);
+ txq->ring[w].word0.bits32 = frag->size;
+ txq->ring[w].word1.bits32 = 0;
+ txq->ring[w].word2.bits32 = mapping;
+ txq->ring[w].word3.bits32 = 0;
+
+ netif_info(gmac, tx_queued, dev,
+ "txq%ld[%u]: 0x%08x 0x%08x 0x%08x 0x%08x, data %u @ %p+0x%03x\n",
+ txq - gmac->txq, w,
+ txq->ring[w].word0.bits32, txq->ring[w].word1.bits32,
+ txq->ring[w].word2.bits32, txq->ring[w].word3.bits32,
+ frag->size, frag->page, frag->page_offset);
+
+ ++frag;
+ }
+
+ txq->ring[w].word3.bits32 |= EOFIE_BIT | EOF_BIT;
+
+ return __RWPTR_NEXT(w, dev->tx_queue_len - 1);
+
+map_error:
+ while (w != desc) {
+ dma_unmap_page(dma_dev, txq->ring[w].word2.buf_adr,
+ txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE);
+ w = __RWPTR_PREV(w, dev->tx_queue_len - 1);
+ }
+
+ dma_unmap_single(dma_dev, txq->ring[w].word2.buf_adr,
+ txq->ring[w].word0.bits.buffer_size, DMA_TO_DEVICE);
+
+map1_error:
+ netif_info(gmac, tx_err, dev,
+ "txq%ld: DMA mapping error\n", txq - gmac->txq);
+
+ return -ENOMEM;
+}
+
+static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+
+ void __iomem *ptr_reg;
+ struct gmac_txq *txq;
+ struct netdev_queue *ntxq;
+ int w, nw, txq_num, nfrags;
+ unsigned long flags;
+
+ SKB_FRAG_ASSERT(skb);
+
+ txq_num = skb_get_queue_mapping(skb);
+ ptr_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE_PTR_REG(txq_num));
+ txq = &gmac->txq[txq_num];
+ ntxq = netdev_get_tx_queue(dev, txq_num);
+
+ netif_info(gmac, tx_queued, dev, "txq%u: %u,%u,%u ? %p (%u @ %p) /%u\n",
+ txq_num, txq->cptr, GET_RPTR(ptr_reg), GET_WPTR(ptr_reg),
+ skb, skb->len, skb->data, skb_shinfo(skb)->gso_size);
+ if (netif_msg_pktdata(gmac))
+ print_hex_dump(KERN_DEBUG, "TX: ", DUMP_PREFIX_OFFSET, 16, 1,
+ skb->data, skb_headlen(skb), true);
+
+ if (skb->len >= 0x10000) {
+ dev_kfree_skb_any(skb);
+ ++ntxq->tx_dropped;
+ return NETDEV_TX_OK;
+ }
+
+ w = GET_WPTR(ptr_reg);
+ spin_lock_irqsave(&toe->irq_lock, flags);
+ nw = __RWPTR_DISTANCE(w, txq->cptr - 1, dev->tx_queue_len - 1);
+ if (!nw) {
+ netif_tx_stop_queue(ntxq);
+ spin_unlock_irqrestore(&toe->irq_lock, flags);
+ ++ntxq->tx_dropped;
+ return NETDEV_TX_BUSY;
+ }
+ spin_unlock_irqrestore(&toe->irq_lock, flags);
+
+ nfrags = skb_shinfo(skb)->nr_frags;
+ if (nw <= nfrags || nfrags >= TX_MAX_FRAGS) {
+ if (skb_linearize(skb)) {
+ ++ntxq->tx_dropped;
+ return NETDEV_TX_OK;
+ }
+ ++gmac->tx_frags_linearized;
+ } else
+ ++gmac->tx_frag_stats[nfrags];
+
+ txq->skb[w] = skb;
+
+ w = gmac_map_tx_bufs(dev, skb, txq, w,
+ (skb->ip_summed != CHECKSUM_NONE ? TSS_CHECKUM_ENABLE : 0)
+ );
+
+ if (w < 0) {
+ ++ntxq->tx_dropped;
+ return NETDEV_TX_OK;
+ }
+
+ if (skb->ip_summed != CHECKSUM_NONE)
+ ++gmac->tx_hw_csummed;
+
+ netif_info(gmac, tx_queued, dev, "txq%u: %u,%u,%u + %p\n",
+ txq_num, txq->cptr, GET_RPTR(ptr_reg), w, skb);
+
+ SET_WPTR(ptr_reg, w);
+ ntxq->trans_start = jiffies;
+
+ /* stats updated on tx completion */
+ return NETDEV_TX_OK;
+}
+
+static void gmac_rx_interrupt(struct net_device *dev, unsigned budget)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ void __iomem *ptr_reg = gmac->rxq_rwptr;
+
+ unsigned i, mask = __RWPTR_MASK(gmac->rxq_size2);
+ struct sk_buff *skb;
+ GMAC_RXDESC_T *rx;
+ unsigned pkt_size, rx_status, rx_csum;
+
+ netif_info(gmac, rx_status, dev, "rxq: %u,%u\n",
+ GET_RPTR(ptr_reg), GET_WPTR(ptr_reg));
+
+ for (i = GET_RPTR(ptr_reg); budget-- && (i != GET_WPTR(ptr_reg)); i = __RWPTR_NEXT(i, mask)) {
+ rx = gmac->rxq_ring + i;
+ skb = toe_get_rx_skb(rx);
+
+ netif_info(gmac, rx_status, dev,
+ "rxq[%u]: 0x%08x 0x%08x 0x%08x 0x%08x, skbd %p, skb %p\n",
+ i, rx->word0.bits32, rx->word1.bits32,
+ rx->word2.bits32, rx->word3.bits32,
+ __va(rx->word2.buf_adr), skb);
+
+ WARN_ON_ONCE(!skb);
+ if (!skb)
+ continue;
+
+ dma_unmap_single(toe->dev, rx->word2.buf_adr,
+ skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
+
+ pkt_size = rx->word1.bits.byte_count;
+ rx_status = rx->word0.bits.status;
+ rx_csum = rx->word0.bits.chksum_status;
+ ++gmac->rx_stats[rx_status];
+ ++gmac->rx_csum_stats[rx_csum];
+
+ if (rx->word0.bits.derr || rx->word0.bits.perr ||
+ rx_status || pkt_size < ETH_ZLEN ||
+ rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
+ DEV_INC_STATS(gmac, rx_errors);
+
+ if (pkt_size < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
+ DEV_INC_STATS(gmac, rx_length_errors);
+ if (RX_ERROR_OVER(rx_status))
+ DEV_INC_STATS(gmac, rx_over_errors);
+ if (RX_ERROR_CRC(rx_status))
+ DEV_INC_STATS(gmac, rx_crc_errors);
+ if (RX_ERROR_FRAME(rx_status))
+ DEV_INC_STATS(gmac, rx_frame_errors);
+ if (RX_ERROR_FIFO(rx_status))
+ DEV_INC_STATS(gmac, rx_fifo_errors);
+
+ dev_kfree_skb_irq(skb);
+ continue;
+ }
+
+ if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+ skb_reserve(skb, RX_INSERT_BYTES);
+ skb_put(skb, pkt_size);
+ skb->dev = dev;
+ skb->protocol = eth_type_trans(skb, dev);
+
+ DEV_INC_STATS(gmac, rx_packets);
+ DEV_ADD_STATS(gmac, rx_bytes, skb->len);
+ dev->last_rx = jiffies;
+ netif_rx(skb);
+ }
+
+ SET_RPTR(ptr_reg, i);
+}
+
+#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT|GMAC0_TXPERR_INT_BIT| \
+ GMAC0_RXDERR_INT_BIT|GMAC0_RXPERR_INT_BIT)
+#define GMAC0_IRQ0_6 (GMAC0_SWTQ00_EOF_INT_BIT|GMAC0_SWTQ00_FIN_INT_BIT)
+#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT)
+
+static void gmac_enable_irq(struct net_device *dev, int enable)
+{
+ struct toe_private *toe = netdev_to_toe(dev);
+ unsigned long flags;
+ unsigned val, mask;
+
+ spin_lock_irqsave(&toe->irq_lock, flags);
+
+ mask = (GMAC0_IRQ0_2 << (dev->dev_id * 2)) |
+ (GMAC0_IRQ0_6 << (dev->dev_id * 6));
+ val = __raw_readl(toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_0_REG));
+ val = enable ? (val | mask) : (val & ~mask);
+ __raw_writel(val, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_0_REG));
+
+ mask = DEFAULT_Q0_INT_BIT << dev->dev_id;
+ val = __raw_readl(toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG));
+ val = enable ? (val | mask) : (val & ~mask);
+ __raw_writel(val, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG));
+
+ mask = GMAC0_IRQ4_8 << (dev->dev_id * 8);
+ val = __raw_readl(toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG));
+ val = enable ? (val | mask) : (val & ~mask);
+ __raw_writel(val, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG));
+
+ spin_unlock_irqrestore(&toe->irq_lock, flags);
+}
+
+static void gmac_dump_dma_state(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ void __iomem *ptr_reg;
+ unsigned reg[4];
+
+ /* RX DMA status */
+ reg[0] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_FIRST_DESC_REG));
+ reg[1] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_CURR_DESC_REG));
+ reg[2] = GET_RPTR(gmac->rxq_rwptr);
+ reg[3] = GET_WPTR(gmac->rxq_rwptr);
+ netdev_err(dev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
+ reg[0], reg[1], reg[2], reg[3]);
+
+ reg[0] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_DESC_WORD0_REG));
+ reg[1] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_DESC_WORD1_REG));
+ reg[2] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_DESC_WORD2_REG));
+ reg[3] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_RX_DESC_WORD3_REG));
+ netdev_err(dev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ reg[0], reg[1], reg[2], reg[3]);
+
+ /* TX DMA status */
+ ptr_reg = gmac_dma_reg(dev, GMAC_SW_TX_QUEUE0_PTR_REG);
+
+ reg[0] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_FIRST_DESC_REG));
+ reg[1] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_CURR_DESC_REG));
+ reg[2] = GET_RPTR(ptr_reg);
+ reg[3] = GET_WPTR(ptr_reg);
+ netdev_err(dev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
+ reg[0], reg[1], reg[2], reg[3]);
+
+ reg[0] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_DESC_WORD0_REG));
+ reg[1] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_DESC_WORD1_REG));
+ reg[2] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_DESC_WORD2_REG));
+ reg[3] = __raw_readl(gmac_dma_reg(dev, GMAC_DMA_TX_DESC_WORD3_REG));
+ netdev_err(dev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ reg[0], reg[1], reg[2], reg[3]);
+
+ /* FREE queues status */
+ ptr_reg = toe_reg(toe, GLOBAL_SWFQ_RWPTR_REG);
+
+ reg[0] = GET_RPTR(ptr_reg);
+ reg[1] = GET_WPTR(ptr_reg);
+
+ ptr_reg = toe_reg(toe, GLOBAL_HWFQ_RWPTR_REG);
+
+ reg[2] = GET_RPTR(ptr_reg);
+ reg[3] = GET_WPTR(ptr_reg);
+ netdev_err(dev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
+ reg[0], reg[1], reg[2], reg[3]);
+}
+
+static void gmac_update_hw_stats(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ unsigned rx_discards, rx_mcast, rx_bcast;
+
+ gmac->hw_stats[0] += rx_discards = __raw_readl(gmac_ctl_reg(dev, GMAC_IN_DISCARDS));
+ gmac->hw_stats[1] += __raw_readl(gmac_ctl_reg(dev, GMAC_IN_ERRORS));
+ gmac->hw_stats[2] += rx_mcast = __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MCAST));
+ gmac->hw_stats[3] += rx_bcast = __raw_readl(gmac_ctl_reg(dev, GMAC_IN_BCAST));
+ gmac->hw_stats[4] += __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MAC1));
+ gmac->hw_stats[5] += __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MAC2));
+
+ DEV_ADD_STATS(gmac, rx_missed_errors, rx_discards);
+ DEV_ADD_STATS(gmac, rx_dropped, rx_discards);
+ DEV_ADD_STATS(gmac, multicast, rx_mcast);
+ DEV_ADD_STATS(gmac, multicast, rx_bcast);
+}
+
+static irqreturn_t gmac_interrupt(int irq, void *data)
+{
+ struct net_device *dev = data;
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+
+ void __iomem *irqif_reg, *irqen_reg;
+ unsigned val, orr = 0;
+
+
+ irqif_reg = toe_reg(toe, GLOBAL_INTERRUPT_STATUS_0_REG);
+ irqen_reg = toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_0_REG);
+
+ val = __raw_readl(irqif_reg) & __raw_readl(irqen_reg);
+ netif_info(gmac, intr, dev, "irq: val0&en = 0x%08x\n", val);
+
+ if (val & (GMAC0_IRQ0_2 << (dev->dev_id * 2))) {
+ /* oh, crap. */
+ netif_err(gmac, intr, dev, "hw failure/sw bug; status0&en = 0x%08x\n", val);
+
+ /* don't know how to recover, just reduce losses */
+ gmac_enable_irq(dev, 0);
+
+ gmac_dump_dma_state(dev);
+ }
+
+ if (val & (GMAC0_IRQ0_6 << (dev->dev_id * 6)))
+ gmac_tx_interrupt(dev, 0);
+
+ __raw_writel(val, irqif_reg);
+ orr |= val;
+
+
+ irqif_reg = toe_reg(toe, GLOBAL_INTERRUPT_STATUS_1_REG);
+ irqen_reg = toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG);
+
+ val = __raw_readl(irqif_reg) & __raw_readl(irqen_reg);
+ netif_info(gmac, intr, dev, "irq: val1&en = 0x%08x\n", val);
+
+ if (val & (DEFAULT_Q0_INT_BIT << dev->dev_id))
+ gmac_rx_interrupt(dev, ~0);
+
+ __raw_writel(val, irqif_reg);
+ orr |= val;
+
+
+ irqif_reg = toe_reg(toe, GLOBAL_INTERRUPT_STATUS_4_REG);
+ irqen_reg = toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_4_REG);
+
+ val = __raw_readl(irqif_reg) & __raw_readl(irqen_reg);
+ netif_info(gmac, intr, dev, "irq: val4&en = 0x%08x\n", val);
+
+ if (val & (GMAC0_MIB_INT_BIT << (dev->dev_id * 8))) {
+ spin_lock(&toe->irq_lock);
+ gmac_update_hw_stats(dev);
+ spin_unlock(&toe->irq_lock);
+ }
+
+ __raw_writel(val, irqif_reg);
+ orr |= val;
+
+
+ return orr ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static int gmac_open(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ int err;
+
+ gmac->rxq_size2 = DEFAULT_GMAC_FREEQ_LEN_SHIFT;
+ err = gmac_setup_rxq(dev);
+ if (err)
+ return err;
+
+ err = min(12, max(6, ilog2(dev->tx_queue_len)));
+ dev->tx_queue_len = 1 << err;
+ err = gmac_setup_txqs(dev);
+ if (err)
+ goto err_rxq;
+
+ err = request_irq(dev->irq, gmac_interrupt, IRQF_SHARED, dev->name, dev);
+ if (err)
+ goto err_txq;
+
+ netif_carrier_off(dev);
+ phy_start(dev->phydev);
+
+ gmac_hw_start(dev);
+ gmac_enable_irq(dev, 1);
+ netif_tx_start_all_queues(dev);
+ gmac_enable_tx_rx(dev);
+
+ return 0;
+
+err_txq:
+ gmac_cleanup_txqs(dev);
+err_rxq:
+ gmac_cleanup_rxq(dev);
+ return err;
+}
+
+static int gmac_close(struct net_device *dev)
+{
+ netif_tx_stop_all_queues(dev);
+
+ gmac_disable_tx_rx(dev);
+ gmac_hw_stop(dev);
+
+ phy_stop(dev->phydev);
+
+ gmac_enable_irq(dev, 0);
+ free_irq(dev->irq, dev);
+
+ gmac_update_hw_stats(dev);
+
+ gmac_cleanup_txqs(dev);
+ gmac_cleanup_rxq(dev);
+
+ return 0;
+}
+
+static void gmac_set_multicast_list(struct net_device *dev)
+{
+ struct netdev_hw_addr *ha;
+ __u32 mc_filter[2];
+ unsigned bit_nr;
+
+ if (dev->flags & IFF_ALLMULTI)
+ return;
+
+ mc_filter[1] = mc_filter[0] = 0;
+ netdev_for_each_mc_addr(ha, dev) {
+ bit_nr = ~crc32_be(~0, ha->addr, ETH_ALEN) & 0x3f;
+ mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
+ }
+
+ __raw_writel(mc_filter[0], gmac_ctl_reg(dev, GMAC_MCAST_FIL0));
+ __raw_writel(mc_filter[1], gmac_ctl_reg(dev, GMAC_MCAST_FIL1));
+}
+
+static void gmac_set_rx_mode(struct net_device *dev)
+{
+ GMAC_RX_FLTR_T filter = { .bits = {
+ .broadcast = 1,
+ .multicast = 1,
+ .unicast = 1,
+ } };
+
+ if (dev->flags & IFF_PROMISC) {
+ filter.bits.error = 1;
+ filter.bits.promiscuous = 1;
+ } else if (dev->flags & IFF_ALLMULTI) {
+ __raw_writel(~0, gmac_ctl_reg(dev, GMAC_MCAST_FIL0));
+ __raw_writel(~0, gmac_ctl_reg(dev, GMAC_MCAST_FIL1));
+ } else {
+ gmac_set_multicast_list(dev);
+ }
+
+ __raw_writel(filter.bits32, gmac_ctl_reg(dev, GMAC_RX_FLTR));
+}
+
+static void __gmac_set_mac_address(struct net_device *dev)
+{
+ __le32 addr[3];
+
+ memset(addr, 0, sizeof(addr));
+ memcpy(addr, dev->dev_addr, ETH_ALEN);
+
+ __raw_writel(le32_to_cpu(addr[0]), gmac_ctl_reg(dev, GMAC_STA_ADD0));
+ __raw_writel(le32_to_cpu(addr[1]), gmac_ctl_reg(dev, GMAC_STA_ADD1));
+ __raw_writel(le32_to_cpu(addr[2]), gmac_ctl_reg(dev, GMAC_STA_ADD2));
+}
+
+static int gmac_set_mac_address(struct net_device *dev, void *addr)
+{
+ struct sockaddr *sa = addr;
+
+ memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
+ __gmac_set_mac_address(dev);
+
+ return 0;
+}
+
+static void gmac_clear_rx_stats(struct net_device *dev)
+{
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_DISCARDS));
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_ERRORS));
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MCAST));
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_BCAST));
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MAC1));
+ __raw_readl(gmac_ctl_reg(dev, GMAC_IN_MAC2));
+}
+
+static struct rtnl_link_stats64 *gmac_get_stats64(struct net_device *dev,
+ struct rtnl_link_stats64 *storage)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ struct toe_private *toe = netdev_to_toe(dev);
+ unsigned long flags;
+
+ spin_lock_irqsave(&toe->irq_lock, flags);
+ gmac_update_hw_stats(dev);
+ spin_unlock_irqrestore(&toe->irq_lock, flags);
+
+ dev_txq_stats_fold(dev, &gmac->stats);
+
+ return &gmac->stats;
+}
+
+static u32 gmac_get_rx_csum(struct net_device *dev)
+{
+ return !!(__raw_readl(gmac_ctl_reg(dev, GMAC_CONFIG0)) & CONFIG0_RX_CHKSUM);
+}
+
+static int gmac_set_rx_csum(struct net_device *dev, u32 enable)
+{
+ gmac_update_config0_reg(dev,
+ enable ? CONFIG0_RX_CHKSUM : 0, CONFIG0_RX_CHKSUM);
+
+ return 0;
+}
+
+static int gmac_set_tso(struct net_device *dev, u32 data)
+{
+ if (data)
+ dev->features |= NETIF_TSO_FEATURES;
+ else
+ dev->features &= ~NETIF_TSO_FEATURES;
+
+ return 0;
+}
+
+static int gmac_get_sset_count(struct net_device *dev, int sset)
+{
+ return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
+}
+
+static void gmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
+{
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
+}
+
+static void gmac_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *estats, u64 *values)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ int i;
+
+ gmac_get_stats64(dev, NULL);
+
+ for (i = 0; i < RX_STATUS_NUM; ++i)
+ *values++ = gmac->rx_stats[i];
+ for (i = 0; i < RX_STATS_NUM; ++i)
+ *values++ = gmac->hw_stats[i];
+ for (i = 0; i < RX_CHKSUM_NUM; ++i)
+ *values++ = gmac->rx_csum_stats[i];
+ for (i = 0; i < TX_MAX_FRAGS; ++i)
+ *values++ = gmac->tx_frag_stats[i];
+ *values++ = gmac->tx_frags_linearized;
+ *values++ = gmac->tx_hw_csummed;
+}
+
+static int gmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ return phy_ethtool_gset(dev->phydev, cmd);
+}
+
+static int gmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ return phy_ethtool_sset(dev->phydev, cmd);
+}
+
+static int gmac_nway_reset(struct net_device *dev)
+{
+ return phy_start_aneg(dev->phydev);
+}
+
+static void gmac_get_pauseparam(struct net_device *dev,
+ struct ethtool_pauseparam *pparam)
+{
+ GMAC_CONFIG0_T config0;
+
+ config0.bits32 = __raw_readl(gmac_ctl_reg(dev, GMAC_CONFIG0));
+
+ pparam->rx_pause = config0.bits.rx_fc_en;
+ pparam->tx_pause = config0.bits.tx_fc_en;
+ pparam->autoneg = true;
+}
+
+static u32 gmac_get_msglevel(struct net_device *dev)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ return gmac->msg_enable;
+}
+
+static void gmac_set_msglevel(struct net_device *dev, u32 level)
+{
+ struct gmac_private *gmac = netdev_to_gmac(dev);
+ gmac->msg_enable = level;
+}
+
+static void gmac_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *info)
+{
+ strcpy(info->driver, "sl351x");
+ strcpy(info->version, "mq-k");
+ strcpy(info->bus_info, dev->dev_id ? "1" : "0");
+}
+
+const static struct net_device_ops gmac_351x_ops = {
+ .ndo_init = gmac_init,
+ .ndo_uninit = gmac_uninit,
+ .ndo_open = gmac_open,
+ .ndo_stop = gmac_close,
+ .ndo_start_xmit = gmac_start_xmit,
+ .ndo_tx_timeout = gmac_dump_dma_state,
+ .ndo_set_multicast_list = gmac_set_multicast_list,
+ .ndo_set_rx_mode = gmac_set_rx_mode,
+ .ndo_set_mac_address = gmac_set_mac_address,
+ .ndo_get_stats64 = gmac_get_stats64,
+};
+
+const struct ethtool_ops gmac_351x_ethtool_ops = {
+ .get_rx_csum = gmac_get_rx_csum,
+ .set_rx_csum = gmac_set_rx_csum,
+ .get_tx_csum = ethtool_op_get_tx_csum,
+ .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
+ .get_sg = ethtool_op_get_sg,
+ .set_sg = ethtool_op_set_sg,
+ .get_tso = ethtool_op_get_tso,
+ .set_tso = gmac_set_tso,
+ .get_sset_count = gmac_get_sset_count,
+ .get_strings = gmac_get_strings,
+ .get_ethtool_stats = gmac_get_ethtool_stats,
+ .get_settings = gmac_get_settings,
+ .set_settings = gmac_set_settings,
+ .get_link = ethtool_op_get_link,
+ .nway_reset = gmac_nway_reset,
+ .get_pauseparam = gmac_get_pauseparam,
+ .get_msglevel = gmac_get_msglevel,
+ .set_msglevel = gmac_set_msglevel,
+ .get_drvinfo = gmac_get_drvinfo,
+};
+
+static int __devinit gmac_init_netdev(struct toe_private *toe, int num,
+ struct platform_device *pdev)
+{
+ struct gemini_gmac_platform_data *pdata = pdev->dev.platform_data;
+ struct gmac_private *gmac;
+ struct net_device *dev;
+ __le32 addr[3];
+ int irq, err;
+
+ if (!pdata->bus_id[num])
+ return 0;
+
+ irq = platform_get_irq(pdev, num);
+ if (irq < 0) {
+ dev_err(toe->dev, "No IRQ for ethernet device #%d\n", num);
+ return irq;
+ }
+
+ dev = alloc_etherdev_mq(sizeof(*gmac), TX_QUEUE_NUM);
+ if (!dev) {
+ dev_err(toe->dev, "Can't allocate ethernet device #%d\n", num);
+ return -ENOMEM;
+ }
+
+ gmac = netdev_priv(dev);
+ dev->ml_priv = toe;
+ SET_NETDEV_DEV(dev, toe->dev);
+
+ toe->netdev[num] = dev;
+ dev->dev_id = num;
+
+ gmac->dma_iomem = toe->iomem + TOE_GMAC_DMA_BASE(num);
+ dev->base_addr = (unsigned long)(toe->iomem + TOE_GMAC_BASE(num));
+ dev->irq = irq;
+
+ dev->netdev_ops = &gmac_351x_ops;
+ SET_ETHTOOL_OPS(dev, &gmac_351x_ethtool_ops);
+
+ spin_lock_init(&gmac->config_lock);
+ gmac->msg_enable = debug_level;
+ dev->tx_queue_len = 1 << DEFAULT_GMAC_TXQ_LEN_SHIFT;
+ gmac_clear_rx_stats(dev);
+
+ /* dump MAC address regs; CPU is LE anyway */
+ addr[0] = cpu_to_le32(__raw_readl(gmac_ctl_reg(dev, GMAC_STA_ADD0)));
+ addr[1] = cpu_to_le32(__raw_readl(gmac_ctl_reg(dev, GMAC_STA_ADD1)));
+ addr[2] = cpu_to_le32(__raw_readl(gmac_ctl_reg(dev, GMAC_STA_ADD2)));
+ dev_dbg(&pdev->dev, "port %d address regs: %pM %pM\n",
+ num, (char *)addr, (char *)addr + ETH_ALEN);
+
+ if (is_valid_ether_addr((void *)addr))
+ memcpy(dev->dev_addr, addr, ETH_ALEN);
+ else
+ random_ether_addr(dev->dev_addr);
+ __gmac_set_mac_address(dev);
+
+ err = register_netdev(dev);
+ if (!err)
+ return 0;
+
+ toe->netdev[num] = NULL;
+ free_netdev(dev);
+ return err;
+}
+
+static unsigned int __toe_fill_freeq(struct toe_private *toe,
+ unsigned int begin, unsigned int end)
+{
+ void __iomem *ptr_reg = toe_reg(toe, GLOBAL_SWFQ_RWPTR_REG);
+ GMAC_RXDESC_T *desc;
+ struct sk_buff *skb;
+ unsigned count;
+
+ dev_dbg(toe->dev, "freeq: filling <%u,%u) (ptr: %u %u)\n",
+ begin, end, GET_RPTR(ptr_reg), GET_WPTR(ptr_reg));
+
+ desc = toe->freeq_ring + begin;
+
+ for (count = 0; begin != end; ++begin, ++count) {
+ skb = __dev_alloc_skb(toe->freeq_skb_size + SKB_PRIVATE_BYTES, GFP_KERNEL);
+ if (!skb)
+ break;
+
+ skb->ip_summed = CHECKSUM_NONE;
+
+ toe_set_rx_skb(desc, skb);
+
+ /* only word2 gets copied to rxq descriptor */
+ /* buffer size is taken from DMA_SKB_SIZE_REG */
+ desc->word2.buf_adr = dma_map_single(toe->dev,
+ skb->data, skb_end_pointer(skb) - skb->data,
+ DMA_FROM_DEVICE);
+
+ if (!count)
+ dev_dbg(toe->dev, "freeq[%u]: 0x%08x 0x%08x 0x%08x 0x%08x, skbd %p, skb %p\n",
+ begin, desc->word0.bits32, desc->word1.bits32,
+ desc->word2.bits32, desc->word3.bits32, skb->data, skb);
+ ++desc;
+ }
+
+ SET_WPTR(ptr_reg, begin & __RWPTR_MASK(toe->freeq_size2));
+
+ return count;
+}
+
+static void toe_enable_irq(struct toe_private *toe, int enable)
+{
+ void __iomem *irqen_reg = toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_4_REG);
+
+ unsigned long flags;
+ unsigned val;
+
+ spin_lock_irqsave(&toe->irq_lock, flags);
+
+ val = __raw_readl(irqen_reg);
+ if (enable)
+ val |= SWFQ_EMPTY_INT_BIT;
+ else
+ val &= ~SWFQ_EMPTY_INT_BIT;
+ __raw_writel(val, irqen_reg);
+
+ spin_unlock_irqrestore(&toe->irq_lock, flags);
+}
+
+static irqreturn_t toe_interrupt(int irq, void *data)
+{
+ struct toe_private *toe = data;
+
+ void __iomem *irqif_reg = toe_reg(toe, GLOBAL_INTERRUPT_STATUS_4_REG);
+ void __iomem *irqen_reg = toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_4_REG);
+ unsigned val, en;
+ irqreturn_t ret = IRQ_NONE;
+
+ spin_lock(&toe->irq_lock);
+
+ val = __raw_readl(irqif_reg);
+ val &= en = __raw_readl(irqen_reg);
+
+ if (val & SWFQ_EMPTY_INT_BIT) {
+ toe_enable_irq(toe, 0);
+ ret = IRQ_WAKE_THREAD;
+ }
+
+ spin_unlock(&toe->irq_lock);
+
+ return ret;
+}
+
+static irqreturn_t toe_interrupt_thread(int irq, void *data)
+{
+ struct toe_private *toe = data;
+
+ void __iomem *irqif_reg = toe_reg(toe, GLOBAL_INTERRUPT_STATUS_4_REG);
+ void __iomem *rwptr_reg = toe_reg(toe, GLOBAL_SWFQ_RWPTR_REG);
+ unsigned r, w, count;
+
+ w = GET_WPTR(rwptr_reg);
+ r = RWPTR_PREV(GET_RPTR(rwptr_reg), toe->freeq_size2);
+ if (w <= r)
+ count = __toe_fill_freeq(toe, w, r);
+ else {
+ count = __toe_fill_freeq(toe, w, 1 << toe->freeq_size2);
+ r = GET_RPTR(rwptr_reg);
+ if (r > 0)
+ count += __toe_fill_freeq(toe, 0, r - 1);
+ }
+
+ dev_dbg(toe->dev, "freeq: filled %u skbs\n", count);
+
+ __raw_writel(SWFQ_EMPTY_INT_BIT, irqif_reg);
+ toe_enable_irq(toe, 1);
+
+ return IRQ_HANDLED;
+}
+
+static int __devinit toe_setup_freeq(struct toe_private *toe)
+{
+ void __iomem *dma_reg = toe_reg(toe, GLOBAL_SW_FREEQ_BASE_SIZE_REG);
+ unsigned nskb = (1 << toe->freeq_size2) - 1;
+ QUEUE_THRESHOLD_T qt;
+ DMA_SKB_SIZE_T skbsz = { .bits = { .sw_skb_size = toe->freeq_skb_size } };
+ unsigned n;
+
+ toe->freeq_ring = dma_alloc_coherent(toe->dev,
+ sizeof(*toe->freeq_ring) << toe->freeq_size2,
+ &toe->freeq_dma_base, GFP_KERNEL);
+ if (!toe->freeq_ring)
+ return -ENOMEM;
+
+ BUG_ON(toe->freeq_dma_base & ~DMA_Q_BASE_MASK);
+
+ __raw_writel(toe->freeq_dma_base | toe->freeq_size2, dma_reg);
+ __raw_writel(skbsz.bits32, toe_reg(toe, GLOBAL_DMA_SKB_SIZE_REG));
+
+ /* fill ring */
+ n = __toe_fill_freeq(toe, 0, nskb);
+ if (!n)
+ goto err_freeq;
+ if (n != nskb)
+ dev_warn(toe->dev, "Allocated only %u of %u RX skbs\n",
+ n, nskb);
+
+ qt.bits32 = __raw_readl(toe_reg(toe, GLOBAL_QUEUE_THRESHOLD_REG));
+ qt.bits.swfq_empty = min_t(unsigned, (n + 1) >> 1, 255);
+ __raw_writel(qt.bits32, toe_reg(toe, GLOBAL_QUEUE_THRESHOLD_REG));
+
+ dev_dbg(toe->dev, "freeq: ring %p (dma 0x%08x), len %u (order %u), thr %u\n",
+ toe->freeq_ring, toe->freeq_dma_base,
+ 1 << toe->freeq_size2, toe->freeq_size2, qt.bits.swfq_empty);
+
+ return 0;
+
+err_freeq:
+ __raw_writel(0, dma_reg);
+ dma_free_coherent(toe->dev, sizeof(*toe->freeq_ring) << toe->freeq_size2,
+ toe->freeq_ring, toe->freeq_dma_base);
+
+ return -ENOMEM;
+}
+
+static void toe_cleanup_freeq(struct toe_private *toe)
+{
+ void __iomem *dma_reg = toe_reg(toe, GLOBAL_SW_FREEQ_BASE_SIZE_REG);
+ void __iomem *ptr_reg = toe_reg(toe, GLOBAL_SWFQ_RWPTR_REG);
+ struct sk_buff *skb;
+ unsigned i, e, mask = __RWPTR_MASK(toe->freeq_size2);
+
+ i = GET_RPTR(ptr_reg);
+ e = GET_WPTR(ptr_reg);
+ __raw_writel(0, ptr_reg);
+ __raw_writel(0, dma_reg);
+
+ for (; i != e; i = __RWPTR_NEXT(i, mask)) {
+ skb = toe_get_rx_skb(toe->freeq_ring + i);
+
+ dma_unmap_single(toe->dev, toe->freeq_ring[i].word2.buf_adr,
+ skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE);
+ kfree_skb(skb);
+ }
+
+ dma_free_coherent(toe->dev, sizeof(*toe->freeq_ring) << toe->freeq_size2,
+ toe->freeq_ring, toe->freeq_dma_base);
+}
+
+/*
+ * Interrupt config:
+ *
+ * GMAC0 intr bits ------> int0 ----> eth0
+ * GMAC1 intr bits ------> int1 ----> eth1
+ * TOE intr -------------> int1 ----> eth1
+ * Classification Intr --> int0 ----> eth0
+ * Default Q0 -----------> int0 ----> eth0
+ * Default Q1 -----------> int1 ----> eth1
+ * FreeQ intr -----------> int1 ----> eth1
+ */
+static void toe_prepare_irq(struct toe_private *toe)
+{
+ __raw_writel(0, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_0_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_1_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_2_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_3_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_INTERRUPT_ENABLE_4_REG));
+
+ __raw_writel(0xCCFC0FC0, toe_reg(toe, GLOBAL_INTERRUPT_SELECT_0_REG));
+ __raw_writel(0x00F00002, toe_reg(toe, GLOBAL_INTERRUPT_SELECT_1_REG));
+ __raw_writel(0xFFFFFFFF, toe_reg(toe, GLOBAL_INTERRUPT_SELECT_2_REG));
+ __raw_writel(0xFFFFFFFF, toe_reg(toe, GLOBAL_INTERRUPT_SELECT_3_REG));
+ __raw_writel(0xFF000003, toe_reg(toe, GLOBAL_INTERRUPT_SELECT_4_REG));
+
+ __raw_writel(~0, toe_reg(toe, GLOBAL_INTERRUPT_STATUS_0_REG));
+ __raw_writel(~0, toe_reg(toe, GLOBAL_INTERRUPT_STATUS_1_REG));
+ __raw_writel(~0, toe_reg(toe, GLOBAL_INTERRUPT_STATUS_2_REG));
+ __raw_writel(~0, toe_reg(toe, GLOBAL_INTERRUPT_STATUS_3_REG));
+ __raw_writel(~0, toe_reg(toe, GLOBAL_INTERRUPT_STATUS_4_REG));
+}
+
+static __devinit int toe_init(struct toe_private *toe, struct platform_device *pdev)
+{
+ int err;
+
+ __raw_writel(0, toe_reg(toe, GLOBAL_SW_FREEQ_BASE_SIZE_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_HW_FREEQ_BASE_SIZE_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_SWFQ_RWPTR_REG));
+ __raw_writel(0, toe_reg(toe, GLOBAL_HWFQ_RWPTR_REG));
+
+ toe->freeq_skb_size = DEFAULT_RX_SKB_SIZE;
+ toe->freeq_size2 = DEFAULT_GMAC_FREEQ_LEN_SHIFT;
+ err = toe_setup_freeq(toe);
+ if (err)
+ return err;
+
+ toe_prepare_irq(toe);
+ err = request_threaded_irq(toe->irq, toe_interrupt, toe_interrupt_thread,
+ IRQF_SHARED, "sl351x-TOE", toe);
+ if (err)
+ goto err_freeq;
+
+ toe_enable_irq(toe, 1);
+
+ return 0;
+
+err_freeq:
+ toe_cleanup_freeq(toe);
+ return err;
+}
+
+static void toe_deinit(struct toe_private *toe)
+{
+ toe_prepare_irq(toe);
+ free_irq(toe->irq, toe);
+ toe_cleanup_freeq(toe);
+}
+
+static int toe_reset(struct toe_private *toe)
+{
+ unsigned int reg, retry = 5;
+
+ reg = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
+ reg |= RESET_GMAC1 | RESET_GMAC0;
+ __raw_writel(reg, IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
+
+ do {
+ udelay(2);
+ reg = __raw_readl(toe_reg(toe, GLOBAL_TOE_VERSION_REG));
+ barrier();
+ } while (!reg && --retry);
+
+ dev_info(toe->dev, "Gemini GMAC version 0x%x\n", reg);
+
+ return reg ? 0 : -EIO;
+}
+
+static int __devinit gemini_gmac_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ struct toe_private *toe;
+ int retval;
+
+ if (!pdev->dev.platform_data)
+ return -EINVAL;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "can't get device resources\n");
+ return -ENODEV;
+ }
+
+ toe = kzalloc(sizeof(*toe), GFP_KERNEL);
+ if (!toe)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, toe);
+ toe->dev = &pdev->dev;
+ toe->iomem = ioremap(res->start, resource_size(res));
+ if (!toe->iomem) {
+ dev_err(toe->dev, "ioremap failed\n");
+ retval = -EIO;
+ goto err_data;
+ }
+
+ retval = toe_reset(toe);
+ if (retval < 0)
+ goto err_unmap;
+
+ retval = toe->irq = platform_get_irq(pdev, 1);
+ if (retval < 0)
+ goto err_unmap;
+
+ spin_lock_init(&toe->irq_lock);
+
+ retval = toe_init(toe, pdev);
+ if (retval)
+ goto err_unmap;
+
+ retval = gmac_init_netdev(toe, 0, pdev);
+ if (retval)
+ goto err_uninit;
+
+ retval = gmac_init_netdev(toe, 1, pdev);
+ if (retval)
+ goto err_uninit;
+
+ dev_dbg(&pdev->dev, "initialized.\n");
+ return 0;
+
+err_uninit:
+ if (toe->netdev[0])
+ unregister_netdev(toe->netdev[0]);
+ toe_deinit(toe);
+err_unmap:
+ iounmap(toe->iomem);
+err_data:
+ kfree(toe);
+ return retval;
+}
+
+static int __devexit gemini_gmac_remove(struct platform_device *pdev)
+{
+ struct toe_private *toe = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < 2; i++)
+ if (toe->netdev[i])
+ unregister_netdev(toe->netdev[i]);
+ toe_deinit(toe);
+
+ iounmap(toe->iomem);
+ kfree(toe);
+
+ return 0;
+}
+
+static struct platform_driver gemini_gmac_driver = {
+ .probe = gemini_gmac_probe,
+ .remove = __devexit_p(gemini_gmac_remove),
+ .driver.name = "gemini-gmac",
+ .driver.owner = THIS_MODULE,
+};
+
+static int __init gemini_gmac_init(void)
+{
+ return platform_driver_register(&gemini_gmac_driver);
+}
+
+static void __exit gemini_gmac_exit(void)
+{
+ platform_driver_unregister(&gemini_gmac_driver);
+}
+
+module_init(gemini_gmac_init);
+module_exit(gemini_gmac_exit);
+
+MODULE_AUTHOR("Michał Mirosław");
+MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:gemini-gmac");
diff --git a/drivers/net/sl351x_hw.h b/drivers/net/sl351x_hw.h
new file mode 100644
index 0000000..2a1c7cc
--- /dev/null
+++ b/drivers/net/sl351x_hw.h
@@ -0,0 +1,1423 @@
+/*
+ * Register definitions for Gemini LEPUS GMAC Ethernet device driver.
+ *
+ * Copyright (C) 2006, Storlink, Corp.
+ * Copyright (C) 2008-2009, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ * Copyright (C) 2010, Michał Mirosław <mirq-linux@rere.qmqm.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef _GMAC_HW_H
+#define _GMAC_HW_H
+
+#include <linux/bitops.h>
+
+/*
+ * Base Registers
+ */
+#define TOE_NONTOE_QUE_HDR_BASE 0x2000
+#define TOE_TOE_QUE_HDR_BASE 0x3000
+#define TOE_V_BIT_BASE 0x4000
+#define TOE_A_BIT_BASE 0x6000
+#define TOE_GMAC_DMA_BASE(x) (0x8000 + 0x4000 * (x))
+#define TOE_GMAC_BASE(x) (0xA000 + 0x4000 * (x))
+
+/*
+ * Queue ID
+ */
+#define TOE_SW_FREE_QID 0x00
+#define TOE_HW_FREE_QID 0x01
+#define TOE_GMAC0_SW_TXQ0_QID 0x02
+#define TOE_GMAC0_SW_TXQ1_QID 0x03
+#define TOE_GMAC0_SW_TXQ2_QID 0x04
+#define TOE_GMAC0_SW_TXQ3_QID 0x05
+#define TOE_GMAC0_SW_TXQ4_QID 0x06
+#define TOE_GMAC0_SW_TXQ5_QID 0x07
+#define TOE_GMAC0_HW_TXQ0_QID 0x08
+#define TOE_GMAC0_HW_TXQ1_QID 0x09
+#define TOE_GMAC0_HW_TXQ2_QID 0x0A
+#define TOE_GMAC0_HW_TXQ3_QID 0x0B
+#define TOE_GMAC1_SW_TXQ0_QID 0x12
+#define TOE_GMAC1_SW_TXQ1_QID 0x13
+#define TOE_GMAC1_SW_TXQ2_QID 0x14
+#define TOE_GMAC1_SW_TXQ3_QID 0x15
+#define TOE_GMAC1_SW_TXQ4_QID 0x16
+#define TOE_GMAC1_SW_TXQ5_QID 0x17
+#define TOE_GMAC1_HW_TXQ0_QID 0x18
+#define TOE_GMAC1_HW_TXQ1_QID 0x19
+#define TOE_GMAC1_HW_TXQ2_QID 0x1A
+#define TOE_GMAC1_HW_TXQ3_QID 0x1B
+#define TOE_GMAC0_DEFAULT_QID 0x20
+#define TOE_GMAC1_DEFAULT_QID 0x21
+#define TOE_CLASSIFICATION_QID(x) (0x22 + x) // 0x22 ~ 0x2F
+#define TOE_TOE_QID(x) (0x40 + x) // 0x40 ~ 0x7F
+
+/*
+ * old info:
+ * TOE DMA Queue Size should be 2^n, n = 6...12
+ * TOE DMA Queues are the following queue types:
+ * SW Free Queue, HW Free Queue,
+ * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
+ * The base address and descriptor number are configured at
+ * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
+ */
+
+#define GET_WPTR(addr) __raw_readw((addr) + 2)
+#define GET_RPTR(addr) __raw_readw((addr))
+#define SET_WPTR(addr, data) __raw_writew((data), (addr) + 2)
+#define SET_RPTR(addr, data) __raw_writew((data), (addr))
+#define __RWPTR_NEXT(x, mask) (((unsigned int)(x) + 1) & (mask))
+#define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
+#define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
+#define __RWPTR_MASK(order) ((1 << (order)) - 1)
+#define RWPTR_NEXT(x, order) __RWPTR_NEXT(x, __RWPTR_MASK(order))
+#define RWPTR_PREV(x, order) __RWPTR_PREV(x, __RWPTR_MASK(order))
+
+/*
+ * Global registers
+ * #define TOE_GLOBAL_BASE (TOE_BASE + 0x0000)
+ * Base 0x60000000
+ */
+#define GLOBAL_TOE_VERSION_REG 0x0000
+#define GLOBAL_SW_FREEQ_BASE_SIZE_REG 0x0004
+#define GLOBAL_HW_FREEQ_BASE_SIZE_REG 0x0008
+#define GLOBAL_DMA_SKB_SIZE_REG 0x0010
+#define GLOBAL_SWFQ_RWPTR_REG 0x0014
+#define GLOBAL_HWFQ_RWPTR_REG 0x0018
+#define GLOBAL_INTERRUPT_STATUS_0_REG 0x0020
+#define GLOBAL_INTERRUPT_ENABLE_0_REG 0x0024
+#define GLOBAL_INTERRUPT_SELECT_0_REG 0x0028
+#define GLOBAL_INTERRUPT_STATUS_1_REG 0x0030
+#define GLOBAL_INTERRUPT_ENABLE_1_REG 0x0034
+#define GLOBAL_INTERRUPT_SELECT_1_REG 0x0038
+#define GLOBAL_INTERRUPT_STATUS_2_REG 0x0040
+#define GLOBAL_INTERRUPT_ENABLE_2_REG 0x0044
+#define GLOBAL_INTERRUPT_SELECT_2_REG 0x0048
+#define GLOBAL_INTERRUPT_STATUS_3_REG 0x0050
+#define GLOBAL_INTERRUPT_ENABLE_3_REG 0x0054
+#define GLOBAL_INTERRUPT_SELECT_3_REG 0x0058
+#define GLOBAL_INTERRUPT_STATUS_4_REG 0x0060
+#define GLOBAL_INTERRUPT_ENABLE_4_REG 0x0064
+#define GLOBAL_INTERRUPT_SELECT_4_REG 0x0068
+#define GLOBAL_HASH_TABLE_BASE_REG 0x006C
+#define GLOBAL_QUEUE_THRESHOLD_REG 0x0070
+
+/*
+ * GMAC 0/1 DMA/TOE register
+ * #define TOE_GMAC0_DMA_BASE (TOE_BASE + 0x8000)
+ * #define TOE_GMAC1_DMA_BASE (TOE_BASE + 0xC000)
+ * Base 0x60008000 or 0x6000C000
+ */
+#define GMAC_DMA_CTRL_REG 0x0000
+#define GMAC_TX_WEIGHTING_CTRL_0_REG 0x0004
+#define GMAC_TX_WEIGHTING_CTRL_1_REG 0x0008
+#define GMAC_SW_TX_QUEUE0_PTR_REG 0x000C
+#define GMAC_SW_TX_QUEUE1_PTR_REG 0x0010
+#define GMAC_SW_TX_QUEUE2_PTR_REG 0x0014
+#define GMAC_SW_TX_QUEUE3_PTR_REG 0x0018
+#define GMAC_SW_TX_QUEUE4_PTR_REG 0x001C
+#define GMAC_SW_TX_QUEUE5_PTR_REG 0x0020
+#define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
+#define GMAC_HW_TX_QUEUE0_PTR_REG 0x0024
+#define GMAC_HW_TX_QUEUE1_PTR_REG 0x0028
+#define GMAC_HW_TX_QUEUE2_PTR_REG 0x002C
+#define GMAC_HW_TX_QUEUE3_PTR_REG 0x0030
+#define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
+#define GMAC_DMA_TX_FIRST_DESC_REG 0x0038
+#define GMAC_DMA_TX_CURR_DESC_REG 0x003C
+#define GMAC_DMA_TX_DESC_WORD0_REG 0x0040
+#define GMAC_DMA_TX_DESC_WORD1_REG 0x0044
+#define GMAC_DMA_TX_DESC_WORD2_REG 0x0048
+#define GMAC_DMA_TX_DESC_WORD3_REG 0x004C
+#define GMAC_SW_TX_QUEUE_BASE_REG 0x0050
+#define GMAC_HW_TX_QUEUE_BASE_REG 0x0054
+#define GMAC_DMA_RX_FIRST_DESC_REG 0x0058
+#define GMAC_DMA_RX_CURR_DESC_REG 0x005C
+#define GMAC_DMA_RX_DESC_WORD0_REG 0x0060
+#define GMAC_DMA_RX_DESC_WORD1_REG 0x0064
+#define GMAC_DMA_RX_DESC_WORD2_REG 0x0068
+#define GMAC_DMA_RX_DESC_WORD3_REG 0x006C
+#define GMAC_HASH_ENGINE_REG0 0x0070
+#define GMAC_HASH_ENGINE_REG1 0x0074
+/* matching rule 0 Control register 0 */
+#define GMAC_MR0CR0 0x0078
+#define GMAC_MR0CR1 0x007C
+#define GMAC_MR0CR2 0x0080
+#define GMAC_MR1CR0 0x0084
+#define GMAC_MR1CR1 0x0088
+#define GMAC_MR1CR2 0x008C
+#define GMAC_MR2CR0 0x0090
+#define GMAC_MR2CR1 0x0094
+#define GMAC_MR2CR2 0x0098
+#define GMAC_MR3CR0 0x009C
+#define GMAC_MR3CR1 0x00A0
+#define GMAC_MR3CR2 0x00A4
+/* Support Protocol Regsister 0 */
+#define GMAC_SPR0 0x00A8
+#define GMAC_SPR1 0x00AC
+#define GMAC_SPR2 0x00B0
+#define GMAC_SPR3 0x00B4
+#define GMAC_SPR4 0x00B8
+#define GMAC_SPR5 0x00BC
+#define GMAC_SPR6 0x00C0
+#define GMAC_SPR7 0x00C4
+/* GMAC Hash/Rx/Tx AHB Weighting register */
+#define GMAC_AHB_WEIGHT_REG 0x00C8
+
+/*
+ * TOE GMAC 0/1 register
+ * #define TOE_GMAC0_BASE (TOE_BASE + 0xA000)
+ * #define TOE_GMAC1_BASE (TOE_BASE + 0xE000)
+ * Base 0x6000A000 or 0x6000E000
+ */
+enum GMAC_REGISTER {
+ GMAC_STA_ADD0 = 0x0000,
+ GMAC_STA_ADD1 = 0x0004,
+ GMAC_STA_ADD2 = 0x0008,
+ GMAC_RX_FLTR = 0x000c,
+ GMAC_MCAST_FIL0 = 0x0010,
+ GMAC_MCAST_FIL1 = 0x0014,
+ GMAC_CONFIG0 = 0x0018,
+ GMAC_CONFIG1 = 0x001c,
+ GMAC_CONFIG2 = 0x0020,
+ GMAC_CONFIG3 = 0x0024,
+ GMAC_RESERVED = 0x0028,
+ GMAC_STATUS = 0x002c,
+ GMAC_IN_DISCARDS= 0x0030,
+ GMAC_IN_ERRORS = 0x0034,
+ GMAC_IN_MCAST = 0x0038,
+ GMAC_IN_BCAST = 0x003c,
+ GMAC_IN_MAC1 = 0x0040, /* for STA 1 MAC Address */
+ GMAC_IN_MAC2 = 0x0044 /* for STA 2 MAC Address */
+};
+
+#define RX_STATS_NUM 6
+
+/*
+ * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int base_size;
+} DMA_Q_BASE_SIZE_T;
+#define DMA_Q_BASE_MASK (~0x0f)
+
+/*
+ * DMA SKB Buffer register (offset 0x0008)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0008 {
+ unsigned int sw_skb_size : 16; /* SW Free poll SKB Size */
+ unsigned int hw_skb_size : 16; /* HW Free poll SKB Size */
+ } bits;
+} DMA_SKB_SIZE_T;
+
+/*
+ * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_000c {
+ unsigned int rptr : 16; /* Read Ptr, RO */
+ unsigned int wptr : 16; /* Write Ptr, RW */
+ } bits;
+} DMA_RWPTR_T;
+
+/*
+ * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
+ * see DMA_RWPTR_T structure
+ */
+
+/*
+ * Interrupt Status Register 0 (offset 0x0020)
+ * Interrupt Mask Register 0 (offset 0x0024)
+ * Interrupt Select Register 0 (offset 0x0028)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0020 {
+ /* GMAC0 SW Tx Queue 0 EOF Interrupt */
+ unsigned int swtq00_eof : 1;
+ unsigned int swtq01_eof : 1;
+ unsigned int swtq02_eof : 1;
+ unsigned int swtq03_eof : 1;
+ unsigned int swtq04_eof : 1;
+ unsigned int swtq05_eof : 1;
+ /* GMAC1 SW Tx Queue 0 EOF Interrupt */
+ unsigned int swtq10_eof : 1;
+ unsigned int swtq11_eof : 1;
+ unsigned int swtq12_eof : 1;
+ unsigned int swtq13_eof : 1;
+ unsigned int swtq14_eof : 1;
+ unsigned int swtq15_eof : 1;
+ /* GMAC0 SW Tx Queue 0 Finish Interrupt */
+ unsigned int swtq00_fin : 1;
+ unsigned int swtq01_fin : 1;
+ unsigned int swtq02_fin : 1;
+ unsigned int swtq03_fin : 1;
+ unsigned int swtq04_fin : 1;
+ unsigned int swtq05_fin : 1;
+ /* GMAC1 SW Tx Queue 0 Finish Interrupt */
+ unsigned int swtq10_fin : 1;
+ unsigned int swtq11_fin : 1;
+ unsigned int swtq12_fin : 1;
+ unsigned int swtq13_fin : 1;
+ unsigned int swtq14_fin : 1;
+ unsigned int swtq15_fin : 1;
+ /* GMAC0 Rx Descriptor Protocol Error */
+ unsigned int rxPerr0 : 1;
+ /* GMAC0 AHB Bus Error while Rx */
+ unsigned int rxDerr0 : 1;
+ /* GMAC1 Rx Descriptor Protocol Error */
+ unsigned int rxPerr1 : 1;
+ /* GMAC1 AHB Bus Error while Rx */
+ unsigned int rxDerr1 : 1;
+ /* GMAC0 Tx Descriptor Protocol Error */
+ unsigned int txPerr0 : 1;
+ /* GMAC0 AHB Bus Error while Tx */
+ unsigned int txDerr0 : 1;
+ /* GMAC1 Tx Descriptor Protocol Error */
+ unsigned int txPerr1 : 1;
+ /* GMAC1 AHB Bus Error while Tx */
+ unsigned int txDerr1 : 1;
+ } bits;
+} INTR_REG0_T;
+
+#define GMAC1_TXDERR_INT_BIT BIT(31)
+#define GMAC1_TXPERR_INT_BIT BIT(30)
+#define GMAC0_TXDERR_INT_BIT BIT(29)
+#define GMAC0_TXPERR_INT_BIT BIT(28)
+#define GMAC1_RXDERR_INT_BIT BIT(27)
+#define GMAC1_RXPERR_INT_BIT BIT(26)
+#define GMAC0_RXDERR_INT_BIT BIT(25)
+#define GMAC0_RXPERR_INT_BIT BIT(24)
+#define GMAC1_SWTQ15_FIN_INT_BIT BIT(23)
+#define GMAC1_SWTQ14_FIN_INT_BIT BIT(22)
+#define GMAC1_SWTQ13_FIN_INT_BIT BIT(21)
+#define GMAC1_SWTQ12_FIN_INT_BIT BIT(20)
+#define GMAC1_SWTQ11_FIN_INT_BIT BIT(19)
+#define GMAC1_SWTQ10_FIN_INT_BIT BIT(18)
+#define GMAC0_SWTQ05_FIN_INT_BIT BIT(17)
+#define GMAC0_SWTQ04_FIN_INT_BIT BIT(16)
+#define GMAC0_SWTQ03_FIN_INT_BIT BIT(15)
+#define GMAC0_SWTQ02_FIN_INT_BIT BIT(14)
+#define GMAC0_SWTQ01_FIN_INT_BIT BIT(13)
+#define GMAC0_SWTQ00_FIN_INT_BIT BIT(12)
+#define GMAC1_SWTQ15_EOF_INT_BIT BIT(11)
+#define GMAC1_SWTQ14_EOF_INT_BIT BIT(10)
+#define GMAC1_SWTQ13_EOF_INT_BIT BIT(9)
+#define GMAC1_SWTQ12_EOF_INT_BIT BIT(8)
+#define GMAC1_SWTQ11_EOF_INT_BIT BIT(7)
+#define GMAC1_SWTQ10_EOF_INT_BIT BIT(6)
+#define GMAC0_SWTQ05_EOF_INT_BIT BIT(5)
+#define GMAC0_SWTQ04_EOF_INT_BIT BIT(4)
+#define GMAC0_SWTQ03_EOF_INT_BIT BIT(3)
+#define GMAC0_SWTQ02_EOF_INT_BIT BIT(2)
+#define GMAC0_SWTQ01_EOF_INT_BIT BIT(1)
+#define GMAC0_SWTQ00_EOF_INT_BIT BIT(0)
+
+/*
+ * Interrupt Status Register 1 (offset 0x0030)
+ * Interrupt Mask Register 1 (offset 0x0034)
+ * Interrupt Select Register 1 (offset 0x0038)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0030 {
+ unsigned int default_q0_eof : 1; /* Default Queue 0 EOF Interrupt */
+ unsigned int default_q1_eof : 1; /* Default Queue 1 EOF Interrupt */
+ unsigned int class_rx : 14; /* Classification Queue Rx Interrupt */
+ unsigned int hwtq00_eof : 1; /* GMAC0 HW Tx Queue0 EOF Interrupt */
+ unsigned int hwtq01_eof : 1; /* GMAC0 HW Tx Queue1 EOF Interrupt */
+ unsigned int hwtq02_eof : 1; /* GMAC0 HW Tx Queue2 EOF Interrupt */
+ unsigned int hwtq03_eof : 1; /* GMAC0 HW Tx Queue3 EOF Interrupt */
+ unsigned int hwtq10_eof : 1; /* GMAC1 HW Tx Queue0 EOF Interrupt */
+ unsigned int hwtq11_eof : 1; /* GMAC1 HW Tx Queue1 EOF Interrupt */
+ unsigned int hwtq12_eof : 1; /* GMAC1 HW Tx Queue2 EOF Interrupt */
+ unsigned int hwtq13_eof : 1; /* GMAC1 HW Tx Queue3 EOF Interrupt */
+ unsigned int toe_iq0_intr : 1; /* TOE Interrupt Queue 0 with Interrupts */
+ unsigned int toe_iq1_intr : 1; /* TOE Interrupt Queue 1 with Interrupts */
+ unsigned int toe_iq2_intr : 1; /* TOE Interrupt Queue 2 with Interrupts */
+ unsigned int toe_iq3_intr : 1; /* TOE Interrupt Queue 3 with Interrupts */
+ unsigned int toe_iq0_full : 1; /* TOE Interrupt Queue 0 Full Interrupt */
+ unsigned int toe_iq1_full : 1; /* TOE Interrupt Queue 1 Full Interrupt */
+ unsigned int toe_iq2_full : 1; /* TOE Interrupt Queue 2 Full Interrupt */
+ unsigned int toe_iq3_full : 1; /* TOE Interrupt Queue 3 Full Interrupt */
+ } bits;
+} INTR_REG1_T;
+
+#define TOE_IQ3_FULL_INT_BIT BIT(31)
+#define TOE_IQ2_FULL_INT_BIT BIT(30)
+#define TOE_IQ1_FULL_INT_BIT BIT(29)
+#define TOE_IQ0_FULL_INT_BIT BIT(28)
+#define TOE_IQ3_INT_BIT BIT(27)
+#define TOE_IQ2_INT_BIT BIT(26)
+#define TOE_IQ1_INT_BIT BIT(25)
+#define TOE_IQ0_INT_BIT BIT(24)
+#define GMAC1_HWTQ13_EOF_INT_BIT BIT(23)
+#define GMAC1_HWTQ12_EOF_INT_BIT BIT(22)
+#define GMAC1_HWTQ11_EOF_INT_BIT BIT(21)
+#define GMAC1_HWTQ10_EOF_INT_BIT BIT(20)
+#define GMAC0_HWTQ03_EOF_INT_BIT BIT(19)
+#define GMAC0_HWTQ02_EOF_INT_BIT BIT(18)
+#define GMAC0_HWTQ01_EOF_INT_BIT BIT(17)
+#define GMAC0_HWTQ00_EOF_INT_BIT BIT(16)
+#define CLASS_RX_INT_BIT(x) BIT((x + 2))
+#define DEFAULT_Q1_INT_BIT BIT(1)
+#define DEFAULT_Q0_INT_BIT BIT(0)
+
+#define TOE_IQ_INT_BITS (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
+ TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
+#define TOE_IQ_FULL_BITS (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
+ TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
+#define TOE_IQ_ALL_BITS (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
+#define TOE_CLASS_RX_INT_BITS 0xfffc
+
+/*
+ * Interrupt Status Register 2 (offset 0x0040)
+ * Interrupt Mask Register 2 (offset 0x0044)
+ * Interrupt Select Register 2 (offset 0x0048)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0040 {
+ unsigned int toe_q0_full : 1; // bit 0 TOE Queue 0 Full Interrupt
+ unsigned int toe_q1_full : 1; // bit 1 TOE Queue 1 Full Interrupt
+ unsigned int toe_q2_full : 1; // bit 2 TOE Queue 2 Full Interrupt
+ unsigned int toe_q3_full : 1; // bit 3 TOE Queue 3 Full Interrupt
+ unsigned int toe_q4_full : 1; // bit 4 TOE Queue 4 Full Interrupt
+ unsigned int toe_q5_full : 1; // bit 5 TOE Queue 5 Full Interrupt
+ unsigned int toe_q6_full : 1; // bit 6 TOE Queue 6 Full Interrupt
+ unsigned int toe_q7_full : 1; // bit 7 TOE Queue 7 Full Interrupt
+ unsigned int toe_q8_full : 1; // bit 8 TOE Queue 8 Full Interrupt
+ unsigned int toe_q9_full : 1; // bit 9 TOE Queue 9 Full Interrupt
+ unsigned int toe_q10_full : 1; // bit 10 TOE Queue 10 Full Interrupt
+ unsigned int toe_q11_full : 1; // bit 11 TOE Queue 11 Full Interrupt
+ unsigned int toe_q12_full : 1; // bit 12 TOE Queue 12 Full Interrupt
+ unsigned int toe_q13_full : 1; // bit 13 TOE Queue 13 Full Interrupt
+ unsigned int toe_q14_full : 1; // bit 14 TOE Queue 14 Full Interrupt
+ unsigned int toe_q15_full : 1; // bit 15 TOE Queue 15 Full Interrupt
+ unsigned int toe_q16_full : 1; // bit 16 TOE Queue 16 Full Interrupt
+ unsigned int toe_q17_full : 1; // bit 17 TOE Queue 17 Full Interrupt
+ unsigned int toe_q18_full : 1; // bit 18 TOE Queue 18 Full Interrupt
+ unsigned int toe_q19_full : 1; // bit 19 TOE Queue 19 Full Interrupt
+ unsigned int toe_q20_full : 1; // bit 20 TOE Queue 20 Full Interrupt
+ unsigned int toe_q21_full : 1; // bit 21 TOE Queue 21 Full Interrupt
+ unsigned int toe_q22_full : 1; // bit 22 TOE Queue 22 Full Interrupt
+ unsigned int toe_q23_full : 1; // bit 23 TOE Queue 23 Full Interrupt
+ unsigned int toe_q24_full : 1; // bit 24 TOE Queue 24 Full Interrupt
+ unsigned int toe_q25_full : 1; // bit 25 TOE Queue 25 Full Interrupt
+ unsigned int toe_q26_full : 1; // bit 26 TOE Queue 26 Full Interrupt
+ unsigned int toe_q27_full : 1; // bit 27 TOE Queue 27 Full Interrupt
+ unsigned int toe_q28_full : 1; // bit 28 TOE Queue 28 Full Interrupt
+ unsigned int toe_q29_full : 1; // bit 29 TOE Queue 29 Full Interrupt
+ unsigned int toe_q30_full : 1; // bit 30 TOE Queue 30 Full Interrupt
+ unsigned int toe_q31_full : 1; // bit 31 TOE Queue 31 Full Interrupt
+ } bits;
+} INTR_REG2_T;
+
+#define TOE_QL_FULL_INT_BIT(x) BIT(x)
+
+/*
+ * Interrupt Status Register 3 (offset 0x0050)
+ * Interrupt Mask Register 3 (offset 0x0054)
+ * Interrupt Select Register 3 (offset 0x0058)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0050 {
+ unsigned int toe_q32_full : 1; // bit 32 TOE Queue 32 Full Interrupt
+ unsigned int toe_q33_full : 1; // bit 33 TOE Queue 33 Full Interrupt
+ unsigned int toe_q34_full : 1; // bit 34 TOE Queue 34 Full Interrupt
+ unsigned int toe_q35_full : 1; // bit 35 TOE Queue 35 Full Interrupt
+ unsigned int toe_q36_full : 1; // bit 36 TOE Queue 36 Full Interrupt
+ unsigned int toe_q37_full : 1; // bit 37 TOE Queue 37 Full Interrupt
+ unsigned int toe_q38_full : 1; // bit 38 TOE Queue 38 Full Interrupt
+ unsigned int toe_q39_full : 1; // bit 39 TOE Queue 39 Full Interrupt
+ unsigned int toe_q40_full : 1; // bit 40 TOE Queue 40 Full Interrupt
+ unsigned int toe_q41_full : 1; // bit 41 TOE Queue 41 Full Interrupt
+ unsigned int toe_q42_full : 1; // bit 42 TOE Queue 42 Full Interrupt
+ unsigned int toe_q43_full : 1; // bit 43 TOE Queue 43 Full Interrupt
+ unsigned int toe_q44_full : 1; // bit 44 TOE Queue 44 Full Interrupt
+ unsigned int toe_q45_full : 1; // bit 45 TOE Queue 45 Full Interrupt
+ unsigned int toe_q46_full : 1; // bit 46 TOE Queue 46 Full Interrupt
+ unsigned int toe_q47_full : 1; // bit 47 TOE Queue 47 Full Interrupt
+ unsigned int toe_q48_full : 1; // bit 48 TOE Queue 48 Full Interrupt
+ unsigned int toe_q49_full : 1; // bit 49 TOE Queue 49 Full Interrupt
+ unsigned int toe_q50_full : 1; // bit 50 TOE Queue 50 Full Interrupt
+ unsigned int toe_q51_full : 1; // bit 51 TOE Queue 51 Full Interrupt
+ unsigned int toe_q52_full : 1; // bit 52 TOE Queue 52 Full Interrupt
+ unsigned int toe_q53_full : 1; // bit 53 TOE Queue 53 Full Interrupt
+ unsigned int toe_q54_full : 1; // bit 54 TOE Queue 54 Full Interrupt
+ unsigned int toe_q55_full : 1; // bit 55 TOE Queue 55 Full Interrupt
+ unsigned int toe_q56_full : 1; // bit 56 TOE Queue 56 Full Interrupt
+ unsigned int toe_q57_full : 1; // bit 57 TOE Queue 57 Full Interrupt
+ unsigned int toe_q58_full : 1; // bit 58 TOE Queue 58 Full Interrupt
+ unsigned int toe_q59_full : 1; // bit 59 TOE Queue 59 Full Interrupt
+ unsigned int toe_q60_full : 1; // bit 60 TOE Queue 60 Full Interrupt
+ unsigned int toe_q61_full : 1; // bit 61 TOE Queue 61 Full Interrupt
+ unsigned int toe_q62_full : 1; // bit 62 TOE Queue 62 Full Interrupt
+ unsigned int toe_q63_full : 1; // bit 63 TOE Queue 63 Full Interrupt
+ } bits;
+} INTR_REG3_T;
+
+#define TOE_QH_FULL_INT_BIT(x) BIT(x-32)
+
+/*
+ * Interrupt Status Register 4 (offset 0x0060)
+ * Interrupt Mask Register 4 (offset 0x0064)
+ * Interrupt Select Register 4 (offset 0x0068)
+ */
+typedef union {
+ unsigned char byte;
+ struct bit_0060 {
+ unsigned char status_changed : 1; // Status Changed Intr for RGMII Mode
+ unsigned char rx_overrun : 1; // GMAC Rx FIFO overrun interrupt
+ unsigned char tx_pause_off : 1; // received pause off frame interrupt
+ unsigned char rx_pause_off : 1; // received pause off frame interrupt
+ unsigned char tx_pause_on : 1; // transmit pause on frame interrupt
+ unsigned char rx_pause_on : 1; // received pause on frame interrupt
+ unsigned char cnt_full : 1; // MIB counters half full interrupt
+ unsigned char reserved : 1; //
+ } __packed bits;
+} __packed GMAC_INTR_T;
+
+typedef union {
+ unsigned int bits32;
+ struct bit_0060_2 {
+ unsigned int swfq_empty : 1; // bit 0 Software Free Queue Empty Intr.
+ unsigned int hwfq_empty : 1; // bit 1 Hardware Free Queue Empty Intr.
+ unsigned int class_qf_int : 14; // bit 15:2 Classification Rx Queue13-0 Full Intr.
+ GMAC_INTR_T gmac0;
+ GMAC_INTR_T gmac1;
+ } bits;
+} INTR_REG4_T;
+
+#define GMAC1_RESERVED_INT_BIT BIT(31)
+#define GMAC1_MIB_INT_BIT BIT(30)
+#define GMAC1_RX_PAUSE_ON_INT_BIT BIT(29)
+#define GMAC1_TX_PAUSE_ON_INT_BIT BIT(28)
+#define GMAC1_RX_PAUSE_OFF_INT_BIT BIT(27)
+#define GMAC1_TX_PAUSE_OFF_INT_BIT BIT(26)
+#define GMAC1_RX_OVERRUN_INT_BIT BIT(25)
+#define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
+#define GMAC0_RESERVED_INT_BIT BIT(23)
+#define GMAC0_MIB_INT_BIT BIT(22)
+#define GMAC0_RX_PAUSE_ON_INT_BIT BIT(21)
+#define GMAC0_TX_PAUSE_ON_INT_BIT BIT(20)
+#define GMAC0_RX_PAUSE_OFF_INT_BIT BIT(19)
+#define GMAC0_TX_PAUSE_OFF_INT_BIT BIT(18)
+#define GMAC0_RX_OVERRUN_INT_BIT BIT(17)
+#define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
+#define CLASS_RX_FULL_INT_BIT(x) BIT((x+2))
+#define HWFQ_EMPTY_INT_BIT BIT(1)
+#define SWFQ_EMPTY_INT_BIT BIT(0)
+
+#define GMAC0_INT_BITS (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
+ GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT | \
+ GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT | \
+ GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
+#define GMAC1_INT_BITS (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
+ GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT | \
+ GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT | \
+ GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
+
+#define CLASS_RX_FULL_INT_BITS 0xfffc
+
+/*
+ * GLOBAL_QUEUE_THRESHOLD_REG (offset 0x0070)
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_0070_2 {
+ unsigned int swfq_empty : 8; // 7:0 Software Free Queue Empty Threshold
+ unsigned int hwfq_empty : 8; // 15:8 Hardware Free Queue Empty Threshold
+ unsigned int intrq : 8; // 23:16
+ unsigned int toe_class : 8; // 31:24
+ } bits;
+} QUEUE_THRESHOLD_T;
+
+
+/*
+ * GMAC DMA Control Register
+ * GMAC0 offset 0x8000
+ * GMAC1 offset 0xC000
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8000 {
+ unsigned int td_bus : 2; // bit 1:0 Peripheral Bus Width
+ unsigned int td_burst_size : 2; // bit 3:2 TxDMA max burst size for every AHB request
+ unsigned int td_prot : 4; // bit 7:4 TxDMA protection control
+ unsigned int rd_bus : 2; // bit 9:8 Peripheral Bus Width
+ unsigned int rd_burst_size : 2; // bit 11:10 DMA max burst size for every AHB request
+ unsigned int rd_prot : 4; // bit 15:12 DMA Protection Control
+ unsigned int rd_insert_bytes : 2; // bit 17:16
+ unsigned int reserved : 10; // bit 27:18
+ unsigned int drop_small_ack : 1; // bit 28 1: Drop, 0: Accept
+ unsigned int loopback : 1; // bit 29 Loopback TxDMA to RxDMA
+ unsigned int td_enable : 1; // bit 30 Tx DMA Enable
+ unsigned int rd_enable : 1; // bit 31 Rx DMA Enable
+ } bits;
+} GMAC_DMA_CTRL_T;
+
+/*
+ * GMAC Tx Weighting Control Register 0
+ * GMAC0 offset 0x8004
+ * GMAC1 offset 0xC004
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8004 {
+ unsigned int hw_tq0 : 6; // bit 5:0 HW TX Queue 3
+ unsigned int hw_tq1 : 6; // bit 11:6 HW TX Queue 2
+ unsigned int hw_tq2 : 6; // bit 17:12 HW TX Queue 1
+ unsigned int hw_tq3 : 6; // bit 23:18 HW TX Queue 0
+ unsigned int reserved : 8; // bit 31:24
+ } bits;
+} GMAC_TX_WCR0_T; /* Weighting Control Register 0 */
+
+/*
+ * GMAC Tx Weighting Control Register 1
+ * GMAC0 offset 0x8008
+ * GMAC1 offset 0xC008
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8008 {
+ unsigned int sw_tq0 : 5; // bit 4:0 SW TX Queue 0
+ unsigned int sw_tq1 : 5; // bit 9:5 SW TX Queue 1
+ unsigned int sw_tq2 : 5; // bit 14:10 SW TX Queue 2
+ unsigned int sw_tq3 : 5; // bit 19:15 SW TX Queue 3
+ unsigned int sw_tq4 : 5; // bit 24:20 SW TX Queue 4
+ unsigned int sw_tq5 : 5; // bit 29:25 SW TX Queue 5
+ unsigned int reserved : 2; // bit 31:30
+ } bits;
+} GMAC_TX_WCR1_T; /* Weighting Control Register 1 */
+
+/*
+ * Queue Read/Write Pointer
+ * GMAC SW TX Queue 0~5 Read/Write Pointer register
+ * GMAC0 offset 0x800C ~ 0x8020
+ * GMAC1 offset 0xC00C ~ 0xC020
+ * GMAC HW TX Queue 0~3 Read/Write Pointer register
+ * GMAC0 offset 0x8024 ~ 0x8030
+ * GMAC1 offset 0xC024 ~ 0xC030
+ *
+ * see DMA_RWPTR_T structure
+ */
+
+/*
+ * GMAC DMA Tx First Description Address Register
+ * GMAC0 offset 0x8038
+ * GMAC1 offset 0xC038
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8038 {
+ unsigned int reserved : 3;
+ unsigned int td_busy : 1; // bit 3 1: TxDMA busy; 0: TxDMA idle
+ unsigned int td_first_des_ptr : 28; // bit 31:4 first descriptor address
+ } bits;
+} GMAC_TXDMA_FIRST_DESC_T;
+
+/*
+ * GMAC DMA Tx Current Description Address Register
+ * GMAC0 offset 0x803C
+ * GMAC1 offset 0xC03C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_803C {
+ unsigned int reserved : 4;
+ unsigned int td_curr_desc_ptr : 28; // bit 31:4 current descriptor address
+ } bits;
+} GMAC_TXDMA_CURR_DESC_T;
+
+/*
+ * GMAC DMA Tx Description Word 0 Register
+ * GMAC0 offset 0x8040
+ * GMAC1 offset 0xC040
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8040 {
+ unsigned int buffer_size : 16; // bit 15:0 Transfer size
+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
+ unsigned int status_tx_ok : 1; // bit 22 Tx Status, 1: Successful 0: Failed
+ unsigned int status_rvd : 6; // bit 28:23 Tx Status, Reserved bits
+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
+ unsigned int reserved : 1; // bit 31
+ } bits;
+} GMAC_TXDESC_0_T;
+
+/*
+ * GMAC DMA Tx Description Word 1 Register
+ * GMAC0 offset 0x8044
+ * GMAC1 offset 0xC044
+ */
+typedef union {
+ unsigned int bits32;
+ struct txdesc_word1 {
+ unsigned int byte_count : 16; // bit 15: 0 Tx Frame Byte Count
+ unsigned int mtu_enable : 1; // bit 16 TSS segmentation use MTU setting
+ unsigned int ip_chksum : 1; // bit 17 IPV4 Header Checksum Enable
+ unsigned int ipv6_enable : 1; // bit 18 IPV6 Tx Enable
+ unsigned int tcp_chksum : 1; // bit 19 TCP Checksum Enable
+ unsigned int udp_chksum : 1; // bit 20 UDP Checksum Enable
+ unsigned int bypass_tss : 1; // bit 21
+ unsigned int ip_fixed_len : 1; // bit 22
+ unsigned int reserved : 9; // bit 31:23 Tx Flag, Reserved
+ } bits;
+} GMAC_TXDESC_1_T;
+
+#define TSS_IP_FIXED_LEN_BIT BIT(22)
+#define TSS_BYPASS_BIT BIT(21)
+#define TSS_UDP_CHKSUM_BIT BIT(20)
+#define TSS_TCP_CHKSUM_BIT BIT(19)
+#define TSS_IPV6_ENABLE_BIT BIT(18)
+#define TSS_IP_CHKSUM_BIT BIT(17)
+#define TSS_MTU_ENABLE_BIT BIT(16)
+
+#define TSS_CHECKUM_ENABLE \
+ (TSS_IP_CHKSUM_BIT|TSS_IPV6_ENABLE_BIT| \
+ TSS_TCP_CHKSUM_BIT|TSS_UDP_CHKSUM_BIT)
+
+/*
+ * GMAC DMA Tx Description Word 2 Register
+ * GMAC0 offset 0x8048
+ * GMAC1 offset 0xC048
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int buf_adr;
+} GMAC_TXDESC_2_T;
+
+/*
+ * GMAC DMA Tx Description Word 3 Register
+ * GMAC0 offset 0x804C
+ * GMAC1 offset 0xC04C
+ */
+typedef union {
+ unsigned int bits32;
+ struct txdesc_word3 {
+ unsigned int mtu_size : 11; // bit 10: 0 Tx Frame Byte Count
+ unsigned int reserved : 18; // bit 28:11
+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
+ } bits;
+} GMAC_TXDESC_3_T;
+#define SOF_EOF_BIT_MASK 0x3fffffff
+#define SOF_BIT 0x80000000
+#define EOF_BIT 0x40000000
+#define EOFIE_BIT BIT(29)
+#define MTU_SIZE_BIT_MASK 0x7ff
+
+/*
+ * GMAC Tx Descriptor
+ */
+typedef struct {
+ GMAC_TXDESC_0_T word0;
+ GMAC_TXDESC_1_T word1;
+ GMAC_TXDESC_2_T word2;
+ GMAC_TXDESC_3_T word3;
+} GMAC_TXDESC_T;
+
+/*
+ * GMAC DMA Rx First Description Address Register
+ * GMAC0 offset 0x8058
+ * GMAC1 offset 0xC058
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8058 {
+ unsigned int reserved : 3; // bit 2:0
+ unsigned int rd_busy : 1; // bit 3 1-RxDMA busy; 0-RxDMA idle
+ unsigned int rd_first_des_ptr : 28; // bit 31:4 first descriptor address
+ } bits;
+} GMAC_RXDMA_FIRST_DESC_T;
+
+/*
+ * GMAC DMA Rx Current Description Address Register
+ * GMAC0 offset 0x805C
+ * GMAC1 offset 0xC05C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_805C {
+ unsigned int reserved : 4; // bit 3:0
+ unsigned int rd_curr_des_ptr : 28; // bit 31:4 current descriptor address
+ } bits;
+} GMAC_RXDMA_CURR_DESC_T;
+
+/*
+ * GMAC DMA Rx Description Word 0 Register
+ * GMAC0 offset 0x8060
+ * GMAC1 offset 0xC060
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8060 {
+ unsigned int buffer_size : 16; // bit 15:0 number of descriptors used for the current frame
+ unsigned int desc_count : 6; // bit 21:16 number of descriptors used for the current frame
+ unsigned int status : 4; // bit 24:22 Status of rx frame
+ unsigned int chksum_status : 3; // bit 28:26 Check Sum Status
+ unsigned int perr : 1; // bit 29 protocol error during processing this descriptor
+ unsigned int derr : 1; // bit 30 data error during processing this descriptor
+ unsigned int drop : 1; // bit 31 TOE/CIS Queue Full dropped packet to default queue
+ } bits;
+} GMAC_RXDESC_0_T;
+
+#define GMAC_RXDESC_0_T_derr BIT(30)
+#define GMAC_RXDESC_0_T_perr BIT(29)
+#define GMAC_RXDESC_0_T_chksum_status(x) BIT((x+26))
+#define GMAC_RXDESC_0_T_status(x) BIT((x+22))
+#define GMAC_RXDESC_0_T_desc_count(x) BIT((x+16))
+
+#define RX_CHKSUM_IP_UDP_TCP_OK 0
+#define RX_CHKSUM_IP_OK_ONLY 1
+#define RX_CHKSUM_NONE 2
+#define RX_CHKSUM_IP_ERR_UNKNOWN 4
+#define RX_CHKSUM_IP_ERR 5
+#define RX_CHKSUM_TCP_UDP_ERR 6
+#define RX_CHKSUM_NUM 8
+
+#define RX_STATUS_GOOD_FRAME 0
+#define RX_STATUS_TOO_LONG_GOOD_CRC 1
+#define RX_STATUS_RUNT_FRAME 2
+#define RX_STATUS_SFD_NOT_FOUND 3
+#define RX_STATUS_CRC_ERROR 4
+#define RX_STATUS_TOO_LONG_BAD_CRC 5
+#define RX_STATUS_ALIGNMENT_ERROR 6
+#define RX_STATUS_TOO_LONG_BAD_ALIGN 7
+#define RX_STATUS_RX_ERR 8
+#define RX_STATUS_DA_FILTERED 9
+#define RX_STATUS_BUFFER_FULL 10
+#define RX_STATUS_NUM 16
+
+#define RX_ERROR_LENGTH(s) \
+ ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
+ (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
+ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
+#define RX_ERROR_OVER(s) \
+ ((s) == RX_STATUS_BUFFER_FULL)
+#define RX_ERROR_CRC(s) \
+ ((s) == RX_STATUS_CRC_ERROR || \
+ (s) == RX_STATUS_TOO_LONG_BAD_CRC)
+#define RX_ERROR_FRAME(s) \
+ ((s) == RX_STATUS_ALIGNMENT_ERROR || \
+ (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
+#define RX_ERROR_FIFO(s) \
+ (0)
+
+/*
+ * GMAC DMA Rx Description Word 1 Register
+ * GMAC0 offset 0x8064
+ * GMAC1 offset 0xC064
+ */
+typedef union {
+ unsigned int bits32;
+ struct rxdesc_word1 {
+ unsigned int byte_count : 16; // bit 15: 0 Rx Frame Byte Count
+ unsigned int sw_id : 16; // bit 31:16 Software ID
+ } bits;
+} GMAC_RXDESC_1_T;
+
+/*
+ * GMAC DMA Rx Description Word 2 Register
+ * GMAC0 offset 0x8068
+ * GMAC1 offset 0xC068
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int buf_adr;
+} GMAC_RXDESC_2_T;
+
+#define RX_INSERT_NONE 0
+#define RX_INSERT_1_BYTE 1
+#define RX_INSERT_2_BYTE 2
+#define RX_INSERT_3_BYTE 3
+
+/*
+ * GMAC DMA Rx Description Word 3 Register
+ * GMAC0 offset 0x806C
+ * GMAC1 offset 0xC06C
+ */
+typedef union {
+ unsigned int bits32;
+ struct rxdesc_word3 {
+ unsigned int l3_offset : 8; // bit 7: 0 L3 data offset
+ unsigned int l4_offset : 8; // bit 15: 8 L4 data offset
+ unsigned int l7_offset : 8; // bit 23: 16 L7 data offset
+ unsigned int dup_ack : 1; // bit 24 Duplicated ACK detected
+ unsigned int abnormal : 1; // bit 25 abnormal case found
+ unsigned int option : 1; // bit 26 IPV4 option or IPV6 extension header
+ unsigned int out_of_seq : 1; // bit 27 Out of Sequence packet
+ unsigned int ctrl_flag : 1; // bit 28 Control Flag is present
+ unsigned int eofie : 1; // bit 29 End of frame interrupt enable
+ unsigned int sof_eof : 2; // bit 31:30 11: only one, 10: first, 01: last, 00: linking
+ } bits;
+} GMAC_RXDESC_3_T;
+
+/*
+ * GMAC Rx Descriptor
+ */
+typedef struct {
+ GMAC_RXDESC_0_T word0;
+ GMAC_RXDESC_1_T word1;
+ GMAC_RXDESC_2_T word2;
+ GMAC_RXDESC_3_T word3;
+} GMAC_RXDESC_T;
+
+/*
+ * GMAC Hash Engine Enable/Action Register 0 Offset Register
+ * GMAC0 offset 0x8070
+ * GMAC1 offset 0xC070
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8070 {
+ unsigned int mr0hel : 6; // bit 5:0 match rule 0 hash entry size
+ unsigned int mr0_action : 5; // bit 10:6 Matching Rule 0 action offset
+ unsigned int reserved0 : 4; // bit 14:11
+ unsigned int mr0en : 1; // bit 15 Enable Matching Rule 0
+ unsigned int mr1hel : 6; // bit 21:16 match rule 1 hash entry size
+ unsigned int mr1_action : 5; // bit 26:22 Matching Rule 1 action offset
+ unsigned int timing : 3; // bit 29:27
+ unsigned int reserved1 : 1; // bit 30
+ unsigned int mr1en : 1; // bit 31 Enable Matching Rule 1
+ } bits;
+} GMAC_HASH_ENABLE_REG0_T;
+
+/*
+ * GMAC Hash Engine Enable/Action Register 1 Offset Register
+ * GMAC0 offset 0x8074
+ * GMAC1 offset 0xC074
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8074 {
+ unsigned int mr2hel : 6; // bit 5:0 match rule 2 hash entry size
+ unsigned int mr2_action : 5; // bit 10:6 Matching Rule 2 action offset
+ unsigned int reserved2 : 4; // bit 14:11
+ unsigned int mr2en : 1; // bit 15 Enable Matching Rule 2
+ unsigned int mr3hel : 6; // bit 21:16 match rule 3 hash entry size
+ unsigned int mr3_action : 5; // bit 26:22 Matching Rule 3 action offset
+ unsigned int reserved1 : 4; // bit 30:27
+ unsigned int mr3en : 1; // bit 31 Enable Matching Rule 3
+ } bits;
+} GMAC_HASH_ENABLE_REG1_T;
+
+/*
+ * GMAC Matching Rule Control Register 0
+ * GMAC0 offset 0x8078
+ * GMAC1 offset 0xC078
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8078 {
+ unsigned int sprx : 8; // bit 7:0 Support Protocol Register 7:0
+ unsigned int reserved2 : 4; // bit 11:8
+ unsigned int tos_traffic : 1; // bit 12 IPV4 TOS or IPV6 Traffice Class
+ unsigned int flow_lable : 1; // bit 13 IPV6 Flow label
+ unsigned int ip_hdr_len : 1; // bit 14 IPV4 Header length
+ unsigned int ip_version : 1; // bit 15 0: IPV4, 1: IPV6
+ unsigned int reserved1 : 3; // bit 18:16
+ unsigned int pppoe : 1; // bit 19 PPPoE Session ID enable
+ unsigned int vlan : 1; // bit 20 VLAN ID enable
+ unsigned int ether_type : 1; // bit 21 Ethernet type enable
+ unsigned int sa : 1; // bit 22 MAC SA enable
+ unsigned int da : 1; // bit 23 MAC DA enable
+ unsigned int priority : 3; // bit 26:24 priority if multi-rules matched
+ unsigned int port : 1; // bit 27 PORT ID matching enable
+ unsigned int l7 : 1; // bit 28 L7 matching enable
+ unsigned int l4 : 1; // bit 29 L4 matching enable
+ unsigned int l3 : 1; // bit 30 L3 matching enable
+ unsigned int l2 : 1; // bit 31 L2 matching enable
+ } bits;
+} GMAC_MRxCR0_T;
+
+#define MR_L2_BIT BIT(31)
+#define MR_L3_BIT BIT(30)
+#define MR_L4_BIT BIT(29)
+#define MR_L7_BIT BIT(28)
+#define MR_PORT_BIT BIT(27)
+#define MR_PRIORITY_BIT BIT(26)
+#define MR_DA_BIT BIT(23)
+#define MR_SA_BIT BIT(22)
+#define MR_ETHER_TYPE_BIT BIT(21)
+#define MR_VLAN_BIT BIT(20)
+#define MR_PPPOE_BIT BIT(19)
+#define MR_IP_VER_BIT BIT(15)
+#define MR_IP_HDR_LEN_BIT BIT(14)
+#define MR_FLOW_LABLE_BIT BIT(13)
+#define MR_TOS_TRAFFIC_BIT BIT(12)
+#define MR_SPR_BIT(x) BIT(x)
+#define MR_SPR_BITS 0xff
+
+/*
+ * GMAC Matching Rule Control Register 1
+ * GMAC0 offset 0x807C
+ * GMAC1 offset 0xC07C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_807C {
+ unsigned int l4_byte0_15 : 16; // bit 15: 0
+ unsigned int dip_netmask : 7; // bit 22:16 Dest IP net mask, number of mask bits
+ unsigned int dip : 1; // bit 23 Dest IP
+ unsigned int sip_netmask : 7; // bit 30:24 Srce IP net mask, number of mask bits
+ unsigned int sip : 1; // bit 31 Srce IP
+ } bits;
+} GMAC_MRxCR1_T;
+
+/*
+ * GMAC Matching Rule Control Register 2
+ * GMAC0 offset 0x8080
+ * GMAC1 offset 0xC080
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_8080 {
+ unsigned int l7_byte0_23 : 24; // bit 23:0
+ unsigned int l4_byte16_24 : 8; // bit 31: 24
+ } bits;
+} GMAC_MRxCR2_T;
+
+/*
+ * GMAC Support registers
+ * GMAC0 offset 0x80A8
+ * GMAC1 offset 0xC0A8
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_80A8 {
+ unsigned int protocol : 8; // bit 7:0 Supported protocol
+ unsigned int swap : 3; // bit 10:8 Swap
+ unsigned int reserved : 21; // bit 31:11
+ } bits;
+} GMAC_SPR_T;
+
+/*
+ * GMAC_AHB_WEIGHT registers
+ * GMAC0 offset 0x80C8
+ * GMAC1 offset 0xC0C8
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_80C8 {
+ unsigned int hash_weight : 5; // 4:0
+ unsigned int rx_weight : 5; // 9:5
+ unsigned int tx_weight : 5; // 14:10
+ unsigned int pre_req : 5; // 19:15 Rx Data Pre Request FIFO Threshold
+ unsigned int tqDV_threshold : 5; // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
+ unsigned int reserved : 7; // 31:25
+ } bits;
+} GMAC_AHB_WEIGHT_T;
+
+/*
+ * the register structure of GMAC
+ */
+
+/*
+ * GMAC RX FLTR
+ * GMAC0 Offset 0xA00C
+ * GMAC1 Offset 0xE00C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_000c {
+ unsigned int unicast : 1; /* enable receive of unicast frames that are sent to STA address */
+ unsigned int multicast : 1; /* enable receive of multicast frames that pass multicast filter */
+ unsigned int broadcast : 1; /* enable receive of broadcast frames */
+ unsigned int promiscuous : 1; /* enable receive of all frames */
+ unsigned int error : 1; /* enable receive of all error frames */
+ unsigned int : 27;
+ } bits;
+} GMAC_RX_FLTR_T;
+
+/*
+ * GMAC Configuration 0
+ * GMAC0 Offset 0xA018
+ * GMAC1 Offset 0xE018
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_0018 {
+ unsigned int dis_tx : 1; /* 0: disable transmit */
+ unsigned int dis_rx : 1; /* 1: disable receive */
+ unsigned int loop_back : 1; /* 2: transmit data loopback enable */
+ unsigned int flow_ctrl : 1; /* 3: flow control also trigged by Rx queues */
+ unsigned int adj_ifg : 4; /* 4-7: adjust IFG from 96+/-56 */
+ unsigned int max_len : 3; /* 8-10 maximum receive frame length allowed */
+ unsigned int dis_bkoff : 1; /* 11: disable back-off function */
+ unsigned int dis_col : 1; /* 12: disable 16 collisions abort function */
+ unsigned int sim_test : 1; /* 13: speed up timers in simulation */
+ unsigned int rx_fc_en : 1; /* 14: RX flow control enable */
+ unsigned int tx_fc_en : 1; /* 15: TX flow control enable */
+ unsigned int rgmii_en : 1; /* 16: RGMII in-band status enable */
+ unsigned int ipv4_rx_chksum : 1; /* 17: IPv4 RX Checksum enable */
+ unsigned int ipv6_rx_chksum : 1; /* 18: IPv6 RX Checksum enable */
+ unsigned int rx_tag_remove : 1; /* 19: Remove Rx VLAN tag */
+ unsigned int rgmm_edge : 1; // 20
+ unsigned int rxc_inv : 1; // 21
+ unsigned int ipv6_exthdr_order : 1; // 22
+ unsigned int rx_err_detect : 1; // 23
+ unsigned int port0_chk_hwq : 1; // 24
+ unsigned int port1_chk_hwq : 1; // 25
+ unsigned int port0_chk_toeq : 1; // 26
+ unsigned int port1_chk_toeq : 1; // 27
+ unsigned int port0_chk_classq : 1; // 28
+ unsigned int port1_chk_classq : 1; // 29
+ unsigned int reserved : 2; // 31
+ } bits;
+} GMAC_CONFIG0_T;
+
+#define CONFIG0_TX_RX_DISABLE (BIT(1)|BIT(0))
+#define CONFIG0_RX_CHKSUM (BIT(18)|BIT(17))
+#define CONFIG0_FLOW_RX (BIT(14))
+#define CONFIG0_FLOW_TX (BIT(15))
+#define CONFIG0_FLOW_TX_RX (BIT(14)|BIT(15))
+#define CONFIG0_FLOW_CTL (BIT(14)|BIT(15))
+
+/*
+ * GMAC Configuration 1
+ * GMAC0 Offset 0xA01C
+ * GMAC1 Offset 0xE01C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_001c {
+ unsigned int set_threshold : 8; /* flow control set threshold */
+ unsigned int rel_threshold : 8; /* flow control release threshold */
+ unsigned int reserved : 16;
+ } bits;
+} GMAC_CONFIG1_T;
+
+#define GMAC_FLOWCTRL_SET_MAX 32
+#define GMAC_FLOWCTRL_SET_MIN 0
+#define GMAC_FLOWCTRL_RELEASE_MAX 32
+#define GMAC_FLOWCTRL_RELEASE_MIN 0
+
+/*
+ * GMAC Configuration 2
+ * GMAC0 Offset 0xA020
+ * GMAC1 Offset 0xE020
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_0020 {
+ unsigned int set_threshold : 16; /* flow control set threshold */
+ unsigned int rel_threshold : 16; /* flow control release threshold */
+ } bits;
+} GMAC_CONFIG2_T;
+
+/*
+ * GMAC Configuration 3
+ * GMAC0 Offset 0xA024
+ * GMAC1 Offset 0xE024
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_0024 {
+ unsigned int set_threshold : 16; /* flow control set threshold */
+ unsigned int rel_threshold : 16; /* flow control release threshold */
+ } bits;
+} GMAC_CONFIG3_T;
+
+
+/*
+ * GMAC STATUS
+ * GMAC0 Offset 0xA02C
+ * GMAC1 Offset 0xE02C
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit1_002c {
+ unsigned int link : 1; /* link status */
+ unsigned int speed : 2; /* link speed(00->2.5M 01->25M 10->125M) */
+ unsigned int duplex : 1; /* duplex mode */
+ unsigned int reserved : 1;
+ unsigned int mii_rmii : 2; /* PHY interface type */
+ unsigned int : 25;
+ } bits;
+} GMAC_STATUS_T;
+
+#define GMAC_SPEED_10 0
+#define GMAC_SPEED_100 1
+#define GMAC_SPEED_1000 2
+
+#define GMAC_PHY_MII 0
+#define GMAC_PHY_GMII 1
+#define GMAC_PHY_RGMII_100_10 2
+#define GMAC_PHY_RGMII_1000 3
+
+/*
+ * Queue Header
+ * (1) TOE Queue Header
+ * (2) Non-TOE Queue Header
+ * (3) Interrupt Queue Header
+ *
+ * memory Layout
+ * TOE Queue Header
+ * 0x60003000 +---------------------------+ 0x0000
+ * | TOE Queue 0 Header |
+ * | 8 * 4 Bytes |
+ * +---------------------------+ 0x0020
+ * | TOE Queue 1 Header |
+ * | 8 * 4 Bytes |
+ * +---------------------------+ 0x0040
+ * | ...... |
+ * | |
+ * +---------------------------+
+ *
+ * Non TOE Queue Header
+ * 0x60002000 +---------------------------+ 0x0000
+ * | Default Queue 0 Header |
+ * | 2 * 4 Bytes |
+ * +---------------------------+ 0x0008
+ * | Default Queue 1 Header |
+ * | 2 * 4 Bytes |
+ * +---------------------------+ 0x0010
+ * | Classification Queue 0 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+
+ * | Classification Queue 1 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+ (n * 8 + 0x10)
+ * | ... |
+ * | 2 * 4 Bytes |
+ * +---------------------------+ (13 * 8 + 0x10)
+ * | Classification Queue 13 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+ 0x80
+ * | Interrupt Queue 0 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+
+ * | Interrupt Queue 1 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+
+ * | Interrupt Queue 2 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+
+ * | Interrupt Queue 3 |
+ * | 2 * 4 Bytes |
+ * +---------------------------+
+ *
+ */
+#define TOE_QUEUE_HDR_ADDR(n) (TOE_TOE_QUE_HDR_BASE + n * 32)
+#define TOE_Q_HDR_AREA_END (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
+#define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
+#define TOE_CLASS_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x10)
+#define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
+#define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
+#define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
+/*
+ * TOE Queue Header Word 0
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int base_size;
+} TOE_QHDR0_T;
+
+#define TOE_QHDR0_BASE_MASK (~0x0f)
+
+/*
+ * TOE Queue Header Word 1
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_qhdr1 {
+ unsigned int rptr : 16; // bit 15:0
+ unsigned int wptr : 16; // bit 31:16
+ } bits;
+} TOE_QHDR1_T;
+
+/*
+ * TOE Queue Header Word 2
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_qhdr2 {
+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
+ unsigned int reserved : 7; // bit 23:17
+ unsigned int dack : 1; // bit 24 1: Duplicated ACK
+ unsigned int abn : 1; // bit 25 1: Abnormal case Found
+ unsigned int tcp_opt : 1; // bit 26 1: Have TCP option
+ unsigned int ip_opt : 1; // bit 27 1: have IPV4 option or IPV6 Extension header
+ unsigned int sat : 1; // bit 28 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
+ unsigned int osq : 1; // bit 29 1: out of sequence
+ unsigned int ctl : 1; // bit 30 1: have control flag bits (except ack)
+ unsigned int usd : 1; // bit 31 0: if no data assembled yet
+ } bits;
+} TOE_QHDR2_T;
+
+/*
+ * TOE Queue Header Word 3
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int seq_num;
+} TOE_QHDR3_T;
+
+/*
+ * TOE Queue Header Word 4
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int ack_num;
+} TOE_QHDR4_T;
+
+/*
+ * TOE Queue Header Word 5
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_qhdr5 {
+ unsigned int AckCnt : 16; // bit 15:0
+ unsigned int SeqCnt : 16; // bit 31:16
+ } bits;
+} TOE_QHDR5_T;
+
+/*
+ * TOE Queue Header Word 6
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_qhdr6 {
+ unsigned int WinSize : 16; // bit 15:0
+ unsigned int iq_num : 2; // bit 17:16
+ unsigned int MaxPktSize : 14; // bit 31:18
+ } bits;
+} TOE_QHDR6_T;
+
+/*
+ * TOE Queue Header Word 7
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_qhdr7 {
+ unsigned int AckThreshold : 16; // bit 15:0
+ unsigned int SeqThreshold : 16; // bit 31:16
+ } bits;
+} TOE_QHDR7_T;
+
+/*
+ * TOE Queue Header
+ */
+typedef struct {
+ TOE_QHDR0_T word0;
+ TOE_QHDR1_T word1;
+ TOE_QHDR2_T word2;
+ TOE_QHDR3_T word3;
+ TOE_QHDR4_T word4;
+ TOE_QHDR5_T word5;
+ TOE_QHDR6_T word6;
+ TOE_QHDR7_T word7;
+} TOE_QHDR_T;
+
+/*
+ * NONTOE Queue Header Word 0
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int base_size;
+} NONTOE_QHDR0_T;
+
+#define NONTOE_QHDR0_BASE_MASK (~0x0f)
+
+/*
+ * NONTOE Queue Header Word 1
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_nonqhdr1 {
+ unsigned int rptr : 16; // bit 15:0
+ unsigned int wptr : 16; // bit 31:16
+ } bits;
+} NONTOE_QHDR1_T;
+
+/*
+ * Non-TOE Queue Header
+ */
+typedef struct {
+ NONTOE_QHDR0_T word0;
+ NONTOE_QHDR1_T word1;
+} NONTOE_QHDR_T;
+
+/*
+ * Interrupt Queue Header Word 0
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_intrqhdr0 {
+ unsigned int win_size : 16; // bit 15:0 Descriptor Ring Size
+ unsigned int wptr : 16; // bit 31:16 Write Pointer where hw stopped
+ } bits;
+} INTR_QHDR0_T;
+
+/*
+ * Interrupt Queue Header Word 1
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_intrqhdr1 {
+ unsigned int TotalPktSize : 17; // bit 16: 0 Total packet size
+ unsigned int tcp_qid : 8; // bit 24:17 TCP Queue ID
+ unsigned int dack : 1; // bit 25 1: Duplicated ACK
+ unsigned int abn : 1; // bit 26 1: Abnormal case Found
+ unsigned int tcp_opt : 1; // bit 27 1: Have TCP option
+ unsigned int ip_opt : 1; // bit 28 1: have IPV4 option or IPV6 Extension header
+ unsigned int sat : 1; // bit 29 1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
+ unsigned int osq : 1; // bit 30 1: out of sequence
+ unsigned int ctl : 1; // bit 31 1: have control flag bits (except ack)
+ } bits;
+} INTR_QHDR1_T;
+
+/*
+ * Interrupt Queue Header Word 2
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int seq_num;
+} INTR_QHDR2_T;
+
+/*
+ * Interrupt Queue Header Word 3
+ */
+typedef union {
+ unsigned int bits32;
+ unsigned int ack_num;
+} INTR_QHDR3_T;
+
+/*
+ * Interrupt Queue Header Word 4
+ */
+typedef union {
+ unsigned int bits32;
+ struct bit_intrqhdr4 {
+ unsigned int AckCnt : 16; // bit 15:0 Ack# change since last ack# intr.
+ unsigned int SeqCnt : 16; // bit 31:16 Seq# change since last seq# intr.
+ } bits;
+} INTR_QHDR4_T;
+
+/*
+ * Interrupt Queue Header
+ */
+typedef struct {
+ INTR_QHDR0_T word0;
+ INTR_QHDR1_T word1;
+ INTR_QHDR2_T word2;
+ INTR_QHDR3_T word3;
+ INTR_QHDR4_T word4;
+ unsigned int word5;
+ unsigned int word6;
+ unsigned int word7;
+} INTR_QHDR_T;
+
+#endif /* _GMAC_SL351x_H */
--
1.7.1
^ permalink raw reply related
* Re: [PATCH net-next-2.6 v2] can: Topcliff: PCH_CAN driver: Fix build warnings
From: Tomoya @ 2010-10-29 10:37 UTC (permalink / raw)
To: Wolfgang Grandegger, David S. Miller, Wolfram Sang,
Christian Pellegrin, Barry Song
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, Masayuki Ohtake, margie.foster
Hi Wolfgang and Marc,
>>> what does this loop do? why is it nessecarry? I don't like delay loops
>>> in the hot path of a driver.
>> This loop is for waiting for all tx Message Object completion.
>> This is Topcliff CAN HW specification.
> What do you mean with "tx Message Object completion"? Is TX done not
> signaled via interrupt?
Yes Tx done is signaled via interrupt.
On the other hand, register "CANTREQx" also shows the status of Message Object.
Reading the register, CAN driver can know the Message Object is empty or not.
In case of this processing, using this register is better, I think.
> Please explain why you need to wait multiples of
>> 500us here in the hot TX path.
You are right. The value "500us" was too big.
According to Topcliff document, it takes 3~6 cycles for transferring between
register and Message Object RAM.
Since 50MHz is, 1cycle=0.02usec, 6cycle=0.12. May be true.
I will modify 500usec to 1usec.
>>>> All these check if busy in the code make me a bit nervous, can you
>>>> please explain why they are needed. A pointer to the manual is okay, too.
>>> Me too. I already ask in my previous mail how long that functions
>>> usually blocks.
>> When accessing read/write from/to Message RAM,
>> Since it takes much time for transferring between Register and Message RAM,
>Much time means how many mirco-seconds?
ditto
>> SW must check busy flag of CAN register.
>> This is a Topcliff HW specification.
>Maybe the busy check could also be done *before* the Message RAM is
>accessed to avoid (or minimize) waiting.
Yes, *before* is right.
If there is *after* processing, this is a bug.
Can you see anyway ?
> Can you give us a pointer into intel's documentation?
You have already had Intel's data sheet(Topcliff/Atom E6xx series), right ?
What's document for ?
>> If you figured out how to use the endianess conversion functions from
>> the cpu_to_{le,be}-{le,to}_to_cpup family use them here, too.
Sorry, I misunderstood the spec of Topcliff CAN endianess.
I have understood endianess conversion is not necessary.
(CAN data is set as Big-Endian in Topcliff CAN register)
>You have to change the definition of the regs struct a bit:
>> u32 if1_mcont;
>> u32 if1_data[4];
>> u32 reserve2;
Uh, I can't find this. Where is this ?
> BTW: Where can I get this Intel Hardware to improve and test the driver?
We don't know, please contact to Intel,
Topcliff is formally called "Atom E6xx series" http://edc.intel.com/Platforms/Atom-E6xx/
I have completed modifying for your comments excepting above.
Receiving many comments, your indication may be dropped. If you find, please indicate again?.
For your confirming my modification, I show current whole of CAN driver.
--
Thanks, Tomoya(OKI SEMICONDUCTOR CO., LTD.)
--- /dev/null
+++ b/drivers/net/can/pch_can.c
@@ -0,0 +1,1436 @@
+/*
+ * Copyright (C) 1999 - 2010 Intel Corporation.
+ * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/can.h>
+#include <linux/can/dev.h>
+#include <linux/can/error.h>
+
+#define MAX_MSG_OBJ 32
+#define MSG_OBJ_RX 0 /* The receive message object flag. */
+#define MSG_OBJ_TX 1 /* The transmit message object flag. */
+
+#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
+#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
+#define CAN_CTRL_IE_SIE_EIE 0x000e
+#define CAN_CTRL_CCE 0x0040
+#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
+#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
+#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
+#define CAN_CMASK_RX_TX_SET 0x00f3
+#define CAN_CMASK_RX_TX_GET 0x0073
+#define CAN_CMASK_ALL 0xff
+#define CAN_CMASK_RDWR 0x80
+#define CAN_CMASK_ARB 0x20
+#define CAN_CMASK_CTRL 0x10
+#define CAN_CMASK_MASK 0x40
+#define CAN_CMASK_NEWDAT 0x04
+#define CAN_CMASK_CLRINTPND 0x08
+
+#define CAN_IF_MCONT_NEWDAT 0x8000
+#define CAN_IF_MCONT_INTPND 0x2000
+#define CAN_IF_MCONT_UMASK 0x1000
+#define CAN_IF_MCONT_TXIE 0x0800
+#define CAN_IF_MCONT_RXIE 0x0400
+#define CAN_IF_MCONT_RMTEN 0x0200
+#define CAN_IF_MCONT_TXRQXT 0x0100
+#define CAN_IF_MCONT_EOB 0x0080
+#define CAN_IF_MCONT_DLC 0x000f
+#define CAN_IF_MCONT_MSGLOST 0x4000
+#define CAN_MASK2_MDIR_MXTD 0xc000
+#define CAN_ID2_DIR 0x2000
+#define CAN_ID_MSGVAL 0x8000
+
+#define CAN_STATUS_INT 0x8000
+#define CAN_IF_CREQ_BUSY 0x8000
+#define CAN_ID2_XTD 0x4000
+
+#define CAN_REC 0x00007f00
+#define CAN_TEC 0x000000ff
+
+#define PCH_RX_OK 0x00000010
+#define PCH_TX_OK 0x00000008
+#define PCH_BUS_OFF 0x00000080
+#define PCH_EWARN 0x00000040
+#define PCH_EPASSIV 0x00000020
+#define PCH_LEC0 0x00000001
+#define PCH_LEC1 0x00000002
+#define PCH_LEC2 0x00000004
+#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
+#define PCH_STUF_ERR PCH_LEC0
+#define PCH_FORM_ERR PCH_LEC1
+#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
+#define PCH_BIT1_ERR PCH_LEC2
+#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
+#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
+
+/* bit position of certain controller bits. */
+#define BIT_BITT_BRP 0
+#define BIT_BITT_SJW 6
+#define BIT_BITT_TSEG1 8
+#define BIT_BITT_TSEG2 12
+#define BIT_IF1_MCONT_RXIE 10
+#define BIT_IF2_MCONT_TXIE 11
+#define BIT_BRPE_BRPE 6
+#define BIT_ES_TXERRCNT 0
+#define BIT_ES_RXERRCNT 8
+#define MSK_BITT_BRP 0x3f
+#define MSK_BITT_SJW 0xc0
+#define MSK_BITT_TSEG1 0xf00
+#define MSK_BITT_TSEG2 0x7000
+#define MSK_BRPE_BRPE 0x3c0
+#define MSK_BRPE_GET 0x0f
+#define MSK_CTRL_IE_SIE_EIE 0x07
+#define MSK_MCONT_TXIE 0x08
+#define MSK_MCONT_RXIE 0x10
+#define PCH_CAN_NO_TX_BUFF 1
+#define COUNTER_LIMIT 10
+
+#define PCH_CAN_CLK 50000000 /* 50MHz */
+
+/*
+ * Define the number of message object.
+ * PCH CAN communications are done via Message RAM.
+ * The Message RAM consists of 32 message objects.
+ */
+#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
+#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
+#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
+
+#define PCH_FIFO_THRESH 16
+
+enum pch_can_mode {
+ PCH_CAN_ENABLE,
+ PCH_CAN_DISABLE,
+ PCH_CAN_ALL,
+ PCH_CAN_NONE,
+ PCH_CAN_STOP,
+ PCH_CAN_RUN,
+};
+
+struct pch_can_regs {
+ u32 cont;
+ u32 stat;
+ u32 errc;
+ u32 bitt;
+ u32 intr;
+ u32 opt;
+ u32 brpe;
+ u32 reserve1;
+ u32 if1_creq;
+ u32 if1_cmask;
+ u32 if1_mask1;
+ u32 if1_mask2;
+ u32 if1_id1;
+ u32 if1_id2;
+ u32 if1_mcont;
+ u32 if1_dataa1;
+ u32 if1_dataa2;
+ u32 if1_datab1;
+ u32 if1_datab2;
+ u32 reserve2;
+ u32 reserve3[12];
+ u32 if2_creq;
+ u32 if2_cmask;
+ u32 if2_mask1;
+ u32 if2_mask2;
+ u32 if2_id1;
+ u32 if2_id2;
+ u32 if2_mcont;
+ u32 if2_dataa1;
+ u32 if2_dataa2;
+ u32 if2_datab1;
+ u32 if2_datab2;
+ u32 reserve4;
+ u32 reserve5[20];
+ u32 treq1;
+ u32 treq2;
+ u32 reserve6[2];
+ u32 reserve7[56];
+ u32 reserve8[3];
+ u32 srst;
+};
+
+struct pch_can_priv {
+ struct can_priv can;
+ struct pci_dev *dev;
+ unsigned int tx_enable[MAX_MSG_OBJ];
+ unsigned int rx_enable[MAX_MSG_OBJ];
+ unsigned int rx_link[MAX_MSG_OBJ];
+ unsigned int int_enables;
+ unsigned int int_stat;
+ struct net_device *ndev;
+ spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
+ unsigned int msg_obj[MAX_MSG_OBJ];
+ struct pch_can_regs __iomem *regs;
+ struct napi_struct napi;
+ unsigned int tx_obj; /* Point next Tx Obj index */
+ unsigned int use_msi;
+};
+
+static struct can_bittiming_const pch_can_bittiming_const = {
+ .name = "pch_can",
+ .tseg1_min = 1,
+ .tseg1_max = 16,
+ .tseg2_min = 1,
+ .tseg2_max = 8,
+ .sjw_max = 4,
+ .brp_min = 1,
+ .brp_max = 1024, /* 6bit + extended 4bit */
+ .brp_inc = 1,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
+ {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
+ {0,}
+};
+MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
+
+static inline void pch_can_bit_set(u32 *addr, u32 mask)
+{
+ iowrite32(ioread32(addr) | mask, addr);
+}
+
+static inline void pch_can_bit_clear(u32 *addr, u32 mask)
+{
+ iowrite32(ioread32(addr) & ~mask, addr);
+}
+
+static void pch_can_set_run_mode(struct pch_can_priv *priv,
+ enum pch_can_mode mode)
+{
+ switch (mode) {
+ case PCH_CAN_RUN:
+ pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
+ break;
+
+ case PCH_CAN_STOP:
+ pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
+ break;
+
+ default:
+ dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
+ break;
+ }
+}
+
+static void pch_can_set_optmode(struct pch_can_priv *priv)
+{
+ u32 reg_val = ioread32(&priv->regs->opt);
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
+ reg_val |= CAN_OPT_SILENT;
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
+ reg_val |= CAN_OPT_LBACK;
+
+ pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
+ iowrite32(reg_val, &priv->regs->opt);
+}
+
+static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
+{
+ u32 counter = COUNTER_LIMIT;
+ u32 ifx_creq;
+
+ iowrite32(num, creq_addr);
+ while (counter) {
+ ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
+ if (!ifx_creq)
+ break;
+ counter--;
+ udelay(1);
+ }
+ if (!counter)
+ pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
+}
+
+static void pch_can_set_int_enables(struct pch_can_priv *priv,
+ enum pch_can_mode interrupt_no)
+{
+ switch (interrupt_no) {
+ case PCH_CAN_ENABLE:
+ pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
+ break;
+
+ case PCH_CAN_DISABLE:
+ pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
+ break;
+
+ case PCH_CAN_ALL:
+ pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+ break;
+
+ case PCH_CAN_NONE:
+ pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+ break;
+
+ default:
+ dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
+ break;
+ }
+}
+
+static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
+ int set)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ /* Reading the receive buffer data from RAM to Interface1 registers */
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
+
+ /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ &priv->regs->if1_cmask);
+
+ if (set == 1) {
+ /* Setting the MsgVal and RxIE bits */
+ pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
+ pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
+
+ } else if (set == 0) {
+ /* Resetting the MsgVal and RxIE bits */
+ pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
+ pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
+ }
+
+ pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+}
+
+static void pch_can_rx_enable_all(struct pch_can_priv *priv)
+{
+ int i;
+
+ /* Traversing to obtain the object configured as receivers. */
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
+ pch_can_set_rx_enable(priv, i, 1);
+}
+
+static void pch_can_rx_disable_all(struct pch_can_priv *priv)
+{
+ int i;
+
+ /* Traversing to obtain the object configured as receivers. */
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
+ pch_can_set_rx_enable(priv, i, 0);
+}
+
+static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
+ u32 set)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ /* Reading the Msg buffer from Message RAM to Interface2 registers. */
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
+
+ /* Setting the IF2CMASK register for accessing the
+ MsgVal and TxIE bits */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ &priv->regs->if2_cmask);
+
+ if (set == 1) {
+ /* Setting the MsgVal and TxIE bits */
+ pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
+ pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
+ } else if (set == 0) {
+ /* Resetting the MsgVal and TxIE bits. */
+ pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
+ pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
+ }
+
+ pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+}
+
+static void pch_can_tx_enable_all(struct pch_can_priv *priv)
+{
+ int i;
+
+ /* Traversing to obtain the object configured as transmit object. */
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
+ pch_can_set_tx_enable(priv, i, 1);
+}
+
+static void pch_can_tx_disable_all(struct pch_can_priv *priv)
+{
+ int i;
+
+ /* Traversing to obtain the object configured as transmit object. */
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
+ pch_can_set_tx_enable(priv, i, 0);
+}
+
+static int pch_can_int_pending(struct pch_can_priv *priv)
+{
+ return ioread32(&priv->regs->intr) & 0xffff;
+}
+
+static void pch_can_clear_buffers(struct pch_can_priv *priv)
+{
+ int i; /* Msg Obj ID (1~32) */
+
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
+ iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
+ iowrite32(0xffff, &priv->regs->if1_mask1);
+ iowrite32(0xffff, &priv->regs->if1_mask2);
+ iowrite32(0x0, &priv->regs->if1_id1);
+ iowrite32(0x0, &priv->regs->if1_id2);
+ iowrite32(0x0, &priv->regs->if1_mcont);
+ iowrite32(0x0, &priv->regs->if1_dataa1);
+ iowrite32(0x0, &priv->regs->if1_dataa2);
+ iowrite32(0x0, &priv->regs->if1_datab1);
+ iowrite32(0x0, &priv->regs->if1_datab2);
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
+ CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, i);
+ }
+
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
+ iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
+ iowrite32(0xffff, &priv->regs->if2_mask1);
+ iowrite32(0xffff, &priv->regs->if2_mask2);
+ iowrite32(0x0, &priv->regs->if2_id1);
+ iowrite32(0x0, &priv->regs->if2_id2);
+ iowrite32(0x0, &priv->regs->if2_mcont);
+ iowrite32(0x0, &priv->regs->if2_dataa1);
+ iowrite32(0x0, &priv->regs->if2_dataa2);
+ iowrite32(0x0, &priv->regs->if2_datab1);
+ iowrite32(0x0, &priv->regs->if2_datab2);
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
+ CAN_CMASK_CTRL, &priv->regs->if2_cmask);
+ pch_can_check_if_busy(&priv->regs->if2_creq, i);
+ }
+}
+
+static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
+{
+ int i;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, i);
+
+ iowrite32(0x0, &priv->regs->if1_id1);
+ iowrite32(0x0, &priv->regs->if1_id2);
+
+ pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_UMASK);
+
+ /* Set FIFO mode set to 0 except last Rx Obj*/
+ pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
+ /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
+ if (i == (PCH_RX_OBJ_NUM - 1))
+ pch_can_bit_set(&priv->regs->if1_mcont,
+ CAN_IF_MCONT_EOB);
+
+ iowrite32(0, &priv->regs->if1_mask1);
+ pch_can_bit_clear(&priv->regs->if1_mask2,
+ 0x1fff | CAN_MASK2_MDIR_MXTD);
+
+ /* Setting CMASK for writing */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
+ CAN_CMASK_CTRL, &priv->regs->if1_cmask);
+
+ pch_can_check_if_busy(&priv->regs->if1_creq, i);
+ }
+
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ pch_can_check_if_busy(&priv->regs->if2_creq, i);
+
+ /* Resetting DIR bit for reception */
+ iowrite32(0x0, &priv->regs->if2_id1);
+ iowrite32(0x0, &priv->regs->if2_id2);
+ pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
+
+ /* Setting EOB bit for transmitter */
+ iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
+
+ pch_can_bit_set(&priv->regs->if2_mcont,
+ CAN_IF_MCONT_UMASK);
+
+ iowrite32(0, &priv->regs->if2_mask1);
+ pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
+
+ /* Setting CMASK for writing */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
+ CAN_CMASK_CTRL, &priv->regs->if2_cmask);
+
+ pch_can_check_if_busy(&priv->regs->if2_creq, i);
+ }
+
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+}
+
+static void pch_can_init(struct pch_can_priv *priv)
+{
+ /* Stopping the Can device. */
+ pch_can_set_run_mode(priv, PCH_CAN_STOP);
+
+ /* Clearing all the message object buffers. */
+ pch_can_clear_buffers(priv);
+
+ /* Configuring the respective message object as either rx/tx object. */
+ pch_can_config_rx_tx_buffers(priv);
+
+ /* Enabling the interrupts. */
+ pch_can_set_int_enables(priv, PCH_CAN_ALL);
+}
+
+static void pch_can_release(struct pch_can_priv *priv)
+{
+ /* Stooping the CAN device. */
+ pch_can_set_run_mode(priv, PCH_CAN_STOP);
+
+ /* Disabling the interrupts. */
+ pch_can_set_int_enables(priv, PCH_CAN_NONE);
+
+ /* Disabling all the receive object. */
+ pch_can_rx_disable_all(priv);
+
+ /* Disabling all the transmit object. */
+ pch_can_tx_disable_all(priv);
+}
+
+/* This function clears interrupt(s) from the CAN device. */
+static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
+{
+ if (mask == CAN_STATUS_INT) {
+ ioread32(&priv->regs->stat);
+ return;
+ }
+
+ /* Clear interrupt for transmit object */
+ if ((mask >= 1) && (mask <= PCH_RX_OBJ_NUM)) {
+ /* Setting CMASK for clearing the reception interrupts. */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
+ &priv->regs->if1_cmask);
+
+ /* Clearing the Dir bit. */
+ pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
+
+ /* Clearing NewDat & IntPnd */
+ pch_can_bit_clear(&priv->regs->if1_mcont,
+ CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
+
+ pch_can_check_if_busy(&priv->regs->if1_creq, mask);
+ } else if ((mask > PCH_RX_OBJ_NUM) && (mask <= PCH_OBJ_NUM)) {
+ /* Setting CMASK for clearing interrupts for
+ frame transmission. */
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
+ &priv->regs->if2_cmask);
+
+ /* Resetting the ID registers. */
+ pch_can_bit_set(&priv->regs->if2_id2,
+ CAN_ID2_DIR | (0x7ff << 2));
+ iowrite32(0x0, &priv->regs->if2_id1);
+
+ /* Claring NewDat, TxRqst & IntPnd */
+ pch_can_bit_clear(&priv->regs->if2_mcont,
+ CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
+ CAN_IF_MCONT_TXRQXT);
+ pch_can_check_if_busy(&priv->regs->if2_creq, mask);
+ }
+}
+
+static u32 pch_can_get_buffer_status(struct pch_can_priv *priv)
+{
+ return (ioread32(&priv->regs->treq1) & 0xffff) |
+ ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
+}
+
+static void pch_can_reset(struct pch_can_priv *priv)
+{
+ /* write to sw reset register */
+ iowrite32(1, &priv->regs->srst);
+ iowrite32(0, &priv->regs->srst);
+}
+
+static void pch_can_error(struct net_device *ndev, u32 status)
+{
+ struct sk_buff *skb;
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct can_frame *cf;
+ u32 errc;
+ struct net_device_stats *stats = &(priv->ndev->stats);
+ enum can_state state = priv->can.state;
+
+ skb = alloc_can_err_skb(ndev, &cf);
+ if (!skb)
+ return;
+
+ if (status & PCH_BUS_OFF) {
+ pch_can_tx_disable_all(priv);
+ pch_can_rx_disable_all(priv);
+ state = CAN_STATE_BUS_OFF;
+ cf->can_id |= CAN_ERR_BUSOFF;
+ can_bus_off(ndev);
+ }
+
+ /* Warning interrupt. */
+ if (status & PCH_EWARN) {
+ state = CAN_STATE_ERROR_WARNING;
+ priv->can.can_stats.error_warning++;
+ cf->can_id |= CAN_ERR_CRTL;
+ errc = ioread32(&priv->regs->errc);
+ if (((errc & CAN_REC) >> 8) > 96)
+ cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+ if ((errc & CAN_TEC) > 96)
+ cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+ dev_warn(&ndev->dev,
+ "%s -> Error Counter is more than 96.\n", __func__);
+ }
+ /* Error passive interrupt. */
+ if (status & PCH_EPASSIV) {
+ priv->can.can_stats.error_passive++;
+ state = CAN_STATE_ERROR_PASSIVE;
+ cf->can_id |= CAN_ERR_CRTL;
+ errc = ioread32(&priv->regs->errc);
+ if (((errc & CAN_REC) >> 8) > 127)
+ cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+ if ((errc & CAN_TEC) > 127)
+ cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+ dev_err(&ndev->dev,
+ "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
+ }
+
+ if (status & PCH_LEC_ALL) {
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ switch (status & PCH_LEC_ALL) {
+ case PCH_STUF_ERR:
+ cf->data[2] |= CAN_ERR_PROT_STUFF;
+ break;
+ case PCH_FORM_ERR:
+ cf->data[2] |= CAN_ERR_PROT_FORM;
+ break;
+ case PCH_ACK_ERR:
+ cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
+ CAN_ERR_PROT_LOC_ACK_DEL;
+ break;
+ case PCH_BIT1_ERR:
+ case PCH_BIT0_ERR:
+ cf->data[2] |= CAN_ERR_PROT_BIT;
+ break;
+ case PCH_CRC_ERR:
+ cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
+ CAN_ERR_PROT_LOC_CRC_DEL;
+ break;
+ default:
+ iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
+ break;
+ }
+
+ }
+
+ priv->can.state = state;
+ netif_receive_skb(skb);
+
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+}
+
+static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = (struct net_device *)dev_id;
+ struct pch_can_priv *priv = netdev_priv(ndev);
+
+ pch_can_set_int_enables(priv, PCH_CAN_NONE);
+ napi_schedule(&priv->napi);
+
+ return IRQ_HANDLED;
+}
+
+static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
+{
+ if (obj_id < PCH_FIFO_THRESH) {
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
+ CAN_CMASK_ARB, &priv->regs->if1_cmask);
+
+ /* Clearing the Dir bit. */
+ pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
+
+ /* Clearing NewDat & IntPnd */
+ pch_can_bit_clear(&priv->regs->if1_mcont,
+ CAN_IF_MCONT_INTPND);
+ pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
+ } else if (obj_id > PCH_FIFO_THRESH) {
+ pch_can_int_clr(priv, obj_id);
+ } else if (obj_id == PCH_FIFO_THRESH) {
+ int cnt;
+ for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
+ pch_can_int_clr(priv, cnt+1);
+ }
+}
+
+static int pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &(priv->ndev->stats);
+ struct sk_buff *skb;
+ struct can_frame *cf;
+
+ dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
+ pch_can_bit_clear(&priv->regs->if1_mcont,
+ CAN_IF_MCONT_MSGLOST);
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
+ &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
+
+ skb = alloc_can_err_skb(ndev, &cf);
+ if (!skb)
+ return -ENOMEM;
+
+ priv->can.can_stats.error_passive++;
+ priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ cf->can_id |= CAN_ERR_CRTL;
+ cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+ stats->rx_over_errors++;
+ stats->rx_errors++;
+
+ netif_receive_skb(skb);
+
+ return 0;
+}
+
+static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
+{
+ u32 reg;
+ canid_t id;
+ u32 ide;
+ u32 rtr;
+ int rcv_pkts = 0;
+ int rtn;
+ int next_flag = 0;
+ struct sk_buff *skb;
+ struct can_frame *cf;
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &(priv->ndev->stats);
+
+ /* Reading the messsage object from the Message RAM */
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, obj_num);
+
+ /* Reading the MCONT register. */
+ reg = ioread32(&priv->regs->if1_mcont);
+ reg &= 0xffff;
+
+ for (; (!(reg & CAN_IF_MCONT_EOB)) && (quota > 0);
+ obj_num++, next_flag = 0) {
+ /* If MsgLost bit set. */
+ if (reg & CAN_IF_MCONT_MSGLOST) {
+ rtn = pch_can_rx_msg_lost(ndev, obj_num);
+ if (!rtn)
+ return rtn;
+ rcv_pkts++;
+ quota--;
+ next_flag = 1;
+ } else if (!(reg & CAN_IF_MCONT_NEWDAT))
+ next_flag = 1;
+
+ if (!next_flag) {
+ skb = alloc_can_skb(priv->ndev, &cf);
+ if (!skb)
+ return -ENOMEM;
+
+ /* Get Received data */
+ ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD);
+ if (ide) {
+ id = (ioread32(&priv->regs->if1_id1) & 0xffff);
+ id |= (((ioread32(&priv->regs->if1_id2)) &
+ 0x1fff) << 16);
+ cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ } else {
+ id = (((ioread32(&priv->regs->if1_id2)) &
+ (CAN_SFF_MASK << 2)) >> 2);
+ cf->can_id = (id & CAN_SFF_MASK);
+ }
+
+ rtr = ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR;
+
+ if (rtr)
+ cf->can_id |= CAN_RTR_FLAG;
+
+ cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
+ if1_mcont)) & 0xF);
+ *(u16 *)(cf->data + 0) = ioread16(&priv->regs->
+ if1_dataa1);
+ *(u16 *)(cf->data + 2) = ioread16(&priv->regs->
+ if1_dataa2);
+ *(u16 *)(cf->data + 4) = ioread16(&priv->regs->
+ if1_datab1);
+ *(u16 *)(cf->data + 6) = ioread16(&priv->regs->
+ if1_datab2);
+
+ netif_receive_skb(skb);
+ rcv_pkts++;
+ stats->rx_packets++;
+ quota--;
+ stats->rx_bytes += cf->can_dlc;
+
+ pch_fifo_thresh(priv, obj_num);
+ }
+
+ /* Reading the messsage object from the Message RAM */
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, obj_num + 1);
+ reg = ioread32(&priv->regs->if1_mcont);
+ }
+
+ return rcv_pkts;
+}
+
+static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &(priv->ndev->stats);
+ unsigned long flags;
+ u32 dlc;
+
+ can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
+ &priv->regs->if2_cmask);
+ dlc = ioread32(&priv->regs->if2_mcont) & CAN_IF_MCONT_DLC;
+ pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+ if (dlc > 8)
+ dlc = 8;
+ stats->tx_bytes += dlc;
+ stats->tx_packets++;
+}
+
+static int pch_can_rx_poll(struct napi_struct *napi, int quota)
+{
+ struct net_device *ndev = napi->dev;
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ u32 int_stat;
+ int rcv_pkts = 0;
+ u32 reg_stat;
+ unsigned long flags;
+
+ int_stat = pch_can_int_pending(priv);
+ if (!int_stat)
+ goto END;
+
+ if ((int_stat == CAN_STATUS_INT) && (quota > 0)) {
+ reg_stat = ioread32(&priv->regs->stat);
+ if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
+ if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
+ pch_can_error(ndev, reg_stat);
+ quota--;
+ }
+ }
+
+ if (reg_stat & PCH_TX_OK) {
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ pch_can_check_if_busy(&priv->regs->if2_creq,
+ ioread32(&priv->regs->intr));
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+ pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
+ }
+
+ if (reg_stat & PCH_RX_OK)
+ pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
+
+ int_stat = pch_can_int_pending(priv);
+ }
+
+ if (quota == 0)
+ goto END;
+
+ if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+ quota -= rcv_pkts;
+ if (rcv_pkts < 0)
+ goto END;
+ } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
+ /* Handle transmission interrupt */
+ pch_can_tx_complete(ndev, int_stat);
+ }
+
+END:
+ napi_complete(napi);
+ pch_can_set_int_enables(priv, PCH_CAN_ALL);
+
+ return rcv_pkts;
+}
+
+static int pch_set_bittiming(struct net_device *ndev)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ const struct can_bittiming *bt = &priv->can.bittiming;
+ u32 canbit;
+ u32 bepe;
+
+ /* Setting the CCE bit for accessing the Can Timing register. */
+ pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
+
+ canbit = (bt->brp - 1) & MSK_BITT_BRP;
+ canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
+ canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
+ canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
+ bepe = ((bt->brp - 1) & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
+ iowrite32(canbit, &priv->regs->bitt);
+ iowrite32(bepe, &priv->regs->brpe);
+ pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
+
+ return 0;
+}
+
+static void pch_can_start(struct net_device *ndev)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+
+ if (priv->can.state != CAN_STATE_STOPPED)
+ pch_can_reset(priv);
+
+ pch_set_bittiming(ndev);
+ pch_can_set_optmode(priv);
+
+ pch_can_tx_enable_all(priv);
+ pch_can_rx_enable_all(priv);
+
+ /* Setting the CAN to run mode. */
+ pch_can_set_run_mode(priv, PCH_CAN_RUN);
+
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+ return;
+}
+
+static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+ int ret = 0;
+
+ switch (mode) {
+ case CAN_MODE_START:
+ pch_can_start(ndev);
+ netif_wake_queue(ndev);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ return ret;
+}
+
+static int pch_can_open(struct net_device *ndev)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ int retval;
+
+ /* Regsitering the interrupt. */
+ retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
+ ndev->name, ndev);
+ if (retval) {
+ dev_err(&ndev->dev, "request_irq failed.\n");
+ goto req_irq_err;
+ }
+
+ /* Open common can device */
+ retval = open_candev(ndev);
+ if (retval) {
+ dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
+ goto err_open_candev;
+ }
+
+ pch_can_init(priv);
+ pch_can_start(ndev);
+ napi_enable(&priv->napi);
+ netif_start_queue(ndev);
+
+ return 0;
+
+err_open_candev:
+ free_irq(priv->dev->irq, ndev);
+req_irq_err:
+ pch_can_release(priv);
+
+ return retval;
+}
+
+static int pch_close(struct net_device *ndev)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+
+ netif_stop_queue(ndev);
+ napi_disable(&priv->napi);
+ pch_can_release(priv);
+ free_irq(priv->dev->irq, ndev);
+ close_candev(ndev);
+ priv->can.state = CAN_STATE_STOPPED;
+ return 0;
+}
+
+static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+ unsigned long flags;
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct can_frame *cf = (struct can_frame *)skb->data;
+ int tx_buffer_avail = 0;
+
+ if (can_dropped_invalid_skb(ndev, skb))
+ return NETDEV_TX_OK;
+
+ if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj + 1 */
+ while (ioread32(&priv->regs->treq2) & 0xfc00)
+ udelay(1);
+ priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
+ }
+
+ tx_buffer_avail = priv->tx_obj;
+ priv->tx_obj++;
+
+ /* Attaining the lock. */
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+
+ /* Setting the CMASK register to set value*/
+ iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
+
+ /* If ID extended is set. */
+ if (cf->can_id & CAN_EFF_FLAG) {
+ iowrite32(cf->can_id & 0xffff, &priv->regs->if2_id1);
+ iowrite32(((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD,
+ &priv->regs->if2_id2);
+ } else {
+ iowrite32(0, &priv->regs->if2_id1);
+ iowrite32((cf->can_id & CAN_SFF_MASK) << 2,
+ &priv->regs->if2_id2);
+ }
+
+ pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
+
+ /* If remote frame has to be transmitted.. */
+ if (!(cf->can_id & CAN_RTR_FLAG))
+ pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
+
+ /* If remote frame has to be transmitted.. */
+ if (cf->can_id & CAN_RTR_FLAG)
+ pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
+
+ /* Copy data to register */
+ if (cf->can_dlc > 0) {
+ u32 data1 = *((u16 *)&cf->data[0]);
+ iowrite32(data1, &priv->regs->if2_dataa1);
+ }
+ if (cf->can_dlc > 2) {
+ u32 data1 = *((u16 *)&cf->data[2]);
+ iowrite32(data1, &priv->regs->if2_dataa2);
+ }
+ if (cf->can_dlc > 4) {
+ u32 data1 = *((u16 *)&cf->data[4]);
+ iowrite32(data1, &priv->regs->if2_datab1);
+ }
+ if (cf->can_dlc > 6) {
+ u32 data1 = *((u16 *)&cf->data[6]);
+ iowrite32(data1, &priv->regs->if2_datab2);
+ }
+
+ can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
+
+ /* Set the size of the data. */
+ iowrite32(cf->can_dlc, &priv->regs->if2_mcont);
+
+ /* Update if2_mcont */
+ pch_can_bit_set(&priv->regs->if2_mcont,
+ CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT |
+ CAN_IF_MCONT_TXIE);
+
+ if (tx_buffer_avail == PCH_RX_OBJ_NUM) /* If points tail of FIFO */
+ pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_EOB);
+ pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+
+ return NETDEV_TX_OK;
+}
+
+static const struct net_device_ops pch_can_netdev_ops = {
+ .ndo_open = pch_can_open,
+ .ndo_stop = pch_close,
+ .ndo_start_xmit = pch_xmit,
+};
+
+static void __devexit pch_can_remove(struct pci_dev *pdev)
+{
+ struct net_device *ndev = pci_get_drvdata(pdev);
+ struct pch_can_priv *priv = netdev_priv(ndev);
+
+ unregister_candev(priv->ndev);
+ pci_iounmap(pdev, priv->regs);
+ if (priv->use_msi)
+ pci_disable_msi(priv->dev);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+ free_candev(priv->ndev);
+}
+
+#ifdef CONFIG_PM
+static void pch_can_set_int_custom(struct pch_can_priv *priv)
+{
+ /* Clearing the IE, SIE and EIE bits of Can control register. */
+ pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+
+ /* Appropriately setting them. */
+ pch_can_bit_set(&priv->regs->cont,
+ ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
+}
+
+/* This function retrieves interrupt enabled for the CAN device. */
+static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
+{
+ /* Obtaining the status of IE, SIE and EIE interrupt bits. */
+ return (ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1;
+}
+
+static u32 pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num)
+{
+ unsigned long flags;
+ u32 enable;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
+
+ if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
+ ((ioread32(&priv->regs->if1_mcont)) &
+ CAN_IF_MCONT_RXIE))
+ enable = 1;
+ else
+ enable = 0;
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+ return enable;
+}
+
+static u32 pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num)
+{
+ unsigned long flags;
+ u32 enable;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
+ if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
+ ((ioread32(&priv->regs->if2_mcont)) &
+ CAN_IF_MCONT_TXIE)) {
+ enable = 1;
+ } else {
+ enable = 0;
+ }
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+
+ return enable;
+}
+
+static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
+ u32 buffer_num, u32 set)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
+ iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
+ if (set == 1)
+ pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
+ else
+ pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
+
+ pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+}
+
+static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
+{
+ unsigned long flags;
+ u32 link;
+
+ spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+ iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
+
+ if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
+ link = 0;
+ else
+ link = 1;
+ spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+ return link;
+}
+
+static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ int i;
+ int retval;
+ u32 buf_stat; /* Variable for reading the transmit buffer status. */
+ u32 counter = COUNTER_LIMIT;
+
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct pch_can_priv *priv = netdev_priv(dev);
+
+ /* Stop the CAN controller */
+ pch_can_set_run_mode(priv, PCH_CAN_STOP);
+
+ /* Indicate that we are aboutto/in suspend */
+ priv->can.state = CAN_STATE_STOPPED;
+
+ /* Waiting for all transmission to complete. */
+ while (counter) {
+ buf_stat = pch_can_get_buffer_status(priv);
+ if (!buf_stat)
+ break;
+ counter--;
+ udelay(1);
+ }
+ if (!counter)
+ dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
+
+ /* Save interrupt configuration and then disable them */
+ priv->int_enables = pch_can_get_int_enables(priv);
+ pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
+
+ /* Save Tx buffer enable state */
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
+ priv->tx_enable[i] = pch_can_get_tx_enable(priv, i);
+
+ /* Disable all Transmit buffers */
+ pch_can_tx_disable_all(priv);
+
+ /* Save Rx buffer enable state */
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
+ priv->rx_enable[i] = pch_can_get_rx_enable(priv, i);
+ priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
+ }
+
+ /* Disable all Receive buffers */
+ pch_can_rx_disable_all(priv);
+ retval = pci_save_state(pdev);
+ if (retval) {
+ dev_err(&pdev->dev, "pci_save_state failed.\n");
+ } else {
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
+ }
+
+ return retval;
+}
+
+static int pch_can_resume(struct pci_dev *pdev)
+{
+ int i;
+ int retval;
+ struct net_device *dev = pci_get_drvdata(pdev);
+ struct pch_can_priv *priv = netdev_priv(dev);
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ retval = pci_enable_device(pdev);
+ if (retval) {
+ dev_err(&pdev->dev, "pci_enable_device failed.\n");
+ return retval;
+ }
+
+ pci_enable_wake(pdev, PCI_D3hot, 0);
+
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+ /* Disabling all interrupts. */
+ pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
+
+ /* Setting the CAN device in Stop Mode. */
+ pch_can_set_run_mode(priv, PCH_CAN_STOP);
+
+ /* Configuring the transmit and receive buffers. */
+ pch_can_config_rx_tx_buffers(priv);
+
+ /* Restore the CAN state */
+ pch_set_bittiming(dev);
+
+ /* Listen/Active */
+ pch_can_set_optmode(priv);
+
+ /* Enabling the transmit buffer. */
+ for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
+ pch_can_set_tx_enable(priv, i, priv->tx_enable[i]);
+
+ /* Configuring the receive buffer and enabling them. */
+ for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
+ /* Restore buffer link */
+ pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
+
+ /* Restore buffer enables */
+ pch_can_set_rx_enable(priv, i, priv->rx_enable[i]);
+ }
+
+ /* Enable CAN Interrupts */
+ pch_can_set_int_custom(priv);
+
+ /* Restore Run Mode */
+ pch_can_set_run_mode(priv, PCH_CAN_RUN);
+
+ return retval;
+}
+#else
+#define pch_can_suspend NULL
+#define pch_can_resume NULL
+#endif
+
+static int pch_can_get_berr_counter(const struct net_device *dev,
+ struct can_berr_counter *bec)
+{
+ struct pch_can_priv *priv = netdev_priv(dev);
+
+ bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
+ bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
+
+ return 0;
+}
+
+static int __devinit pch_can_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct net_device *ndev;
+ struct pch_can_priv *priv;
+ int rc;
+ void __iomem *addr;
+
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
+ goto probe_exit_endev;
+ }
+
+ rc = pci_request_regions(pdev, KBUILD_MODNAME);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
+ goto probe_exit_pcireq;
+ }
+
+ addr = pci_iomap(pdev, 1, 0);
+ if (!addr) {
+ rc = -EIO;
+ dev_err(&pdev->dev, "Failed pci_iomap\n");
+ goto probe_exit_ipmap;
+ }
+
+ ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
+ if (!ndev) {
+ rc = -ENOMEM;
+ dev_err(&pdev->dev, "Failed alloc_candev\n");
+ goto probe_exit_alloc_candev;
+ }
+
+ priv = netdev_priv(ndev);
+ priv->ndev = ndev;
+ priv->regs = addr;
+ priv->dev = pdev;
+ priv->can.bittiming_const = &pch_can_bittiming_const;
+ priv->can.do_set_mode = pch_can_do_set_mode;
+ priv->can.do_get_berr_counter = pch_can_get_berr_counter;
+ priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
+ CAN_CTRLMODE_LOOPBACK;
+ priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
+
+ ndev->irq = pdev->irq;
+ ndev->flags |= IFF_ECHO;
+
+ pci_set_drvdata(pdev, ndev);
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ ndev->netdev_ops = &pch_can_netdev_ops;
+ priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
+
+ netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
+
+ rc = pci_enable_msi(priv->dev);
+ if (rc) {
+ dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
+ priv->use_msi = 0;
+ } else {
+ dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
+ priv->use_msi = 1;
+ }
+
+ rc = register_candev(ndev);
+ if (rc) {
+ dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
+ goto probe_exit_reg_candev;
+ }
+
+ return 0;
+
+probe_exit_reg_candev:
+ free_candev(ndev);
+probe_exit_alloc_candev:
+ pci_iounmap(pdev, addr);
+probe_exit_ipmap:
+ pci_release_regions(pdev);
+probe_exit_pcireq:
+ pci_disable_device(pdev);
+probe_exit_endev:
+ return rc;
+}
+
+static struct pci_driver pch_can_pcidev = {
+ .name = "pch_can",
+ .id_table = pch_pci_tbl,
+ .probe = pch_can_probe,
+ .remove = __devexit_p(pch_can_remove),
+ .suspend = pch_can_suspend,
+ .resume = pch_can_resume,
+};
+
+static int __init pch_can_pci_init(void)
+{
+ return pci_register_driver(&pch_can_pcidev);
+}
+module_init(pch_can_pci_init);
+
+static void __exit pch_can_pci_exit(void)
+{
+ pci_unregister_driver(&pch_can_pcidev);
+}
+module_exit(pch_can_pci_exit);
+
+MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION("0.94");
^ permalink raw reply
* Re: [PATCH] virtio_net: Fix queue full check
From: Krishna Kumar2 @ 2010-10-29 10:55 UTC (permalink / raw)
To: Rusty Russell; +Cc: davem, netdev
In-Reply-To: <201010292017.25099.rusty@rustcorp.com.au>
Rusty Russell <rusty@rustcorp.com.au> wrote on 10/29/2010 03:17:24 PM:
> > Oct 17 10:22:40 localhost kernel: net eth0: Unexpected TX queue
failure: -28
> > Oct 17 10:28:22 localhost kernel: net eth0: Unexpected TX queue
failure: -28
> > Oct 17 10:35:58 localhost kernel: net eth0: Unexpected TX queue
failure: -28
> > Oct 17 10:41:06 localhost kernel: net eth0: Unexpected TX queue
failure: -28
> >
> > I initially changed the check from -ENOMEM to -ENOSPC, but
> > virtqueue_add_buf can return only -ENOSPC when it doesn't have
> > space for new request. Patch removes redundant checks but
> > displays the failure errno.
> >
> > Signed-off-by: Krishna Kumar <krkumar2@in.ibm.com>
> > ---
> > drivers/net/virtio_net.c | 15 ++++-----------
> > 1 file changed, 4 insertions(+), 11 deletions(-)
> >
> > diff -ruNp org/drivers/net/virtio_net.c new/drivers/net/virtio_net.c
> > --- org/drivers/net/virtio_net.c 2010-10-11 10:20:02.000000000 +0530
> > +++ new/drivers/net/virtio_net.c 2010-10-21 17:37:45.000000000 +0530
> > @@ -570,17 +570,10 @@ static netdev_tx_t start_xmit(struct sk_
> >
> > /* This can happen with OOM and indirect buffers. */
> > if (unlikely(capacity < 0)) {
> > - if (net_ratelimit()) {
> > - if (likely(capacity == -ENOMEM)) {
> > - dev_warn(&dev->dev,
> > - "TX queue failure: out of memory\n");
> > - } else {
> > - dev->stats.tx_fifo_errors++;
> > - dev_warn(&dev->dev,
> > - "Unexpected TX queue failure: %d\n",
> > - capacity);
> > - }
> > - }
> > + if (net_ratelimit())
> > + dev_warn(&dev->dev,
> > + "TX queue failure (%d): out of memory\n",
> > + capacity);
>
> Hold on... you were getting -ENOSPC, which shouldn't happen. What makes
you
> think it's out of memory?
virtqueue_add_buf_gfp returns only -ENOSPC on failure, whether
direct or indirect descriptors are used, so isn't -ENOSPC
"expected"? (vring_add_indirect returns -ENOMEM on memory
failure, but that is masked out and we go direct which is
the failure point).
Thanks,
- KK
^ permalink raw reply
* [PATCH] RDMA/addr: remove dev_base_lock use from rdma_translate_ip()
From: Eric Dumazet @ 2010-10-29 11:03 UTC (permalink / raw)
To: David Miller
Cc: netdev, Roland Dreier, Sean Hefty, Hal Rosenstock, linux-rdma
dev_base_lock is the legacy way to lock the device list, and is planned
to disappear. (writers hold RTNL, readers hold RCU lock)
Convert rdma_translate_ip() to RCU locking.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
---
drivers/infiniband/core/addr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c
index a5ea1bc..309b477 100644
--- a/drivers/infiniband/core/addr.c
+++ b/drivers/infiniband/core/addr.c
@@ -130,8 +130,8 @@ int rdma_translate_ip(struct sockaddr *addr, struct rdma_dev_addr *dev_addr)
#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
case AF_INET6:
- read_lock(&dev_base_lock);
- for_each_netdev(&init_net, dev) {
+ rcu_read_lock();
+ for_each_netdev_rcu(&init_net, dev) {
if (ipv6_chk_addr(&init_net,
&((struct sockaddr_in6 *) addr)->sin6_addr,
dev, 1)) {
@@ -139,7 +139,7 @@ int rdma_translate_ip(struct sockaddr *addr, struct rdma_dev_addr *dev_addr)
break;
}
}
- read_unlock(&dev_base_lock);
+ rcu_read_unlock();
break;
#endif
}
^ permalink raw reply related
* Re: [RFC PATCH 0/2] SL351x (Gemini) ethernet driver
From: Paulius Zaleckas @ 2010-10-29 11:14 UTC (permalink / raw)
To: Michał Mirosław
Cc: Hans Ulli Kroll, Russell King, linux-arm-kernel, linux-kernel,
netdev, Janos Laube
In-Reply-To: <cover.1288321597.git.mirq-linux@rere.qmqm.pl>
2010/10/29 Michał Mirosław <mirq-linux@rere.qmqm.pl>:
> This is a driver for SL351x (Gemini) SoC ethernet peripheral.
> Based on work by Paulius Zaleckas and GPLd code from Raidsonic
> and other NAS vendors.
>
> This is work in progress. Please comment and test if you can.
> Patches are against 2.6.37-rc (current Linus' tree) but should
> apply to 2.6.36. You probably also need patches for PATA from
> git://git.berlios.de/gemini-board ib4220
Nice to hear!
> Known bugs:
> - repeatable bad HW calculated TCP csum
> happens for only some packets in a TCP stream
> looks like it doesn't like some data pattern or timing
> (difference between correct and generated csum is the same
> when the packet is retransmitted with changed header/TCP tstamp)
> - TX DMA hangs sometimes (needs module reload when that happens)
> with debugging printks disabled and HW TX csum enabled
AFAIK DMA hangs are associated with HW checksum errors. So generally
disabling HW csum is the best solution so far. If I am not wrong, OpenWRT
does just this in their patches.
DMA hangs happen for other reasons as well and main cause seems to be MII
interface. If timing is wrong or some noise gets onto PCB tracks it is
very likely
that DMA will hang. Also using both ports at one time increases posibility of
hang.
> - unsynced counters
>
> I started to work on Paulius' code to find out why the TX DMA hangs
> happen, but then I realized that complete rewrite was a better way
> to understand how the hardware works and why it doesn't. As a "bonus"
> this got some additional features:
> - ethtool support
> - 64-bit counters
> - proper cleanup on ifdown/module unload
> - better DMA API usage
> - cleaned up code
> - a lot of tx/rx debugging printks
> - based on 2.6.36 DMA and netdev interfaces
>
> TODO:
> - NAPI
> - MTU changing
Super cool! NAPI shouldn't be very hard...
> For normal use tx-csum and tso have to be disabled:
> ethtool -K eth0 tso off tx off
>
> Tested on Raidsonic IcyBox 4220-B (dual SATA NAS).
>
> I'm also interested in getting copies of various GPL packages for
> StorLink SL3516. I already have following packages (md5sum):
>
> 89991e543eb2e473e3d380ac9a4cd8b4 GPL_source_code(Raidsonic).zip
> 6ba8b833c429794315f0a73ce2961bd8 Gemini_v2_6_0-n.tgz
> fe87e97a33554bcab8284d25ff86e383 n299_n199_1.00.24_GPL.tar.bz2
> eca8994354368304ca3b5bd1429c20bb sl-boot_1.0.9.tgz
> eafd6497074fe0651459bf38c39d66bd vt4kern-1.5.tar.bz2.tar
I will see what I can provide you when I get home.
>
> Best Regards,
> Michał Mirosław
>
> ---
>
> Michał Mirosław (2):
> Gemini: create platform device for ethernet in Raidsonic IB-4220B
> Gemini: SL351x Ethernet driver
>
> arch/arm/mach-gemini/board-nas4220b.c | 53 +
> arch/arm/mach-gemini/common.h | 2 +
> arch/arm/mach-gemini/devices.c | 52 +
> arch/arm/mach-gemini/include/mach/gmac.h | 21 +
> drivers/net/Kconfig | 7 +
> drivers/net/Makefile | 1 +
> drivers/net/sl351x.c | 1706 ++++++++++++++++++++++++++++++
> drivers/net/sl351x_hw.h | 1423 +++++++++++++++++++++++++
> 8 files changed, 3265 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-gemini/include/mach/gmac.h
> create mode 100644 drivers/net/sl351x.c
> create mode 100644 drivers/net/sl351x_hw.h
>
>
^ permalink raw reply
* [PATCH] aoe: remove dev_base_lock use from aoecmd_cfg_pkts()
From: Eric Dumazet @ 2010-10-29 11:15 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Ed L. Cashin
dev_base_lock is the legacy way to lock the device list, and is planned
to disappear. (writers hold RTNL, readers hold RCU lock)
Convert aoecmd_cfg_pkts() to RCU locking.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Cc: "Ed L. Cashin" <ecashin@coraid.com>
---
drivers/block/aoe/aoecmd.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/block/aoe/aoecmd.c b/drivers/block/aoe/aoecmd.c
index 5674bd0..de0435e 100644
--- a/drivers/block/aoe/aoecmd.c
+++ b/drivers/block/aoe/aoecmd.c
@@ -297,8 +297,8 @@ aoecmd_cfg_pkts(ushort aoemajor, unsigned char aoeminor, struct sk_buff_head *qu
struct sk_buff *skb;
struct net_device *ifp;
- read_lock(&dev_base_lock);
- for_each_netdev(&init_net, ifp) {
+ rcu_read_lock();
+ for_each_netdev_rcu(&init_net, ifp) {
dev_hold(ifp);
if (!is_aoe_netif(ifp))
goto cont;
@@ -325,7 +325,7 @@ aoecmd_cfg_pkts(ushort aoemajor, unsigned char aoeminor, struct sk_buff_head *qu
cont:
dev_put(ifp);
}
- read_unlock(&dev_base_lock);
+ rcu_read_unlock();
}
static void
^ permalink raw reply related
* Re: [RFC PATCH 1/2] Gemini: create platform device for ethernet in Raidsonic IB-4220B
From: Paulius Zaleckas @ 2010-10-29 11:17 UTC (permalink / raw)
To: Michał Mirosław
Cc: Hans Ulli Kroll, Russell King, linux-arm-kernel, linux-kernel,
netdev, Janos Laube
In-Reply-To: <181be0f834f3670249d3c8d7ba1462dab1ece2c1.1288321597.git.mirq-linux@rere.qmqm.pl>
2010/10/29 Michał Mirosław <mirq-linux@rere.qmqm.pl>:
> This is cherry-picked from:
>
> git://git.berlios.de/gemini-board ib4220
>
> Code by Paulius Zaleckas <paulius.zaleckas@gmail.com>
> and Janos Laube <janos.dev@gmail.com>.
>
> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
> ---
>
> arch/arm/mach-gemini/board-nas4220b.c | 53 ++++++++++++++++++++++++++++++
> arch/arm/mach-gemini/common.h | 2 +
> arch/arm/mach-gemini/devices.c | 52 +++++++++++++++++++++++++++++
> arch/arm/mach-gemini/include/mach/gmac.h | 21 ++++++++++++
> 4 files changed, 128 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/mach-gemini/include/mach/gmac.h
>
[...]
> diff --git a/arch/arm/mach-gemini/include/mach/gmac.h b/arch/arm/mach-gemini/include/mach/gmac.h
> new file mode 100644
> index 0000000..c6eeacc
> --- /dev/null
> +++ b/arch/arm/mach-gemini/include/mach/gmac.h
> @@ -0,0 +1,21 @@
> +/*
> + * Gemini GMAC specific defines
> + *
> + * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
This e-mail is dead. Please change it to gmail one.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef __MACH_GMAC_H__
> +#define __MACH_GMAC_H__
> +
> +#include <linux/phy.h>
> +
> +struct gemini_gmac_platform_data {
> + char *bus_id[2]; /* NULL means that this port is not used */
> + phy_interface_t interface[2];
> +};
> +
> +#endif /* __MACH_GMAC_H__ */
> --
> 1.7.1
>
>
^ permalink raw reply
* Re: [v3 RFC PATCH 0/4] Implement multiqueue virtio-net
From: Michael S. Tsirkin @ 2010-10-29 11:26 UTC (permalink / raw)
To: Krishna Kumar2
Cc: anthony, arnd, avi, davem, eric.dumazet, kvm, netdev, rusty
In-Reply-To: <OFE75E1E91.9722BFB3-ON652577CA.00256D94-652577CA.0027E1CE@in.ibm.com>
On Thu, Oct 28, 2010 at 12:48:57PM +0530, Krishna Kumar2 wrote:
> > Krishna Kumar2/India/IBM wrote on 10/28/2010 10:44:14 AM:
> >
> > > > > > Results for UDP BW tests (unidirectional, sum across
> > > > > > 3 iterations, each iteration of 45 seconds, default
> > > > > > netperf, vhosts bound to cpus 0-3; no other tuning):
> > > > >
> > > > > Is binding vhost threads to CPUs really required?
> > > > > What happens if we let the scheduler do its job?
> > > >
> > > > Nothing drastic, I remember BW% and SD% both improved a
> > > > bit as a result of binding.
> > >
> > > If there's a significant improvement this would mean that
> > > we need to rethink the vhost-net interaction with the scheduler.
> >
> > I will get a test run with and without binding and post the
> > results later today.
>
> Correction: The result with binding is is much better for
> SD/CPU compared to without-binding:
Can you pls ty finding out why that is? Is some thread bouncing between
CPUs? Does a wrong numa node get picked up?
In practice users are very unlikely to pin threads to CPUs.
--
MST
^ permalink raw reply
* Re: [PATCH] virtio_net: Fix queue full check
From: Rusty Russell @ 2010-10-29 11:28 UTC (permalink / raw)
To: Krishna Kumar2; +Cc: davem, netdev, Michael S. Tsirkin
In-Reply-To: <OF30574F6E.113EC5F4-ON652577CB.0037DAB5-652577CB.003BACE8@in.ibm.com>
On Fri, 29 Oct 2010 09:25:09 pm Krishna Kumar2 wrote:
> Rusty Russell <rusty@rustcorp.com.au> wrote on 10/29/2010 03:17:24 PM:
>
> > > Oct 17 10:22:40 localhost kernel: net eth0: Unexpected TX queue
> failure: -28
> > > Oct 17 10:28:22 localhost kernel: net eth0: Unexpected TX queue
> failure: -28
> > > Oct 17 10:35:58 localhost kernel: net eth0: Unexpected TX queue
> failure: -28
> > > Oct 17 10:41:06 localhost kernel: net eth0: Unexpected TX queue
> failure: -28
> > >
> > > I initially changed the check from -ENOMEM to -ENOSPC, but
> > > virtqueue_add_buf can return only -ENOSPC when it doesn't have
> > > space for new request. Patch removes redundant checks but
> > > displays the failure errno.
> > >
> > > Signed-off-by: Krishna Kumar <krkumar2@in.ibm.com>
> > > ---
> > > drivers/net/virtio_net.c | 15 ++++-----------
> > > 1 file changed, 4 insertions(+), 11 deletions(-)
> > >
> > > diff -ruNp org/drivers/net/virtio_net.c new/drivers/net/virtio_net.c
> > > --- org/drivers/net/virtio_net.c 2010-10-11 10:20:02.000000000 +0530
> > > +++ new/drivers/net/virtio_net.c 2010-10-21 17:37:45.000000000 +0530
> > > @@ -570,17 +570,10 @@ static netdev_tx_t start_xmit(struct sk_
> > >
> > > /* This can happen with OOM and indirect buffers. */
> > > if (unlikely(capacity < 0)) {
> > > - if (net_ratelimit()) {
> > > - if (likely(capacity == -ENOMEM)) {
> > > - dev_warn(&dev->dev,
> > > - "TX queue failure: out of memory\n");
> > > - } else {
> > > - dev->stats.tx_fifo_errors++;
> > > - dev_warn(&dev->dev,
> > > - "Unexpected TX queue failure: %d\n",
> > > - capacity);
> > > - }
> > > - }
> > > + if (net_ratelimit())
> > > + dev_warn(&dev->dev,
> > > + "TX queue failure (%d): out of memory\n",
> > > + capacity);
> >
> > Hold on... you were getting -ENOSPC, which shouldn't happen. What makes
> you
> > think it's out of memory?
>
> virtqueue_add_buf_gfp returns only -ENOSPC on failure, whether
> direct or indirect descriptors are used, so isn't -ENOSPC
> "expected"? (vring_add_indirect returns -ENOMEM on memory
> failure, but that is masked out and we go direct which is
> the failure point).
Ah, OK, gotchya.
I'm not even sure the fallback to linear makes sense; if we're failing
kmallocs we should probably just return -ENOMEM. Would mean we can
tell the difference between "out of space" (which should never happen
since we stop the queue when we have < 2+MAX_SKB_FRAGS slots left)
and this case.
Michael, what do you think?
Thanks,
Rusty.
^ permalink raw reply
* [PATCH] bonding: remove dev_base_lock use
From: Eric Dumazet @ 2010-10-29 11:52 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Jay Vosburgh
bond_info_seq_start() uses a read_lock(&dev_base_lock) to make sure
device doesn’t disappear. Same goal can be achieved using RCU.
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
---
drivers/net/bonding/bond_main.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index bdb68a6..5188448 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -3209,7 +3209,7 @@ out:
#ifdef CONFIG_PROC_FS
static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos)
- __acquires(&dev_base_lock)
+ __acquires(RCU)
__acquires(&bond->lock)
{
struct bonding *bond = seq->private;
@@ -3218,7 +3218,7 @@ static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos)
int i;
/* make sure the bond won't be taken away */
- read_lock(&dev_base_lock);
+ rcu_read_lock();
read_lock(&bond->lock);
if (*pos == 0)
@@ -3248,12 +3248,12 @@ static void *bond_info_seq_next(struct seq_file *seq, void *v, loff_t *pos)
static void bond_info_seq_stop(struct seq_file *seq, void *v)
__releases(&bond->lock)
- __releases(&dev_base_lock)
+ __releases(RCU)
{
struct bonding *bond = seq->private;
read_unlock(&bond->lock);
- read_unlock(&dev_base_lock);
+ rcu_read_unlock();
}
static void bond_info_show_master(struct seq_file *seq)
^ permalink raw reply related
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