* Re: bonding: flow control regression [was Re: bridging: flow control regression]
From: Eric Dumazet @ 2010-11-02 4:53 UTC (permalink / raw)
To: Simon Horman; +Cc: netdev, Jay Vosburgh, David S. Miller
In-Reply-To: <20101102020625.GA22724@verge.net.au>
Le mardi 02 novembre 2010 à 11:06 +0900, Simon Horman a écrit :
> Thanks for the explanation.
> I'm not entirely sure how much of a problem this is in practice.
Maybe for virtual devices (tunnels, bonding, ...), it would make sense
to delay the orphaning up to the real device.
But if the socket send buffer is very large, it would defeat the flow
control any way...
^ permalink raw reply
* Re: bonding: flow control regression [was Re: bridging: flow control regression]
From: Simon Horman @ 2010-11-02 7:03 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, Jay Vosburgh, David S. Miller
In-Reply-To: <1288673622.2660.147.camel@edumazet-laptop>
On Tue, Nov 02, 2010 at 05:53:42AM +0100, Eric Dumazet wrote:
> Le mardi 02 novembre 2010 à 11:06 +0900, Simon Horman a écrit :
>
> > Thanks for the explanation.
> > I'm not entirely sure how much of a problem this is in practice.
>
> Maybe for virtual devices (tunnels, bonding, ...), it would make sense
> to delay the orphaning up to the real device.
That was my initial thought. Could you give me some guidance
on how that might be done so I can try and make a patch to test?
> But if the socket send buffer is very large, it would defeat the flow
> control any way...
I'm primarily concerned about a situation where
UDP packets are sent as fast as possible, indefinitely.
And in that scenario, I think it would need to be a rather large buffer.
^ permalink raw reply
* RE: About the Davicom PHY in drivers/net/phy in Linux kernel
From: macpaul @ 2010-11-02 7:27 UTC (permalink / raw)
To: joseph_chang, netdev; +Cc: afleming, jeff, f.rodo
Hi Joseph,
> From: Joseph Chang [mailto:joseph_chang@mail.davicom.com.tw]
> Sent: Monday, November 01, 2010 10:27 AM
> To: Macpaul Chih-Pin Lin(林智斌); netdev@vger.kernel.org
> Cc: afleming@freescale.com; jeff@garzik.org; f.rodo@til-technologies.fr
> Subject: RE: About the Davicom PHY in drivers/net/phy in Linux kernel
>
> Dear MacPaul,
>
> 1.Yes. I have downloaded it. And below is the know items.
>
> DM9161A
> cpu: Faraday A320 (arm920t) + Andes AG101 (NDS32) ;SoC
> OS: Linux: 2.6.32
> Actions:
> - davicom.c // Download from LXR
> - include-linux-mii.h // Download from LXR
Yes
> 2.Your quote is right. Please tell us the test result.
On our EVB board, RESET won't have dhcp problem (unstable) however ISOLATE does.
> 3.I have a question for you,
> Where is your company? I browse for andestech, And found that andestech
> located at
> SiSoft SIPP Center! (Address: 2F, No.1, Li-Hsin First Road, Science-Based
> Industrial Park)
> Is it right?
Yes. That's the location of my company.
>
> Best Regards,
> Joseph CHANG
> System Application Engineering Division
> Davicom Semiconductor, Inc.
> No. 6 Li-Hsin Rd. VI, Science-Based Park,
> Hsin-Chu, Taiwan.
> Tel: 886-3-5798797 Ex 8534
> Fax: 886-3-5646929
> Web: http://www.davicom.com.tw
[Deleted]
Best regards,
Macpaul Lin
^ permalink raw reply
* Re: bonding: flow control regression [was Re: bridging: flow control regression]
From: Eric Dumazet @ 2010-11-02 7:30 UTC (permalink / raw)
To: Simon Horman; +Cc: netdev, Jay Vosburgh, David S. Miller
In-Reply-To: <20101102070308.GA19924@verge.net.au>
Le mardi 02 novembre 2010 à 16:03 +0900, Simon Horman a écrit :
> On Tue, Nov 02, 2010 at 05:53:42AM +0100, Eric Dumazet wrote:
> > Le mardi 02 novembre 2010 à 11:06 +0900, Simon Horman a écrit :
> >
> > > Thanks for the explanation.
> > > I'm not entirely sure how much of a problem this is in practice.
> >
> > Maybe for virtual devices (tunnels, bonding, ...), it would make sense
> > to delay the orphaning up to the real device.
>
> That was my initial thought. Could you give me some guidance
> on how that might be done so I can try and make a patch to test?
>
> > But if the socket send buffer is very large, it would defeat the flow
> > control any way...
>
> I'm primarily concerned about a situation where
> UDP packets are sent as fast as possible, indefinitely.
> And in that scenario, I think it would need to be a rather large buffer.
>
Please try following patch, thanks.
drivers/net/bonding/bond_main.c | 1 +
include/linux/if.h | 3 +++
net/core/dev.c | 5 +++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index bdb68a6..325931e 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -4714,6 +4714,7 @@ static void bond_setup(struct net_device *bond_dev)
bond_dev->flags |= IFF_MASTER|IFF_MULTICAST;
bond_dev->priv_flags |= IFF_BONDING;
bond_dev->priv_flags &= ~IFF_XMIT_DST_RELEASE;
+ bond_dev->priv_flags &= ~IFF_EARLY_ORPHAN;
if (bond->params.arp_interval)
bond_dev->priv_flags |= IFF_MASTER_ARPMON;
diff --git a/include/linux/if.h b/include/linux/if.h
index 1239599..7499a99 100644
--- a/include/linux/if.h
+++ b/include/linux/if.h
@@ -77,6 +77,9 @@
#define IFF_BRIDGE_PORT 0x8000 /* device used as bridge port */
#define IFF_OVS_DATAPATH 0x10000 /* device used as Open vSwitch
* datapath port */
+#define IFF_EARLY_ORPHAN 0x20000 /* early orphan skbs in
+ * dev_hard_start_xmit()
+ */
#define IF_GET_IFACE 0x0001 /* for querying only */
#define IF_GET_PROTO 0x0002
diff --git a/net/core/dev.c b/net/core/dev.c
index 35dfb83..eabf94d 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -2005,7 +2005,8 @@ int dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev,
if (dev->priv_flags & IFF_XMIT_DST_RELEASE)
skb_dst_drop(skb);
- skb_orphan_try(skb);
+ if (dev->priv_flags & IFF_EARLY_ORPHAN)
+ skb_orphan_try(skb);
if (vlan_tx_tag_present(skb) &&
!(dev->features & NETIF_F_HW_VLAN_TX)) {
@@ -5590,7 +5591,7 @@ struct net_device *alloc_netdev_mq(int sizeof_priv, const char *name,
INIT_LIST_HEAD(&dev->napi_list);
INIT_LIST_HEAD(&dev->unreg_list);
INIT_LIST_HEAD(&dev->link_watch_list);
- dev->priv_flags = IFF_XMIT_DST_RELEASE;
+ dev->priv_flags = IFF_XMIT_DST_RELEASE | IFF_EARLY_ORPHAN ;
setup(dev);
strcpy(dev->name, name);
return dev;
^ permalink raw reply related
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^ permalink raw reply
* Re: bonding: flow control regression [was Re: bridging: flow control regression]
From: Simon Horman @ 2010-11-02 8:46 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, Jay Vosburgh, David S. Miller
In-Reply-To: <1288683057.2660.154.camel@edumazet-laptop>
On Tue, Nov 02, 2010 at 08:30:57AM +0100, Eric Dumazet wrote:
> Le mardi 02 novembre 2010 à 16:03 +0900, Simon Horman a écrit :
> > On Tue, Nov 02, 2010 at 05:53:42AM +0100, Eric Dumazet wrote:
> > > Le mardi 02 novembre 2010 à 11:06 +0900, Simon Horman a écrit :
> > >
> > > > Thanks for the explanation.
> > > > I'm not entirely sure how much of a problem this is in practice.
> > >
> > > Maybe for virtual devices (tunnels, bonding, ...), it would make sense
> > > to delay the orphaning up to the real device.
> >
> > That was my initial thought. Could you give me some guidance
> > on how that might be done so I can try and make a patch to test?
> >
> > > But if the socket send buffer is very large, it would defeat the flow
> > > control any way...
> >
> > I'm primarily concerned about a situation where
> > UDP packets are sent as fast as possible, indefinitely.
> > And in that scenario, I think it would need to be a rather large buffer.
> >
>
> Please try following patch, thanks.
Thanks Eric, that seems to resolve the problem that I was seeing.
With your patch I see:
No bonding
# netperf -c -4 -t UDP_STREAM -H 172.17.60.216 -l 30 -- -m 1472
UDP UNIDIRECTIONAL SEND TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 172.17.60.216 (172.17.60.216) port 0 AF_INET
Socket Message Elapsed Messages CPU Service
Size Size Time Okay Errors Throughput Util Demand
bytes bytes secs # # 10^6bits/sec % SU us/KB
116736 1472 30.00 2438413 0 957.2 8.52 1.458
129024 30.00 2438413 957.2 -1.00 -1.000
With bonding (one slave, the interface used in the test above)
netperf -c -4 -t UDP_STREAM -H 172.17.60.216 -l 30 -- -m 1472
UDP UNIDIRECTIONAL SEND TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 172.17.60.216 (172.17.60.216) port 0 AF_INET
Socket Message Elapsed Messages CPU Service
Size Size Time Okay Errors Throughput Util Demand
bytes bytes secs # # 10^6bits/sec % SU us/KB
116736 1472 30.00 2438390 0 957.1 8.97 1.535
129024 30.00 2438390 957.1 -1.00 -1.000
^ permalink raw reply
* Urgent...(Webmail upgrade notice)
From: Webmail Help Desk @ 2010-11-02 8:06 UTC (permalink / raw)
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^ permalink raw reply
* Re: bonding: flow control regression [was Re: bridging: flow control regression]
From: Eric Dumazet @ 2010-11-02 9:29 UTC (permalink / raw)
To: Simon Horman; +Cc: netdev, Jay Vosburgh, David S. Miller
In-Reply-To: <20101102084646.GA23774@verge.net.au>
Le mardi 02 novembre 2010 à 17:46 +0900, Simon Horman a écrit :
> Thanks Eric, that seems to resolve the problem that I was seeing.
>
> With your patch I see:
>
> No bonding
>
> # netperf -c -4 -t UDP_STREAM -H 172.17.60.216 -l 30 -- -m 1472
> UDP UNIDIRECTIONAL SEND TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 172.17.60.216 (172.17.60.216) port 0 AF_INET
> Socket Message Elapsed Messages CPU Service
> Size Size Time Okay Errors Throughput Util Demand
> bytes bytes secs # # 10^6bits/sec % SU us/KB
>
> 116736 1472 30.00 2438413 0 957.2 8.52 1.458
> 129024 30.00 2438413 957.2 -1.00 -1.000
>
> With bonding (one slave, the interface used in the test above)
>
> netperf -c -4 -t UDP_STREAM -H 172.17.60.216 -l 30 -- -m 1472
> UDP UNIDIRECTIONAL SEND TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 172.17.60.216 (172.17.60.216) port 0 AF_INET
> Socket Message Elapsed Messages CPU Service
> Size Size Time Okay Errors Throughput Util Demand
> bytes bytes secs # # 10^6bits/sec % SU us/KB
>
> 116736 1472 30.00 2438390 0 957.1 8.97 1.535
> 129024 30.00 2438390 957.1 -1.00 -1.000
>
Sure the patch helps when not too many flows are involved, but this is a
hack.
Say the device queue is 1000 packets, and you run a workload with 2000
sockets, it wont work...
Or device queue is 1000 packets, one flow, and socket send queue size
allows for more than 1000 packets to be 'in flight' (echo 2000000
>/proc/sys/net/core/wmem_default) , it wont work too with bonding, only
with devices with a qdisc sitting in the first device met after the
socket.
^ permalink raw reply
* Re: [PATCH net-next-2.6 v2] can: Topcliff: PCH_CAN driver: Fix build warnings
From: Tomoya MORINAGA @ 2010-11-02 10:27 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w, Masayuki Ohtake,
Samuel Ortiz, margie.foster-ral2JQCrhuEAvxtiuMwx3w,
netdev-u79uwXL29TY76Z2rM5mHXA, LKML,
socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
kok.howg.ewe-ral2JQCrhuEAvxtiuMwx3w, Wolfgang Grandegger,
joel.clark-ral2JQCrhuEAvxtiuMwx3w, David S. Miller,
Christian Pellegrin, qi.wang-ral2JQCrhuEAvxtiuMwx3w
In-Reply-To: <4CCAF517.2000409@pengutronix.de>
On Saturday, October 30, 2010 1:23 AM, Marc Kleine-Budde wrote:
> > The driver has already been merged. Please send incremental patches
> > against david's net-2.6 branch.
I agree.
>
> Here a review, find comments inline. Lets talk about my remarks, please
> answer inline and don't delete the code.
>
> Can you please explain me your locking sheme? If I understand the
> documenation correctly the two message interfaces can be used mutual.
> And you use one for rx the other one for tx.
I show our locking scheme.
When CPU accesses MessageRAM via IF1, CPU protect until read-modify-write
so that IF2 access not occurred, vice versa.
>
> Please use netdev_<level> instead of dev_<level> for debug.
I agree.
>
> > --- /dev/null
> > +++ b/drivers/net/can/pch_can.c
> > @@ -0,0 +1,1436 @@
> > +/*
> > + * Copyright (C) 1999 - 2010 Intel Corporation.
> > + * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; version 2 of the License.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
> > + */
> > +
> > +#include <linux/interrupt.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/sched.h>
> > +#include <linux/pci.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/errno.h>
> > +#include <linux/netdevice.h>
> > +#include <linux/skbuff.h>
> > +#include <linux/can.h>
> > +#include <linux/can/dev.h>
> > +#include <linux/can/error.h>
> > +
> > +#define MAX_MSG_OBJ 32
> > +#define MSG_OBJ_RX 0 /* The receive message object flag. */
> > +#define MSG_OBJ_TX 1 /* The transmit message object flag. */
> > +
> > +#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
> > +#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
> > +#define CAN_CTRL_IE_SIE_EIE 0x000e
> > +#define CAN_CTRL_CCE 0x0040
> > +#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
> > +#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
> > +#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
> > +#define CAN_CMASK_RX_TX_SET 0x00f3
> > +#define CAN_CMASK_RX_TX_GET 0x0073
> > +#define CAN_CMASK_ALL 0xff
> > +#define CAN_CMASK_RDWR 0x80
> > +#define CAN_CMASK_ARB 0x20
> > +#define CAN_CMASK_CTRL 0x10
> > +#define CAN_CMASK_MASK 0x40
> > +#define CAN_CMASK_NEWDAT 0x04
> > +#define CAN_CMASK_CLRINTPND 0x08
> > +
> > +#define CAN_IF_MCONT_NEWDAT 0x8000
> > +#define CAN_IF_MCONT_INTPND 0x2000
> > +#define CAN_IF_MCONT_UMASK 0x1000
> > +#define CAN_IF_MCONT_TXIE 0x0800
> > +#define CAN_IF_MCONT_RXIE 0x0400
> > +#define CAN_IF_MCONT_RMTEN 0x0200
> > +#define CAN_IF_MCONT_TXRQXT 0x0100
> > +#define CAN_IF_MCONT_EOB 0x0080
> > +#define CAN_IF_MCONT_DLC 0x000f
> > +#define CAN_IF_MCONT_MSGLOST 0x4000
> > +#define CAN_MASK2_MDIR_MXTD 0xc000
> > +#define CAN_ID2_DIR 0x2000
> > +#define CAN_ID_MSGVAL 0x8000
> > +
> > +#define CAN_STATUS_INT 0x8000
> > +#define CAN_IF_CREQ_BUSY 0x8000
> > +#define CAN_ID2_XTD 0x4000
> > +
> > +#define CAN_REC 0x00007f00
> > +#define CAN_TEC 0x000000ff
>
> A prefix for like PCH_ instead of CAN_ for all those define above would
> be fine to avoid namespace clashes and/or confusion with the defines from the socketcan framework.
>
I agree.
> > +
> > +#define PCH_RX_OK 0x00000010
> > +#define PCH_TX_OK 0x00000008
> > +#define PCH_BUS_OFF 0x00000080
> > +#define PCH_EWARN 0x00000040
> > +#define PCH_EPASSIV 0x00000020
> > +#define PCH_LEC0 0x00000001
> > +#define PCH_LEC1 0x00000002
> > +#define PCH_LEC2 0x00000004
>
> These are just single set bit, please use BIT()
> Consider adding the name of the corresponding register to the define's
> name.
I agree.
>
> > +#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
> > +#define PCH_STUF_ERR PCH_LEC0
> > +#define PCH_FORM_ERR PCH_LEC1
> > +#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
> > +#define PCH_BIT1_ERR PCH_LEC2
> > +#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
> > +#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
> > +
> > +/* bit position of certain controller bits. */
> > +#define BIT_BITT_BRP 0
> > +#define BIT_BITT_SJW 6
> > +#define BIT_BITT_TSEG1 8
> > +#define BIT_BITT_TSEG2 12
> > +#define BIT_IF1_MCONT_RXIE 10
> > +#define BIT_IF2_MCONT_TXIE 11
> > +#define BIT_BRPE_BRPE 6
> > +#define BIT_ES_TXERRCNT 0
> > +#define BIT_ES_RXERRCNT 8
>
> these are usually called SHIFT
I agree. Is the below TRUE ?
e.g.#define PCH_SHIFT_BITT_BRP 0
>
> > +#define MSK_BITT_BRP 0x3f
> > +#define MSK_BITT_SJW 0xc0
> > +#define MSK_BITT_TSEG1 0xf00
> > +#define MSK_BITT_TSEG2 0x7000
> > +#define MSK_BRPE_BRPE 0x3c0
> > +#define MSK_BRPE_GET 0x0f
> > +#define MSK_CTRL_IE_SIE_EIE 0x07
> > +#define MSK_MCONT_TXIE 0x08
> > +#define MSK_MCONT_RXIE 0x10
>
> MSK or MASK is okay, however the last two are just single bits.
>
> Please add a PCH_ prefix here, too.
I agree.
>
> > +#define PCH_CAN_NO_TX_BUFF 1
> > +#define COUNTER_LIMIT 10
>
> dito
I agree.
>
> > +
> > +#define PCH_CAN_CLK 50000000 /* 50MHz */
> > +
> > +/*
> > + * Define the number of message object.
> > + * PCH CAN communications are done via Message RAM.
> > + * The Message RAM consists of 32 message objects.
> > + */
> > +#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
> > +#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
> > +#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
>
> You define MAX_MSG_OBJ earlier, seems like two names for the same value.
In case, a use uses all message objects(=32), you are right.
But user does not alway use all message object.
>
> > +
> > +#define PCH_FIFO_THRESH 16
> > +
> > +enum pch_can_mode {
> > + PCH_CAN_ENABLE,
> > + PCH_CAN_DISABLE,
> > + PCH_CAN_ALL,
> > + PCH_CAN_NONE,
> > + PCH_CAN_STOP,
> > + PCH_CAN_RUN,
> > +};
> > +
> > +struct pch_can_regs {
> > + u32 cont;
> > + u32 stat;
> > + u32 errc;
> > + u32 bitt;
> > + u32 intr;
> > + u32 opt;
> > + u32 brpe;
> > + u32 reserve1;
>
> VVVV
> > + u32 if1_creq;
> > + u32 if1_cmask;
> > + u32 if1_mask1;
> > + u32 if1_mask2;
> > + u32 if1_id1;
> > + u32 if1_id2;
> > + u32 if1_mcont;
> > + u32 if1_dataa1;
> > + u32 if1_dataa2;
> > + u32 if1_datab1;
> > + u32 if1_datab2;
> ^^^^
>
> these registers and....
>
> > + u32 reserve2;
> > + u32 reserve3[12];
>
> ...and these
>
> VVVV
> > + u32 if2_creq;
> > + u32 if2_cmask;
> > + u32 if2_mask1;
> > + u32 if2_mask2;
> > + u32 if2_id1;
> > + u32 if2_id2;
> > + u32 if2_mcont;
> > + u32 if2_dataa1;
> > + u32 if2_dataa2;
> > + u32 if2_datab1;
> > + u32 if2_datab2;
>
> ^^^^
>
> ...are identical. I suggest to make a struct defining a complete
> "Message Interface Register Set". If you include the correct number of
> reserved bytes in the struct, you can have an array of two of these
> structs in the struct pch_can_regs.
To me, IMHOHO, it looks insignificant point.
Please show the merit ?
>
> > + u32 reserve4;
> > + u32 reserve5[20];
> > + u32 treq1;
> > + u32 treq2;
> > + u32 reserve6[2];
> > + u32 reserve7[56];
> > + u32 reserve8[3];
> > + u32 srst;
> > +};
> > +
> > +struct pch_can_priv {
> > + struct can_priv can;
> > + struct pci_dev *dev;
> > + unsigned int tx_enable[MAX_MSG_OBJ];
> > + unsigned int rx_enable[MAX_MSG_OBJ];
> > + unsigned int rx_link[MAX_MSG_OBJ];
> > + unsigned int int_enables;
> > + unsigned int int_stat;
> > + struct net_device *ndev;
> > + spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
> ^^^
> please add a whitespace
I agree.
>
> > + unsigned int msg_obj[MAX_MSG_OBJ];
> > + struct pch_can_regs __iomem *regs;
> > + struct napi_struct napi;
> > + unsigned int tx_obj; /* Point next Tx Obj index */
> > + unsigned int use_msi;
> > +};
> > +
> > +static struct can_bittiming_const pch_can_bittiming_const = {
> > + .name = "pch_can",
> > + .tseg1_min = 1,
> > + .tseg1_max = 16,
> > + .tseg2_min = 1,
> > + .tseg2_max = 8,
> > + .sjw_max = 4,
> > + .brp_min = 1,
> > + .brp_max = 1024, /* 6bit + extended 4bit */
> > + .brp_inc = 1,
> > +};
> > +
> > +static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
> > + {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
> > + {0,}
> > +};
> > +MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
> > +
> > +static inline void pch_can_bit_set(u32 *addr, u32 mask)
> ^^^^^
>
> that should be an void __iomem *, see mail I've send the other day.
> Please use sparse to check for this kinds of errors.
> (Compile the driver with C=2, i.e.: make drivers/net/can/pch_can.ko C=2)
>
I agree.
> > +{
> > + iowrite32(ioread32(addr) | mask, addr);
> > +}
> > +
> > +static inline void pch_can_bit_clear(u32 *addr, u32 mask)
> ^^^^^
>
> dito
I agree.
>
> > +{
> > + iowrite32(ioread32(addr) & ~mask, addr);
> > +}
> > +
> > +static void pch_can_set_run_mode(struct pch_can_priv *priv,
> > + enum pch_can_mode mode)
> > +{
> > + switch (mode) {
> > + case PCH_CAN_RUN:
> > + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
> > + break;
> > +
> > + case PCH_CAN_STOP:
> > + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
> > + break;
> > +
> > + default:
> > + dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
> > + break;
> > + }
> > +}
> > +
> > +static void pch_can_set_optmode(struct pch_can_priv *priv)
> > +{
> > + u32 reg_val = ioread32(&priv->regs->opt);
> > +
> > + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
> > + reg_val |= CAN_OPT_SILENT;
> > +
> > + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
> > + reg_val |= CAN_OPT_LBACK;
> > +
> > + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
> > + iowrite32(reg_val, &priv->regs->opt);
> > +}
> > +
>
> IMHO the function name is missleading, if I understand the code
> correctly, this functions triggers the transmission of the message.
> After this it checks for busy,
Yes, your understanding is TRUE.
> but
>
> > +static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
> ^^^^
>
Yes, me too.
I will rename the function name.
How about "pch_can_rw_msg_obj"
> that should probaby be a void
What't the above mean ?
pch_can_check_if_busy is already "void" function.
>
> > +{
> > + u32 counter = COUNTER_LIMIT;
> > + u32 ifx_creq;
> > +
> > + iowrite32(num, creq_addr);
> > + while (counter) {
> > + ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
> > + if (!ifx_creq)
> > + break;
> > + counter--;
> > + udelay(1);
> > + }
> > + if (!counter)
> > + pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
> > +}
> > +
> > +static void pch_can_set_int_enables(struct pch_can_priv *priv,
> > + enum pch_can_mode interrupt_no)
> > +{
> > + switch (interrupt_no) {
> > + case PCH_CAN_ENABLE:
> > + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
>
> noone uses this case.
I agree.
>
> > + break;
> > +
> > + case PCH_CAN_DISABLE:
> > + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
> > + break;
> > +
> > + case PCH_CAN_ALL:
> > + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> > + break;
> > +
> > + case PCH_CAN_NONE:
> > + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> > + break;
> > +
> > + default:
> > + dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
> > + break;
> > + }
> > +}
> > +
> > +static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
> > + int set)
> > +{
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + /* Reading the receive buffer data from RAM to Interface1 registers */
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
> > +
> > + /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
> > + &priv->regs->if1_cmask);
> > +
> > + if (set == 1) {
> > + /* Setting the MsgVal and RxIE bits */
> > + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
> > + pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
> > +
> > + } else if (set == 0) {
> > + /* Resetting the MsgVal and RxIE bits */
> > + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
> > + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
> > + }
> > +
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +}
> > +
> > +static void pch_can_rx_enable_all(struct pch_can_priv *priv)
> > +{
> > + int i;
> > +
> > + /* Traversing to obtain the object configured as receivers. */
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
> > + pch_can_set_rx_enable(priv, i, 1);
> > +}
> > +
> > +static void pch_can_rx_disable_all(struct pch_can_priv *priv)
> > +{
> > + int i;
> > +
> > + /* Traversing to obtain the object configured as receivers. */
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
> > + pch_can_set_rx_enable(priv, i, 0);
> > +}
> > +
> > +static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
> > + u32 set)
> > +{
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + /* Reading the Msg buffer from Message RAM to Interface2 registers. */
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> > + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
> > +
> > + /* Setting the IF2CMASK register for accessing the
> > + MsgVal and TxIE bits */
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
> > + &priv->regs->if2_cmask);
> > +
> > + if (set == 1) {
> > + /* Setting the MsgVal and TxIE bits */
> > + pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
> > + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
> > + } else if (set == 0) {
> > + /* Resetting the MsgVal and TxIE bits. */
> > + pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
> > + pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
> > + }
> > +
> > + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +}
> > +
> > +static void pch_can_tx_enable_all(struct pch_can_priv *priv)
> > +{
> > + int i;
> > +
> > + /* Traversing to obtain the object configured as transmit object. */
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
> > + pch_can_set_tx_enable(priv, i, 1);
> > +}
> > +
> > +static void pch_can_tx_disable_all(struct pch_can_priv *priv)
> > +{
> > + int i;
> > +
> > + /* Traversing to obtain the object configured as transmit object. */
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
> > + pch_can_set_tx_enable(priv, i, 0);
> > +}
> > +
> > +static int pch_can_int_pending(struct pch_can_priv *priv)
> ^^^
>
> make it u32 as it returns a register value, or a u16 as you only use
> the 16 lower bits.
I agree. I will modify to u32.
>
> > +{
> > + return ioread32(&priv->regs->intr) & 0xffff;
> > +}
> > +
> > +static void pch_can_clear_buffers(struct pch_can_priv *priv)
> > +{
> > + int i; /* Msg Obj ID (1~32) */
> > +
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
>
> IMHO the readability would be improved if you define something like
> PCH_RX_OBJ_START and PCH_RX_OBJ_END.
I agree.
>
> > + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
> > + iowrite32(0xffff, &priv->regs->if1_mask1);
> > + iowrite32(0xffff, &priv->regs->if1_mask2);
> > + iowrite32(0x0, &priv->regs->if1_id1);
> > + iowrite32(0x0, &priv->regs->if1_id2);
> > + iowrite32(0x0, &priv->regs->if1_mcont);
> > + iowrite32(0x0, &priv->regs->if1_dataa1);
> > + iowrite32(0x0, &priv->regs->if1_dataa2);
> > + iowrite32(0x0, &priv->regs->if1_datab1);
> > + iowrite32(0x0, &priv->regs->if1_datab2);
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
> > + CAN_CMASK_ARB | CAN_CMASK_CTRL,
> > + &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, i);
> > + }
> > +
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
> ^^^^^^^^^^^^^^^^^^
> dito for TX objects
I agree.
>
> > + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
> > + iowrite32(0xffff, &priv->regs->if2_mask1);
> > + iowrite32(0xffff, &priv->regs->if2_mask2);
> > + iowrite32(0x0, &priv->regs->if2_id1);
> > + iowrite32(0x0, &priv->regs->if2_id2);
> > + iowrite32(0x0, &priv->regs->if2_mcont);
> > + iowrite32(0x0, &priv->regs->if2_dataa1);
> > + iowrite32(0x0, &priv->regs->if2_dataa2);
> > + iowrite32(0x0, &priv->regs->if2_datab1);
> > + iowrite32(0x0, &priv->regs->if2_datab2);
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
> > + CAN_CMASK_CTRL, &priv->regs->if2_cmask);
> > + pch_can_check_if_busy(&priv->regs->if2_creq, i);
> > + }
> > +}
> > +
> > +static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
> > +{
> > + int i;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > +
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, i);
>
> If I understand the code correctly, the about function triggers a
> transfer. Why do you first trigger a transfer, then set the message contents....
For doing Read-Modify-Write.
As to fixed parameter of message object, it doesn't be modified every access.
We will modify to write only.
> > +
> > + iowrite32(0x0, &priv->regs->if1_id1);
> > + iowrite32(0x0, &priv->regs->if1_id2);
> > +
> > + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_UMASK);
>
> Why do you set the "Use acceptance mask" bit? We want to receive
> all can messages.
Without "Use acceptance mask" means received packet matched ID[28:0] only.
As a result, filter is enabled.
With "Use acceptance mask" and setting Msk[0:28]=all 1, all packets can be received(=No filter state)
>
> > +
> > + /* Set FIFO mode set to 0 except last Rx Obj*/
> > + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
> > + /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
> > + if (i == (PCH_RX_OBJ_NUM - 1))
> > + pch_can_bit_set(&priv->regs->if1_mcont,
> > + CAN_IF_MCONT_EOB);
>
> Make it if () { } else { }, please.
Sorry, I can't understand.
else {} is not necessary.
>
> > +
> > + iowrite32(0, &priv->regs->if1_mask1);
> > + pch_can_bit_clear(&priv->regs->if1_mask2,
> > + 0x1fff | CAN_MASK2_MDIR_MXTD);
> > +
> > + /* Setting CMASK for writing */
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
> > + CAN_CMASK_CTRL, &priv->regs->if1_cmask);
> > +
> > + pch_can_check_if_busy(&priv->regs->if1_creq, i);
>
> ...and then trigger the transfer again?
This means Read-Modify-Write.
>
> > + }
> > +
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> > + pch_can_check_if_busy(&priv->regs->if2_creq, i);
>
> same question about triggering the transfer 2 times applied here, too
ditto.
> > +
> > + /* Resetting DIR bit for reception */
> > + iowrite32(0x0, &priv->regs->if2_id1);
> > + iowrite32(0x0, &priv->regs->if2_id2);
> > + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
>
> Can you combine the two accesses to >if2_id2 into one?
I agree.
>
> > +
> > + /* Setting EOB bit for transmitter */
> > + iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
> > +
> > + pch_can_bit_set(&priv->regs->if2_mcont,
> > + CAN_IF_MCONT_UMASK);
>
> dito for if2_mcont
ditto.
>
> > +
> > + iowrite32(0, &priv->regs->if2_mask1);
> > + pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
> > +
> > + /* Setting CMASK for writing */
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
> > + CAN_CMASK_CTRL, &priv->regs->if2_cmask);
> > +
> > + pch_can_check_if_busy(&priv->regs->if2_creq, i);
> > + }
> > +
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +}
> > +
> > +static void pch_can_init(struct pch_can_priv *priv)
> > +{
> > + /* Stopping the Can device. */
> > + pch_can_set_run_mode(priv, PCH_CAN_STOP);
> > +
> > + /* Clearing all the message object buffers. */
> > + pch_can_clear_buffers(priv);
> > +
> > + /* Configuring the respective message object as either rx/tx object. */
> > + pch_can_config_rx_tx_buffers(priv);
> > +
> > + /* Enabling the interrupts. */
> > + pch_can_set_int_enables(priv, PCH_CAN_ALL);
> > +}
> > +
> > +static void pch_can_release(struct pch_can_priv *priv)
> > +{
> > + /* Stooping the CAN device. */
> > + pch_can_set_run_mode(priv, PCH_CAN_STOP);
> > +
> > + /* Disabling the interrupts. */
> > + pch_can_set_int_enables(priv, PCH_CAN_NONE);
> > +
> > + /* Disabling all the receive object. */
> > + pch_can_rx_disable_all(priv);
> > +
> > + /* Disabling all the transmit object. */
> > + pch_can_tx_disable_all(priv);
> > +}
> > +
> > +/* This function clears interrupt(s) from the CAN device. */
> > +static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
> > +{
> > + if (mask == CAN_STATUS_INT) {
>
> is this a valid case?
This "if" is always false.
I will delete this condition.
>
> > + ioread32(&priv->regs->stat);
> > + return;
> > + }
> > +
> > + /* Clear interrupt for transmit object */
> > + if ((mask >= 1) && (mask <= PCH_RX_OBJ_NUM)) {
> > + /* Setting CMASK for clearing the reception interrupts. */
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
> > + &priv->regs->if1_cmask);
> > +
> > + /* Clearing the Dir bit. */
> > + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
> > +
> > + /* Clearing NewDat & IntPnd */
> > + pch_can_bit_clear(&priv->regs->if1_mcont,
> > + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
> > +
> > + pch_can_check_if_busy(&priv->regs->if1_creq, mask);
> > + } else if ((mask > PCH_RX_OBJ_NUM) && (mask <= PCH_OBJ_NUM)) {
> > + /* Setting CMASK for clearing interrupts for
> > + frame transmission. */
>
> /*
> * this is the prefered style of multi line comments,
> * please adjust you comments
> */
I understand.
>
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
> > + &priv->regs->if2_cmask);
> > +
> > + /* Resetting the ID registers. */
> > + pch_can_bit_set(&priv->regs->if2_id2,
> > + CAN_ID2_DIR | (0x7ff << 2));
> > + iowrite32(0x0, &priv->regs->if2_id1);
> > +
> > + /* Claring NewDat, TxRqst & IntPnd */
> > + pch_can_bit_clear(&priv->regs->if2_mcont,
> > + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
> > + CAN_IF_MCONT_TXRQXT);
> > + pch_can_check_if_busy(&priv->regs->if2_creq, mask);
> > + }
> > +}
> > +
> > +static u32 pch_can_get_buffer_status(struct pch_can_priv *priv)
> > +{
> > + return (ioread32(&priv->regs->treq1) & 0xffff) |
> > + ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
>
> the second 0xffff is not needed, as the return value is u32 and you shift by 16.
I agree.
>
> > +}
> > +
> > +static void pch_can_reset(struct pch_can_priv *priv)
> > +{
> > + /* write to sw reset register */
> > + iowrite32(1, &priv->regs->srst);
> > + iowrite32(0, &priv->regs->srst);
> > +}
> > +
> > +static void pch_can_error(struct net_device *ndev, u32 status)
> > +{
> > + struct sk_buff *skb;
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + struct can_frame *cf;
> > + u32 errc;
> > + struct net_device_stats *stats = &(priv->ndev->stats);
> > + enum can_state state = priv->can.state;
> > +
> > + skb = alloc_can_err_skb(ndev, &cf);
> > + if (!skb)
> > + return;
> > +
> > + if (status & PCH_BUS_OFF) {
> > + pch_can_tx_disable_all(priv);
> > + pch_can_rx_disable_all(priv);
> > + state = CAN_STATE_BUS_OFF;
> > + cf->can_id |= CAN_ERR_BUSOFF;
> > + can_bus_off(ndev);
> > + }
> > +
> > + /* Warning interrupt. */
> > + if (status & PCH_EWARN) {
> > + state = CAN_STATE_ERROR_WARNING;
> > + priv->can.can_stats.error_warning++;
> > + cf->can_id |= CAN_ERR_CRTL;
> > + errc = ioread32(&priv->regs->errc);
> > + if (((errc & CAN_REC) >> 8) > 96)
> > + cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
> > + if ((errc & CAN_TEC) > 96)
> > + cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
> > + dev_warn(&ndev->dev,
> > + "%s -> Error Counter is more than 96.\n", __func__);
>
> Please use just "debug" level not warning here. Consider to use
> netdev_dbg() instead. IMHO the __func__ can be dropped and the
> "official" name for the error is "Error Warning".
I want to know the reason.
Why is it not dev_warn but netdev_dbg ?
>
> > + }
> > + /* Error passive interrupt. */
> > + if (status & PCH_EPASSIV) {
> > + priv->can.can_stats.error_passive++;
> > + state = CAN_STATE_ERROR_PASSIVE;
> > + cf->can_id |= CAN_ERR_CRTL;
> > + errc = ioread32(&priv->regs->errc);
> > + if (((errc & CAN_REC) >> 8) > 127)
> > + cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
> > + if ((errc & CAN_TEC) > 127)
> > + cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
> > + dev_err(&ndev->dev,
> > + "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
>
> dito
ditto
>
> > + }
> > +
> > + if (status & PCH_LEC_ALL) {
> > + priv->can.can_stats.bus_error++;
> > + stats->rx_errors++;
> > + switch (status & PCH_LEC_ALL) {
>
> I suggest to convert to a if-bit-set because there might be more than
> one bit set.
I agree.
>
> > + case PCH_STUF_ERR:
> > + cf->data[2] |= CAN_ERR_PROT_STUFF;
> > + break;
> > + case PCH_FORM_ERR:
> > + cf->data[2] |= CAN_ERR_PROT_FORM;
> > + break;
> > + case PCH_ACK_ERR:
> > + cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
> > + CAN_ERR_PROT_LOC_ACK_DEL;
> > + break;
> > + case PCH_BIT1_ERR:
> > + case PCH_BIT0_ERR:
> > + cf->data[2] |= CAN_ERR_PROT_BIT;
> > + break;
> > + case PCH_CRC_ERR:
> > + cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
> > + CAN_ERR_PROT_LOC_CRC_DEL;
> > + break;
> > + default:
> > + iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
> > + break;
> > + }
> > +
> > + }
> > +
> > + priv->can.state = state;
> > + netif_receive_skb(skb);
> > +
> > + stats->rx_packets++;
> > + stats->rx_bytes += cf->can_dlc;
> > +}
> > +
> > +static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
> > +{
> > + struct net_device *ndev = (struct net_device *)dev_id;
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > +
> > + pch_can_set_int_enables(priv, PCH_CAN_NONE);
> > + napi_schedule(&priv->napi);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
> > +{
> > + if (obj_id < PCH_FIFO_THRESH) {
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
> > + CAN_CMASK_ARB, &priv->regs->if1_cmask);
> > +
> > + /* Clearing the Dir bit. */
> > + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
> > +
> > + /* Clearing NewDat & IntPnd */
> > + pch_can_bit_clear(&priv->regs->if1_mcont,
> > + CAN_IF_MCONT_INTPND);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
> > + } else if (obj_id > PCH_FIFO_THRESH) {
> > + pch_can_int_clr(priv, obj_id);
> > + } else if (obj_id == PCH_FIFO_THRESH) {
> > + int cnt;
> > + for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
> > + pch_can_int_clr(priv, cnt+1);
> > + }
> > +}
> > +
> > +static int pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + struct net_device_stats *stats = &(priv->ndev->stats);
> > + struct sk_buff *skb;
> > + struct can_frame *cf;
> > +
> > + dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
> > + pch_can_bit_clear(&priv->regs->if1_mcont,
> > + CAN_IF_MCONT_MSGLOST);
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
> > + &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
> > +
> > + skb = alloc_can_err_skb(ndev, &cf);
> > + if (!skb)
> > + return -ENOMEM;
> > +
> > + priv->can.can_stats.error_passive++;
> > + priv->can.state = CAN_STATE_ERROR_PASSIVE;
> > + cf->can_id |= CAN_ERR_CRTL;
> > + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
> > + stats->rx_over_errors++;
> > + stats->rx_errors++;
> > +
> > + netif_receive_skb(skb);
> > +
> > + return 0;
> > +}
> > +
> > +static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
> > +{
> > + u32 reg;
> > + canid_t id;
> > + u32 ide;
> > + u32 rtr;
> > + int rcv_pkts = 0;
> > + int rtn;
> > + int next_flag = 0;
> > + struct sk_buff *skb;
> > + struct can_frame *cf;
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + struct net_device_stats *stats = &(priv->ndev->stats);
> > +
> > + /* Reading the messsage object from the Message RAM */
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, obj_num);
> > +
> > + /* Reading the MCONT register. */
> > + reg = ioread32(&priv->regs->if1_mcont);
> > + reg &= 0xffff;
> > +
> > + for (; (!(reg & CAN_IF_MCONT_EOB)) && (quota > 0);
> > + obj_num++, next_flag = 0) {
> > + /* If MsgLost bit set. */
> > + if (reg & CAN_IF_MCONT_MSGLOST) {
> > + rtn = pch_can_rx_msg_lost(ndev, obj_num);
> > + if (!rtn)
> > + return rtn;
> > + rcv_pkts++;
> > + quota--;
> > + next_flag = 1;
> > + } else if (!(reg & CAN_IF_MCONT_NEWDAT))
> > + next_flag = 1;
> > +
>
> after rearanging the code (see below..) you should be able to use a continue here.
>
> > + if (!next_flag) {
> > + skb = alloc_can_skb(priv->ndev, &cf);
> > + if (!skb)
> > + return -ENOMEM;
> > +
> > + /* Get Received data */
> > + ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD);
> > + if (ide) {
> > + id = (ioread32(&priv->regs->if1_id1) & 0xffff);
> > + id |= (((ioread32(&priv->regs->if1_id2)) &
> > + 0x1fff) << 16);
> > + cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
> ^^^^^^^^^^^^^^^^^
>
> is the mask needed, you mask the if1_id{1,2} already
I will delete
>
> > + } else {
> > + id = (((ioread32(&priv->regs->if1_id2)) &
> > + (CAN_SFF_MASK << 2)) >> 2);
> > + cf->can_id = (id & CAN_SFF_MASK);
>
> one mask can go away
I agree.
>
> > + }
> > +
> > + rtr = ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR;
> ^^
>
> remove one space
I agree.
>
> > +
> > + if (rtr)
> > + cf->can_id |= CAN_RTR_FLAG;
> > +
> > + cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
> > + if1_mcont)) & 0xF);
> > + *(u16 *)(cf->data + 0) = ioread16(&priv->regs->
> > + if1_dataa1);
> > + *(u16 *)(cf->data + 2) = ioread16(&priv->regs->
> > + if1_dataa2);
> > + *(u16 *)(cf->data + 4) = ioread16(&priv->regs->
> > + if1_datab1);
> > + *(u16 *)(cf->data + 6) = ioread16(&priv->regs->
> > + if1_datab2);
>
> are you sure, the bytes in the can package a in the correct order.
> Please test your pch_can against a non pch_can system.
Unfortunately, we don't have non pch_can system.
>
> > +
> > + netif_receive_skb(skb);
> > + rcv_pkts++;
> > + stats->rx_packets++;
> > + quota--;
> > + stats->rx_bytes += cf->can_dlc;
> > +
> > + pch_fifo_thresh(priv, obj_num);
> > + }
> > +
> > + /* Reading the messsage object from the Message RAM */
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, obj_num + 1);
> > + reg = ioread32(&priv->regs->if1_mcont);
>
> this is almost the same code as before the the loop, can you rearange
> the code to avoid duplication?
I agree.
>
> > + }
> > +
> > + return rcv_pkts;
> > +}
> > +
> > +static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + struct net_device_stats *stats = &(priv->ndev->stats);
> > + unsigned long flags;
> > + u32 dlc;
> > +
> > + can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
> > + &priv->regs->if2_cmask);
> > + dlc = ioread32(&priv->regs->if2_mcont) & CAN_IF_MCONT_DLC;
> > + pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > + if (dlc > 8)
> > + dlc = 8;
>
> use get_can_dlc
I agree.
>
> > + stats->tx_bytes += dlc;
> > + stats->tx_packets++;
> > +}
> > +
> > +static int pch_can_rx_poll(struct napi_struct *napi, int quota)
> > +{
> > + struct net_device *ndev = napi->dev;
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + u32 int_stat;
> > + int rcv_pkts = 0;
> > + u32 reg_stat;
> > + unsigned long flags;
> > +
> > + int_stat = pch_can_int_pending(priv);
> > + if (!int_stat)
> > + goto END;
> > +
> > + if ((int_stat == CAN_STATUS_INT) && (quota > 0)) {
> > + reg_stat = ioread32(&priv->regs->stat);
> > + if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
> > + if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
> > + pch_can_error(ndev, reg_stat);
> > + quota--;
> > + }
> > + }
> > +
> > + if (reg_stat & PCH_TX_OK) {
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> > + pch_can_check_if_busy(&priv->regs->if2_creq,
> > + ioread32(&priv->regs->intr));
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Isn't this "int_stat". Might it be possilbe that regs->intr changes
> between the pch_can_int_pending and here?
This code was mistake.
This condition, message object is not acccessed.
Thus, pch_can_check_if_busy can be deleted.
>
> What should this transfer do?
>
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > + pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
> > + }
> > +
> > + if (reg_stat & PCH_RX_OK)
> > + pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
> > +
> > + int_stat = pch_can_int_pending(priv);
> > + }
> > +
> > + if (quota == 0)
> > + goto END;
> > +
> > + if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > + quota -= rcv_pkts;
> > + if (rcv_pkts < 0)
>
> how can this happen?
My mistake.
if (quota < 0) is TRUE.
>
> > + goto END;
> > + } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
> > + /* Handle transmission interrupt */
> > + pch_can_tx_complete(ndev, int_stat);
> > + }
> > +
> > +END:
> > + napi_complete(napi);
> > + pch_can_set_int_enables(priv, PCH_CAN_ALL);
> > +
> > + return rcv_pkts;
> > +}
> > +
> > +static int pch_set_bittiming(struct net_device *ndev)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + const struct can_bittiming *bt = &priv->can.bittiming;
> > + u32 canbit;
> > + u32 bepe;
> > +
> > + /* Setting the CCE bit for accessing the Can Timing register. */
> > + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
> > +
> > + canbit = (bt->brp - 1) & MSK_BITT_BRP;
> > + canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
> > + canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
> > + canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
> > + bepe = ((bt->brp - 1) & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
> > + iowrite32(canbit, &priv->regs->bitt);
> > + iowrite32(bepe, &priv->regs->brpe);
> > + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
> > +
> > + return 0;
> > +}
> > +
> > +static void pch_can_start(struct net_device *ndev)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > +
> > + if (priv->can.state != CAN_STATE_STOPPED)
> > + pch_can_reset(priv);
> > +
> > + pch_set_bittiming(ndev);
> > + pch_can_set_optmode(priv);
> > +
> > + pch_can_tx_enable_all(priv);
> > + pch_can_rx_enable_all(priv);
> > +
> > + /* Setting the CAN to run mode. */
> > + pch_can_set_run_mode(priv, PCH_CAN_RUN);
> > +
> > + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> > +
> > + return;
> > +}
> > +
> > +static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
> > +{
> > + int ret = 0;
> > +
> > + switch (mode) {
> > + case CAN_MODE_START:
> > + pch_can_start(ndev);
> > + netif_wake_queue(ndev);
> > + break;
> > + default:
> > + ret = -EOPNOTSUPP;
> > + break;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int pch_can_open(struct net_device *ndev)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + int retval;
> > +
> > + /* Regsitering the interrupt. */
> > + retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
> > + ndev->name, ndev);
> > + if (retval) {
> > + dev_err(&ndev->dev, "request_irq failed.\n");
> > + goto req_irq_err;
> > + }
> > +
> > + /* Open common can device */
> > + retval = open_candev(ndev);
> > + if (retval) {
> > + dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
> > + goto err_open_candev;
> > + }
> > +
> > + pch_can_init(priv);
> > + pch_can_start(ndev);
> > + napi_enable(&priv->napi);
> > + netif_start_queue(ndev);
> > +
> > + return 0;
> > +
> > +err_open_candev:
> > + free_irq(priv->dev->irq, ndev);
> > +req_irq_err:
> > + pch_can_release(priv);
> > +
> > + return retval;
> > +}
> > +
> > +static int pch_close(struct net_device *ndev)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > +
> > + netif_stop_queue(ndev);
> > + napi_disable(&priv->napi);
> > + pch_can_release(priv);
> > + free_irq(priv->dev->irq, ndev);
> > + close_candev(ndev);
> > + priv->can.state = CAN_STATE_STOPPED;
> > + return 0;
> > +}
> > +
> > +static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
> > +{
> > + unsigned long flags;
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > + struct can_frame *cf = (struct can_frame *)skb->data;
> > + int tx_buffer_avail = 0;
>
> What I'm totally missing is the TX flow controll. Your driver has to
> ensure that the package leave the controller in the order that come
> into the xmit function. Further you have to stop your xmit queue if
> you're out of tx objects and reenable if you have a object free.
>
> Use netif_stop_queue() and netif_wake_queue() for this.
In this code, I think "out of tx objects" cannot be occurred.
Nevertheless, are netif_stop_queue() and netif_wake_queue() is necessary ?
>
> > +
> > + if (can_dropped_invalid_skb(ndev, skb))
> > + return NETDEV_TX_OK;
> > +
> > + if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj + 1 */
> > + while (ioread32(&priv->regs->treq2) & 0xfc00)
> > + udelay(1);
>
> please no (possible) infinite delays!
I will add break processing.
>
> > + priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
> > + }
>
> > +
> > + tx_buffer_avail = priv->tx_obj;
>
> why has the "object" become a "buffer" now? :)
You are right.
I will modify the name.
>
> > + priv->tx_obj++;
> > +
> > + /* Attaining the lock. */
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > +
> > + /* Setting the CMASK register to set value*/
> ^^^
>
> pleas add a whitespace
I agree.
>
> > + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
> > +
> > + /* If ID extended is set. */
> > + if (cf->can_id & CAN_EFF_FLAG) {
> > + iowrite32(cf->can_id & 0xffff, &priv->regs->if2_id1);
> > + iowrite32(((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD,
> > + &priv->regs->if2_id2);
> > + } else {
> > + iowrite32(0, &priv->regs->if2_id1);
> > + iowrite32((cf->can_id & CAN_SFF_MASK) << 2,
> > + &priv->regs->if2_id2);
> > + }
> > +
> > + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
>
> Do you need to do a read-modify-write of the hardware register? Please
> prepare the values you want to write to hardware, then do it.
Current design policy for read/write message object,
the driver is designed with Read-Modify-Write.
I will modify to Write only for reducing accessing Message RAM.
>
> > +
> > + /* If remote frame has to be transmitted.. */
> > + if (!(cf->can_id & CAN_RTR_FLAG))
> > + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
> dito
> > + /* If remote frame has to be transmitted.. */
> > + if (cf->can_id & CAN_RTR_FLAG)
> > + pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
> dito
> > +
> > + /* Copy data to register */
> > + if (cf->can_dlc > 0) {
> > + u32 data1 = *((u16 *)&cf->data[0]);
> > + iowrite32(data1, &priv->regs->if2_dataa1);
>
> do you think you send the bytes in correct order?
Let me study this endianess.
>
> > + }
> > + if (cf->can_dlc > 2) {
> > + u32 data1 = *((u16 *)&cf->data[2]);
> > + iowrite32(data1, &priv->regs->if2_dataa2);
> > + }
> > + if (cf->can_dlc > 4) {
> > + u32 data1 = *((u16 *)&cf->data[4]);
> > + iowrite32(data1, &priv->regs->if2_datab1);
> > + }
> > + if (cf->can_dlc > 6) {
> > + u32 data1 = *((u16 *)&cf->data[6]);
> > + iowrite32(data1, &priv->regs->if2_datab2);
> > + }
> > +
> > + can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
> > +
> > + /* Set the size of the data. */
> > + iowrite32(cf->can_dlc, &priv->regs->if2_mcont);
> > +
> > + /* Update if2_mcont */
> > + pch_can_bit_set(&priv->regs->if2_mcont,
> > + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT |
> > + CAN_IF_MCONT_TXIE);
>
> pleae first perpare your value, then write to hardware.
ditto.
>
> > +
> > + if (tx_buffer_avail == PCH_RX_OBJ_NUM) /* If points tail of FIFO */
> > + pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_EOB);
>
> dito
>
> Is EOB relevant for TX objects?
This is mistake. No meaning for tx.
I will modify.
>
> > + pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +
> > + return NETDEV_TX_OK;
> > +}
> > +
> > +static const struct net_device_ops pch_can_netdev_ops = {
> > + .ndo_open = pch_can_open,
> > + .ndo_stop = pch_close,
> > + .ndo_start_xmit = pch_xmit,
> > +};
> > +
> > +static void __devexit pch_can_remove(struct pci_dev *pdev)
> > +{
> > + struct net_device *ndev = pci_get_drvdata(pdev);
> > + struct pch_can_priv *priv = netdev_priv(ndev);
> > +
> > + unregister_candev(priv->ndev);
> > + pci_iounmap(pdev, priv->regs);
> > + if (priv->use_msi)
> > + pci_disable_msi(priv->dev);
> > + pci_release_regions(pdev);
> > + pci_disable_device(pdev);
> > + pci_set_drvdata(pdev, NULL);
> > + free_candev(priv->ndev);
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static void pch_can_set_int_custom(struct pch_can_priv *priv)
> > +{
> > + /* Clearing the IE, SIE and EIE bits of Can control register. */
> > + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> > +
> > + /* Appropriately setting them. */
> > + pch_can_bit_set(&priv->regs->cont,
> > + ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
> > +}
> > +
> > +/* This function retrieves interrupt enabled for the CAN device. */
> > +static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
> > +{
> > + /* Obtaining the status of IE, SIE and EIE interrupt bits. */
> > + return (ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1;
> > +}
> > +
> > +static u32 pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num)
> > +{
> > + unsigned long flags;
> > + u32 enable;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
> > +
> > + if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
> > + ((ioread32(&priv->regs->if1_mcont)) &
> > + CAN_IF_MCONT_RXIE))
> > + enable = 1;
> > + else
> > + enable = 0;
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > + return enable;
> > +}
> > +
> > +static u32 pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num)
> > +{
> > + unsigned long flags;
> > + u32 enable;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > +
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> > + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
> > + if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
> > + ((ioread32(&priv->regs->if2_mcont)) &
> > + CAN_IF_MCONT_TXIE)) {
> > + enable = 1;
> > + } else {
> > + enable = 0;
> > + }
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +
> > + return enable;
> > +}
> > +
> > +static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
> > + u32 buffer_num, u32 set)
> > +{
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
> > + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
> > + if (set == 1)
> > + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
> > + else
> > + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
> > +
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > +}
> > +
> > +static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
> > +{
> > + unsigned long flags;
> > + u32 link;
> > +
> > + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> > + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> > + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
> > +
> > + if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
> > + link = 0;
> > + else
> > + link = 1;
> > + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> > + return link;
> > +}
> > +
> > +static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
> > +{
> > + int i;
> > + int retval;
> > + u32 buf_stat; /* Variable for reading the transmit buffer status. */
> > + u32 counter = COUNTER_LIMIT;
> > +
> > + struct net_device *dev = pci_get_drvdata(pdev);
> > + struct pch_can_priv *priv = netdev_priv(dev);
> > +
> > + /* Stop the CAN controller */
> > + pch_can_set_run_mode(priv, PCH_CAN_STOP);
> > +
> > + /* Indicate that we are aboutto/in suspend */
> > + priv->can.state = CAN_STATE_STOPPED;
> > +
> > + /* Waiting for all transmission to complete. */
> > + while (counter) {
> > + buf_stat = pch_can_get_buffer_status(priv);
> > + if (!buf_stat)
> > + break;
> > + counter--;
> > + udelay(1);
> > + }
> > + if (!counter)
> > + dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
> > +
> > + /* Save interrupt configuration and then disable them */
> > + priv->int_enables = pch_can_get_int_enables(priv);
> > + pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
> > +
> > + /* Save Tx buffer enable state */
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
> > + priv->tx_enable[i] = pch_can_get_tx_enable(priv, i);
> > +
> > + /* Disable all Transmit buffers */
> > + pch_can_tx_disable_all(priv);
> > +
> > + /* Save Rx buffer enable state */
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
> > + priv->rx_enable[i] = pch_can_get_rx_enable(priv, i);
> > + priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
> > + }
> > +
> > + /* Disable all Receive buffers */
> > + pch_can_rx_disable_all(priv);
> > + retval = pci_save_state(pdev);
> > + if (retval) {
> > + dev_err(&pdev->dev, "pci_save_state failed.\n");
> > + } else {
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > + pci_disable_device(pdev);
> > + pci_set_power_state(pdev, pci_choose_state(pdev, state));
> > + }
> > +
> > + return retval;
> > +}
> > +
> > +static int pch_can_resume(struct pci_dev *pdev)
> > +{
> > + int i;
> > + int retval;
> > + struct net_device *dev = pci_get_drvdata(pdev);
> > + struct pch_can_priv *priv = netdev_priv(dev);
> > +
> > + pci_set_power_state(pdev, PCI_D0);
> > + pci_restore_state(pdev);
> > + retval = pci_enable_device(pdev);
> > + if (retval) {
> > + dev_err(&pdev->dev, "pci_enable_device failed.\n");
> > + return retval;
> > + }
> > +
> > + pci_enable_wake(pdev, PCI_D3hot, 0);
> > +
> > + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> > +
> > + /* Disabling all interrupts. */
> > + pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
> > +
> > + /* Setting the CAN device in Stop Mode. */
> > + pch_can_set_run_mode(priv, PCH_CAN_STOP);
> > +
> > + /* Configuring the transmit and receive buffers. */
> > + pch_can_config_rx_tx_buffers(priv);
> > +
> > + /* Restore the CAN state */
> > + pch_set_bittiming(dev);
> > +
> > + /* Listen/Active */
> > + pch_can_set_optmode(priv);
> > +
> > + /* Enabling the transmit buffer. */
> > + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
> > + pch_can_set_tx_enable(priv, i, priv->tx_enable[i]);
> > +
> > + /* Configuring the receive buffer and enabling them. */
> > + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
> > + /* Restore buffer link */
> > + pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
> > +
> > + /* Restore buffer enables */
> > + pch_can_set_rx_enable(priv, i, priv->rx_enable[i]);
> > + }
> > +
> > + /* Enable CAN Interrupts */
> > + pch_can_set_int_custom(priv);
> > +
> > + /* Restore Run Mode */
> > + pch_can_set_run_mode(priv, PCH_CAN_RUN);
> > +
> > + return retval;
> > +}
> > +#else
> > +#define pch_can_suspend NULL
> > +#define pch_can_resume NULL
> > +#endif
> > +
> > +static int pch_can_get_berr_counter(const struct net_device *dev,
> > + struct can_berr_counter *bec)
> > +{
> > + struct pch_can_priv *priv = netdev_priv(dev);
> > +
> > + bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
> > + bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
> > +
> > + return 0;
> > +}
> > +
> > +static int __devinit pch_can_probe(struct pci_dev *pdev,
> > + const struct pci_device_id *id)
> > +{
> > + struct net_device *ndev;
> > + struct pch_can_priv *priv;
> > + int rc;
> > + void __iomem *addr;
> > +
> > + rc = pci_enable_device(pdev);
> > + if (rc) {
> > + dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
> > + goto probe_exit_endev;
> > + }
> > +
> > + rc = pci_request_regions(pdev, KBUILD_MODNAME);
> > + if (rc) {
> > + dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
> > + goto probe_exit_pcireq;
> > + }
> > +
> > + addr = pci_iomap(pdev, 1, 0);
> > + if (!addr) {
> > + rc = -EIO;
> > + dev_err(&pdev->dev, "Failed pci_iomap\n");
> > + goto probe_exit_ipmap;
> > + }
> > +
> > + ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
> > + if (!ndev) {
> > + rc = -ENOMEM;
> > + dev_err(&pdev->dev, "Failed alloc_candev\n");
> > + goto probe_exit_alloc_candev;
> > + }
> > +
> > + priv = netdev_priv(ndev);
> > + priv->ndev = ndev;
> > + priv->regs = addr;
> > + priv->dev = pdev;
> > + priv->can.bittiming_const = &pch_can_bittiming_const;
> > + priv->can.do_set_mode = pch_can_do_set_mode;
> > + priv->can.do_get_berr_counter = pch_can_get_berr_counter;
> > + priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
> > + CAN_CTRLMODE_LOOPBACK;
> > + priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
> > +
> > + ndev->irq = pdev->irq;
> > + ndev->flags |= IFF_ECHO;
> > +
> > + pci_set_drvdata(pdev, ndev);
> > + SET_NETDEV_DEV(ndev, &pdev->dev);
> > + ndev->netdev_ops = &pch_can_netdev_ops;
> > + priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
> > +
> > + netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
> > +
> > + rc = pci_enable_msi(priv->dev);
> > + if (rc) {
> > + dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
> > + priv->use_msi = 0;
> > + } else {
> > + dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
> > + priv->use_msi = 1;
> > + }
> > +
> > + rc = register_candev(ndev);
> > + if (rc) {
> > + dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
> > + goto probe_exit_reg_candev;
> > + }
> > +
> > + return 0;
> > +
> > +probe_exit_reg_candev:
> > + free_candev(ndev);
> > +probe_exit_alloc_candev:
> > + pci_iounmap(pdev, addr);
> > +probe_exit_ipmap:
> > + pci_release_regions(pdev);
> > +probe_exit_pcireq:
> > + pci_disable_device(pdev);
> > +probe_exit_endev:
> > + return rc;
> > +}
> > +
> > +static struct pci_driver pch_can_pcidev = {
> > + .name = "pch_can",
> > + .id_table = pch_pci_tbl,
> > + .probe = pch_can_probe,
> > + .remove = __devexit_p(pch_can_remove),
> > + .suspend = pch_can_suspend,
> > + .resume = pch_can_resume,
> > +};
> > +
> > +static int __init pch_can_pci_init(void)
> > +{
> > + return pci_register_driver(&pch_can_pcidev);
> > +}
> > +module_init(pch_can_pci_init);
> > +
> > +static void __exit pch_can_pci_exit(void)
> > +{
> > + pci_unregister_driver(&pch_can_pcidev);
> > +}
> > +module_exit(pch_can_pci_exit);
> > +
> > +MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_VERSION("0.94");
>
> cheers, Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Industrial Linux Solutions | Phone: +49-231-2826-924 |
> Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
> Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
>
>
Thanks, Tomoya(OKI SEMICONDUCTOR CO., LTD.)
^ permalink raw reply
* Re: [PATCH net-next-2.6 v2] can: Topcliff: PCH_CAN driver: Fix build warnings
From: Marc Kleine-Budde @ 2010-11-02 11:03 UTC (permalink / raw)
To: Tomoya MORINAGA
Cc: andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w, Masayuki Ohtake,
Samuel Ortiz, margie.foster-ral2JQCrhuEAvxtiuMwx3w,
netdev-u79uwXL29TY76Z2rM5mHXA, LKML,
socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
kok.howg.ewe-ral2JQCrhuEAvxtiuMwx3w, Wolfgang Grandegger,
joel.clark-ral2JQCrhuEAvxtiuMwx3w, David S. Miller,
Christian Pellegrin, qi.wang-ral2JQCrhuEAvxtiuMwx3w
In-Reply-To: <001701cb7a78$99e1fe20$66f8800a-a06+6cuVnkTSQfdrb5gaxUEOCMrvLtNR@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 57708 bytes --]
On 11/02/2010 11:27 AM, Tomoya MORINAGA wrote:
> On Saturday, October 30, 2010 1:23 AM, Marc Kleine-Budde wrote:
>
>>> The driver has already been merged. Please send incremental patches
>>> against david's net-2.6 branch.
>
> I agree.
>
>>
>> Here a review, find comments inline. Lets talk about my remarks, please
>> answer inline and don't delete the code.
>>
>> Can you please explain me your locking sheme? If I understand the
>> documenation correctly the two message interfaces can be used mutual.
>> And you use one for rx the other one for tx.
>
> I show our locking scheme.
> When CPU accesses MessageRAM via IF1, CPU protect until read-modify-write
> so that IF2 access not occurred, vice versa.
Why is that needed?
>
>>
>> Please use netdev_<level> instead of dev_<level> for debug.
>
> I agree.
>
>>
>>> --- /dev/null
>>> +++ b/drivers/net/can/pch_can.c
>>> @@ -0,0 +1,1436 @@
>>> +/*
>>> + * Copyright (C) 1999 - 2010 Intel Corporation.
>>> + * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation; version 2 of the License.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
>>> + */
>>> +
>>> +#include <linux/interrupt.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/sched.h>
>>> +#include <linux/pci.h>
>>> +#include <linux/init.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/types.h>
>>> +#include <linux/errno.h>
>>> +#include <linux/netdevice.h>
>>> +#include <linux/skbuff.h>
>>> +#include <linux/can.h>
>>> +#include <linux/can/dev.h>
>>> +#include <linux/can/error.h>
>>> +
>>> +#define MAX_MSG_OBJ 32
>>> +#define MSG_OBJ_RX 0 /* The receive message object flag. */
>>> +#define MSG_OBJ_TX 1 /* The transmit message object flag. */
>>> +
>>> +#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
>>> +#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
>>> +#define CAN_CTRL_IE_SIE_EIE 0x000e
>>> +#define CAN_CTRL_CCE 0x0040
>>> +#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
>>> +#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
>>> +#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
>>> +#define CAN_CMASK_RX_TX_SET 0x00f3
>>> +#define CAN_CMASK_RX_TX_GET 0x0073
>>> +#define CAN_CMASK_ALL 0xff
>>> +#define CAN_CMASK_RDWR 0x80
>>> +#define CAN_CMASK_ARB 0x20
>>> +#define CAN_CMASK_CTRL 0x10
>>> +#define CAN_CMASK_MASK 0x40
>>> +#define CAN_CMASK_NEWDAT 0x04
>>> +#define CAN_CMASK_CLRINTPND 0x08
>>> +
>>> +#define CAN_IF_MCONT_NEWDAT 0x8000
>>> +#define CAN_IF_MCONT_INTPND 0x2000
>>> +#define CAN_IF_MCONT_UMASK 0x1000
>>> +#define CAN_IF_MCONT_TXIE 0x0800
>>> +#define CAN_IF_MCONT_RXIE 0x0400
>>> +#define CAN_IF_MCONT_RMTEN 0x0200
>>> +#define CAN_IF_MCONT_TXRQXT 0x0100
>>> +#define CAN_IF_MCONT_EOB 0x0080
>>> +#define CAN_IF_MCONT_DLC 0x000f
>>> +#define CAN_IF_MCONT_MSGLOST 0x4000
>>> +#define CAN_MASK2_MDIR_MXTD 0xc000
>>> +#define CAN_ID2_DIR 0x2000
>>> +#define CAN_ID_MSGVAL 0x8000
>>> +
>>> +#define CAN_STATUS_INT 0x8000
>>> +#define CAN_IF_CREQ_BUSY 0x8000
>>> +#define CAN_ID2_XTD 0x4000
>>> +
>>> +#define CAN_REC 0x00007f00
>>> +#define CAN_TEC 0x000000ff
>>
>> A prefix for like PCH_ instead of CAN_ for all those define above would
>> be fine to avoid namespace clashes and/or confusion with the defines from the socketcan framework.
>>
>
> I agree.
>
>>> +
>>> +#define PCH_RX_OK 0x00000010
>>> +#define PCH_TX_OK 0x00000008
>>> +#define PCH_BUS_OFF 0x00000080
>>> +#define PCH_EWARN 0x00000040
>>> +#define PCH_EPASSIV 0x00000020
>>> +#define PCH_LEC0 0x00000001
>>> +#define PCH_LEC1 0x00000002
>>> +#define PCH_LEC2 0x00000004
>>
>> These are just single set bit, please use BIT()
>> Consider adding the name of the corresponding register to the define's
>> name.
>
> I agree.
>
>>
>>> +#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
>>> +#define PCH_STUF_ERR PCH_LEC0
>>> +#define PCH_FORM_ERR PCH_LEC1
>>> +#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
>>> +#define PCH_BIT1_ERR PCH_LEC2
>>> +#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
>>> +#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
>>> +
>>> +/* bit position of certain controller bits. */
>>> +#define BIT_BITT_BRP 0
>>> +#define BIT_BITT_SJW 6
>>> +#define BIT_BITT_TSEG1 8
>>> +#define BIT_BITT_TSEG2 12
>>> +#define BIT_IF1_MCONT_RXIE 10
>>> +#define BIT_IF2_MCONT_TXIE 11
>>> +#define BIT_BRPE_BRPE 6
>>> +#define BIT_ES_TXERRCNT 0
>>> +#define BIT_ES_RXERRCNT 8
>>
>> these are usually called SHIFT
>
> I agree. Is the below TRUE ?
> e.g.#define PCH_SHIFT_BITT_BRP 0
I would put the SHIFT at the end, YMMV
#define PCH_BIT_BRP_SHIFT
>
>>
>>> +#define MSK_BITT_BRP 0x3f
>>> +#define MSK_BITT_SJW 0xc0
>>> +#define MSK_BITT_TSEG1 0xf00
>>> +#define MSK_BITT_TSEG2 0x7000
>>> +#define MSK_BRPE_BRPE 0x3c0
>>> +#define MSK_BRPE_GET 0x0f
>>> +#define MSK_CTRL_IE_SIE_EIE 0x07
>>> +#define MSK_MCONT_TXIE 0x08
>>> +#define MSK_MCONT_RXIE 0x10
>>
>> MSK or MASK is okay, however the last two are just single bits.
>>
>> Please add a PCH_ prefix here, too.
>
> I agree.
>
>>
>>> +#define PCH_CAN_NO_TX_BUFF 1
>>> +#define COUNTER_LIMIT 10
>>
>> dito
>
> I agree.
>
>>
>>> +
>>> +#define PCH_CAN_CLK 50000000 /* 50MHz */
>>> +
>>> +/*
>>> + * Define the number of message object.
>>> + * PCH CAN communications are done via Message RAM.
>>> + * The Message RAM consists of 32 message objects.
>>> + */
>>> +#define PCH_RX_OBJ_NUM 26 /* 1~ PCH_RX_OBJ_NUM is Rx*/
>>> +#define PCH_TX_OBJ_NUM 6 /* PCH_RX_OBJ_NUM is RX ~ Tx*/
>>> +#define PCH_OBJ_NUM (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
>>
>> You define MAX_MSG_OBJ earlier, seems like two names for the same value.
>
> In case, a use uses all message objects(=32), you are right.
> But user does not alway use all message object.
No one will change these values if the driver isn't buggy. And it
doesn't make any sense to not use all objects.
>
>
>>
>>> +
>>> +#define PCH_FIFO_THRESH 16
>>> +
>>> +enum pch_can_mode {
>>> + PCH_CAN_ENABLE,
>>> + PCH_CAN_DISABLE,
>>> + PCH_CAN_ALL,
>>> + PCH_CAN_NONE,
>>> + PCH_CAN_STOP,
>>> + PCH_CAN_RUN,
>>> +};
>>> +
>>> +struct pch_can_regs {
>>> + u32 cont;
>>> + u32 stat;
>>> + u32 errc;
>>> + u32 bitt;
>>> + u32 intr;
>>> + u32 opt;
>>> + u32 brpe;
>>> + u32 reserve1;
>>
>> VVVV
>>> + u32 if1_creq;
>>> + u32 if1_cmask;
>>> + u32 if1_mask1;
>>> + u32 if1_mask2;
>>> + u32 if1_id1;
>>> + u32 if1_id2;
>>> + u32 if1_mcont;
>>> + u32 if1_dataa1;
>>> + u32 if1_dataa2;
>>> + u32 if1_datab1;
>>> + u32 if1_datab2;
>> ^^^^
>>
>> these registers and....
>>
>>> + u32 reserve2;
>>> + u32 reserve3[12];
>>
>> ...and these
>>
>> VVVV
>>> + u32 if2_creq;
>>> + u32 if2_cmask;
>>> + u32 if2_mask1;
>>> + u32 if2_mask2;
>>> + u32 if2_id1;
>>> + u32 if2_id2;
>>> + u32 if2_mcont;
>>> + u32 if2_dataa1;
>>> + u32 if2_dataa2;
>>> + u32 if2_datab1;
>>> + u32 if2_datab2;
>>
>> ^^^^
>>
>> ...are identical. I suggest to make a struct defining a complete
>> "Message Interface Register Set". If you include the correct number of
>> reserved bytes in the struct, you can have an array of two of these
>> structs in the struct pch_can_regs.
>
> To me, IMHOHO, it looks insignificant point.
> Please show the merit ?
See Wolfgangs comments. You can get rid of duplicated code....
>
>>
>>> + u32 reserve4;
>>> + u32 reserve5[20];
>>> + u32 treq1;
>>> + u32 treq2;
>>> + u32 reserve6[2];
>>> + u32 reserve7[56];
>>> + u32 reserve8[3];
>>> + u32 srst;
>>> +};
>>> +
>>> +struct pch_can_priv {
>>> + struct can_priv can;
>>> + struct pci_dev *dev;
>>> + unsigned int tx_enable[MAX_MSG_OBJ];
>>> + unsigned int rx_enable[MAX_MSG_OBJ];
>>> + unsigned int rx_link[MAX_MSG_OBJ];
>>> + unsigned int int_enables;
>>> + unsigned int int_stat;
>>> + struct net_device *ndev;
>>> + spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
>> ^^^
>> please add a whitespace
>
> I agree.
>
>>
>>> + unsigned int msg_obj[MAX_MSG_OBJ];
>>> + struct pch_can_regs __iomem *regs;
>>> + struct napi_struct napi;
>>> + unsigned int tx_obj; /* Point next Tx Obj index */
>>> + unsigned int use_msi;
>>> +};
>>> +
>>> +static struct can_bittiming_const pch_can_bittiming_const = {
>>> + .name = "pch_can",
>>> + .tseg1_min = 1,
>>> + .tseg1_max = 16,
>>> + .tseg2_min = 1,
>>> + .tseg2_max = 8,
>>> + .sjw_max = 4,
>>> + .brp_min = 1,
>>> + .brp_max = 1024, /* 6bit + extended 4bit */
>>> + .brp_inc = 1,
>>> +};
>>> +
>>> +static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
>>> + {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
>>> + {0,}
>>> +};
>>> +MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
>>> +
>>> +static inline void pch_can_bit_set(u32 *addr, u32 mask)
>> ^^^^^
>>
>> that should be an void __iomem *, see mail I've send the other day.
>> Please use sparse to check for this kinds of errors.
>> (Compile the driver with C=2, i.e.: make drivers/net/can/pch_can.ko C=2)
>>
>
> I agree.
>
>>> +{
>>> + iowrite32(ioread32(addr) | mask, addr);
>>> +}
>>> +
>>> +static inline void pch_can_bit_clear(u32 *addr, u32 mask)
>> ^^^^^
>>
>> dito
>
> I agree.
>
>>
>>> +{
>>> + iowrite32(ioread32(addr) & ~mask, addr);
>>> +}
>>> +
>>> +static void pch_can_set_run_mode(struct pch_can_priv *priv,
>>> + enum pch_can_mode mode)
>>> +{
>>> + switch (mode) {
>>> + case PCH_CAN_RUN:
>>> + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
>>> + break;
>>> +
>>> + case PCH_CAN_STOP:
>>> + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
>>> + break;
>>> +
>>> + default:
>>> + dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void pch_can_set_optmode(struct pch_can_priv *priv)
>>> +{
>>> + u32 reg_val = ioread32(&priv->regs->opt);
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
>>> + reg_val |= CAN_OPT_SILENT;
>>> +
>>> + if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
>>> + reg_val |= CAN_OPT_LBACK;
>>> +
>>> + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
>>> + iowrite32(reg_val, &priv->regs->opt);
>>> +}
>>> +
>>
>> IMHO the function name is missleading, if I understand the code
>> correctly, this functions triggers the transmission of the message.
>> After this it checks for busy,
>
> Yes, your understanding is TRUE.
>
>> but
>>
>>> +static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
>> ^^^^
>>
>
> Yes, me too.
> I will rename the function name.
>
> How about "pch_can_rw_msg_obj"
>
>> that should probaby be a void
> What't the above mean ?
> pch_can_check_if_busy is already "void" function.
>>> +static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
>> ^^^^
That u32 should be a void.
BTW: Does the Intel chip support x64? If so, have you tested the driver
on a 64 bit kernel.
>
>>
>>> +{
>>> + u32 counter = COUNTER_LIMIT;
>>> + u32 ifx_creq;
>>> +
>>> + iowrite32(num, creq_addr);
>>> + while (counter) {
>>> + ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
>>> + if (!ifx_creq)
>>> + break;
>>> + counter--;
>>> + udelay(1);
>>> + }
>>> + if (!counter)
>>> + pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
>>> +}
>>> +
>>> +static void pch_can_set_int_enables(struct pch_can_priv *priv,
>>> + enum pch_can_mode interrupt_no)
>>> +{
>>> + switch (interrupt_no) {
>>> + case PCH_CAN_ENABLE:
>>> + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
>>
>> noone uses this case.
>
> I agree.
>
>>
>>> + break;
>>> +
>>> + case PCH_CAN_DISABLE:
>>> + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
>>> + break;
>>> +
>>> + case PCH_CAN_ALL:
>>> + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
>>> + break;
>>> +
>>> + case PCH_CAN_NONE:
>>> + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
>>> + break;
>>> +
>>> + default:
>>> + dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
>>> + int set)
>>> +{
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + /* Reading the receive buffer data from RAM to Interface1 registers */
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
>>> +
>>> + /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
>>> + &priv->regs->if1_cmask);
>>> +
>>> + if (set == 1) {
>>> + /* Setting the MsgVal and RxIE bits */
>>> + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
>>> + pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
>>> +
>>> + } else if (set == 0) {
>>> + /* Resetting the MsgVal and RxIE bits */
>>> + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
>>> + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
>>> + }
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +}
>>> +
>>> +static void pch_can_rx_enable_all(struct pch_can_priv *priv)
>>> +{
>>> + int i;
>>> +
>>> + /* Traversing to obtain the object configured as receivers. */
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
>>> + pch_can_set_rx_enable(priv, i, 1);
>>> +}
>>> +
>>> +static void pch_can_rx_disable_all(struct pch_can_priv *priv)
>>> +{
>>> + int i;
>>> +
>>> + /* Traversing to obtain the object configured as receivers. */
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
>>> + pch_can_set_rx_enable(priv, i, 0);
>>> +}
>>> +
>>> +static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
>>> + u32 set)
>>> +{
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + /* Reading the Msg buffer from Message RAM to Interface2 registers. */
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
>>> +
>>> + /* Setting the IF2CMASK register for accessing the
>>> + MsgVal and TxIE bits */
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
>>> + &priv->regs->if2_cmask);
>>> +
>>> + if (set == 1) {
>>> + /* Setting the MsgVal and TxIE bits */
>>> + pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
>>> + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
>>> + } else if (set == 0) {
>>> + /* Resetting the MsgVal and TxIE bits. */
>>> + pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
>>> + pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
>>> + }
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +}
>>> +
>>> +static void pch_can_tx_enable_all(struct pch_can_priv *priv)
>>> +{
>>> + int i;
>>> +
>>> + /* Traversing to obtain the object configured as transmit object. */
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
>>> + pch_can_set_tx_enable(priv, i, 1);
>>> +}
>>> +
>>> +static void pch_can_tx_disable_all(struct pch_can_priv *priv)
>>> +{
>>> + int i;
>>> +
>>> + /* Traversing to obtain the object configured as transmit object. */
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
>>> + pch_can_set_tx_enable(priv, i, 0);
>>> +}
>>> +
>>> +static int pch_can_int_pending(struct pch_can_priv *priv)
>> ^^^
>>
>> make it u32 as it returns a register value, or a u16 as you only use
>> the 16 lower bits.
>
> I agree. I will modify to u32.
>
>>
>>> +{
>>> + return ioread32(&priv->regs->intr) & 0xffff;
>>> +}
>>> +
>>> +static void pch_can_clear_buffers(struct pch_can_priv *priv)
>>> +{
>>> + int i; /* Msg Obj ID (1~32) */
>>> +
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
>>
>> IMHO the readability would be improved if you define something like
>> PCH_RX_OBJ_START and PCH_RX_OBJ_END.
>
> I agree.
>
>>
>>> + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
>>> + iowrite32(0xffff, &priv->regs->if1_mask1);
>>> + iowrite32(0xffff, &priv->regs->if1_mask2);
>>> + iowrite32(0x0, &priv->regs->if1_id1);
>>> + iowrite32(0x0, &priv->regs->if1_id2);
>>> + iowrite32(0x0, &priv->regs->if1_mcont);
>>> + iowrite32(0x0, &priv->regs->if1_dataa1);
>>> + iowrite32(0x0, &priv->regs->if1_dataa2);
>>> + iowrite32(0x0, &priv->regs->if1_datab1);
>>> + iowrite32(0x0, &priv->regs->if1_datab2);
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
>>> + CAN_CMASK_ARB | CAN_CMASK_CTRL,
>>> + &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, i);
>>> + }
>>> +
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
>> ^^^^^^^^^^^^^^^^^^
>> dito for TX objects
>
> I agree.
>
>>
>>> + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
>>> + iowrite32(0xffff, &priv->regs->if2_mask1);
>>> + iowrite32(0xffff, &priv->regs->if2_mask2);
>>> + iowrite32(0x0, &priv->regs->if2_id1);
>>> + iowrite32(0x0, &priv->regs->if2_id2);
>>> + iowrite32(0x0, &priv->regs->if2_mcont);
>>> + iowrite32(0x0, &priv->regs->if2_dataa1);
>>> + iowrite32(0x0, &priv->regs->if2_dataa2);
>>> + iowrite32(0x0, &priv->regs->if2_datab1);
>>> + iowrite32(0x0, &priv->regs->if2_datab2);
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
>>> + CAN_CMASK_CTRL, &priv->regs->if2_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, i);
>>> + }
>>> +}
>>> +
>>> +static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
>>> +{
>>> + int i;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> +
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, i);
>>
>> If I understand the code correctly, the about function triggers a
>> transfer. Why do you first trigger a transfer, then set the message contents....
>
> For doing Read-Modify-Write.
> As to fixed parameter of message object, it doesn't be modified every access.
I see.
> We will modify to write only.
>
>>> +
>>> + iowrite32(0x0, &priv->regs->if1_id1);
>>> + iowrite32(0x0, &priv->regs->if1_id2);
>>> +
>>> + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_UMASK);
>>
>> Why do you set the "Use acceptance mask" bit? We want to receive
>> all can messages.
>
> Without "Use acceptance mask" means received packet matched ID[28:0] only.
> As a result, filter is enabled.
>
> With "Use acceptance mask" and setting Msk[0:28]=all 1, all packets can be received(=No filter state)
Thanks for the explenation.
>
>>
>>> +
>>> + /* Set FIFO mode set to 0 except last Rx Obj*/
>>> + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
>>> + /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
>>> + if (i == (PCH_RX_OBJ_NUM - 1))
>>> + pch_can_bit_set(&priv->regs->if1_mcont,
>>> + CAN_IF_MCONT_EOB);
>>
>> Make it if () { } else { }, please.
>
> Sorry, I can't understand.
> else {} is not necessary.
Please look at the code block above, again. You frist clean the bit
unconditionally, then you set the bit in the if. Please make it:
if (last)
set_bit
else
clear_bit
>
>>
>>> +
>>> + iowrite32(0, &priv->regs->if1_mask1);
>>> + pch_can_bit_clear(&priv->regs->if1_mask2,
>>> + 0x1fff | CAN_MASK2_MDIR_MXTD);
>>> +
>>> + /* Setting CMASK for writing */
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
>>> + CAN_CMASK_CTRL, &priv->regs->if1_cmask);
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, i);
>>
>> ...and then trigger the transfer again?
>
> This means Read-Modify-Write.
ic
>
>>
>>> + }
>>> +
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, i);
>>
>> same question about triggering the transfer 2 times applied here, too
>
> ditto.
>
>>> +
>>> + /* Resetting DIR bit for reception */
>>> + iowrite32(0x0, &priv->regs->if2_id1);
>>> + iowrite32(0x0, &priv->regs->if2_id2);
>>> + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
>>
>> Can you combine the two accesses to >if2_id2 into one?
>
> I agree.
>
>>
>>> +
>>> + /* Setting EOB bit for transmitter */
>>> + iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
>>> +
>>> + pch_can_bit_set(&priv->regs->if2_mcont,
>>> + CAN_IF_MCONT_UMASK);
>>
>> dito for if2_mcont
>
> ditto.
>
>>
>>> +
>>> + iowrite32(0, &priv->regs->if2_mask1);
>>> + pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
>>> +
>>> + /* Setting CMASK for writing */
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK | CAN_CMASK_ARB |
>>> + CAN_CMASK_CTRL, &priv->regs->if2_cmask);
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, i);
>>> + }
>>> +
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +}
>>> +
>>> +static void pch_can_init(struct pch_can_priv *priv)
>>> +{
>>> + /* Stopping the Can device. */
>>> + pch_can_set_run_mode(priv, PCH_CAN_STOP);
>>> +
>>> + /* Clearing all the message object buffers. */
>>> + pch_can_clear_buffers(priv);
>>> +
>>> + /* Configuring the respective message object as either rx/tx object. */
>>> + pch_can_config_rx_tx_buffers(priv);
>>> +
>>> + /* Enabling the interrupts. */
>>> + pch_can_set_int_enables(priv, PCH_CAN_ALL);
>>> +}
>>> +
>>> +static void pch_can_release(struct pch_can_priv *priv)
>>> +{
>>> + /* Stooping the CAN device. */
>>> + pch_can_set_run_mode(priv, PCH_CAN_STOP);
>>> +
>>> + /* Disabling the interrupts. */
>>> + pch_can_set_int_enables(priv, PCH_CAN_NONE);
>>> +
>>> + /* Disabling all the receive object. */
>>> + pch_can_rx_disable_all(priv);
>>> +
>>> + /* Disabling all the transmit object. */
>>> + pch_can_tx_disable_all(priv);
>>> +}
>>> +
>>> +/* This function clears interrupt(s) from the CAN device. */
>>> +static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
>>> +{
>>> + if (mask == CAN_STATUS_INT) {
>>
>> is this a valid case?
>
> This "if" is always false.
> I will delete this condition.
>
>>
>>> + ioread32(&priv->regs->stat);
>>> + return;
>>> + }
>>> +
>>> + /* Clear interrupt for transmit object */
>>> + if ((mask >= 1) && (mask <= PCH_RX_OBJ_NUM)) {
>>> + /* Setting CMASK for clearing the reception interrupts. */
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
>>> + &priv->regs->if1_cmask);
>>> +
>>> + /* Clearing the Dir bit. */
>>> + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
>>> +
>>> + /* Clearing NewDat & IntPnd */
>>> + pch_can_bit_clear(&priv->regs->if1_mcont,
>>> + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, mask);
>>> + } else if ((mask > PCH_RX_OBJ_NUM) && (mask <= PCH_OBJ_NUM)) {
>>> + /* Setting CMASK for clearing interrupts for
>>> + frame transmission. */
>>
>> /*
>> * this is the prefered style of multi line comments,
>> * please adjust you comments
>> */
>
> I understand.
>
>>
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
>>> + &priv->regs->if2_cmask);
>>> +
>>> + /* Resetting the ID registers. */
>>> + pch_can_bit_set(&priv->regs->if2_id2,
>>> + CAN_ID2_DIR | (0x7ff << 2));
>>> + iowrite32(0x0, &priv->regs->if2_id1);
>>> +
>>> + /* Claring NewDat, TxRqst & IntPnd */
>>> + pch_can_bit_clear(&priv->regs->if2_mcont,
>>> + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
>>> + CAN_IF_MCONT_TXRQXT);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, mask);
>>> + }
>>> +}
>>> +
>>> +static u32 pch_can_get_buffer_status(struct pch_can_priv *priv)
>>> +{
>>> + return (ioread32(&priv->regs->treq1) & 0xffff) |
>>> + ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
>>
>> the second 0xffff is not needed, as the return value is u32 and you shift by 16.
>
> I agree.
>
>>
>>> +}
>>> +
>>> +static void pch_can_reset(struct pch_can_priv *priv)
>>> +{
>>> + /* write to sw reset register */
>>> + iowrite32(1, &priv->regs->srst);
>>> + iowrite32(0, &priv->regs->srst);
>>> +}
>>> +
>>> +static void pch_can_error(struct net_device *ndev, u32 status)
>>> +{
>>> + struct sk_buff *skb;
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + struct can_frame *cf;
>>> + u32 errc;
>>> + struct net_device_stats *stats = &(priv->ndev->stats);
>>> + enum can_state state = priv->can.state;
>>> +
>>> + skb = alloc_can_err_skb(ndev, &cf);
>>> + if (!skb)
>>> + return;
>>> +
>>> + if (status & PCH_BUS_OFF) {
>>> + pch_can_tx_disable_all(priv);
>>> + pch_can_rx_disable_all(priv);
>>> + state = CAN_STATE_BUS_OFF;
>>> + cf->can_id |= CAN_ERR_BUSOFF;
>>> + can_bus_off(ndev);
>>> + }
>>> +
>>> + /* Warning interrupt. */
>>> + if (status & PCH_EWARN) {
>>> + state = CAN_STATE_ERROR_WARNING;
>>> + priv->can.can_stats.error_warning++;
>>> + cf->can_id |= CAN_ERR_CRTL;
>>> + errc = ioread32(&priv->regs->errc);
>>> + if (((errc & CAN_REC) >> 8) > 96)
>>> + cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
>>> + if ((errc & CAN_TEC) > 96)
>>> + cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
>>> + dev_warn(&ndev->dev,
>>> + "%s -> Error Counter is more than 96.\n", __func__);
>>
>> Please use just "debug" level not warning here. Consider to use
>> netdev_dbg() instead. IMHO the __func__ can be dropped and the
>> "official" name for the error is "Error Warning".
>
> I want to know the reason.
> Why is it not dev_warn but netdev_dbg ?
If you use warning level it would end up on the console or and in the
syslog. It's quite complicated (for programs) to get information from
there. This is why we send CAN error frames. They hold the same
information but int a binary form, thus it's easier to process.
>
>>
>>> + }
>>> + /* Error passive interrupt. */
>>> + if (status & PCH_EPASSIV) {
>>> + priv->can.can_stats.error_passive++;
>>> + state = CAN_STATE_ERROR_PASSIVE;
>>> + cf->can_id |= CAN_ERR_CRTL;
>>> + errc = ioread32(&priv->regs->errc);
>>> + if (((errc & CAN_REC) >> 8) > 127)
>>> + cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
>>> + if ((errc & CAN_TEC) > 127)
>>> + cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
>>> + dev_err(&ndev->dev,
>>> + "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
>>
>> dito
>
> ditto
>
>>
>>> + }
>>> +
>>> + if (status & PCH_LEC_ALL) {
>>> + priv->can.can_stats.bus_error++;
>>> + stats->rx_errors++;
>>> + switch (status & PCH_LEC_ALL) {
>>
>> I suggest to convert to a if-bit-set because there might be more than
>> one bit set.
>
> I agree.
>
>>
>>> + case PCH_STUF_ERR:
>>> + cf->data[2] |= CAN_ERR_PROT_STUFF;
>>> + break;
>>> + case PCH_FORM_ERR:
>>> + cf->data[2] |= CAN_ERR_PROT_FORM;
>>> + break;
>>> + case PCH_ACK_ERR:
>>> + cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
>>> + CAN_ERR_PROT_LOC_ACK_DEL;
>>> + break;
>>> + case PCH_BIT1_ERR:
>>> + case PCH_BIT0_ERR:
>>> + cf->data[2] |= CAN_ERR_PROT_BIT;
>>> + break;
>>> + case PCH_CRC_ERR:
>>> + cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
>>> + CAN_ERR_PROT_LOC_CRC_DEL;
>>> + break;
>>> + default:
>>> + iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
>>> + break;
>>> + }
>>> +
>>> + }
>>> +
>>> + priv->can.state = state;
>>> + netif_receive_skb(skb);
>>> +
>>> + stats->rx_packets++;
>>> + stats->rx_bytes += cf->can_dlc;
>>> +}
>>> +
>>> +static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
>>> +{
>>> + struct net_device *ndev = (struct net_device *)dev_id;
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> +
>>> + pch_can_set_int_enables(priv, PCH_CAN_NONE);
>>> + napi_schedule(&priv->napi);
>>> +
>>> + return IRQ_HANDLED;
>>> +}
>>> +
>>> +static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
>>> +{
>>> + if (obj_id < PCH_FIFO_THRESH) {
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
>>> + CAN_CMASK_ARB, &priv->regs->if1_cmask);
>>> +
>>> + /* Clearing the Dir bit. */
>>> + pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
>>> +
>>> + /* Clearing NewDat & IntPnd */
>>> + pch_can_bit_clear(&priv->regs->if1_mcont,
>>> + CAN_IF_MCONT_INTPND);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
>>> + } else if (obj_id > PCH_FIFO_THRESH) {
>>> + pch_can_int_clr(priv, obj_id);
>>> + } else if (obj_id == PCH_FIFO_THRESH) {
>>> + int cnt;
>>> + for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
>>> + pch_can_int_clr(priv, cnt+1);
>>> + }
>>> +}
>>> +
>>> +static int pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + struct net_device_stats *stats = &(priv->ndev->stats);
>>> + struct sk_buff *skb;
>>> + struct can_frame *cf;
>>> +
>>> + dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
>>> + pch_can_bit_clear(&priv->regs->if1_mcont,
>>> + CAN_IF_MCONT_MSGLOST);
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
>>> + &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, obj_id);
>>> +
>>> + skb = alloc_can_err_skb(ndev, &cf);
>>> + if (!skb)
>>> + return -ENOMEM;
>>> +
>>> + priv->can.can_stats.error_passive++;
>>> + priv->can.state = CAN_STATE_ERROR_PASSIVE;
>>> + cf->can_id |= CAN_ERR_CRTL;
>>> + cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
>>> + stats->rx_over_errors++;
>>> + stats->rx_errors++;
>>> +
>>> + netif_receive_skb(skb);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
>>> +{
>>> + u32 reg;
>>> + canid_t id;
>>> + u32 ide;
>>> + u32 rtr;
>>> + int rcv_pkts = 0;
>>> + int rtn;
>>> + int next_flag = 0;
>>> + struct sk_buff *skb;
>>> + struct can_frame *cf;
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + struct net_device_stats *stats = &(priv->ndev->stats);
>>> +
>>> + /* Reading the messsage object from the Message RAM */
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, obj_num);
>>> +
>>> + /* Reading the MCONT register. */
>>> + reg = ioread32(&priv->regs->if1_mcont);
>>> + reg &= 0xffff;
>>> +
>>> + for (; (!(reg & CAN_IF_MCONT_EOB)) && (quota > 0);
>>> + obj_num++, next_flag = 0) {
>>> + /* If MsgLost bit set. */
>>> + if (reg & CAN_IF_MCONT_MSGLOST) {
>>> + rtn = pch_can_rx_msg_lost(ndev, obj_num);
>>> + if (!rtn)
>>> + return rtn;
>>> + rcv_pkts++;
>>> + quota--;
>>> + next_flag = 1;
>>> + } else if (!(reg & CAN_IF_MCONT_NEWDAT))
>>> + next_flag = 1;
>>> +
>>
>> after rearanging the code (see below..) you should be able to use a continue here.
>>
>>> + if (!next_flag) {
>>> + skb = alloc_can_skb(priv->ndev, &cf);
>>> + if (!skb)
>>> + return -ENOMEM;
>>> +
>>> + /* Get Received data */
>>> + ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD);
>>> + if (ide) {
>>> + id = (ioread32(&priv->regs->if1_id1) & 0xffff);
>>> + id |= (((ioread32(&priv->regs->if1_id2)) &
>>> + 0x1fff) << 16);
>>> + cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
>> ^^^^^^^^^^^^^^^^^
>>
>> is the mask needed, you mask the if1_id{1,2} already
>
> I will delete
>
>>
>>> + } else {
>>> + id = (((ioread32(&priv->regs->if1_id2)) &
>>> + (CAN_SFF_MASK << 2)) >> 2);
>>> + cf->can_id = (id & CAN_SFF_MASK);
>>
>> one mask can go away
>
> I agree.
>
>>
>>> + }
>>> +
>>> + rtr = ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR;
>> ^^
>>
>> remove one space
>
> I agree.
>
>>
>>> +
>>> + if (rtr)
>>> + cf->can_id |= CAN_RTR_FLAG;
>>> +
>>> + cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
>>> + if1_mcont)) & 0xF);
>>> + *(u16 *)(cf->data + 0) = ioread16(&priv->regs->
>>> + if1_dataa1);
>>> + *(u16 *)(cf->data + 2) = ioread16(&priv->regs->
>>> + if1_dataa2);
>>> + *(u16 *)(cf->data + 4) = ioread16(&priv->regs->
>>> + if1_datab1);
>>> + *(u16 *)(cf->data + 6) = ioread16(&priv->regs->
>>> + if1_datab2);
>>
>> are you sure, the bytes in the can package a in the correct order.
>> Please test your pch_can against a non pch_can system.
>
> Unfortunately, we don't have non pch_can system.
Have a look a the driver/net/can/usb subdir and buy one of those. It
really hard to find bugs if you test against your own driver.
>
>>
>>> +
>>> + netif_receive_skb(skb);
>>> + rcv_pkts++;
>>> + stats->rx_packets++;
>>> + quota--;
>>> + stats->rx_bytes += cf->can_dlc;
>>> +
>>> + pch_fifo_thresh(priv, obj_num);
>>> + }
>>> +
>>> + /* Reading the messsage object from the Message RAM */
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, obj_num + 1);
>>> + reg = ioread32(&priv->regs->if1_mcont);
>>
>> this is almost the same code as before the the loop, can you rearange
>> the code to avoid duplication?
>
> I agree.
>
>>
>>> + }
>>> +
>>> + return rcv_pkts;
>>> +}
>>> +
>>> +static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + struct net_device_stats *stats = &(priv->ndev->stats);
>>> + unsigned long flags;
>>> + u32 dlc;
>>> +
>>> + can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
>>> + &priv->regs->if2_cmask);
>>> + dlc = ioread32(&priv->regs->if2_mcont) & CAN_IF_MCONT_DLC;
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> + if (dlc > 8)
>>> + dlc = 8;
>>
>> use get_can_dlc
>
> I agree.
>
>>
>>> + stats->tx_bytes += dlc;
>>> + stats->tx_packets++;
>>> +}
>>> +
>>> +static int pch_can_rx_poll(struct napi_struct *napi, int quota)
>>> +{
>>> + struct net_device *ndev = napi->dev;
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + u32 int_stat;
>>> + int rcv_pkts = 0;
>>> + u32 reg_stat;
>>> + unsigned long flags;
>>> +
>>> + int_stat = pch_can_int_pending(priv);
>>> + if (!int_stat)
>>> + goto END;
>>> +
>>> + if ((int_stat == CAN_STATUS_INT) && (quota > 0)) {
>>> + reg_stat = ioread32(&priv->regs->stat);
>>> + if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
>>> + if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
>>> + pch_can_error(ndev, reg_stat);
>>> + quota--;
>>> + }
>>> + }
>>> +
>>> + if (reg_stat & PCH_TX_OK) {
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq,
>>> + ioread32(&priv->regs->intr));
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>> Isn't this "int_stat". Might it be possilbe that regs->intr changes
>> between the pch_can_int_pending and here?
>
> This code was mistake.
> This condition, message object is not acccessed.
> Thus, pch_can_check_if_busy can be deleted.
>
>>
>> What should this transfer do?
>>
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> + pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
>>> + }
>>> +
>>> + if (reg_stat & PCH_RX_OK)
>>> + pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
>>> +
>>> + int_stat = pch_can_int_pending(priv);
>>> + }
>>> +
>>> + if (quota == 0)
>>> + goto END;
>>> +
>>> + if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> + quota -= rcv_pkts;
>>> + if (rcv_pkts < 0)
>>
>> how can this happen?
>
> My mistake.
> if (quota < 0) is TRUE.
>
>
>>
>>> + goto END;
>>> + } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
>>> + /* Handle transmission interrupt */
>>> + pch_can_tx_complete(ndev, int_stat);
>>> + }
>>> +
>>> +END:
>>> + napi_complete(napi);
>>> + pch_can_set_int_enables(priv, PCH_CAN_ALL);
>>> +
>>> + return rcv_pkts;
>>> +}
>>> +
>>> +static int pch_set_bittiming(struct net_device *ndev)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + const struct can_bittiming *bt = &priv->can.bittiming;
>>> + u32 canbit;
>>> + u32 bepe;
>>> +
>>> + /* Setting the CCE bit for accessing the Can Timing register. */
>>> + pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
>>> +
>>> + canbit = (bt->brp - 1) & MSK_BITT_BRP;
>>> + canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
>>> + canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
>>> + canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
>>> + bepe = ((bt->brp - 1) & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
>>> + iowrite32(canbit, &priv->regs->bitt);
>>> + iowrite32(bepe, &priv->regs->brpe);
>>> + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void pch_can_start(struct net_device *ndev)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> +
>>> + if (priv->can.state != CAN_STATE_STOPPED)
>>> + pch_can_reset(priv);
>>> +
>>> + pch_set_bittiming(ndev);
>>> + pch_can_set_optmode(priv);
>>> +
>>> + pch_can_tx_enable_all(priv);
>>> + pch_can_rx_enable_all(priv);
>>> +
>>> + /* Setting the CAN to run mode. */
>>> + pch_can_set_run_mode(priv, PCH_CAN_RUN);
>>> +
>>> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
>>> +
>>> + return;
>>> +}
>>> +
>>> +static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
>>> +{
>>> + int ret = 0;
>>> +
>>> + switch (mode) {
>>> + case CAN_MODE_START:
>>> + pch_can_start(ndev);
>>> + netif_wake_queue(ndev);
>>> + break;
>>> + default:
>>> + ret = -EOPNOTSUPP;
>>> + break;
>>> + }
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int pch_can_open(struct net_device *ndev)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + int retval;
>>> +
>>> + /* Regsitering the interrupt. */
>>> + retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
>>> + ndev->name, ndev);
>>> + if (retval) {
>>> + dev_err(&ndev->dev, "request_irq failed.\n");
>>> + goto req_irq_err;
>>> + }
>>> +
>>> + /* Open common can device */
>>> + retval = open_candev(ndev);
>>> + if (retval) {
>>> + dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
>>> + goto err_open_candev;
>>> + }
>>> +
>>> + pch_can_init(priv);
>>> + pch_can_start(ndev);
>>> + napi_enable(&priv->napi);
>>> + netif_start_queue(ndev);
>>> +
>>> + return 0;
>>> +
>>> +err_open_candev:
>>> + free_irq(priv->dev->irq, ndev);
>>> +req_irq_err:
>>> + pch_can_release(priv);
>>> +
>>> + return retval;
>>> +}
>>> +
>>> +static int pch_close(struct net_device *ndev)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> +
>>> + netif_stop_queue(ndev);
>>> + napi_disable(&priv->napi);
>>> + pch_can_release(priv);
>>> + free_irq(priv->dev->irq, ndev);
>>> + close_candev(ndev);
>>> + priv->can.state = CAN_STATE_STOPPED;
>>> + return 0;
>>> +}
>>> +
>>> +static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
>>> +{
>>> + unsigned long flags;
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> + struct can_frame *cf = (struct can_frame *)skb->data;
>>> + int tx_buffer_avail = 0;
>>
>> What I'm totally missing is the TX flow controll. Your driver has to
>> ensure that the package leave the controller in the order that come
>> into the xmit function. Further you have to stop your xmit queue if
>> you're out of tx objects and reenable if you have a object free.
>>
>> Use netif_stop_queue() and netif_wake_queue() for this.
>
> In this code, I think "out of tx objects" cannot be occurred.
It's not a matter of code it's the hardware. You cannot put more than a
certain number of CAN frames into the hardware. If you have a CAN bus at
a certain speed, you can only send a certain number of CAN frames in a
second. So you cannot push more than this amount of frames/s into the
hardware.
> Nevertheless, are netif_stop_queue() and netif_wake_queue() is necessary ?
Yes.
>
>>
>>> +
>>> + if (can_dropped_invalid_skb(ndev, skb))
>>> + return NETDEV_TX_OK;
>>> +
>>> + if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj + 1 */
>>> + while (ioread32(&priv->regs->treq2) & 0xfc00)
>>> + udelay(1);
>>
>> please no (possible) infinite delays!
>
> I will add break processing.
>
>>
>>> + priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
>>> + }
>>
>>> +
>>> + tx_buffer_avail = priv->tx_obj;
>>
>> why has the "object" become a "buffer" now? :)
>
> You are right.
> I will modify the name.
>
>>
>>> + priv->tx_obj++;
>>> +
>>> + /* Attaining the lock. */
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> +
>>> + /* Setting the CMASK register to set value*/
>> ^^^
>>
>> pleas add a whitespace
>
> I agree.
>
>>
>>> + iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
>>> +
>>> + /* If ID extended is set. */
>>> + if (cf->can_id & CAN_EFF_FLAG) {
>>> + iowrite32(cf->can_id & 0xffff, &priv->regs->if2_id1);
>>> + iowrite32(((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD,
>>> + &priv->regs->if2_id2);
>>> + } else {
>>> + iowrite32(0, &priv->regs->if2_id1);
>>> + iowrite32((cf->can_id & CAN_SFF_MASK) << 2,
>>> + &priv->regs->if2_id2);
>>> + }
>>> +
>>> + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
>>
>> Do you need to do a read-modify-write of the hardware register? Please
>> prepare the values you want to write to hardware, then do it.
>
> Current design policy for read/write message object,
> the driver is designed with Read-Modify-Write.
>
> I will modify to Write only for reducing accessing Message RAM.
>
>>
>>> +
>>> + /* If remote frame has to be transmitted.. */
>>> + if (!(cf->can_id & CAN_RTR_FLAG))
>>> + pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
>> dito
>>> + /* If remote frame has to be transmitted.. */
>>> + if (cf->can_id & CAN_RTR_FLAG)
>>> + pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
>> dito
>>> +
>>> + /* Copy data to register */
>>> + if (cf->can_dlc > 0) {
>>> + u32 data1 = *((u16 *)&cf->data[0]);
>>> + iowrite32(data1, &priv->regs->if2_dataa1);
>>
>> do you think you send the bytes in correct order?
>
> Let me study this endianess.
>
>>
>>> + }
>>> + if (cf->can_dlc > 2) {
>>> + u32 data1 = *((u16 *)&cf->data[2]);
>>> + iowrite32(data1, &priv->regs->if2_dataa2);
>>> + }
>>> + if (cf->can_dlc > 4) {
>>> + u32 data1 = *((u16 *)&cf->data[4]);
>>> + iowrite32(data1, &priv->regs->if2_datab1);
>>> + }
>>> + if (cf->can_dlc > 6) {
>>> + u32 data1 = *((u16 *)&cf->data[6]);
>>> + iowrite32(data1, &priv->regs->if2_datab2);
>>> + }
>>> +
>>> + can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
>>> +
>>> + /* Set the size of the data. */
>>> + iowrite32(cf->can_dlc, &priv->regs->if2_mcont);
>>> +
>>> + /* Update if2_mcont */
>>> + pch_can_bit_set(&priv->regs->if2_mcont,
>>> + CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT |
>>> + CAN_IF_MCONT_TXIE);
>>
>> pleae first perpare your value, then write to hardware.
>
> ditto.
>
>>
>>> +
>>> + if (tx_buffer_avail == PCH_RX_OBJ_NUM) /* If points tail of FIFO */
>>> + pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_EOB);
>>
>> dito
>>
>> Is EOB relevant for TX objects?
>
> This is mistake. No meaning for tx.
> I will modify.
>
>>
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +
>>> + return NETDEV_TX_OK;
>>> +}
>>> +
>>> +static const struct net_device_ops pch_can_netdev_ops = {
>>> + .ndo_open = pch_can_open,
>>> + .ndo_stop = pch_close,
>>> + .ndo_start_xmit = pch_xmit,
>>> +};
>>> +
>>> +static void __devexit pch_can_remove(struct pci_dev *pdev)
>>> +{
>>> + struct net_device *ndev = pci_get_drvdata(pdev);
>>> + struct pch_can_priv *priv = netdev_priv(ndev);
>>> +
>>> + unregister_candev(priv->ndev);
>>> + pci_iounmap(pdev, priv->regs);
>>> + if (priv->use_msi)
>>> + pci_disable_msi(priv->dev);
>>> + pci_release_regions(pdev);
>>> + pci_disable_device(pdev);
>>> + pci_set_drvdata(pdev, NULL);
>>> + free_candev(priv->ndev);
>>> +}
>>> +
>>> +#ifdef CONFIG_PM
>>> +static void pch_can_set_int_custom(struct pch_can_priv *priv)
>>> +{
>>> + /* Clearing the IE, SIE and EIE bits of Can control register. */
>>> + pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
>>> +
>>> + /* Appropriately setting them. */
>>> + pch_can_bit_set(&priv->regs->cont,
>>> + ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
>>> +}
>>> +
>>> +/* This function retrieves interrupt enabled for the CAN device. */
>>> +static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
>>> +{
>>> + /* Obtaining the status of IE, SIE and EIE interrupt bits. */
>>> + return (ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1;
>>> +}
>>> +
>>> +static u32 pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num)
>>> +{
>>> + unsigned long flags;
>>> + u32 enable;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
>>> +
>>> + if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
>>> + ((ioread32(&priv->regs->if1_mcont)) &
>>> + CAN_IF_MCONT_RXIE))
>>> + enable = 1;
>>> + else
>>> + enable = 0;
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> + return enable;
>>> +}
>>> +
>>> +static u32 pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num)
>>> +{
>>> + unsigned long flags;
>>> + u32 enable;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> +
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
>>> + if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
>>> + ((ioread32(&priv->regs->if2_mcont)) &
>>> + CAN_IF_MCONT_TXIE)) {
>>> + enable = 1;
>>> + } else {
>>> + enable = 0;
>>> + }
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +
>>> + return enable;
>>> +}
>>> +
>>> +static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
>>> + u32 buffer_num, u32 set)
>>> +{
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
>>> + iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
>>> + if (set == 1)
>>> + pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
>>> + else
>>> + pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
>>> +
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> +}
>>> +
>>> +static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
>>> +{
>>> + unsigned long flags;
>>> + u32 link;
>>> +
>>> + spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>>> + iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
>>> + pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
>>> +
>>> + if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
>>> + link = 0;
>>> + else
>>> + link = 1;
>>> + spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
>>> + return link;
>>> +}
>>> +
>>> +static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
>>> +{
>>> + int i;
>>> + int retval;
>>> + u32 buf_stat; /* Variable for reading the transmit buffer status. */
>>> + u32 counter = COUNTER_LIMIT;
>>> +
>>> + struct net_device *dev = pci_get_drvdata(pdev);
>>> + struct pch_can_priv *priv = netdev_priv(dev);
>>> +
>>> + /* Stop the CAN controller */
>>> + pch_can_set_run_mode(priv, PCH_CAN_STOP);
>>> +
>>> + /* Indicate that we are aboutto/in suspend */
>>> + priv->can.state = CAN_STATE_STOPPED;
>>> +
>>> + /* Waiting for all transmission to complete. */
>>> + while (counter) {
>>> + buf_stat = pch_can_get_buffer_status(priv);
>>> + if (!buf_stat)
>>> + break;
>>> + counter--;
>>> + udelay(1);
>>> + }
>>> + if (!counter)
>>> + dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
>>> +
>>> + /* Save interrupt configuration and then disable them */
>>> + priv->int_enables = pch_can_get_int_enables(priv);
>>> + pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
>>> +
>>> + /* Save Tx buffer enable state */
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++)
>>> + priv->tx_enable[i] = pch_can_get_tx_enable(priv, i);
>>> +
>>> + /* Disable all Transmit buffers */
>>> + pch_can_tx_disable_all(priv);
>>> +
>>> + /* Save Rx buffer enable state */
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++) {
>>> + priv->rx_enable[i] = pch_can_get_rx_enable(priv, i);
>>> + priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
>>> + }
>>> +
>>> + /* Disable all Receive buffers */
>>> + pch_can_rx_disable_all(priv);
>>> + retval = pci_save_state(pdev);
>>> + if (retval) {
>>> + dev_err(&pdev->dev, "pci_save_state failed.\n");
>>> + } else {
>>> + pci_enable_wake(pdev, PCI_D3hot, 0);
>>> + pci_disable_device(pdev);
>>> + pci_set_power_state(pdev, pci_choose_state(pdev, state));
>>> + }
>>> +
>>> + return retval;
>>> +}
>>> +
>>> +static int pch_can_resume(struct pci_dev *pdev)
>>> +{
>>> + int i;
>>> + int retval;
>>> + struct net_device *dev = pci_get_drvdata(pdev);
>>> + struct pch_can_priv *priv = netdev_priv(dev);
>>> +
>>> + pci_set_power_state(pdev, PCI_D0);
>>> + pci_restore_state(pdev);
>>> + retval = pci_enable_device(pdev);
>>> + if (retval) {
>>> + dev_err(&pdev->dev, "pci_enable_device failed.\n");
>>> + return retval;
>>> + }
>>> +
>>> + pci_enable_wake(pdev, PCI_D3hot, 0);
>>> +
>>> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
>>> +
>>> + /* Disabling all interrupts. */
>>> + pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
>>> +
>>> + /* Setting the CAN device in Stop Mode. */
>>> + pch_can_set_run_mode(priv, PCH_CAN_STOP);
>>> +
>>> + /* Configuring the transmit and receive buffers. */
>>> + pch_can_config_rx_tx_buffers(priv);
>>> +
>>> + /* Restore the CAN state */
>>> + pch_set_bittiming(dev);
>>> +
>>> + /* Listen/Active */
>>> + pch_can_set_optmode(priv);
>>> +
>>> + /* Enabling the transmit buffer. */
>>> + for (i = 1; i <= PCH_RX_OBJ_NUM; i++)
>>> + pch_can_set_tx_enable(priv, i, priv->tx_enable[i]);
>>> +
>>> + /* Configuring the receive buffer and enabling them. */
>>> + for (i = PCH_RX_OBJ_NUM + 1; i <= PCH_OBJ_NUM; i++) {
>>> + /* Restore buffer link */
>>> + pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
>>> +
>>> + /* Restore buffer enables */
>>> + pch_can_set_rx_enable(priv, i, priv->rx_enable[i]);
>>> + }
>>> +
>>> + /* Enable CAN Interrupts */
>>> + pch_can_set_int_custom(priv);
>>> +
>>> + /* Restore Run Mode */
>>> + pch_can_set_run_mode(priv, PCH_CAN_RUN);
>>> +
>>> + return retval;
>>> +}
>>> +#else
>>> +#define pch_can_suspend NULL
>>> +#define pch_can_resume NULL
>>> +#endif
>>> +
>>> +static int pch_can_get_berr_counter(const struct net_device *dev,
>>> + struct can_berr_counter *bec)
>>> +{
>>> + struct pch_can_priv *priv = netdev_priv(dev);
>>> +
>>> + bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
>>> + bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int __devinit pch_can_probe(struct pci_dev *pdev,
>>> + const struct pci_device_id *id)
>>> +{
>>> + struct net_device *ndev;
>>> + struct pch_can_priv *priv;
>>> + int rc;
>>> + void __iomem *addr;
>>> +
>>> + rc = pci_enable_device(pdev);
>>> + if (rc) {
>>> + dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
>>> + goto probe_exit_endev;
>>> + }
>>> +
>>> + rc = pci_request_regions(pdev, KBUILD_MODNAME);
>>> + if (rc) {
>>> + dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
>>> + goto probe_exit_pcireq;
>>> + }
>>> +
>>> + addr = pci_iomap(pdev, 1, 0);
>>> + if (!addr) {
>>> + rc = -EIO;
>>> + dev_err(&pdev->dev, "Failed pci_iomap\n");
>>> + goto probe_exit_ipmap;
>>> + }
>>> +
>>> + ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
>>> + if (!ndev) {
>>> + rc = -ENOMEM;
>>> + dev_err(&pdev->dev, "Failed alloc_candev\n");
>>> + goto probe_exit_alloc_candev;
>>> + }
>>> +
>>> + priv = netdev_priv(ndev);
>>> + priv->ndev = ndev;
>>> + priv->regs = addr;
>>> + priv->dev = pdev;
>>> + priv->can.bittiming_const = &pch_can_bittiming_const;
>>> + priv->can.do_set_mode = pch_can_do_set_mode;
>>> + priv->can.do_get_berr_counter = pch_can_get_berr_counter;
>>> + priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
>>> + CAN_CTRLMODE_LOOPBACK;
>>> + priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
>>> +
>>> + ndev->irq = pdev->irq;
>>> + ndev->flags |= IFF_ECHO;
>>> +
>>> + pci_set_drvdata(pdev, ndev);
>>> + SET_NETDEV_DEV(ndev, &pdev->dev);
>>> + ndev->netdev_ops = &pch_can_netdev_ops;
>>> + priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
>>> +
>>> + netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
>>> +
>>> + rc = pci_enable_msi(priv->dev);
>>> + if (rc) {
>>> + dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
>>> + priv->use_msi = 0;
>>> + } else {
>>> + dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
>>> + priv->use_msi = 1;
>>> + }
>>> +
>>> + rc = register_candev(ndev);
>>> + if (rc) {
>>> + dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
>>> + goto probe_exit_reg_candev;
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +probe_exit_reg_candev:
>>> + free_candev(ndev);
>>> +probe_exit_alloc_candev:
>>> + pci_iounmap(pdev, addr);
>>> +probe_exit_ipmap:
>>> + pci_release_regions(pdev);
>>> +probe_exit_pcireq:
>>> + pci_disable_device(pdev);
>>> +probe_exit_endev:
>>> + return rc;
>>> +}
>>> +
>>> +static struct pci_driver pch_can_pcidev = {
>>> + .name = "pch_can",
>>> + .id_table = pch_pci_tbl,
>>> + .probe = pch_can_probe,
>>> + .remove = __devexit_p(pch_can_remove),
>>> + .suspend = pch_can_suspend,
>>> + .resume = pch_can_resume,
>>> +};
>>> +
>>> +static int __init pch_can_pci_init(void)
>>> +{
>>> + return pci_register_driver(&pch_can_pcidev);
>>> +}
>>> +module_init(pch_can_pci_init);
>>> +
>>> +static void __exit pch_can_pci_exit(void)
>>> +{
>>> + pci_unregister_driver(&pch_can_pcidev);
>>> +}
>>> +module_exit(pch_can_pci_exit);
>>> +
>>> +MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_VERSION("0.94");
>>
>> cheers, Marc
>>
>> --
>> Pengutronix e.K. | Marc Kleine-Budde |
>> Industrial Linux Solutions | Phone: +49-231-2826-924 |
>> Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
>> Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
>>
>>
>
> Thanks, Tomoya(OKI SEMICONDUCTOR CO., LTD.)
cheers, Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #1.2: OpenPGP digital signature --]
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_______________________________________________
Socketcan-core mailing list
Socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org
https://lists.berlios.de/mailman/listinfo/socketcan-core
^ permalink raw reply
* [PATCH] rds: Lost locking in loop connection freeing
From: Pavel Emelyanov @ 2010-11-02 11:52 UTC (permalink / raw)
To: Andy Grover, David Miller; +Cc: rds-devel, Linux Netdev List
The conn is removed from list in there and this requires
proper lock protection.
Signed-off-by: Pavel Emelyanov <xemul@openvz.org>
---
diff --git a/net/rds/loop.c b/net/rds/loop.c
index c390156..aeec1d4 100644
--- a/net/rds/loop.c
+++ b/net/rds/loop.c
@@ -134,8 +134,12 @@ static int rds_loop_conn_alloc(struct rds_connection *conn, gfp_t gfp)
static void rds_loop_conn_free(void *arg)
{
struct rds_loop_connection *lc = arg;
+ unsigned long flags;
+
rdsdebug("lc %p\n", lc);
+ spin_lock_irqsave(&loop_conns_lock, flags);
list_del(&lc->loop_node);
+ spin_unlock_irqrestore(&loop_conns_lock, flags);
kfree(lc);
}
--
1.5.5.6
^ permalink raw reply related
* [PATCH] rds: Remove kfreed tcp conn from list
From: Pavel Emelyanov @ 2010-11-02 11:54 UTC (permalink / raw)
To: Andy Grover, David Miller; +Cc: rds-devel, Linux Netdev List
All the rds_tcp_connection objects are stored list, but when
being freed it should be removed from there.
Signed-off-by: Pavel Emelyanov <xemul@openvz.org>
---
diff --git a/net/rds/tcp.c b/net/rds/tcp.c
index 08a8c6c..8e0a320 100644
--- a/net/rds/tcp.c
+++ b/net/rds/tcp.c
@@ -221,7 +221,13 @@ static int rds_tcp_conn_alloc(struct rds_connection *conn, gfp_t gfp)
static void rds_tcp_conn_free(void *arg)
{
struct rds_tcp_connection *tc = arg;
+ unsigned long flags;
rdsdebug("freeing tc %p\n", tc);
+
+ spin_lock_irqsave(&rds_tcp_conn_lock, flags);
+ list_del(&tc->t_tcp_node);
+ spin_unlock_irqrestore(&rds_tcp_conn_lock, flags);
+
kmem_cache_free(rds_tcp_conn_slab, tc);
}
--
1.5.5.6
^ permalink raw reply related
* For your interest
From: Srood Sherif @ 2010-11-02 12:59 UTC (permalink / raw)
[-- Attachment #1: Type: text/plain, Size: 359 bytes --]
Greeting,
My name is Mr. Srood A. Sherif, I live and work in Abu
Dhabi UAE. I have an urgent business which I believe
will interest you. Find the enclose for details.
For any reason you cannot open that attachment, please
let me know so that I can resend it in the body of the
mail, thank you.
I wait for your response, Thank you.
Regards
Srood A. Sherif
[-- Attachment #2: THE INFORMATION.jpg --]
[-- Type: image/jpeg, Size: 240015 bytes --]
^ permalink raw reply
* Re: [PATCH] net: sh_eth: ctrl_in/outX to __raw_read/writeX conversion.
From: Paul Mundt @ 2010-11-02 13:39 UTC (permalink / raw)
To: Nobuhiro Iwamatsu; +Cc: netdev
In-Reply-To: <1288666295-12529-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com>
On Tue, Nov 02, 2010 at 11:51:35AM +0900, Nobuhiro Iwamatsu wrote:
> The ctrl_xxx routines are deprecated, switch over to the __raw_xxx
> versions.
>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
I sent a similar patch yesterday:
http://patchwork.ozlabs.org/patch/69831/
It doesn't matter really which one gets applied, although I opted to use
the accessors with strong ordering given that we'll continue to see this
block in newer CPUs where weak ordering is unlikely to be sufficient.
^ permalink raw reply
* Partnership..?
From: Mr. Vincent Cheng @ 2010-11-02 9:44 UTC (permalink / raw)
To: info
Hello,
I am Mr. Vincent Cheng, and have a sensitive and confidential brief from
Hong Kong.
I am asking for your partnership in re-profiling funds and will give the
details.
This is a legitimate transaction and you will be paid a handsome
percentage for your "Management Fees". If interested you can kindly write
and provide me with your confidential telephone number or fax number
and I will provide further details with proper guidelines. I require absolute
confidentiality as to any political problems.
Finally, note that this must be concluded within two weeks. Kindly write
back to this email mrchengvich66@yahoo.com.hk, I look forward to hear from
you.
Regards,
Vincent Cheng.
^ permalink raw reply
* Re: 2.6.35->2.6.36 regression, vanilla kernel panic, ppp or hrtimers crashing
From: Denys Fedoryshchenko @ 2010-11-02 13:49 UTC (permalink / raw)
To: Jarek Poplawski; +Cc: Thomas Gleixner, Paul Mackerras, linux-kernel, netdev
In-Reply-To: <20101028070550.GA7647@ff.dom.local>
I didn't try yet, but i enable more debugs and catch linked list corruption.
Here is dumps from netconsole:
http://www.nuclearcat.com/ll.txt
http://www.nuclearcat.com/ll2.txt
I have another PC, also fails to run 2.6.36, but netconsole don't give
anything.
Both PC's have strange issue with clock drifting away too much (on 2.6.35 and
maybe even before).
On Thursday 28 October 2010 10:05:50 Jarek Poplawski wrote:
> On 2010-10-25 11:22, Denys Fedoryshchenko wrote:
> > Hi
> >
> > Here is what i got from netconsole
> >
> > [ 259.238755] BUG: unable to handle kernel
> > paging request
> > at f8ba001c
> > [ 259.238953] IP:
> > [<c0199ebe>] do_select+0x2cc/0x502
>
> ...
>
> > It is not easy to do full git bisect(it is semi-embedded distro), but i
> > can try reversing particular commits, if someone can give idea which
> > one, and can try debug patches.
>
> Hi,
> Nothing concrete, but you might try reverting this one:
>
> http://git.kernel.org/?p=linux/kernel/git/stable/linux-2.6.36.y.git;a=commi
> tdiff;h=15fd0cd9a2ad24a78fbee369dec8ca660979d57e
>
> Jarek P.
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [SECURITY] memory corruption in X.25 facilities parsing
From: Dan Rosenberg @ 2010-11-02 15:02 UTC (permalink / raw)
To: andrew.hendry; +Cc: netdev, security, stable
I put this together after a quick glance, so if someone knows this code
better than I do (i.e. at all), feel free to comment or drop this patch
if it's unnecessary.
A value of 0 will cause a memcpy() of ULONG_MAX size, destroying the
kernel heap.
Signed-off-by: Dan Rosenberg <drosenberg@vsecurity.com>
--- linux-2.6.36-rc6.orig/net/x25/x25_facilities.c 2010-09-28 21:01:22.000000000 -0400
+++ linux-2.6.36-rc6/net/x25/x25_facilities.c 2010-11-02 10:36:02.827291324 -0400
@@ -134,14 +134,14 @@ int x25_parse_facilities(struct sk_buff
case X25_FAC_CLASS_D:
switch (*p) {
case X25_FAC_CALLING_AE:
- if (p[1] > X25_MAX_DTE_FACIL_LEN)
+ if (p[1] > X25_MAX_DTE_FACIL_LEN || p[1] == 0)
break;
dte_facs->calling_len = p[2];
memcpy(dte_facs->calling_ae, &p[3], p[1] - 1);
*vc_fac_mask |= X25_MASK_CALLING_AE;
break;
case X25_FAC_CALLED_AE:
- if (p[1] > X25_MAX_DTE_FACIL_LEN)
+ if (p[1] > X25_MAX_DTE_FACIL_LEN || p[1] == 0)
break;
dte_facs->called_len = p[2];
memcpy(dte_facs->called_ae, &p[3], p[1] - 1);
^ permalink raw reply
* Re: [PATCH] bluetooth: bnep: fix information leak to userland
From: Marcel Holtmann @ 2010-11-02 15:35 UTC (permalink / raw)
To: Vasiliy Kulikov
Cc: kernel-janitors-u79uwXL29TY76Z2rM5mHXA, Gustavo F. Padovan,
David S. Miller, Eric Dumazet, Thadeu Lima de Souza Cascardo,
Tejun Heo, Jiri Kosina, linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1288448782-5582-1-git-send-email-segooon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Vasiiy,
> Structure bnep_conninfo is copied to userland with the field "device"
> that has the last elements unitialized. It leads to leaking of
> contents of kernel stack memory.
>
> Signed-off-by: Vasiliy Kulikov <segooon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Marcel Holtmann <marcel-kz+m5ild9QBg9hUCZPvPmw@public.gmane.org>
Regards
Marcel
^ permalink raw reply
* Re: [PATCH] bluetooth: cmtp: fix information leak to userland
From: Marcel Holtmann @ 2010-11-02 15:35 UTC (permalink / raw)
To: Vasiliy Kulikov
Cc: kernel-janitors, Gustavo F. Padovan, David S. Miller,
Eric Dumazet, linux-bluetooth, netdev, linux-kernel
In-Reply-To: <1288448787-5848-1-git-send-email-segooon@gmail.com>
Hi Vasiliy,
> Structure cmtp_conninfo is copied to userland with some padding fields
> unitialized. It leads to leaking of contents of kernel stack memory.
>
> Signed-off-by: Vasiliy Kulikov <segooon@gmail.com>
Acked-by: Marcel Holtmann <marcel@holtmann.org>
Regards
Marcel
^ permalink raw reply
* Re: [PATCH] bluetooth: hidp: fix information leak to userland
From: Marcel Holtmann @ 2010-11-02 15:36 UTC (permalink / raw)
To: Vasiliy Kulikov
Cc: kernel-janitors-u79uwXL29TY76Z2rM5mHXA, Gustavo F. Padovan,
David S. Miller, Jiri Kosina, Michael Poole, Bastien Nocera,
linux-bluetooth-u79uwXL29TY76Z2rM5mHXA,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1288448791-6009-1-git-send-email-segooon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Vasiliy,
> Structure hidp_conninfo is copied to userland with version, product,
> vendor and name fields unitialized if both session->input and session->hid
> are NULL. It leads to leaking of contents of kernel stack memory.
>
> Signed-off-by: Vasiliy Kulikov <segooon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Marcel Holtmann <marcel-kz+m5ild9QBg9hUCZPvPmw@public.gmane.org>
Regards
Marcel
^ permalink raw reply
* Re: [PATCH] virtio_net: Fix queue full check
From: Michael S. Tsirkin @ 2010-11-02 16:17 UTC (permalink / raw)
To: Rusty Russell; +Cc: Krishna Kumar2, davem, netdev, yvugenfi
In-Reply-To: <201010292158.40411.rusty@rustcorp.com.au>
On Fri, Oct 29, 2010 at 09:58:40PM +1030, Rusty Russell wrote:
> On Fri, 29 Oct 2010 09:25:09 pm Krishna Kumar2 wrote:
> > Rusty Russell <rusty@rustcorp.com.au> wrote on 10/29/2010 03:17:24 PM:
> >
> > > > Oct 17 10:22:40 localhost kernel: net eth0: Unexpected TX queue
> > failure: -28
> > > > Oct 17 10:28:22 localhost kernel: net eth0: Unexpected TX queue
> > failure: -28
> > > > Oct 17 10:35:58 localhost kernel: net eth0: Unexpected TX queue
> > failure: -28
> > > > Oct 17 10:41:06 localhost kernel: net eth0: Unexpected TX queue
> > failure: -28
> > > >
> > > > I initially changed the check from -ENOMEM to -ENOSPC, but
> > > > virtqueue_add_buf can return only -ENOSPC when it doesn't have
> > > > space for new request. Patch removes redundant checks but
> > > > displays the failure errno.
> > > >
> > > > Signed-off-by: Krishna Kumar <krkumar2@in.ibm.com>
> > > > ---
> > > > drivers/net/virtio_net.c | 15 ++++-----------
> > > > 1 file changed, 4 insertions(+), 11 deletions(-)
> > > >
> > > > diff -ruNp org/drivers/net/virtio_net.c new/drivers/net/virtio_net.c
> > > > --- org/drivers/net/virtio_net.c 2010-10-11 10:20:02.000000000 +0530
> > > > +++ new/drivers/net/virtio_net.c 2010-10-21 17:37:45.000000000 +0530
> > > > @@ -570,17 +570,10 @@ static netdev_tx_t start_xmit(struct sk_
> > > >
> > > > /* This can happen with OOM and indirect buffers. */
> > > > if (unlikely(capacity < 0)) {
> > > > - if (net_ratelimit()) {
> > > > - if (likely(capacity == -ENOMEM)) {
> > > > - dev_warn(&dev->dev,
> > > > - "TX queue failure: out of memory\n");
> > > > - } else {
> > > > - dev->stats.tx_fifo_errors++;
> > > > - dev_warn(&dev->dev,
> > > > - "Unexpected TX queue failure: %d\n",
> > > > - capacity);
> > > > - }
> > > > - }
> > > > + if (net_ratelimit())
> > > > + dev_warn(&dev->dev,
> > > > + "TX queue failure (%d): out of memory\n",
> > > > + capacity);
> > >
> > > Hold on... you were getting -ENOSPC, which shouldn't happen. What makes
> > you
> > > think it's out of memory?
> >
> > virtqueue_add_buf_gfp returns only -ENOSPC on failure, whether
> > direct or indirect descriptors are used, so isn't -ENOSPC
> > "expected"? (vring_add_indirect returns -ENOMEM on memory
> > failure, but that is masked out and we go direct which is
> > the failure point).
>
> Ah, OK, gotchya.
> I'm not even sure the fallback to linear makes sense; if we're failing
> kmallocs we should probably just return -ENOMEM. Would mean we can
> tell the difference between "out of space" (which should never happen
> since we stop the queue when we have < 2+MAX_SKB_FRAGS slots left)
> and this case.
>
> Michael, what do you think?
>
> Thanks,
> Rusty.
Let's make sure I understand the issue: we use indirect buffers
so we assume there's still a lot of place in the ring, then
allocation for the indirect fails and so we return -ENOSPC?
So first, I agree it's a bug. But I am not sure killing the fallback
is such a good idea: recovering from add buf failure is hard
generally, we should try to accomodate if we can. Let's just fix
the return code for now?
And generally, we should be smarter: as long as the ring is almost
empty, and s/g list is short, it is a waste to use indirect buffers.
BTW we have had a FIXME there for a long while, I think Yan suggested
increasing that threshold to 3. Yan?
Further, maybe preallocating some memory for the indirect buffers might
be a good idea.
In short, lots of good ideas, let's start with the minimal patch that is
a good 2.6.37 candidate too. How about the following (untested)?
virtio: fix add_buf return code for OOM
add_buff returned ENOSPC on out of memory: this is a bug
as at leats virtio-net expects ENOMEM and handles it
specially. Fix that.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 1475ed6..0a89098 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -165,7 +165,7 @@ int virtqueue_add_buf_gfp(struct virtqueue *_vq,
{
struct vring_virtqueue *vq = to_vvq(_vq);
unsigned int i, avail, uninitialized_var(prev);
- int head;
+ int head = -ENOSPC;
START_USE(vq);
@@ -191,7 +191,7 @@ int virtqueue_add_buf_gfp(struct virtqueue *_vq,
if (out)
vq->notify(&vq->vq);
END_USE(vq);
- return -ENOSPC;
+ return head;
}
/* We're about to use some buffers from the free list. */
--
MST
^ permalink raw reply related
* [SECURITY] CAN info leak/minor heap overflow
From: Dan Rosenberg @ 2010-11-02 18:28 UTC (permalink / raw)
To: socketcan, oliver.hartkopp, urs.thuermann; +Cc: netdev, security
In bcm_connect() (in net/can/bcm.c), I noticed the following code:
sprintf(bo->procname, "%p", sock);
"procname" is a 9-byte char array. This code is wrong on two levels.
First, leaking a kernel address via a /proc filename is bad. Secondly,
on 64-bit platforms, up to 17 bytes may be copied into the buffer.
Fortunately, structure padding will most likely prevent this from being
a problem, except for the trailing NULL byte, which may overwrite the
first byte of the next heap object. Please name your procfile in a way
that doesn't leak information and fits into the desired name buffer.
-Dan
^ permalink raw reply
* Re: [RFC PATCH] macvlan: Introduce a PASSTHRU mode to takeover the underlying device
From: Michael S. Tsirkin @ 2010-11-02 18:42 UTC (permalink / raw)
To: Sridhar Samudrala; +Cc: kaber, Arnd Bergmann, netdev, kvm@vger.kernel.org
In-Reply-To: <4CD05621.6000706@us.ibm.com>
On Tue, Nov 02, 2010 at 11:19:13AM -0700, Sridhar Samudrala wrote:
> On Mon, 2010-11-01 at 10:28 +0200, Michael S. Tsirkin wrote:
>
> On Tue, Oct 26, 2010 at 03:19:38PM -0700, Sridhar Samudrala wrote:
> > With the current default macvtap mode, a KVM guest using virtio with
> > macvtap backend has the following limitations.
> > - cannot change/add a mac address on the guest virtio-net
> > - cannot create a vlan device on the guest virtio-net
> > - cannot enable promiscuous mode on guest virtio-net
> >
> > This patch introduces a new mode called 'passthru' when creating a
> > macvlan device which allows takeover of the underlying device and
> > passing it to a guest using virtio with macvtap backend.
> >
> > Only one macvlan device is allowed in passthru mode and it inherits
> > the mac address from the underlying device and sets it in promiscuous
> > mode to receive and forward all the packets.
> >
> > Thanks
> > Sridhar
>
> One concern with promisc mode is that for the common case,
> which is a single mac and no vlans, we will be getting
> extra packets that will get dropped in userspace/guest
> as compared to the case where same mac is programmed
> in hardware and by guest.
>
> In the tap/bridge model also, the external i/f is put in promiscuous mode and
> the
> bridge does the filtering of extra packets.
Yes but
1. that is much cheaper than passing them all the way up to the guest.
2. it's pretty painful for management to have to decide between
features and speed. Better give them both :)
> We could let userspace supply a list of mac/vlan addresses through
> an ioctl on macvtap, and then
> 1. for a single mac, program it in hardware
> 2. for other configurations, set promisc mode
>
> tun already has TUNSETTXFILTER which might come in handy here.
> We don't pass in vlans with the filter now but maybe we should.
> How does this sound?
>
> I guess this can be done. But i am not sure if we can extend the existing
> TUNSETTXFILTER
> to support vlans too. we may need a new ioctl.
>
> Thanks
> Sridhar
OK. Maybe add it to tap too.
--
MST
^ permalink raw reply
* Re: Routing over multiple interfaces
From: Bandan Das @ 2010-11-02 18:47 UTC (permalink / raw)
To: David Miller; +Cc: dwmw2, netdev, uweber
In-Reply-To: <20101101.141638.116372747.davem@davemloft.net>
On 0, David Miller <davem@davemloft.net> wrote:
> From: David Woodhouse <dwmw2@infradead.org>
> Date: Mon, 01 Nov 2010 17:12:02 -0400
>
> > But when I do a large upload, I find that the kernel is only ever using
> > a *single* link at a time, rather than both. How can I make it use
> > *both* links? It's fine to confine each flow to a single link if it
> > doesn't saturate that link... but once the queue is full, it should
> > overflow onto the other device.
>
> Once a TCP socket gets a routing cache entry, that's what it uses
> for the rest of the life of the connection.
>
> The multi-pathing decision happens at the time the routing
> cache entry is created.
>
> What you want is multi-path routing support in the routing cache.
>
> We used to have that, but the guy who implemented it (after bugging
> me to integrate it for 4 months straight, non-stop) just did a code
> dump and then disappeared and fixed none of the serious fundamental
> problems which existed in his code.
You are talking about the equalize patch, right ?
I had a similar requirement once a long time back and I didn't
know of any other way to do it, so, I just "forced" this patch
on a 2.6.23 kernel.
David W, may be you can take a look just to get an idea..
http://th.oughts.org/equalize_2.6_0.3.patch
Bandan
^ permalink raw reply
* Re: [SECURITY] CAN info leak/minor heap overflow
From: Oliver Hartkopp @ 2010-11-02 19:43 UTC (permalink / raw)
To: Dan Rosenberg; +Cc: urs.thuermann, netdev, security
In-Reply-To: <1288722503.2504.14.camel@dan>
Hello Dan,
On 02.11.2010 19:28, Dan Rosenberg wrote:
> In bcm_connect() (in net/can/bcm.c), I noticed the following code:
>
> sprintf(bo->procname, "%p", sock);
>
> "procname" is a 9-byte char array. This code is wrong on two levels.
> First, leaking a kernel address via a /proc filename is bad.
Why is this bad? Can the addresses of CAN-BCM sock structs be used for
anything from userspace?
For me they are just intented to be unique numbers ...
> Secondly,
> on 64-bit platforms, up to 17 bytes may be copied into the buffer.
Hm - that's indeed not wanted. Will send a patch at least for this issue.
> Fortunately, structure padding will most likely prevent this from being
> a problem, except for the trailing NULL byte, which may overwrite the
> first byte of the next heap object. Please name your procfile in a way
> that doesn't leak information and fits into the desired name buffer.
>
> -Dan
>
Regards,
Oliver
^ permalink raw reply
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