* Re: [PATCH v3] filter: Optimize instruction revalidation code.
From: Changli Gao @ 2010-11-17 7:54 UTC (permalink / raw)
To: Eric Dumazet; +Cc: Tetsuo Handa, mjt, davem, drosenberg, hagen, netdev
In-Reply-To: <1289980137.2732.280.camel@edumazet-laptop>
On Wed, Nov 17, 2010 at 3:48 PM, Eric Dumazet <eric.dumazet@gmail.com> wrote:
>
> Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
>
> Please repost it when Changli patch is accepted by David
> (if accepted :)), to get rid of the "+ 1"
>
Oh. No need, if David accepts this patch first, otherwise, there is
just some offset, and patch can handle it. :)
--
Regards,
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [PATCH v3] filter: Optimize instruction revalidation code.
From: Tetsuo Handa @ 2010-11-17 8:06 UTC (permalink / raw)
To: eric.dumazet; +Cc: mjt, davem, drosenberg, hagen, xiaosuo, netdev
In-Reply-To: <1289980137.2732.280.camel@edumazet-laptop>
Eric Dumazet wrote:
> > > But how about this:
> > >
> > > enum {
> > > BPF_S_RET_K = 1,
> >
> > If BPF_S_* are only for kernel internal use, I think we don't need to translate
> > from the beginning because only net/core/filter.c uses BPF_S_*.
> >
> > BPF_S_* are exposed to userspace via /usr/include/linux/filter.h since 2.6.36.
> > Is it no problem to change?
>
> No problem, and Changli posted patch to move them to net/core/filter.c
> anyway.
> Please repost it when Changli patch is accepted by David
> (if accepted :)), to get rid of the "+ 1"
But if Changli's patch is accepted, we can remove BPF_S_* like below.
switch (fentry->code) {
- case BPF_S_ALU_ADD_X:
+ case BPF_ALU|BPF_ADD|BPF_X: /* BPF_S_ALU_ADD_X */
A += X;
continue;
- case BPF_S_ALU_ADD_K:
+ case BPF_ALU|BPF_ADD|BPF_K: /* BPF_S_ALU_ADD_K */
A += f_k;
continue;
- case BPF_S_ALU_SUB_X:
+ case BPF_ALU|BPF_SUB|BPF_X: /* BPF_S_ALU_SUB_X */
A -= X;
continue;
- case BPF_S_ALU_SUB_K:
+ case BPF_ALU|BPF_SUB|BPF_K: /* BPF_S_ALU_SUB_K */
A -= f_k;
continue;
If compilers can generate better code for continuous case values
than discontinuous case values, then keeping BPF_S_* makes sense.
^ permalink raw reply
* RE: [PATCH v15 00/17] Provide a zero-copy method on KVM virtio-net.
From: Xin, Xiaohui @ 2010-11-17 8:09 UTC (permalink / raw)
To: Xin, Xiaohui, David Miller
Cc: netdev@vger.kernel.org, kvm@vger.kernel.org,
linux-kernel@vger.kernel.org, mst@redhat.com, mingo@elte.hu,
herbert@gondor.apana.org.au, jdike@linux.intel.com
In-Reply-To: <F2E9EB7348B8264F86B6AB8151CE2D793498A31E75@shsmsx502.ccr.corp.intel.com>
>-----Original Message-----
>From: kvm-owner@vger.kernel.org [mailto:kvm-owner@vger.kernel.org] On Behalf Of Xin,
>Xiaohui
>Sent: Thursday, November 11, 2010 4:28 PM
>To: David Miller
>Cc: netdev@vger.kernel.org; kvm@vger.kernel.org; linux-kernel@vger.kernel.org;
>mst@redhat.com; mingo@elte.hu; herbert@gondor.apana.org.au; jdike@linux.intel.com
>Subject: RE: [PATCH v15 00/17] Provide a zero-copy method on KVM virtio-net.
>
>>-----Original Message-----
>>From: David Miller [mailto:davem@davemloft.net]
>>Sent: Thursday, November 11, 2010 1:47 AM
>>To: Xin, Xiaohui
>>Cc: netdev@vger.kernel.org; kvm@vger.kernel.org; linux-kernel@vger.kernel.org;
>>mst@redhat.com; mingo@elte.hu; herbert@gondor.apana.org.au; jdike@linux.intel.com
>>Subject: Re: [PATCH v15 00/17] Provide a zero-copy method on KVM virtio-net.
>>
>>From: xiaohui.xin@intel.com
>>Date: Wed, 10 Nov 2010 17:23:28 +0800
>>
>>> From: Xin Xiaohui <xiaohui.xin@intel.com>
>>>
>>>>2) The idea to key off of skb->dev in skb_release_data() is
>>>> fundamentally flawed since many actions can change skb->dev on you,
>>>> which will end up causing a leak of your external data areas.
>>>
>>> How about this one? If the destructor_arg is not a good candidate,
>>> then I have to add an apparent field in shinfo.
>>
>>If destructor_arg is actually a net_device pointer or similar,
>>you will need to take a reference count on it or similar.
>>
>Do you mean destructor_arg will be consumed by other user?
>If that case, may I add a new structure member in shinfo?
>Thus only zero-copy will use it, and no need for the reference count.
>
How about this? It really needs somewhere to track the external data area,
and if something wrong with it, we can also release the data area. We think
skb_release_data() is the right place to deal with it. If I understood right,
that destructor_arg will be used by other else that why reference count is
needed, then how about add a new structure member in shinfo?
Thanks
Xiaohui
>>Which means --> good bye performance especially on SMP.
>>
>>You're going to be adding new serialization points and at
>>least two new atomics per packet.
>--
>To unsubscribe from this list: send the line "unsubscribe kvm" in
>the body of a message to majordomo@vger.kernel.org
>More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3] filter: Optimize instruction revalidation code.
From: Eric Dumazet @ 2010-11-17 8:18 UTC (permalink / raw)
To: Changli Gao; +Cc: Tetsuo Handa, mjt, davem, drosenberg, hagen, netdev
In-Reply-To: <AANLkTimi1AhXnqv8991Y3=HwoYwvYxEbPd0LroGouZp9@mail.gmail.com>
Le mercredi 17 novembre 2010 à 15:54 +0800, Changli Gao a écrit :
> On Wed, Nov 17, 2010 at 3:48 PM, Eric Dumazet <eric.dumazet@gmail.com> wrote:
> >
> > Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
> >
> > Please repost it when Changli patch is accepted by David
> > (if accepted :)), to get rid of the "+ 1"
> >
>
> Oh. No need, if David accepts this patch first, otherwise, there is
> just some offset, and patch can handle it. :)
>
>
I was speaking of all the "+ 1" in codes[] init
+ static const u8 codes[] = {
+ [BPF_ALU|BPF_ADD|BPF_K] = BPF_S_ALU_ADD_K + 1,
+ [BPF_ALU|BPF_ADD|BPF_X] = BPF_S_ALU_ADD_X + 1,
+ [BPF_ALU|BPF_SUB|BPF_K] = BPF_S_ALU_SUB_K + 1,
+ [BPF_ALU|BPF_SUB|BPF_X] = BPF_S_ALU_SUB_X + 1,
+ [BPF_ALU|BPF_MUL|BPF_K] = BPF_S_ALU_MUL_K + 1,
+ [BPF_ALU|BPF_MUL|BPF_X] = BPF_S_ALU_MUL_X + 1,
+ [BPF_ALU|BPF_DIV|BPF_X] = BPF_S_ALU_DIV_X + 1,
+ [BPF_ALU|BPF_AND|BPF_K] = BPF_S_ALU_AND_K + 1,
+ [BPF_ALU|BPF_AND|BPF_X] = BPF_S_ALU_AND_X + 1,
+ [BPF_ALU|BPF_OR|BPF_K] = BPF_S_ALU_OR_K + 1,
+ [BPF_ALU|BPF_OR|BPF_X] = BPF_S_ALU_OR_X + 1,
+ [BPF_ALU|BPF_LSH|BPF_K] = BPF_S_ALU_LSH_K + 1,
+ [BPF_ALU|BPF_LSH|BPF_X] = BPF_S_ALU_LSH_X + 1,
+ [BPF_ALU|BPF_RSH|BPF_K] = BPF_S_ALU_RSH_K + 1,
+ [BPF_ALU|BPF_RSH|BPF_X] = BPF_S_ALU_RSH_X + 1,
+ [BPF_ALU|BPF_NEG] = BPF_S_ALU_NEG + 1,
+ [BPF_LD|BPF_W|BPF_ABS] = BPF_S_LD_W_ABS + 1,
+ [BPF_LD|BPF_H|BPF_ABS] = BPF_S_LD_H_ABS + 1,
+ [BPF_LD|BPF_B|BPF_ABS] = BPF_S_LD_B_ABS + 1,
+ [BPF_LD|BPF_W|BPF_LEN] = BPF_S_LD_W_LEN + 1,
+ [BPF_LD|BPF_W|BPF_IND] = BPF_S_LD_W_IND + 1,
+ [BPF_LD|BPF_H|BPF_IND] = BPF_S_LD_H_IND + 1,
+ [BPF_LD|BPF_B|BPF_IND] = BPF_S_LD_B_IND + 1,
+ [BPF_LD|BPF_IMM] = BPF_S_LD_IMM + 1,
+ [BPF_LDX|BPF_W|BPF_LEN] = BPF_S_LDX_W_LEN + 1,
+ [BPF_LDX|BPF_B|BPF_MSH] = BPF_S_LDX_B_MSH + 1,
+ [BPF_LDX|BPF_IMM] = BPF_S_LDX_IMM + 1,
+ [BPF_MISC|BPF_TAX] = BPF_S_MISC_TAX + 1,
+ [BPF_MISC|BPF_TXA] = BPF_S_MISC_TXA + 1,
+ [BPF_RET|BPF_K] = BPF_S_RET_K + 1,
+ [BPF_RET|BPF_A] = BPF_S_RET_A + 1,
+ [BPF_ALU|BPF_DIV|BPF_K] = BPF_S_ALU_DIV_K + 1,
+ [BPF_LD|BPF_MEM] = BPF_S_LD_MEM + 1,
+ [BPF_LDX|BPF_MEM] = BPF_S_LDX_MEM + 1,
+ [BPF_ST] = BPF_S_ST + 1,
+ [BPF_STX] = BPF_S_STX + 1,
+ [BPF_JMP|BPF_JA] = BPF_S_JMP_JA + 1,
+ [BPF_JMP|BPF_JEQ|BPF_K] = BPF_S_JMP_JEQ_K + 1,
+ [BPF_JMP|BPF_JEQ|BPF_X] = BPF_S_JMP_JEQ_X + 1,
+ [BPF_JMP|BPF_JGE|BPF_K] = BPF_S_JMP_JGE_K + 1,
+ [BPF_JMP|BPF_JGE|BPF_X] = BPF_S_JMP_JGE_X + 1,
+ [BPF_JMP|BPF_JGT|BPF_K] = BPF_S_JMP_JGT_K + 1,
+ [BPF_JMP|BPF_JGT|BPF_X] = BPF_S_JMP_JGT_X + 1,
+ [BPF_JMP|BPF_JSET|BPF_K] = BPF_S_JMP_JSET_K + 1,
+ [BPF_JMP|BPF_JSET|BPF_X] = BPF_S_JMP_JSET_X + 1,
+ };
This was needed because the translated instructions were begining from 0
If we change them to start at offset 1, we can avoid all the "+ 1" :
and avoid the bit ugly :
if (!code--) ...
^ permalink raw reply
* Re: [PATCH v3] filter: Optimize instruction revalidation code.
From: Hagen Paul Pfeifer @ 2010-11-17 9:01 UTC (permalink / raw)
To: Tetsuo Handa; +Cc: eric.dumazet, mjt, davem, drosenberg, xiaosuo, netdev
In-Reply-To: <201011170806.oAH86AdI013337@www262.sakura.ne.jp>
On Wed, 17 Nov 2010 17:06:10 +0900, Tetsuo Handawrote:
> If compilers can generate better code for continuous case values
> than discontinuous case values, then keeping BPF_S_* makes sense.
Yes, this is crucial. A compiler cannot generate a jump table of O(1) for
dense labels. The BPF_S_* translation was done to convert to a dense label
construct. So this "optimization" is a no-go.
Look at the log and read my comment for a detailed explanation.
Anyway: "code--" increments the _copied_ value, not the value in the
evaluated opcode itself. I will validate the patch!
Hagen
^ permalink raw reply
* prize @msn for you
From: msn_customerservice @ 2010-11-17 10:03 UTC (permalink / raw)
[-- Attachment #1: Type: text/plain, Size: 0 bytes --]
[-- Attachment #2: YOU HAVE WON A PRIZE.doc --]
[-- Type: application/msword, Size: 196096 bytes --]
^ permalink raw reply
* Re: [PATCH] net: move definitions of BPF_S_* to net/core/filter.c
From: Hagen Paul Pfeifer @ 2010-11-17 9:10 UTC (permalink / raw)
To: Changli Gao; +Cc: David S. Miller, Tetsuo Handa, Eric Dumazet, netdev
In-Reply-To: <1289975304-19796-1-git-send-email-xiaosuo@gmail.com>
On Wed, 17 Nov 2010 14:28:24 +0800, Changli Gao <xiaosuo@gmail.com> wrote:
> Signed-off-by: Changli Gao <xiaosuo@gmail.com>
Acked-by: Hagen Paul Pfeifer <hagen@jauu.net>
^ permalink raw reply
* Re: [PATCH net-next-2.6 ] can: EG20T PCH: add prefix to macro
From: Marc Kleine-Budde @ 2010-11-17 9:12 UTC (permalink / raw)
To: Tomoya MORINAGA
Cc: Wolfgang Grandegger, David S. Miller, Wolfram Sang,
Christian Pellegrin, Barry Song, Samuel Ortiz, socketcan-core,
netdev, linux-kernel, andrew.chih.howe.khor, qi.wang,
margie.foster, yong.y.wang, kok.howg.ewe, joel.clark
In-Reply-To: <4CE3648D.2070102@dsn.okisemi.com>
[-- Attachment #1: Type: text/plain, Size: 36274 bytes --]
On 11/17/2010 06:13 AM, Tomoya MORINAGA wrote:
> For easy to readable/identifiable, add prefix "PCH_" to all of #define macros.
>
> Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
You broke the indention in some lines, fix it and add my:
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
cheers, Marc
> ---
> drivers/net/can/pch_can.c | 392 ++++++++++++++++++++++-----------------------
> 1 files changed, 190 insertions(+), 202 deletions(-)
>
> diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
> index 6727182..b4bb775 100644
> --- a/drivers/net/can/pch_can.c
> +++ b/drivers/net/can/pch_can.c
> @@ -32,49 +32,48 @@
> #include <linux/can/dev.h>
> #include <linux/can/error.h>
>
> -#define MAX_MSG_OBJ 32
> -#define MSG_OBJ_RX 0 /* The receive message object flag. */
> -#define MSG_OBJ_TX 1 /* The transmit message object flag. */
> -
> -#define ENABLE 1 /* The enable flag */
> -#define DISABLE 0 /* The disable flag */
> -#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
> -#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
> -#define CAN_CTRL_IE_SIE_EIE 0x000e
> -#define CAN_CTRL_CCE 0x0040
> -#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
> -#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
> -#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
> -#define CAN_CMASK_RX_TX_SET 0x00f3
> -#define CAN_CMASK_RX_TX_GET 0x0073
> -#define CAN_CMASK_ALL 0xff
> -#define CAN_CMASK_RDWR 0x80
> -#define CAN_CMASK_ARB 0x20
> -#define CAN_CMASK_CTRL 0x10
> -#define CAN_CMASK_MASK 0x40
> -#define CAN_CMASK_NEWDAT 0x04
> -#define CAN_CMASK_CLRINTPND 0x08
> -
> -#define CAN_IF_MCONT_NEWDAT 0x8000
> -#define CAN_IF_MCONT_INTPND 0x2000
> -#define CAN_IF_MCONT_UMASK 0x1000
> -#define CAN_IF_MCONT_TXIE 0x0800
> -#define CAN_IF_MCONT_RXIE 0x0400
> -#define CAN_IF_MCONT_RMTEN 0x0200
> -#define CAN_IF_MCONT_TXRQXT 0x0100
> -#define CAN_IF_MCONT_EOB 0x0080
> -#define CAN_IF_MCONT_DLC 0x000f
> -#define CAN_IF_MCONT_MSGLOST 0x4000
> -#define CAN_MASK2_MDIR_MXTD 0xc000
> -#define CAN_ID2_DIR 0x2000
> -#define CAN_ID_MSGVAL 0x8000
> -
> -#define CAN_STATUS_INT 0x8000
> -#define CAN_IF_CREQ_BUSY 0x8000
> -#define CAN_ID2_XTD 0x4000
> -
> -#define CAN_REC 0x00007f00
> -#define CAN_TEC 0x000000ff
> +#define PCH_MAX_MSG_OBJ 32
> +#define PCH_MSG_OBJ_RX 0 /* The receive message object flag. */
> +#define PCH_MSG_OBJ_TX 1 /* The transmit message object flag. */
> +
> +#define PCH_ENABLE 1 /* The enable flag */
> +#define PCH_DISABLE 0 /* The disable flag */
^^^ here
> +#define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
> +#define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */
> +#define PCH_CTRL_IE_SIE_EIE 0x000e
> +#define PCH_CTRL_CCE 0x0040
> +#define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
> +#define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
> +#define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
> +#define PCH_CMASK_RX_TX_SET 0x00f3
> +#define PCH_CMASK_RX_TX_GET 0x0073
> +#define PCH_CMASK_ALL 0xff
> +#define PCH_CMASK_RDWR 0x80
> +#define PCH_CMASK_ARB 0x20
> +#define PCH_CMASK_CTRL 0x10
> +#define PCH_CMASK_MASK 0x40
> +#define PCH_CMASK_NEWDAT 0x04
> +#define PCH_CMASK_CLRINTPND 0x08
> +#define PCH_IF_MCONT_NEWDAT 0x8000
> +#define PCH_IF_MCONT_INTPND 0x2000
> +#define PCH_IF_MCONT_UMASK 0x1000
> +#define PCH_IF_MCONT_TXIE 0x0800
> +#define PCH_IF_MCONT_RXIE 0x0400
> +#define PCH_IF_MCONT_RMTEN 0x0200
> +#define PCH_IF_MCONT_TXRQXT 0x0100
> +#define PCH_IF_MCONT_EOB 0x0080
> +#define PCH_IF_MCONT_DLC 0x000f
> +#define PCH_IF_MCONT_MSGLOST 0x4000
> +#define PCH_MASK2_MDIR_MXTD 0xc000
> +#define PCH_ID2_DIR 0x2000
> +#define PCH_ID2_XTD 0x4000
> +#define PCH_ID_MSGVAL 0x8000
> +#define PCH_IF_CREQ_BUSY 0x8000
> +
> +#define PCH_STATUS_INT 0x8000
> +#define PCH_REC 0x00007f00
> +#define PCH_TEC 0x000000ff
> +
>
> #define PCH_RX_OK 0x00000010
> #define PCH_TX_OK 0x00000008
> @@ -93,26 +92,15 @@
> #define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
>
> /* bit position of certain controller bits. */
> -#define BIT_BITT_BRP 0
> -#define BIT_BITT_SJW 6
> -#define BIT_BITT_TSEG1 8
> -#define BIT_BITT_TSEG2 12
> -#define BIT_IF1_MCONT_RXIE 10
> -#define BIT_IF2_MCONT_TXIE 11
> -#define BIT_BRPE_BRPE 6
> -#define BIT_ES_TXERRCNT 0
> -#define BIT_ES_RXERRCNT 8
> -#define MSK_BITT_BRP 0x3f
> -#define MSK_BITT_SJW 0xc0
> -#define MSK_BITT_TSEG1 0xf00
> -#define MSK_BITT_TSEG2 0x7000
> -#define MSK_BRPE_BRPE 0x3c0
> -#define MSK_BRPE_GET 0x0f
> -#define MSK_CTRL_IE_SIE_EIE 0x07
> -#define MSK_MCONT_TXIE 0x08
> -#define MSK_MCONT_RXIE 0x10
> -#define PCH_CAN_NO_TX_BUFF 1
> -#define COUNTER_LIMIT 10
> +#define PCH_BIT_BRP 0
> +#define PCH_BIT_SJW 6
> +#define PCH_BIT_TSEG1 8
> +#define PCH_BIT_TSEG2 12
> +#define PCH_BIT_BRPE_BRPE 6
> +#define PCH_MSK_BITT_BRP 0x3f
> +#define PCH_MSK_BRPE_BRPE 0x3c0
^^^ here
> +#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
> +#define PCH_COUNTER_LIMIT 10
>
> #define PCH_CAN_CLK 50000000 /* 50MHz */
>
> @@ -181,14 +169,14 @@ struct pch_can_priv {
> struct can_priv can;
> unsigned int can_num;
> struct pci_dev *dev;
> - unsigned int tx_enable[MAX_MSG_OBJ];
> - unsigned int rx_enable[MAX_MSG_OBJ];
> - unsigned int rx_link[MAX_MSG_OBJ];
> + unsigned int tx_enable[PCH_MAX_MSG_OBJ];
> + unsigned int rx_enable[PCH_MAX_MSG_OBJ];
> + unsigned int rx_link[PCH_MAX_MSG_OBJ];
> unsigned int int_enables;
> unsigned int int_stat;
> struct net_device *ndev;
> spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
> - unsigned int msg_obj[MAX_MSG_OBJ];
> + unsigned int msg_obj[PCH_MAX_MSG_OBJ];
> struct pch_can_regs __iomem *regs;
> struct napi_struct napi;
> unsigned int tx_obj; /* Point next Tx Obj index */
> @@ -228,11 +216,11 @@ static void pch_can_set_run_mode(struct pch_can_priv *priv,
> {
> switch (mode) {
> case PCH_CAN_RUN:
> - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
> + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
> break;
>
> case PCH_CAN_STOP:
> - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
> + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
> break;
>
> default:
> @@ -246,30 +234,30 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
> u32 reg_val = ioread32(&priv->regs->opt);
>
> if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
> - reg_val |= CAN_OPT_SILENT;
> + reg_val |= PCH_OPT_SILENT;
>
> if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
> - reg_val |= CAN_OPT_LBACK;
> + reg_val |= PCH_OPT_LBACK;
>
> - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
> + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
> iowrite32(reg_val, &priv->regs->opt);
> }
>
> static void pch_can_set_int_custom(struct pch_can_priv *priv)
> {
> /* Clearing the IE, SIE and EIE bits of Can control register. */
> - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
>
> /* Appropriately setting them. */
> pch_can_bit_set(&priv->regs->cont,
> - ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
> + ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
> }
>
> /* This function retrieves interrupt enabled for the CAN device. */
> static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
> {
> /* Obtaining the status of IE, SIE and EIE interrupt bits. */
> - *enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1);
> + *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
> }
>
> static void pch_can_set_int_enables(struct pch_can_priv *priv,
> @@ -277,19 +265,19 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
> {
> switch (interrupt_no) {
> case PCH_CAN_ENABLE:
> - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
> + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
> break;
>
> case PCH_CAN_DISABLE:
> - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
> + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
> break;
>
> case PCH_CAN_ALL:
> - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
> break;
>
> case PCH_CAN_NONE:
> - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
> + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
> break;
>
> default:
> @@ -300,12 +288,12 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
>
> static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
> {
> - u32 counter = COUNTER_LIMIT;
> + u32 counter = PCH_COUNTER_LIMIT;
> u32 ifx_creq;
>
> iowrite32(num, creq_addr);
> while (counter) {
> - ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
> + ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
> if (!ifx_creq)
> break;
> counter--;
> @@ -322,22 +310,22 @@ static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> /* Reading the receive buffer data from RAM to Interface1 registers */
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
>
> /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if1_cmask);
>
> - if (set == ENABLE) {
> + if (set == PCH_ENABLE) {
> /* Setting the MsgVal and RxIE bits */
> - pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
> - pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
> + pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
> + pch_can_bit_set(&priv->regs->if1_id2, PCH_ID_MSGVAL);
>
> - } else if (set == DISABLE) {
> + } else if (set == PCH_DISABLE) {
> /* Resetting the MsgVal and RxIE bits */
> - pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
> - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
> + pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
> + pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID_MSGVAL);
> }
>
> pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
> @@ -350,8 +338,8 @@ static void pch_can_rx_enable_all(struct pch_can_priv *priv)
>
> /* Traversing to obtain the object configured as receivers. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_RX)
> - pch_can_set_rx_enable(priv, i + 1, ENABLE);
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
> + pch_can_set_rx_enable(priv, i + 1, PCH_ENABLE);
> }
> }
>
> @@ -361,8 +349,8 @@ static void pch_can_rx_disable_all(struct pch_can_priv *priv)
>
> /* Traversing to obtain the object configured as receivers. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_RX)
> - pch_can_set_rx_enable(priv, i + 1, DISABLE);
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
> + pch_can_set_rx_enable(priv, i + 1, PCH_DISABLE);
> }
> }
>
> @@ -373,22 +361,22 @@ static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> /* Reading the Msg buffer from Message RAM to Interface2 registers. */
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
>
> /* Setting the IF2CMASK register for accessing the
> MsgVal and TxIE bits */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if2_cmask);
>
> - if (set == ENABLE) {
> + if (set == PCH_ENABLE) {
> /* Setting the MsgVal and TxIE bits */
> - pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
> - pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
> - } else if (set == DISABLE) {
> + pch_can_bit_set(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
> + pch_can_bit_set(&priv->regs->if2_id2, PCH_ID_MSGVAL);
> + } else if (set == PCH_DISABLE) {
> /* Resetting the MsgVal and TxIE bits. */
> - pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
> - pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
> + pch_can_bit_clear(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
> + pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID_MSGVAL);
> }
>
> pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
> @@ -401,8 +389,8 @@ static void pch_can_tx_enable_all(struct pch_can_priv *priv)
>
> /* Traversing to obtain the object configured as transmit object. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_TX)
> - pch_can_set_tx_enable(priv, i + 1, ENABLE);
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
> + pch_can_set_tx_enable(priv, i + 1, PCH_ENABLE);
> }
> }
>
> @@ -412,8 +400,8 @@ static void pch_can_tx_disable_all(struct pch_can_priv *priv)
>
> /* Traversing to obtain the object configured as transmit object. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_TX)
> - pch_can_set_tx_enable(priv, i + 1, DISABLE);
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
> + pch_can_set_tx_enable(priv, i + 1, PCH_DISABLE);
> }
> }
>
> @@ -423,15 +411,15 @@ static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
> unsigned long flags;
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
>
> - if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
> + if (((ioread32(&priv->regs->if1_id2)) & PCH_ID_MSGVAL) &&
> ((ioread32(&priv->regs->if1_mcont)) &
> - CAN_IF_MCONT_RXIE))
> - *enable = ENABLE;
> + PCH_IF_MCONT_RXIE))
> + *enable = PCH_ENABLE;
> else
> - *enable = DISABLE;
> + *enable = PCH_DISABLE;
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> }
>
> @@ -441,15 +429,15 @@ static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
> unsigned long flags;
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
>
> - if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
> + if (((ioread32(&priv->regs->if2_id2)) & PCH_ID_MSGVAL) &&
> ((ioread32(&priv->regs->if2_mcont)) &
> - CAN_IF_MCONT_TXIE)) {
> - *enable = ENABLE;
> + PCH_IF_MCONT_TXIE)) {
> + *enable = PCH_ENABLE;
> } else {
> - *enable = DISABLE;
> + *enable = PCH_DISABLE;
> }
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> }
> @@ -465,13 +453,13 @@ static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
> unsigned long flags;
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
> - if (set == ENABLE)
> - pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, &priv->regs->if1_cmask);
> + if (set == PCH_ENABLE)
> + pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
> else
> - pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
> + pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
>
> pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> @@ -483,13 +471,13 @@ static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
> unsigned long flags;
>
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
>
> - if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
> - *link = DISABLE;
> + if (ioread32(&priv->regs->if1_mcont) & PCH_IF_MCONT_EOB)
> + *link = PCH_DISABLE;
> else
> - *link = ENABLE;
> + *link = PCH_ENABLE;
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> }
>
> @@ -498,7 +486,7 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
> int i;
>
> for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
> - iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
> iowrite32(0xffff, &priv->regs->if1_mask1);
> iowrite32(0xffff, &priv->regs->if1_mask2);
> iowrite32(0x0, &priv->regs->if1_id1);
> @@ -508,14 +496,14 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
> iowrite32(0x0, &priv->regs->if1_dataa2);
> iowrite32(0x0, &priv->regs->if1_datab1);
> iowrite32(0x0, &priv->regs->if1_datab2);
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
> - CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
> + PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
> }
>
> for (i = i; i < PCH_OBJ_NUM; i++) {
> - iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
> + iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
> iowrite32(0xffff, &priv->regs->if2_mask1);
> iowrite32(0xffff, &priv->regs->if2_mask2);
> iowrite32(0x0, &priv->regs->if2_id1);
> @@ -525,8 +513,8 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
> iowrite32(0x0, &priv->regs->if2_dataa2);
> iowrite32(0x0, &priv->regs->if2_datab1);
> iowrite32(0x0, &priv->regs->if2_datab2);
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
> - CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
> + PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
> }
> @@ -540,8 +528,8 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_RX) {
> - iowrite32(CAN_CMASK_RX_TX_GET,
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
> + iowrite32(PCH_CMASK_RX_TX_GET,
> &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
>
> @@ -549,48 +537,48 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
> iowrite32(0x0, &priv->regs->if1_id2);
>
> pch_can_bit_set(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_UMASK);
> + PCH_IF_MCONT_UMASK);
>
> /* Set FIFO mode set to 0 except last Rx Obj*/
> pch_can_bit_clear(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_EOB);
> + PCH_IF_MCONT_EOB);
> /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
> if (i == (PCH_RX_OBJ_NUM - 1))
> pch_can_bit_set(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_EOB);
> + PCH_IF_MCONT_EOB);
>
> iowrite32(0, &priv->regs->if1_mask1);
> pch_can_bit_clear(&priv->regs->if1_mask2,
> - 0x1fff | CAN_MASK2_MDIR_MXTD);
> + 0x1fff | PCH_MASK2_MDIR_MXTD);
>
> /* Setting CMASK for writing */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
> - CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
> + PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if1_cmask);
>
> pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
> - } else if (priv->msg_obj[i] == MSG_OBJ_TX) {
> - iowrite32(CAN_CMASK_RX_TX_GET,
> + } else if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
> + iowrite32(PCH_CMASK_RX_TX_GET,
> &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
>
> /* Resetting DIR bit for reception */
> iowrite32(0x0, &priv->regs->if2_id1);
> iowrite32(0x0, &priv->regs->if2_id2);
> - pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
> + pch_can_bit_set(&priv->regs->if2_id2, PCH_ID2_DIR);
>
> /* Setting EOB bit for transmitter */
> - iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
> + iowrite32(PCH_IF_MCONT_EOB, &priv->regs->if2_mcont);
>
> pch_can_bit_set(&priv->regs->if2_mcont,
> - CAN_IF_MCONT_UMASK);
> + PCH_IF_MCONT_UMASK);
>
> iowrite32(0, &priv->regs->if2_mask1);
> pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
>
> /* Setting CMASK for writing */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
> - CAN_CMASK_ARB | CAN_CMASK_CTRL,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
> + PCH_CMASK_ARB | PCH_CMASK_CTRL,
> &priv->regs->if2_cmask);
>
> pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
> @@ -632,39 +620,39 @@ static void pch_can_release(struct pch_can_priv *priv)
> /* This function clears interrupt(s) from the CAN device. */
> static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
> {
> - if (mask == CAN_STATUS_INT) {
> + if (mask == PCH_STATUS_INT) {
> ioread32(&priv->regs->stat);
> return;
> }
>
> /* Clear interrupt for transmit object */
> - if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) {
> + if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_TX) {
> /* Setting CMASK for clearing interrupts for
> frame transmission. */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
> &priv->regs->if2_cmask);
>
> /* Resetting the ID registers. */
> pch_can_bit_set(&priv->regs->if2_id2,
> - CAN_ID2_DIR | (0x7ff << 2));
> + PCH_ID2_DIR | (0x7ff << 2));
> iowrite32(0x0, &priv->regs->if2_id1);
>
> /* Claring NewDat, TxRqst & IntPnd */
> pch_can_bit_clear(&priv->regs->if2_mcont,
> - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
> - CAN_IF_MCONT_TXRQXT);
> + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
> + PCH_IF_MCONT_TXRQXT);
> pch_can_check_if_busy(&priv->regs->if2_creq, mask);
> - } else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) {
> + } else if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_RX) {
> /* Setting CMASK for clearing the reception interrupts. */
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
> &priv->regs->if1_cmask);
>
> /* Clearing the Dir bit. */
> - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
> + pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
>
> /* Clearing NewDat & IntPnd */
> pch_can_bit_clear(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
> + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
>
> pch_can_check_if_busy(&priv->regs->if1_creq, mask);
> }
> @@ -712,9 +700,9 @@ static void pch_can_error(struct net_device *ndev, u32 status)
> priv->can.can_stats.error_warning++;
> cf->can_id |= CAN_ERR_CRTL;
> errc = ioread32(&priv->regs->errc);
> - if (((errc & CAN_REC) >> 8) > 96)
> + if (((errc & PCH_REC) >> 8) > 96)
> cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
> - if ((errc & CAN_TEC) > 96)
> + if ((errc & PCH_TEC) > 96)
> cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
> dev_warn(&ndev->dev,
> "%s -> Error Counter is more than 96.\n", __func__);
> @@ -725,9 +713,9 @@ static void pch_can_error(struct net_device *ndev, u32 status)
> state = CAN_STATE_ERROR_PASSIVE;
> cf->can_id |= CAN_ERR_CRTL;
> errc = ioread32(&priv->regs->errc);
> - if (((errc & CAN_REC) >> 8) > 127)
> + if (((errc & PCH_REC) >> 8) > 127)
> cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
> - if ((errc & CAN_TEC) > 127)
> + if ((errc & PCH_TEC) > 127)
> cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
> dev_err(&ndev->dev,
> "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
> @@ -795,20 +783,20 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> struct net_device_stats *stats = &(priv->ndev->stats);
>
> /* Reading the messsage object from the Message RAM */
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);
>
> /* Reading the MCONT register. */
> reg = ioread32(&priv->regs->if1_mcont);
> reg &= 0xffff;
>
> - for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) {
> + for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
> /* If MsgLost bit set. */
> - if (reg & CAN_IF_MCONT_MSGLOST) {
> + if (reg & PCH_IF_MCONT_MSGLOST) {
> dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
> pch_can_bit_clear(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_MSGLOST);
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
> + PCH_IF_MCONT_MSGLOST);
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
> &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, k);
>
> @@ -828,7 +816,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> rcv_pkts++;
> goto RX_NEXT;
> }
> - if (!(reg & CAN_IF_MCONT_NEWDAT))
> + if (!(reg & PCH_IF_MCONT_NEWDAT))
> goto RX_NEXT;
>
> skb = alloc_can_skb(priv->ndev, &cf);
> @@ -836,7 +824,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> return -ENOMEM;
>
> /* Get Received data */
> - ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14;
> + ide = ((ioread32(&priv->regs->if1_id2)) & PCH_ID2_XTD) >> 14;
> if (ide) {
> id = (ioread32(&priv->regs->if1_id1) & 0xffff);
> id |= (((ioread32(&priv->regs->if1_id2)) &
> @@ -848,7 +836,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> cf->can_id = (id & CAN_SFF_MASK);
> }
>
> - rtr = (ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR);
> + rtr = (ioread32(&priv->regs->if1_id2) & PCH_ID2_DIR);
> if (rtr) {
> cf->can_dlc = 0;
> cf->can_id |= CAN_RTR_FLAG;
> @@ -871,15 +859,15 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> stats->rx_bytes += cf->can_dlc;
>
> if (k < PCH_FIFO_THRESH) {
> - iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
> - CAN_CMASK_ARB, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
> + PCH_CMASK_ARB, &priv->regs->if1_cmask);
>
> /* Clearing the Dir bit. */
> - pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
> + pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
>
> /* Clearing NewDat & IntPnd */
> pch_can_bit_clear(&priv->regs->if1_mcont,
> - CAN_IF_MCONT_INTPND);
> + PCH_IF_MCONT_INTPND);
> pch_can_check_if_busy(&priv->regs->if1_creq, k);
> } else if (k > PCH_FIFO_THRESH) {
> pch_can_int_clr(priv, k);
> @@ -890,7 +878,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
> }
> RX_NEXT:
> /* Reading the messsage object from the Message RAM */
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
> pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
> reg = ioread32(&priv->regs->if1_mcont);
> }
> @@ -913,7 +901,7 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota)
> return 0;
>
> INT_STAT:
> - if (int_stat == CAN_STATUS_INT) {
> + if (int_stat == PCH_STATUS_INT) {
> reg_stat = ioread32(&priv->regs->stat);
> if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
> if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
> @@ -922,7 +910,7 @@ INT_STAT:
>
> if (reg_stat & PCH_TX_OK) {
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq,
> ioread32(&priv->regs->intr));
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> @@ -933,7 +921,7 @@ INT_STAT:
> pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
>
> int_stat = pch_can_int_pending(priv);
> - if (int_stat == CAN_STATUS_INT)
> + if (int_stat == PCH_STATUS_INT)
> goto INT_STAT;
> }
>
> @@ -945,14 +933,14 @@ MSG_OBJ:
> if (rcv_pkts < 0)
> return 0;
> } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
> - if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) {
> + if (priv->msg_obj[int_stat - 1] == PCH_MSG_OBJ_TX) {
> /* Handle transmission interrupt */
> can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
> - iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
> + iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
> &priv->regs->if2_cmask);
> dlc = ioread32(&priv->regs->if2_mcont) &
> - CAN_IF_MCONT_DLC;
> + PCH_IF_MCONT_DLC;
> pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
> spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
> if (dlc > 8)
> @@ -963,7 +951,7 @@ MSG_OBJ:
> }
>
> int_stat = pch_can_int_pending(priv);
> - if (int_stat == CAN_STATUS_INT)
> + if (int_stat == PCH_STATUS_INT)
> goto INT_STAT;
> else if (int_stat >= 1 && int_stat <= 32)
> goto MSG_OBJ;
> @@ -983,17 +971,17 @@ static int pch_set_bittiming(struct net_device *ndev)
> u32 brp;
>
> /* Setting the CCE bit for accessing the Can Timing register. */
> - pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
> + pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
>
> brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
> - canbit = brp & MSK_BITT_BRP;
> - canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
> - canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
> - canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
> - bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
> + canbit = brp & PCH_MSK_BITT_BRP;
> + canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
> + canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
> + canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
> + bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
> iowrite32(canbit, &priv->regs->bitt);
> iowrite32(bepe, &priv->regs->brpe);
> - pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
> + pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
>
> return 0;
> }
> @@ -1137,19 +1125,19 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
> spin_lock_irqsave(&priv->msgif_reg_lock, flags);
>
> /* Reading the Msg Obj from the Msg RAM to the Interface register. */
> - iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> + iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
> pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
>
> /* Setting the CMASK register. */
> - pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL);
> + pch_can_bit_set(&priv->regs->if2_cmask, PCH_CMASK_ALL);
>
> /* If ID extended is set. */
> pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
> - pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD);
> + pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | PCH_ID2_XTD);
> if (cf->can_id & CAN_EFF_FLAG) {
> pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
> pch_can_bit_set(&priv->regs->if2_id2,
> - ((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD);
> + ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
> } else {
> pch_can_bit_set(&priv->regs->if2_id1, 0);
> pch_can_bit_set(&priv->regs->if2_id2,
> @@ -1158,7 +1146,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
>
> /* If remote frame has to be transmitted.. */
> if (cf->can_id & CAN_RTR_FLAG)
> - pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
> + pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID2_DIR);
>
> for (i = 0, j = 0; i < cf->can_dlc; j++) {
> iowrite32(le32_to_cpu(cf->data[i++]),
> @@ -1177,12 +1165,12 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
>
> /* Clearing IntPend, NewDat & TxRqst */
> pch_can_bit_clear(&priv->regs->if2_mcont,
> - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
> - CAN_IF_MCONT_TXRQXT);
> + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
> + PCH_IF_MCONT_TXRQXT);
>
> /* Setting NewDat, TxRqst bits */
> pch_can_bit_set(&priv->regs->if2_mcont,
> - CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT);
> + PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
>
> pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
>
> @@ -1245,7 +1233,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
>
> /* Save Tx buffer enable state */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_TX)
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
> pch_can_get_tx_enable(priv, i + 1,
> &(priv->tx_enable[i]));
> }
> @@ -1255,7 +1243,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
>
> /* Save Rx buffer enable state */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_RX) {
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
> pch_can_get_rx_enable(priv, i + 1,
> &(priv->rx_enable[i]));
> pch_can_get_rx_buffer_link(priv, i + 1,
> @@ -1313,7 +1301,7 @@ static int pch_can_resume(struct pci_dev *pdev)
>
> /* Enabling the transmit buffer. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_TX) {
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
> pch_can_set_tx_enable(priv, i + 1,
> priv->tx_enable[i]);
> }
> @@ -1321,7 +1309,7 @@ static int pch_can_resume(struct pci_dev *pdev)
>
> /* Configuring the receive buffer and enabling them. */
> for (i = 0; i < PCH_OBJ_NUM; i++) {
> - if (priv->msg_obj[i] == MSG_OBJ_RX) {
> + if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
> /* Restore buffer link */
> pch_can_set_rx_buffer_link(priv, i + 1,
> priv->rx_link[i]);
> @@ -1349,8 +1337,8 @@ static int pch_can_get_berr_counter(const struct net_device *dev,
> {
> struct pch_can_priv *priv = netdev_priv(dev);
>
> - bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
> - bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
> + bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
> + bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
>
> return 0;
> }
> @@ -1410,10 +1398,10 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
>
> priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
> for (index = 0; index < PCH_RX_OBJ_NUM;)
> - priv->msg_obj[index++] = MSG_OBJ_RX;
> + priv->msg_obj[index++] = PCH_MSG_OBJ_RX;
>
> for (index = index; index < PCH_OBJ_NUM;)
> - priv->msg_obj[index++] = MSG_OBJ_TX;
> + priv->msg_obj[index++] = PCH_MSG_OBJ_TX;
>
> netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
>
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 262 bytes --]
^ permalink raw reply
* Re: [RFC PATCH v1 1/2] net: implement mechanism for HW based QOS
From: Thomas Graf @ 2010-11-17 9:18 UTC (permalink / raw)
To: John Fastabend; +Cc: netdev, nhorman, davem
In-Reply-To: <20101117051544.19800.97654.stgit@jf-dev1-dcblab>
On Tue, Nov 16, 2010 at 09:15:45PM -0800, John Fastabend wrote:
> This patch provides a mechanism for lower layer devices to
> steer traffic using skb->priority to tx queues. This allows
> for hardware based QOS schemes to use the default qdisc without
> incurring the penalties related to global state and the qdisc
> lock. While reliably receiving skbs on the correct tx ring
> to avoid head of line blocking resulting from shuffling in
> the LLD. Finally, all the goodness from txq caching and xps/rps
> can still be leveraged.
Nice.
> If this approach seems reasonable I'll go ahead and finish
> this up. The priority to tc mapping should probably be exposed
> to userspace either through sysfs or rtnetlink. Any thoughts?
Please use netlink for this and add a new IFLA_ attribute. I
suggest you put nested attributes into it so you can extend it
later on and/or obsolete attributes:
[IFLA_TC] = {
[IFLA_TC_MAX_TCS]
[IFLA_TC_NUM_TCS]
[IFLA_TC_TXQCOUNT]
[IFLA_TC_TXQOFFSET]
[IFLA_TC_MAP]
}
Or whatever is reasonable to export to userspace.
^ permalink raw reply
* Re: ping -I eth1 ....
From: Joakim Tjernlund @ 2010-11-17 9:29 UTC (permalink / raw)
Cc: Thomas Graf, Eric Dumazet, netdev
In-Reply-To: <OFC0986D69.B0E22D17-ONC12577D6.006B4A38-C12577D6.006B72F9@LocalDomain>
Joakim Tjernlund/Transmode wrote on 2010/11/09 20:33:37:
>
> Joakim Tjernlund/Transmode wrote on 2010/11/06 10:42:46:
> > Thomas Graf <tgr@infradead.org> wrote on 2010/11/05 21:31:50:
> > >
> > > On Fri, Nov 05, 2010 at 04:54:18PM +0100, Joakim Tjernlund wrote:
> > > > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/05 16:06:54:
> > > > >
> > > > > > Hopefully most of that is legacy or just plain wrong? Unless
> > > > > > someone can say why only test IFF_UP one should consider changing them.
> > > > > >
> > > > >
> > > > > Most of the places are hot path.
> > > > >
> > > > > You dont want to replace one test by four tests.
> > > > >
> > > > > _This_ would be wrong :)
> > > >
> > > > Wrong is wrong, even if it is in the hot path :)
> > > > Perhaps it is time define and internal IFF_OPERATIONAL flag
> > > > which is the sum of IFF_UP, IFF_RUNNING etc.? Tht
> > > > way you still get one test in the hot path and can abstract
> > > > what defines an operational link.
> > >
> > > You definitely don't want to have your send() call fail simply because
> > > the carrier was off for a few msec or the routing daemon has put a link
> > > down temporarly. Also, the outgoing interface looked up at routing
> > > decision is not necessarly the interface used for sending in the end.
> > > The packet may get mangled and rerouted by netfilter or tc on the way.
> >
> > But do you handle the case when the link is non operational for a long time?
> >
> > >
> > > Personally I'm even ok with the current behaviour of sendto() while the
> > > socket is bound to an interface but if we choose to return an error
> > > if the interface is down we might as well do so based on the operational
> > > status.
> > Perhaps there is a better way. This all started when pppd hung because
> > of ping -I <ppp interface>, then someone pulled the cable for the on the link.
> >
> > This is a strace where we have two ping -I,
> > ping -I p1-2-1-2-2 .. and ping -I p1-2-3-2-4 ..
> > Notice how pppd hangs for a long time in PPPIOCDETACH
> > As far as I can tell this is due to ping -I has claimed the ppp interfaces
> > and doesn't noticed that the link is down. Ideally ping should receive
> > a ENODEV as soon as pppd calls PPPIOCDETACH.
> >
> > 0.000908 write(0, "Connection terminated.\n", 23) = 23
> > 0.000481 gettimeofday({1288952770, 566048}, NULL) = 0
> > 0.001553 ioctl(7, PPPIOCDETACH
> > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > Brazil kernel: unregister_netdevice: waiting for p1-2-1-2-2 to become free. Usage count = 3
> > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > Brazil kernel: unregister_netdevice: waiting for p1-2-3-2-4 to become free. Usage count = 3
> > Message from syslogd@Brazil at Fri Nov 5 11:26:51 2010 ...
> > Brazil last message repeated 3 times
> > , 0xbfbc3398) = 0
> > 66.559216 connect(9, {sa_family=AF_PPPOX, sa_data="\0\0\0\0\0\0\0\252\273\314\335\356hd"}, 30) = 0
> > 0.000693 close(10) = 0
> > 0.000449 close(7) = 0
> > 0.009801 close(9) = 0
>
> Any comment on this last strace? It is expected that ping -I should
> hold pppd hostage?
>
Ping?
^ permalink raw reply
* Re: ping -I eth1 ....
From: Eric Dumazet @ 2010-11-17 9:51 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Thomas Graf, netdev
In-Reply-To: <OFDE99BE0E.BC2CFBA0-ONC12577DE.00341E5C-C12577DE.00342E2E@transmode.se>
Le mercredi 17 novembre 2010 à 10:29 +0100, Joakim Tjernlund a écrit :
> Joakim Tjernlund/Transmode wrote on 2010/11/09 20:33:37:
> >
> > Joakim Tjernlund/Transmode wrote on 2010/11/06 10:42:46:
> > > Thomas Graf <tgr@infradead.org> wrote on 2010/11/05 21:31:50:
> > > >
> > > > On Fri, Nov 05, 2010 at 04:54:18PM +0100, Joakim Tjernlund wrote:
> > > > > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/05 16:06:54:
> > > > > >
> > > > > > > Hopefully most of that is legacy or just plain wrong? Unless
> > > > > > > someone can say why only test IFF_UP one should consider changing them.
> > > > > > >
> > > > > >
> > > > > > Most of the places are hot path.
> > > > > >
> > > > > > You dont want to replace one test by four tests.
> > > > > >
> > > > > > _This_ would be wrong :)
> > > > >
> > > > > Wrong is wrong, even if it is in the hot path :)
> > > > > Perhaps it is time define and internal IFF_OPERATIONAL flag
> > > > > which is the sum of IFF_UP, IFF_RUNNING etc.? Tht
> > > > > way you still get one test in the hot path and can abstract
> > > > > what defines an operational link.
> > > >
> > > > You definitely don't want to have your send() call fail simply because
> > > > the carrier was off for a few msec or the routing daemon has put a link
> > > > down temporarly. Also, the outgoing interface looked up at routing
> > > > decision is not necessarly the interface used for sending in the end.
> > > > The packet may get mangled and rerouted by netfilter or tc on the way.
> > >
> > > But do you handle the case when the link is non operational for a long time?
> > >
> > > >
> > > > Personally I'm even ok with the current behaviour of sendto() while the
> > > > socket is bound to an interface but if we choose to return an error
> > > > if the interface is down we might as well do so based on the operational
> > > > status.
>
> > > Perhaps there is a better way. This all started when pppd hung because
> > > of ping -I <ppp interface>, then someone pulled the cable for the on the link.
> > >
> > > This is a strace where we have two ping -I,
> > > ping -I p1-2-1-2-2 .. and ping -I p1-2-3-2-4 ..
> > > Notice how pppd hangs for a long time in PPPIOCDETACH
> > > As far as I can tell this is due to ping -I has claimed the ppp interfaces
> > > and doesn't noticed that the link is down. Ideally ping should receive
> > > a ENODEV as soon as pppd calls PPPIOCDETACH.
> > >
> > > 0.000908 write(0, "Connection terminated.\n", 23) = 23
> > > 0.000481 gettimeofday({1288952770, 566048}, NULL) = 0
> > > 0.001553 ioctl(7, PPPIOCDETACH
> > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > Brazil kernel: unregister_netdevice: waiting for p1-2-1-2-2 to become free. Usage count = 3
> > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > Brazil kernel: unregister_netdevice: waiting for p1-2-3-2-4 to become free. Usage count = 3
> > > Message from syslogd@Brazil at Fri Nov 5 11:26:51 2010 ...
> > > Brazil last message repeated 3 times
> > > , 0xbfbc3398) = 0
> > > 66.559216 connect(9, {sa_family=AF_PPPOX, sa_data="\0\0\0\0\0\0\0\252\273\314\335\356hd"}, 30) = 0
> > > 0.000693 close(10) = 0
> > > 0.000449 close(7) = 0
> > > 0.009801 close(9) = 0
> >
> > Any comment on this last strace? It is expected that ping -I should
> > hold pppd hostage?
> >
>
> Ping?
>
I thought I posted a patch, is there something else ?
Could you please test with latest net-next-2.6 and following patch ?
Thanks
[PATCH net-next-2.6] ipv4: dont create a route if device is down
ip_route_output_slow() should not create a route if device is down, so
that we report -ENETUNREACH error to users.
Reported-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Reported-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
---
net/ipv4/route.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 66610ea..3cc4191 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -2559,8 +2559,11 @@ static int ip_route_output_slow(struct net *net, struct rtable **rp,
goto out;
/* RACE: Check return value of inet_select_addr instead. */
- if (rcu_dereference(dev_out->ip_ptr) == NULL)
- goto out; /* Wrong error code */
+ if (!(dev_out->flags & IFF_UP) ||
+ rcu_dereference(dev_out->ip_ptr) == NULL) {
+ err = -ENETUNREACH;
+ goto out;
+ }
if (ipv4_is_local_multicast(oldflp->fl4_dst) ||
ipv4_is_lbcast(oldflp->fl4_dst)) {
^ permalink raw reply related
* Re: ping -I eth1 ....
From: Joakim Tjernlund @ 2010-11-17 10:09 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, Thomas Graf
In-Reply-To: <1289987467.2687.15.camel@edumazet-laptop>
Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/17 10:51:07:
>
> Le mercredi 17 novembre 2010 à 10:29 +0100, Joakim Tjernlund a écrit :
> > Joakim Tjernlund/Transmode wrote on 2010/11/09 20:33:37:
> > >
> > > Joakim Tjernlund/Transmode wrote on 2010/11/06 10:42:46:
> > > > Thomas Graf <tgr@infradead.org> wrote on 2010/11/05 21:31:50:
> > > > >
> > > > > On Fri, Nov 05, 2010 at 04:54:18PM +0100, Joakim Tjernlund wrote:
> > > > > > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/05 16:06:54:
> > > > > > >
> > > > > > > > Hopefully most of that is legacy or just plain wrong? Unless
> > > > > > > > someone can say why only test IFF_UP one should consider changing them.
> > > > > > > >
> > > > > > >
> > > > > > > Most of the places are hot path.
> > > > > > >
> > > > > > > You dont want to replace one test by four tests.
> > > > > > >
> > > > > > > _This_ would be wrong :)
> > > > > >
> > > > > > Wrong is wrong, even if it is in the hot path :)
> > > > > > Perhaps it is time define and internal IFF_OPERATIONAL flag
> > > > > > which is the sum of IFF_UP, IFF_RUNNING etc.? Tht
> > > > > > way you still get one test in the hot path and can abstract
> > > > > > what defines an operational link.
> > > > >
> > > > > You definitely don't want to have your send() call fail simply because
> > > > > the carrier was off for a few msec or the routing daemon has put a link
> > > > > down temporarly. Also, the outgoing interface looked up at routing
> > > > > decision is not necessarly the interface used for sending in the end.
> > > > > The packet may get mangled and rerouted by netfilter or tc on the way.
> > > >
> > > > But do you handle the case when the link is non operational for a long time?
> > > >
> > > > >
> > > > > Personally I'm even ok with the current behaviour of sendto() while the
> > > > > socket is bound to an interface but if we choose to return an error
> > > > > if the interface is down we might as well do so based on the operational
> > > > > status.
> >
> > > > Perhaps there is a better way. This all started when pppd hung because
> > > > of ping -I <ppp interface>, then someone pulled the cable for the on the link.
> > > >
> > > > This is a strace where we have two ping -I,
> > > > ping -I p1-2-1-2-2 .. and ping -I p1-2-3-2-4 ..
> > > > Notice how pppd hangs for a long time in PPPIOCDETACH
> > > > As far as I can tell this is due to ping -I has claimed the ppp interfaces
> > > > and doesn't noticed that the link is down. Ideally ping should receive
> > > > a ENODEV as soon as pppd calls PPPIOCDETACH.
> > > >
> > > > 0.000908 write(0, "Connection terminated.\n", 23) = 23
> > > > 0.000481 gettimeofday({1288952770, 566048}, NULL) = 0
> > > > 0.001553 ioctl(7, PPPIOCDETACH
> > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > Brazil kernel: unregister_netdevice: waiting for p1-2-1-2-2 to become free. Usage count = 3
> > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > Brazil kernel: unregister_netdevice: waiting for p1-2-3-2-4 to become free. Usage count = 3
> > > > Message from syslogd@Brazil at Fri Nov 5 11:26:51 2010 ...
> > > > Brazil last message repeated 3 times
> > > > , 0xbfbc3398) = 0
> > > > 66.559216 connect(9, {sa_family=AF_PPPOX, sa_data="\0\0\0\0\0\0\0\252\273\314\335\356hd"}, 30) = 0
> > > > 0.000693 close(10) = 0
> > > > 0.000449 close(7) = 0
> > > > 0.009801 close(9) = 0
> > >
> > > Any comment on this last strace? It is expected that ping -I should
> > > hold pppd hostage?
> > >
> >
> > Ping?
> >
>
> I thought I posted a patch, is there something else ?
yes, I wondered about the above strace and if it is expected that ping -I
should hold pppd hostage? Should not ping receive a ENODEV as soon as
pppd detaches an interface?
>
> Could you please test with latest net-next-2.6 and following patch ?
I tested the first patch you sent and that one worked well. I can try
again on 2.6.35( our boards takes a while to move forward)?
>
>
> Thanks
>
> [PATCH net-next-2.6] ipv4: dont create a route if device is down
>
> ip_route_output_slow() should not create a route if device is down, so
> that we report -ENETUNREACH error to users.
>
> Reported-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
> Reported-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
> ---
> net/ipv4/route.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/net/ipv4/route.c b/net/ipv4/route.c
> index 66610ea..3cc4191 100644
> --- a/net/ipv4/route.c
> +++ b/net/ipv4/route.c
> @@ -2559,8 +2559,11 @@ static int ip_route_output_slow(struct net *net, struct rtable **rp,
> goto out;
>
> /* RACE: Check return value of inet_select_addr instead. */
> - if (rcu_dereference(dev_out->ip_ptr) == NULL)
> - goto out; /* Wrong error code */
> + if (!(dev_out->flags & IFF_UP) ||
> + rcu_dereference(dev_out->ip_ptr) == NULL) {
> + err = -ENETUNREACH;
> + goto out;
> + }
>
> if (ipv4_is_local_multicast(oldflp->fl4_dst) ||
> ipv4_is_lbcast(oldflp->fl4_dst)) {
>
>
^ permalink raw reply
* Re: ping -I eth1 ....
From: Eric Dumazet @ 2010-11-17 10:23 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: netdev, Thomas Graf
In-Reply-To: <OF76197EA2.D5EFE8B7-ONC12577DE.0036FE30-C12577DE.0037C54E@transmode.se>
Le mercredi 17 novembre 2010 à 11:09 +0100, Joakim Tjernlund a écrit :
> Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/17 10:51:07:
> >
> > Le mercredi 17 novembre 2010 à 10:29 +0100, Joakim Tjernlund a écrit :
> > > Joakim Tjernlund/Transmode wrote on 2010/11/09 20:33:37:
> > > >
> > > > Joakim Tjernlund/Transmode wrote on 2010/11/06 10:42:46:
> > > > > Thomas Graf <tgr@infradead.org> wrote on 2010/11/05 21:31:50:
> > > > > >
> > > > > > On Fri, Nov 05, 2010 at 04:54:18PM +0100, Joakim Tjernlund wrote:
> > > > > > > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/05 16:06:54:
> > > > > > > >
> > > > > > > > > Hopefully most of that is legacy or just plain wrong? Unless
> > > > > > > > > someone can say why only test IFF_UP one should consider changing them.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Most of the places are hot path.
> > > > > > > >
> > > > > > > > You dont want to replace one test by four tests.
> > > > > > > >
> > > > > > > > _This_ would be wrong :)
> > > > > > >
> > > > > > > Wrong is wrong, even if it is in the hot path :)
> > > > > > > Perhaps it is time define and internal IFF_OPERATIONAL flag
> > > > > > > which is the sum of IFF_UP, IFF_RUNNING etc.? Tht
> > > > > > > way you still get one test in the hot path and can abstract
> > > > > > > what defines an operational link.
> > > > > >
> > > > > > You definitely don't want to have your send() call fail simply because
> > > > > > the carrier was off for a few msec or the routing daemon has put a link
> > > > > > down temporarly. Also, the outgoing interface looked up at routing
> > > > > > decision is not necessarly the interface used for sending in the end.
> > > > > > The packet may get mangled and rerouted by netfilter or tc on the way.
> > > > >
> > > > > But do you handle the case when the link is non operational for a long time?
> > > > >
> > > > > >
> > > > > > Personally I'm even ok with the current behaviour of sendto() while the
> > > > > > socket is bound to an interface but if we choose to return an error
> > > > > > if the interface is down we might as well do so based on the operational
> > > > > > status.
> > >
> > > > > Perhaps there is a better way. This all started when pppd hung because
> > > > > of ping -I <ppp interface>, then someone pulled the cable for the on the link.
> > > > >
> > > > > This is a strace where we have two ping -I,
> > > > > ping -I p1-2-1-2-2 .. and ping -I p1-2-3-2-4 ..
> > > > > Notice how pppd hangs for a long time in PPPIOCDETACH
> > > > > As far as I can tell this is due to ping -I has claimed the ppp interfaces
> > > > > and doesn't noticed that the link is down. Ideally ping should receive
> > > > > a ENODEV as soon as pppd calls PPPIOCDETACH.
> > > > >
> > > > > 0.000908 write(0, "Connection terminated.\n", 23) = 23
> > > > > 0.000481 gettimeofday({1288952770, 566048}, NULL) = 0
> > > > > 0.001553 ioctl(7, PPPIOCDETACH
> > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > > Brazil kernel: unregister_netdevice: waiting for p1-2-1-2-2 to become free. Usage count = 3
> > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > > Brazil kernel: unregister_netdevice: waiting for p1-2-3-2-4 to become free. Usage count = 3
> > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:51 2010 ...
> > > > > Brazil last message repeated 3 times
> > > > > , 0xbfbc3398) = 0
> > > > > 66.559216 connect(9, {sa_family=AF_PPPOX, sa_data="\0\0\0\0\0\0\0\252\273\314\335\356hd"}, 30) = 0
> > > > > 0.000693 close(10) = 0
> > > > > 0.000449 close(7) = 0
> > > > > 0.009801 close(9) = 0
> > > >
> > > > Any comment on this last strace? It is expected that ping -I should
> > > > hold pppd hostage?
> > > >
> > >
> > > Ping?
> > >
> >
> > I thought I posted a patch, is there something else ?
>
> yes, I wondered about the above strace and if it is expected that ping -I
> should hold pppd hostage? Should not ping receive a ENODEV as soon as
> pppd detaches an interface?
>
> >
> > Could you please test with latest net-next-2.6 and following patch ?
>
> I tested the first patch you sent and that one worked well. I can try
> again on 2.6.35( our boards takes a while to move forward)?
Well, in this case, apply commit :
332dd96f7ac15e937088fe11f15cfe0210e8edd1
(net/dst: dst_dev_event() called after other notifiers)
http://git2.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=332dd96f7ac15e937088fe11f15cfe0210e8edd1
^ permalink raw reply
* [PATCH net-next-2.6 v2] can: EG20T PCH: add prefix to macro
From: Tomoya MORINAGA @ 2010-11-17 11:13 UTC (permalink / raw)
To: Wolfgang Grandegger, David S. Miller, Wolfram Sang,
Christian Pellegrin, Barry Song
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
For easy to readable/identifiable, add prefix "PCH_" to all of #define macros.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/net/can/pch_can.c | 391 ++++++++++++++++++++++-----------------------
1 files changed, 189 insertions(+), 202 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 6727182..c523e3d 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -32,49 +32,47 @@
#include <linux/can/dev.h>
#include <linux/can/error.h>
-#define MAX_MSG_OBJ 32
-#define MSG_OBJ_RX 0 /* The receive message object flag. */
-#define MSG_OBJ_TX 1 /* The transmit message object flag. */
-
-#define ENABLE 1 /* The enable flag */
-#define DISABLE 0 /* The disable flag */
-#define CAN_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
-#define CAN_CTRL_IE 0x0002 /* The IE bit of CAN control register */
-#define CAN_CTRL_IE_SIE_EIE 0x000e
-#define CAN_CTRL_CCE 0x0040
-#define CAN_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
-#define CAN_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
-#define CAN_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
-#define CAN_CMASK_RX_TX_SET 0x00f3
-#define CAN_CMASK_RX_TX_GET 0x0073
-#define CAN_CMASK_ALL 0xff
-#define CAN_CMASK_RDWR 0x80
-#define CAN_CMASK_ARB 0x20
-#define CAN_CMASK_CTRL 0x10
-#define CAN_CMASK_MASK 0x40
-#define CAN_CMASK_NEWDAT 0x04
-#define CAN_CMASK_CLRINTPND 0x08
-
-#define CAN_IF_MCONT_NEWDAT 0x8000
-#define CAN_IF_MCONT_INTPND 0x2000
-#define CAN_IF_MCONT_UMASK 0x1000
-#define CAN_IF_MCONT_TXIE 0x0800
-#define CAN_IF_MCONT_RXIE 0x0400
-#define CAN_IF_MCONT_RMTEN 0x0200
-#define CAN_IF_MCONT_TXRQXT 0x0100
-#define CAN_IF_MCONT_EOB 0x0080
-#define CAN_IF_MCONT_DLC 0x000f
-#define CAN_IF_MCONT_MSGLOST 0x4000
-#define CAN_MASK2_MDIR_MXTD 0xc000
-#define CAN_ID2_DIR 0x2000
-#define CAN_ID_MSGVAL 0x8000
-
-#define CAN_STATUS_INT 0x8000
-#define CAN_IF_CREQ_BUSY 0x8000
-#define CAN_ID2_XTD 0x4000
-
-#define CAN_REC 0x00007f00
-#define CAN_TEC 0x000000ff
+#define PCH_MAX_MSG_OBJ 32
+#define PCH_MSG_OBJ_RX 0 /* The receive message object flag. */
+#define PCH_MSG_OBJ_TX 1 /* The transmit message object flag. */
+
+#define PCH_ENABLE 1 /* The enable flag */
+#define PCH_DISABLE 0 /* The disable flag */
+#define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
+#define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */
+#define PCH_CTRL_IE_SIE_EIE 0x000e
+#define PCH_CTRL_CCE 0x0040
+#define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
+#define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
+#define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
+#define PCH_CMASK_RX_TX_SET 0x00f3
+#define PCH_CMASK_RX_TX_GET 0x0073
+#define PCH_CMASK_ALL 0xff
+#define PCH_CMASK_RDWR 0x80
+#define PCH_CMASK_ARB 0x20
+#define PCH_CMASK_CTRL 0x10
+#define PCH_CMASK_MASK 0x40
+#define PCH_CMASK_NEWDAT 0x04
+#define PCH_CMASK_CLRINTPND 0x08
+#define PCH_IF_MCONT_NEWDAT 0x8000
+#define PCH_IF_MCONT_INTPND 0x2000
+#define PCH_IF_MCONT_UMASK 0x1000
+#define PCH_IF_MCONT_TXIE 0x0800
+#define PCH_IF_MCONT_RXIE 0x0400
+#define PCH_IF_MCONT_RMTEN 0x0200
+#define PCH_IF_MCONT_TXRQXT 0x0100
+#define PCH_IF_MCONT_EOB 0x0080
+#define PCH_IF_MCONT_DLC 0x000f
+#define PCH_IF_MCONT_MSGLOST 0x4000
+#define PCH_MASK2_MDIR_MXTD 0xc000
+#define PCH_ID2_DIR 0x2000
+#define PCH_ID2_XTD 0x4000
+#define PCH_ID_MSGVAL 0x8000
+#define PCH_IF_CREQ_BUSY 0x8000
+
+#define PCH_STATUS_INT 0x8000
+#define PCH_REC 0x00007f00
+#define PCH_TEC 0x000000ff
#define PCH_RX_OK 0x00000010
#define PCH_TX_OK 0x00000008
@@ -93,26 +91,15 @@
#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
/* bit position of certain controller bits. */
-#define BIT_BITT_BRP 0
-#define BIT_BITT_SJW 6
-#define BIT_BITT_TSEG1 8
-#define BIT_BITT_TSEG2 12
-#define BIT_IF1_MCONT_RXIE 10
-#define BIT_IF2_MCONT_TXIE 11
-#define BIT_BRPE_BRPE 6
-#define BIT_ES_TXERRCNT 0
-#define BIT_ES_RXERRCNT 8
-#define MSK_BITT_BRP 0x3f
-#define MSK_BITT_SJW 0xc0
-#define MSK_BITT_TSEG1 0xf00
-#define MSK_BITT_TSEG2 0x7000
-#define MSK_BRPE_BRPE 0x3c0
-#define MSK_BRPE_GET 0x0f
-#define MSK_CTRL_IE_SIE_EIE 0x07
-#define MSK_MCONT_TXIE 0x08
-#define MSK_MCONT_RXIE 0x10
-#define PCH_CAN_NO_TX_BUFF 1
-#define COUNTER_LIMIT 10
+#define PCH_BIT_BRP 0
+#define PCH_BIT_SJW 6
+#define PCH_BIT_TSEG1 8
+#define PCH_BIT_TSEG2 12
+#define PCH_BIT_BRPE_BRPE 6
+#define PCH_MSK_BITT_BRP 0x3f
+#define PCH_MSK_BRPE_BRPE 0x3c0
+#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
+#define PCH_COUNTER_LIMIT 10
#define PCH_CAN_CLK 50000000 /* 50MHz */
@@ -181,14 +168,14 @@ struct pch_can_priv {
struct can_priv can;
unsigned int can_num;
struct pci_dev *dev;
- unsigned int tx_enable[MAX_MSG_OBJ];
- unsigned int rx_enable[MAX_MSG_OBJ];
- unsigned int rx_link[MAX_MSG_OBJ];
+ unsigned int tx_enable[PCH_MAX_MSG_OBJ];
+ unsigned int rx_enable[PCH_MAX_MSG_OBJ];
+ unsigned int rx_link[PCH_MAX_MSG_OBJ];
unsigned int int_enables;
unsigned int int_stat;
struct net_device *ndev;
spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
- unsigned int msg_obj[MAX_MSG_OBJ];
+ unsigned int msg_obj[PCH_MAX_MSG_OBJ];
struct pch_can_regs __iomem *regs;
struct napi_struct napi;
unsigned int tx_obj; /* Point next Tx Obj index */
@@ -228,11 +215,11 @@ static void pch_can_set_run_mode(struct pch_can_priv *priv,
{
switch (mode) {
case PCH_CAN_RUN:
- pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
break;
case PCH_CAN_STOP:
- pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
+ pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
break;
default:
@@ -246,30 +233,30 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
u32 reg_val = ioread32(&priv->regs->opt);
if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
- reg_val |= CAN_OPT_SILENT;
+ reg_val |= PCH_OPT_SILENT;
if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
- reg_val |= CAN_OPT_LBACK;
+ reg_val |= PCH_OPT_LBACK;
- pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
+ pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
iowrite32(reg_val, &priv->regs->opt);
}
static void pch_can_set_int_custom(struct pch_can_priv *priv)
{
/* Clearing the IE, SIE and EIE bits of Can control register. */
- pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
/* Appropriately setting them. */
pch_can_bit_set(&priv->regs->cont,
- ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
+ ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
}
/* This function retrieves interrupt enabled for the CAN device. */
static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
{
/* Obtaining the status of IE, SIE and EIE interrupt bits. */
- *enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1);
+ *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
}
static void pch_can_set_int_enables(struct pch_can_priv *priv,
@@ -277,19 +264,19 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
{
switch (interrupt_no) {
case PCH_CAN_ENABLE:
- pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
+ pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
break;
case PCH_CAN_DISABLE:
- pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
break;
case PCH_CAN_ALL:
- pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+ pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
break;
case PCH_CAN_NONE:
- pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
break;
default:
@@ -300,12 +287,12 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
{
- u32 counter = COUNTER_LIMIT;
+ u32 counter = PCH_COUNTER_LIMIT;
u32 ifx_creq;
iowrite32(num, creq_addr);
while (counter) {
- ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
+ ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
if (!ifx_creq)
break;
counter--;
@@ -322,22 +309,22 @@ static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
/* Reading the receive buffer data from RAM to Interface1 registers */
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
/* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if1_cmask);
- if (set == ENABLE) {
+ if (set == PCH_ENABLE) {
/* Setting the MsgVal and RxIE bits */
- pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
- pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
+ pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
+ pch_can_bit_set(&priv->regs->if1_id2, PCH_ID_MSGVAL);
- } else if (set == DISABLE) {
+ } else if (set == PCH_DISABLE) {
/* Resetting the MsgVal and RxIE bits */
- pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
- pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
+ pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
+ pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID_MSGVAL);
}
pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
@@ -350,8 +337,8 @@ static void pch_can_rx_enable_all(struct pch_can_priv *priv)
/* Traversing to obtain the object configured as receivers. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_RX)
- pch_can_set_rx_enable(priv, i + 1, ENABLE);
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
+ pch_can_set_rx_enable(priv, i + 1, PCH_ENABLE);
}
}
@@ -361,8 +348,8 @@ static void pch_can_rx_disable_all(struct pch_can_priv *priv)
/* Traversing to obtain the object configured as receivers. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_RX)
- pch_can_set_rx_enable(priv, i + 1, DISABLE);
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
+ pch_can_set_rx_enable(priv, i + 1, PCH_DISABLE);
}
}
@@ -373,22 +360,22 @@ static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
/* Reading the Msg buffer from Message RAM to Interface2 registers. */
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
/* Setting the IF2CMASK register for accessing the
MsgVal and TxIE bits */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if2_cmask);
- if (set == ENABLE) {
+ if (set == PCH_ENABLE) {
/* Setting the MsgVal and TxIE bits */
- pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
- pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
- } else if (set == DISABLE) {
+ pch_can_bit_set(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
+ pch_can_bit_set(&priv->regs->if2_id2, PCH_ID_MSGVAL);
+ } else if (set == PCH_DISABLE) {
/* Resetting the MsgVal and TxIE bits. */
- pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
- pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
+ pch_can_bit_clear(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
+ pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID_MSGVAL);
}
pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
@@ -401,8 +388,8 @@ static void pch_can_tx_enable_all(struct pch_can_priv *priv)
/* Traversing to obtain the object configured as transmit object. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_TX)
- pch_can_set_tx_enable(priv, i + 1, ENABLE);
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
+ pch_can_set_tx_enable(priv, i + 1, PCH_ENABLE);
}
}
@@ -412,8 +399,8 @@ static void pch_can_tx_disable_all(struct pch_can_priv *priv)
/* Traversing to obtain the object configured as transmit object. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_TX)
- pch_can_set_tx_enable(priv, i + 1, DISABLE);
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
+ pch_can_set_tx_enable(priv, i + 1, PCH_DISABLE);
}
}
@@ -423,15 +410,15 @@ static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
unsigned long flags;
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
- if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
+ if (((ioread32(&priv->regs->if1_id2)) & PCH_ID_MSGVAL) &&
((ioread32(&priv->regs->if1_mcont)) &
- CAN_IF_MCONT_RXIE))
- *enable = ENABLE;
+ PCH_IF_MCONT_RXIE))
+ *enable = PCH_ENABLE;
else
- *enable = DISABLE;
+ *enable = PCH_DISABLE;
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
@@ -441,15 +428,15 @@ static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
unsigned long flags;
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
- if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
+ if (((ioread32(&priv->regs->if2_id2)) & PCH_ID_MSGVAL) &&
((ioread32(&priv->regs->if2_mcont)) &
- CAN_IF_MCONT_TXIE)) {
- *enable = ENABLE;
+ PCH_IF_MCONT_TXIE)) {
+ *enable = PCH_ENABLE;
} else {
- *enable = DISABLE;
+ *enable = PCH_DISABLE;
}
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
@@ -465,13 +452,13 @@ static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
unsigned long flags;
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
- if (set == ENABLE)
- pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, &priv->regs->if1_cmask);
+ if (set == PCH_ENABLE)
+ pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
else
- pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
+ pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
@@ -483,13 +470,13 @@ static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
unsigned long flags;
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
- if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
- *link = DISABLE;
+ if (ioread32(&priv->regs->if1_mcont) & PCH_IF_MCONT_EOB)
+ *link = PCH_DISABLE;
else
- *link = ENABLE;
+ *link = PCH_ENABLE;
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
@@ -498,7 +485,7 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
int i;
for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
- iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
iowrite32(0xffff, &priv->regs->if1_mask1);
iowrite32(0xffff, &priv->regs->if1_mask2);
iowrite32(0x0, &priv->regs->if1_id1);
@@ -508,14 +495,14 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
iowrite32(0x0, &priv->regs->if1_dataa2);
iowrite32(0x0, &priv->regs->if1_datab1);
iowrite32(0x0, &priv->regs->if1_datab2);
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
- CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
+ PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
}
for (i = i; i < PCH_OBJ_NUM; i++) {
- iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
+ iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
iowrite32(0xffff, &priv->regs->if2_mask1);
iowrite32(0xffff, &priv->regs->if2_mask2);
iowrite32(0x0, &priv->regs->if2_id1);
@@ -525,8 +512,8 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
iowrite32(0x0, &priv->regs->if2_dataa2);
iowrite32(0x0, &priv->regs->if2_datab1);
iowrite32(0x0, &priv->regs->if2_datab2);
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
- CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
+ PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
}
@@ -540,8 +527,8 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_RX) {
- iowrite32(CAN_CMASK_RX_TX_GET,
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
+ iowrite32(PCH_CMASK_RX_TX_GET,
&priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
@@ -549,48 +536,48 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
iowrite32(0x0, &priv->regs->if1_id2);
pch_can_bit_set(&priv->regs->if1_mcont,
- CAN_IF_MCONT_UMASK);
+ PCH_IF_MCONT_UMASK);
/* Set FIFO mode set to 0 except last Rx Obj*/
pch_can_bit_clear(&priv->regs->if1_mcont,
- CAN_IF_MCONT_EOB);
+ PCH_IF_MCONT_EOB);
/* In case FIFO mode, Last EoB of Rx Obj must be 1 */
if (i == (PCH_RX_OBJ_NUM - 1))
pch_can_bit_set(&priv->regs->if1_mcont,
- CAN_IF_MCONT_EOB);
+ PCH_IF_MCONT_EOB);
iowrite32(0, &priv->regs->if1_mask1);
pch_can_bit_clear(&priv->regs->if1_mask2,
- 0x1fff | CAN_MASK2_MDIR_MXTD);
+ 0x1fff | PCH_MASK2_MDIR_MXTD);
/* Setting CMASK for writing */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
- CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
+ PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
- } else if (priv->msg_obj[i] == MSG_OBJ_TX) {
- iowrite32(CAN_CMASK_RX_TX_GET,
+ } else if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
+ iowrite32(PCH_CMASK_RX_TX_GET,
&priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
/* Resetting DIR bit for reception */
iowrite32(0x0, &priv->regs->if2_id1);
iowrite32(0x0, &priv->regs->if2_id2);
- pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
+ pch_can_bit_set(&priv->regs->if2_id2, PCH_ID2_DIR);
/* Setting EOB bit for transmitter */
- iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
+ iowrite32(PCH_IF_MCONT_EOB, &priv->regs->if2_mcont);
pch_can_bit_set(&priv->regs->if2_mcont,
- CAN_IF_MCONT_UMASK);
+ PCH_IF_MCONT_UMASK);
iowrite32(0, &priv->regs->if2_mask1);
pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
/* Setting CMASK for writing */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
- CAN_CMASK_ARB | CAN_CMASK_CTRL,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
+ PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
@@ -632,39 +619,39 @@ static void pch_can_release(struct pch_can_priv *priv)
/* This function clears interrupt(s) from the CAN device. */
static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
{
- if (mask == CAN_STATUS_INT) {
+ if (mask == PCH_STATUS_INT) {
ioread32(&priv->regs->stat);
return;
}
/* Clear interrupt for transmit object */
- if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) {
+ if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_TX) {
/* Setting CMASK for clearing interrupts for
frame transmission. */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
&priv->regs->if2_cmask);
/* Resetting the ID registers. */
pch_can_bit_set(&priv->regs->if2_id2,
- CAN_ID2_DIR | (0x7ff << 2));
+ PCH_ID2_DIR | (0x7ff << 2));
iowrite32(0x0, &priv->regs->if2_id1);
/* Claring NewDat, TxRqst & IntPnd */
pch_can_bit_clear(&priv->regs->if2_mcont,
- CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
- CAN_IF_MCONT_TXRQXT);
+ PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
+ PCH_IF_MCONT_TXRQXT);
pch_can_check_if_busy(&priv->regs->if2_creq, mask);
- } else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) {
+ } else if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_RX) {
/* Setting CMASK for clearing the reception interrupts. */
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
&priv->regs->if1_cmask);
/* Clearing the Dir bit. */
- pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
+ pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
/* Clearing NewDat & IntPnd */
pch_can_bit_clear(&priv->regs->if1_mcont,
- CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
+ PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
pch_can_check_if_busy(&priv->regs->if1_creq, mask);
}
@@ -712,9 +699,9 @@ static void pch_can_error(struct net_device *ndev, u32 status)
priv->can.can_stats.error_warning++;
cf->can_id |= CAN_ERR_CRTL;
errc = ioread32(&priv->regs->errc);
- if (((errc & CAN_REC) >> 8) > 96)
+ if (((errc & PCH_REC) >> 8) > 96)
cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
- if ((errc & CAN_TEC) > 96)
+ if ((errc & PCH_TEC) > 96)
cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
dev_warn(&ndev->dev,
"%s -> Error Counter is more than 96.\n", __func__);
@@ -725,9 +712,9 @@ static void pch_can_error(struct net_device *ndev, u32 status)
state = CAN_STATE_ERROR_PASSIVE;
cf->can_id |= CAN_ERR_CRTL;
errc = ioread32(&priv->regs->errc);
- if (((errc & CAN_REC) >> 8) > 127)
+ if (((errc & PCH_REC) >> 8) > 127)
cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
- if ((errc & CAN_TEC) > 127)
+ if ((errc & PCH_TEC) > 127)
cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
dev_err(&ndev->dev,
"%s -> CAN controller is ERROR PASSIVE .\n", __func__);
@@ -795,20 +782,20 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
struct net_device_stats *stats = &(priv->ndev->stats);
/* Reading the messsage object from the Message RAM */
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);
/* Reading the MCONT register. */
reg = ioread32(&priv->regs->if1_mcont);
reg &= 0xffff;
- for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) {
+ for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
/* If MsgLost bit set. */
- if (reg & CAN_IF_MCONT_MSGLOST) {
+ if (reg & PCH_IF_MCONT_MSGLOST) {
dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
pch_can_bit_clear(&priv->regs->if1_mcont,
- CAN_IF_MCONT_MSGLOST);
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
+ PCH_IF_MCONT_MSGLOST);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
&priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, k);
@@ -828,7 +815,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
rcv_pkts++;
goto RX_NEXT;
}
- if (!(reg & CAN_IF_MCONT_NEWDAT))
+ if (!(reg & PCH_IF_MCONT_NEWDAT))
goto RX_NEXT;
skb = alloc_can_skb(priv->ndev, &cf);
@@ -836,7 +823,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
return -ENOMEM;
/* Get Received data */
- ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14;
+ ide = ((ioread32(&priv->regs->if1_id2)) & PCH_ID2_XTD) >> 14;
if (ide) {
id = (ioread32(&priv->regs->if1_id1) & 0xffff);
id |= (((ioread32(&priv->regs->if1_id2)) &
@@ -848,7 +835,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
cf->can_id = (id & CAN_SFF_MASK);
}
- rtr = (ioread32(&priv->regs->if1_id2) & CAN_ID2_DIR);
+ rtr = (ioread32(&priv->regs->if1_id2) & PCH_ID2_DIR);
if (rtr) {
cf->can_dlc = 0;
cf->can_id |= CAN_RTR_FLAG;
@@ -871,15 +858,15 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
stats->rx_bytes += cf->can_dlc;
if (k < PCH_FIFO_THRESH) {
- iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
- CAN_CMASK_ARB, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
+ PCH_CMASK_ARB, &priv->regs->if1_cmask);
/* Clearing the Dir bit. */
- pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
+ pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
/* Clearing NewDat & IntPnd */
pch_can_bit_clear(&priv->regs->if1_mcont,
- CAN_IF_MCONT_INTPND);
+ PCH_IF_MCONT_INTPND);
pch_can_check_if_busy(&priv->regs->if1_creq, k);
} else if (k > PCH_FIFO_THRESH) {
pch_can_int_clr(priv, k);
@@ -890,7 +877,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
}
RX_NEXT:
/* Reading the messsage object from the Message RAM */
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
reg = ioread32(&priv->regs->if1_mcont);
}
@@ -913,7 +900,7 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota)
return 0;
INT_STAT:
- if (int_stat == CAN_STATUS_INT) {
+ if (int_stat == PCH_STATUS_INT) {
reg_stat = ioread32(&priv->regs->stat);
if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
@@ -922,7 +909,7 @@ INT_STAT:
if (reg_stat & PCH_TX_OK) {
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq,
ioread32(&priv->regs->intr));
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
@@ -933,7 +920,7 @@ INT_STAT:
pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
int_stat = pch_can_int_pending(priv);
- if (int_stat == CAN_STATUS_INT)
+ if (int_stat == PCH_STATUS_INT)
goto INT_STAT;
}
@@ -945,14 +932,14 @@ MSG_OBJ:
if (rcv_pkts < 0)
return 0;
} else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
- if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) {
+ if (priv->msg_obj[int_stat - 1] == PCH_MSG_OBJ_TX) {
/* Handle transmission interrupt */
can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
- iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
+ iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
&priv->regs->if2_cmask);
dlc = ioread32(&priv->regs->if2_mcont) &
- CAN_IF_MCONT_DLC;
+ PCH_IF_MCONT_DLC;
pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
if (dlc > 8)
@@ -963,7 +950,7 @@ MSG_OBJ:
}
int_stat = pch_can_int_pending(priv);
- if (int_stat == CAN_STATUS_INT)
+ if (int_stat == PCH_STATUS_INT)
goto INT_STAT;
else if (int_stat >= 1 && int_stat <= 32)
goto MSG_OBJ;
@@ -983,17 +970,17 @@ static int pch_set_bittiming(struct net_device *ndev)
u32 brp;
/* Setting the CCE bit for accessing the Can Timing register. */
- pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
+ pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
- canbit = brp & MSK_BITT_BRP;
- canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
- canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
- canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
- bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
+ canbit = brp & PCH_MSK_BITT_BRP;
+ canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
+ canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
+ canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
+ bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
iowrite32(canbit, &priv->regs->bitt);
iowrite32(bepe, &priv->regs->brpe);
- pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
return 0;
}
@@ -1137,19 +1124,19 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
/* Reading the Msg Obj from the Msg RAM to the Interface register. */
- iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
/* Setting the CMASK register. */
- pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL);
+ pch_can_bit_set(&priv->regs->if2_cmask, PCH_CMASK_ALL);
/* If ID extended is set. */
pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
- pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD);
+ pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | PCH_ID2_XTD);
if (cf->can_id & CAN_EFF_FLAG) {
pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
pch_can_bit_set(&priv->regs->if2_id2,
- ((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD);
+ ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
} else {
pch_can_bit_set(&priv->regs->if2_id1, 0);
pch_can_bit_set(&priv->regs->if2_id2,
@@ -1158,7 +1145,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
/* If remote frame has to be transmitted.. */
if (cf->can_id & CAN_RTR_FLAG)
- pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
+ pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID2_DIR);
for (i = 0, j = 0; i < cf->can_dlc; j++) {
iowrite32(le32_to_cpu(cf->data[i++]),
@@ -1177,12 +1164,12 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
/* Clearing IntPend, NewDat & TxRqst */
pch_can_bit_clear(&priv->regs->if2_mcont,
- CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
- CAN_IF_MCONT_TXRQXT);
+ PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
+ PCH_IF_MCONT_TXRQXT);
/* Setting NewDat, TxRqst bits */
pch_can_bit_set(&priv->regs->if2_mcont,
- CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT);
+ PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
@@ -1245,7 +1232,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
/* Save Tx buffer enable state */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_TX)
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
pch_can_get_tx_enable(priv, i + 1,
&(priv->tx_enable[i]));
}
@@ -1255,7 +1242,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
/* Save Rx buffer enable state */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_RX) {
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
pch_can_get_rx_enable(priv, i + 1,
&(priv->rx_enable[i]));
pch_can_get_rx_buffer_link(priv, i + 1,
@@ -1313,7 +1300,7 @@ static int pch_can_resume(struct pci_dev *pdev)
/* Enabling the transmit buffer. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_TX) {
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
pch_can_set_tx_enable(priv, i + 1,
priv->tx_enable[i]);
}
@@ -1321,7 +1308,7 @@ static int pch_can_resume(struct pci_dev *pdev)
/* Configuring the receive buffer and enabling them. */
for (i = 0; i < PCH_OBJ_NUM; i++) {
- if (priv->msg_obj[i] == MSG_OBJ_RX) {
+ if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
/* Restore buffer link */
pch_can_set_rx_buffer_link(priv, i + 1,
priv->rx_link[i]);
@@ -1349,8 +1336,8 @@ static int pch_can_get_berr_counter(const struct net_device *dev,
{
struct pch_can_priv *priv = netdev_priv(dev);
- bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
- bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
+ bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
+ bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
return 0;
}
@@ -1410,10 +1397,10 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
for (index = 0; index < PCH_RX_OBJ_NUM;)
- priv->msg_obj[index++] = MSG_OBJ_RX;
+ priv->msg_obj[index++] = PCH_MSG_OBJ_RX;
for (index = index; index < PCH_OBJ_NUM;)
- priv->msg_obj[index++] = MSG_OBJ_TX;
+ priv->msg_obj[index++] = PCH_MSG_OBJ_TX;
netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
--
1.6.0.6
^ permalink raw reply related
* Re: [PATCH 3/3] SELinux: return -ECONNREFUSED from ip_postroute to signal fatal error
From: Patrick McHardy @ 2010-11-17 11:43 UTC (permalink / raw)
To: Eric Paris
Cc: netdev, linux-kernel, selinux, netfilter-devel, equinox,
eric.dumazet, davem, hzhong, jmorris, kuznet, paul.moore, pekkas,
sds, yoshfuji
In-Reply-To: <20101116215257.6727.12163.stgit@paris.rdu.redhat.com>
On 16.11.2010 22:52, Eric Paris wrote:
> The SELinux netfilter hooks just return NF_DROP if they drop a packet. We
> want to signal that a drop in this hook is a permanant fatal error and is not
> transient. If we do this the error will be passed back up the stack in some
> places and applications will get a faster interaction that something went
> wrong.
Looks good to me. I'd suggest to have these patches go through Dave's
tree since I want to make use of the netfilter error propagation
mechanism to return proper errno codes for netfilter re-routing
failures.
^ permalink raw reply
* [PATCH net-2.6] ipv6: Expose IFLA_PROTINFO timer values in msecs instead of jiffies
From: Thomas Graf @ 2010-11-17 11:44 UTC (permalink / raw)
To: davem; +Cc: netdev, YOSHIFUJI Hideaki
IFLA_PROTINFO exposes timer related per device settings in jiffies.
Change it to expose these values in msecs like the sysctl interface
does.
I did not find any users of IFLA_PROTINFO which rely on any of these
values and even if there are, they are likely already broken because
there is no way for them to reliably convert such a value to another
time format.
Signed-off-by: Thomas Graf <tgraf@infradead.org>
Cc: YOSHIFUJI Hideaki <yoshfuji@linux-ipv6.org>
Index: net-2.6/net/ipv6/addrconf.c
===================================================================
--- net-2.6.orig/net/ipv6/addrconf.c
+++ net-2.6/net/ipv6/addrconf.c
@@ -3798,8 +3798,10 @@ static inline void ipv6_store_devconf(st
array[DEVCONF_AUTOCONF] = cnf->autoconf;
array[DEVCONF_DAD_TRANSMITS] = cnf->dad_transmits;
array[DEVCONF_RTR_SOLICITS] = cnf->rtr_solicits;
- array[DEVCONF_RTR_SOLICIT_INTERVAL] = cnf->rtr_solicit_interval;
- array[DEVCONF_RTR_SOLICIT_DELAY] = cnf->rtr_solicit_delay;
+ array[DEVCONF_RTR_SOLICIT_INTERVAL] =
+ jiffies_to_msecs(cnf->rtr_solicit_interval);
+ array[DEVCONF_RTR_SOLICIT_DELAY] =
+ jiffies_to_msecs(cnf->rtr_solicit_delay);
array[DEVCONF_FORCE_MLD_VERSION] = cnf->force_mld_version;
#ifdef CONFIG_IPV6_PRIVACY
array[DEVCONF_USE_TEMPADDR] = cnf->use_tempaddr;
@@ -3813,7 +3815,8 @@ static inline void ipv6_store_devconf(st
array[DEVCONF_ACCEPT_RA_PINFO] = cnf->accept_ra_pinfo;
#ifdef CONFIG_IPV6_ROUTER_PREF
array[DEVCONF_ACCEPT_RA_RTR_PREF] = cnf->accept_ra_rtr_pref;
- array[DEVCONF_RTR_PROBE_INTERVAL] = cnf->rtr_probe_interval;
+ array[DEVCONF_RTR_PROBE_INTERVAL] =
+ jiffies_to_msecs(cnf->rtr_probe_interval);
#ifdef CONFIG_IPV6_ROUTE_INFO
array[DEVCONF_ACCEPT_RA_RT_INFO_MAX_PLEN] = cnf->accept_ra_rt_info_max_plen;
#endif
^ permalink raw reply
* Re:Response Required.
From: Joseph Poon @ 2010-11-17 11:39 UTC (permalink / raw)
I am Joseph Poon, I work with Hang Seng Bank Hong Kong. I have a
sensitive and confidential business worth 24.5 million US Dollars. I
am asking for your partnership in this business. Are you interested?
Kindly reply via <j.poon121@nba2k.com.cn> I am Joseph Poon, I work
with Hang Seng Bank Hong Kong. I have a sensitive and confidential
business worth 24.5 million US Dollars. I am asking for your
partnership in this business. Are you interested? Kindly reply via
<j.poon121@nba2k.com.cn>
----------------------------------------------------------------
This message was sent using IMP, the Internet Messaging Program.
^ permalink raw reply
* [PATCH net-next-2.6] can: EG20T PCH: use BIT(X)
From: Tomoya MORINAGA @ 2010-11-17 12:22 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Replace bit assignment value to BIT(X).
For easy to readable/identifiable, replace all bit assigned macros to BIT(X)
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 73 +++++++++++++++++++++++----------------------
1 files changed, 37 insertions(+), 36 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index c523e3d..238622a 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -38,50 +38,51 @@
#define PCH_ENABLE 1 /* The enable flag */
#define PCH_DISABLE 0 /* The disable flag */
-#define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
-#define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */
-#define PCH_CTRL_IE_SIE_EIE 0x000e
-#define PCH_CTRL_CCE 0x0040
-#define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
-#define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
-#define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
+#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
+#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
+#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
+#define PCH_CTRL_CCE BIT(6)
+#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
+#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
+#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
+
#define PCH_CMASK_RX_TX_SET 0x00f3
#define PCH_CMASK_RX_TX_GET 0x0073
#define PCH_CMASK_ALL 0xff
-#define PCH_CMASK_RDWR 0x80
-#define PCH_CMASK_ARB 0x20
-#define PCH_CMASK_CTRL 0x10
-#define PCH_CMASK_MASK 0x40
-#define PCH_CMASK_NEWDAT 0x04
-#define PCH_CMASK_CLRINTPND 0x08
-#define PCH_IF_MCONT_NEWDAT 0x8000
-#define PCH_IF_MCONT_INTPND 0x2000
-#define PCH_IF_MCONT_UMASK 0x1000
-#define PCH_IF_MCONT_TXIE 0x0800
-#define PCH_IF_MCONT_RXIE 0x0400
-#define PCH_IF_MCONT_RMTEN 0x0200
-#define PCH_IF_MCONT_TXRQXT 0x0100
-#define PCH_IF_MCONT_EOB 0x0080
-#define PCH_IF_MCONT_DLC 0x000f
-#define PCH_IF_MCONT_MSGLOST 0x4000
-#define PCH_MASK2_MDIR_MXTD 0xc000
-#define PCH_ID2_DIR 0x2000
-#define PCH_ID2_XTD 0x4000
-#define PCH_ID_MSGVAL 0x8000
-#define PCH_IF_CREQ_BUSY 0x8000
+#define PCH_CMASK_NEWDAT BIT(2)
+#define PCH_CMASK_CLRINTPND BIT(3)
+#define PCH_CMASK_CTRL BIT(4)
+#define PCH_CMASK_ARB BIT(5)
+#define PCH_CMASK_MASK BIT(6)
+#define PCH_CMASK_RDWR BIT(7)
+#define PCH_IF_MCONT_NEWDAT BIT(15)
+#define PCH_IF_MCONT_MSGLOST BIT(14)
+#define PCH_IF_MCONT_INTPND BIT(13)
+#define PCH_IF_MCONT_UMASK BIT(12)
+#define PCH_IF_MCONT_TXIE BIT(11)
+#define PCH_IF_MCONT_RXIE BIT(10)
+#define PCH_IF_MCONT_RMTEN BIT(9)
+#define PCH_IF_MCONT_TXRQXT BIT(8)
+#define PCH_IF_MCONT_EOB BIT(7)
+#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
+#define PCH_ID2_DIR BIT(13)
+#define PCH_ID2_XTD BIT(14)
+#define PCH_ID_MSGVAL BIT(15)
+#define PCH_IF_CREQ_BUSY BIT(15)
#define PCH_STATUS_INT 0x8000
#define PCH_REC 0x00007f00
#define PCH_TEC 0x000000ff
-#define PCH_RX_OK 0x00000010
-#define PCH_TX_OK 0x00000008
-#define PCH_BUS_OFF 0x00000080
-#define PCH_EWARN 0x00000040
-#define PCH_EPASSIV 0x00000020
-#define PCH_LEC0 0x00000001
-#define PCH_LEC1 0x00000002
-#define PCH_LEC2 0x00000004
+#define PCH_TX_OK BIT(3)
+#define PCH_RX_OK BIT(4)
+#define PCH_EPASSIV BIT(5)
+#define PCH_EWARN BIT(6)
+#define PCH_BUS_OFF BIT(7)
+#define PCH_LEC0 BIT(0)
+#define PCH_LEC1 BIT(1)
+#define PCH_LEC2 BIT(2)
#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
#define PCH_STUF_ERR PCH_LEC0
#define PCH_FORM_ERR PCH_LEC1
--
1.6.0.6
^ permalink raw reply related
* Re: [PATCH net-next-2.6] can: EG20T PCH: use BIT(X)
From: Marc Kleine-Budde @ 2010-11-17 13:04 UTC (permalink / raw)
To: Tomoya MORINAGA
Cc: andrew.chih.howe.khor-ral2JQCrhuEAvxtiuMwx3w, Samuel Ortiz,
margie.foster-ral2JQCrhuEAvxtiuMwx3w,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
yong.y.wang-ral2JQCrhuEAvxtiuMwx3w,
kok.howg.ewe-ral2JQCrhuEAvxtiuMwx3w, Wolfgang Grandegger,
joel.clark-ral2JQCrhuEAvxtiuMwx3w, David S. Miller,
Christian Pellegrin, qi.wang-ral2JQCrhuEAvxtiuMwx3w
In-Reply-To: <4CE3C90D.6010705-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 4446 bytes --]
On 11/17/2010 01:22 PM, Tomoya MORINAGA wrote:
> Replace bit assignment value to BIT(X).
> For easy to readable/identifiable, replace all bit assigned macros to BIT(X)
>
> Signed-off-by: Tomoya MORINAGA <tomoya-linux-ECg8zkTtlr0C6LszWs/t0g@public.gmane.org>
IMHO you can squash this into the "add prefix to macro" patch.
You have my Acked-by for both solutions.
cheers, Marc
> ---
> drivers/net/can/pch_can.c | 73 +++++++++++++++++++++++----------------------
> 1 files changed, 37 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
> index c523e3d..238622a 100644
> --- a/drivers/net/can/pch_can.c
> +++ b/drivers/net/can/pch_can.c
> @@ -38,50 +38,51 @@
>
> #define PCH_ENABLE 1 /* The enable flag */
> #define PCH_DISABLE 0 /* The disable flag */
> -#define PCH_CTRL_INIT 0x0001 /* The INIT bit of CANCONT register. */
> -#define PCH_CTRL_IE 0x0002 /* The IE bit of CAN control register */
> -#define PCH_CTRL_IE_SIE_EIE 0x000e
> -#define PCH_CTRL_CCE 0x0040
> -#define PCH_CTRL_OPT 0x0080 /* The OPT bit of CANCONT register. */
> -#define PCH_OPT_SILENT 0x0008 /* The Silent bit of CANOPT reg. */
> -#define PCH_OPT_LBACK 0x0010 /* The LoopBack bit of CANOPT reg. */
> +#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
> +#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
> +#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
> +#define PCH_CTRL_CCE BIT(6)
> +#define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
> +#define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
> +#define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
> +
> #define PCH_CMASK_RX_TX_SET 0x00f3
> #define PCH_CMASK_RX_TX_GET 0x0073
> #define PCH_CMASK_ALL 0xff
> -#define PCH_CMASK_RDWR 0x80
> -#define PCH_CMASK_ARB 0x20
> -#define PCH_CMASK_CTRL 0x10
> -#define PCH_CMASK_MASK 0x40
> -#define PCH_CMASK_NEWDAT 0x04
> -#define PCH_CMASK_CLRINTPND 0x08
> -#define PCH_IF_MCONT_NEWDAT 0x8000
> -#define PCH_IF_MCONT_INTPND 0x2000
> -#define PCH_IF_MCONT_UMASK 0x1000
> -#define PCH_IF_MCONT_TXIE 0x0800
> -#define PCH_IF_MCONT_RXIE 0x0400
> -#define PCH_IF_MCONT_RMTEN 0x0200
> -#define PCH_IF_MCONT_TXRQXT 0x0100
> -#define PCH_IF_MCONT_EOB 0x0080
> -#define PCH_IF_MCONT_DLC 0x000f
> -#define PCH_IF_MCONT_MSGLOST 0x4000
> -#define PCH_MASK2_MDIR_MXTD 0xc000
> -#define PCH_ID2_DIR 0x2000
> -#define PCH_ID2_XTD 0x4000
> -#define PCH_ID_MSGVAL 0x8000
> -#define PCH_IF_CREQ_BUSY 0x8000
> +#define PCH_CMASK_NEWDAT BIT(2)
> +#define PCH_CMASK_CLRINTPND BIT(3)
> +#define PCH_CMASK_CTRL BIT(4)
> +#define PCH_CMASK_ARB BIT(5)
> +#define PCH_CMASK_MASK BIT(6)
> +#define PCH_CMASK_RDWR BIT(7)
> +#define PCH_IF_MCONT_NEWDAT BIT(15)
> +#define PCH_IF_MCONT_MSGLOST BIT(14)
> +#define PCH_IF_MCONT_INTPND BIT(13)
> +#define PCH_IF_MCONT_UMASK BIT(12)
> +#define PCH_IF_MCONT_TXIE BIT(11)
> +#define PCH_IF_MCONT_RXIE BIT(10)
> +#define PCH_IF_MCONT_RMTEN BIT(9)
> +#define PCH_IF_MCONT_TXRQXT BIT(8)
> +#define PCH_IF_MCONT_EOB BIT(7)
> +#define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
> +#define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
> +#define PCH_ID2_DIR BIT(13)
> +#define PCH_ID2_XTD BIT(14)
> +#define PCH_ID_MSGVAL BIT(15)
> +#define PCH_IF_CREQ_BUSY BIT(15)
>
> #define PCH_STATUS_INT 0x8000
> #define PCH_REC 0x00007f00
> #define PCH_TEC 0x000000ff
>
> -#define PCH_RX_OK 0x00000010
> -#define PCH_TX_OK 0x00000008
> -#define PCH_BUS_OFF 0x00000080
> -#define PCH_EWARN 0x00000040
> -#define PCH_EPASSIV 0x00000020
> -#define PCH_LEC0 0x00000001
> -#define PCH_LEC1 0x00000002
> -#define PCH_LEC2 0x00000004
> +#define PCH_TX_OK BIT(3)
> +#define PCH_RX_OK BIT(4)
> +#define PCH_EPASSIV BIT(5)
> +#define PCH_EWARN BIT(6)
> +#define PCH_BUS_OFF BIT(7)
> +#define PCH_LEC0 BIT(0)
> +#define PCH_LEC1 BIT(1)
> +#define PCH_LEC2 BIT(2)
> #define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
> #define PCH_STUF_ERR PCH_LEC0
> #define PCH_FORM_ERR PCH_LEC1
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* Re: ping -I eth1 ....
From: Joakim Tjernlund @ 2010-11-17 14:03 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, Thomas Graf
In-Reply-To: <1289989412.2687.18.camel@edumazet-laptop>
Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/17 11:23:32:
>
> Le mercredi 17 novembre 2010 à 11:09 +0100, Joakim Tjernlund a écrit :
> > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/17 10:51:07:
> > >
> > > Le mercredi 17 novembre 2010 à 10:29 +0100, Joakim Tjernlund a écrit :
> > > > Joakim Tjernlund/Transmode wrote on 2010/11/09 20:33:37:
> > > > >
> > > > > Joakim Tjernlund/Transmode wrote on 2010/11/06 10:42:46:
> > > > > > Thomas Graf <tgr@infradead.org> wrote on 2010/11/05 21:31:50:
> > > > > > >
> > > > > > > On Fri, Nov 05, 2010 at 04:54:18PM +0100, Joakim Tjernlund wrote:
> > > > > > > > Eric Dumazet <eric.dumazet@gmail.com> wrote on 2010/11/05 16:06:54:
> > > > > > > > >
> > > > > > > > > > Hopefully most of that is legacy or just plain wrong? Unless
> > > > > > > > > > someone can say why only test IFF_UP one should consider changing them.
> > > > > > > > > >
> > > > > > > > >
> > > > > > > > > Most of the places are hot path.
> > > > > > > > >
> > > > > > > > > You dont want to replace one test by four tests.
> > > > > > > > >
> > > > > > > > > _This_ would be wrong :)
> > > > > > > >
> > > > > > > > Wrong is wrong, even if it is in the hot path :)
> > > > > > > > Perhaps it is time define and internal IFF_OPERATIONAL flag
> > > > > > > > which is the sum of IFF_UP, IFF_RUNNING etc.? Tht
> > > > > > > > way you still get one test in the hot path and can abstract
> > > > > > > > what defines an operational link.
> > > > > > >
> > > > > > > You definitely don't want to have your send() call fail simply because
> > > > > > > the carrier was off for a few msec or the routing daemon has put a link
> > > > > > > down temporarly. Also, the outgoing interface looked up at routing
> > > > > > > decision is not necessarly the interface used for sending in the end.
> > > > > > > The packet may get mangled and rerouted by netfilter or tc on the way.
> > > > > >
> > > > > > But do you handle the case when the link is non operational for a long time?
> > > > > >
> > > > > > >
> > > > > > > Personally I'm even ok with the current behaviour of sendto() while the
> > > > > > > socket is bound to an interface but if we choose to return an error
> > > > > > > if the interface is down we might as well do so based on the operational
> > > > > > > status.
> > > >
> > > > > > Perhaps there is a better way. This all started when pppd hung because
> > > > > > of ping -I <ppp interface>, then someone pulled the cable for the on the link.
> > > > > >
> > > > > > This is a strace where we have two ping -I,
> > > > > > ping -I p1-2-1-2-2 .. and ping -I p1-2-3-2-4 ..
> > > > > > Notice how pppd hangs for a long time in PPPIOCDETACH
> > > > > > As far as I can tell this is due to ping -I has claimed the ppp interfaces
> > > > > > and doesn't noticed that the link is down. Ideally ping should receive
> > > > > > a ENODEV as soon as pppd calls PPPIOCDETACH.
> > > > > >
> > > > > > 0.000908 write(0, "Connection terminated.\n", 23) = 23
> > > > > > 0.000481 gettimeofday({1288952770, 566048}, NULL) = 0
> > > > > > 0.001553 ioctl(7, PPPIOCDETACH
> > > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > > > Brazil kernel: unregister_netdevice: waiting for p1-2-1-2-2 to become free. Usage count = 3
> > > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:20 2010 ...
> > > > > > Brazil kernel: unregister_netdevice: waiting for p1-2-3-2-4 to become free. Usage count = 3
> > > > > > Message from syslogd@Brazil at Fri Nov 5 11:26:51 2010 ...
> > > > > > Brazil last message repeated 3 times
> > > > > > , 0xbfbc3398) = 0
> > > > > > 66.559216 connect(9, {sa_family=AF_PPPOX, sa_data="\0\0\0\0\0\0\0\252\273\314\335\356hd"}, 30) = 0
> > > > > > 0.000693 close(10) = 0
> > > > > > 0.000449 close(7) = 0
> > > > > > 0.009801 close(9) = 0
> > > > >
> > > > > Any comment on this last strace? It is expected that ping -I should
> > > > > hold pppd hostage?
> > > > >
> > > >
> > > > Ping?
> > > >
> > >
> > > I thought I posted a patch, is there something else ?
> >
> > yes, I wondered about the above strace and if it is expected that ping -I
> > should hold pppd hostage? Should not ping receive a ENODEV as soon as
> > pppd detaches an interface?
> >
> > >
> > > Could you please test with latest net-next-2.6 and following patch ?
> >
> > I tested the first patch you sent and that one worked well. I can try
> > again on 2.6.35( our boards takes a while to move forward)?
>
> Well, in this case, apply commit :
>
> 332dd96f7ac15e937088fe11f15cfe0210e8edd1
>
> (net/dst: dst_dev_event() called after other notifiers)
>
> http://git2.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=332dd96f7ac15e937088fe11f15cfe0210e8edd1
hmm, with (or without) this and/or your other patch I get:
vconfig add eth0 1
ifconfig eth0.1 up
ping -I eth0.1
<in other session do>
vconfig rem eth0.1
Now vconfig rem eth0.1 hangs and I get several:
localhost kernel: unregister_netdevice: waiting for eth0.1 to become free. Usage count = 3
After some time vconfig rem eth0.1 succeeds
hmm, last test I did is still stuck, vconfig rem eth0.1 still hangs after 5 minutes.
The ping -I dies right after vconfig rem eth0.1
kernel 2.6.35
^ permalink raw reply
* [PATCH net-2.6] ipv6: Expose reachable and retrans timer values as msecs
From: Thomas Graf @ 2010-11-17 14:12 UTC (permalink / raw)
To: davem; +Cc: netdev, YOSHIFUJI Hideaki
Expose reachable and retrans timer values in msecs instead of jiffies.
Both timer values are already exposed as msecs in the neighbour table
netlink interface.
The creation timestamp format with increased precision is kept but
cleaned up.
Signed-off-by: Thomas Graf <tgraf@infradead.org>
Cc: YOSHIFUJI Hideaki <yoshfuji@linux-ipv6.org>
Index: net-2.6/net/ipv6/addrconf.c
===================================================================
--- net-2.6.orig/net/ipv6/addrconf.c
+++ net-2.6/net/ipv6/addrconf.c
@@ -98,7 +98,11 @@
#endif
#define INFINITY_LIFE_TIME 0xFFFFFFFF
-#define TIME_DELTA(a, b) ((unsigned long)((long)(a) - (long)(b)))
+
+static inline u32 cstamp_delta(unsigned long cstamp)
+{
+ return (cstamp - INITIAL_JIFFIES) * 100UL / HZ;
+}
#define ADDRCONF_TIMER_FUZZ_MINUS (HZ > 50 ? HZ/50 : 1)
#define ADDRCONF_TIMER_FUZZ (HZ / 4)
@@ -3444,10 +3448,8 @@ static int put_cacheinfo(struct sk_buff
{
struct ifa_cacheinfo ci;
- ci.cstamp = (u32)(TIME_DELTA(cstamp, INITIAL_JIFFIES) / HZ * 100
- + TIME_DELTA(cstamp, INITIAL_JIFFIES) % HZ * 100 / HZ);
- ci.tstamp = (u32)(TIME_DELTA(tstamp, INITIAL_JIFFIES) / HZ * 100
- + TIME_DELTA(tstamp, INITIAL_JIFFIES) % HZ * 100 / HZ);
+ ci.cstamp = cstamp_delta(cstamp);
+ ci.tstamp = cstamp_delta(tstamp);
ci.ifa_prefered = preferred;
ci.ifa_valid = valid;
@@ -3905,10 +3907,9 @@ static int inet6_fill_ifla6_attrs(struct
NLA_PUT_U32(skb, IFLA_INET6_FLAGS, idev->if_flags);
ci.max_reasm_len = IPV6_MAXPLEN;
- ci.tstamp = (__u32)(TIME_DELTA(idev->tstamp, INITIAL_JIFFIES) / HZ * 100
- + TIME_DELTA(idev->tstamp, INITIAL_JIFFIES) % HZ * 100 / HZ);
- ci.reachable_time = idev->nd_parms->reachable_time;
- ci.retrans_time = idev->nd_parms->retrans_time;
+ ci.tstamp = cstamp_delta(idev->tstamp);
+ ci.reachable_time = jiffies_to_msecs(idev->nd_parms->reachable_time);
+ ci.retrans_time = jiffies_to_msecs(idev->nd_parms->retrans_time);
NLA_PUT(skb, IFLA_INET6_CACHEINFO, sizeof(ci), &ci);
nla = nla_reserve(skb, IFLA_INET6_CONF, DEVCONF_MAX * sizeof(s32));
^ permalink raw reply
* Re: [PATCH 3/3] SELinux: return -ECONNREFUSED from ip_postroute to signal fatal error
From: Eric Paris @ 2010-11-17 14:38 UTC (permalink / raw)
To: Patrick McHardy
Cc: netdev, linux-kernel, selinux, netfilter-devel, equinox,
eric.dumazet, davem, hzhong, jmorris, kuznet, paul.moore, pekkas,
sds, yoshfuji
In-Reply-To: <4CE3BFC4.1010706@trash.net>
On Wed, 2010-11-17 at 12:43 +0100, Patrick McHardy wrote:
> On 16.11.2010 22:52, Eric Paris wrote:
> > The SELinux netfilter hooks just return NF_DROP if they drop a packet. We
> > want to signal that a drop in this hook is a permanant fatal error and is not
> > transient. If we do this the error will be passed back up the stack in some
> > places and applications will get a faster interaction that something went
> > wrong.
>
> Looks good to me. I'd suggest to have these patches go through Dave's
> tree since I want to make use of the netfilter error propagation
> mechanism to return proper errno codes for netfilter re-routing
> failures.
I'd be happy if Dave pulled patches 1 and 2. I can resend patch #3 once
I can cajole another of the SELinux maintainers to look at it (I believe
he most likely one is on vacation this week)
-Eric
^ permalink raw reply
* Re: [net-2.6 PATCH] ipv6: fix missing in6_ifa_put in addrconf
From: Anders Franzen @ 2010-11-17 15:20 UTC (permalink / raw)
To: Eric Dumazet
Cc: John Fastabend, davem@davemloft.net, netdev@vger.kernel.org,
shemminger@vyatta.com
In-Reply-To: <1289889454.3364.122.camel@edumazet-laptop>
Hi, I was hunting for a bug that a colleague discovered.
When we exit a network namespace, the ns was hanging with dangling
references to dev lo.
When I saw the patch below, I fetched the latest net-next from Daves
repository.
And the problem is gone. Was this really the fix, since it seems to me
that this is a fix to a recently added patch (dont remove address ....).
Did you fix anything else in the Ipv6 addrconf w.r.g dev_hold/dev_put?
netns still have problems with slab corruption during exit though:
Nov 17 15:00:20 p04 user.err kernel: Slab corruption: size-4096
start=ffff88000612a000, len=4096
Nov 17 15:00:20 p04 user.err kernel: 020: 6b 6b 6b 6b 6b 6b
Nov 17 15:00:20 p04 user.info kernel: 6b 6b 00 00 00 00 00 00 00
Nov 17 15:00:20 p04 user.info kernel: 00
BR
Anders
On Tue, 2010-11-16 at 07:37 +0100, Eric Dumazet wrote:
> Le lundi 15 novembre 2010 à 22:29 -0800, John Fastabend a écrit :
> > Fix ref count bug introduced by
> >
> > commit 2de795707294972f6c34bae9de713e502c431296
> > Author: Lorenzo Colitti <lorenzo@google.com>
> > Date: Wed Oct 27 18:16:49 2010 +0000
> >
> > ipv6: addrconf: don't remove address state on ifdown if the address
> > is being kept
> >
> >
> > Fix logic so that addrconf_ifdown() decrements the inet6_ifaddr
> > refcnt correctly with in6_ifa_put().
> >
> > Reported-by: Stephen Hemminger <shemminger@vyatta.com>
> > Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
> > ---
> >
> > net/ipv6/addrconf.c | 6 +++---
> > 1 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
> > index b41ce0f..aaa3ca4 100644
> > --- a/net/ipv6/addrconf.c
> > +++ b/net/ipv6/addrconf.c
> > @@ -2754,13 +2754,13 @@ static int addrconf_ifdown(struct net_device *dev, int how)
> > ifa->state = INET6_IFADDR_STATE_DEAD;
> > spin_unlock_bh(&ifa->state_lock);
> >
> > - if (state == INET6_IFADDR_STATE_DEAD) {
> > - in6_ifa_put(ifa);
> > - } else {
> > + if (state != INET6_IFADDR_STATE_DEAD) {
> > __ipv6_ifa_notify(RTM_DELADDR, ifa);
> > atomic_notifier_call_chain(&inet6addr_chain,
> > NETDEV_DOWN, ifa);
> > }
> > +
> > + in6_ifa_put(ifa);
> > write_lock_bh(&idev->lock);
> > }
> > }
> >
>
> Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
>
> Thanks again John
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe netdev" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [net-2.6 PATCH] ipv6: fix missing in6_ifa_put in addrconf
From: Eric Dumazet @ 2010-11-17 15:38 UTC (permalink / raw)
To: Anders Franzen
Cc: John Fastabend, davem@davemloft.net, netdev@vger.kernel.org,
shemminger@vyatta.com
In-Reply-To: <1290007231.2222.10.camel@seasc7941.dyn.rnd.as.sw.ericsson.se>
Le mercredi 17 novembre 2010 à 16:20 +0100, Anders Franzen a écrit :
> Hi, I was hunting for a bug that a colleague discovered.
> When we exit a network namespace, the ns was hanging with dangling
> references to dev lo.
>
> When I saw the patch below, I fetched the latest net-next from Daves
> repository.
>
> And the problem is gone. Was this really the fix, since it seems to me
> that this is a fix to a recently added patch (dont remove address ....).
>
> Did you fix anything else in the Ipv6 addrconf w.r.g dev_hold/dev_put?
>
> netns still have problems with slab corruption during exit though:
>
> Nov 17 15:00:20 p04 user.err kernel: Slab corruption: size-4096
> start=ffff88000612a000, len=4096
> Nov 17 15:00:20 p04 user.err kernel: 020: 6b 6b 6b 6b 6b 6b
> Nov 17 15:00:20 p04 user.info kernel: 6b 6b 00 00 00 00 00 00 00
> Nov 17 15:00:20 p04 user.info kernel: 00
>
> BR
> Anders
>
>
Hi Anders
Several patches of interest :
commit 9d82ca98f71fd686ef2f3017c5e3e6a4871b6e46
(ipv6: fix missing in6_ifa_put in addrconf)
commit 332dd96f7ac15e937088fe11f15cfe0210e8edd1
(net/dst: dst_dev_event() called after other notifiers)
commit ef885afbf8a37689afc1d9d545e2f3e7a8276c17
(net: use rcu_barrier() in rollback_registered_many)
^ permalink raw reply
* Re: [PATCH] 3c59x: fix build failure on !CONFIG_PCI
From: Randy Dunlap @ 2010-11-17 15:58 UTC (permalink / raw)
To: Namhyung Kim; +Cc: Steffen Klassert, netdev, linux-kernel
In-Reply-To: <1289960532.1663.24.camel@leonhard>
On 11/16/10 18:22, Namhyung Kim wrote:
> 2010-11-16 (화), 09:14 -0800, Randy Dunlap:
>> Hi,
>>
>
> Hi, Randy
>
>
>> Interesting patch. I have reported this build error and looked
>> into fixing it, but did not come up with this solution.
>>
>> Looking at it more: if CONFIG_PCI is not enabled, DEVICE_PCI() is NULL.
>> That makes VORTEX_PCI() (with or without your patch) have a value of NULL.
>>
>> Is the line with the reported syntax error (3211) executed in
>> function acpi_set_WOL() ? If so, let's assume that vp->enable_wol is true.
>> Then what happens on line 3211 (or 3213 after your patch)?
>>
>> if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
>> return;
>>
>> or if I am really confuzed this morning, please tell me how it works.
>>
>
> At first glance, I've noticed that the code above could make a NULL
> dereference so I added NULL check prior to the line.
>
> But after reading more code I realized that other pci-functions called
> in acpi_set_WOL() would not work with NULL pci_dev pointer also. And I
> found all callers of the acpi_set_WOL() already checked NULL pointer
> before the call. Finally I could remove the NULL check and leave the
> code as is. That's how it works. :)
I see. and concur. Thanks for the explanation.
--
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***
^ permalink raw reply
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