* [PATCH net-next-2.6 v6 03/20] can: EG20T PCH: Enumerate LEC macros
From: Tomoya MORINAGA @ 2010-11-30 4:16 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
For easy to readable, LEC #define macros are replaced to enums.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 77 ++++++++++++++++++++++++---------------------
1 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 982ff2d..2d4ab0f 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -71,21 +71,12 @@
#define PCH_REC 0x00007f00
#define PCH_TEC 0x000000ff
+
#define PCH_TX_OK BIT(3)
#define PCH_RX_OK BIT(4)
#define PCH_EPASSIV BIT(5)
#define PCH_EWARN BIT(6)
#define PCH_BUS_OFF BIT(7)
-#define PCH_LEC0 BIT(0)
-#define PCH_LEC1 BIT(1)
-#define PCH_LEC2 BIT(2)
-#define PCH_LEC_ALL (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
-#define PCH_STUF_ERR PCH_LEC0
-#define PCH_FORM_ERR PCH_LEC1
-#define PCH_ACK_ERR (PCH_LEC0 | PCH_LEC1)
-#define PCH_BIT1_ERR PCH_LEC2
-#define PCH_BIT0_ERR (PCH_LEC0 | PCH_LEC2)
-#define PCH_CRC_ERR (PCH_LEC1 | PCH_LEC2)
/* bit position of certain controller bits. */
#define PCH_BIT_BRP 0
@@ -117,6 +108,16 @@ enum pch_ifreg {
PCH_TX_IFREG,
};
+enum pch_can_err {
+ PCH_STUF_ERR = 1,
+ PCH_FORM_ERR,
+ PCH_ACK_ERR,
+ PCH_BIT1_ERR,
+ PCH_BIT0_ERR,
+ PCH_CRC_ERR,
+ PCH_LEC_ALL,
+};
+
enum pch_can_mode {
PCH_CAN_ENABLE,
PCH_CAN_DISABLE,
@@ -620,7 +621,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
struct sk_buff *skb;
struct pch_can_priv *priv = netdev_priv(ndev);
struct can_frame *cf;
- u32 errc;
+ u32 errc, lec;
struct net_device_stats *stats = &(priv->ndev->stats);
enum can_state state = priv->can.state;
@@ -665,33 +666,37 @@ static void pch_can_error(struct net_device *ndev, u32 status)
"%s -> CAN controller is ERROR PASSIVE .\n", __func__);
}
- if (status & PCH_LEC_ALL) {
+ lec = status & PCH_LEC_ALL;
+ switch (lec) {
+ case PCH_STUF_ERR:
+ cf->data[2] |= CAN_ERR_PROT_STUFF;
priv->can.can_stats.bus_error++;
stats->rx_errors++;
- switch (status & PCH_LEC_ALL) {
- case PCH_STUF_ERR:
- cf->data[2] |= CAN_ERR_PROT_STUFF;
- break;
- case PCH_FORM_ERR:
- cf->data[2] |= CAN_ERR_PROT_FORM;
- break;
- case PCH_ACK_ERR:
- cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
- CAN_ERR_PROT_LOC_ACK_DEL;
- break;
- case PCH_BIT1_ERR:
- case PCH_BIT0_ERR:
- cf->data[2] |= CAN_ERR_PROT_BIT;
- break;
- case PCH_CRC_ERR:
- cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
- CAN_ERR_PROT_LOC_CRC_DEL;
- break;
- default:
- iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
- break;
- }
-
+ break;
+ case PCH_FORM_ERR:
+ cf->data[2] |= CAN_ERR_PROT_FORM;
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ break;
+ case PCH_ACK_ERR:
+ cf->can_id |= CAN_ERR_ACK;
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ break;
+ case PCH_BIT1_ERR:
+ case PCH_BIT0_ERR:
+ cf->data[2] |= CAN_ERR_PROT_BIT;
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ break;
+ case PCH_CRC_ERR:
+ cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
+ CAN_ERR_PROT_LOC_CRC_DEL;
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ break;
+ case PCH_LEC_ALL: /* Written by CPU. No error status */
+ break;
}
priv->can.state = state;
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 04/20] can: EG20T PCH: Add Tx Flow Control
From: Tomoya MORINAGA @ 2010-11-30 4:18 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Currently, there is no flow control processing.
Thus, Add flow control processing as
when there is no empty of tx buffer,
netif_stop_queue is called.
When there is empty buffer, netif_wake_queue is called.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 27 ++++++++-------------------
1 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 2d4ab0f..8686d93 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -899,6 +899,8 @@ MSG_OBJ:
dlc = 8;
stats->tx_bytes += dlc;
stats->tx_packets++;
+ if (int_stat == PCH_TX_OBJ_END)
+ netif_wake_queue(ndev);
}
int_stat = pch_can_int_pending(priv);
@@ -1037,18 +1039,6 @@ static int pch_close(struct net_device *ndev)
return 0;
}
-static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
-{
- u32 buffer_status = 0;
- struct pch_can_priv *priv = netdev_priv(ndev);
-
- /* Getting the message object status. */
- buffer_status = (u32) pch_can_get_buffer_status(priv);
-
- return buffer_status & obj_id;
-}
-
-
static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
{
int i, j;
@@ -1060,17 +1050,16 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
if (can_dropped_invalid_skb(ndev, skb))
return NETDEV_TX_OK;
- if (priv->tx_obj == PCH_TX_OBJ_END) { /* Point tail Obj */
- while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
- PCH_RX_OBJ_NUM)))
- udelay(500);
+ if (priv->tx_obj == PCH_TX_OBJ_END) {
+ if (ioread32(&priv->regs->treq2) & 0xfc00)
+ netif_stop_queue(ndev);
- priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj ID */
- tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
+ tx_buffer_avail = priv->tx_obj;
+ priv->tx_obj = PCH_TX_OBJ_START;
} else {
tx_buffer_avail = priv->tx_obj;
+ priv->tx_obj++;
}
- priv->tx_obj++;
/* Attaining the lock. */
spin_lock_irqsave(&priv->msgif_reg_lock, flags);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 05/20] can: EG20T PCH: Delete unnecessary spin_lock
From: Tomoya MORINAGA @ 2010-11-30 4:19 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Delete unnecessary spin_lock for accessing Message Object.
Since all message objects are divided into tx/rx area completely,
spin_lock processing is unnecessary.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/net/can/pch_can.c | 34 ----------------------------------
1 files changed, 0 insertions(+), 34 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 8686d93..6437e60 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -71,7 +71,6 @@
#define PCH_REC 0x00007f00
#define PCH_TEC 0x000000ff
-
#define PCH_TX_OK BIT(3)
#define PCH_RX_OK BIT(4)
#define PCH_EPASSIV BIT(5)
@@ -178,7 +177,6 @@ struct pch_can_priv {
unsigned int int_enables;
unsigned int int_stat;
struct net_device *ndev;
- spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
unsigned int msg_obj[PCH_TX_OBJ_END];
struct pch_can_regs __iomem *regs;
struct napi_struct napi;
@@ -309,7 +307,6 @@ static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
u32 set, enum pch_ifreg dir)
{
- unsigned long flags;
u32 ie;
if (dir)
@@ -317,7 +314,6 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
else
ie = PCH_IF_MCONT_RXIE;
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
/* Reading the receive buffer data from RAM to Interface1 registers */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
@@ -338,10 +334,8 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
}
pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
-
static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
{
int i;
@@ -363,7 +357,6 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
enum pch_ifreg dir)
{
- unsigned long flags;
u32 ie, enable;
if (dir)
@@ -371,7 +364,6 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
else
ie = PCH_IF_MCONT_TXIE;
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
@@ -381,7 +373,6 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
} else {
enable = 0;
}
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
return enable;
}
@@ -393,9 +384,6 @@ static int pch_can_int_pending(struct pch_can_priv *priv)
static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
u32 buffer_num, u32 set)
{
- unsigned long flags;
-
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
@@ -407,15 +395,11 @@ static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
u32 buffer_num, u32 *link)
{
- unsigned long flags;
-
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
@@ -423,7 +407,6 @@ static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
*link = PCH_DISABLE;
else
*link = PCH_ENABLE;
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
static void pch_can_clear_buffers(struct pch_can_priv *priv)
@@ -468,9 +451,6 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
{
int i;
- unsigned long flags;
-
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
iowrite32(PCH_CMASK_RX_TX_GET,
@@ -529,7 +509,6 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
}
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}
static void pch_can_init(struct pch_can_priv *priv)
@@ -845,7 +824,6 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota)
u32 int_stat;
int rcv_pkts = 0;
u32 reg_stat;
- unsigned long flags;
int_stat = pch_can_int_pending(priv);
if (!int_stat)
@@ -860,12 +838,10 @@ INT_STAT:
}
if (reg_stat & PCH_TX_OK) {
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
iowrite32(PCH_CMASK_RX_TX_GET,
&priv->regs->ifregs[1].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[1].creq,
ioread32(&priv->regs->intr));
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
}
@@ -879,22 +855,18 @@ INT_STAT:
MSG_OBJ:
if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
rcv_pkts = pch_can_rx_normal(ndev, int_stat);
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
if (rcv_pkts < 0)
return 0;
} else if ((int_stat >= PCH_TX_OBJ_START) &&
(int_stat <= PCH_TX_OBJ_END)) {
/* Handle transmission interrupt */
can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
&priv->regs->ifregs[1].cmask);
dlc = ioread32(&priv->regs->ifregs[1].mcont) &
PCH_IF_MCONT_DLC;
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
if (dlc > 8)
dlc = 8;
stats->tx_bytes += dlc;
@@ -1042,7 +1014,6 @@ static int pch_close(struct net_device *ndev)
static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
{
int i, j;
- unsigned long flags;
struct pch_can_priv *priv = netdev_priv(ndev);
struct can_frame *cf = (struct can_frame *)skb->data;
int tx_buffer_avail = 0;
@@ -1061,9 +1032,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
priv->tx_obj++;
}
- /* Attaining the lock. */
- spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-
/* Reading the Msg Obj from the Msg RAM to the Interface register. */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
@@ -1115,8 +1083,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
- spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-
return NETDEV_TX_OK;
}
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 06/20] can: EG20T PCH: Fix endianness issue
From: Tomoya MORINAGA @ 2010-11-30 4:20 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
there is endianness issue both Tx and Rx.
Currently, data is set like below.
Register:
MSB--LSB
x x D0 D1
x x D2 D3
x x D4 D5
x x D6 D7
But Data to be sent must be set like below.
Register:
MSB--LSB
x x D1 D0
x x D3 D2
x x D5 D4
x x D7 D6 (x means reserved area.)
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 118 +++++++++++++++++++++------------------------
1 files changed, 55 insertions(+), 63 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 6437e60..98e7e9f 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -134,10 +134,7 @@ struct pch_can_if_regs {
u32 id1;
u32 id2;
u32 mcont;
- u32 dataa1;
- u32 dataa2;
- u32 datab1;
- u32 datab2;
+ u32 data[4];
u32 rsv[13];
};
@@ -420,10 +417,10 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
iowrite32(0x0, &priv->regs->ifregs[0].id1);
iowrite32(0x0, &priv->regs->ifregs[0].id2);
iowrite32(0x0, &priv->regs->ifregs[0].mcont);
- iowrite32(0x0, &priv->regs->ifregs[0].dataa1);
- iowrite32(0x0, &priv->regs->ifregs[0].dataa2);
- iowrite32(0x0, &priv->regs->ifregs[0].datab1);
- iowrite32(0x0, &priv->regs->ifregs[0].datab2);
+ iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
+ iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
+ iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
+ iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[0].cmask);
@@ -437,10 +434,10 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
iowrite32(0x0, &priv->regs->ifregs[1].id1);
iowrite32(0x0, &priv->regs->ifregs[1].id2);
iowrite32(0x0, &priv->regs->ifregs[1].mcont);
- iowrite32(0x0, &priv->regs->ifregs[1].dataa1);
- iowrite32(0x0, &priv->regs->ifregs[1].dataa2);
- iowrite32(0x0, &priv->regs->ifregs[1].datab1);
- iowrite32(0x0, &priv->regs->ifregs[1].datab2);
+ iowrite32(0x0, &priv->regs->ifregs[1].data[0]);
+ iowrite32(0x0, &priv->regs->ifregs[1].data[1]);
+ iowrite32(0x0, &priv->regs->ifregs[1].data[2]);
+ iowrite32(0x0, &priv->regs->ifregs[1].data[3]);
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[1].cmask);
@@ -703,12 +700,13 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
canid_t id;
u32 ide;
u32 rtr;
- int i, j, k;
+ int i, k;
int rcv_pkts = 0;
struct sk_buff *skb;
struct can_frame *cf;
struct pch_can_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &(priv->ndev->stats);
+ u16 data_reg;
/* Reading the messsage object from the Message RAM */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
@@ -774,12 +772,10 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f);
}
- for (i = 0, j = 0; i < cf->can_dlc; j++) {
- reg = ioread32(&priv->regs->ifregs[0].dataa1 + j*4);
- cf->data[i++] = cpu_to_le32(reg & 0xff);
- if (i == cf->can_dlc)
- break;
- cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
+ for (i = 0; i < cf->can_dlc; i += 2) {
+ data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
+ cf->data[i] = data_reg & 0xff;
+ cf->data[i + 1] = data_reg >> 8;
}
netif_receive_skb(skb);
@@ -815,72 +811,71 @@ RX_NEXT:
return rcv_pkts;
}
-static int pch_can_rx_poll(struct napi_struct *napi, int quota)
+
+static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
{
- struct net_device *ndev = napi->dev;
struct pch_can_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &(priv->ndev->stats);
u32 dlc;
+
+ can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
+ iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
+ &priv->regs->ifregs[1].cmask);
+ pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
+ dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
+ PCH_IF_MCONT_DLC);
+ stats->tx_bytes += dlc;
+ stats->tx_packets++;
+ if (int_stat == PCH_TX_OBJ_END)
+ netif_wake_queue(ndev);
+}
+
+static int pch_can_rx_poll(struct napi_struct *napi, int quota)
+{
+ struct net_device *ndev = napi->dev;
+ struct pch_can_priv *priv = netdev_priv(ndev);
u32 int_stat;
int rcv_pkts = 0;
u32 reg_stat;
int_stat = pch_can_int_pending(priv);
if (!int_stat)
- return 0;
+ goto end;
-INT_STAT:
- if (int_stat == PCH_STATUS_INT) {
+ if ((int_stat == PCH_STATUS_INT) && (quota > 0)) {
reg_stat = ioread32(&priv->regs->stat);
if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
- if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
+ if (reg_stat & PCH_BUS_OFF ||
+ (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
pch_can_error(ndev, reg_stat);
+ quota--;
+ }
}
- if (reg_stat & PCH_TX_OK) {
- iowrite32(PCH_CMASK_RX_TX_GET,
- &priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq,
- ioread32(&priv->regs->intr));
+ if (reg_stat & PCH_TX_OK)
pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
- }
if (reg_stat & PCH_RX_OK)
pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
int_stat = pch_can_int_pending(priv);
- if (int_stat == PCH_STATUS_INT)
- goto INT_STAT;
}
-MSG_OBJ:
+ if (quota == 0)
+ goto end;
+
if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
- rcv_pkts = pch_can_rx_normal(ndev, int_stat);
- if (rcv_pkts < 0)
- return 0;
+ rcv_pkts += pch_can_rx_normal(ndev, int_stat);
+ quota -= rcv_pkts;
+ if (quota < 0)
+ goto end;
} else if ((int_stat >= PCH_TX_OBJ_START) &&
(int_stat <= PCH_TX_OBJ_END)) {
/* Handle transmission interrupt */
- can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
- iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
- &priv->regs->ifregs[1].cmask);
- dlc = ioread32(&priv->regs->ifregs[1].mcont) &
- PCH_IF_MCONT_DLC;
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
- if (dlc > 8)
- dlc = 8;
- stats->tx_bytes += dlc;
- stats->tx_packets++;
- if (int_stat == PCH_TX_OBJ_END)
- netif_wake_queue(ndev);
+ pch_can_tx_complete(ndev, int_stat);
}
- int_stat = pch_can_int_pending(priv);
- if (int_stat == PCH_STATUS_INT)
- goto INT_STAT;
- else if (int_stat >= 1 && int_stat <= 32)
- goto MSG_OBJ;
-
+end:
napi_complete(napi);
pch_can_set_int_enables(priv, PCH_CAN_ALL);
@@ -1013,10 +1008,10 @@ static int pch_close(struct net_device *ndev)
static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
{
- int i, j;
struct pch_can_priv *priv = netdev_priv(ndev);
struct can_frame *cf = (struct can_frame *)skb->data;
int tx_buffer_avail = 0;
+ int i;
if (can_dropped_invalid_skb(ndev, skb))
return NETDEV_TX_OK;
@@ -1057,13 +1052,10 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
if (cf->can_id & CAN_RTR_FLAG)
pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
- for (i = 0, j = 0; i < cf->can_dlc; j++) {
- iowrite32(le32_to_cpu(cf->data[i++]),
- (&priv->regs->ifregs[1].dataa1) + j*4);
- if (i == cf->can_dlc)
- break;
- iowrite32(le32_to_cpu(cf->data[i++] << 8),
- (&priv->regs->ifregs[1].dataa1) + j*4);
+ /* Copy data to register */
+ for (i = 0; i < cf->can_dlc; i += 2) {
+ iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
+ &priv->regs->ifregs[1].data[i / 2]);
}
can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 07/20] can: EG20T PCH: Improve rx processing.
From: Tomoya MORINAGA @ 2010-11-30 4:23 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Replace complex "goto" to "do~while".
For easy to read/understand, it divides a rx function into some functions.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 160 +++++++++++++++++++++++----------------------
1 files changed, 83 insertions(+), 77 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 98e7e9f..8fb17dc 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -694,120 +694,126 @@ static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
+static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
+{
+ if (obj_id < PCH_FIFO_THRESH) {
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
+ PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
+
+ /* Clearing the Dir bit. */
+ pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
+
+ /* Clearing NewDat & IntPnd */
+ pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+ PCH_IF_MCONT_INTPND);
+ pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
+ } else if (obj_id > PCH_FIFO_THRESH) {
+ pch_can_int_clr(priv, obj_id);
+ } else if (obj_id == PCH_FIFO_THRESH) {
+ int cnt;
+ for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
+ pch_can_int_clr(priv, cnt + 1);
+ }
+}
+
+static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
+{
+ struct pch_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &(priv->ndev->stats);
+ struct sk_buff *skb;
+ struct can_frame *cf;
+
+ netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
+ pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+ PCH_IF_MCONT_MSGLOST);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
+ &priv->regs->ifregs[0].cmask);
+ pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
+
+ skb = alloc_can_err_skb(ndev, &cf);
+ if (!skb)
+ return;
+
+ cf->can_id |= CAN_ERR_CRTL;
+ cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+ stats->rx_over_errors++;
+ stats->rx_errors++;
+
+ netif_receive_skb(skb);
+}
+
+static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
{
u32 reg;
canid_t id;
- u32 ide;
- u32 rtr;
- int i, k;
int rcv_pkts = 0;
struct sk_buff *skb;
struct can_frame *cf;
struct pch_can_priv *priv = netdev_priv(ndev);
struct net_device_stats *stats = &(priv->ndev->stats);
+ int i;
+ u32 id2;
u16 data_reg;
- /* Reading the messsage object from the Message RAM */
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, int_stat);
+ do {
+ /* Reading the messsage object from the Message RAM */
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+ pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num);
- /* Reading the MCONT register. */
- reg = ioread32(&priv->regs->ifregs[0].mcont);
- reg &= 0xffff;
+ /* Reading the MCONT register. */
+ reg = ioread32(&priv->regs->ifregs[0].mcont);
+
+ if (reg & PCH_IF_MCONT_EOB)
+ break;
- for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
/* If MsgLost bit set. */
if (reg & PCH_IF_MCONT_MSGLOST) {
- dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
- pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
- PCH_IF_MCONT_MSGLOST);
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
- &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
-
- skb = alloc_can_err_skb(ndev, &cf);
- if (!skb)
- return -ENOMEM;
-
- priv->can.can_stats.error_passive++;
- priv->can.state = CAN_STATE_ERROR_PASSIVE;
- cf->can_id |= CAN_ERR_CRTL;
- cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
- cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
- stats->rx_packets++;
- stats->rx_bytes += cf->can_dlc;
-
- netif_receive_skb(skb);
+ pch_can_rx_msg_lost(ndev, obj_num);
rcv_pkts++;
- goto RX_NEXT;
+ quota--;
+ obj_num++;
+ continue;
+ } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
+ obj_num++;
+ continue;
}
- if (!(reg & PCH_IF_MCONT_NEWDAT))
- goto RX_NEXT;
skb = alloc_can_skb(priv->ndev, &cf);
if (!skb)
return -ENOMEM;
/* Get Received data */
- ide = ((ioread32(&priv->regs->ifregs[0].id2)) & PCH_ID2_XTD) >>
- 14;
- if (ide) {
+ id2 = ioread32(&priv->regs->ifregs[0].id2);
+ if (id2 & PCH_ID2_XTD) {
id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
- id |= (((ioread32(&priv->regs->ifregs[0].id2)) &
- 0x1fff) << 16);
- cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ id |= (((id2) & 0x1fff) << 16);
+ cf->can_id = id | CAN_EFF_FLAG;
} else {
- id = (((ioread32(&priv->regs->ifregs[0].id2)) &
- (CAN_SFF_MASK << 2)) >> 2);
- cf->can_id = (id & CAN_SFF_MASK);
+ id = (id2 >> 2) & CAN_SFF_MASK;
+ cf->can_id = id;
}
- rtr = (ioread32(&priv->regs->ifregs[0].id2) & PCH_ID2_DIR);
- if (rtr) {
- cf->can_dlc = 0;
+ if (id2 & PCH_ID2_DIR)
cf->can_id |= CAN_RTR_FLAG;
- } else {
- cf->can_dlc =
- ((ioread32(&priv->regs->ifregs[0].mcont)) & 0x0f);
- }
+
+ cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
+ ifregs[0].mcont)) & 0xF);
for (i = 0; i < cf->can_dlc; i += 2) {
data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
- cf->data[i] = data_reg & 0xff;
+ cf->data[i] = data_reg;
cf->data[i + 1] = data_reg >> 8;
}
netif_receive_skb(skb);
rcv_pkts++;
stats->rx_packets++;
+ quota--;
stats->rx_bytes += cf->can_dlc;
- if (k < PCH_FIFO_THRESH) {
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
- PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
-
- /* Clearing the Dir bit. */
- pch_can_bit_clear(&priv->regs->ifregs[0].id2,
- PCH_ID2_DIR);
-
- /* Clearing NewDat & IntPnd */
- pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
- PCH_IF_MCONT_INTPND);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
- } else if (k > PCH_FIFO_THRESH) {
- pch_can_int_clr(priv, k);
- } else if (k == PCH_FIFO_THRESH) {
- int cnt;
- for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
- pch_can_int_clr(priv, cnt+1);
- }
-RX_NEXT:
- /* Reading the messsage object from the Message RAM */
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, k);
- reg = ioread32(&priv->regs->ifregs[0].mcont);
- }
+ pch_fifo_thresh(priv, obj_num);
+ obj_num++;
+ } while (quota > 0);
return rcv_pkts;
}
@@ -865,7 +871,7 @@ static int pch_can_rx_poll(struct napi_struct *napi, int quota)
goto end;
if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
- rcv_pkts += pch_can_rx_normal(ndev, int_stat);
+ rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
quota -= rcv_pkts;
if (quota < 0)
goto end;
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 08/20] can: EG20T PCH: Rename function/macro name
From: Tomoya MORINAGA @ 2010-11-30 4:25 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
For easy to read/understand, Rename function/macro name.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 356 +++++++++++++++++++++------------------------
1 files changed, 164 insertions(+), 192 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 8fb17dc..11492a3 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -32,8 +32,6 @@
#include <linux/can/dev.h>
#include <linux/can/error.h>
-#define PCH_ENABLE 1 /* The enable flag */
-#define PCH_DISABLE 0 /* The disable flag */
#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
@@ -78,11 +76,12 @@
#define PCH_BUS_OFF BIT(7)
/* bit position of certain controller bits. */
-#define PCH_BIT_BRP 0
-#define PCH_BIT_SJW 6
-#define PCH_BIT_TSEG1 8
-#define PCH_BIT_TSEG2 12
-#define PCH_BIT_BRPE_BRPE 6
+#define PCH_BIT_BRP_SHIFT 0
+#define PCH_BIT_SJW_SHIFT 6
+#define PCH_BIT_TSEG1_SHIFT 8
+#define PCH_BIT_TSEG2_SHIFT 12
+#define PCH_BIT_BRPE_BRPE_SHIFT 6
+
#define PCH_MSK_BITT_BRP 0x3f
#define PCH_MSK_BRPE_BRPE 0x3c0
#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
@@ -102,6 +101,10 @@
#define PCH_FIFO_THRESH 16
+/* TxRqst2 show status of MsgObjNo.17~32 */
+#define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
+ (PCH_RX_OBJ_END - 16))
+
enum pch_ifreg {
PCH_RX_IFREG,
PCH_TX_IFREG,
@@ -166,19 +169,16 @@ struct pch_can_regs {
struct pch_can_priv {
struct can_priv can;
- unsigned int can_num;
struct pci_dev *dev;
- int tx_enable[PCH_TX_OBJ_END];
- int rx_enable[PCH_TX_OBJ_END];
- int rx_link[PCH_TX_OBJ_END];
- unsigned int int_enables;
- unsigned int int_stat;
+ u32 tx_enable[PCH_TX_OBJ_END];
+ u32 rx_enable[PCH_TX_OBJ_END];
+ u32 rx_link[PCH_TX_OBJ_END];
+ u32 int_enables;
struct net_device *ndev;
- unsigned int msg_obj[PCH_TX_OBJ_END];
struct pch_can_regs __iomem *regs;
struct napi_struct napi;
- unsigned int tx_obj; /* Point next Tx Obj index */
- unsigned int use_msi;
+ int tx_obj; /* Point next Tx Obj index */
+ int use_msi;
};
static struct can_bittiming_const pch_can_bittiming_const = {
@@ -241,31 +241,27 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
iowrite32(reg_val, &priv->regs->opt);
}
-static void pch_can_set_int_custom(struct pch_can_priv *priv)
+static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
{
- /* Clearing the IE, SIE and EIE bits of Can control register. */
- pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
-
- /* Appropriately setting them. */
- pch_can_bit_set(&priv->regs->cont,
- ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
-}
+ int counter = PCH_COUNTER_LIMIT;
+ u32 ifx_creq;
-/* This function retrieves interrupt enabled for the CAN device. */
-static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
-{
- /* Obtaining the status of IE, SIE and EIE interrupt bits. */
- *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
+ iowrite32(num, creq_addr);
+ while (counter) {
+ ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
+ if (!ifx_creq)
+ break;
+ counter--;
+ udelay(1);
+ }
+ if (!counter)
+ pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
}
static void pch_can_set_int_enables(struct pch_can_priv *priv,
enum pch_can_mode interrupt_no)
{
switch (interrupt_no) {
- case PCH_CAN_ENABLE:
- pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
- break;
-
case PCH_CAN_DISABLE:
pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
break;
@@ -284,25 +280,8 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
}
}
-static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
-{
- u32 counter = PCH_COUNTER_LIMIT;
- u32 ifx_creq;
-
- iowrite32(num, creq_addr);
- while (counter) {
- ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
- if (!ifx_creq)
- break;
- counter--;
- udelay(1);
- }
- if (!counter)
- pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
-}
-
static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
- u32 set, enum pch_ifreg dir)
+ int set, enum pch_ifreg dir)
{
u32 ie;
@@ -313,27 +292,27 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
/* Reading the receive buffer data from RAM to Interface1 registers */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
/* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[dir].cmask);
- if (set == PCH_ENABLE) {
+ if (set) {
/* Setting the MsgVal and RxIE bits */
pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
- } else if (set == PCH_DISABLE) {
+ } else {
/* Resetting the MsgVal and RxIE bits */
pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
}
- pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
}
-static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
+static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
{
int i;
@@ -342,7 +321,7 @@ static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
}
-static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
+static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
{
int i;
@@ -351,66 +330,16 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
}
-static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
- enum pch_ifreg dir)
-{
- u32 ie, enable;
-
- if (dir)
- ie = PCH_IF_MCONT_RXIE;
- else
- ie = PCH_IF_MCONT_TXIE;
-
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
-
- if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
- ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
- enable = 1;
- } else {
- enable = 0;
- }
- return enable;
-}
-
-static int pch_can_int_pending(struct pch_can_priv *priv)
+static u32 pch_can_int_pending(struct pch_can_priv *priv)
{
return ioread32(&priv->regs->intr) & 0xffff;
}
-static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
- u32 buffer_num, u32 set)
-{
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
- &priv->regs->ifregs[0].cmask);
- if (set == PCH_ENABLE)
- pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
- PCH_IF_MCONT_EOB);
- else
- pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
-
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
-}
-
-static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
- u32 buffer_num, u32 *link)
+static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
{
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
-
- if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
- *link = PCH_DISABLE;
- else
- *link = PCH_ENABLE;
-}
+ int i; /* Msg Obj ID (1~32) */
-static void pch_can_clear_buffers(struct pch_can_priv *priv)
-{
- int i;
-
- for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
+ for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
@@ -424,24 +353,7 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
- }
-
- for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
- iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask);
- iowrite32(0xffff, &priv->regs->ifregs[1].mask1);
- iowrite32(0xffff, &priv->regs->ifregs[1].mask2);
- iowrite32(0x0, &priv->regs->ifregs[1].id1);
- iowrite32(0x0, &priv->regs->ifregs[1].id2);
- iowrite32(0x0, &priv->regs->ifregs[1].mcont);
- iowrite32(0x0, &priv->regs->ifregs[1].data[0]);
- iowrite32(0x0, &priv->regs->ifregs[1].data[1]);
- iowrite32(0x0, &priv->regs->ifregs[1].data[2]);
- iowrite32(0x0, &priv->regs->ifregs[1].data[3]);
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
- PCH_CMASK_ARB | PCH_CMASK_CTRL,
- &priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
}
}
@@ -452,7 +364,7 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
iowrite32(PCH_CMASK_RX_TX_GET,
&priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
iowrite32(0x0, &priv->regs->ifregs[0].id1);
iowrite32(0x0, &priv->regs->ifregs[0].id2);
@@ -460,12 +372,12 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
pch_can_bit_set(&priv->regs->ifregs[0].mcont,
PCH_IF_MCONT_UMASK);
- /* Set FIFO mode set to 0 except last Rx Obj*/
- pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
- PCH_IF_MCONT_EOB);
/* In case FIFO mode, Last EoB of Rx Obj must be 1 */
if (i == PCH_RX_OBJ_END)
pch_can_bit_set(&priv->regs->ifregs[0].mcont,
+ PCH_IF_MCONT_EOB);
+ else
+ pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
PCH_IF_MCONT_EOB);
iowrite32(0, &priv->regs->ifregs[0].mask1);
@@ -477,24 +389,21 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
}
for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
iowrite32(PCH_CMASK_RX_TX_GET,
&priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
/* Resetting DIR bit for reception */
iowrite32(0x0, &priv->regs->ifregs[1].id1);
- iowrite32(0x0, &priv->regs->ifregs[1].id2);
- pch_can_bit_set(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
+ iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
/* Setting EOB bit for transmitter */
- iowrite32(PCH_IF_MCONT_EOB, &priv->regs->ifregs[1].mcont);
-
- pch_can_bit_set(&priv->regs->ifregs[1].mcont,
- PCH_IF_MCONT_UMASK);
+ iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
+ &priv->regs->ifregs[1].mcont);
iowrite32(0, &priv->regs->ifregs[1].mask1);
pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
@@ -504,7 +413,7 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
}
}
@@ -514,7 +423,7 @@ static void pch_can_init(struct pch_can_priv *priv)
pch_can_set_run_mode(priv, PCH_CAN_STOP);
/* Clearing all the message object buffers. */
- pch_can_clear_buffers(priv);
+ pch_can_clear_if_buffers(priv);
/* Configuring the respective message object as either rx/tx object. */
pch_can_config_rx_tx_buffers(priv);
@@ -559,7 +468,7 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
} else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
/* Setting CMASK for clearing interrupts for
frame transmission. */
@@ -575,14 +484,14 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
PCH_IF_MCONT_TXRQXT);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
}
}
-static int pch_can_get_buffer_status(struct pch_can_priv *priv)
+static u32 pch_can_get_buffer_status(struct pch_can_priv *priv)
{
return (ioread32(&priv->regs->treq1) & 0xffff) |
- ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
+ (ioread32(&priv->regs->treq2) << 16);
}
static void pch_can_reset(struct pch_can_priv *priv)
@@ -615,12 +524,12 @@ static void pch_can_error(struct net_device *ndev, u32 status)
dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
}
+ errc = ioread32(&priv->regs->errc);
/* Warning interrupt. */
if (status & PCH_EWARN) {
state = CAN_STATE_ERROR_WARNING;
priv->can.can_stats.error_warning++;
cf->can_id |= CAN_ERR_CRTL;
- errc = ioread32(&priv->regs->errc);
if (((errc & PCH_REC) >> 8) > 96)
cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
if ((errc & PCH_TEC) > 96)
@@ -633,7 +542,6 @@ static void pch_can_error(struct net_device *ndev, u32 status)
priv->can.can_stats.error_passive++;
state = CAN_STATE_ERROR_PASSIVE;
cf->can_id |= CAN_ERR_CRTL;
- errc = ioread32(&priv->regs->errc);
if (((errc & PCH_REC) >> 8) > 127)
cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
if ((errc & PCH_TEC) > 127)
@@ -706,7 +614,7 @@ static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
/* Clearing NewDat & IntPnd */
pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
PCH_IF_MCONT_INTPND);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
} else if (obj_id > PCH_FIFO_THRESH) {
pch_can_int_clr(priv, obj_id);
} else if (obj_id == PCH_FIFO_THRESH) {
@@ -728,7 +636,7 @@ static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
PCH_IF_MCONT_MSGLOST);
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
&priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
skb = alloc_can_err_skb(ndev, &cf);
if (!skb)
@@ -758,7 +666,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
do {
/* Reading the messsage object from the Message RAM */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
/* Reading the MCONT register. */
reg = ioread32(&priv->regs->ifregs[0].mcont);
@@ -827,7 +735,7 @@ static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
&priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
PCH_IF_MCONT_DLC);
stats->tx_bytes += dlc;
@@ -836,7 +744,7 @@ static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
netif_wake_queue(ndev);
}
-static int pch_can_rx_poll(struct napi_struct *napi, int quota)
+static int pch_can_poll(struct napi_struct *napi, int quota)
{
struct net_device *ndev = napi->dev;
struct pch_can_priv *priv = netdev_priv(ndev);
@@ -901,10 +809,10 @@ static int pch_set_bittiming(struct net_device *ndev)
brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
canbit = brp & PCH_MSK_BITT_BRP;
- canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
- canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
- canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
- bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
+ canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
+ canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
+ canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
+ bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
iowrite32(canbit, &priv->regs->bitt);
iowrite32(bepe, &priv->regs->brpe);
pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
@@ -1016,47 +924,49 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
{
struct pch_can_priv *priv = netdev_priv(ndev);
struct can_frame *cf = (struct can_frame *)skb->data;
- int tx_buffer_avail = 0;
+ int tx_obj_no;
int i;
+ u32 id2;
if (can_dropped_invalid_skb(ndev, skb))
return NETDEV_TX_OK;
if (priv->tx_obj == PCH_TX_OBJ_END) {
- if (ioread32(&priv->regs->treq2) & 0xfc00)
+ if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
netif_stop_queue(ndev);
- tx_buffer_avail = priv->tx_obj;
+ tx_obj_no = priv->tx_obj;
priv->tx_obj = PCH_TX_OBJ_START;
} else {
- tx_buffer_avail = priv->tx_obj;
+ tx_obj_no = priv->tx_obj;
priv->tx_obj++;
}
/* Reading the Msg Obj from the Msg RAM to the Interface register. */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
/* Setting the CMASK register. */
pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
/* If ID extended is set. */
- pch_can_bit_clear(&priv->regs->ifregs[1].id1, 0xffff);
- pch_can_bit_clear(&priv->regs->ifregs[1].id2, 0x1fff | PCH_ID2_XTD);
if (cf->can_id & CAN_EFF_FLAG) {
- pch_can_bit_set(&priv->regs->ifregs[1].id1,
- cf->can_id & 0xffff);
- pch_can_bit_set(&priv->regs->ifregs[1].id2,
- ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
+ iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
+ id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
} else {
- pch_can_bit_set(&priv->regs->ifregs[1].id1, 0);
- pch_can_bit_set(&priv->regs->ifregs[1].id2,
- (cf->can_id & CAN_SFF_MASK) << 2);
+ iowrite32(0, &priv->regs->ifregs[1].id1);
+ id2 = (cf->can_id & CAN_SFF_MASK) << 2;
}
+ id2 |= PCH_ID_MSGVAL;
+
/* If remote frame has to be transmitted.. */
if (cf->can_id & CAN_RTR_FLAG)
- pch_can_bit_clear(&priv->regs->ifregs[1].id2, PCH_ID2_DIR);
+ id2 &= ~PCH_ID2_DIR;
+ else
+ id2 |= PCH_ID2_DIR;
+
+ iowrite32(id2, &priv->regs->ifregs[1].id2);
/* Copy data to register */
for (i = 0; i < cf->can_dlc; i += 2) {
@@ -1064,22 +974,13 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
&priv->regs->ifregs[1].data[i / 2]);
}
- can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1);
+ can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
/* Updating the size of the data. */
- pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f);
- pch_can_bit_set(&priv->regs->ifregs[1].mcont, cf->can_dlc);
+ iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
+ PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
- /* Clearing IntPend, NewDat & TxRqst */
- pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
- PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
- PCH_IF_MCONT_TXRQXT);
-
- /* Setting NewDat, TxRqst bits */
- pch_can_bit_set(&priv->regs->ifregs[1].mcont,
- PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
-
- pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
return NETDEV_TX_OK;
}
@@ -1105,12 +1006,82 @@ static void __devexit pch_can_remove(struct pci_dev *pdev)
}
#ifdef CONFIG_PM
+static void pch_can_set_int_custom(struct pch_can_priv *priv)
+{
+ /* Clearing the IE, SIE and EIE bits of Can control register. */
+ pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
+
+ /* Appropriately setting them. */
+ pch_can_bit_set(&priv->regs->cont,
+ ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
+}
+
+/* This function retrieves interrupt enabled for the CAN device. */
+static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
+{
+ /* Obtaining the status of IE, SIE and EIE interrupt bits. */
+ return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
+}
+
+static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
+ enum pch_ifreg dir)
+{
+ u32 ie, enable;
+
+ if (dir)
+ ie = PCH_IF_MCONT_RXIE;
+ else
+ ie = PCH_IF_MCONT_TXIE;
+
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
+
+ if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
+ ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
+ enable = 1;
+ } else {
+ enable = 0;
+ }
+ return enable;
+}
+
+static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
+ u32 buffer_num, int set)
+{
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
+ &priv->regs->ifregs[0].cmask);
+ if (set)
+ pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+ PCH_IF_MCONT_EOB);
+ else
+ pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
+
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+}
+
+static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
+{
+ u32 link;
+
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+ pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+
+ if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
+ link = 0;
+ else
+ link = 1;
+ return link;
+}
+
+
static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
{
int i; /* Counter variable. */
int retval; /* Return value. */
u32 buf_stat; /* Variable for reading the transmit buffer status. */
- u32 counter = 0xFFFFFF;
+ int counter = PCH_COUNTER_LIMIT;
struct net_device *dev = pci_get_drvdata(pdev);
struct pch_can_priv *priv = netdev_priv(dev);
@@ -1133,7 +1104,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
/* Save interrupt configuration and then disable them */
- pch_can_get_int_enables(priv, &(priv->int_enables));
+ priv->int_enables = pch_can_get_int_enables(priv);
pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
/* Save Tx buffer enable state */
@@ -1146,7 +1117,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
/* Save Rx buffer enable state */
for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
- pch_can_get_rx_buffer_link(priv, i, &priv->rx_link[i]);
+ priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
}
/* Disable all Receive buffers */
@@ -1227,9 +1198,10 @@ static int pch_can_get_berr_counter(const struct net_device *dev,
struct can_berr_counter *bec)
{
struct pch_can_priv *priv = netdev_priv(dev);
+ u32 errc = ioread32(&priv->regs->errc);
- bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
- bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
+ bec->txerr = errc & PCH_TEC;
+ bec->rxerr = (errc & PCH_REC) >> 8;
return 0;
}
@@ -1287,7 +1259,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
ndev->netdev_ops = &pch_can_netdev_ops;
priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
- netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END);
+ netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
rc = register_candev(ndev);
if (rc) {
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 09/20] can: EG20T PCH: Change Copyright and module description
From: Tomoya MORINAGA @ 2010-11-30 4:26 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Currently, Copyright and module description are not formal.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 11492a3..01d4126 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 1999 - 2010 Intel Corporation.
- * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -1302,6 +1302,6 @@ static void __exit pch_can_pci_exit(void)
}
module_exit(pch_can_pci_exit);
-MODULE_DESCRIPTION("Controller Area Network Driver");
+MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
MODULE_LICENSE("GPL v2");
MODULE_VERSION("0.94");
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 10/20] can: EG20T PCH: Replace netdev_dbg instead of dev_dbg partly
From: Tomoya MORINAGA @ 2010-11-30 4:27 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
For easy to readable, use netdev_dbg instead of dev_dbg partly
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 01d4126..09d0844 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -222,7 +222,7 @@ static void pch_can_set_run_mode(struct pch_can_priv *priv,
break;
default:
- dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
+ netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
break;
}
}
@@ -275,7 +275,7 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
break;
default:
- dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
+ netdev_err(priv->ndev, "Invalid interrupt number.\n");
break;
}
}
@@ -534,7 +534,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
if ((errc & PCH_TEC) > 96)
cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
- dev_warn(&ndev->dev,
+ netdev_dbg(ndev,
"%s -> Error Counter is more than 96.\n", __func__);
}
/* Error passive interrupt. */
@@ -546,7 +546,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
if ((errc & PCH_TEC) > 127)
cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
- dev_err(&ndev->dev,
+ netdev_dbg(ndev,
"%s -> CAN controller is ERROR PASSIVE .\n", __func__);
}
@@ -865,10 +865,10 @@ static int pch_can_open(struct net_device *ndev)
retval = pci_enable_msi(priv->dev);
if (retval) {
- dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
+ netdev_err(ndev, "PCH CAN opened without MSI\n");
priv->use_msi = 0;
} else {
- dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
+ netdev_err(ndev, "PCH CAN opened with MSI\n");
priv->use_msi = 1;
}
@@ -876,14 +876,14 @@ static int pch_can_open(struct net_device *ndev)
retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
ndev->name, ndev);
if (retval) {
- dev_err(&ndev->dev, "request_irq failed.\n");
+ netdev_err(ndev, "request_irq failed.\n");
goto req_irq_err;
}
/* Open common can device */
retval = open_candev(ndev);
if (retval) {
- dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
+ netdev_err(ndev, "open_candev() failed %d\n", retval);
goto err_open_candev;
}
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 11/20] can: EG20T PCH: Fix coding rule violation.
From: Tomoya MORINAGA @ 2010-11-30 4:30 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Fix coding rule violation.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/net/can/pch_can.c | 45 +++++++++++++++++++++------------------------
1 files changed, 21 insertions(+), 24 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 09d0844..8e607ad 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -89,9 +89,11 @@
#define PCH_CAN_CLK 50000000 /* 50MHz */
-/* Define the number of message object.
+/*
+ * Define the number of message object.
* PCH CAN communications are done via Message RAM.
- * The Message RAM consists of 32 message objects. */
+ * The Message RAM consists of 32 message objects.
+ */
#define PCH_RX_OBJ_NUM 26
#define PCH_TX_OBJ_NUM 6
#define PCH_RX_OBJ_START 1
@@ -126,7 +128,7 @@ enum pch_can_mode {
PCH_CAN_ALL,
PCH_CAN_NONE,
PCH_CAN_STOP,
- PCH_CAN_RUN
+ PCH_CAN_RUN,
};
struct pch_can_if_regs {
@@ -290,21 +292,20 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
else
ie = PCH_IF_MCONT_RXIE;
- /* Reading the receive buffer data from RAM to Interface1 registers */
+ /* Reading the receive buffer data from RAM to Interface1/2 registers */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
- /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
+ /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
&priv->regs->ifregs[dir].cmask);
if (set) {
- /* Setting the MsgVal and RxIE bits */
+ /* Setting the MsgVal and RxIE/TxIE bits */
pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
-
} else {
- /* Resetting the MsgVal and RxIE bits */
+ /* Clearing the MsgVal and RxIE/TxIE bits */
pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
}
@@ -362,8 +363,7 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
int i;
for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
- iowrite32(PCH_CMASK_RX_TX_GET,
- &priv->regs->ifregs[0].cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
iowrite32(0x0, &priv->regs->ifregs[0].id1);
@@ -385,16 +385,14 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
0x1fff | PCH_MASK2_MDIR_MXTD);
/* Setting CMASK for writing */
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
- PCH_CMASK_ARB | PCH_CMASK_CTRL,
- &priv->regs->ifregs[0].cmask);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
+ PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
}
for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
- iowrite32(PCH_CMASK_RX_TX_GET,
- &priv->regs->ifregs[1].cmask);
+ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
/* Resetting DIR bit for reception */
@@ -409,9 +407,8 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
/* Setting CMASK for writing */
- iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
- PCH_CMASK_ARB | PCH_CMASK_CTRL,
- &priv->regs->ifregs[1].cmask);
+ iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
+ PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
}
@@ -470,8 +467,9 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
} else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
- /* Setting CMASK for clearing interrupts for
- frame transmission. */
+ /*
+ * Setting CMASK for clearing interrupts for frame transmission.
+ */
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
&priv->regs->ifregs[1].cmask);
@@ -596,7 +594,6 @@ static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
struct pch_can_priv *priv = netdev_priv(ndev);
pch_can_set_int_enables(priv, PCH_CAN_NONE);
-
napi_schedule(&priv->napi);
return IRQ_HANDLED;
@@ -1037,11 +1034,11 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
- ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
+ ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
enable = 1;
- } else {
+ else
enable = 0;
- }
+
return enable;
}
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 12/20] can: EG20T PCH: Delete unnecessary/redundant code
From: Tomoya MORINAGA @ 2010-11-30 4:31 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Delete unnecessary/redundant code.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 14 +-------------
1 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 8e607ad..9f5241b 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -447,11 +447,6 @@ static void pch_can_release(struct pch_can_priv *priv)
/* This function clears interrupt(s) from the CAN device. */
static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
{
- if (mask == PCH_STATUS_INT) {
- ioread32(&priv->regs->stat);
- return;
- }
-
/* Clear interrupt for transmit object */
if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
/* Setting CMASK for clearing the reception interrupts. */
@@ -518,8 +513,6 @@ static void pch_can_error(struct net_device *ndev, u32 status)
state = CAN_STATE_BUS_OFF;
cf->can_id |= CAN_ERR_BUSOFF;
can_bus_off(ndev);
- pch_can_set_run_mode(priv, PCH_CAN_RUN);
- dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
}
errc = ioread32(&priv->regs->errc);
@@ -753,7 +746,7 @@ static int pch_can_poll(struct napi_struct *napi, int quota)
if (!int_stat)
goto end;
- if ((int_stat == PCH_STATUS_INT) && (quota > 0)) {
+ if (int_stat == PCH_STATUS_INT) {
reg_stat = ioread32(&priv->regs->stat);
if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
if (reg_stat & PCH_BUS_OFF ||
@@ -939,10 +932,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
priv->tx_obj++;
}
- /* Reading the Msg Obj from the Msg RAM to the Interface register. */
- iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
- pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
-
/* Setting the CMASK register. */
pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
@@ -1072,7 +1061,6 @@ static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
return link;
}
-
static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
{
int i; /* Counter variable. */
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 13/20] can: EG20T PCH: Fix bit timing calculation issue
From: Tomoya MORINAGA @ 2010-11-30 4:34 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Modify to use calculated value directly passed by CAN core module.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
drivers/net/can/pch_can.c | 6 ++----
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 9f5241b..b57b505 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -792,17 +792,15 @@ static int pch_set_bittiming(struct net_device *ndev)
const struct can_bittiming *bt = &priv->can.bittiming;
u32 canbit;
u32 bepe;
- u32 brp;
/* Setting the CCE bit for accessing the Can Timing register. */
pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
- brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
- canbit = brp & PCH_MSK_BITT_BRP;
+ canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
- bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
+ bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
iowrite32(canbit, &priv->regs->bitt);
iowrite32(bepe, &priv->regs->brpe);
pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 14/20] can: EG20T PCH: Fix miss-setting status issue
From: Tomoya MORINAGA @ 2010-11-30 4:35 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Modify miss-setting status issue at suspend.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index b57b505..1009d9b 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -1073,7 +1073,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
pch_can_set_run_mode(priv, PCH_CAN_STOP);
/* Indicate that we are aboutto/in suspend */
- priv->can.state = CAN_STATE_SLEEPING;
+ priv->can.state = CAN_STATE_STOPPED;
/* Waiting for all transmission to complete. */
while (counter) {
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 15/20] can: EG20T PCH: Comment optimization
From: Tomoya MORINAGA @ 2010-11-30 4:36 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Comment optimization.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 1009d9b..6508dca 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -292,7 +292,7 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
else
ie = PCH_IF_MCONT_RXIE;
- /* Reading the receive buffer data from RAM to Interface1/2 registers */
+ /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
@@ -860,7 +860,7 @@ static int pch_can_open(struct net_device *ndev)
priv->use_msi = 1;
}
- /* Regsitering the interrupt. */
+ /* Regstering the interrupt. */
retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
ndev->name, ndev);
if (retval) {
@@ -960,7 +960,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
- /* Updating the size of the data. */
+ /* Set the size of the data. Update if2_mcont */
iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
@@ -1061,8 +1061,8 @@ static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
{
- int i; /* Counter variable. */
- int retval; /* Return value. */
+ int i;
+ int retval;
u32 buf_stat; /* Variable for reading the transmit buffer status. */
int counter = PCH_COUNTER_LIMIT;
@@ -1119,8 +1119,8 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
static int pch_can_resume(struct pci_dev *pdev)
{
- int i; /* Counter variable. */
- int retval; /* Return variable. */
+ int i;
+ int retval;
struct net_device *dev = pci_get_drvdata(pdev);
struct pch_can_priv *priv = netdev_priv(dev);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 16/20] can: EG20T PCH: Move MSI processing to probe/remove processing
From: Tomoya MORINAGA @ 2010-11-30 4:37 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Currently, in case this driver is integrated as module, and when this
module is re-installed, no interrupts is to be occurred.
For the above issue, move MSI processing to open/release processing.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 29 ++++++++++++++---------------
1 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 6508dca..f8b4a66 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -851,15 +851,6 @@ static int pch_can_open(struct net_device *ndev)
struct pch_can_priv *priv = netdev_priv(ndev);
int retval;
- retval = pci_enable_msi(priv->dev);
- if (retval) {
- netdev_err(ndev, "PCH CAN opened without MSI\n");
- priv->use_msi = 0;
- } else {
- netdev_err(ndev, "PCH CAN opened with MSI\n");
- priv->use_msi = 1;
- }
-
/* Regstering the interrupt. */
retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
ndev->name, ndev);
@@ -885,9 +876,6 @@ static int pch_can_open(struct net_device *ndev)
err_open_candev:
free_irq(priv->dev->irq, ndev);
req_irq_err:
- if (priv->use_msi)
- pci_disable_msi(priv->dev);
-
pch_can_release(priv);
return retval;
@@ -901,8 +889,6 @@ static int pch_close(struct net_device *ndev)
napi_disable(&priv->napi);
pch_can_release(priv);
free_irq(priv->dev->irq, ndev);
- if (priv->use_msi)
- pci_disable_msi(priv->dev);
close_candev(ndev);
priv->can.state = CAN_STATE_STOPPED;
return 0;
@@ -981,12 +967,14 @@ static void __devexit pch_can_remove(struct pci_dev *pdev)
struct pch_can_priv *priv = netdev_priv(ndev);
unregister_candev(priv->ndev);
- free_candev(priv->ndev);
pci_iounmap(pdev, priv->regs);
+ if (priv->use_msi)
+ pci_disable_msi(priv->dev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
pch_can_reset(priv);
+ free_candev(priv->ndev);
}
#ifdef CONFIG_PM
@@ -1244,6 +1232,15 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
+ rc = pci_enable_msi(priv->dev);
+ if (rc) {
+ netdev_err(ndev, "PCH CAN opened without MSI\n");
+ priv->use_msi = 0;
+ } else {
+ netdev_err(ndev, "PCH CAN opened with MSI\n");
+ priv->use_msi = 1;
+ }
+
rc = register_candev(ndev);
if (rc) {
dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
@@ -1253,6 +1250,8 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
return 0;
probe_exit_reg_candev:
+ if (priv->use_msi)
+ pci_disable_msi(priv->dev);
free_candev(ndev);
probe_exit_alloc_candev:
pci_iounmap(pdev, addr);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 17/20] can: EG20T PCH: Fix incorrect return processing
From: Tomoya MORINAGA @ 2010-11-30 4:38 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Fix incorrect return processing
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index f8b4a66..743385b 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -586,9 +586,11 @@ static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
struct net_device *ndev = (struct net_device *)dev_id;
struct pch_can_priv *priv = netdev_priv(ndev);
+ if (!pch_can_int_pending(priv))
+ return IRQ_NONE;
+
pch_can_set_int_enables(priv, PCH_CAN_NONE);
napi_schedule(&priv->napi);
-
return IRQ_HANDLED;
}
@@ -677,8 +679,10 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
}
skb = alloc_can_skb(priv->ndev, &cf);
- if (!skb)
- return -ENOMEM;
+ if (!skb) {
+ netdev_err(ndev, "alloc_can_skb Failed\n");
+ return rcv_pkts;
+ }
/* Get Received data */
id2 = ioread32(&priv->regs->ifregs[0].id2);
@@ -739,8 +743,8 @@ static int pch_can_poll(struct napi_struct *napi, int quota)
struct net_device *ndev = napi->dev;
struct pch_can_priv *priv = netdev_priv(ndev);
u32 int_stat;
- int rcv_pkts = 0;
u32 reg_stat;
+ int quota_save = quota;
int_stat = pch_can_int_pending(priv);
if (!int_stat)
@@ -769,10 +773,7 @@ static int pch_can_poll(struct napi_struct *napi, int quota)
goto end;
if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
- rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
- quota -= rcv_pkts;
- if (quota < 0)
- goto end;
+ quota -= pch_can_rx_normal(ndev, int_stat, quota);
} else if ((int_stat >= PCH_TX_OBJ_START) &&
(int_stat <= PCH_TX_OBJ_END)) {
/* Handle transmission interrupt */
@@ -783,7 +784,7 @@ end:
napi_complete(napi);
pch_can_set_int_enables(priv, PCH_CAN_ALL);
- return rcv_pkts;
+ return quota_save - quota;
}
static int pch_set_bittiming(struct net_device *ndev)
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 18/20] can: EG20T PCH: Optimize "if" condition
From: Tomoya MORINAGA @ 2010-11-30 4:39 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
For reduce "if" condition, easy to read/understand the code,
optimize "if" condition in rx/tx processing.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 26 ++++++++++----------------
1 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 743385b..e11ec36 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -752,19 +752,16 @@ static int pch_can_poll(struct napi_struct *napi, int quota)
if (int_stat == PCH_STATUS_INT) {
reg_stat = ioread32(&priv->regs->stat);
- if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
- if (reg_stat & PCH_BUS_OFF ||
- (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
- pch_can_error(ndev, reg_stat);
- quota--;
- }
- }
- if (reg_stat & PCH_TX_OK)
- pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
+ if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
+ ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
+ pch_can_error(ndev, reg_stat);
+ quota--;
+ }
- if (reg_stat & PCH_RX_OK)
- pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
+ if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
+ pch_can_bit_clear(&priv->regs->stat,
+ reg_stat & (PCH_TX_OK | PCH_RX_OK));
int_stat = pch_can_int_pending(priv);
}
@@ -906,14 +903,13 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
if (can_dropped_invalid_skb(ndev, skb))
return NETDEV_TX_OK;
+ tx_obj_no = priv->tx_obj;
if (priv->tx_obj == PCH_TX_OBJ_END) {
if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
netif_stop_queue(ndev);
- tx_obj_no = priv->tx_obj;
priv->tx_obj = PCH_TX_OBJ_START;
} else {
- tx_obj_no = priv->tx_obj;
priv->tx_obj++;
}
@@ -932,9 +928,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
id2 |= PCH_ID_MSGVAL;
/* If remote frame has to be transmitted.. */
- if (cf->can_id & CAN_RTR_FLAG)
- id2 &= ~PCH_ID2_DIR;
- else
+ if (!(cf->can_id & CAN_RTR_FLAG))
id2 |= PCH_ID2_DIR;
iowrite32(id2, &priv->regs->ifregs[1].id2);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 19/20] can: EG20T PCH: Add setting TEC/REC statistics processing
From: Tomoya MORINAGA @ 2010-11-30 4:40 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Add setting TEC/REC statistics processing.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index e11ec36..596dc1e 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -574,6 +574,9 @@ static void pch_can_error(struct net_device *ndev, u32 status)
break;
}
+ cf->data[6] = errc & PCH_TEC;
+ cf->data[7] = (errc & PCH_REC) >> 8;
+
priv->can.state = state;
netif_rx(skb);
--
1.6.0.6
^ permalink raw reply related
* [PATCH net-next-2.6 v6 20/20] can: EG20T PCH: Replace netif_rx to netif_receive_skb
From: Tomoya MORINAGA @ 2010-11-30 4:41 UTC (permalink / raw)
To: Wolfgang Grandegger, Wolfram Sang, Christian Pellegrin,
Barry Song, Samuel Ortiz
Cc: qi.wang, yong.y.wang, andrew.chih.howe.khor, joel.clark,
kok.howg.ewe, margie.foster
Since this driver is implemented as NAPI,
netif_receive_skb must be used not netif_rx.
Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
---
drivers/net/can/pch_can.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 596dc1e..0ee3fc6 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -578,7 +578,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
cf->data[7] = (errc & PCH_REC) >> 8;
priv->can.state = state;
- netif_rx(skb);
+ netif_receive_skb(skb);
stats->rx_packets++;
stats->rx_bytes += cf->can_dlc;
--
1.6.0.6
^ permalink raw reply related
* Re: [PATCH 1/3] inetpeer: Support ipv6 addresses.
From: Changli Gao @ 2010-11-30 4:51 UTC (permalink / raw)
To: David Miller; +Cc: netdev
In-Reply-To: <20101129.191457.193722052.davem@davemloft.net>
On Tue, Nov 30, 2010 at 11:14 AM, David Miller <davem@davemloft.net> wrote:
> From: Changli Gao <xiaosuo@gmail.com>
> Date: Tue, 30 Nov 2010 10:33:49 +0800
>
>> I have thought about converting this AVL tree to rbtree. When I saw
>> the comment above, I gave it up, because rbtree makes this structure
>> bigger. If ipv6 support is added, I think it is time to turn to
>> rbtree. :)
>
> If it takes size over 128 bytes, it is probably still a bad idea.
> Right now it is just under 128.
>
Why 128? The current size of inet_peer is 64 bytes, and after your
ipv6 patch, it is just 80. And, inet_peer is allocated from its own
mem_cache, so the size of the memory for it should not be aligned to
2^n.
If rbtree is used instead, extra 8 bytes will be needed, and the size
of inet_peer will be 88.
--
Regards,
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* Re: [PATCH 1/3] inetpeer: Support ipv6 addresses.
From: David Miller @ 2010-11-30 5:22 UTC (permalink / raw)
To: xiaosuo; +Cc: netdev
In-Reply-To: <AANLkTin11AYaFWMArC6fNQnvej2+=WUfOtTVrtX8WLEZ@mail.gmail.com>
From: Changli Gao <xiaosuo@gmail.com>
Date: Tue, 30 Nov 2010 12:51:08 +0800
> On Tue, Nov 30, 2010 at 11:14 AM, David Miller <davem@davemloft.net> wrote:
>> From: Changli Gao <xiaosuo@gmail.com>
>> Date: Tue, 30 Nov 2010 10:33:49 +0800
>>
>>> I have thought about converting this AVL tree to rbtree. When I saw
>>> the comment above, I gave it up, because rbtree makes this structure
>>> bigger. If ipv6 support is added, I think it is time to turn to
>>> rbtree. :)
>>
>> If it takes size over 128 bytes, it is probably still a bad idea.
>> Right now it is just under 128.
>>
>
> Why 128? The current size of inet_peer is 64 bytes, and after your
> ipv6 patch, it is just 80. And, inet_peer is allocated from its own
> mem_cache, so the size of the memory for it should not be aligned to
> 2^n.
Sorry, I was taking into the consideration other work I am doing
which will move all of the routing metrics into inet_peer as well.
With ipv6 address support, it fits perfectly into 128 bytes on
64-bit.
^ permalink raw reply
* Re: [PATCH 1/3] inetpeer: Support ipv6 addresses.
From: Eric Dumazet @ 2010-11-30 5:42 UTC (permalink / raw)
To: David Miller; +Cc: xiaosuo, netdev
In-Reply-To: <20101129.212222.115953137.davem@davemloft.net>
Le lundi 29 novembre 2010 à 21:22 -0800, David Miller a écrit :
> From: Changli Gao <xiaosuo@gmail.com>
> Date: Tue, 30 Nov 2010 12:51:08 +0800
>
> > On Tue, Nov 30, 2010 at 11:14 AM, David Miller <davem@davemloft.net> wrote:
> >> From: Changli Gao <xiaosuo@gmail.com>
> >> Date: Tue, 30 Nov 2010 10:33:49 +0800
> >>
> >>> I have thought about converting this AVL tree to rbtree. When I saw
> >>> the comment above, I gave it up, because rbtree makes this structure
> >>> bigger. If ipv6 support is added, I think it is time to turn to
> >>> rbtree. :)
> >>
> >> If it takes size over 128 bytes, it is probably still a bad idea.
> >> Right now it is just under 128.
> >>
> >
> > Why 128? The current size of inet_peer is 64 bytes, and after your
> > ipv6 patch, it is just 80. And, inet_peer is allocated from its own
> > mem_cache, so the size of the memory for it should not be aligned to
> > 2^n.
>
> Sorry, I was taking into the consideration other work I am doing
> which will move all of the routing metrics into inet_peer as well.
>
> With ipv6 address support, it fits perfectly into 128 bytes on
> 64-bit.
> --
Its a bit early in the morning here, I must confess I dont yet
understand your patch David :)
As we use a tree, why not using two different trees for ipv4 / ipv6 ?
I dont understand how computing a 32bit key (sort of hash key) is going
to help when hash collision happens, with an avl tree.
For Changli : AVL tree was OK for RCU conversion, I am not sure about
RBtree yet.
Either version of tree (AVL/rbtree) will be expensive to use if depth is
big (With 2 millions entries, depth is going to be very big). I
understand you want to get rid of route cache ?
^ permalink raw reply
* [PATCH] net/ipv6/sit.c: return unhandled skb to tunnel4_rcv
From: David McCullough @ 2010-11-30 5:32 UTC (permalink / raw)
To: netdev
Hi all,
I found a problem using an IPv6 over IPv4 tunnel. When CONFIG_IPV6_SIT
was enabled, the packets would be rejected as net/ipv6/sit.c was catching
all IPPROTO_IPV6 packets and returning an ICMP port unreachable error.
I think this patch fixes the problem cleanly. I believe the code in
net/ipv4/tunnel4.c:tunnel4_rcv takes care of it properly if none of the
handlers claim the skb.
Patch is against 2.6.35, bit still applies to current.
Cheers,
Davidm
Signed-off-by: David McCullough <david_mccullough@mcafee.com>
diff -u -r1.1.1.45 sit.c
--- a/net/ipv6/sit.c 12 Aug 2010 00:16:26 -0000 1.1.1.45
+++ b/net/ipv6/sit.c 30 Nov 2010 05:01:19 -0000
@@ -575,8 +575,9 @@
return 0;
}
- icmp_send(skb, ICMP_DEST_UNREACH, ICMP_PORT_UNREACH, 0);
+ /* no tunnel matched, let upstream know, ipsec may handle it */
rcu_read_unlock();
+ return 1;
out:
kfree_skb(skb);
return 0;
--
David McCullough, david_mccullough@mcafee.com, Ph:+61 734352815
McAfee - SnapGear http://www.mcafee.com http://www.uCdot.org
^ permalink raw reply
* Re: [PATCH 1/3] inetpeer: Support ipv6 addresses.
From: David Miller @ 2010-11-30 5:53 UTC (permalink / raw)
To: eric.dumazet; +Cc: xiaosuo, netdev
In-Reply-To: <1291095736.2725.5.camel@edumazet-laptop>
From: Eric Dumazet <eric.dumazet@gmail.com>
Date: Tue, 30 Nov 2010 06:42:16 +0100
> Its a bit early in the morning here, I must confess I dont yet
> understand your patch David :)
>
> As we use a tree, why not using two different trees for ipv4 / ipv6 ?
The "key" just creates a natural ordering in the tree, it's
almost arbitrary except that it must distribute well amongst
the entries.
I currently don't see any reason to make two trees right now.
> I dont understand how computing a 32bit key (sort of hash key) is going
> to help when hash collision happens, with an avl tree.
> Either version of tree (AVL/rbtree) will be expensive to use if depth is
> big (With 2 millions entries, depth is going to be very big). I
> understand you want to get rid of route cache ?
Do we plan to talk to 2 million unique destinations and have active
non-default metrics for each one of them very often?
inet_peer entries will only get created when we need to make
non-default metric settings for a specific destination address.
See that's the thing, it's scope is so much smaller than the existing
routing cache. It's only going to be used in limited if not
controlled cases.
^ permalink raw reply
* Re: [PATCH 1/3] inetpeer: Support ipv6 addresses.
From: Eric Dumazet @ 2010-11-30 6:11 UTC (permalink / raw)
To: David Miller; +Cc: xiaosuo, netdev
In-Reply-To: <20101129.215303.48488457.davem@davemloft.net>
Le lundi 29 novembre 2010 à 21:53 -0800, David Miller a écrit :
> From: Eric Dumazet <eric.dumazet@gmail.com>
> Date: Tue, 30 Nov 2010 06:42:16 +0100
>
> > Its a bit early in the morning here, I must confess I dont yet
> > understand your patch David :)
> >
> > As we use a tree, why not using two different trees for ipv4 / ipv6 ?
>
> The "key" just creates a natural ordering in the tree, it's
> almost arbitrary except that it must distribute well amongst
> the entries.
Hmm. AVL search must take a decision, take the left or the right path.
if current key is equal, which path do you take ?
@@ -165,9 +208,9 @@ static void unlink_from_unused(struct inet_peer *p)
> for (u = rcu_dereference_protected(peers.root, \
> lockdep_is_held(&peers.lock)); \
> u != peer_avl_empty; ) { \
> - if (_daddr == u->v4daddr) \
> + if (inet_peer_addr_equal(_daddr, &u->daddr)) \
> break; \
> - if ((__force __u32)_daddr < (__force __u32)u->v4daddr) \
> + if (key < inet_peer_key(&u->daddr)) \
> v = &u->avl_left; \
> else \
> v = &u->avl_right; \
Apparently you take the right one, you may miss the target if its on the
left path ?
>
> I currently don't see any reason to make two trees right now.
>
Cost of a tree is one pointer, and ipv4 search would be faster if we use
different search functions.
> > I dont understand how computing a 32bit key (sort of hash key) is going
> > to help when hash collision happens, with an avl tree.
> > Either version of tree (AVL/rbtree) will be expensive to use if depth is
> > big (With 2 millions entries, depth is going to be very big). I
> > understand you want to get rid of route cache ?
>
> Do we plan to talk to 2 million unique destinations and have active
> non-default metrics for each one of them very often?
>
> inet_peer entries will only get created when we need to make
> non-default metric settings for a specific destination address.
>
> See that's the thing, it's scope is so much smaller than the existing
> routing cache. It's only going to be used in limited if not
> controlled cases.
>
OK good :)
I have no idea how many addresses have non default metric settings.
Do you know how to make an estimation on a server ?
^ permalink raw reply
* Re: [PATCH] net/ipv6/sit.c: return unhandled skb to tunnel4_rcv
From: Eric Dumazet @ 2010-11-30 6:12 UTC (permalink / raw)
To: David McCullough; +Cc: netdev
In-Reply-To: <20101130053234.GA28609@mcafee.com>
Le mardi 30 novembre 2010 à 15:32 +1000, David McCullough a écrit :
> Hi all,
>
> I found a problem using an IPv6 over IPv4 tunnel. When CONFIG_IPV6_SIT
> was enabled, the packets would be rejected as net/ipv6/sit.c was catching
> all IPPROTO_IPV6 packets and returning an ICMP port unreachable error.
>
> I think this patch fixes the problem cleanly. I believe the code in
> net/ipv4/tunnel4.c:tunnel4_rcv takes care of it properly if none of the
> handlers claim the skb.
>
> Patch is against 2.6.35, bit still applies to current.
>
> Cheers,
> Davidm
>
> Signed-off-by: David McCullough <david_mccullough@mcafee.com>
>
> diff -u -r1.1.1.45 sit.c
> --- a/net/ipv6/sit.c 12 Aug 2010 00:16:26 -0000 1.1.1.45
> +++ b/net/ipv6/sit.c 30 Nov 2010 05:01:19 -0000
> @@ -575,8 +575,9 @@
> return 0;
> }
>
> - icmp_send(skb, ICMP_DEST_UNREACH, ICMP_PORT_UNREACH, 0);
> + /* no tunnel matched, let upstream know, ipsec may handle it */
> rcu_read_unlock();
> + return 1;
> out:
> kfree_skb(skb);
> return 0;
>
Good catch !
Acked-by: Eric Dumazet <eric.dumazet@gmail.com>
^ permalink raw reply
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