* [PATCH net-next 0/9] cnic: Bug fixes and FCoE support
From: Michael Chan @ 2010-12-23 17:42 UTC (permalink / raw)
To: davem; +Cc: netdev
David, bug fixes and FCoE enablement patches for net-next.
Please review. Thanks.
^ permalink raw reply
* [PATCH net-next 7/9] cnic: Call cm_connect_complete() immediately on error
From: Michael Chan @ 2010-12-23 17:43 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-7-git-send-email-mchan@broadcom.com>
From: Eddie Wai <waie@broadcom.com>
If we get a path_resp error from userspace, call cm_connect_complete()
immediately with error so that bnx2i can react to the error faster.
Signed-off-by: Eddie Wai <waie@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 16 ++++++++++++++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 1240dea..36c1578 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -322,6 +322,8 @@ static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
return 0;
}
+static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
+
static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
char *buf, u16 len)
{
@@ -351,7 +353,9 @@ static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
}
csk = &cp->csk_tbl[l5_cid];
csk_hold(csk);
- if (cnic_in_use(csk)) {
+ if (cnic_in_use(csk) &&
+ test_bit(SK_F_CONNECT_START, &csk->flags)) {
+
memcpy(csk->ha, path_resp->mac_addr, 6);
if (test_bit(SK_F_IPV6, &csk->flags))
memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
@@ -359,8 +363,16 @@ static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
else
memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
sizeof(struct in_addr));
- if (is_valid_ether_addr(csk->ha))
+
+ if (is_valid_ether_addr(csk->ha)) {
cnic_cm_set_pg(csk);
+ } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
+ !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
+
+ cnic_cm_upcall(cp, csk,
+ L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
+ clear_bit(SK_F_CONNECT_START, &csk->flags);
+ }
}
csk_put(csk);
rcu_read_unlock();
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 1/9] cnic: Fix iSCSI TCP port endian order.
From: Michael Chan @ 2010-12-23 17:42 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-1-git-send-email-mchan@broadcom.com>
Pass the TCP port parameter for iSCSI connections to the firmware in
proper endian order.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 23 +++++++++++++----------
drivers/net/cnic.h | 2 +-
2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 594ca9c..9c2e786 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -2883,7 +2883,7 @@ static void cnic_cm_cleanup(struct cnic_sock *csk)
struct cnic_dev *dev = csk->dev;
struct cnic_local *cp = dev->cnic_priv;
- cnic_free_id(&cp->csk_port_tbl, csk->src_port);
+ cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
csk->src_port = 0;
}
}
@@ -3014,7 +3014,8 @@ static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
int is_v6, rc = 0;
struct dst_entry *dst = NULL;
struct net_device *realdev;
- u32 local_port;
+ __be16 local_port;
+ u32 port_id;
if (saddr->local.v6.sin6_family == AF_INET6 &&
saddr->remote.v6.sin6_family == AF_INET6)
@@ -3054,19 +3055,21 @@ static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
}
}
- if (local_port >= CNIC_LOCAL_PORT_MIN &&
- local_port < CNIC_LOCAL_PORT_MAX) {
- if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
- local_port = 0;
+ port_id = be16_to_cpu(local_port);
+ if (port_id >= CNIC_LOCAL_PORT_MIN &&
+ port_id < CNIC_LOCAL_PORT_MAX) {
+ if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
+ port_id = 0;
} else
- local_port = 0;
+ port_id = 0;
- if (!local_port) {
- local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
- if (local_port == -1) {
+ if (!port_id) {
+ port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
+ if (port_id == -1) {
rc = -ENOMEM;
goto err_out;
}
+ local_port = cpu_to_be16(port_id);
}
csk->src_port = local_port;
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index 6a4a0ae..bf38e57 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -82,7 +82,7 @@ struct cnic_redirect_entry {
#define MAX_ISCSI_TBL_SZ 256
#define CNIC_LOCAL_PORT_MIN 60000
-#define CNIC_LOCAL_PORT_MAX 61000
+#define CNIC_LOCAL_PORT_MAX 61024
#define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
#define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe))
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 3/9] cnic: Improve ->iscsi_nl_msg_send()
From: Michael Chan @ 2010-12-23 17:42 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-3-git-send-email-mchan@broadcom.com>
1. Change first parameter from cnic_dev to ulp_handle which is the hba
pointer. All other similar upcalls are using hba pointer. The callee
can then directly reference the hba without conversion.
2. Change return value from void to int so that an error code can be
passed back. This allows the operation to be retried.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 21 ++++++++++++++++-----
drivers/net/cnic_if.h | 2 +-
drivers/scsi/bnx2i/bnx2i_hwi.c | 14 ++++++++------
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 3a7d3ce..9f80fb4 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -279,6 +279,7 @@ static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
u32 msg_type = ISCSI_KEVENT_IF_DOWN;
struct cnic_ulp_ops *ulp_ops;
struct cnic_uio_dev *udev = cp->udev;
+ int rc = 0, retry = 0;
if (!udev || udev->uio_dev == -1)
return -ENODEV;
@@ -303,11 +304,21 @@ static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
path_req.pmtu = csk->mtu;
}
- rcu_read_lock();
- ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
- if (ulp_ops)
- ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
- rcu_read_unlock();
+ while (retry < 3) {
+ rc = 0;
+ rcu_read_lock();
+ ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
+ if (ulp_ops)
+ rc = ulp_ops->iscsi_nl_send_msg(
+ cp->ulp_handle[CNIC_ULP_ISCSI],
+ msg_type, buf, len);
+ rcu_read_unlock();
+ if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
+ break;
+
+ msleep(100);
+ retry++;
+ }
return 0;
}
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h
index 0dbeaec..33333e7 100644
--- a/drivers/net/cnic_if.h
+++ b/drivers/net/cnic_if.h
@@ -301,7 +301,7 @@ struct cnic_ulp_ops {
void (*cm_abort_complete)(struct cnic_sock *);
void (*cm_remote_close)(struct cnic_sock *);
void (*cm_remote_abort)(struct cnic_sock *);
- void (*iscsi_nl_send_msg)(struct cnic_dev *dev, u32 msg_type,
+ int (*iscsi_nl_send_msg)(void *ulp_ctx, u32 msg_type,
char *data, u16 data_size);
struct module *owner;
atomic_t ref_count;
diff --git a/drivers/scsi/bnx2i/bnx2i_hwi.c b/drivers/scsi/bnx2i/bnx2i_hwi.c
index 8d9dbb3..2f9622e 100644
--- a/drivers/scsi/bnx2i/bnx2i_hwi.c
+++ b/drivers/scsi/bnx2i/bnx2i_hwi.c
@@ -2346,19 +2346,21 @@ static void bnx2i_cm_remote_abort(struct cnic_sock *cm_sk)
}
-static void bnx2i_send_nl_mesg(struct cnic_dev *dev, u32 msg_type,
+static int bnx2i_send_nl_mesg(void *context, u32 msg_type,
char *buf, u16 buflen)
{
- struct bnx2i_hba *hba;
+ struct bnx2i_hba *hba = context;
+ int rc;
- hba = bnx2i_find_hba_for_cnic(dev);
if (!hba)
- return;
+ return -ENODEV;
- if (iscsi_offload_mesg(hba->shost, &bnx2i_iscsi_transport,
- msg_type, buf, buflen))
+ rc = iscsi_offload_mesg(hba->shost, &bnx2i_iscsi_transport,
+ msg_type, buf, buflen);
+ if (rc)
printk(KERN_ALERT "bnx2i: private nl message send error\n");
+ return rc;
}
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 5/9] cnic: Support NIC Partition mode
From: Michael Chan @ 2010-12-23 17:43 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-6-git-send-email-mchan@broadcom.com>
Add a common function cnic_read_bnx2x_iscsi_mac() to read the iSCSI
MAC address at any specified shared memory location. In NIC Partition
mode, we need to get the MAC address from the MF_CFG area of shared
memory.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 84 ++++++++++++++++++++++++++++++++++++++++-----------
drivers/net/cnic.h | 3 ++
2 files changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 9bd133d..bf4a804 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -4247,10 +4247,36 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
cp->rx_cons = *cp->rx_cons_ptr;
}
+static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
+ u32 lower_addr)
+{
+ u32 val;
+ u8 mac[6];
+
+ val = CNIC_RD(dev, upper_addr);
+
+ mac[0] = (u8) (val >> 8);
+ mac[1] = (u8) val;
+
+ val = CNIC_RD(dev, lower_addr);
+
+ mac[2] = (u8) (val >> 24);
+ mac[3] = (u8) (val >> 16);
+ mac[4] = (u8) (val >> 8);
+ mac[5] = (u8) val;
+
+ if (is_valid_ether_addr(mac)) {
+ memcpy(dev->mac_addr, mac, 6);
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+}
+
static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
{
struct cnic_local *cp = dev->cnic_priv;
- u32 base, base2, addr, val;
+ u32 base, base2, addr, addr1, val;
int port = CNIC_PORT(cp);
dev->max_iscsi_conn = 0;
@@ -4263,20 +4289,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
addr = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_upper);
- val = CNIC_RD(dev, addr);
-
- dev->mac_addr[0] = (u8) (val >> 8);
- dev->mac_addr[1] = (u8) val;
-
- addr = BNX2X_SHMEM_ADDR(base,
+ addr1 = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_lower);
- val = CNIC_RD(dev, addr);
-
- dev->mac_addr[2] = (u8) (val >> 24);
- dev->mac_addr[3] = (u8) (val >> 16);
- dev->mac_addr[4] = (u8) (val >> 8);
- dev->mac_addr[5] = (u8) val;
+ cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
val = CNIC_RD(dev, addr);
@@ -4302,21 +4318,53 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
else
mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
- addr = mf_cfg_addr +
- offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ /* Must determine if the MF is SD vs SI mode */
+ addr = BNX2X_SHMEM_ADDR(base,
+ dev_info.shared_feature_config.config);
+ val = CNIC_RD(dev, addr);
+ if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
+ SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
+ int rc;
+
+ /* MULTI_FUNCTION_SI mode */
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].func_cfg);
+ val = CNIC_RD(dev, addr);
+ if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
+ dev->max_iscsi_conn = 0;
+
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].
+ iscsi_mac_addr_upper);
+ addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].
+ iscsi_mac_addr_lower);
+ rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
+ addr1);
+ if (rc && func > 1)
+ dev->max_iscsi_conn = 0;
+
+ return;
+ }
+ }
+
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_mf_config[func].e1hov_tag);
val = CNIC_RD(dev, addr);
val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
- addr = mf_cfg_addr +
- offsetof(struct mf_cfg,
- func_mf_config[func].config);
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_mf_config[func].config);
val = CNIC_RD(dev, addr);
val &= FUNC_MF_CFG_PROTOCOL_MASK;
if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
dev->max_iscsi_conn = 0;
}
}
+ if (!is_valid_ether_addr(dev->mac_addr))
+ dev->max_iscsi_conn = 0;
}
static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index 8e947b7..fb3b753 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -422,6 +422,9 @@ struct bnx2x_bd_chain_next {
(CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
offsetof(struct shmem2_region, field)))
+#define BNX2X_MF_CFG_ADDR(base, field) \
+ ((base) + offsetof(struct mf_cfg, field))
+
#define CNIC_PORT(cp) ((cp)->pfid & 1)
#define CNIC_FUNC(cp) ((cp)->func)
#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 4/9] cnic: Use proper client and connection IDs on iSCSI ring
From: Michael Chan @ 2010-12-23 17:42 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-4-git-send-email-mchan@broadcom.com>
Use the IDs specified by the bnx2x driver when initializing the ring.
We don't have to make code changes when these IDs change in the future.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 21 ++++++++++++---------
drivers/net/cnic.h | 5 -----
2 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 9f80fb4..9bd133d 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -4119,7 +4119,7 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
int port = CNIC_PORT(cp);
int i;
- int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+ u32 cli = cp->ethdev->iscsi_l2_client_id;
u32 val;
memset(txbd, 0, BCM_PAGE_SIZE);
@@ -4180,7 +4180,7 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
int i;
int port = CNIC_PORT(cp);
- int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+ u32 cli = cp->ethdev->iscsi_l2_client_id;
int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
u32 val;
dma_addr_t ring_map = udev->l2_ring_map;
@@ -4244,6 +4244,7 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
cp->rx_cons_ptr =
&sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
+ cp->rx_cons = *cp->rx_cons_ptr;
}
static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
@@ -4437,7 +4438,8 @@ static void cnic_init_rings(struct cnic_dev *dev)
cnic_init_bnx2_rx_ring(dev);
set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
} else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
- u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+ u32 cli = cp->ethdev->iscsi_l2_client_id;
+ u32 cid = cp->ethdev->iscsi_l2_cid;
u32 cl_qzone_id, type;
struct client_init_ramrod_data *data;
union l5cm_specific_data l5_data;
@@ -4478,7 +4480,7 @@ static void cnic_init_rings(struct cnic_dev *dev)
set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
- BNX2X_ISCSI_L2_CID, type, &l5_data);
+ cid, type, &l5_data);
i = 0;
while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
@@ -4489,7 +4491,7 @@ static void cnic_init_rings(struct cnic_dev *dev)
netdev_err(dev->netdev,
"iSCSI CLIENT_SETUP did not complete\n");
cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
- cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
+ cnic_ring_ctl(dev, cid, cli, 1);
}
}
@@ -4504,19 +4506,20 @@ static void cnic_shutdown_rings(struct cnic_dev *dev)
cnic_shutdown_bnx2_rx_ring(dev);
} else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
struct cnic_local *cp = dev->cnic_priv;
- u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+ u32 cli = cp->ethdev->iscsi_l2_client_id;
+ u32 cid = cp->ethdev->iscsi_l2_cid;
union l5cm_specific_data l5_data;
int i;
u32 type;
- cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
+ cnic_ring_ctl(dev, cid, cli, 0);
set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
l5_data.phy_address.lo = cli;
l5_data.phy_address.hi = 0;
cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
- BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
+ cid, ETH_CONNECTION_TYPE, &l5_data);
i = 0;
while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
++i < 10)
@@ -4533,7 +4536,7 @@ static void cnic_shutdown_rings(struct cnic_dev *dev)
type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
SPE_HDR_FUNCTION_ID);
cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
- BNX2X_ISCSI_L2_CID, type, &l5_data);
+ cid, type, &l5_data);
msleep(10);
}
clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index bf38e57..8e947b7 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -356,11 +356,6 @@ struct bnx2x_bd_chain_next {
#define BNX2X_CONTEXT_MEM_SIZE 1024
#define BNX2X_FCOE_CID 16
-/* iSCSI client IDs are 17, 19, 21, 23 */
-#define BNX2X_ISCSI_BASE_CL_ID 17
-#define BNX2X_ISCSI_CL_ID(vn) (BNX2X_ISCSI_BASE_CL_ID + ((vn) << 1))
-
-#define BNX2X_ISCSI_L2_CID 17
#define BNX2X_ISCSI_START_CID 18
#define BNX2X_ISCSI_NUM_CONNECTIONS 128
#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 2/9] cnic: Prevent "scheduling while atomic" when calling ->cnic_init()
From: Michael Chan @ 2010-12-23 17:42 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-2-git-send-email-mchan@broadcom.com>
cnic_dev_list is protected by rtnl_lock and cnic_dev_lock spin_lock during
modifications. When looping on cnic_dev_list and calling ->cnic_init(),
we should just hold rtnl_lock since ->cnic_init() may sleep.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 9c2e786..3a7d3ce 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -59,6 +59,7 @@ MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(CNIC_MODULE_VERSION);
+/* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
static LIST_HEAD(cnic_dev_list);
static LIST_HEAD(cnic_udev_list);
static DEFINE_RWLOCK(cnic_dev_lock);
@@ -445,14 +446,12 @@ int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
/* Prevent race conditions with netdev_event */
rtnl_lock();
- read_lock(&cnic_dev_lock);
list_for_each_entry(dev, &cnic_dev_list, list) {
struct cnic_local *cp = dev->cnic_priv;
if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
ulp_ops->cnic_init(dev);
}
- read_unlock(&cnic_dev_lock);
rtnl_unlock();
return 0;
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 5/9] cnic: Support NIC Partition mode
From: Michael Chan @ 2010-12-23 17:43 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-5-git-send-email-mchan@broadcom.com>
Add a common function cnic_read_bnx2x_iscsi_mac() to read the iSCSI
MAC address at any specified shared memory location. In NIC Partition
mode, we need to get the MAC address from the MF_CFG area of shared
memory.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 84 ++++++++++++++++++++++++++++++++++++++++-----------
drivers/net/cnic.h | 3 ++
2 files changed, 69 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 9bd133d..bf4a804 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -4247,10 +4247,36 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
cp->rx_cons = *cp->rx_cons_ptr;
}
+static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
+ u32 lower_addr)
+{
+ u32 val;
+ u8 mac[6];
+
+ val = CNIC_RD(dev, upper_addr);
+
+ mac[0] = (u8) (val >> 8);
+ mac[1] = (u8) val;
+
+ val = CNIC_RD(dev, lower_addr);
+
+ mac[2] = (u8) (val >> 24);
+ mac[3] = (u8) (val >> 16);
+ mac[4] = (u8) (val >> 8);
+ mac[5] = (u8) val;
+
+ if (is_valid_ether_addr(mac)) {
+ memcpy(dev->mac_addr, mac, 6);
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+}
+
static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
{
struct cnic_local *cp = dev->cnic_priv;
- u32 base, base2, addr, val;
+ u32 base, base2, addr, addr1, val;
int port = CNIC_PORT(cp);
dev->max_iscsi_conn = 0;
@@ -4263,20 +4289,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
addr = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_upper);
- val = CNIC_RD(dev, addr);
-
- dev->mac_addr[0] = (u8) (val >> 8);
- dev->mac_addr[1] = (u8) val;
-
- addr = BNX2X_SHMEM_ADDR(base,
+ addr1 = BNX2X_SHMEM_ADDR(base,
dev_info.port_hw_config[port].iscsi_mac_lower);
- val = CNIC_RD(dev, addr);
-
- dev->mac_addr[2] = (u8) (val >> 24);
- dev->mac_addr[3] = (u8) (val >> 16);
- dev->mac_addr[4] = (u8) (val >> 8);
- dev->mac_addr[5] = (u8) val;
+ cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
val = CNIC_RD(dev, addr);
@@ -4302,21 +4318,53 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
else
mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
- addr = mf_cfg_addr +
- offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ /* Must determine if the MF is SD vs SI mode */
+ addr = BNX2X_SHMEM_ADDR(base,
+ dev_info.shared_feature_config.config);
+ val = CNIC_RD(dev, addr);
+ if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
+ SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
+ int rc;
+
+ /* MULTI_FUNCTION_SI mode */
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].func_cfg);
+ val = CNIC_RD(dev, addr);
+ if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
+ dev->max_iscsi_conn = 0;
+
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].
+ iscsi_mac_addr_upper);
+ addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_ext_config[func].
+ iscsi_mac_addr_lower);
+ rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
+ addr1);
+ if (rc && func > 1)
+ dev->max_iscsi_conn = 0;
+
+ return;
+ }
+ }
+
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_mf_config[func].e1hov_tag);
val = CNIC_RD(dev, addr);
val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
- addr = mf_cfg_addr +
- offsetof(struct mf_cfg,
- func_mf_config[func].config);
+ addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+ func_mf_config[func].config);
val = CNIC_RD(dev, addr);
val &= FUNC_MF_CFG_PROTOCOL_MASK;
if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
dev->max_iscsi_conn = 0;
}
}
+ if (!is_valid_ether_addr(dev->mac_addr))
+ dev->max_iscsi_conn = 0;
}
static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index 8e947b7..fb3b753 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -422,6 +422,9 @@ struct bnx2x_bd_chain_next {
(CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
offsetof(struct shmem2_region, field)))
+#define BNX2X_MF_CFG_ADDR(base, field) \
+ ((base) + offsetof(struct mf_cfg, field))
+
#define CNIC_PORT(cp) ((cp)->pfid & 1)
#define CNIC_FUNC(cp) ((cp)->func)
#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 9/9] cnic: Add FCoE support on 57712
From: Michael Chan @ 2010-12-23 17:43 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-9-git-send-email-mchan@broadcom.com>
- Connection ID (cid) management
- Slow-path command and response support
- Update version to 2.2.11.
Reviewed-by: Bhanu Prakash Gollapudi <bprakash@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 466 +++++++++++-
drivers/net/cnic.h | 16 +-
drivers/net/cnic_defs.h | 2095 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/cnic_if.h | 22 +-
4 files changed, 2585 insertions(+), 14 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 6ce7398..4a9c628 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -850,6 +850,7 @@ static void cnic_free_resc(struct cnic_dev *dev)
kfree(cp->ctx_tbl);
cp->ctx_tbl = NULL;
+ cnic_free_id_tbl(&cp->fcoe_cid_tbl);
cnic_free_id_tbl(&cp->cid_tbl);
}
@@ -1137,12 +1138,22 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
cp->iro_arr = ethdev->iro_arr;
- cp->max_cid_space = MAX_ISCSI_TBL_SZ;
+ cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
cp->iscsi_start_cid = start_cid;
+ cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
+
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
+ cp->fcoe_init_cid = ethdev->fcoe_init_cid;
+ if (!cp->fcoe_init_cid)
+ cp->fcoe_init_cid = 0x10;
+ }
+
if (start_cid < BNX2X_ISCSI_START_CID) {
u32 delta = BNX2X_ISCSI_START_CID - start_cid;
cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
+ cp->fcoe_start_cid += delta;
cp->max_cid_space += delta;
}
@@ -1161,6 +1172,9 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
}
+ for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
+ cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
+
pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
PAGE_SIZE;
@@ -1454,8 +1468,11 @@ static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
cnic_free_dma(dev, &iscsi->hq_info);
cnic_free_dma(dev, &iscsi->r2tq_info);
cnic_free_dma(dev, &iscsi->task_array_info);
+ cnic_free_id(&cp->cid_tbl, ctx->cid);
+ } else {
+ cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
}
- cnic_free_id(&cp->cid_tbl, ctx->cid);
+
ctx->cid = 0;
}
@@ -1467,6 +1484,16 @@ static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
struct cnic_iscsi *iscsi = ctx->proto.iscsi;
+ if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
+ cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
+ if (cid == -1) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ ctx->cid = cid;
+ return 0;
+ }
+
cid = cnic_alloc_new_id(&cp->cid_tbl);
if (cid == -1) {
ret = -ENOMEM;
@@ -2107,8 +2134,307 @@ static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
return 0;
}
-static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
- u32 num_wqes)
+static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+ struct fcoe_kwqe_stat *req;
+ struct fcoe_stat_ramrod_params *fcoe_stat;
+ union l5cm_specific_data l5_data;
+ struct cnic_local *cp = dev->cnic_priv;
+ int ret;
+ u32 cid;
+
+ req = (struct fcoe_kwqe_stat *) kwqe;
+ cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+
+ fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
+ if (!fcoe_stat)
+ return -ENOMEM;
+
+ memset(fcoe_stat, 0, sizeof(*fcoe_stat));
+ memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
+
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
+ u32 num, int *work)
+{
+ int ret;
+ struct cnic_local *cp = dev->cnic_priv;
+ u32 cid;
+ struct fcoe_init_ramrod_params *fcoe_init;
+ struct fcoe_kwqe_init1 *req1;
+ struct fcoe_kwqe_init2 *req2;
+ struct fcoe_kwqe_init3 *req3;
+ union l5cm_specific_data l5_data;
+
+ if (num < 3) {
+ *work = num;
+ return -EINVAL;
+ }
+ req1 = (struct fcoe_kwqe_init1 *) wqes[0];
+ req2 = (struct fcoe_kwqe_init2 *) wqes[1];
+ req3 = (struct fcoe_kwqe_init3 *) wqes[2];
+ if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
+ *work = 1;
+ return -EINVAL;
+ }
+ if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
+ *work = 2;
+ return -EINVAL;
+ }
+
+ if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
+ netdev_err(dev->netdev, "fcoe_init size too big\n");
+ return -ENOMEM;
+ }
+ fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
+ if (!fcoe_init)
+ return -ENOMEM;
+
+ memset(fcoe_init, 0, sizeof(*fcoe_init));
+ memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
+ memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
+ memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
+ fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
+ fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
+ fcoe_init->eq_next_page_addr.lo =
+ cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
+ fcoe_init->eq_next_page_addr.hi =
+ (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
+
+ fcoe_init->sb_num = cp->status_blk_num;
+ fcoe_init->eq_prod = MAX_KCQ_IDX;
+ fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
+ cp->kcq2.sw_prod_idx = 0;
+
+ cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+ printk(KERN_ERR "bdbg: submitting INIT RAMROD \n");
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ *work = 3;
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
+ u32 num, int *work)
+{
+ int ret = 0;
+ u32 cid = -1, l5_cid;
+ struct cnic_local *cp = dev->cnic_priv;
+ struct fcoe_kwqe_conn_offload1 *req1;
+ struct fcoe_kwqe_conn_offload2 *req2;
+ struct fcoe_kwqe_conn_offload3 *req3;
+ struct fcoe_kwqe_conn_offload4 *req4;
+ struct fcoe_conn_offload_ramrod_params *fcoe_offload;
+ struct cnic_context *ctx;
+ struct fcoe_context *fctx;
+ struct regpair ctx_addr;
+ union l5cm_specific_data l5_data;
+ struct fcoe_kcqe kcqe;
+ struct kcqe *cqes[1];
+
+ if (num < 4) {
+ *work = num;
+ return -EINVAL;
+ }
+ req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
+ req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
+ req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
+ req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
+
+ *work = 4;
+
+ l5_cid = req1->fcoe_conn_id;
+ if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+ goto err_reply;
+
+ l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+ ctx = &cp->ctx_tbl[l5_cid];
+ if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
+ goto err_reply;
+
+ ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
+ if (ret) {
+ ret = 0;
+ goto err_reply;
+ }
+ cid = ctx->cid;
+
+ fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
+ if (fctx) {
+ u32 hw_cid = BNX2X_HW_CID(cp, cid);
+ u32 val;
+
+ val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
+ FCOE_CONNECTION_TYPE);
+ fctx->xstorm_ag_context.cdu_reserved = val;
+ val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
+ FCOE_CONNECTION_TYPE);
+ fctx->ustorm_ag_context.cdu_usage = val;
+ }
+ if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
+ netdev_err(dev->netdev, "fcoe_offload size too big\n");
+ goto err_reply;
+ }
+ fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+ if (!fcoe_offload)
+ goto err_reply;
+
+ memset(fcoe_offload, 0, sizeof(*fcoe_offload));
+ memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
+ memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
+ memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
+ memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
+
+ cid = BNX2X_HW_CID(cp, cid);
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ if (!ret)
+ set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
+
+ return ret;
+
+err_reply:
+ if (cid != -1)
+ cnic_free_bnx2x_conn_resc(dev, l5_cid);
+
+ memset(&kcqe, 0, sizeof(kcqe));
+ kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
+ kcqe.fcoe_conn_id = req1->fcoe_conn_id;
+ kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
+
+ cqes[0] = (struct kcqe *) &kcqe;
+ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+ struct fcoe_kwqe_conn_enable_disable *req;
+ struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
+ union l5cm_specific_data l5_data;
+ int ret;
+ u32 cid, l5_cid;
+ struct cnic_local *cp = dev->cnic_priv;
+
+ req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
+ cid = req->context_id;
+ l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
+
+ if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
+ netdev_err(dev->netdev, "fcoe_enable size too big\n");
+ return -ENOMEM;
+ }
+ fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+ if (!fcoe_enable)
+ return -ENOMEM;
+
+ memset(fcoe_enable, 0, sizeof(*fcoe_enable));
+ memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+ struct fcoe_kwqe_conn_enable_disable *req;
+ struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
+ union l5cm_specific_data l5_data;
+ int ret;
+ u32 cid, l5_cid;
+ struct cnic_local *cp = dev->cnic_priv;
+
+ req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
+ cid = req->context_id;
+ l5_cid = req->conn_id;
+ if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+ return -EINVAL;
+
+ l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+ if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
+ netdev_err(dev->netdev, "fcoe_disable size too big\n");
+ return -ENOMEM;
+ }
+ fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+ if (!fcoe_disable)
+ return -ENOMEM;
+
+ memset(fcoe_disable, 0, sizeof(*fcoe_disable));
+ memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+ struct fcoe_kwqe_conn_destroy *req;
+ union l5cm_specific_data l5_data;
+ int ret;
+ u32 cid, l5_cid;
+ struct cnic_local *cp = dev->cnic_priv;
+ struct cnic_context *ctx;
+ struct fcoe_kcqe kcqe;
+ struct kcqe *cqes[1];
+
+ req = (struct fcoe_kwqe_conn_destroy *) kwqe;
+ cid = req->context_id;
+ l5_cid = req->conn_id;
+ if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+ return -EINVAL;
+
+ l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+ ctx = &cp->ctx_tbl[l5_cid];
+
+ init_waitqueue_head(&ctx->waitq);
+ ctx->wait_cond = 0;
+
+ memset(&l5_data, 0, sizeof(l5_data));
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ if (ret == 0) {
+ wait_event(ctx->waitq, ctx->wait_cond);
+ set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
+ queue_delayed_work(cnic_wq, &cp->delete_task,
+ msecs_to_jiffies(2000));
+ }
+
+ memset(&kcqe, 0, sizeof(kcqe));
+ kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
+ kcqe.fcoe_conn_id = req->conn_id;
+ kcqe.fcoe_conn_context_id = cid;
+
+ cqes[0] = (struct kcqe *) &kcqe;
+ cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
+ return ret;
+}
+
+static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+ struct fcoe_kwqe_destroy *req;
+ union l5cm_specific_data l5_data;
+ struct cnic_local *cp = dev->cnic_priv;
+ int ret;
+ u32 cid;
+
+ req = (struct fcoe_kwqe_destroy *) kwqe;
+ cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+
+ memset(&l5_data, 0, sizeof(l5_data));
+ ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
+ FCOE_CONNECTION_TYPE, &l5_data);
+ return ret;
+}
+
+static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
+ struct kwqe *wqes[], u32 num_wqes)
{
int i, work, ret;
u32 opcode;
@@ -2172,6 +2498,98 @@ static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
return 0;
}
+static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
+ struct kwqe *wqes[], u32 num_wqes)
+{
+ struct cnic_local *cp = dev->cnic_priv;
+ int i, work, ret;
+ u32 opcode;
+ struct kwqe *kwqe;
+
+ if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
+ return -EAGAIN; /* bnx2 is down */
+
+ if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
+ return -EINVAL;
+
+ for (i = 0; i < num_wqes; ) {
+ kwqe = wqes[i];
+ opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
+ work = 1;
+
+ switch (opcode) {
+ case FCOE_KWQE_OPCODE_INIT1:
+ ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
+ num_wqes - i, &work);
+ break;
+ case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
+ ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
+ num_wqes - i, &work);
+ break;
+ case FCOE_KWQE_OPCODE_ENABLE_CONN:
+ ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
+ break;
+ case FCOE_KWQE_OPCODE_DISABLE_CONN:
+ ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
+ break;
+ case FCOE_KWQE_OPCODE_DESTROY_CONN:
+ ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
+ break;
+ case FCOE_KWQE_OPCODE_DESTROY:
+ ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
+ break;
+ case FCOE_KWQE_OPCODE_STAT:
+ ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
+ break;
+ default:
+ ret = 0;
+ netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
+ opcode);
+ break;
+ }
+ if (ret < 0)
+ netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
+ opcode);
+ i += work;
+ }
+ return 0;
+}
+
+static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
+ u32 num_wqes)
+{
+ int ret = -EINVAL;
+ u32 layer_code;
+
+ if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
+ return -EAGAIN; /* bnx2x is down */
+
+ if (!num_wqes)
+ return 0;
+
+ layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
+ switch (layer_code) {
+ case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
+ case KWQE_FLAGS_LAYER_MASK_L4:
+ case KWQE_FLAGS_LAYER_MASK_L2:
+ ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
+ break;
+
+ case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
+ ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
+ break;
+ }
+ return ret;
+}
+
+static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
+{
+ if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
+ return KCQE_FLAGS_LAYER_MASK_L4;
+
+ return opflag & KCQE_FLAGS_LAYER_MASK;
+}
+
static void service_kcqes(struct cnic_dev *dev, int num_cqes)
{
struct cnic_local *cp = dev->cnic_priv;
@@ -2183,7 +2601,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
struct cnic_ulp_ops *ulp_ops;
int ulp_type;
u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
- u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
+ u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
comp++;
@@ -2191,7 +2609,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
while (j < num_cqes) {
u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
- if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
+ if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
break;
if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
@@ -2203,6 +2621,8 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
ulp_type = CNIC_ULP_RDMA;
else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
ulp_type = CNIC_ULP_ISCSI;
+ else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
+ ulp_type = CNIC_ULP_FCOE;
else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
ulp_type = CNIC_ULP_L4;
else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
@@ -3249,6 +3669,18 @@ done:
csk_put(csk);
}
+static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
+{
+ struct cnic_local *cp = dev->cnic_priv;
+ struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
+ u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
+ struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
+
+ ctx->timestamp = jiffies;
+ ctx->wait_cond = 1;
+ wake_up(&ctx->waitq);
+}
+
static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
{
struct cnic_local *cp = dev->cnic_priv;
@@ -3257,6 +3689,10 @@ static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
u32 l5_cid;
struct cnic_sock *csk;
+ if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
+ cnic_process_fcoe_term_conn(dev, kcqe);
+ return;
+ }
if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
cnic_cm_process_offld_pg(dev, l4kcqe);
@@ -3893,7 +4329,7 @@ static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
memset(&l2kwqe, 0, sizeof(l2kwqe));
wqes[0] = &l2kwqe;
- l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
+ l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
(L2_KWQE_OPCODE_VALUE_FLUSH <<
KWQE_OPCODE_SHIFT) | 2;
dev->submit_kwqes(dev, wqes, 1);
@@ -4336,6 +4772,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
val16 ^= 0x1e1e;
dev->max_iscsi_conn = val16;
}
+
+ if (BNX2X_CHIP_IS_E2(cp->chip_id))
+ dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
+
if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
int func = CNIC_FUNC(cp);
u32 mf_cfg_addr;
@@ -4362,6 +4802,9 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
dev->max_iscsi_conn = 0;
+ if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
+ dev->max_fcoe_conn = 0;
+
addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
func_ext_config[func].
iscsi_mac_addr_upper);
@@ -4463,6 +4906,15 @@ static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
if (ret)
return -ENOMEM;
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
+ BNX2X_FCOE_NUM_CONNECTIONS,
+ cp->fcoe_start_cid);
+
+ if (ret)
+ return -ENOMEM;
+ }
+
cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
cnic_init_bnx2x_kcq(dev);
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index e46b4c1..b328f6c 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -291,6 +291,10 @@ struct cnic_local {
atomic_t iscsi_conn;
u32 iscsi_start_cid;
+ u32 fcoe_init_cid;
+ u32 fcoe_start_cid;
+ struct cnic_id_tbl fcoe_cid_tbl;
+
u32 max_cid_space;
/* per connection parameters */
@@ -368,6 +372,10 @@ struct bnx2x_bd_chain_next {
#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
+#define BNX2X_FCOE_NUM_CONNECTIONS 128
+
+#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
+
#define BNX2X_CHIP_NUM_57710 0x164e
#define BNX2X_CHIP_NUM_57711 0x164f
#define BNX2X_CHIP_NUM_57711E 0x1650
@@ -426,6 +434,10 @@ struct bnx2x_bd_chain_next {
#define BNX2X_MF_CFG_ADDR(base, field) \
((base) + offsetof(struct mf_cfg, field))
+#ifndef ETH_MAX_RX_CLIENTS_E2
+#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
+#endif
+
#define CNIC_PORT(cp) ((cp)->pfid & 1)
#define CNIC_FUNC(cp) ((cp)->func)
#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
@@ -438,7 +450,9 @@ struct bnx2x_bd_chain_next {
#define BNX2X_SW_CID(x) (x & 0x1ffff)
#define BNX2X_CL_QZONE_ID(cp, cli) \
- (cli + (CNIC_PORT(cp) * ETH_MAX_RX_CLIENTS_E1H))
+ (cli + (CNIC_PORT(cp) * (BNX2X_CHIP_IS_E2(cp->chip_id) ?\
+ ETH_MAX_RX_CLIENTS_E2 : \
+ ETH_MAX_RX_CLIENTS_E1H)))
#define TCP_TSTORM_OOO_DROP_AND_PROC_ACK (0<<4)
#endif
diff --git a/drivers/net/cnic_defs.h b/drivers/net/cnic_defs.h
index 328e8b2..fdbc004 100644
--- a/drivers/net/cnic_defs.h
+++ b/drivers/net/cnic_defs.h
@@ -35,6 +35,40 @@
#define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14)
#define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15)
+#define FCOE_KCQE_OPCODE_INIT_FUNC (0x10)
+#define FCOE_KCQE_OPCODE_DESTROY_FUNC (0x11)
+#define FCOE_KCQE_OPCODE_STAT_FUNC (0x12)
+#define FCOE_KCQE_OPCODE_OFFLOAD_CONN (0x15)
+#define FCOE_KCQE_OPCODE_ENABLE_CONN (0x16)
+#define FCOE_KCQE_OPCODE_DISABLE_CONN (0x17)
+#define FCOE_KCQE_OPCODE_DESTROY_CONN (0x18)
+#define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20)
+#define FCOE_KCQE_OPCODE_FCOE_ERROR (0x21)
+
+#define FCOE_RAMROD_CMD_ID_INIT (FCOE_KCQE_OPCODE_INIT_FUNC)
+#define FCOE_RAMROD_CMD_ID_DESTROY (FCOE_KCQE_OPCODE_DESTROY_FUNC)
+#define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
+#define FCOE_RAMROD_CMD_ID_ENABLE_CONN (FCOE_KCQE_OPCODE_ENABLE_CONN)
+#define FCOE_RAMROD_CMD_ID_DISABLE_CONN (FCOE_KCQE_OPCODE_DISABLE_CONN)
+#define FCOE_RAMROD_CMD_ID_DESTROY_CONN (FCOE_KCQE_OPCODE_DESTROY_CONN)
+#define FCOE_RAMROD_CMD_ID_STAT (FCOE_KCQE_OPCODE_STAT_FUNC)
+#define FCOE_RAMROD_CMD_ID_TERMINATE_CONN (0x81)
+
+#define FCOE_KWQE_OPCODE_INIT1 (0)
+#define FCOE_KWQE_OPCODE_INIT2 (1)
+#define FCOE_KWQE_OPCODE_INIT3 (2)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN1 (3)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN2 (4)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN3 (5)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN4 (6)
+#define FCOE_KWQE_OPCODE_ENABLE_CONN (7)
+#define FCOE_KWQE_OPCODE_DISABLE_CONN (8)
+#define FCOE_KWQE_OPCODE_DESTROY_CONN (9)
+#define FCOE_KWQE_OPCODE_DESTROY (10)
+#define FCOE_KWQE_OPCODE_STAT (11)
+
+#define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3)
+
/* KCQ (kernel completion queue) response op codes */
#define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53)
#define L4_KCQE_OPCODE_VALUE_RESET_COMP (54)
@@ -683,6 +717,1496 @@ struct cstorm_iscsi_ag_context {
};
/*
+ * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section
+ */
+struct ustorm_fcoe_params {
+#if defined(__BIG_ENDIAN)
+ u16 fcoe_conn_id;
+ u16 flags;
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
+#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
+#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
+#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
+#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
+#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
+#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
+#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
+#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
+#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
+#elif defined(__LITTLE_ENDIAN)
+ u16 flags;
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
+#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
+#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
+#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
+#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
+#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
+#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
+#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
+#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
+#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
+ u16 fcoe_conn_id;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 hc_csdm_byte_en;
+ u8 func_id;
+ u8 port_id;
+ u8 vnic_id;
+#elif defined(__LITTLE_ENDIAN)
+ u8 vnic_id;
+ u8 port_id;
+ u8 func_id;
+ u8 hc_csdm_byte_en;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 rx_total_conc_seqs;
+ u16 rx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rx_max_fc_pay_len;
+ u16 rx_total_conc_seqs;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 ox_id;
+ u16 rx_max_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rx_max_conc_seqs;
+ u16 ox_id;
+#endif
+};
+
+/*
+ * FCoE 16-bits index structure
+ */
+struct fcoe_idx16_fields {
+ u16 fields;
+#define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
+#define FCOE_IDX16_FIELDS_IDX_SHIFT 0
+#define FCOE_IDX16_FIELDS_MSB (0x1<<15)
+#define FCOE_IDX16_FIELDS_MSB_SHIFT 15
+};
+
+/*
+ * FCoE 16-bits index union
+ */
+union fcoe_idx16_field_union {
+ struct fcoe_idx16_fields fields;
+ u16 val;
+};
+
+/*
+ * 4 regs size
+ */
+struct fcoe_bd_ctx {
+ u32 buf_addr_hi;
+ u32 buf_addr_lo;
+#if defined(__BIG_ENDIAN)
+ u16 rsrv0;
+ u16 buf_len;
+#elif defined(__LITTLE_ENDIAN)
+ u16 buf_len;
+ u16 rsrv0;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 rsrv1;
+ u16 flags;
+#elif defined(__LITTLE_ENDIAN)
+ u16 flags;
+ u16 rsrv1;
+#endif
+};
+
+/*
+ * Parameters required for placement according to SGL
+ */
+struct ustorm_fcoe_data_place {
+#if defined(__BIG_ENDIAN)
+ u16 cached_sge_off;
+ u8 cached_num_sges;
+ u8 cached_sge_idx;
+#elif defined(__LITTLE_ENDIAN)
+ u8 cached_sge_idx;
+ u8 cached_num_sges;
+ u16 cached_sge_off;
+#endif
+ struct fcoe_bd_ctx cached_sge[3];
+};
+
+struct fcoe_task_ctx_entry_txwr_rxrd {
+#if defined(__BIG_ENDIAN)
+ u16 verify_tx_seq;
+ u8 init_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
+ u8 tx_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
+#elif defined(__LITTLE_ENDIAN)
+ u8 tx_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
+ u8 init_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
+ u16 verify_tx_seq;
+#endif
+};
+
+struct fcoe_fcp_cmd_payload {
+ u32 opaque[8];
+};
+
+struct fcoe_fc_hdr {
+#if defined(__BIG_ENDIAN)
+ u8 cs_ctl;
+ u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 s_id[3];
+ u8 cs_ctl;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 r_ctl;
+ u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 d_id[3];
+ u8 r_ctl;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 seq_id;
+ u8 df_ctl;
+ u16 seq_cnt;
+#elif defined(__LITTLE_ENDIAN)
+ u16 seq_cnt;
+ u8 df_ctl;
+ u8 seq_id;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 type;
+ u8 f_ctl[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 f_ctl[3];
+ u8 type;
+#endif
+ u32 parameters;
+#if defined(__BIG_ENDIAN)
+ u16 ox_id;
+ u16 rx_id;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rx_id;
+ u16 ox_id;
+#endif
+};
+
+struct fcoe_fc_frame {
+ struct fcoe_fc_hdr fc_hdr;
+ u32 reserved0[2];
+};
+
+union fcoe_cmd_flow_info {
+ struct fcoe_fcp_cmd_payload fcp_cmd_payload;
+ struct fcoe_fc_frame mp_fc_frame;
+};
+
+struct fcoe_read_flow_info {
+ struct fcoe_fc_hdr fc_data_in_hdr;
+ u32 reserved[2];
+};
+
+struct fcoe_fcp_xfr_rdy_payload {
+ u32 burst_len;
+ u32 data_ro;
+};
+
+struct fcoe_write_flow_info {
+ struct fcoe_fc_hdr fc_data_out_hdr;
+ struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload;
+};
+
+struct fcoe_fcp_rsp_flags {
+ u8 flags;
+#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
+#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
+#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
+#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
+#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
+#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
+#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
+#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
+};
+
+struct fcoe_fcp_rsp_payload {
+ struct regpair reserved0;
+ u32 fcp_resid;
+#if defined(__BIG_ENDIAN)
+ u16 retry_delay_timer;
+ struct fcoe_fcp_rsp_flags fcp_flags;
+ u8 scsi_status_code;
+#elif defined(__LITTLE_ENDIAN)
+ u8 scsi_status_code;
+ struct fcoe_fcp_rsp_flags fcp_flags;
+ u16 retry_delay_timer;
+#endif
+ u32 fcp_rsp_len;
+ u32 fcp_sns_len;
+};
+
+/*
+ * Fixed size structure in order to plant it in Union structure
+ */
+struct fcoe_fcp_rsp_union {
+ struct fcoe_fcp_rsp_payload payload;
+ struct regpair reserved0;
+};
+
+/*
+ * Fixed size structure in order to plant it in Union structure
+ */
+struct fcoe_abts_rsp_union {
+ u32 r_ctl;
+ u32 abts_rsp_payload[7];
+};
+
+union fcoe_rsp_flow_info {
+ struct fcoe_fcp_rsp_union fcp_rsp;
+ struct fcoe_abts_rsp_union abts_rsp;
+};
+
+struct fcoe_cleanup_flow_info {
+#if defined(__BIG_ENDIAN)
+ u16 reserved1;
+ u16 task_id;
+#elif defined(__LITTLE_ENDIAN)
+ u16 task_id;
+ u16 reserved1;
+#endif
+ u32 reserved2[7];
+};
+
+/*
+ * 32 bytes used for general purposes
+ */
+union fcoe_general_task_ctx {
+ union fcoe_cmd_flow_info cmd_info;
+ struct fcoe_read_flow_info read_info;
+ struct fcoe_write_flow_info write_info;
+ union fcoe_rsp_flow_info rsp_info;
+ struct fcoe_cleanup_flow_info cleanup_info;
+ u32 comp_info[8];
+};
+
+struct fcoe_s_stat_ctx {
+ u8 flags;
+#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
+#define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
+#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
+#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
+#define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
+#define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
+#define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
+#define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
+#define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
+#define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
+#define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
+#define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
+#define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
+#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
+};
+
+/*
+ * Common section. Both TX and RX processing might write and read from it in different flows
+ */
+struct fcoe_task_ctx_entry_tx_rx_cmn {
+ u32 data_2_trns;
+ union fcoe_general_task_ctx general;
+#if defined(__BIG_ENDIAN)
+ u16 tx_low_seq_cnt;
+ struct fcoe_s_stat_ctx tx_s_stat;
+ u8 tx_seq_id;
+#elif defined(__LITTLE_ENDIAN)
+ u8 tx_seq_id;
+ struct fcoe_s_stat_ctx tx_s_stat;
+ u16 tx_low_seq_cnt;
+#endif
+ u32 common_flags;
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
+};
+
+struct fcoe_task_ctx_entry_rxwr_txrd {
+#if defined(__BIG_ENDIAN)
+ u16 rx_id;
+ u16 rx_flags;
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
+#elif defined(__LITTLE_ENDIAN)
+ u16 rx_flags;
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
+ u16 rx_id;
+#endif
+};
+
+struct fcoe_seq_ctx {
+#if defined(__BIG_ENDIAN)
+ u16 low_seq_cnt;
+ struct fcoe_s_stat_ctx s_stat;
+ u8 seq_id;
+#elif defined(__LITTLE_ENDIAN)
+ u8 seq_id;
+ struct fcoe_s_stat_ctx s_stat;
+ u16 low_seq_cnt;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 err_seq_cnt;
+ u16 high_seq_cnt;
+#elif defined(__LITTLE_ENDIAN)
+ u16 high_seq_cnt;
+ u16 err_seq_cnt;
+#endif
+ u32 low_exp_ro;
+ u32 high_exp_ro;
+};
+
+struct fcoe_single_sge_ctx {
+ struct regpair cur_buf_addr;
+#if defined(__BIG_ENDIAN)
+ u16 reserved0;
+ u16 cur_buf_rem;
+#elif defined(__LITTLE_ENDIAN)
+ u16 cur_buf_rem;
+ u16 reserved0;
+#endif
+};
+
+struct fcoe_mul_sges_ctx {
+ struct regpair cur_sge_addr;
+#if defined(__BIG_ENDIAN)
+ u8 sgl_size;
+ u8 cur_sge_idx;
+ u16 cur_sge_off;
+#elif defined(__LITTLE_ENDIAN)
+ u16 cur_sge_off;
+ u8 cur_sge_idx;
+ u8 sgl_size;
+#endif
+};
+
+union fcoe_sgl_ctx {
+ struct fcoe_single_sge_ctx single_sge;
+ struct fcoe_mul_sges_ctx mul_sges;
+};
+
+struct fcoe_task_ctx_entry_rx_only {
+ struct fcoe_seq_ctx seq_ctx;
+ struct fcoe_seq_ctx ooo_seq_ctx;
+ u32 rsrv3;
+ union fcoe_sgl_ctx sgl_ctx;
+};
+
+struct ustorm_fcoe_task_ctx_entry_rd {
+ struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+ struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+ struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+ struct fcoe_task_ctx_entry_rx_only rx_wr;
+ u32 reserved;
+};
+
+/*
+ * Ustorm FCoE Storm Context
+ */
+struct ustorm_fcoe_st_context {
+ struct ustorm_fcoe_params fcoe_params;
+ struct regpair task_addr;
+ struct regpair cq_base_addr;
+ struct regpair rq_pbl_base;
+ struct regpair rq_cur_page_addr;
+ struct regpair confq_pbl_base_addr;
+ struct regpair conn_db_base;
+ struct regpair xfrq_base_addr;
+ struct regpair lcq_base_addr;
+#if defined(__BIG_ENDIAN)
+ union fcoe_idx16_field_union rq_cons;
+ union fcoe_idx16_field_union rq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ union fcoe_idx16_field_union rq_prod;
+ union fcoe_idx16_field_union rq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 xfrq_prod;
+ u16 cq_cons;
+#elif defined(__LITTLE_ENDIAN)
+ u16 cq_cons;
+ u16 xfrq_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 lcq_cons;
+ u16 hc_cram_address;
+#elif defined(__LITTLE_ENDIAN)
+ u16 hc_cram_address;
+ u16 lcq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 sq_xfrq_lcq_confq_size;
+ u16 confq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 confq_prod;
+ u16 sq_xfrq_lcq_confq_size;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 hc_csdm_agg_int;
+ u8 flags;
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
+#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
+#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
+ u8 available_rqes;
+ u8 sp_q_flush_cnt;
+#elif defined(__LITTLE_ENDIAN)
+ u8 sp_q_flush_cnt;
+ u8 available_rqes;
+ u8 flags;
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
+#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
+#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
+ u8 hc_csdm_agg_int;
+#endif
+ struct ustorm_fcoe_data_place data_place;
+ struct ustorm_fcoe_task_ctx_entry_rd tce;
+};
+
+/*
+ * The FCoE non-aggregative context of Tstorm
+ */
+struct tstorm_fcoe_st_context {
+ struct regpair reserved0;
+ struct regpair reserved1;
+};
+
+/*
+ * The fcoe aggregative context section of Xstorm
+ */
+struct xstorm_fcoe_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+ u8 tcp_agg_vars1;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
+ u8 __reserved_da_cnt;
+ u16 __mtu;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __mtu;
+ u8 __reserved_da_cnt;
+ u8 tcp_agg_vars1;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
+#endif
+ u32 __task_addr_lo;
+ u32 __task_addr_hi;
+ u32 __reserved55;
+ u32 __tx_prods;
+#if defined(__BIG_ENDIAN)
+ u8 __agg_val8_th;
+ u8 __agg_val8;
+ u16 tcp_agg_vars2;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
+#elif defined(__LITTLE_ENDIAN)
+ u16 tcp_agg_vars2;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
+ u8 __agg_val8;
+ u8 __agg_val8_th;
+#endif
+ u32 __sq_base_addr_lo;
+ u32 __sq_base_addr_hi;
+ u32 __xfrq_base_addr_lo;
+ u32 __xfrq_base_addr_hi;
+#if defined(__BIG_ENDIAN)
+ u16 __xfrq_cons;
+ u16 __xfrq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __xfrq_prod;
+ u16 __xfrq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 __tcp_agg_vars5;
+ u8 __tcp_agg_vars4;
+ u8 __tcp_agg_vars3;
+ u8 __reserved_force_pure_ack_cnt;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __reserved_force_pure_ack_cnt;
+ u8 __tcp_agg_vars3;
+ u8 __tcp_agg_vars4;
+ u8 __tcp_agg_vars5;
+#endif
+ u32 __tcp_agg_vars6;
+#if defined(__BIG_ENDIAN)
+ u16 __agg_misc6;
+ u16 __tcp_agg_vars7;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __tcp_agg_vars7;
+ u16 __agg_misc6;
+#endif
+ u32 __agg_val10;
+ u32 __agg_val10_th;
+#if defined(__BIG_ENDIAN)
+ u16 __reserved3;
+ u8 __reserved2;
+ u8 __da_only_cnt;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __da_only_cnt;
+ u8 __reserved2;
+ u16 __reserved3;
+#endif
+};
+
+/*
+ * The fcoe aggregative context of Xstorm
+ */
+struct xstorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+ u16 agg_val1;
+ u8 agg_vars1;
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
+ u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __state;
+ u8 agg_vars1;
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
+ u16 agg_val1;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 cdu_reserved;
+ u8 __agg_vars4;
+ u8 agg_vars3;
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
+ u8 agg_vars2;
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+ u8 agg_vars2;
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+ u8 agg_vars3;
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
+ u8 __agg_vars4;
+ u8 cdu_reserved;
+#endif
+ u32 more_to_send;
+#if defined(__BIG_ENDIAN)
+ u16 agg_vars5;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
+ u16 sq_cons;
+#elif defined(__LITTLE_ENDIAN)
+ u16 sq_cons;
+ u16 agg_vars5;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
+#endif
+ struct xstorm_fcoe_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+ u16 agg_vars7;
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
+ u8 agg_val3_th;
+ u8 agg_vars6;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
+#elif defined(__LITTLE_ENDIAN)
+ u8 agg_vars6;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
+ u8 agg_val3_th;
+ u16 agg_vars7;
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __agg_val11_th;
+ u16 __agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __agg_val11;
+ u16 __agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 __reserved1;
+ u8 __agg_val6_th;
+ u16 __confq_tx_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __confq_tx_prod;
+ u8 __agg_val6_th;
+ u8 __reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 confq_cons;
+ u16 confq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 confq_prod;
+ u16 confq_cons;
+#endif
+ u32 agg_vars8;
+#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX (0xFFFFFF<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
+#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
+#if defined(__BIG_ENDIAN)
+ u16 ox_id;
+ u16 sq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 sq_prod;
+ u16 ox_id;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 agg_val3;
+ u8 agg_val6;
+ u8 agg_val5_th;
+ u8 agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+ u8 agg_val5;
+ u8 agg_val5_th;
+ u8 agg_val6;
+ u8 agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __pbf_tx_seq_ack;
+ u16 agg_limit1;
+#elif defined(__LITTLE_ENDIAN)
+ u16 agg_limit1;
+ u16 __pbf_tx_seq_ack;
+#endif
+ u32 completion_seq;
+ u32 confq_pbl_base_lo;
+ u32 confq_pbl_base_hi;
+};
+
+/*
+ * The fcoe extra aggregative context section of Tstorm
+ */
+struct tstorm_fcoe_extra_ag_context_section {
+ u32 __agg_val1;
+#if defined(__BIG_ENDIAN)
+ u8 __tcp_agg_vars2;
+ u8 __agg_val3;
+ u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+ u16 __agg_val2;
+ u8 __agg_val3;
+ u8 __tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __agg_val5;
+ u8 __agg_val6;
+ u8 __tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+ u8 __tcp_agg_vars3;
+ u8 __agg_val6;
+ u16 __agg_val5;
+#endif
+ u32 __lcq_prod;
+ u32 rtt_seq;
+ u32 rtt_time;
+ u32 __reserved66;
+ u32 wnd_right_edge;
+ u32 tcp_agg_vars1;
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
+ u32 snd_max;
+ u32 __lcq_cons;
+ u32 __reserved2;
+};
+
+/*
+ * The fcoe aggregative context of Tstorm
+ */
+struct tstorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+ u16 ulp_credit;
+ u8 agg_vars1;
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+ u8 state;
+#elif defined(__LITTLE_ENDIAN)
+ u8 state;
+ u8 agg_vars1;
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+ u16 ulp_credit;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __agg_val4;
+ u16 agg_vars2;
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
+#elif defined(__LITTLE_ENDIAN)
+ u16 agg_vars2;
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
+ u16 __agg_val4;
+#endif
+ struct tstorm_fcoe_extra_ag_context_section __extra_section;
+};
+
+/*
+ * The fcoe aggregative context of Ustorm
+ */
+struct ustorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+ u8 __aux_counter_flags;
+ u8 agg_vars2;
+#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
+ u8 agg_vars1;
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
+#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
+ u8 state;
+#elif defined(__LITTLE_ENDIAN)
+ u8 state;
+ u8 agg_vars1;
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
+#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
+ u8 agg_vars2;
+#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
+ u8 __aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 cdu_usage;
+ u8 agg_misc2;
+ u16 pbf_tx_seq_ack;
+#elif defined(__LITTLE_ENDIAN)
+ u16 pbf_tx_seq_ack;
+ u8 agg_misc2;
+ u8 cdu_usage;
+#endif
+ u32 agg_misc4;
+#if defined(__BIG_ENDIAN)
+ u8 agg_val3_th;
+ u8 agg_val3;
+ u16 agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+ u16 agg_misc3;
+ u8 agg_val3;
+ u8 agg_val3_th;
+#endif
+ u32 expired_task_id;
+ u32 agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+ u16 cq_prod;
+ u16 cq_cons;
+#elif defined(__LITTLE_ENDIAN)
+ u16 cq_cons;
+ u16 cq_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 __reserved2;
+ u8 decision_rules;
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
+ u8 decision_rule_enable_bits;
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+ u8 decision_rule_enable_bits;
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+ u8 decision_rules;
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
+ u16 __reserved2;
+#endif
+};
+
+/*
+ * Ethernet context section
+ */
+struct xstorm_fcoe_eth_context_section {
+#if defined(__BIG_ENDIAN)
+ u8 remote_addr_4;
+ u8 remote_addr_5;
+ u8 local_addr_0;
+ u8 local_addr_1;
+#elif defined(__LITTLE_ENDIAN)
+ u8 local_addr_1;
+ u8 local_addr_0;
+ u8 remote_addr_5;
+ u8 remote_addr_4;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 remote_addr_0;
+ u8 remote_addr_1;
+ u8 remote_addr_2;
+ u8 remote_addr_3;
+#elif defined(__LITTLE_ENDIAN)
+ u8 remote_addr_3;
+ u8 remote_addr_2;
+ u8 remote_addr_1;
+ u8 remote_addr_0;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 reserved_vlan_type;
+ u16 params;
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
+#elif defined(__LITTLE_ENDIAN)
+ u16 params;
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
+ u16 reserved_vlan_type;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 local_addr_2;
+ u8 local_addr_3;
+ u8 local_addr_4;
+ u8 local_addr_5;
+#elif defined(__LITTLE_ENDIAN)
+ u8 local_addr_5;
+ u8 local_addr_4;
+ u8 local_addr_3;
+ u8 local_addr_2;
+#endif
+};
+
+/*
+ * Flags used in FCoE context section - 1 byte
+ */
+struct xstorm_fcoe_context_flags {
+ u8 flags;
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED (0x1<<3)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED_SHIFT 3
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED (0x1<<7)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED_SHIFT 7
+};
+
+/*
+ * FCoE SQ element
+ */
+struct fcoe_sqe {
+ u16 wqe;
+#define FCOE_SQE_TASK_ID (0x7FFF<<0)
+#define FCOE_SQE_TASK_ID_SHIFT 0
+#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
+#define FCOE_SQE_TOGGLE_BIT_SHIFT 15
+};
+
+/*
+ * FCoE XFRQ element
+ */
+struct fcoe_xfrqe {
+ u16 wqe;
+#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
+#define FCOE_XFRQE_TASK_ID_SHIFT 0
+#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
+#define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
+};
+
+/*
+ * FCoE SQ\XFRQ element
+ */
+struct fcoe_cached_wqe {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_xfrqe xfrqe;
+ struct fcoe_sqe sqe;
+#elif defined(__LITTLE_ENDIAN)
+ struct fcoe_sqe sqe;
+ struct fcoe_xfrqe xfrqe;
+#endif
+};
+
+struct fcoe_task_ctx_entry_tx_only {
+ union fcoe_sgl_ctx sgl_ctx;
+};
+
+struct xstorm_fcoe_task_ctx_entry_rd {
+ struct fcoe_task_ctx_entry_tx_only tx_wr;
+ struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+ struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+ struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+};
+
+/*
+ * Cached SGEs
+ */
+struct common_fcoe_sgl {
+ struct fcoe_bd_ctx sge[2];
+};
+
+/*
+ * FCP_DATA parameters required for transmission
+ */
+struct xstorm_fcoe_fcp_data {
+ u32 io_rem;
+#if defined(__BIG_ENDIAN)
+ u16 cached_sge_off;
+ u8 cached_num_sges;
+ u8 cached_sge_idx;
+#elif defined(__LITTLE_ENDIAN)
+ u8 cached_sge_idx;
+ u8 cached_num_sges;
+ u16 cached_sge_off;
+#endif
+ struct common_fcoe_sgl cached_sgl;
+};
+
+/*
+ * FCoE context section
+ */
+struct xstorm_fcoe_context_section {
+#if defined(__BIG_ENDIAN)
+ u8 vlan_flag;
+ u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 s_id[3];
+ u8 vlan_flag;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 func_id;
+ u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 d_id[3];
+ u8 func_id;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 sq_xfrq_lcq_confq_size;
+ u16 tx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+ u16 tx_max_fc_pay_len;
+ u16 sq_xfrq_lcq_confq_size;
+#endif
+ u32 lcq_prod;
+#if defined(__BIG_ENDIAN)
+ u8 port_id;
+ u8 tx_max_conc_seqs_c3;
+ u8 seq_id;
+ struct xstorm_fcoe_context_flags tx_flags;
+#elif defined(__LITTLE_ENDIAN)
+ struct xstorm_fcoe_context_flags tx_flags;
+ u8 seq_id;
+ u8 tx_max_conc_seqs_c3;
+ u8 port_id;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 verify_tx_seq;
+ u8 func_mode;
+ u8 vnic_id;
+#elif defined(__LITTLE_ENDIAN)
+ u8 vnic_id;
+ u8 func_mode;
+ u16 verify_tx_seq;
+#endif
+ struct regpair confq_curr_page_addr;
+ struct fcoe_cached_wqe cached_wqe[8];
+ struct regpair lcq_base_addr;
+ struct xstorm_fcoe_task_ctx_entry_rd tce;
+ struct xstorm_fcoe_fcp_data fcp_data;
+#if defined(__BIG_ENDIAN)
+ u16 fcoe_tx_stat_params_ram_addr;
+ u16 cmng_port_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+ u16 cmng_port_ram_addr;
+ u16 fcoe_tx_stat_params_ram_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 fcp_cmd_pb_cmd_size;
+ u8 eth_hdr_size;
+ u16 pbf_addr;
+#elif defined(__LITTLE_ENDIAN)
+ u16 pbf_addr;
+ u8 eth_hdr_size;
+ u8 fcp_cmd_pb_cmd_size;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 reserved2[2];
+ u8 cos;
+ u8 dcb_version;
+#elif defined(__LITTLE_ENDIAN)
+ u8 dcb_version;
+ u8 cos;
+ u8 reserved2[2];
+#endif
+ u32 reserved3;
+ struct regpair reserved4[2];
+};
+
+/*
+ * Xstorm FCoE Storm Context
+ */
+struct xstorm_fcoe_st_context {
+ struct xstorm_fcoe_eth_context_section eth;
+ struct xstorm_fcoe_context_section fcoe;
+};
+
+/*
+ * Fcoe connection context
+ */
+struct fcoe_context {
+ struct ustorm_fcoe_st_context ustorm_st_context;
+ struct tstorm_fcoe_st_context tstorm_st_context;
+ struct xstorm_fcoe_ag_context xstorm_ag_context;
+ struct tstorm_fcoe_ag_context tstorm_ag_context;
+ struct ustorm_fcoe_ag_context ustorm_ag_context;
+ struct timers_block_context timers_context;
+ struct xstorm_fcoe_st_context xstorm_st_context;
+};
+
+/*
* iSCSI context region, used only in iSCSI
*/
struct ustorm_iscsi_rq_db {
@@ -2268,6 +3792,577 @@ struct iscsi_context {
};
/*
+ * FCoE KCQ CQE parameters
+ */
+union fcoe_kcqe_params {
+ u32 reserved0[4];
+};
+
+/*
+ * FCoE KCQ CQE
+ */
+struct fcoe_kcqe {
+ u32 fcoe_conn_id;
+ u32 completion_status;
+ u32 fcoe_conn_context_id;
+ union fcoe_kcqe_params params;
+#if defined(__BIG_ENDIAN)
+ u8 flags;
+#define FCOE_KCQE_RESERVED0 (0x7<<0)
+#define FCOE_KCQE_RESERVED0_SHIFT 0
+#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
+#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
+#define FCOE_KCQE_LAYER_CODE (0x7<<4)
+#define FCOE_KCQE_LAYER_CODE_SHIFT 4
+#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
+#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
+ u8 op_code;
+ u16 qe_self_seq;
+#elif defined(__LITTLE_ENDIAN)
+ u16 qe_self_seq;
+ u8 op_code;
+ u8 flags;
+#define FCOE_KCQE_RESERVED0 (0x7<<0)
+#define FCOE_KCQE_RESERVED0_SHIFT 0
+#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
+#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
+#define FCOE_KCQE_LAYER_CODE (0x7<<4)
+#define FCOE_KCQE_LAYER_CODE_SHIFT 4
+#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
+#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE KWQE header
+ */
+struct fcoe_kwqe_header {
+#if defined(__BIG_ENDIAN)
+ u8 flags;
+#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
+#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
+#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
+#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
+#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
+ u8 op_code;
+#elif defined(__LITTLE_ENDIAN)
+ u8 op_code;
+ u8 flags;
+#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
+#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
+#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
+#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
+#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE firmware init request 1
+ */
+struct fcoe_kwqe_init1 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 num_tasks;
+#elif defined(__LITTLE_ENDIAN)
+ u16 num_tasks;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 task_list_pbl_addr_lo;
+ u32 task_list_pbl_addr_hi;
+ u32 dummy_buffer_addr_lo;
+ u32 dummy_buffer_addr_hi;
+#if defined(__BIG_ENDIAN)
+ u16 rq_num_wqes;
+ u16 sq_num_wqes;
+#elif defined(__LITTLE_ENDIAN)
+ u16 sq_num_wqes;
+ u16 rq_num_wqes;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 cq_num_wqes;
+ u16 rq_buffer_log_size;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rq_buffer_log_size;
+ u16 cq_num_wqes;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 flags;
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
+#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
+ u8 num_sessions_log;
+ u16 mtu;
+#elif defined(__LITTLE_ENDIAN)
+ u16 mtu;
+ u8 num_sessions_log;
+ u8 flags;
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
+#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE firmware init request 2
+ */
+struct fcoe_kwqe_init2 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 hash_tbl_pbl_addr_lo;
+ u32 hash_tbl_pbl_addr_hi;
+ u32 t2_hash_tbl_addr_lo;
+ u32 t2_hash_tbl_addr_hi;
+ u32 t2_ptr_hash_tbl_addr_lo;
+ u32 t2_ptr_hash_tbl_addr_hi;
+ u32 free_list_count;
+};
+
+/*
+ * FCoE firmware init request 3
+ */
+struct fcoe_kwqe_init3 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 error_bit_map_lo;
+ u32 error_bit_map_hi;
+#if defined(__BIG_ENDIAN)
+ u8 reserved21[3];
+ u8 cached_session_enable;
+#elif defined(__LITTLE_ENDIAN)
+ u8 cached_session_enable;
+ u8 reserved21[3];
+#endif
+ u32 reserved2[4];
+};
+
+/*
+ * FCoE connection offload request 1
+ */
+struct fcoe_kwqe_conn_offload1 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 fcoe_conn_id;
+#elif defined(__LITTLE_ENDIAN)
+ u16 fcoe_conn_id;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 sq_addr_lo;
+ u32 sq_addr_hi;
+ u32 rq_pbl_addr_lo;
+ u32 rq_pbl_addr_hi;
+ u32 rq_first_pbe_addr_lo;
+ u32 rq_first_pbe_addr_hi;
+#if defined(__BIG_ENDIAN)
+ u16 reserved0;
+ u16 rq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rq_prod;
+ u16 reserved0;
+#endif
+};
+
+/*
+ * FCoE connection offload request 2
+ */
+struct fcoe_kwqe_conn_offload2 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 tx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+ u16 tx_max_fc_pay_len;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 cq_addr_lo;
+ u32 cq_addr_hi;
+ u32 xferq_addr_lo;
+ u32 xferq_addr_hi;
+ u32 conn_db_addr_lo;
+ u32 conn_db_addr_hi;
+ u32 reserved1;
+};
+
+/*
+ * FCoE connection offload request 3
+ */
+struct fcoe_kwqe_conn_offload3 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 vlan_tag;
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
+#elif defined(__LITTLE_ENDIAN)
+ u16 vlan_tag;
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
+ struct fcoe_kwqe_header hdr;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 tx_max_conc_seqs_c3;
+ u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 s_id[3];
+ u8 tx_max_conc_seqs_c3;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 flags;
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
+ u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 d_id[3];
+ u8 flags;
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
+#endif
+ u32 reserved;
+ u32 confq_first_pbe_addr_lo;
+ u32 confq_first_pbe_addr_hi;
+#if defined(__BIG_ENDIAN)
+ u16 rx_max_fc_pay_len;
+ u16 tx_total_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+ u16 tx_total_conc_seqs;
+ u16 rx_max_fc_pay_len;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 rx_open_seqs_exch_c3;
+ u8 rx_max_conc_seqs_c3;
+ u16 rx_total_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+ u16 rx_total_conc_seqs;
+ u8 rx_max_conc_seqs_c3;
+ u8 rx_open_seqs_exch_c3;
+#endif
+};
+
+/*
+ * FCoE connection offload request 4
+ */
+struct fcoe_kwqe_conn_offload4 {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u8 reserved2;
+ u8 e_d_tov_timer_val;
+#elif defined(__LITTLE_ENDIAN)
+ u8 e_d_tov_timer_val;
+ u8 reserved2;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u8 src_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+ u8 dst_mac_addr_hi16[2];
+ u8 src_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+ u8 src_mac_addr_hi16[2];
+ u8 dst_mac_addr_hi16[2];
+#endif
+ u8 dst_mac_addr_lo32[4];
+ u32 lcq_addr_lo;
+ u32 lcq_addr_hi;
+ u32 confq_pbl_base_addr_lo;
+ u32 confq_pbl_base_addr_hi;
+};
+
+/*
+ * FCoE connection enable request
+ */
+struct fcoe_kwqe_conn_enable_disable {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u8 src_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+ u16 vlan_tag;
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
+ u8 src_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+ u8 src_mac_addr_hi16[2];
+ u16 vlan_tag;
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
+#endif
+ u8 dst_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+ u16 reserved1;
+ u8 dst_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+ u8 dst_mac_addr_hi16[2];
+ u16 reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 vlan_flag;
+ u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 s_id[3];
+ u8 vlan_flag;
+#endif
+#if defined(__BIG_ENDIAN)
+ u8 reserved3;
+ u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+ u8 d_id[3];
+ u8 reserved3;
+#endif
+ u32 context_id;
+ u32 conn_id;
+ u32 reserved4;
+};
+
+/*
+ * FCoE connection destroy request
+ */
+struct fcoe_kwqe_conn_destroy {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 context_id;
+ u32 conn_id;
+ u32 reserved1[5];
+};
+
+/*
+ * FCoe destroy request
+ */
+struct fcoe_kwqe_destroy {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 reserved1[7];
+};
+
+/*
+ * FCoe statistics request
+ */
+struct fcoe_kwqe_stat {
+#if defined(__BIG_ENDIAN)
+ struct fcoe_kwqe_header hdr;
+ u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+ u16 reserved0;
+ struct fcoe_kwqe_header hdr;
+#endif
+ u32 stat_params_addr_lo;
+ u32 stat_params_addr_hi;
+ u32 reserved1[5];
+};
+
+/*
+ * FCoE KWQ WQE
+ */
+union fcoe_kwqe {
+ struct fcoe_kwqe_init1 init1;
+ struct fcoe_kwqe_init2 init2;
+ struct fcoe_kwqe_init3 init3;
+ struct fcoe_kwqe_conn_offload1 conn_offload1;
+ struct fcoe_kwqe_conn_offload2 conn_offload2;
+ struct fcoe_kwqe_conn_offload3 conn_offload3;
+ struct fcoe_kwqe_conn_offload4 conn_offload4;
+ struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
+ struct fcoe_kwqe_conn_destroy conn_destroy;
+ struct fcoe_kwqe_destroy destroy;
+ struct fcoe_kwqe_stat statistics;
+};
+
+struct fcoe_task_ctx_entry {
+ struct fcoe_task_ctx_entry_tx_only tx_wr_only;
+ struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+ struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+ struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+ struct fcoe_task_ctx_entry_rx_only rx_wr_only;
+ u32 reserved[4];
+};
+
+/*
+ * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod
+ */
+struct fcoe_conn_enable_disable_ramrod_params {
+ struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
+};
+
+
+/*
+ * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
+ */
+struct fcoe_conn_offload_ramrod_params {
+ struct fcoe_kwqe_conn_offload1 offload_kwqe1;
+ struct fcoe_kwqe_conn_offload2 offload_kwqe2;
+ struct fcoe_kwqe_conn_offload3 offload_kwqe3;
+ struct fcoe_kwqe_conn_offload4 offload_kwqe4;
+};
+
+/*
+ * FCoE init params passed by driver to FW in FCoE init ramrod
+ */
+struct fcoe_init_ramrod_params {
+ struct fcoe_kwqe_init1 init_kwqe1;
+ struct fcoe_kwqe_init2 init_kwqe2;
+ struct fcoe_kwqe_init3 init_kwqe3;
+ struct regpair eq_addr;
+ struct regpair eq_next_page_addr;
+#if defined(__BIG_ENDIAN)
+ u16 sb_num;
+ u16 eq_prod;
+#elif defined(__LITTLE_ENDIAN)
+ u16 eq_prod;
+ u16 sb_num;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 reserved1;
+ u8 reserved0;
+ u8 sb_id;
+#elif defined(__LITTLE_ENDIAN)
+ u8 sb_id;
+ u8 reserved0;
+ u16 reserved1;
+#endif
+};
+
+
+/*
+ * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod
+ */
+struct fcoe_stat_ramrod_params {
+ struct fcoe_kwqe_stat stat_kwqe;
+};
+
+
+/*
+ * FCoE 16-bits vlan structure
+ */
+struct fcoe_vlan_fields {
+ u16 fields;
+#define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
+#define FCOE_VLAN_FIELDS_VID_SHIFT 0
+#define FCOE_VLAN_FIELDS_CLI (0x1<<12)
+#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
+#define FCOE_VLAN_FIELDS_PRI (0x7<<13)
+#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
+};
+
+
+/*
+ * FCoE 16-bits vlan union
+ */
+union fcoe_vlan_field_union {
+ struct fcoe_vlan_fields fields;
+ u16 val;
+};
+
+/*
+ * Parameters used for Class 2 verifications
+ */
+struct ustorm_fcoe_c2_params {
+#if defined(__BIG_ENDIAN)
+ u16 e2e_credit;
+ u16 con_seq;
+#elif defined(__LITTLE_ENDIAN)
+ u16 con_seq;
+ u16 e2e_credit;
+#endif
+#if defined(__BIG_ENDIAN)
+ u16 ackq_prod;
+ u16 open_seq_per_exch;
+#elif defined(__LITTLE_ENDIAN)
+ u16 open_seq_per_exch;
+ u16 ackq_prod;
+#endif
+ struct regpair ackq_pbl_base;
+ struct regpair ackq_cur_seg;
+};
+
+/*
+ * Parameters used for Class 2 verifications
+ */
+struct xstorm_fcoe_c2_params {
+#if defined(__BIG_ENDIAN)
+ u16 reserved0;
+ u8 ackq_x_prod;
+ u8 max_conc_seqs_c2;
+#elif defined(__LITTLE_ENDIAN)
+ u8 max_conc_seqs_c2;
+ u8 ackq_x_prod;
+ u16 reserved0;
+#endif
+ struct regpair ackq_pbl_base;
+ struct regpair ackq_cur_seg;
+};
+
+/*
* Buffer per connection, used in Tstorm
*/
struct iscsi_conn_buf {
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h
index 33333e7..ccd8140 100644
--- a/drivers/net/cnic_if.h
+++ b/drivers/net/cnic_if.h
@@ -12,22 +12,31 @@
#ifndef CNIC_IF_H
#define CNIC_IF_H
-#define CNIC_MODULE_VERSION "2.2.6"
-#define CNIC_MODULE_RELDATE "Oct 12, 2010"
+#define CNIC_MODULE_VERSION "2.2.11"
+#define CNIC_MODULE_RELDATE "Dec 22, 2010"
#define CNIC_ULP_RDMA 0
#define CNIC_ULP_ISCSI 1
-#define CNIC_ULP_L4 2
-#define MAX_CNIC_ULP_TYPE_EXT 2
-#define MAX_CNIC_ULP_TYPE 3
+#define CNIC_ULP_FCOE 2
+#define CNIC_ULP_L4 3
+#define MAX_CNIC_ULP_TYPE_EXT 3
+#define MAX_CNIC_ULP_TYPE 4
struct kwqe {
u32 kwqe_op_flag;
+#define KWQE_QID_SHIFT 8
#define KWQE_OPCODE_MASK 0x00ff0000
#define KWQE_OPCODE_SHIFT 16
-#define KWQE_FLAGS_LAYER_SHIFT 28
#define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT)
+#define KWQE_LAYER_MASK 0x70000000
+#define KWQE_LAYER_SHIFT 28
+#define KWQE_FLAGS_LAYER_MASK_L2 (2<<28)
+#define KWQE_FLAGS_LAYER_MASK_L3 (3<<28)
+#define KWQE_FLAGS_LAYER_MASK_L4 (4<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28)
u32 kwqe_info0;
u32 kwqe_info1;
@@ -62,6 +71,7 @@ struct kcqe {
#define KCQE_FLAGS_LAYER_MASK_L4 (4<<28)
#define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28)
#define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28)
+ #define KCQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28)
#define KCQE_FLAGS_NEXT (1<<31)
#define KCQE_FLAGS_OPCODE_MASK (0xff<<16)
#define KCQE_FLAGS_OPCODE_SHIFT (16)
--
1.6.4.GIT
^ permalink raw reply related
* [PATCH net-next 8/9] cnic: Add kcq2 support on 57712
From: Michael Chan @ 2010-12-23 17:43 UTC (permalink / raw)
To: davem; +Cc: netdev
In-Reply-To: <1293126184-13097-8-git-send-email-mchan@broadcom.com>
The kcq2 (2nd kernel work queue) is used by FCoE on 57712 devices.
Signed-off-by: Michael Chan <mchan@broadcom.com>
---
drivers/net/cnic.c | 76 +++++++++++++++++++++++++++++++++++++--------------
drivers/net/cnic.h | 1 +
2 files changed, 56 insertions(+), 21 deletions(-)
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 36c1578..6ce7398 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -843,6 +843,7 @@ static void cnic_free_resc(struct cnic_dev *dev)
cnic_free_dma(dev, &cp->conn_buf_info);
cnic_free_dma(dev, &cp->kwq_info);
cnic_free_dma(dev, &cp->kwq_16_data_info);
+ cnic_free_dma(dev, &cp->kcq2.dma);
cnic_free_dma(dev, &cp->kcq1.dma);
kfree(cp->iscsi_tbl);
cp->iscsi_tbl = NULL;
@@ -1183,6 +1184,12 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
if (ret)
goto error;
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ ret = cnic_alloc_kcq(dev, &cp->kcq2);
+ if (ret)
+ goto error;
+ }
+
pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
@@ -2493,12 +2500,19 @@ static void cnic_service_bnx2x_bh(unsigned long data)
status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
- if (BNX2X_CHIP_IS_E2(cp->chip_id))
+
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
+
+ CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
+ MAX_KCQ_IDX);
+
cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
status_idx, IGU_INT_ENABLE, 1);
- else
+ } else {
cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
status_idx, IGU_INT_ENABLE, 1);
+ }
}
static int cnic_service_bnx2x(void *data, void *status_blk)
@@ -4381,6 +4395,44 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
dev->max_iscsi_conn = 0;
}
+static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
+{
+ struct cnic_local *cp = dev->cnic_priv;
+ u32 pfid = cp->pfid;
+
+ cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
+ CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
+ cp->kcq1.sw_prod_idx = 0;
+
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
+
+ cp->kcq1.hw_prod_idx_ptr =
+ &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+ cp->kcq1.status_idx_ptr =
+ &sb->sb.running_index[SM_RX_ID];
+ } else {
+ struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
+
+ cp->kcq1.hw_prod_idx_ptr =
+ &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+ cp->kcq1.status_idx_ptr =
+ &sb->sb.running_index[SM_RX_ID];
+ }
+
+ if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+ struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
+
+ cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
+ USTORM_FCOE_EQ_PROD_OFFSET(pfid);
+ cp->kcq2.sw_prod_idx = 0;
+ cp->kcq2.hw_prod_idx_ptr =
+ &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
+ cp->kcq2.status_idx_ptr =
+ &sb->sb.running_index[SM_RX_ID];
+ }
+}
+
static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
{
struct cnic_local *cp = dev->cnic_priv;
@@ -4413,25 +4465,7 @@ static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
- cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
- CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
- cp->kcq1.sw_prod_idx = 0;
-
- if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
- struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
-
- cp->kcq1.hw_prod_idx_ptr =
- &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
- cp->kcq1.status_idx_ptr =
- &sb->sb.running_index[SM_RX_ID];
- } else {
- struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
-
- cp->kcq1.hw_prod_idx_ptr =
- &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
- cp->kcq1.status_idx_ptr =
- &sb->sb.running_index[SM_RX_ID];
- }
+ cnic_init_bnx2x_kcq(dev);
cnic_get_bnx2x_iscsi_info(dev);
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index fb3b753..e46b4c1 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -258,6 +258,7 @@ struct cnic_local {
u16 kwq_con_idx;
struct kcq_info kcq1;
+ struct kcq_info kcq2;
union {
void *gen;
--
1.6.4.GIT
^ permalink raw reply related
* Re: [patch] USB: mcs7830: return negative if auto negotiate fails
From: David Miller @ 2010-12-23 18:22 UTC (permalink / raw)
To: error27; +Cc: gregkh, linux-usb, netdev, kernel-janitors
In-Reply-To: <20101217132542.GL1639@bicker>
From: Dan Carpenter <error27@gmail.com>
Date: Fri, 17 Dec 2010 16:25:43 +0300
> The original code returns 0 on success and 1 on failure. In fact, at
> this point, "ret" is already either zero or a negative error code so
> we can just return it directly.
>
> Signed-off-by: Dan Carpenter <error27@gmail.com>
Indeed, the USBNET ->bind() method, which this return value propagates
to, expects negative return values on error.
Applied, and queued up for -stable, thanks Dan.
^ permalink raw reply
* Re: [PATCH] irda: prevent integer underflow in IRLMP_ENUMDEVICES
From: David Miller @ 2010-12-23 18:09 UTC (permalink / raw)
To: drosenberg; +Cc: samuel, netdev, security
In-Reply-To: <1293062307.9820.331.camel@dan>
From: Dan Rosenberg <drosenberg@vsecurity.com>
Date: Wed, 22 Dec 2010 18:58:27 -0500
> If the user-provided len is less than the expected offset, the
> IRLMP_ENUMDEVICES getsockopt will do a copy_to_user() with a very large
> size value. While this isn't be a security issue on x86 because it will
> get caught by the access_ok() check, it may leak large amounts of kernel
> heap on other architectures. In any event, this patch fixes it.
>
> Signed-off-by: Dan Rosenberg <drosenberg@vsecurity.com>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH 00/12] make rpc_pipefs be mountable multiple times
From: J. Bruce Fields @ 2010-12-23 18:02 UTC (permalink / raw)
To: Kirill A. Shutemov
Cc: Trond Myklebust, Neil Brown, Pavel Emelyanov,
linux-nfs-u79uwXL29TY76Z2rM5mHXA, David S. Miller,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20101223065033.GA14006-oKw7cIdHH8eLwutG50LtGA@public.gmane.org>
On Thu, Dec 23, 2010 at 08:50:33AM +0200, Kirill A. Shutemov wrote:
> On Tue, Dec 21, 2010 at 06:45:21PM -0500, J. Bruce Fields wrote:
> > On Wed, Dec 22, 2010 at 01:32:15AM +0200, Kirill A. Shutemov wrote:
> > > On Mon, Dec 20, 2010 at 09:46:44AM -0500, J. Bruce Fields wrote:
> > > > By the way, was there ever a resolution to Trond's question?:
> > > >
> > > > http://marc.info/?l=linux-nfs&m=128655758712817&w=2
> > > >
> > > > "The keyring upcalls are currently initiated through the same
> > > > mechanism as module_request and therefore get started with the
> > > > init_nsproxy namespace. We'd really like them to run inside the
> > > > same container as the process. As part of the same problem,
> > > > there is the issue of what to do with the dns resolver and
> > > > Bryan's new keyring based idmapper code."
> > >
> > > I'm not sure that I understand the problem correctly.
> > >
> > > Currently, idmap uses dentry taken from client's cl_rpcclient->cl_path
> > > (see nfs_idmap_new()). cl_rpcclient (and cl_path) is initialized with
> > > rpcmount resolved against mount namespace of mount process (see
> > > nfs_create_rpc_client()).
> > > I assume it's correct.
> >
> > There's actually two separate sets of idmapper code; look at
> > fs/nfs/idmapper.c, the first part of the file (between #ifdef
> > CONFIG_NFS_USE_NEW_IDMAPPER and #else) is idmapping code that uses
> > request_key(). The code you're looking at (including nfs_idmap_new())
> > is later in the file, and deprecated.
>
> IIUC, we need to save nsproxy of mount process in struct nfs_client and
> pass it down to request_key(). I think it's outside of this patchset.
OK. Yes, I wasn't expecting this patchset to deal with it, just
wondered if there was a plan.
--b.
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* RE: [PATCH] bna: bnad_udelay macro cleanup
From: Rasesh Mody @ 2010-12-23 18:00 UTC (permalink / raw)
To: David Miller; +Cc: netdev@vger.kernel.org, Debashis Dutt, Jing Huang
In-Reply-To: <20101223.093819.104073648.davem@davemloft.net>
>From: David Miller [mailto:davem@davemloft.net]
>Sent: Thursday, December 23, 2010 9:38 AM
>
>From: Rasesh Mody <rmody@brocade.com>
>Date: Wed, 22 Dec 2010 23:05:49 -0800
>
>> Change details:
>> - Removed unnecessary bnad_udelay macro for ia64
>>
>> Signed-off-by: Debashis Dutt <ddutt@brocade.com>
>> Signed-off-by: Rasesh Mody <rmody@brocade.com>
>
>Please don't do it this way.
>
>We don't add known crap, then add a patch to remove the crap.
>
>Respin your BNA patch series so that this IA64 stuff never shows
>up in the first place.
>
>Thanks.
We'll respin and resubmit the patches with ia64 macro removed as
per your suggestion. In future we'll take care to avoid this.
--Rasesh
^ permalink raw reply
* Re: [PATCH] smsc911x: add disable and re-enable Rx int to de-assert interrupt pin
From: David Miller @ 2010-12-23 17:59 UTC (permalink / raw)
To: jason77.wang; +Cc: netdev, steve.glendinning, linux-omap
In-Reply-To: <1293100993-3956-1-git-send-email-jason77.wang@gmail.com>
From: Jason Wang <jason77.wang@gmail.com>
Date: Thu, 23 Dec 2010 18:43:13 +0800
> When kernel enters irqhanlder, it will check the Rx interrupt status
> bit, if Rx status is set but can't call napi_schedule(), it will do
> nothing and directly return form irqhandler. This situation is prone
> to be produced when we repeatly call irqhandler through netpoll
> interface(i.e kgdboe connecting).
>
> This is a potential risk for those level triggered platforms(i.e
> ti_omap3evm), because if we don't handle Rx int and just return from
> irqhandler, the irq pin will be keeping asserted, the level triggered
> platforms will have no chance to jump out from the Rx irq. The whole
> system will hung into the irq subsystem.
>
> To solve it, we add a disable/re-enable Rx int operation for this
> situation, this operation can de-assert interrupt pin for this time
> and will leave the received data and status in the FIFO for later
> interrupts to handle.
>
> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
You absolutely cannot do this.
You now can race with the NAPI completion code turning the RX
interrupts back on, and you'll leave the chip with RX interrupts
disabled.
You must solve your level triggered interrupt some other way, every
NAPI based device must manage the interrupt disabling carefully and
only when the napi POLL is successfully scheduled in order to avoid
races.
And especially you must not make a crazy hack like this for obscure
things like kgdboe.
^ permalink raw reply
* Re: [PATCH] tcp: cleanup of cwnd initialization in tcp_init_metrics()
From: David Miller @ 2010-12-23 17:56 UTC (permalink / raw)
To: jkosina; +Cc: eric.dumazet, netdev, linux-kernel, vojtech, ilpo.jarvinen
In-Reply-To: <alpine.LNX.2.00.1012231022430.16569@pobox.suse.cz>
From: Jiri Kosina <jkosina@suse.cz>
Date: Thu, 23 Dec 2010 10:23:38 +0100 (CET)
> Right, that's even better. Updated patch below.
>
>
> From: Jiri Kosina <jkosina@suse.cz>
> Subject: [PATCH] tcp: cleanup of cwnd initialization in tcp_init_metrics()
>
> Commit 86bcebafc5e7f5 ("tcp: fix >2 iw selection") fixed a case
> when congestion window initialization has been mistakenly omitted
> by introducing cwnd label and putting backwards goto from the
> end of the function.
>
> This makes the code unnecessarily tricky to read and understand
> on a first sight.
>
> Shuffle the code around a little bit to make it more obvious.
>
> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Applied, thanks everyone.
^ permalink raw reply
* Re: Workqueues vs. kernel threads for processing asynchronous socket events
From: Martin Sustrik @ 2010-12-23 17:54 UTC (permalink / raw)
To: Martin Lucina; +Cc: netdev
In-Reply-To: <20101210152754.GC28580@dezo.moloch.sk>
On 12/10/2010 04:27 PM, Martin Lucina wrote:
> I'm trying to find the best mechanism to process events from kernel space
> sockets in an asynchronous manner. The work in progress code I have at the
> moment tries to at least call kernel_accept() on a bound TCP socket when it
> gets called by the underlying sk->sk_data_ready callback.
>
> The current approach I have is to use a workqueue and try to schedule work
> inside the callback, but this has the kernel complaining about "scheduling
> while atomic", so it doesn't look like it's the right approach? Am I
> allowed to call schedule_work() from the context of a sk->sk_data_ready
> callback or not?
It turns out that the issue was caused by kmalloc(GFP_KERNEL) in the
callback function, not the schedule_work() function. Using GFP_ATOMIC
instead solves the problem.
Sorry for the annoyance.
Martin
^ permalink raw reply
* Re: ip rule and/or route problem in 2.6.37-rc5+
From: David Miller @ 2010-12-23 17:42 UTC (permalink / raw)
To: zenczykowski; +Cc: therbert, greearb, netdev
In-Reply-To: <AANLkTin0mNkfaDvs3ZrEhxY27kdmZLh8ikKNpc-MXC44@mail.gmail.com>
From: Maciej Żenczykowski <zenczykowski@gmail.com>
Date: Thu, 23 Dec 2010 10:22:23 +0100
> Could we please revert this ( 4465b469008bc03b98a1b8df4e9ae501b6c69d4b
> ) and make sure the revert makes it into 2.6.37? We definitely don't
> want to ship 2.6.37 with this patch in its current state.
I'm moving towards reverting this commit simply because Tom is taking
way too long to fix this regression.
^ permalink raw reply
* Re: [PATCH] bna: bnad_udelay macro cleanup
From: David Miller @ 2010-12-23 17:38 UTC (permalink / raw)
To: rmody; +Cc: netdev, ddutt
In-Reply-To: <1293087949-17613-1-git-send-email-rmody@brocade.com>
From: Rasesh Mody <rmody@brocade.com>
Date: Wed, 22 Dec 2010 23:05:49 -0800
> Change details:
> - Removed unnecessary bnad_udelay macro for ia64
>
> Signed-off-by: Debashis Dutt <ddutt@brocade.com>
> Signed-off-by: Rasesh Mody <rmody@brocade.com>
Please don't do it this way.
We don't add known crap, then add a patch to remove the crap.
Respin your BNA patch series so that this IA64 stuff never shows
up in the first place.
Thanks.
^ permalink raw reply
* Re: 2.6.36.2 - loop on read /proc/net/tcp
From: David Miller @ 2010-12-23 17:33 UTC (permalink / raw)
To: eric.dumazet; +Cc: renton, linux-kernel, netdev
In-Reply-To: <1293080846.2679.41.camel@edumazet-laptop>
From: Eric Dumazet <eric.dumazet@gmail.com>
Date: Thu, 23 Dec 2010 06:07:26 +0100
> [PATCH] tcp: fix listening_get_next()
>
> Alexey Vlasov found /proc/net/tcp could sometime loop and display
> millions of sockets in LISTEN state.
>
> In 2.6.29, when we converted TCP hash tables to RCU, we left two
> sk_next() calls in listening_get_next().
>
> We must instead use sk_nulls_next() to properly detect an end of chain.
>
> Reported-by: Alexey Vlasov <renton@renton.name>
> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com>
Applied, thanks everyone.
^ permalink raw reply
* Re: [PATCH] Export ACPI _DSM provided firmware instance number and string name to sysfs
From: Matt Domsch @ 2010-12-23 14:32 UTC (permalink / raw)
To: Narendra_K
Cc: linux-pci, linux-hotplug, netdev, Jordan_Hargrave, Charles_Rose,
Vijay_Nijhawan
In-Reply-To: <20101222170737.GA2428@fedora14-r610.oslab.blr.amer.dell.com>
On Wed, Dec 22, 2010 at 08:42:39AM -0800, Narendra_K@Dell.com wrote:
> Hello,
>
> This patch exports ACPI _DSM provided firmware instance number and
> string name to sysfs.
>
> Please review -
There are now two different meanings for the 'index' file:
1) SMBIOS-provided "type instance" value, which I've only seen in
range [1..N] for N devices, monotonically stepwise increasing.
2) ACPI-provided "index" value, which per spec only needs to be a
"sort key", not starting at 0 or 1, and while monotonically
increasing, not necessarily stepwise. It's perfectly valid for the
values to be (12, 16, 27, 29) if that's convenient for BIOS to
generate.
Therefore, a consumer of this value (such as biosdevname) must know
which of the two it's dealing with, and either accept the value as-is,
or sort the value list. While I suppose it could sort the value list
in either case, I'd prefer the ACPI value to be exposed in its own
file, perhaps 'acpi_index', to make this explicit rather than
implicit.
'label' is fine for either case, with ACPI taking priority over
SMBIOS if both happen to be present.
Thanks,
Matt
--
Matt Domsch
Technology Strategist
Dell | Office of the CTO
^ permalink raw reply
* Re: [PATCH net-next-2.6 1/2] can: add driver for Softing card
From: Marc Kleine-Budde @ 2010-12-23 14:25 UTC (permalink / raw)
To: Kurt Van Dijck
Cc: socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20101223094302.GB325-MxZ6Iy/zr/UdbCeoMzGj59i2O/JbrIOy@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 59786 bytes --]
On 12/23/2010 10:43 AM, Kurt Van Dijck wrote:
> This patch adds a driver for the platform:softing device.
> This will create (up to) 2 CAN network devices from 1
> platform:softing device
>
> Signed-off-by: Kurt Van Dijck <kurt.van.dijck-/BeEPy95v10@public.gmane.org>
I did some review, but gotta go now, will do more later.
regards, Marc
>
> ---
> drivers/net/can/Kconfig | 2 +
> drivers/net/can/Makefile | 1 +
> drivers/net/can/softing/Kconfig | 16 +
> drivers/net/can/softing/Makefile | 5 +
> drivers/net/can/softing/softing.h | 216 +++++++
> drivers/net/can/softing/softing_fw.c | 664 ++++++++++++++++++++
> drivers/net/can/softing/softing_main.c | 935 ++++++++++++++++++++++++++++
> drivers/net/can/softing/softing_platform.h | 38 ++
> 8 files changed, 1877 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
> index d5a9db6..986195e 100644
> --- a/drivers/net/can/Kconfig
> +++ b/drivers/net/can/Kconfig
> @@ -117,6 +117,8 @@ source "drivers/net/can/sja1000/Kconfig"
>
> source "drivers/net/can/usb/Kconfig"
>
> +source "drivers/net/can/softing/Kconfig"
> +
> config CAN_DEBUG_DEVICES
> bool "CAN devices debugging messages"
> depends on CAN
> diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
> index 07ca159..53c82a7 100644
> --- a/drivers/net/can/Makefile
> +++ b/drivers/net/can/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_CAN_DEV) += can-dev.o
> can-dev-y := dev.o
>
> obj-y += usb/
> +obj-y += softing/
I think it will (at least marginally) speed up the Kernel build process
only to dive into the softing subdir if Softing is enabled in Kconfig.
>
> obj-$(CONFIG_CAN_SJA1000) += sja1000/
> obj-$(CONFIG_CAN_MSCAN) += mscan/
> diff --git a/drivers/net/can/softing/Kconfig b/drivers/net/can/softing/Kconfig
> new file mode 100644
> index 0000000..072f337
> --- /dev/null
> +++ b/drivers/net/can/softing/Kconfig
> @@ -0,0 +1,16 @@
> +config CAN_SOFTING
> + tristate "Softing Gmbh CAN generic support"
> + depends on CAN_DEV
> + ---help---
> + Support for CAN cards from Softing Gmbh & some cards
> + from Vector Gmbh.
> + Softing Gmbh CAN cards come with 1 or 2 physical busses.
> + Those cards typically use Dual Port RAM to communicate
> + with the host CPU. The interface is then identical for PCI
> + and PCMCIA cards. This driver operates on a platform device,
> + which has been created by softing_cs or softing_pci driver.
> + Warning:
> + The API of the card does not allow fine control per bus, but
> + controls the 2 busses on the card together.
> + As such, some actions (start/stop/busoff recovery) on 1 bus
> + must bring down the other bus too temporarily.
> diff --git a/drivers/net/can/softing/Makefile b/drivers/net/can/softing/Makefile
> new file mode 100644
> index 0000000..7878b7b
> --- /dev/null
> +++ b/drivers/net/can/softing/Makefile
> @@ -0,0 +1,5 @@
> +
> +softing-y := softing_main.o softing_fw.o
> +obj-$(CONFIG_CAN_SOFTING) += softing.o
> +
> +ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
> diff --git a/drivers/net/can/softing/softing.h b/drivers/net/can/softing/softing.h
> new file mode 100644
> index 0000000..99046a7
> --- /dev/null
> +++ b/drivers/net/can/softing/softing.h
> @@ -0,0 +1,216 @@
> +/*
> + * softing common interfaces
> + *
> + * by Kurt Van Dijck, 06-2008
> + */
> +
> +#include <linux/netdevice.h>
> +#include <linux/ktime.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/can.h>
> +#include <linux/can/dev.h>
> +
> +#include "softing_platform.h"
> +
> +#ifndef CAN_CTRLMODE_BERR_REPORTING
> +#define CAN_CTRLMODE_BERR_REPORTING 0
> +#endif
> +
> +struct softing;
> +
> +struct softing_priv {
> + struct can_priv can; /* must be the first member! */
> + struct net_device *netdev;
> + struct softing *card;
> + struct {
> + int pending;
> + /* variables wich hold the circular buffer */
> + int echo_put;
> + int echo_get;
> + } tx;
> + struct can_bittiming_const btr_const;
> + int index;
> + u8 output;
> + u16 chip;
> +};
> +#define netdev2softing(netdev) ((struct softing_priv *)netdev_priv(netdev))
> +
> +struct softing {
> + const struct softing_platform_data *pdat;
> + struct platform_device *pdev;
> + struct net_device *net[2];
> + spinlock_t spin; /* protect this structure & DPRAM access */
please just one space after spinlock_t
> + ktime_t ts_ref;
> + ktime_t ts_overflow; /* timestamp overflow value, in ktime */
> +
> + struct {
> + /* indication of firmware status */
> + int up;
> + /* protection of the 'up' variable */
> + struct mutex lock;
> + } fw;
what about using an atomic_t for the firmware status?
> + struct {
> + int nr;
> + int requested;
> + struct tasklet_struct bh;
> + int svc_count;
> + } irq;
> + struct {
> + int pending;
> + int last_bus;
> + /* keep the bus that last tx'd a message,
> + * in order to let every netdev queue resume
> + */
/*
* please fix multi-line comments to
* this style
*/
> + } tx;
> + struct {
> + unsigned long phys;
> + unsigned long size;
> + unsigned char *virt;
> + unsigned char *end;
> + struct softing_fct *fct;
> + struct softing_info *info;
> + struct softing_rx *rx;
> + struct softing_tx *tx;
> + struct softing_irq *irq;
please use just one space
> + unsigned short *command;
> + unsigned short *receipt;
> + } dpram;
> + struct {
> + u32 serial, fw, hw, lic;
> + u16 chip[2];
> + u32 freq;
> + } id;
> +};
> +
> +extern int softing_default_output(struct net_device *netdev);
> +
> +extern ktime_t softing_raw2ktime(struct softing *card, u32 raw);
> +
> +extern int softing_fct_cmd(struct softing *card
> + , int cmd, int vector, const char *msg);
> +
> +extern int softing_bootloader_command(struct softing *card
> + , int command, const char *msg);
> +
Please create a header file for these prototypes. The comma "," should
not be the first char in the new line.
> +/* reset DPRAM */
> +static inline void softing_set_reset_dpram(struct softing *card)
> +{
> + if (card->pdat->generation >= 2) {
> + spin_lock_bh(&card->spin);
> + card->dpram.virt[0xe00] &= ~1;
Can you define a costant (or enum) for 0xe00?
> + spin_unlock_bh(&card->spin);
> + }
> +}
> +
> +static inline void softing_clr_reset_dpram(struct softing *card)
> +{
> + if (card->pdat->generation >= 2) {
> + spin_lock_bh(&card->spin);
> + card->dpram.virt[0xe00] |= 1;
> + spin_unlock_bh(&card->spin);
> + }
> +}
> +
> +/* Load firmware after reset */
> +extern int softing_load_fw(const char *file, struct softing *card,
> + unsigned char *virt, unsigned int size, int offset);
> +
> +/* Load final application firmware after bootloader */
> +extern int softing_load_app_fw(const char *file, struct softing *card);
> +
> +extern int softing_reset_chip(struct softing *card);
> +
> +/*
> + * enable or disable irq
> + * only called with fw.lock locked
> + */
> +extern int softing_enable_irq(struct softing *card, int enable);
> +
> +/* start/stop 1 bus on card */
> +extern int softing_startstop(struct net_device *netdev, int up);
> +
> +/* netif_rx() */
> +extern int softing_netdev_rx(struct net_device *netdev,
> + const struct can_frame *msg, ktime_t ktime);
please put these into a header file.
> +/* SOFTING DPRAM mappings */
> +struct softing_rx {
> + u8 fifo[16][32];
> + u8 dummy1;
Just curious, why did they put a padding byte here, that makes the rest
unaligned?
> + u16 rd;
> + u16 dummy2;
> + u16 wr;
> + u16 dummy3;
> + u16 lost_msg;
> +} __attribute__((packed));
> +
> +#define TXMAX 31
> +struct softing_tx {
> + u8 fifo[32][16];
> + u8 dummy1;
> + u16 rd;
> + u16 dummy2;
> + u16 wr;
> + u8 dummy3;
> +} __attribute__((packed));
> +
> +struct softing_irq {
> + u8 to_host;
> + u8 to_card;
> +} __attribute__((packed));
> +
> +struct softing_fct {
> + s16 param[20]; /* 0 is index */
> + s16 returned;
> + u8 dummy;
> + u16 host_access;
> +} __attribute__((packed));
> +
> +struct softing_info {
> + u8 dummy1;
> + u16 bus_state;
> + u16 dummy2;
> + u16 bus_state2;
> + u16 dummy3;
> + u16 error_state;
> + u16 dummy4;
> + u16 error_state2;
> + u16 dummy5;
> + u16 reset;
> + u16 dummy6;
> + u16 clear_rcv_fifo;
> + u16 dummy7;
> + u16 dummyxx;
> + u16 dummy8;
> + u16 time_reset;
> + u8 dummy9;
> + u32 time;
> + u32 time_wrap;
> + u8 wr_start;
> + u8 wr_end;
> + u8 dummy10;
> + u16 dummy12;
> + u16 dummy12x;
> + u16 dummy13;
> + u16 reset_rcv_fifo;
> + u8 dummy14;
> + u8 reset_xmt_fifo;
> + u8 read_fifo_levels;
> + u16 rcv_fifo_level;
> + u16 xmt_fifo_level;
> +} __attribute__((packed));
Can you renumber the dummy variables (there are some "x" in there), or
does it correspond to some datasheet?
> +
> +/* DPRAM return codes */
> +#define RES_NONE 0
> +#define RES_OK 1
> +#define RES_NOK 2
> +#define RES_UNKNOWN 3
You can use a enum for these.
> +/* DPRAM flags */
> +#define CMD_TX 0x01
> +#define CMD_ACK 0x02
> +#define CMD_XTD 0x04
> +#define CMD_RTR 0x08
> +#define CMD_ERR 0x10
> +#define CMD_BUS2 0x80
An enum can be used here, too, you also can use BIT(x) to define
constants with single bits set.
> +
> diff --git a/drivers/net/can/softing/softing_fw.c b/drivers/net/can/softing/softing_fw.c
> new file mode 100644
> index 0000000..f61299c
> --- /dev/null
> +++ b/drivers/net/can/softing/softing_fw.c
> @@ -0,0 +1,664 @@
> +/*
> +* drivers/net/can/softing/softing_fw.c
> +*
> +* Copyright (C) 2008-2010
> +*
> +* - Kurt Van Dijck, EIA Electronics
> +*
> +* This program is free software; you can redistribute it and/or modify
> +* it under the terms of the version 2 of the GNU General Public License
> +* as published by the Free Software Foundation
> +*
> +* This program is distributed in the hope that it will be useful,
> +* but WITHOUT ANY WARRANTY; without even the implied warranty of
> +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +* GNU General Public License for more details.
> +*
> +* You should have received a copy of the GNU General Public License
> +* along with this program; if not, write to the Free Software
> +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> +*/
> +
> +#include <linux/firmware.h>
> +#include <linux/sched.h>
> +#include <asm/div64.h>
> +
> +#include "softing.h"
> +
> +int softing_fct_cmd(struct softing *card, int cmd, int vector, const char *msg)
> +{
> + int ret;
> + unsigned long stamp;
> + if (vector == RES_OK)
> + vector = RES_NONE;
> + card->dpram.fct->param[0] = cmd;
param[] is an array of s16 and cmd is an int.
hmmm..all stuff behind dpram is __iomem, isn't it? I think it should
only be accessed with via the ioread/iowrite operators. Please check
your code with sparse (compile with "make C=2").
> + card->dpram.fct->host_access = vector;
int vs. s16
> + /* be sure to flush this to the card */
> + wmb();
> + stamp = jiffies;
> + /*wait for card */
^^
please add a space.
> + do {
> + ret = card->dpram.fct->host_access;
> + /* don't have any cached variables */
> + rmb();
> + if (ret == RES_OK) {
> + /*don't read return-value now */
^^
dito
> + ret = card->dpram.fct->returned;
> + if (ret)
> + dev_alert(&card->pdev->dev,
> + "%s returned %u\n", msg, ret);
> + return 0;
If "ret" is != 0 you return 0 here.
> + }
> + if ((jiffies - stamp) >= 1 * HZ)
That's not good. I don't remember the name, but there are some
functions/defines to do this kind of things properly.
> + break;
> + if (in_interrupt())
> + /* go as fast as possible */
In the worst case this means you lock up the system for one second. Does
the card issue an interrupt if it's finished? Another option is to write
a threaded interrupt handler.
> + continue;
> + /* process context => relax */
> + schedule();
> + } while (!signal_pending(current));
> +
> + if (ret == RES_NONE) {
> + dev_alert(&card->pdev->dev,
> + "%s, no response from card on %u/0x%02x\n",
> + msg, cmd, vector);
> + return 1;
> + } else {
> + dev_alert(&card->pdev->dev,
> + "%s, bad response from card on %u/0x%02x, 0x%04x\n",
> + msg, cmd, vector, ret);
> + /*make sure to return something not 0 */
^^
space
> + return ret ? ret : 1;
> + }
> +}
> +
> +int softing_bootloader_command(struct softing *card
> + , int command, const char *msg)
please move the comma one line up.
> +{
> + int ret;
> + unsigned long stamp;
> + card->dpram.receipt[0] = RES_NONE;
> + card->dpram.command[0] = command;
> + /* be sure to flush this to the card */
> + wmb();
> + stamp = jiffies;
> + /*wait for card */
> + do {
> + ret = card->dpram.receipt[0];
> + /* don't have any cached variables */
> + rmb();
> + if (ret == RES_OK)
> + return 0;
> + if ((jiffies - stamp) >= (3 * HZ))
> + break;
> + schedule();
same applies here, too. Although this command seems not to be called
from interrupt context, what about using a msleep() instead of a schedule?
> + } while (!signal_pending(current));
> +
> + switch (ret) {
> + case RES_NONE:
> + dev_alert(&card->pdev->dev, "%s: no response from card\n", msg);
> + break;
> + case RES_NOK:
> + dev_alert(&card->pdev->dev, "%s: response from card nok\n",
> + msg);
> + break;
> + case RES_UNKNOWN:
> + dev_alert(&card->pdev->dev, "%s: command 0x%04x unknown\n",
> + msg, command);
> + break;
> + default:
> + dev_alert(&card->pdev->dev, "%s: bad response from card: %i\n",
> + msg, ret);
> + break;
> + }
> + return ret ? ret : 1;
> +}
> +
> +struct fw_hdr {
> + u16 type;
> + u32 addr;
> + u16 len;
> + u16 checksum;
> + const unsigned char *base;
> +} __attribute__ ((packed));
> +
> +static int fw_parse(const unsigned char **pmem, struct fw_hdr *hdr)
> +{
> + u16 tmp;
> + const unsigned char *mem;
> + const unsigned char *end;
you can define a struct with __be16 and use be16_to_cpu to access these...
> + mem = *pmem;
> + hdr->type = (mem[0] << 0) | (mem[1] << 8);
> + hdr->addr = (mem[2] << 0) | (mem[3] << 8)
> + | (mem[4] << 16) | (mem[5] << 24);
> + hdr->len = (mem[6] << 0) | (mem[7] << 8);
> + hdr->base = &mem[8];
> + hdr->checksum =
> + (hdr->base[hdr->len] << 0) | (hdr->base[hdr->len + 1] << 8);
> + for (tmp = 0, mem = *pmem, end = &hdr->base[hdr->len]; mem < end; ++mem)
> + tmp += *mem;
> + if (tmp != hdr->checksum)
> + return -EINVAL;
> + *pmem += 10 + hdr->len;
> + return 0;
> +}
> +
> +int softing_load_fw(const char *file, struct softing *card,
> + unsigned char *virt, unsigned int size, int offset)
> +{
> + const struct firmware *fw;
> + const unsigned char *mem;
> + const unsigned char *end;
> + int ret = 0;
> + u32 start_addr;
> + struct fw_hdr rec;
> + int ok = 0;
> + unsigned char buf[1024];
> +
> + ret = request_firmware(&fw, file, &card->pdev->dev);
> + if (ret) {
> + dev_alert(&card->pdev->dev, "request_firmware(%s) got %i\n",
> + file, ret);
> + return ret;
> + }
> + dev_dbg(&card->pdev->dev, "%s, firmware(%s) got %u bytes"
> + ", offset %c0x%04x\n",
> + card->pdat->name, file, (unsigned int)fw->size,
> + (offset >= 0) ? '+' : '-', (unsigned int)abs(offset));
> + /* parse the firmware */
> + mem = fw->data;
> + end = &mem[fw->size];
> + /* look for header record */
> + ret = fw_parse(&mem, &rec);
> + if (ret < 0)
> + goto fw_end;
> + if (rec.type != 0xffff) {
> + dev_alert(&card->pdev->dev, "firware starts with type 0x%04x\n",
> + rec.type);
> + goto fw_end;
> + }
> + if (strncmp("Structured Binary Format, Softing GmbH"
> + , rec.base, rec.len)) {
> + dev_info(&card->pdev->dev, "firware string '%.*s'\n",
> + rec.len, rec.base);
> + goto fw_end;
> + }
> + ok |= 1;
> + /* ok, we had a header */
> + while (mem < end) {
> + ret = fw_parse(&mem, &rec);
> + if (ret)
> + break;
> + if (rec.type == 3) {
> + /*start address */
> + start_addr = rec.addr;
> + ok |= 2;
> + continue;
> + } else if (rec.type == 1) {
> + /*eof */
> + ok |= 4;
> + goto fw_end;
> + } else if (rec.type != 0) {
> + dev_alert(&card->pdev->dev, "unknown record type 0x%04x\n",
> + rec.type);
> + break;
> + }
> +
> + if ((rec.addr + rec.len + offset) > size) {
> + dev_alert(&card->pdev->dev,
> + "firmware out of range (0x%08x / 0x%08x)\n",
> + (rec.addr + rec.len + offset), size);
> + goto fw_end;
> + }
> + memcpy_toio(&virt[rec.addr + offset],
> + rec.base, rec.len);
> + /* be sure to flush caches from IO space */
> + mb();
> + if (rec.len > sizeof(buf)) {
> + dev_info(&card->pdev->dev,
> + "record is big (%u bytes), not verifying\n",
> + rec.len);
> + continue;
> + }
> + /* verify record data */
> + memcpy_fromio(buf, &virt[rec.addr + offset], rec.len);
> + if (!memcmp(buf, rec.base, rec.len))
> + /* is ok */
> + continue;
> + dev_alert(&card->pdev->dev, "0x%08x:0x%03x at 0x%p failed\n",
> + rec.addr, rec.len, &virt[rec.addr + offset]);
> + goto fw_end;
> + }
> +fw_end:
> + release_firmware(fw);
> + if (0x5 == (ok & 0x5))
> + /* got eof & start */
> + return 0;
> + dev_info(&card->pdev->dev, "firmware %s failed\n", file);
> + return ret ?: -EINVAL;
> +}
> +
> +int softing_load_app_fw(const char *file, struct softing *card)
> +{
> + const struct firmware *fw;
> + const unsigned char *mem;
> + const unsigned char *end;
> + int ret;
> + struct fw_hdr rec;
> + int ok = 0;
> + u32 start_addr = 0;
> + u16 rx_sum;
> + unsigned int sum;
> + const unsigned char *mem_lp;
> + const unsigned char *mem_end;
> + struct cpy {
> + u32 src;
> + u32 dst;
> + u16 len;
> + u8 do_cs;
> + } __attribute__((packed)) *pcpy =
> + (struct cpy *)&card->dpram.command[1];
> + struct cmd {
> + u32 start;
> + u8 autorestart;
> + } __attribute__((packed)) *pcmdstart =
> + (struct cmd *)&card->dpram.command[1];
> +
> + ret = request_firmware(&fw, file, &card->pdev->dev);
> + if (ret) {
> + dev_alert(&card->pdev->dev, "request_firmware(%s) got %i\n",
> + file, ret);
> + return ret;
> + }
> + dev_dbg(&card->pdev->dev, "firmware(%s) got %lu bytes\n",
> + file, (unsigned long)fw->size);
> + /* parse the firmware */
> + mem = fw->data;
> + end = &mem[fw->size];
> + /* look for header record */
> + ret = fw_parse(&mem, &rec);
> + if (ret)
> + goto fw_end;
> + if (rec.type != 0xffff) {
> + dev_alert(&card->pdev->dev, "firware starts with type 0x%04x\n",
> + rec.type);
> + goto fw_end;
> + }
> + if (strncmp("Structured Binary Format, Softing GmbH"
> + , rec.base, rec.len)) {
> + dev_alert(&card->pdev->dev, "firware string '%.*s' fault\n",
> + rec.len, rec.base);
> + goto fw_end;
> + }
> + ok |= 1;
> + /* ok, we had a header */
> + while (mem < end) {
> + ret = fw_parse(&mem, &rec);
> + if (ret)
> + break;
> +
> + if (rec.type == 3) {
> + /*start address */
> + start_addr = rec.addr;
> + ok |= 2;
> + continue;
> + } else if (rec.type == 1) {
> + /*eof */
> + ok |= 4;
> + goto fw_end;
> + } else if (rec.type != 0) {
> + dev_alert(&card->pdev->dev, "unknown record type 0x%04x\n",
> + rec.type);
> + break;
> + }
> + /* regualar data */
> + for (sum = 0, mem_lp = rec.base, mem_end = &mem_lp[rec.len];
> + mem_lp < mem_end; ++mem_lp)
> + sum += *mem_lp;
> +
> + memcpy_toio(&card->dpram. virt[card->pdat->app.offs],
> + rec.base, rec.len);
> + pcpy->src = card->pdat->app.offs + card->pdat->app.addr;
> + pcpy->dst = rec.addr;
> + pcpy->len = rec.len;
> + pcpy->do_cs = 1;
> + if (softing_bootloader_command(card, 1, "loading app."))
> + goto fw_end;
> + /*verify checksum */
> + rx_sum = card->dpram.receipt[1];
> + if (rx_sum != (sum & 0xffff)) {
> + dev_alert(&card->pdev->dev, "SRAM seems to be damaged"
> + ", wanted 0x%04x, got 0x%04x\n", sum, rx_sum);
> + goto fw_end;
> + }
> + }
> +fw_end:
> + release_firmware(fw);
> + if (ok != 7)
> + goto fw_failed;
> + /*got start, start_addr, & eof */
> + pcmdstart->start = start_addr;
> + pcmdstart->autorestart = 1;
> + if (softing_bootloader_command(card, 3, "start app."))
> + goto fw_failed;
> + dev_info(&card->pdev->dev, "firmware %s up\n", file);
> + return 0;
> +fw_failed:
> + dev_info(&card->pdev->dev, "firmware %s failed\n", file);
> + return ret ?: -EINVAL;
> +}
> +
> +int softing_reset_chip(struct softing *card)
> +{
> + do {
> + /*reset chip */
> + card->dpram.info->reset_rcv_fifo = 0;
> + card->dpram.info->reset = 1;
> + if (!softing_fct_cmd(card, 0, 0, "reset_chip"))
> + break;
> + if (signal_pending(current))
> + goto failed;
> + /*sync */
> + if (softing_fct_cmd(card, 99, 0x55, "sync-a"))
> + goto failed;
> + if (softing_fct_cmd(card, 99, 0xaa, "sync-a"))
> + goto failed;
> + } while (1);
> + card->tx.pending = 0;
> + return 0;
> +failed:
> + return -EIO;
> +}
> +
> +static void softing_initialize_timestamp(struct softing *card)
> +{
> + uint64_t ovf;
> +
> + card->ts_ref = ktime_get();
> +
> + /* 16MHz is the reference */
> + ovf = 0x100000000ULL * 16;
> + do_div(ovf, card->pdat->freq ?: 16);
> +
> + card->ts_overflow = ktime_add_us(ktime_set(0, 0), ovf);
> +}
> +
> +ktime_t softing_raw2ktime(struct softing *card, u32 raw)
> +{
> + uint64_t rawl;
> + ktime_t now, real_offset;
> + ktime_t target;
> + ktime_t tmp;
> +
> + now = ktime_get();
> + real_offset = ktime_sub(ktime_get_real(), now);
> +
> + /* find nsec from card */
> + rawl = raw * 16;
> + do_div(rawl, card->pdat->freq ?: 16);
> + target = ktime_add_us(card->ts_ref, rawl);
> + /* test for overflows */
> + tmp = ktime_add(target, card->ts_overflow);
> + while (unlikely(ktime_to_ns(tmp) > ktime_to_ns(now))) {
> + card->ts_ref = ktime_add(card->ts_ref, card->ts_overflow);
> + target = tmp;
> + tmp = ktime_add(target, card->ts_overflow);
> + }
> + return ktime_add(target, real_offset);
> +}
> +
> +static inline int softing_error_reporting(struct net_device *netdev)
> +{
> + struct softing_priv *priv = netdev_priv(netdev);
> +
> + return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
> + ? 1 : 0;
> +}
> +
> +int softing_startstop(struct net_device *dev, int up)
> +{
> + int ret;
> + struct softing *card;
> + struct softing_priv *priv;
> + struct net_device *netdev;
> + int mask_start;
> + int j, error_reporting;
> + struct can_frame msg;
> +
> + priv = netdev_priv(dev);
> + card = priv->card;
> +
> + if (!card->fw.up)
> + return -EIO;
> +
> + ret = mutex_lock_interruptible(&card->fw.lock);
> + if (ret)
> + return ret;
> +
> + mask_start = 0;
> + if (dev && up)
> + /* prepare to start this bus as well */
> + mask_start |= (1 << priv->index);
> + /* bring netdevs down */
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + netdev = card->net[j];
> + if (!netdev)
> + continue;
> + priv = netdev_priv(netdev);
> +
> + if (dev != netdev)
> + netif_stop_queue(netdev);
> +
> + if (netif_running(netdev)) {
> + if (dev != netdev)
> + mask_start |= (1 << j);
> + priv->tx.pending = 0;
> + priv->tx.echo_put = 0;
> + priv->tx.echo_get = 0;
> + /* this bus' may just have called open_candev()
> + * which is rather stupid to call close_candev()
> + * already
> + * but we may come here from busoff recovery too
> + * in which case the echo_skb _needs_ flushing too.
> + * just be sure to call open_candev() again
> + */
> + close_candev(netdev);
> + }
> + priv->can.state = CAN_STATE_STOPPED;
> + }
> + card->tx.pending = 0;
> +
> + softing_enable_irq(card, 0);
> + ret = softing_reset_chip(card);
> + if (ret)
> + goto failed;
> + if (!mask_start)
> + /* no busses to be brought up */
> + goto card_done;
> +
> + if ((mask_start & 1) && (mask_start & 2)
> + && (softing_error_reporting(card->net[0])
> + != softing_error_reporting(card->net[1]))) {
> + dev_alert(&card->pdev->dev,
> + "err_reporting flag differs for busses\n");
> + goto invalid;
> + }
> + error_reporting = 0;
> + if (mask_start & 1) {
> + netdev = card->net[0];
> + priv = netdev_priv(netdev);
> + error_reporting += softing_error_reporting(netdev);
> + /*init chip 1 */
> + card->dpram.fct->param[1] = priv->can.bittiming.brp;
> + card->dpram.fct->param[2] = priv->can.bittiming.sjw;
> + card->dpram.fct->param[3] =
> + priv->can.bittiming.phase_seg1 +
> + priv->can.bittiming.prop_seg;
> + card->dpram.fct->param[4] =
> + priv->can.bittiming.phase_seg2;
> + card->dpram.fct->param[5] = (priv->can.ctrlmode &
> + CAN_CTRLMODE_3_SAMPLES) ? 1 : 0;
> + if (softing_fct_cmd(card, 1, 0, "initialize_chip[0]"))
> + goto failed;
> + /*set mode */
> + card->dpram.fct->param[1] = 0;
> + card->dpram.fct->param[2] = 0;
> + if (softing_fct_cmd(card, 3, 0, "set_mode[0]"))
> + goto failed;
> + /*set filter */
> + card->dpram.fct->param[1] = 0x0000;/*card->bus[0].s.msg; */
> + card->dpram.fct->param[2] = 0x07ff;/*card->bus[0].s.msk; */
> + card->dpram.fct->param[3] = 0x0000;/*card->bus[0].l.msg; */
> + card->dpram.fct->param[4] = 0xffff;/*card->bus[0].l.msk; */
> + card->dpram.fct->param[5] = 0x0000;/*card->bus[0].l.msg >> 16;*/
> + card->dpram.fct->param[6] = 0x1fff;/*card->bus[0].l.msk >> 16;*/
> + if (softing_fct_cmd(card, 7, 0, "set_filter[0]"))
> + goto failed;
> + /*set output control */
> + card->dpram.fct->param[1] = priv->output;
> + if (softing_fct_cmd(card, 5, 0, "set_output[0]"))
> + goto failed;
> + }
> + if (mask_start & 2) {
> + netdev = card->net[1];
> + priv = netdev_priv(netdev);
> + error_reporting += softing_error_reporting(netdev);
> + /*init chip2 */
> + card->dpram.fct->param[1] = priv->can.bittiming.brp;
> + card->dpram.fct->param[2] = priv->can.bittiming.sjw;
> + card->dpram.fct->param[3] =
> + priv->can.bittiming.phase_seg1 +
> + priv->can.bittiming.prop_seg;
> + card->dpram.fct->param[4] =
> + priv->can.bittiming.phase_seg2;
> + card->dpram.fct->param[5] = (priv->can.ctrlmode &
> + CAN_CTRLMODE_3_SAMPLES) ? 1 : 0;
> + if (softing_fct_cmd(card, 2, 0, "initialize_chip[1]"))
> + goto failed;
> + /*set mode2 */
> + card->dpram.fct->param[1] = 0;
> + card->dpram.fct->param[2] = 0;
> + if (softing_fct_cmd(card, 4, 0, "set_mode[1]"))
> + goto failed;
> + /*set filter2 */
> + card->dpram.fct->param[1] = 0x0000;/*card->bus[1].s.msg; */
> + card->dpram.fct->param[2] = 0x07ff;/*card->bus[1].s.msk; */
> + card->dpram.fct->param[3] = 0x0000;/*card->bus[1].l.msg; */
> + card->dpram.fct->param[4] = 0xffff;/*card->bus[1].l.msk; */
> + card->dpram.fct->param[5] = 0x0000;/*card->bus[1].l.msg >> 16;*/
> + card->dpram.fct->param[6] = 0x1fff;/*card->bus[1].l.msk >> 16;*/
> + if (softing_fct_cmd(card, 8, 0, "set_filter[1]"))
> + goto failed;
> + /*set output control2 */
> + card->dpram.fct->param[1] = priv->output;
> + if (softing_fct_cmd(card, 6, 0, "set_output[1]"))
> + goto failed;
> + }
> + /*enable_error_frame */
> + if (error_reporting) {
> + if (softing_fct_cmd(card, 51, 0, "enable_error_frame"))
> + goto failed;
> + }
> + /*initialize interface */
> + card->dpram.fct->param[1] = 1;
> + card->dpram.fct->param[2] = 1;
> + card->dpram.fct->param[3] = 1;
> + card->dpram.fct->param[4] = 1;
> + card->dpram.fct->param[5] = 1;
> + card->dpram.fct->param[6] = 1;
> + card->dpram.fct->param[7] = 1;
> + card->dpram.fct->param[8] = 1;
> + card->dpram.fct->param[9] = 1;
> + card->dpram.fct->param[10] = 1;
> + if (softing_fct_cmd(card, 17, 0, "initialize_interface"))
> + goto failed;
> + /*enable_fifo */
> + if (softing_fct_cmd(card, 36, 0, "enable_fifo"))
> + goto failed;
> + /*enable fifo tx ack */
> + if (softing_fct_cmd(card, 13, 0, "fifo_tx_ack[0]"))
> + goto failed;
> + /*enable fifo tx ack2 */
> + if (softing_fct_cmd(card, 14, 0, "fifo_tx_ack[1]"))
> + goto failed;
> + /*enable timestamps */
> + /*is default, no code found */
> + /*start_chip */
> + if (softing_fct_cmd(card, 11, 0, "start_chip"))
> + goto failed;
> + card->dpram.info->bus_state = 0;
> + card->dpram.info->bus_state2 = 0;
> + dev_info(&card->pdev->dev, "%s up\n", __func__);
> + if (card->pdat->generation < 2) {
> + card->dpram.irq->to_host = 0;
> + /* flush the DPRAM caches */
> + wmb();
> + }
> +
> + softing_initialize_timestamp(card);
> +
> + /*
> + * do socketcan notifications/status changes
> + * from here, no errors should occur, or the failed: part
> + * must be reviewed
> + */
> + memset(&msg, 0, sizeof(msg));
> + msg.can_id = CAN_ERR_FLAG | CAN_ERR_RESTARTED;
> + msg.can_dlc = CAN_ERR_DLC;
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + if (!(mask_start & (1 << j)))
> + continue;
> + netdev = card->net[j];
> + if (!netdev)
> + continue;
> + priv = netdev_priv(netdev);
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> + open_candev(netdev);
> + if (dev != netdev) {
> + /* notify other busses on the restart */
> + softing_netdev_rx(netdev, &msg, ktime_set(0, 0));
> + ++priv->can.can_stats.restarts;
> + }
> + netif_wake_queue(netdev);
> + }
> +
> + /* enable interrupts */
> + ret = softing_enable_irq(card, 1);
> + if (ret)
> + goto failed;
> +card_done:
> + mutex_unlock(&card->fw.lock);
> + return 0;
> +failed:
> + dev_alert(&card->pdev->dev, "firmware failed, going idle\n");
> +invalid:
> + softing_enable_irq(card, 0);
> + softing_reset_chip(card);
> + mutex_unlock(&card->fw.lock);
> + /* bring all other interfaces down */
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + netdev = card->net[j];
> + if (!netdev)
> + continue;
> + dev_close(netdev);
> + }
> + return -EIO;
> +}
> +
> +int softing_default_output(struct net_device *netdev)
> +{
> + struct softing_priv *priv = netdev_priv(netdev);
> + struct softing *card = priv->card;
> +
> + switch (priv->chip) {
> + case 1000:
> + if (card->pdat->generation < 2)
> + return 0xfb;
> + return 0xfa;
> + case 5:
> + return 0x60;
> + default:
> + return 0x40;
> + }
> +}
> +
> diff --git a/drivers/net/can/softing/softing_main.c b/drivers/net/can/softing/softing_main.c
> new file mode 100644
> index 0000000..a3d94d4
> --- /dev/null
> +++ b/drivers/net/can/softing/softing_main.c
> @@ -0,0 +1,935 @@
> +/*
> +* drivers/net/can/softing/softing_main.c
> +*
> +* Copyright (C) 2008-2010
> +*
> +* - Kurt Van Dijck, EIA Electronics
> +*
> +* This program is free software; you can redistribute it and/or modify
> +* it under the terms of the version 2 of the GNU General Public License
> +* as published by the Free Software Foundation
> +*
> +* This program is distributed in the hope that it will be useful,
> +* but WITHOUT ANY WARRANTY; without even the implied warranty of
> +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +* GNU General Public License for more details.
> +*
> +* You should have received a copy of the GNU General Public License
> +* along with this program; if not, write to the Free Software
> +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> +*/
> +
> +#include <linux/version.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +
> +#include "softing.h"
> +
> +#define TX_ECHO_SKB_MAX (TXMAX/2)
> +
> +/*
> + * test is a specific CAN netdev
> + * is online (ie. up 'n running, not sleeping, not busoff
> + */
> +static inline int canif_is_active(struct net_device *netdev)
> +{
> + struct can_priv *can = netdev_priv(netdev);
> + if (!netif_running(netdev))
> + return 0;
> + return (can->state <= CAN_STATE_ERROR_PASSIVE);
> +}
> +
> +/* trigger the tx queue-ing */
> +static netdev_tx_t
> +softing_netdev_start_xmit(struct sk_buff *skb, struct net_device *dev)
> +{
> + struct softing_priv *priv = netdev_priv(dev);
> + struct softing *card = priv->card;
> + int ret;
> + int bhlock;
> + u8 *ptr;
> + u8 cmd;
> + unsigned int fifo_wr;
> + struct can_frame msg;
> +
> + if (can_dropped_invalid_skb(dev, skb))
> + return NETDEV_TX_OK;
> +
> + if (in_interrupt()) {
> + bhlock = 0;
> + spin_lock(&card->spin);
> + } else {
> + bhlock = 1;
> + spin_lock_bh(&card->spin);
> + }
> + ret = NETDEV_TX_BUSY;
> + if (!card->fw.up)
> + goto xmit_done;
> + if (card->tx.pending >= TXMAX)
> + goto xmit_done;
> + if (priv->tx.pending >= TX_ECHO_SKB_MAX)
> + goto xmit_done;
> + fifo_wr = card->dpram.tx->wr;
> + if (fifo_wr == card->dpram.tx->rd)
> + /*fifo full */
> + goto xmit_done;
> + memcpy(&msg, skb->data, sizeof(msg));
> + ptr = &card->dpram.tx->fifo[fifo_wr][0];
> + cmd = CMD_TX;
> + if (msg.can_id & CAN_RTR_FLAG)
> + cmd |= CMD_RTR;
> + if (msg.can_id & CAN_EFF_FLAG)
> + cmd |= CMD_XTD;
> + if (priv->index)
> + cmd |= CMD_BUS2;
> + *ptr++ = cmd;
> + *ptr++ = msg.can_dlc;
> + *ptr++ = (msg.can_id >> 0);
> + *ptr++ = (msg.can_id >> 8);
> + if (msg.can_id & CAN_EFF_FLAG) {
> + *ptr++ = (msg.can_id >> 16);
> + *ptr++ = (msg.can_id >> 24);
> + } else {
> + /*increment 1, not 2 as you might think */
> + ptr += 1;
> + }
> + if (!(msg.can_id & CAN_RTR_FLAG))
> + memcpy_toio(ptr, &msg.data[0], msg.can_dlc);
> + if (++fifo_wr >=
> + sizeof(card->dpram.tx->fifo) /
> + sizeof(card->dpram.tx->fifo[0]))
> + fifo_wr = 0;
> + card->dpram.tx->wr = fifo_wr;
> + card->tx.last_bus = priv->index;
> + ++card->tx.pending;
> + ++priv->tx.pending;
> + can_put_echo_skb(skb, dev, priv->tx.echo_put);
> + ++priv->tx.echo_put;
> + if (priv->tx.echo_put >= TX_ECHO_SKB_MAX)
> + priv->tx.echo_put = 0;
> + /* can_put_echo_skb() saves the skb, safe to return TX_OK */
> + ret = NETDEV_TX_OK;
> +xmit_done:
> + if (bhlock)
> + spin_unlock_bh(&card->spin);
> + else
> + spin_unlock(&card->spin);
> + if (card->tx.pending >= TXMAX) {
> + int j;
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + if (card->net[j])
> + netif_stop_queue(card->net[j]);
> + }
> + }
> + if (ret != NETDEV_TX_OK)
> + netif_stop_queue(dev);
> +
> + return ret;
> +}
> +
> +/*
> + * shortcut for skb delivery
> + */
> +int softing_netdev_rx(struct net_device *netdev,
> + const struct can_frame *msg, ktime_t ktime)
> +{
> + struct sk_buff *skb;
> + struct can_frame *cf;
> + int ret;
> +
> + skb = alloc_can_skb(netdev, &cf);
> + if (!skb)
> + return -ENOMEM;
> + memcpy(cf, msg, sizeof(*msg));
> + skb->tstamp = ktime;
> + ret = netif_rx(skb);
> + if (ret == NET_RX_DROP)
> + ++netdev->stats.rx_dropped;
> + return ret;
> +}
> +
> +/*
> + * softing_handle_1
> + * pop 1 entry from the DPRAM queue, and process
> + */
> +static int softing_handle_1(struct softing *card)
> +{
> + int j;
> + struct net_device *netdev;
> + struct softing_priv *priv;
> + ktime_t ktime;
> + struct can_frame msg;
> +
> + unsigned int fifo_rd;
> + unsigned int cnt = 0;
> + u8 *ptr;
> + u32 tmp;
> + u8 cmd;
> +
> + memset(&msg, 0, sizeof(msg));
> + if (card->dpram.rx->lost_msg) {
> + /*reset condition */
> + card->dpram.rx->lost_msg = 0;
> + /* prepare msg */
> + msg.can_id = CAN_ERR_FLAG | CAN_ERR_CRTL;
> + msg.can_dlc = CAN_ERR_DLC;
> + msg.data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
> + /*
> + * service to all busses, we don't know which it was applicable
> + * but only service busses that are online
> + */
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + netdev = card->net[j];
> + if (!netdev)
> + continue;
> + if (!canif_is_active(netdev))
> + /* a dead bus has no overflows */
> + continue;
> + ++netdev->stats.rx_over_errors;
> + softing_netdev_rx(netdev, &msg, ktime_set(0, 0));
> + }
> + /* prepare for other use */
> + memset(&msg, 0, sizeof(msg));
> + ++cnt;
> + }
> +
> + fifo_rd = card->dpram.rx->rd;
> + if (++fifo_rd >= ARRAY_SIZE(card->dpram.rx->fifo))
> + fifo_rd = 0;
> +
> + if (card->dpram.rx->wr == fifo_rd)
> + return cnt;
> +
> + ptr = &card->dpram.rx->fifo[fifo_rd][0];
> +
> + cmd = *ptr++;
> + if (cmd == 0xff) {
> + /*not quite usefull, probably the card has got out */
> + dev_alert(&card->pdev->dev, "got cmd 0x%02x,"
> + " I suspect the card is lost\n", cmd);
> + }
> + /*mod_trace("0x%02x", cmd);*/
> + netdev = card->net[0];
> + if (cmd & CMD_BUS2)
> + netdev = card->net[1];
> + priv = netdev_priv(netdev);
> +
> + if (cmd & CMD_ERR) {
> + u8 can_state;
> + u8 state;
> + state = *ptr++;
> +
> + msg.can_id = CAN_ERR_FLAG;
> + msg.can_dlc = CAN_ERR_DLC;
> +
> + if (state & 0x80) {
> + can_state = CAN_STATE_BUS_OFF;
> + msg.can_id |= CAN_ERR_BUSOFF;
> + state = 2;
> + } else if (state & 0x60) {
> + can_state = CAN_STATE_ERROR_PASSIVE;
> + msg.can_id |= CAN_ERR_BUSERROR;
> + msg.data[1] = CAN_ERR_CRTL_TX_PASSIVE;
> + state = 1;
> + } else {
> + can_state = CAN_STATE_ERROR_ACTIVE;
> + state = 0;
> + msg.can_id |= CAN_ERR_BUSERROR;
> + }
> + /*update DPRAM */
> + if (!priv->index)
> + card->dpram.info->bus_state = state;
> + else
> + card->dpram.info->bus_state2 = state;
> + /*timestamp */
> + tmp = (ptr[0] << 0) | (ptr[1] << 8)
> + | (ptr[2] << 16) | (ptr[3] << 24);
> + ptr += 4;
> + ktime = softing_raw2ktime(card, tmp);
> + /*trigger dual port RAM */
> + mb();
> + card->dpram.rx->rd = fifo_rd;
> +
> + ++priv->can.can_stats.bus_error;
> + ++netdev->stats.rx_errors;
> + /*update internal status */
> + if (can_state != priv->can.state) {
> + priv->can.state = can_state;
> + if (can_state == CAN_STATE_ERROR_PASSIVE)
> + ++priv->can.can_stats.error_passive;
> + if (can_state == CAN_STATE_BUS_OFF) {
> + /* this calls can_close_cleanup() */
> + can_bus_off(netdev);
> + netif_stop_queue(netdev);
> + }
> + /*trigger socketcan */
> + softing_netdev_rx(netdev, &msg, ktime);
> + }
> +
> + } else {
> + if (cmd & CMD_RTR)
> + msg.can_id |= CAN_RTR_FLAG;
> + /* acknowledge, was tx msg
> + * no real tx flag to set
> + if (cmd & CMD_ACK) {
> + }
> + */
> + msg.can_dlc = get_can_dlc(*ptr++);
> + if (cmd & CMD_XTD) {
> + msg.can_id |= CAN_EFF_FLAG;
> + msg.can_id |= (ptr[0] << 0) | (ptr[1] << 8)
> + | (ptr[2] << 16) | (ptr[3] << 24);
> + ptr += 4;
> + } else {
> + msg.can_id |= (ptr[0] << 0) | (ptr[1] << 8);
> + ptr += 2;
> + }
> + tmp = (ptr[0] << 0) | (ptr[1] << 8)
> + | (ptr[2] << 16) | (ptr[3] << 24);
> + ptr += 4;
> + ktime = softing_raw2ktime(card, tmp);
> + memcpy_fromio(&msg.data[0], ptr, 8);
> + ptr += 8;
> + /*trigger dual port RAM */
> + mb();
> + card->dpram.rx->rd = fifo_rd;
> + /*update socket */
> + if (cmd & CMD_ACK) {
> + struct sk_buff *skb;
> + skb = priv->can.echo_skb[priv->tx.echo_get];
> + if (skb)
> + skb->tstamp = ktime;
> + can_get_echo_skb(netdev, priv->tx.echo_get);
> + ++priv->tx.echo_get;
> + if (priv->tx.echo_get >= TX_ECHO_SKB_MAX)
> + priv->tx.echo_get = 0;
> + if (priv->tx.pending)
> + --priv->tx.pending;
> + if (card->tx.pending)
> + --card->tx.pending;
> + ++netdev->stats.tx_packets;
> + netdev->stats.tx_bytes += msg.can_dlc;
> + } else {
> + ++netdev->stats.rx_packets;
> + netdev->stats.rx_bytes += msg.can_dlc;
> + softing_netdev_rx(netdev, &msg, ktime);
> + }
> + }
> + ++cnt;
> + return cnt;
> +}
> +
> +/*
> + * real interrupt handler
> + */
> +static void softing_handler(unsigned long param)
> +{
> + struct softing *card = (struct softing *)param;
> + struct net_device *netdev;
> + struct softing_priv *priv;
> + int j;
> + int offset;
> +
> + spin_lock(&card->spin);
> + while (softing_handle_1(card) > 0)
> + ++card->irq.svc_count;
> + spin_unlock(&card->spin);
> + /*resume tx queue's */
> + offset = card->tx.last_bus;
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + if (card->tx.pending >= TXMAX)
> + break;
> + netdev = card->net[(j + offset + 1) % card->pdat->nbus];
> + if (!netdev)
> + continue;
> + priv = netdev_priv(netdev);
> + if (!canif_is_active(netdev))
> + /* it makes no sense to wake dead busses */
> + continue;
> + if (priv->tx.pending >= TX_ECHO_SKB_MAX)
> + continue;
> + netif_wake_queue(netdev);
> + }
> +}
> +
> +/*
> + * interrupt routines:
> + * schedule the 'real interrupt handler'
> + */
> +static
> +irqreturn_t softing_irq_new(int irq, void *dev_id)
> +{
> + struct softing *card = (struct softing *)dev_id;
> + unsigned char ir;
> + ir = card->dpram.virt[0xe02];
> + card->dpram.virt[0xe02] = 0;
> + if (card->dpram.rx->rd == 0xffff) {
> + dev_alert(&card->pdev->dev, "I think the card is gone\n");
> + return IRQ_NONE;
> + }
> + if (ir == 1) {
> + tasklet_schedule(&card->irq.bh);
> + return IRQ_HANDLED;
> + } else if (ir == 0x10) {
> + return IRQ_NONE;
> + } else {
> + return IRQ_NONE;
> + }
> +}
> +
> +static
> +irqreturn_t softing_irq_old(int irq, void *dev_id)
> +{
> + struct softing *card = (struct softing *)dev_id;
> + unsigned char irq_host;
> + irq_host = card->dpram.irq->to_host;
> + /* make sure we have a copy, before clearing the variable in DPRAM */
> + rmb();
> + card->dpram.irq->to_host = 0;
> + /* make sure we cleared it */
> + wmb();
> + if (card->dpram.rx->rd == 0xffff) {
> + dev_alert(&card->pdev->dev, "I think the card is gone\n");
> + return IRQ_NONE;
> + }
> + tasklet_schedule(&card->irq.bh);
> + return IRQ_HANDLED;
> +}
> +
> +/*
> + * netdev/candev inter-operability
> + */
> +static int softing_netdev_open(struct net_device *ndev)
> +{
> + int ret;
> +
> + /* check or determine and set bittime */
> + ret = open_candev(ndev);
> + if (ret)
> + goto failed;
> + ret = softing_startstop(ndev, 1);
> + if (ret)
> + goto failed;
> + return 0;
> +failed:
> + return ret;
> +}
> +
> +static int softing_netdev_stop(struct net_device *ndev)
> +{
> + int ret;
> +
> + netif_stop_queue(ndev);
> +
> + /* softing cycle does close_candev() */
> + ret = softing_startstop(ndev, 0);
> + return ret;
> +}
> +
> +static int softing_candev_set_mode(struct net_device *ndev, enum can_mode mode)
> +{
> + int ret;
> +
> + switch (mode) {
> + case CAN_MODE_START:
> + /* softing cycle does close_candev() */
> + ret = softing_startstop(ndev, 1);
> + return ret;
> + case CAN_MODE_STOP:
> + case CAN_MODE_SLEEP:
> + return -EOPNOTSUPP;
> + }
> + return 0;
> +}
> +
> +/*
> + * Softing device management helpers
> + */
> +int softing_enable_irq(struct softing *card, int enable)
> +{
> + int ret;
> + if (!enable) {
> + if (card->irq.requested && card->irq.nr) {
> + free_irq(card->irq.nr, card);
> + card->irq.requested = 0;
> + }
> + return 0;
> + }
> + if (!card->irq.requested && (card->irq.nr)) {
> + ret = request_irq(card->irq.nr,
> + (card->pdat->generation >= 2)
> + ? softing_irq_new : softing_irq_old,
> + IRQF_SHARED, dev_name(&card->pdev->dev), card);
> + if (ret) {
> + dev_alert(&card->pdev->dev, "%s, request_irq(%u) failed\n",
> + card->pdat->name, card->irq.nr);
> + return ret;
> + }
> + card->irq.requested = 1;
> + }
> + return 0;
> +}
> +
> +static void softing_card_shutdown(struct softing *card)
> +{
> + int fw_up = 0;
> + dev_dbg(&card->pdev->dev, "%s()\n", __func__);
> + if (mutex_lock_interruptible(&card->fw.lock))
> + /* return -ERESTARTSYS*/;
> + fw_up = card->fw.up;
> + card->fw.up = 0;
> +
> + if (card->irq.requested && card->irq.nr) {
> + free_irq(card->irq.nr, card);
> + card->irq.requested = 0;
> + }
> + if (fw_up) {
> + if (card->pdat->enable_irq)
> + card->pdat->enable_irq(card->pdev, 0);
> + softing_set_reset_dpram(card);
> + if (card->pdat->reset)
> + card->pdat->reset(card->pdev, 1);
> + }
> + mutex_unlock(&card->fw.lock);
> + tasklet_kill(&card->irq.bh);
> +}
> +
> +static int softing_card_boot(struct softing *card)
> +{
> + unsigned char *lp;
> + static const unsigned char stream[] = {
> + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, };
> + unsigned char back[sizeof(stream)];
> + dev_dbg(&card->pdev->dev, "%s()\n", __func__);
> +
> + if (mutex_lock_interruptible(&card->fw.lock))
> + return -ERESTARTSYS;
> + if (card->fw.up) {
> + mutex_unlock(&card->fw.lock);
> + return 0;
> + }
> + /* reset board */
> + if (card->pdat->enable_irq)
> + card->pdat->enable_irq(card->pdev, 1);
> + /* boot card */
> + softing_set_reset_dpram(card);
> + if (card->pdat->reset)
> + card->pdat->reset(card->pdev, 1);
> + for (lp = card->dpram.virt; &lp[sizeof(stream)] <= card->dpram.end;
> + lp += sizeof(stream)) {
> +
> + memcpy_toio(lp, stream, sizeof(stream));
> + /* flush IO cache */
> + mb();
> + memcpy_fromio(back, lp, sizeof(stream));
> +
> + if (!memcmp(back, stream, sizeof(stream)))
> + continue;
> + /* memory is not equal */
> + dev_alert(&card->pdev->dev, "write to dpram failed at 0x%04lx\n",
> + (unsigned long)(lp - card->dpram.virt));
> + goto open_failed;
> + }
> + wmb();
> + /*load boot firmware */
> + if (softing_load_fw(card->pdat->boot.fw, card, card->dpram.virt,
> + card->dpram.size,
> + card->pdat->boot.offs -
> + card->pdat->boot.addr))
> + goto open_failed;
> + /*load load firmware */
> + if (softing_load_fw(card->pdat->load.fw, card, card->dpram.virt,
> + card->dpram.size,
> + card->pdat->load.offs -
> + card->pdat->load.addr))
> + goto open_failed;
> +
> + if (card->pdat->reset)
> + card->pdat->reset(card->pdev, 0);
> + softing_clr_reset_dpram(card);
> + if (softing_bootloader_command(card, 0, "card boot"))
> + goto open_failed;
> + if (softing_load_app_fw(card->pdat->app.fw, card))
> + goto open_failed;
> + /*reset chip */
> + card->dpram.info->reset_rcv_fifo = 0;
> + card->dpram.info->reset = 1;
> + /*sync */
> + if (softing_fct_cmd(card, 99, 0x55, "sync-a"))
> + goto open_failed;
> + if (softing_fct_cmd(card, 99, 0xaa, "sync-a"))
> + goto open_failed;
> + /*reset chip */
> + if (softing_fct_cmd(card, 0, 0, "reset_chip"))
> + goto open_failed;
> + /*get_serial */
> + if (softing_fct_cmd(card, 43, 0, "get_serial_number"))
> + goto open_failed;
> + card->id.serial =
> + (u16) card->dpram.fct->param[1] +
> + (((u16) card->dpram.fct->param[2]) << 16);
> + /*get_version */
> + if (softing_fct_cmd(card, 12, 0, "get_version"))
> + goto open_failed;
> + card->id.fw = (u16) card->dpram.fct->param[1];
> + card->id.hw = (u16) card->dpram.fct->param[2];
> + card->id.lic = (u16) card->dpram.fct->param[3];
> + card->id.chip[0] = (u16) card->dpram.fct->param[4];
> + card->id.chip[1] = (u16) card->dpram.fct->param[5];
> +
> + dev_info(&card->pdev->dev, "card booted, type %s, "
> + "serial %u, fw %u, hw %u, lic %u, chip (%u,%u)\n",
> + card->pdat->name, card->id.serial, card->id.fw, card->id.hw,
> + card->id.lic, card->id.chip[0], card->id.chip[1]);
> +
> + card->fw.up = 1;
> + mutex_unlock(&card->fw.lock);
> + return 0;
> +open_failed:
> + card->fw.up = 0;
> + if (card->pdat->enable_irq)
> + card->pdat->enable_irq(card->pdev, 0);
> + softing_set_reset_dpram(card);
> + if (card->pdat->reset)
> + card->pdat->reset(card->pdev, 1);
> + mutex_unlock(&card->fw.lock);
> + return -EIO;
> +}
> +
> +/*
> + * netdev sysfs
> + */
> +static ssize_t show_channel(struct device *dev
> + , struct device_attribute *attr, char *buf)
> +{
> + struct net_device *ndev = to_net_dev(dev);
> + struct softing_priv *priv = netdev2softing(ndev);
> + return sprintf(buf, "%i\n", priv->index);
> +}
> +
> +static ssize_t show_chip(struct device *dev
> + , struct device_attribute *attr, char *buf)
> +{
> + struct net_device *ndev = to_net_dev(dev);
> + struct softing_priv *priv = netdev2softing(ndev);
> + return sprintf(buf, "%i\n", priv->chip);
> +}
> +
> +static ssize_t show_output(struct device *dev
> + , struct device_attribute *attr, char *buf)
> +{
> + struct net_device *ndev = to_net_dev(dev);
> + struct softing_priv *priv = netdev2softing(ndev);
> + return sprintf(buf, "0x%02x\n", priv->output);
> +}
> +
> +static ssize_t store_output(struct device *dev
> + , struct device_attribute *attr
> + , const char *buf, size_t count)
> +{
> + struct net_device *ndev = to_net_dev(dev);
> + struct softing_priv *priv = netdev2softing(ndev);
> + struct softing *card = priv->card;
> + unsigned long val;
> + int ret;
> +
> + ret = strict_strtoul(buf, 0, &val);
> + if (ret < 0)
> + return ret;
> + val &= 0xFF;
> +
> + ret = mutex_lock_interruptible(&card->fw.lock);
> + if (ret)
> + return -ERESTARTSYS;
> + if (netif_running(ndev)) {
> + mutex_unlock(&card->fw.lock);
> + return -EBUSY;
> + }
> + priv->output = val;
> + mutex_unlock(&card->fw.lock);
> + return count;
> +}
> +
> +static const DEVICE_ATTR(channel, S_IRUGO, show_channel, 0);
> +static const DEVICE_ATTR(chip, S_IRUGO, show_chip, 0);
> +static const DEVICE_ATTR(output, S_IRUGO | S_IWUSR, show_output, store_output);
> +
> +static const struct attribute *const netdev_sysfs_attrs[] = {
> + &dev_attr_channel.attr,
> + &dev_attr_chip.attr,
> + &dev_attr_output.attr,
> + 0,
> +};
> +static const struct attribute_group netdev_sysfs_group = {
> + .name = 0,
> + .attrs = (struct attribute **)netdev_sysfs_attrs,
> +};
> +
> +static const struct net_device_ops softing_netdev_ops = {
> + .ndo_open = softing_netdev_open,
> + .ndo_stop = softing_netdev_stop,
> + .ndo_start_xmit = softing_netdev_start_xmit,
> +};
> +
> +static const struct can_bittiming_const softing_btr_const = {
> + .tseg1_min = 1,
> + .tseg1_max = 16,
> + .tseg2_min = 1,
> + .tseg2_max = 8,
> + .sjw_max = 4, /* overruled */
> + .brp_min = 1,
> + .brp_max = 32, /* overruled */
> + .brp_inc = 1,
> +};
> +
> +
> +static struct net_device *softing_netdev_create(
> + struct softing *card, u16 chip_id)
> +{
> + struct net_device *netdev;
> + struct softing_priv *priv;
> +
> + netdev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
> + if (!netdev) {
> + dev_alert(&card->pdev->dev, "alloc_candev failed\n");
> + return 0;
> + }
> + priv = netdev_priv(netdev);
> + priv->netdev = netdev;
> + priv->card = card;
> + memcpy(&priv->btr_const, &softing_btr_const, sizeof(priv->btr_const));
> + priv->btr_const.brp_max = card->pdat->max_brp;
> + priv->btr_const.sjw_max = card->pdat->max_sjw;
> + priv->can.bittiming_const = &priv->btr_const;
> + priv->can.clock.freq = 8000000;
> + priv->chip = chip_id;
> + priv->output = softing_default_output(netdev);
> + SET_NETDEV_DEV(netdev, &card->pdev->dev);
> +
> + netdev->flags |= IFF_ECHO;
> + netdev->netdev_ops = &softing_netdev_ops;
> + priv->can.do_set_mode = softing_candev_set_mode;
> + priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
> + CAN_CTRLMODE_BERR_REPORTING;
> +
> + return netdev;
> +}
> +
> +static int softing_netdev_register(struct net_device *netdev)
> +{
> + int ret;
> +
> + /*
> + * provide bus-specific sysfs attributes _during_ the uevent
> + */
> + netdev->sysfs_groups[0] = &netdev_sysfs_group;
> + ret = register_candev(netdev);
> + if (ret) {
> + dev_alert(&netdev->dev, "register failed\n");
> + return ret;
> + }
> + return 0;
> +}
> +
> +static void softing_netdev_cleanup(struct net_device *netdev)
> +{
> + unregister_candev(netdev);
> + free_candev(netdev);
> +}
> +
> +/*
> + * sysfs for Platform device
> + */
> +#define DEV_ATTR_RO(name, member) \
> +static ssize_t show_##name(struct device *dev, \
> + struct device_attribute *attr, char *buf) \
> +{ \
> + struct softing *card = platform_get_drvdata(to_platform_device(dev)); \
> + return sprintf(buf, "%u\n", card->member); \
> +} \
> +static DEVICE_ATTR(name, 0444, show_##name, 0)
> +
> +DEV_ATTR_RO(serial , id.serial);
> +DEV_ATTR_RO(firmware , id.fw);
> +DEV_ATTR_RO(hardware , id.hw);
> +DEV_ATTR_RO(license , id.lic);
> +DEV_ATTR_RO(freq , id.freq);
> +DEV_ATTR_RO(txpending , tx.pending);
> +
> +static struct attribute *softing_pdev_attrs[] = {
> + &dev_attr_serial.attr,
> + &dev_attr_firmware.attr,
> + &dev_attr_hardware.attr,
> + &dev_attr_license.attr,
> + &dev_attr_freq.attr,
> + &dev_attr_txpending.attr,
> + 0,
> +};
> +
> +static const struct attribute_group softing_pdev_group = {
> + .attrs = softing_pdev_attrs,
> +};
> +
> +/*
> + * platform driver
> + */
> +static int softing_pdev_remove(struct platform_device *pdev)
> +{
> + struct softing *card = platform_get_drvdata(pdev);
> + int j;
> +
> + /*first, disable card*/
> + softing_card_shutdown(card);
> + tasklet_kill(&card->irq.bh);
> +
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + if (!card->net[j])
> + continue;
> + softing_netdev_cleanup(card->net[j]);
> + card->net[j] = 0;
> + }
> + sysfs_remove_group(&pdev->dev.kobj, &softing_pdev_group);
> +
> + iounmap(card->dpram.virt);
> + kfree(card);
> + return 0;
> +}
> +
> +static int softing_pdev_probe(struct platform_device *pdev)
> +{
> + const struct softing_platform_data *pdat = pdev->dev.platform_data;
> + struct softing *card;
> + struct net_device *netdev;
> + struct softing_priv *priv;
> + struct resource *pres;
> + int ret;
> + int j;
> +
> + if (!pdat) {
> + dev_warn(&pdev->dev, "no platform data\n");
> + return -EINVAL;
> + }
> + if (pdat->nbus > ARRAY_SIZE(card->net)) {
> + dev_warn(&pdev->dev, "%u nets??\n", pdat->nbus);
> + return -EINVAL;
> + }
> +
> + card = kzalloc(sizeof(*card), GFP_KERNEL);
> + if (!card)
> + return -ENOMEM;
> + card->pdat = pdat;
> + card->pdev = pdev;
> + platform_set_drvdata(pdev, card);
> + /* try_module_get(THIS_MODULE); */
> + mutex_init(&card->fw.lock);
> + spin_lock_init(&card->spin);
> + tasklet_init(&card->irq.bh, softing_handler, (unsigned long)card);
> +
> + ret = -EINVAL;
> + pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!pres)
> + goto ioremap_failed;
^^^^^^^
it platform_get_resource that faile
> + card->dpram.phys = pres->start;
> + card->dpram.size = pres->end - pres->start + 1;
> + card->dpram.virt = ioremap_nocache(card->dpram.phys, card->dpram.size);
> + if (!card->dpram.virt) {
> + dev_alert(&card->pdev->dev, "dpram ioremap failed\n");
> + goto ioremap_failed;
> + }
> + card->dpram.end = &card->dpram.virt[card->dpram.size];
> + /*initialize_board */
> + card->dpram.rx = (struct softing_rx *)&card->dpram.virt[0x0000];
> + card->dpram.tx = (struct softing_tx *)&card->dpram.virt[0x0400];
> + card->dpram.fct = (struct softing_fct *)&card->dpram.virt[0x0300];
> + card->dpram.info = (struct softing_info *)&card->dpram.virt[0x0330];
> + card->dpram.command = (unsigned short *)&card->dpram.virt[0x07e0];
> + card->dpram.receipt = (unsigned short *)&card->dpram.virt[0x07f0];
> + card->dpram.irq = (struct softing_irq *)&card->dpram.virt[0x07fe];
> +
> + pres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> + if (pres)
> + card->irq.nr = pres->start;
> +
> + /*reset card */
> + ret = -EIO;
> + if (softing_card_boot(card)) {
> + dev_alert(&pdev->dev, "failed to boot\n");
> + goto boot_failed;
> + }
> +
> + /*only now, the chip's are known */
> + card->id.freq = card->pdat->freq * 1000000UL;
> +
> + ret = sysfs_create_group(&pdev->dev.kobj, &softing_pdev_group);
> + if (ret < 0) {
> + dev_alert(&card->pdev->dev, "sysfs failed\n");
> + goto sysfs_failed;
> + }
> +
> + ret = -ENOMEM;
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + card->net[j] = netdev =
> + softing_netdev_create(card, card->id.chip[j]);
> + if (!netdev) {
> + dev_alert(&pdev->dev, "failed to make can[%i]", j);
> + goto netdev_failed;
> + }
> + priv = netdev_priv(card->net[j]);
> + priv->index = j;
> + ret = softing_netdev_register(netdev);
> + if (ret) {
> + free_candev(netdev);
> + card->net[j] = 0;
> + dev_alert(&card->pdev->dev,
> + "failed to register can[%i]\n", j);
> + goto netdev_failed;
> + }
> + }
> + dev_info(&card->pdev->dev, "card initialised\n");
> + return 0;
> +
> +netdev_failed:
> + for (j = 0; j < ARRAY_SIZE(card->net); ++j) {
> + if (!card->net[j])
> + continue;
> + softing_netdev_cleanup(card->net[j]);
> + }
> + sysfs_remove_group(&pdev->dev.kobj, &softing_pdev_group);
> +sysfs_failed:
> + softing_card_shutdown(card);
> +boot_failed:
> + iounmap(card->dpram.virt);
> +ioremap_failed:
> + tasklet_kill(&card->irq.bh);
> + kfree(card);
> + return ret;
> +}
> +
> +static struct platform_driver softing_driver = {
> + .driver = {
> + .name = "softing",
> + .owner = THIS_MODULE,
> + },
> + .probe = softing_pdev_probe,
> + .remove = softing_pdev_remove,
> +};
> +
> +MODULE_ALIAS("platform:softing");
> +
> +static int __init softing_start(void)
> +{
> + return platform_driver_register(&softing_driver);
> +}
> +
> +static void __exit softing_stop(void)
> +{
> + platform_driver_unregister(&softing_driver);
> +}
> +
> +module_init(softing_start);
> +module_exit(softing_stop);
> +
> +MODULE_DESCRIPTION("socketcan softing driver");
> +MODULE_AUTHOR("Kurt Van Dijck <kurt.van.dijck-/BeEPy95v10@public.gmane.org>");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/net/can/softing/softing_platform.h b/drivers/net/can/softing/softing_platform.h
> new file mode 100644
> index 0000000..9ff69a1
> --- /dev/null
> +++ b/drivers/net/can/softing/softing_platform.h
> @@ -0,0 +1,38 @@
> +
> +#include <linux/platform_device.h>
> +
> +#ifndef _SOFTING_DEVICE_H_
> +#define _SOFTING_DEVICE_H_
> +
> +/* softing firmware directory prefix */
> +#define fw_dir "softing-4.6/"
> +
> +struct softing_platform_data {
> + unsigned int manf;
> + unsigned int prod;
> + /* generation
> + * 1st with NEC or SJA1000
> + * 8bit, exclusive interrupt, ...
> + * 2nd only SJA11000
> + * 16bit, shared interrupt
> + */
> + int generation;
> + int nbus; /* # busses on device */
> + unsigned int freq; /* crystal in MHz */
> + unsigned int max_brp;
> + unsigned int max_sjw;
> + unsigned long dpram_size;
> + char name[32];
> + struct {
> + unsigned long offs;
> + unsigned long addr;
> + const char *fw;
> + } boot, load, app;
> + /* reset() function, bring pdev in or out of reset, depending on
> + value */
> + int (*reset)(struct platform_device *pdev, int value);
> + int (*enable_irq)(struct platform_device *pdev, int value);
> +};
> +
> +#endif
> +
> _______________________________________________
> Socketcan-core mailing list
> Socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org
> https://lists.berlios.de/mailman/listinfo/socketcan-core
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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_______________________________________________
Socketcan-core mailing list
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https://lists.berlios.de/mailman/listinfo/socketcan-core
^ permalink raw reply
* Re: [PATCH net-2.6] net_sched: always clone skbs
From: jamal @ 2010-12-23 13:35 UTC (permalink / raw)
To: Jarek Poplawski
Cc: Changli Gao, Eric Dumazet, David S. Miller, netdev,
Pawel Staszewski
In-Reply-To: <20101221223704.GA1979@del.dom.local>
On Tue, 2010-12-21 at 23:37 +0100, Jarek Poplawski wrote:
> Actually, when dumb isn't a good principle? ;->
>
> Speaking about wrong things like optimizing this 1st commandment: it
> seems, if we're stealing not shared skb it's not unreasonable to tell
> others not to touch it anymore, and skip kfree_skb() in handle_ing(),
> unless I miss something?
I dont know how much cycles it will save you vs the code you add
but it is not unreasonable. Of course it would mean we are moving
beyond KISSes[1] now Jarek;->
> > In order to make my trick work. We need to assure dev_queue_xmit() and
> > dev_hard_start_xmit() accept shared skbs. As Eric pointed, pktgen also
> > need dev->netdev_ops->ndo_start_xmit() accept shared skbs. We need to
> > fix every ndo_start_xmit() one by one, then dev_hard_start_xmit(), and
> > when dev_queue_xmit() is also fixed, my trick can be added back.
> > :)
>
> I'm not sure pktgen is right - even if it's safe in its case, it seems
> to break some older rules, and drivers should really own the things.
> So it needs reviewing first.
The idea we always try to keep is that the caller is responsible for the
fate of the skb it sent. The callee will do things like make a copy or
clone if it needed to make changes or keep the skb. Same should be
expected of a driver.
cheers,
jamal
[1] Jarek - so you dont misunderstand this as an overture - it means
Keep It Simple Silly (or the principle of dumb we talked about) ;->
^ permalink raw reply
* Re: [PATCH 5/5 v4] net: add old_queue_mapping into skb->cb
From: jamal @ 2010-12-23 13:21 UTC (permalink / raw)
To: Eric Dumazet
Cc: Changli Gao, David S. Miller, Stephen Hemminger, Tom Herbert,
Jiri Pirko, netdev, netem
In-Reply-To: <1292945075.2720.32.camel@edumazet-laptop>
On Tue, 2010-12-21 at 16:24 +0100, Eric Dumazet wrote:
>
> Do we really want a multi queue ifb at all ?
>
> Why not use percpu data and LLTX, like we did for other virtual devices
> (loopback, tunnels, vlans, ...)
>
> I guess most ifb uses need to finaly deliver packets in a monoqueue
> anyway, optimizing ifb might raise lock contention on this resource.
I guess once you start having hardware that is multiqueue on the ingress
side at least then something per cpu is needed on ifb. But i agree that
the optimizations may end up harming the simplicity that ifb intended.
It is already jumping a lot of hoops to work around things as is.
> See what we did in commit 79640a4ca6955e3e (net: add additional lock to
> qdisc to increase throughput) : Adding one spinlock actually helped a
> lot ;)
Yes, that was fascinating stuff;-> I am still scratching my head and
continuing to itch on when i can get more time to look closely with some
testing. But i dont see the connection with what Changli is attempting
with multiq ifb - what do you have in mind.
cheers,
jamal
^ permalink raw reply
* Re: [PATCH 5/5 v4] net: add old_queue_mapping into skb->cb
From: jamal @ 2010-12-23 13:00 UTC (permalink / raw)
To: Changli Gao
Cc: David S. Miller, Stephen Hemminger, Eric Dumazet, Tom Herbert,
Jiri Pirko, netdev, netem
In-Reply-To: <AANLkTimqemuhxCKq-PJu+FD-MDgKaHnYKnP_2ch30wxE@mail.gmail.com>
On Tue, 2010-12-21 at 22:03 +0800, Changli Gao wrote:
> When I tested it, my OS got frozen.
I will look into it the next opportunity i get. The example i showed
is on egress btw. A ping from outside that matches the filter
will be a good test.
> Currently, you can only change the rx queue mapping, because for tx,
> dev_pick_tx() doesn't use skb->queue_mapping to choose tx queue.
If skbedit is on egress, it will happen after (and override whatever
dev_pick_tx() chose), no? Thats the whole point for skbedits queuemap
editing.
> However, I don't think change the rx queue mapping is a good idea.
I agree for that as a default policy. But it is
policy that skbedit can and should be able to override.
> When the skbs returned from ifb enter netif_receive_skb() again,
> get_rps_cpu() may warn about the wrong rx queue, and my this patch is
> used to solve this problem. Even though the rx queue is legal, a
> different rps_cpus settings will be used, and the skbs may be
> redirected to different CPUs. Is it expected?
I am not sure without analyzing what performance impact would be, i.e i
think that the only reason i wouldnt do it is because it may have crazy
effect on performance but:
If i wanted to override the choice made by rps through some policy, why
shouldnt i be able to do it? Same thing if i wanted to bypass rps. tc
level seems appropriate.
I may be misreading the code: Quick glance at the code indicates users
have no choice on ingress: rps happens first then we can do tc level -
so it doesnt matter what changes we make to the queue map it will not
take effect in any case. Am i mistaken?
cheers,
jamal
^ permalink raw reply
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