* [PATCH net-next-2.6 v3 0/2] can: add driver for Softing card
From: Kurt Van Dijck @ 2011-01-11 14:30 UTC (permalink / raw)
To: netdev-u79uwXL29TY76Z2rM5mHXA,
socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
linux-pcmcia-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This series will add a driver for Softing PCMCIA CAN card.
This core CAN networking code exists for a few years in the
socketCAN repository.
The updates since the latest socketCAN version:
* PCMCIA interfacing changed
* seperation between the two drivers via a platform:softing device
* added conditional bus-error reporting
About the platform_device ...
Softing Gmbh has PCMCIA & PCI cards. Both share the same
Dual Port RAM (DPRAM) interface. Therefore, the driver is split in 2 stages:
[1/2] softing.ko: Generic platform bus device driver
It expects a platform:softing device with an IO range that contains
the DPRAM, and an IRQ line.
[2/2] softing_cs.ko: PCMCIA driver
This driver will create a platform:softing device on top of the
pcmcia device.
The 2 drivers are not linked in a way that softing.ko depends
on softing_cs.ko or vice versa. The reason for doing so is that
the DPRAM interface takes quite some code, and building it directly
on the PCMCIA or PCI device was difficult to follow.
The present design eliminates the need for exotic sysfs API's since
all sysfs attributes know they are attached to a platform_device.
Differences since v1 of this series:
* whitespace issues
* use of time_after() to measure elapsed time.
* don't copy data for RTR frames (see commit since v1)
* use usleep_range(), not schedule().
* threaded irq
* fix iomem access (verify with sparse)
* totally 'endian-safe'
* drop error frame detection again. It's not right that when
bus 1 enables error frames, bus 2 would get error frames too.
* drop the Kconfig dependency between softingcs.ko & softing.ko
Differences since v2 of this series:
* Even more whitespace issues
* Let softing_cs.ko depend on softing.ko in Kconfig. A real
user will need them both
* Normalize all frequencies in Hz.
* Proper return codes from firmware communication functions.
* Drop some alignments
* Don't touch byte counters on RTR frames
* Fix bus-error-states
* Less obscure use of bitmasks
* use of __devinit/__devexit
...
Kurt
^ permalink raw reply
* Re: panic in tg3 driver
From: Stephen Clark @ 2011-01-11 14:10 UTC (permalink / raw)
To: Matt Carlson; +Cc: Linux Kernel Network Developers, Michael Chan
In-Reply-To: <20110111020055.GA25351@mcarlson.broadcom.com>
On 01/10/2011 09:00 PM, Matt Carlson wrote:
> On Mon, Jan 10, 2011 at 12:04:34PM -0800, Stephen Clark wrote:
>
>> On 01/10/2011 02:22 PM, Matt Carlson wrote:
>>
>>> On Sun, Jan 09, 2011 at 02:30:50PM -0800, Stephen Clark wrote:
>>>
>>>
>>>> On 01/04/2011 09:54 AM, Stephen Clark wrote:
>>>>
>>>>
>>>>> Hello,
>>>>>
>>>>>
>>>>> The hardware is an Acrosser AR-M0898B micro box.
>>>>> lspci
>>>>> 00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
>>>>> Host Bridge
>>>>> 00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
>>>>> Host Bridge
>>>>> 00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
>>>>> Host Bridge
>>>>> 00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge
>>>>> 00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
>>>>> Host Bridge
>>>>> 00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro
>>>>> Host Bridge
>>>>> 00:01.0 PCI bridge: VIA Technologies, Inc. VT8237/VX700 PCI Bridge
>>>>> 00:0f.0 IDE interface: VIA Technologies, Inc. VT8251 Serial ATA
>>>>> Controller (rev
>>>>> 20)
>>>>> 00:0f.1 IDE interface: VIA Technologies, Inc.
>>>>> VT82C586A/B/VT82C686/A/B/VT823x/A/
>>>>> C PIPC Bus Master IDE (rev 07)
>>>>> 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
>>>>> Controller
>>>>> (rev 91)
>>>>> 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
>>>>> Controller
>>>>> (rev 91)
>>>>> 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
>>>>> Controller
>>>>> (rev 91)
>>>>> 00:10.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1
>>>>> Controller
>>>>> (rev 91)
>>>>> 00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 90)
>>>>> 00:11.0 ISA bridge: VIA Technologies, Inc. VT8251 PCI to ISA Bridge
>>>>> 00:11.7 Host bridge: VIA Technologies, Inc. VT8251 Ultra VLINK Controller
>>>>> 00:13.0 Host bridge: VIA Technologies, Inc. VT8251 Host Bridge
>>>>> 00:13.1 PCI bridge: VIA Technologies, Inc. VT8251 PCI to PCI Bridge
>>>>> 02:08.0 Ethernet controller: Broadcom Corporation BCM4401 100Base-T
>>>>> (rev 02)
>>>>> 02:09.0 Ethernet controller: Broadcom Corporation BCM4401 100Base-T
>>>>> (rev 02)
>>>>> 80:00.0 PCI bridge: VIA Technologies, Inc. VT8251 PCIE Root Port
>>>>> 80:00.1 PCI bridge: VIA Technologies, Inc. VT8251 PCIE Root Port
>>>>> 81:00.0 Ethernet controller: Broadcom Corporation NetLink BCM5906M
>>>>> Fast Ethernet
>>>>> PCI Express (rev 02)
>>>>> 82:00.0 Ethernet controller: Broadcom Corporation NetLink BCM5906M
>>>>> Fast Ethernet
>>>>> PCI Express (rev 02)
>>>>>
>>>>> Kernel 2.6.36-2.el5.elrepo on an i686
>>>>>
>>>>> When I try to ifconfig either of the BCM5906M ports the system panics.
>>>>>
>>>>> Ideas, fixes ?
>>>>>
>>>>> [root@Z1010 ~]# modprobe tg3
>>>>> [root@Z1010 ~]# ifconfig eth2 2.2.2.2/24
>>>>> ------------[ cut here ]------------
>>>>> kernel BUG at drivers/net/tg3.c:4365!
>>>>> invalid opcode: 0000 [#1] PREEMPT SMP
>>>>> last sysfs file: /sys/class/net/eth3/address
>>>>> Modules linked in: tg3 xt_tcpudp ipt_LOG xt_limit xt_state
>>>>> iptable_mangle af_ke]
>>>>>
>>>>> Pid: 20303, comm: kworker/0:2 Not tainted 2.6.36-2.el5.elrepo #1
>>>>> CN700-8251/
>>>>> EIP: 0060:[<e1c62f19>] EFLAGS: 00010202 CPU: 0
>>>>> EIP is at tg3_tx_recover+0x1e/0x53 [tg3]
>>>>> EAX: deece4c0 EBX: dfa9c000 ECX: deece4c0 EDX: ffffffff
>>>>> ESI: deece4c0 EDI: deece500 EBP: c1801f38 ESP: c1801f30
>>>>> DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
>>>>> Process kworker/0:2 (pid: 20303, ti=c1801000 task=df0105d0
>>>>> task.ti=dee62000)
>>>>> Stack:
>>>>> dfa9c000 00000000 c1801f6c e1c630be c1801f6c deece4c0 00000840 00000000
>>>>> <0> df251cc0 00000005 00000000 df979800 deece500 deece4c0 00000040
>>>>> c1801f94
>>>>> <0> e1c661e5 00000000 00000040 c1801f88 e09df1d2 00000000 deece500
>>>>> dfab4000
>>>>> Call Trace:
>>>>> [<e1c630be>] ? tg3_tx+0x157/0x1a2 [tg3]
>>>>> [<e1c661e5>] ? tg3_poll_work+0x2b/0x10b [tg3]
>>>>> [<e09df1d2>] ? ssb_write32+0x11/0x14 [b44]
>>>>> [<e1c662f9>] ? tg3_poll+0x34/0x9a [tg3]
>>>>> [<c0674058>] ? net_rx_action+0x7e/0x11c
>>>>> [<c04409c9>] ? __do_softirq+0x85/0x10c
>>>>> [<c0440944>] ? __do_softirq+0x0/0x10c
>>>>> <IRQ>
>>>>> [<c04404ef>] ? _local_bh_enable_ip+0x68/0x87
>>>>> [<c044051b>] ? local_bh_enable_ip+0xd/0xf
>>>>> [<c046593b>] ? __raw_spin_unlock_bh+0x1c/0x1e
>>>>> [<c06fa4f2>] ? _raw_spin_unlock_bh+0xd/0xf
>>>>> [<e1c6281f>] ? spin_unlock_bh+0xd/0xf [tg3]
>>>>> [<e1c62cbe>] ? tg3_full_unlock+0x10/0x12 [tg3]
>>>>> [<e1c664c7>] ? tg3_reset_task+0xd7/0xe3 [tg3]
>>>>> [<c044ec37>] ? process_one_work+0x10b/0x1bc
>>>>> [<e1c663f0>] ? tg3_reset_task+0x0/0xe3 [tg3]
>>>>> [<c044fd41>] ? worker_thread+0x77/0xf9
>>>>> [<c0453048>] ? kthread+0x60/0x65
>>>>> [<c044fcca>] ? worker_thread+0x0/0xf9
>>>>> [<c0452fe8>] ? kthread+0x0/0x65
>>>>> [<c040337e>] ? kernel_thread_helper+0x6/0x10
>>>>> Code: f0 e8 88 ff ff ff 8d 65 f8 5b 5e 5d c3 55 89 e5 56 53 0f 1f 44
>>>>> 00 00 f6 8
>>>>> EIP: [<e1c62f19>] tg3_tx_recover+0x1e/0x53 [tg3] SS:ESP 0068:c1801f30
>>>>> ---[ end trace 82381e9b93e397ad ]---
>>>>> Kernel panic - not syncing: Fatal exception in interrupt
>>>>> Pid: 20303, comm: kworker/0:2 Tainted: G D
>>>>> 2.6.36-2.el5.elrepo #1
>>>>> Call Trace:
>>>>> [<c043b3cd>] panic+0x62/0x15d
>>>>> [<c06fb7d1>] oops_end+0x99/0xa8
>>>>> [<e1c62f19>] ? tg3_tx_recover+0x1e/0x53 [tg3]
>>>>> [<c0405a62>] die+0x58/0x5e
>>>>>
>>>>> Thanks,
>>>>> Steve
>>>>>
>>>>>
>>>>>
>>>> Additonal info I compiled the latest kernel 2.6.37-rc8+ and still have the problem.
>>>> Also boot with noapic I see this in the dmesg log and interrupts are increasing
>>>> like crazy:
>>>> tg3.c:v3.115 (October 14, 2010)
>>>> tg3 0000:81:00.0: PCI INT A -> Link[LNKA] -> GSI 10 (level, low) -> IRQ 10
>>>> tg3 0000:81:00.0: setting latency timer to 64
>>>> tg3 0000:81:00.0: PCI: Disallowing DAC for device
>>>> tg3 0000:81:00.0: eth2: Tigon3 [partno(BCM95906) rev c002] (PCI Express) MAC add
>>>> ress 00:02:b6:36:d1:39
>>>> tg3 0000:81:00.0: eth2: attached PHY is 5906 (10/100Base-TX Ethernet) (WireSpeed
>>>> [0])
>>>> tg3 0000:81:00.0: eth2: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>>>> tg3 0000:81:00.0: eth2: dma_rwctrl[76180000] dma_mask[32-bit]
>>>> tg3 0000:82:00.0: PCI INT A -> Link[LNKA] -> GSI 10 (level, low) -> IRQ 10
>>>> tg3 0000:82:00.0: setting latency timer to 64
>>>> tg3 0000:82:00.0: PCI: Disallowing DAC for device
>>>> tg3 0000:82:00.0: eth3: Tigon3 [partno(BCM95906) rev c002] (PCI Express) MAC add
>>>> ress 00:02:b6:36:d1:3a
>>>> tg3 0000:82:00.0: eth3: attached PHY is 5906 (10/100Base-TX Ethernet) (WireSpeed
>>>> [0])
>>>> tg3 0000:82:00.0: eth3: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>>>> tg3 0000:82:00.0: eth3: dma_rwctrl[76180000] dma_mask[32-bit]
>>>> tg3 0000:81:00.0: irq 40 for MSI/MSI-X
>>>> tg3 0000:81:00.0: eth2: No interrupt was generated using MSI. Switching to INTx
>>>> mode. Please report this failure to the PCI maintainer and include system chipse
>>>> t information
>>>> ADDRCONF(NETDEV_UP): eth2: link is not ready
>>>> [root@Z1010 ~]# cat /proc/interrupts
>>>> CPU0
>>>> 0: 162 XT-PIC-XT-PIC timer
>>>> 1: 2 XT-PIC-XT-PIC i8042
>>>> 2: 0 XT-PIC-XT-PIC cascade
>>>> 3: 1 XT-PIC-XT-PIC
>>>> 4: 4863 XT-PIC-XT-PIC serial
>>>> 6: 2 XT-PIC-XT-PIC floppy
>>>> 7: 5 XT-PIC-XT-PIC ehci_hcd:usb1, uhci_hcd:usb3
>>>> 8: 0 XT-PIC-XT-PIC rtc0
>>>> 9: 0 XT-PIC-XT-PIC acpi
>>>> 10: 2334234 XT-PIC-XT-PIC uhci_hcd:usb2, eth0, eth2
>>>>
>>>> [root@Z1010 ~]# cat /proc/interrupts |grep eth2
>>>> 10: 18388914 XT-PIC-XT-PIC uhci_hcd:usb2, eth0, eth2
>>>> [root@Z1010 ~]# cat /proc/interrupts |grep eth2
>>>> 10: 18901627 XT-PIC-XT-PIC uhci_hcd:usb2, eth0, eth2
>>>>
>>>> --
>>>>
>>>> "They that give up essential liberty to obtain temporary safety,
>>>> deserve neither liberty nor safety." (Ben Franklin)
>>>>
>>>> "The course of history shows that as a government grows, liberty
>>>> decreases." (Thomas Jefferson)
>>>>
>>>>
>>> I think drivers/net/tg3.c:4365 is at the line that reads
>>> "spin_lock(&tp->lock);" in tg3_tx_recover. Can you verify?
>>>
>>>
>>>
>>
>> tg3_readphy(tp, MII_TG3_DSP_RW_PORT,&phy2);
>>
>> in static void tg3_serdes_parallel_detect(struct tg3 *tp)
>>
>> The driver version is:
>> #define DRV_MODULE_NAME "tg3"
>> #define TG3_MAJ_NUM 3
>> #define TG3_MIN_NUM 115
>>
>
> That doesn't look right. The line number I quoted came from the kernel
> panic output from 2.6.36-2.el5.elrepo. I'm guessing you quoted me the
> sources from the tg3.c file in 2.6.37-rc8+. If you don't have the
> 2.6.36-2.el5.elrepo sources readily available, can you give me the line
> the kernel panic specifies from the tg3.c file from your 2.6.37-rc8+
> sources?
>
>
Oops - You are correct. The problem is most of the time I don't get a
panic on the
screen the box simply reboots.
I'll see if I can get the 2.6.36-2 sources - though they are suppose to
be the virgin
kernel.org sources simply recompiled for Centos.
static void tg3_tx_recover(struct tg3 *tp)
{
BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4365: tp->write32_tx_mbox == tg3_write_indirect_mbox);
> It looks like there are a lot of devices on IRQ 10. Does the interrupt
> count drop if you bring down eth0 (which I'm guessing is the b44 device)?
>
This happens when I boot with noapic. Which I only did as a test. With
the noapic option
the system doesn't panic - but gets all these extra interrupts as soon
as I ifconfig one of
the 5906 ports.
> Can you tell me if you saw the following message in the syslogs?
>
> "The system may be re-ordering memory-mapped I/O cycles to the network
> device, attempting to recover. Please report the problem to the driver
> maintainer and include system chipset information."
>
>
Couldn't find this in the messages file.
^ permalink raw reply
* Re: [PATCH] ip: reuse ip_summed of first fragment for all subsequent fragments
From: Timo Juhani Lindfors @ 2011-01-11 13:49 UTC (permalink / raw)
To: David Miller; +Cc: netdev
In-Reply-To: <20101228.134905.183040321.davem@davemloft.net>
David Miller <davem@davemloft.net> writes:
> > - skb->ip_summed = CHECKSUM_NONE;
> > + skb->ip_summed = skb_prev->ip_summed;
> You can't just assign skb_prev->ip_summed here, if it's CHECKSUM_PARTIAL
> then things will go completely wrong. This is especially true since
> we're about to zero out skb->csum.
Thanks, I clearly didn't understand the semantics of ip_summed. For
received packets CHECKSUM_PARTIAL apparently means that the checksum
is calculated by hardware and CHECKSUM_NONE that it is calculated by
software or it is not calculated at all. I guess the ip_summed of a
new fragment is set to CHECKSUM_NONE because hardware can not handle
checksums of fragments?
Anyways, socket option SO_NO_CHECK sets sk->sk_no_check. Could this be
checked before calculating checksums of each fragment? Currently
udp_push_pending_frames checks this but checksums have already been
calculated at that point (and the only job left is to sum the
checksums together). Here's a patch that works for me (=according to
perf time is no longer spent calculating checksums) but probably
should be reviewed carefully:
>From 67fe193db5a2e1a2efaa0fa8e1c1c2554e108b78 Mon Sep 17 00:00:00 2001
From: Timo Juhani Lindfors <timo.lindfors@iki.fi>
Date: Tue, 11 Jan 2011 14:36:23 +0200
Subject: [PATCH] ip: make sure disabling checksums really works
---
net/ipv4/ip_output.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c
index 439d2a3..9bc163a 100644
--- a/net/ipv4/ip_output.c
+++ b/net/ipv4/ip_output.c
@@ -80,6 +80,7 @@
#include <linux/mroute.h>
#include <linux/netlink.h>
#include <linux/tcp.h>
+#include <net/udp.h>
int sysctl_ip_default_ttl __read_mostly = IPDEFTTL;
@@ -1208,7 +1209,7 @@ ssize_t ip_append_page(struct sock *sk, struct page *page,
goto error;
}
- if (skb->ip_summed == CHECKSUM_NONE) {
+ if (skb->ip_summed == CHECKSUM_NONE && sk->sk_no_check != UDP_CSUM_NOXMIT) {
__wsum csum;
csum = csum_page(page, offset, len);
skb->csum = csum_block_add(skb->csum, csum, skb->len);
--
1.7.2.3
^ permalink raw reply related
* Re: [PATCH v4 08/10] ARM: mxs: add ocotp read function
From: Uwe Kleine-König @ 2011-01-11 14:05 UTC (permalink / raw)
To: Sascha Hauer
Cc: Shawn Guo, gerg, B32542, netdev, jamie, baruch, w.sang, r64343,
eric, bryan.wu, jamie, davem, linux-arm-kernel, lw
In-Reply-To: <20110111133137.GS12078@pengutronix.de>
Hello Sascha,
On Tue, Jan 11, 2011 at 02:31:37PM +0100, Sascha Hauer wrote:
> On Thu, Jan 06, 2011 at 03:13:16PM +0800, Shawn Guo wrote:
> > diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
> > new file mode 100644
> > index 0000000..e2d39aa
> > --- /dev/null
> > +++ b/arch/arm/mach-mxs/ocotp.c
> > @@ -0,0 +1,79 @@
> > +/*
> > + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/err.h>
> > +#include <linux/mutex.h>
> > +
> > +#include <mach/mxs.h>
> > +
> > +#define BM_OCOTP_CTRL_BUSY (1 << 8)
> > +#define BM_OCOTP_CTRL_ERROR (1 << 9)
> > +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
> > +
> > +static DEFINE_MUTEX(ocotp_mutex);
> > +
> > +int mxs_read_ocotp(unsigned offset, size_t count, u32 *values)
> > +{
> > + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
> > + int timeout = 0x400;
> > + size_t i;
> > +
> > + mutex_lock(&ocotp_mutex);
> > +
> > + /*
> > + * clk_enable(hbus_clk) for ocotp can be skipped
> > + * as it must be on when system is running.
> > + */
> > +
> > + /* try to clear ERROR bit */
> > + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
>
> This operation does not try to clear the error bit but actually clears
> it...
>
> > +
> > + /* check both BUSY and ERROR cleared */
> > + while ((__raw_readl(ocotp_base) &
> > + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
> > + cpu_relax();
>
> ...which means you do not have to poll the error bit here...
well, I don't know how the hardware works here, but in general the
argument is broken. Registers are not memory, so just because you set a
bit in register space it doesn't mean it is really set when you read
from the same address.
If there is something wrong with the ocotp I'd even expect that clearing
the error bit doesn't work because it doesn't change the general
condition.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH 3/3] can: at91_can: make can_id of mailbox 0 configurable
From: Kurt Van Dijck @ 2011-01-11 13:43 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA, Marc Kleine-Budde
In-Reply-To: <4D2C5B04.4090706-5Yr1BZd7O62+XT7JhA+gdA@public.gmane.org>
On Tue, Jan 11, 2011 at 02:28:36PM +0100, Wolfgang Grandegger wrote:
>
> On 01/11/2011 01:33 PM, Marc Kleine-Budde wrote:
> > On 01/11/2011 01:27 PM, Wolfgang Grandegger wrote:
> >> On 01/11/2011 12:56 PM, Marc Kleine-Budde wrote:
> >>> On 01/11/2011 12:45 PM, Wolfgang Grandegger wrote:
> >>>> On 01/11/2011 11:28 AM, Marc Kleine-Budde wrote:
> >>>>> Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
> >>>>> "AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
> >>>>> 0 may be send under certain conditions (even if disabled or in rx mode).
> >>>>>
> >>>>> The workaround in the errata suggests not to use the mailbox and load it
> >>>>> with a unused identifier.
> >>>>>
> >>>>> This patch implements the second part of the workaround. A sysfs entry
> >>>>> "mb0_id" is introduced. While the interface is down it can be used to
> >>>>> configure the can_id of mailbox 0. The default value id 0x7ff.
> >>>>>
> >>>>> In order to use an extended can_id add the CAN_EFF_FLAG (0x80000000U)
> >>>>> to the can_id. Example:
> >>>>>
> >>>>> - standard id 0x7ff:
> >>>>> echo 0x7ff > /sys/class/net/can0/mb0_id
> >>>>>
> >>>>> - extended if 0x1fffffff:
> >>> ^^
> >>> I've fixed the typo on my git repo. I'll send an updated series later.
> >>>
> >>>>> echo 0x9fffffff > /sys/class/net/can0/mb0_id
> >>>>
> >>>> As this is a device specific property, I think it should go into
> >>>> /sys/class/net/can0/device/.
> >>>
> >>> The attribute goes autoamtically to /sys/class/net/can0 if you add it to
> >>> the driver via:
> >>>
> >>> + dev->sysfs_groups[0] = &at91_sysfs_attr_group;
> >>>
> >>> I've copied this from the janz-ican3 driver[1].
> >>
> >> Oh, I missed that. And also the Softing driver does it that way :-(. The
> >> member has the comment:
> >>
> >> /* space for optional device, statistics, and wireless sysfs groups */
> >> const struct attribute_group *sysfs_groups[4];
> >>
> >> Therefore it seems to be legal to use it for device specific properties.
> >
> > I'm not really happy with these sysfs approach, but it's quick
> > implemented. Is device specific rtnetlink an option here?
>
> That's toooooooo heavy, I think. I personally would just use
> device_create_file for that purpose. But let's keep using sysfs_groups[]
> if nobody else complains.
sysfs_groups[0] has the advantage that it's ready during the uevent
(ie. for use in udev). device_create_file() may get online after the uevent...
Kurt
^ permalink raw reply
* Re: [PATCH v4 08/10] ARM: mxs: add ocotp read function
From: Sascha Hauer @ 2011-01-11 13:31 UTC (permalink / raw)
To: Shawn Guo
Cc: davem, gerg, baruch, eric, bryan.wu, r64343, B32542,
u.kleine-koenig, lw, w.sang, jamie, jamie, netdev,
linux-arm-kernel
In-Reply-To: <1294297998-26930-9-git-send-email-shawn.guo@freescale.com>
On Thu, Jan 06, 2011 at 03:13:16PM +0800, Shawn Guo wrote:
> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
> ---
> Changes for v4:
> - Call cpu_relax() during polling
>
> Changes for v2:
> - Add mutex locking for mxs_read_ocotp()
> - Use type size_t for count and i
> - Add comment for clk_enable/disable skipping
> - Add ERROR bit clearing and polling step
>
> arch/arm/mach-mxs/Makefile | 2 +-
> arch/arm/mach-mxs/include/mach/common.h | 1 +
> arch/arm/mach-mxs/ocotp.c | 79 +++++++++++++++++++++++++++++++
> 3 files changed, 81 insertions(+), 1 deletions(-)
> create mode 100644 arch/arm/mach-mxs/ocotp.c
>
> diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
> index 39d3f9c..f23ebbd 100644
> --- a/arch/arm/mach-mxs/Makefile
> +++ b/arch/arm/mach-mxs/Makefile
> @@ -1,5 +1,5 @@
> # Common support
> -obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
> +obj-y := clock.o devices.o gpio.o icoll.o iomux.o ocotp.o system.o timer.o
>
> obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
> obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
> diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
> index 59133eb..cf02552 100644
> --- a/arch/arm/mach-mxs/include/mach/common.h
> +++ b/arch/arm/mach-mxs/include/mach/common.h
> @@ -13,6 +13,7 @@
>
> struct clk;
>
> +extern int mxs_read_ocotp(int offset, int count, u32 *values);
> extern int mxs_reset_block(void __iomem *);
> extern void mxs_timer_init(struct clk *, int);
>
> diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
> new file mode 100644
> index 0000000..e2d39aa
> --- /dev/null
> +++ b/arch/arm/mach-mxs/ocotp.c
> @@ -0,0 +1,79 @@
> +/*
> + * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/mutex.h>
> +
> +#include <mach/mxs.h>
> +
> +#define BM_OCOTP_CTRL_BUSY (1 << 8)
> +#define BM_OCOTP_CTRL_ERROR (1 << 9)
> +#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
> +
> +static DEFINE_MUTEX(ocotp_mutex);
> +
> +int mxs_read_ocotp(unsigned offset, size_t count, u32 *values)
> +{
> + void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
> + int timeout = 0x400;
> + size_t i;
> +
> + mutex_lock(&ocotp_mutex);
> +
> + /*
> + * clk_enable(hbus_clk) for ocotp can be skipped
> + * as it must be on when system is running.
> + */
> +
> + /* try to clear ERROR bit */
> + __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
This operation does not try to clear the error bit but actually clears
it...
> +
> + /* check both BUSY and ERROR cleared */
> + while ((__raw_readl(ocotp_base) &
> + (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
> + cpu_relax();
...which means you do not have to poll the error bit here...
> +
> + if (unlikely(!timeout))
> + goto error_unlock;
> +
> + /* open OCOTP banks for read */
> + __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
> +
> + /* approximately wait 32 hclk cycles */
> + udelay(1);
> +
> + /* poll BUSY bit becoming cleared */
> + timeout = 0x400;
> + while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
> + cpu_relax();
...which means you can factor out a ocotp_wait_busy function and let the
code speak instead of the comments.
> +
> + if (unlikely(!timeout))
> + goto error_unlock;
> +
> + for (i = 0; i < count; i++, offset += 4)
> + *values++ = __raw_readl(ocotp_base + offset);
The registers in the ocotp are 16 byte aligned. Does it really make
sense to provide a function allowing to read the gaps between the
registers?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH v4 05/10] net/fec: add dual fec support for mx28
From: Greg Ungerer @ 2011-01-11 13:25 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: baruch, B32542, netdev, Sascha Hauer, jamie, w.sang, r64343,
linux-arm-kernel, eric, bryan.wu, jamie, davem, Shawn Guo, lw
In-Reply-To: <20110111130749.GQ24920@pengutronix.de>
Hi Uwe,
On 11/01/11 23:07, Uwe Kleine-König wrote:
> Hi Greg,
>
> On Tue, Jan 11, 2011 at 10:24:12PM +1000, Greg Ungerer wrote:
>> On 11/01/11 20:27, Sascha Hauer wrote:
>>> On Thu, Jan 06, 2011 at 03:13:13PM +0800, Shawn Guo wrote:
>>> This option is used nowhere and should be removed. Certainly it does not
>>> have the effect of enabling the second ethernet controller.
>>
>> It does for a ColdFire platform...
>>
>> grep -r CONFIG_FEC2 *
>>
>> arch/m68knommu/configs/m5275evb_defconfig:CONFIG_FEC2=y
>> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
>> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
> IMHO Sascha's comment[1] applies here, too.
I am not arguing that it doesn't :-)
Simply that removing that config option and doing nothing
else would not be the right thing to do.
Regards
Greg
> And someone might want to do what he suggested soon or the patch
> removing CONFIG_FEC2[2] needs to be commented accordingly.
>
> Best regards
> Uwe
>
> [1] http://thread.gmane.org/gmane.linux.network/182929/focus=183378
> [2] http://mid.gmane.org/1294747672-4433-1-git-send-email-shawn.guo@freescale.com
>
--
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: gerg@snapgear.com
SnapGear Group, McAfee PHONE: +61 7 3435 2888
8 Gardner Close, FAX: +61 7 3891 3630
Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com
^ permalink raw reply
* Re: [PATCH 3/3] can: at91_can: make can_id of mailbox 0 configurable
From: Wolfgang Grandegger @ 2011-01-11 13:28 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4D2C4E2D.7050309-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On 01/11/2011 01:33 PM, Marc Kleine-Budde wrote:
> On 01/11/2011 01:27 PM, Wolfgang Grandegger wrote:
>> On 01/11/2011 12:56 PM, Marc Kleine-Budde wrote:
>>> On 01/11/2011 12:45 PM, Wolfgang Grandegger wrote:
>>>> On 01/11/2011 11:28 AM, Marc Kleine-Budde wrote:
>>>>> Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
>>>>> "AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
>>>>> 0 may be send under certain conditions (even if disabled or in rx mode).
>>>>>
>>>>> The workaround in the errata suggests not to use the mailbox and load it
>>>>> with a unused identifier.
>>>>>
>>>>> This patch implements the second part of the workaround. A sysfs entry
>>>>> "mb0_id" is introduced. While the interface is down it can be used to
>>>>> configure the can_id of mailbox 0. The default value id 0x7ff.
>>>>>
>>>>> In order to use an extended can_id add the CAN_EFF_FLAG (0x80000000U)
>>>>> to the can_id. Example:
>>>>>
>>>>> - standard id 0x7ff:
>>>>> echo 0x7ff > /sys/class/net/can0/mb0_id
>>>>>
>>>>> - extended if 0x1fffffff:
>>> ^^
>>> I've fixed the typo on my git repo. I'll send an updated series later.
>>>
>>>>> echo 0x9fffffff > /sys/class/net/can0/mb0_id
>>>>
>>>> As this is a device specific property, I think it should go into
>>>> /sys/class/net/can0/device/.
>>>
>>> The attribute goes autoamtically to /sys/class/net/can0 if you add it to
>>> the driver via:
>>>
>>> + dev->sysfs_groups[0] = &at91_sysfs_attr_group;
>>>
>>> I've copied this from the janz-ican3 driver[1].
>>
>> Oh, I missed that. And also the Softing driver does it that way :-(. The
>> member has the comment:
>>
>> /* space for optional device, statistics, and wireless sysfs groups */
>> const struct attribute_group *sysfs_groups[4];
>>
>> Therefore it seems to be legal to use it for device specific properties.
>
> I'm not really happy with these sysfs approach, but it's quick
> implemented. Is device specific rtnetlink an option here?
That's toooooooo heavy, I think. I personally would just use
device_create_file for that purpose. But let's keep using sysfs_groups[]
if nobody else complains.
Wolfgang.
Wolfgang.
^ permalink raw reply
* Re: Bug#609538: r8169: long delay during resume
From: Francois Romieu @ 2011-01-11 13:25 UTC (permalink / raw)
To: Jarek Kamiński; +Cc: Ben Hutchings, 609538, Hayes Wang, netdev
In-Reply-To: <4D2C06CF.4090507@vilo.eu.org>
Jarek Kamiński <jarek@vilo.eu.org> :
[...]
> The last 2.6.36 I've tried was 2.6.36-1~experimental.1, I've then
> passsed and returned to 2.6.32 for unrelated problems. I think it wasn't
> affected, but I can re-check it and/or test later 2.6.36 versions if it
> may help.
The patch below against 2.6.37-git + davem's pending fixes (see
http://marc.info/?l=linux-netdev&m=129448910825754) should help.
Can you give it a try ?
r8169: keep firmware in memory.
The firmware agent is not available during resume.
It will help with http://bugs.debian.org/609538 but it will not avoid
the 60 seconds delay when there is no firmware.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Hayes <hayeswang@realtek.com>
Cc: Ben Hutchings <benh@debian.org>
---
drivers/net/r8169.c | 43 +++++++++++++++++++++++++++++++------------
1 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index dd758cd..7e2f01c 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -554,6 +554,8 @@ struct rtl8169_private {
struct mii_if_info mii;
struct rtl8169_counters counters;
u32 saved_wolopts;
+
+ const struct firmware *fw;
};
MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
@@ -1668,6 +1670,29 @@ rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
}
}
+static void rtl_release_firmware(struct rtl8169_private *tp)
+{
+ release_firmware(tp->fw);
+ tp->fw = NULL;
+}
+
+static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
+{
+ const struct firmware **fw = &tp->fw;
+ int rc = !*fw;
+
+ if (rc) {
+ rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
+ if (rc < 0)
+ goto out;
+ }
+
+ /* TODO: release firmware once rtl_phy_write_fw signals failures. */
+ rtl_phy_write_fw(tp, *fw);
+out:
+ return rc;
+}
+
static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
{
static const struct phy_reg phy_reg_init[] = {
@@ -2041,7 +2066,6 @@ static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
{ 0x0d, 0xf880 }
};
void __iomem *ioaddr = tp->mmio_addr;
- const struct firmware *fw;
rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
@@ -2105,11 +2129,8 @@ static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
rtl_writephy(tp, 0x1f, 0x0005);
rtl_writephy(tp, 0x05, 0x001b);
- if (rtl_readphy(tp, 0x06) == 0xbf00 &&
- request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
- rtl_phy_write_fw(tp, fw);
- release_firmware(fw);
- } else {
+ if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
+ (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
}
@@ -2159,7 +2180,6 @@ static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
{ 0x0d, 0xf880 }
};
void __iomem *ioaddr = tp->mmio_addr;
- const struct firmware *fw;
rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
@@ -2214,11 +2234,8 @@ static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
rtl_writephy(tp, 0x1f, 0x0005);
rtl_writephy(tp, 0x05, 0x001b);
- if (rtl_readphy(tp, 0x06) == 0xb300 &&
- request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
- rtl_phy_write_fw(tp, fw);
- release_firmware(fw);
- } else {
+ if ((rtl_readphy(tp, 0x06) != 0xb300) ||
+ (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
}
@@ -4662,6 +4679,8 @@ static int rtl8169_close(struct net_device *dev)
tp->TxDescArray = NULL;
tp->RxDescArray = NULL;
+ rtl_release_firmware(tp);
+
pm_runtime_put_sync(&pdev->dev);
return 0;
--
1.7.3.4
^ permalink raw reply related
* [PATCH v2 3/3] can: at91_can: make can_id of mailbox 0 configurable
From: Marc Kleine-Budde @ 2011-01-11 13:21 UTC (permalink / raw)
To: Socketcan-core; +Cc: netdev, Marc Kleine-Budde
In-Reply-To: <1294752085-30151-1-git-send-email-mkl@pengutronix.de>
Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
"AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
0 may be send under certain conditions (even if disabled or in rx mode).
The workaround in the errata suggests not to use the mailbox and load it
with an unused identifier.
This patch implements the second part of the workaround. A sysfs entry
"mb0_id" is introduced. While the interface is down it can be used to
configure the can_id of mailbox 0. The default value id 0x7ff.
In order to use an extended can_id add the CAN_EFF_FLAG (0x80000000U)
to the can_id. Example:
- standard id 0x7ff:
echo 0x7ff > /sys/class/net/can0/mb0_id
- extended id 0x1fffffff:
echo 0x9fffffff > /sys/class/net/can0/mb0_id
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
changes since v1:
- Documentation/ABI/testing/sysfs-platform-at91 (as suggested by Wolfram Sang)
- fixed typo in commit message
Documentation/ABI/testing/sysfs-platform-at91 | 25 +++++++
drivers/net/can/at91_can.c | 90 +++++++++++++++++++++++--
2 files changed, 108 insertions(+), 7 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-platform-at91
diff --git a/Documentation/ABI/testing/sysfs-platform-at91 b/Documentation/ABI/testing/sysfs-platform-at91
new file mode 100644
index 0000000..4cc6a86
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-platform-at91
@@ -0,0 +1,25 @@
+What: /sys/devices/platform/at91_can/net/<iface>/mb0_id
+Date: January 2011
+KernelVersion: 2.6.38
+Contact: Marc Kleine-Budde <kernel@pengutronix.de>
+Description:
+ Value representing the can_id of mailbox 0.
+
+ Default: 0x7ff (standard frame)
+
+ Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
+ "AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the
+ contents of mailbox 0 may be send under certain
+ conditions (even if disabled or in rx mode).
+
+ The workaround in the errata suggests not to use the
+ mailbox and load it with an unused identifier.
+
+ In order to use an extended can_id add the
+ CAN_EFF_FLAG (0x80000000U) to the can_id. Example:
+
+ - standard id 0x7ff:
+ echo 0x7ff > /sys/class/net/can0/mb0_id
+
+ - extended id 0x1fffffff:
+ echo 0x9fffffff > /sys/class/net/can0/mb0_id
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 16e45a5..2532b96 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -30,6 +30,7 @@
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
+#include <linux/rtnetlink.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/string.h>
@@ -169,6 +170,8 @@ struct at91_priv {
struct clk *clk;
struct at91_can_data *pdata;
+
+ canid_t mb0_id;
};
static struct can_bittiming_const at91_bittiming_const = {
@@ -221,6 +224,18 @@ static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
set_mb_mode_prio(priv, mb, mode, 0);
}
+static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
+{
+ u32 reg_mid;
+
+ if (can_id & CAN_EFF_FLAG)
+ reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
+ else
+ reg_mid = (can_id & CAN_SFF_MASK) << 18;
+
+ return reg_mid;
+}
+
/*
* Swtich transceiver on or off
*/
@@ -234,6 +249,7 @@ static void at91_setup_mailboxes(struct net_device *dev)
{
struct at91_priv *priv = netdev_priv(dev);
unsigned int i;
+ u32 reg_mid;
/*
* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
@@ -242,8 +258,13 @@ static void at91_setup_mailboxes(struct net_device *dev)
* overwrite option. The overwrite flag indicates a FIFO
* overflow.
*/
- for (i = 0; i < AT91_MB_RX_FIRST; i++)
+ reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
+ for (i = 0; i < AT91_MB_RX_FIRST; i++) {
set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
+ at91_write(priv, AT91_MID(i), reg_mid);
+ at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */
+ }
+
for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
set_mb_mode(priv, i, AT91_MB_MODE_RX);
set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
@@ -378,12 +399,7 @@ static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
return NETDEV_TX_BUSY;
}
-
- if (cf->can_id & CAN_EFF_FLAG)
- reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
- else
- reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
-
+ reg_mid = at91_can_id_to_reg_mid(cf->can_id);
reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
(cf->can_dlc << 16) | AT91_MCR_MTCR;
@@ -1047,6 +1063,64 @@ static const struct net_device_ops at91_netdev_ops = {
.ndo_start_xmit = at91_start_xmit,
};
+static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct at91_priv *priv = netdev_priv(to_net_dev(dev));
+
+ if (priv->mb0_id & CAN_EFF_FLAG)
+ return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
+ else
+ return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
+}
+
+static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct net_device *ndev = to_net_dev(dev);
+ struct at91_priv *priv = netdev_priv(ndev);
+ unsigned long can_id;
+ ssize_t ret;
+ int err;
+
+ rtnl_lock();
+
+ if (ndev->flags & IFF_UP) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ err = strict_strtoul(buf, 0, &can_id);
+ if (err) {
+ ret = err;
+ goto out;
+ }
+
+ if (can_id & CAN_EFF_FLAG)
+ can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
+ else
+ can_id &= CAN_SFF_MASK;
+
+ priv->mb0_id = can_id;
+ ret = count;
+
+ out:
+ rtnl_unlock();
+ return ret;
+}
+
+static DEVICE_ATTR(mb0_id, S_IWUGO | S_IRUGO,
+ at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
+
+static struct attribute *at91_sysfs_attrs[] = {
+ &dev_attr_mb0_id.attr,
+ NULL,
+};
+
+static struct attribute_group at91_sysfs_attr_group = {
+ .attrs = at91_sysfs_attrs,
+};
+
static int __devinit at91_can_probe(struct platform_device *pdev)
{
struct net_device *dev;
@@ -1092,6 +1166,7 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
dev->netdev_ops = &at91_netdev_ops;
dev->irq = irq;
dev->flags |= IFF_ECHO;
+ dev->sysfs_groups[0] = &at91_sysfs_attr_group;
priv = netdev_priv(dev);
priv->can.clock.freq = clk_get_rate(clk);
@@ -1103,6 +1178,7 @@ static int __devinit at91_can_probe(struct platform_device *pdev)
priv->dev = dev;
priv->clk = clk;
priv->pdata = pdev->dev.platform_data;
+ priv->mb0_id = 0x7ff;
netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
--
1.7.2.3
^ permalink raw reply related
* [PATCH v2 2/3] can: at91_can: don't use mailbox 0
From: Marc Kleine-Budde @ 2011-01-11 13:21 UTC (permalink / raw)
To: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, Marc Kleine-Budde
In-Reply-To: <1294752085-30151-1-git-send-email-mkl-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
"AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
0 may be send under certain conditions (even if disabled or in rx mode).
The workaround in the errata suggests not to use the mailbox and load it
with a unused identifier.
This patch implements the first part of the workaround, it updates
AT91_MB_RX_NUM and AT91_MB_RX_FIRST (and the inline documentation)
so that mailbox 0 stays unused.
Signed-off-by: Marc Kleine-Budde <mkl-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
drivers/net/can/at91_can.c | 32 ++++++++++++++++++++------------
1 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 892c3d8..16e45a5 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -40,16 +40,16 @@
#include <mach/board.h>
-#define AT91_NAPI_WEIGHT 12
+#define AT91_NAPI_WEIGHT 11
/*
* RX/TX Mailbox split
* don't dare to touch
*/
-#define AT91_MB_RX_NUM 12
+#define AT91_MB_RX_NUM 11
#define AT91_MB_TX_SHIFT 2
-#define AT91_MB_RX_FIRST 0
+#define AT91_MB_RX_FIRST 1
#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
@@ -236,10 +236,14 @@ static void at91_setup_mailboxes(struct net_device *dev)
unsigned int i;
/*
- * The first 12 mailboxes are used as a reception FIFO. The
- * last mailbox is configured with overwrite option. The
- * overwrite flag indicates a FIFO overflow.
+ * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
+ * mailbox is disabled. The next 11 mailboxes are used as a
+ * reception FIFO. The last mailbox is configured with
+ * overwrite option. The overwrite flag indicates a FIFO
+ * overflow.
*/
+ for (i = 0; i < AT91_MB_RX_FIRST; i++)
+ set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
set_mb_mode(priv, i, AT91_MB_MODE_RX);
set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
@@ -541,27 +545,31 @@ static void at91_read_msg(struct net_device *dev, unsigned int mb)
*
* Theory of Operation:
*
- * 12 of the 16 mailboxes on the chip are reserved for RX. we split
- * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
+ * 11 of the 16 mailboxes on the chip are reserved for RX. we split
+ * them into 2 groups. The lower group holds 7 and upper 4 mailboxes.
*
* Like it or not, but the chip always saves a received CAN message
* into the first free mailbox it finds (starting with the
* lowest). This makes it very difficult to read the messages in the
* right order from the chip. This is how we work around that problem:
*
- * The first message goes into mb nr. 0 and issues an interrupt. All
+ * The first message goes into mb nr. 1 and issues an interrupt. All
* rx ints are disabled in the interrupt handler and a napi poll is
* scheduled. We read the mailbox, but do _not_ reenable the mb (to
* receive another message).
*
* lower mbxs upper
- * ______^______ __^__
- * / \ / \
+ * ____^______ __^__
+ * / \ / \
* +-+-+-+-+-+-+-+-++-+-+-+-+
- * |x|x|x|x|x|x|x|x|| | | | |
+ * | |x|x|x|x|x|x|x|| | | | |
* +-+-+-+-+-+-+-+-++-+-+-+-+
* 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
* 0 1 2 3 4 5 6 7 8 9 0 1 / box
+ * ^
+ * |
+ * \
+ * unused, due to chip bug
*
* The variable priv->rx_next points to the next mailbox to read a
* message from. As long we're in the lower mailboxes we just read the
--
1.7.2.3
^ permalink raw reply related
* [PATCH v2 1/3] can: at91_can: clean up usage of AT91_MB_RX_FIRST and AT91_MB_RX_NUM
From: Marc Kleine-Budde @ 2011-01-11 13:21 UTC (permalink / raw)
To: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, Marc Kleine-Budde
In-Reply-To: <1294752085-30151-1-git-send-email-mkl-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
This patch cleans up the usage of two macros which specify the mailbox
usage. AT91_MB_RX_FIRST and AT91_MB_RX_NUM define the first and the
number of RX mailboxes. The current driver uses these variables in an
unclean way; assuming that AT91_MB_RX_FIRST is 0;
This patch cleans up the usage of these macros, no longer assuming
AT91_MB_RX_FIRST == 0.
Signed-off-by: Marc Kleine-Budde <mkl-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
drivers/net/can/at91_can.c | 18 ++++++++++--------
1 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 7ef83d0..892c3d8 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -2,7 +2,7 @@
* at91_can.c - CAN network driver for AT91 SoC CAN controller
*
* (C) 2007 by Hans J. Koch <hjk-vqZO0P4V72/QD6PfKP4TzA@public.gmane.org>
- * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
*
* This software may be distributed under the terms of the GNU General
* Public License ("GPL") version 2 as distributed in the 'COPYING'
@@ -55,7 +55,8 @@
#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
#define AT91_MB_RX_SPLIT 8
#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
-#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
+#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
+ ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
@@ -254,7 +255,8 @@ static void at91_setup_mailboxes(struct net_device *dev)
set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
/* Reset tx and rx helper pointers */
- priv->tx_next = priv->tx_echo = priv->rx_next = 0;
+ priv->tx_next = priv->tx_echo = 0;
+ priv->rx_next = AT91_MB_RX_FIRST;
}
static int at91_set_bittiming(struct net_device *dev)
@@ -590,10 +592,10 @@ static int at91_poll_rx(struct net_device *dev, int quota)
"order of incoming frames cannot be guaranteed\n");
again:
- for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next);
- mb < AT91_MB_RX_NUM && quota > 0;
+ for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next);
+ mb < AT91_MB_RX_LAST + 1 && quota > 0;
reg_sr = at91_read(priv, AT91_SR),
- mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) {
+ mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) {
at91_read_msg(dev, mb);
/* reactivate mailboxes */
@@ -610,8 +612,8 @@ static int at91_poll_rx(struct net_device *dev, int quota)
/* upper group completed, look again in lower */
if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
- quota > 0 && mb >= AT91_MB_RX_NUM) {
- priv->rx_next = 0;
+ quota > 0 && mb > AT91_MB_RX_LAST) {
+ priv->rx_next = AT91_MB_RX_FIRST;
goto again;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH v2 0/3] can: at91_can: fix for errata 50.2.6.3 & 50.3.5.3
From: Marc Kleine-Budde @ 2011-01-11 13:21 UTC (permalink / raw)
To: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w; +Cc: netdev-u79uwXL29TY76Z2rM5mHXA
Hello,
as promised I've implemented the proposed workaround for the errata
50.2.6.3 & 50.3.5.3:
"Contents of Mailbox 0 can be sent Even if Mailbox is Disabled"
This means under high bus load it can happen that the mailbox 0 is send
to the bus. And it does happen, even with the mainline driver where
Mailbox 0 is a receive mailbox. The errata proposes not to use mailbox 0
and load it with an unused can_id that will not disturb the bus.
The first patch cleans up the driver without any functional changes, so
that the mailbox 0 can be disabled in the second patch. The third patch
adds a sysfs parameter to the driver, so that the identifier of mailbox 0
can configured.
This series applies to net-2.6/master. It has been tested on a ronetix pm9263
board against a PCI-SJA1000 card with the canfdtest utility.
changes since v1:
- Documentation/ABI/testing/sysfs-platform-at91 (as suggested by Wolfram Sang)
- fixed typo in PATCH 3's commit message
regards, Marc
---
The following changes since commit b11a25aaeccc29d5090d1ce9776af20e3ee99ab9:
qlcnic: change module parameter permissions (2011-01-10 13:34:55 -0800)
are available in the git repository at:
git://git.pengutronix.de/git/mkl/linux-2.6.git can/at91_can-for-net-2.6
Marc Kleine-Budde (3):
can: at91_can: clean up usage of AT91_MB_RX_FIRST and AT91_MB_RX_NUM
can: at91_can: don't use mailbox 0
can: at91_can: make can_id of mailbox 0 configurable
Documentation/ABI/testing/sysfs-platform-at91 | 25 +++++
drivers/net/can/at91_can.c | 138 ++++++++++++++++++++-----
2 files changed, 137 insertions(+), 26 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-platform-at91
^ permalink raw reply
* Re: [PATCH net-next-2.6 v4 1/1] can: c_can: Added support for Bosch C_CAN controller
From: Wolfgang Grandegger @ 2011-01-11 13:16 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1294746592-12144-1-git-send-email-bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
Hi Bhupesh,
some final nitpicking as you need to fix Marc remarks anyway...
On 01/11/2011 12:49 PM, Bhupesh Sharma wrote:
> Bosch C_CAN controller is a full-CAN implementation which is compliant
> to CAN protocol version 2.0 part A and B. Bosch C_CAN user manual can be
> obtained from:
> http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/
> c_can/users_manual_c_can.pdf
>
> This patch adds the support for this controller.
> The following are the design choices made while writing the controller
> driver:
> 1. Interface Register set IF1 has be used only in the current design.
> 2. Out of the 32 Message objects available, 16 are kept aside for RX
> purposes and the rest for TX purposes.
> 3. NAPI implementation is such that both the TX and RX paths function
> in polling mode.
>
> Changes since V3:
> 1. Corrected commenting style.
> 2. Removing *non-required* header files from driver files.
> 3. Removed extra *non-required* outer brackets globally.
> 4. Implemented and used a inline routine to check BUSY status.
> 5. Added a board-specific param *priv* inside the c_can_priv struct.
>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
...
> +++ b/drivers/net/can/c_can/c_can.h
> @@ -0,0 +1,235 @@
> +/*
> + * CAN bus driver for Bosch C_CAN controller
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> + *
> + * Borrowed heavily from the C_CAN driver originally written by:
> + * Copyright (C) 2007
> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
> + *
> + * TX and RX NAPI implementation has been borrowed from at91 CAN driver
> + * written by:
> + * Copyright
> + * (C) 2007 by Hans J. Koch <hjk-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
> + * (C) 2008, 2009 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
> + * Bosch C_CAN user manual can be obtained from:
> + * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
> + * users_manual_c_can.pdf
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef C_CAN_H
> +#define C_CAN_H
> +
> +/* control register */
> +#define CONTROL_TEST BIT(7)
> +#define CONTROL_CCE BIT(6)
> +#define CONTROL_DISABLE_AR BIT(5)
> +#define CONTROL_ENABLE_AR (0 << 5)
> +#define CONTROL_EIE BIT(3)
> +#define CONTROL_SIE BIT(2)
> +#define CONTROL_IE BIT(1)
> +#define CONTROL_INIT BIT(0)
> +
> +/* test register */
> +#define TEST_RX BIT(7)
> +#define TEST_TX1 BIT(6)
> +#define TEST_TX2 BIT(5)
> +#define TEST_LBACK BIT(4)
> +#define TEST_SILENT BIT(3)
> +#define TEST_BASIC BIT(2)
> +
> +/* status register */
> +#define STATUS_BOFF BIT(7)
> +#define STATUS_EWARN BIT(6)
> +#define STATUS_EPASS BIT(5)
> +#define STATUS_RXOK BIT(4)
> +#define STATUS_TXOK BIT(3)
> +#define STATUS_LEC_MASK 0x07
> +
> +/* error counter register */
> +#define ERR_COUNTER_TEC_MASK 0xff
> +#define ERR_COUNTER_TEC_SHIFT 0
> +#define ERR_COUNTER_REC_SHIFT 8
> +#define ERR_COUNTER_REC_MASK (0x7f << ERR_COUNTER_REC_SHIFT)
> +#define ERR_COUNTER_RP_SHIFT 15
> +#define ERR_COUNTER_RP_MASK (0x1 << ERR_COUNTER_RP_SHIFT)
s/ERR_COUNTER/ERR_CNT/ to match the member name.
> +
> +/* bit-timing register */
> +#define BTR_BRP_MASK 0x3f
> +#define BTR_BRP_SHIFT 0
> +#define BTR_SJW_SHIFT 6
> +#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
> +#define BTR_TSEG1_SHIFT 8
> +#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
> +#define BTR_TSEG2_SHIFT 12
> +#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
> +
> +/* brp extension register */
> +#define BRP_EXT_BRPE_MASK 0x0f
> +#define BRP_EXT_BRPE_SHIFT 0
> +
> +/* IFx command request */
> +#define IF_COMR_BUSY BIT(15)
> +
> +/* IFx command mask */
> +#define IF_COMM_WR BIT(7)
> +#define IF_COMM_MASK BIT(6)
> +#define IF_COMM_ARB BIT(5)
> +#define IF_COMM_CONTROL BIT(4)
> +#define IF_COMM_CLR_INT_PND BIT(3)
> +#define IF_COMM_TXRQST BIT(2)
> +#define IF_COMM_DATAA BIT(1)
> +#define IF_COMM_DATAB BIT(0)
> +#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
> + IF_COMM_CONTROL | IF_COMM_TXRQST | \
> + IF_COMM_DATAA | IF_COMM_DATAB)
> +
> +/* IFx arbitration */
> +#define IF_ARB_MSGVAL BIT(15)
> +#define IF_ARB_MSGXTD BIT(14)
> +#define IF_ARB_TRANSMIT BIT(13)
> +
> +/* IFx message control */
> +#define IF_MCONT_NEWDAT BIT(15)
> +#define IF_MCONT_MSGLST BIT(14)
> +#define IF_MCONT_CLR_MSGLST (0 << 14)
> +#define IF_MCONT_INTPND BIT(13)
> +#define IF_MCONT_UMASK BIT(12)
> +#define IF_MCONT_TXIE BIT(11)
> +#define IF_MCONT_RXIE BIT(10)
> +#define IF_MCONT_RMTEN BIT(9)
> +#define IF_MCONT_TXRQST BIT(8)
> +#define IF_MCONT_EOB BIT(7)
> +#define IF_MCONT_DLC_MASK 0xf
> +
> +/*
> + * IFx register masks:
> + * allow easy operation on 16-bit registers when the
> + * argument is 32-bit instead
> + */
> +#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
> +#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
> +
> +/* message object split */
> +#define C_CAN_NO_OF_OBJECTS 31
> +#define C_CAN_MSG_OBJ_RX_NUM 16
> +#define C_CAN_MSG_OBJ_TX_NUM 16
> +
> +#define C_CAN_MSG_OBJ_RX_FIRST 0
> +#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
> + C_CAN_MSG_OBJ_RX_NUM - 1)
> +
> +#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
> +#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
> + C_CAN_MSG_OBJ_TX_NUM - 1)
> +
> +#define C_CAN_MSG_OBJ_RX_SPLIT 8
> +#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
> +
> +#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
> +#define RECEIVE_OBJECT_BITS 0x0000ffff
> +
> +/* status interrupt */
> +#define STATUS_INTERRUPT 0x8000
> +
> +/* global interrupt masks */
> +#define ENABLE_ALL_INTERRUPTS 1
> +#define DISABLE_ALL_INTERRUPTS 0
> +
> +/* minimum timeout for checking BUSY status */
> +#define MIN_TIMEOUT_VALUE 6
> +
> +/* napi related */
> +#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
> +
> +/* c_can IF registers */
> +struct c_can_if_regs {
> + u16 com_reg;
> + u16 com_mask;
> + u16 mask1;
> + u16 mask2;
> + u16 arb1;
> + u16 arb2;
> + u16 msg_cntrl;
> + u16 data[4];
> + u16 _reserved[13];
> +};
> +
> +/* c_can hardware registers */
> +struct c_can_regs {
> + u16 control;
> + u16 status;
> + u16 err_cnt;
> + u16 btr;
> + u16 interrupt;
> + u16 test;
> + u16 brp_ext;
> + u16 _reserved1;
> + struct c_can_if_regs intf[2]; /* [0] = IF1 and [1] = IF2 */
I not happy with the name "intf". Sounds more like an interrupt related
property. Above you already use the prefix IF_ for the corresponding
macro definitions and somewhere else the name "iface".
Wolfgang.
^ permalink raw reply
* Re: [PATCH v4 05/10] net/fec: add dual fec support for mx28
From: Uwe Kleine-König @ 2011-01-11 13:07 UTC (permalink / raw)
To: Greg Ungerer
Cc: Sascha Hauer, Shawn Guo, B32542, netdev, jamie, baruch, w.sang,
r64343, eric, bryan.wu, jamie, davem, linux-arm-kernel, lw
In-Reply-To: <4D2C4BEC.1030003@snapgear.com>
Hi Greg,
On Tue, Jan 11, 2011 at 10:24:12PM +1000, Greg Ungerer wrote:
> On 11/01/11 20:27, Sascha Hauer wrote:
> >On Thu, Jan 06, 2011 at 03:13:13PM +0800, Shawn Guo wrote:
> >This option is used nowhere and should be removed. Certainly it does not
> >have the effect of enabling the second ethernet controller.
>
> It does for a ColdFire platform...
>
> grep -r CONFIG_FEC2 *
>
> arch/m68knommu/configs/m5275evb_defconfig:CONFIG_FEC2=y
> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
> arch/m68knommu/platform/527x/config.c:#ifdef CONFIG_FEC2
IMHO Sascha's comment[1] applies here, too.
And someone might want to do what he suggested soon or the patch
removing CONFIG_FEC2[2] needs to be commented accordingly.
Best regards
Uwe
[1] http://thread.gmane.org/gmane.linux.network/182929/focus=183378
[2] http://mid.gmane.org/1294747672-4433-1-git-send-email-shawn.guo@freescale.com
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH] tcp: disallow bind() to reuse addr/port
From: Daniel Baluta @ 2011-01-11 13:04 UTC (permalink / raw)
To: Eric Dumazet; +Cc: David Miller, Gaspar Chilingarov, netdev
In-Reply-To: <1294744462.2927.53.camel@edumazet-laptop>
On Tue, Jan 11, 2011 at 1:14 PM, Eric Dumazet <eric.dumazet@gmail.com> wrote:
> Le mercredi 05 janvier 2011 à 11:00 +0200, Daniel Baluta a écrit :
>
>> Going back to my first email, are there any follow ups on your
>> "tcp: bind() fix when many ports are bound" patch. I've searched
>> netdev archives but no luck. I might have missed something.
>>
>> I really appreciate your help.
>>
>
> I believe following patch should solve the problem.
I have tested the patch and it works.
>
> Thanks for reminding us this issue !
thanks,
Daniel.
^ permalink raw reply
* Re: [PATCH V8 08/13] posix clocks: cleanup the CLOCK_DISPTACH macro
From: Thomas Gleixner @ 2011-01-11 12:57 UTC (permalink / raw)
To: Richard Cochran
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-api-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
Alan Cox, Arnd Bergmann, Christoph Lameter, David Miller,
John Stultz, Krzysztof Halasa, Peter Zijlstra, Rodolfo Giometti
In-Reply-To: <503cd1fa268867573001cfc9bb5681ee3b5b32fa.1293820862.git.richard.cochran-3mrvs1K0uXizZXS1Dc/lvw@public.gmane.org>
On Fri, 31 Dec 2010, Richard Cochran wrote:
> +static inline bool clock_is_posix_cpu(const clockid_t id)
> +{
> + if ((id & CLOCKFD_MASK) == CLOCKFD)
> + return false;
> + else
> + return true;
> +}
> +
> +static inline int dispatch_clock_getres(const clockid_t id, struct timespec *ts)
> +{
> + if (id >= 0) {
> + return posix_clocks[id].clock_getres ?
> + posix_clocks[id].clock_getres(id, ts) : -EINVAL;
> + }
> +
> + if (clock_is_posix_cpu(id))
> + return posix_cpu_clock_getres(id, ts);
I wonder whether we should be a bit more clever here and create an
extra entry for posix_cpu_timers in the posix_clocks array and do the
following:
/* These are local to posix-timer.c and not exposed to anything else */
#define POSIX_INV_CLOCK_ID MAX_CLOCKS
#define POSIX_CPU_CLOCK_ID (MAX_CLOCKS + 1)
#define NR_CLOCK_ENTRIES (MAX_CLOCKS + 2)
static struct k_clock posix_clocks[NR_CLOCK_ENTRIES];
static __init int init_posix_timers(void)
{
......
/*
* We leave the POSIX_INV_CLOCK_ID entries zeroed out, so the
* the dispatch code will return -EINVAL.
*/
init_posix_cpu_timer_entries();
}
static clockid_t clock_get_array_id(const clockid_t id)
{
if (id >= 0)
return id < MAX_CLOCKS ? id : POSIX_INV_CLOCK_ID;
if (clock_is_posix_cpu(id))
return POSIX_CPU_CLOCK_ID;
return POSIX_INV_CLOCK_ID;
}
static inline int dispatch_clock_getres(const clockid_t id, struct timespec *ts)
{
struct k_clock *clk = &posix_clocks[clock_get_array_id(id)];
return clk->clock_getres ? clk->clock_getres(id, ts) : -EINVAL;
}
That reduces the code significantly and the MAX_CLOCKS check in
clock_get_array_id() replaces the invalid_clock() check in the
syscalls as well. It does not matter whether we check this before or
after copying stuff from user.
Adding your new stuff requires just another entry in the array, the
setup of the function pointers and the CLOCKFD check in
clock_get_array_id(). Everything else just falls in place.
> +
> +#define CLOCK_DISPATCH(clock, call, arglist) dispatch_##call arglist
> +
Can we get rid of this completely please ?
> clock_nanosleep_restart(struct restart_block *restart_block)
> {
> - clockid_t which_clock = restart_block->arg0;
> -
How does that compile ?
> return CLOCK_DISPATCH(which_clock, nsleep_restart,
> (restart_block));
> }
Thanks,
tglx
^ permalink raw reply
* [PATCH 14/16] can: mpc5xxx_can: don't treat NULL clk as an error
From: Jamie Iles @ 2011-01-11 12:43 UTC (permalink / raw)
To: linux-kernel; +Cc: Jamie Iles, netdev
In-Reply-To: <1294749833-32019-1-git-send-email-jamie@jamieiles.com>
clk_get() returns a struct clk cookie to the driver and some platforms
may return NULL if they only support a single clock. clk_get() has only
failed if it returns a ERR_PTR() encoded pointer.
Cc: netdev@vger.kernel.org
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
drivers/net/can/mscan/mpc5xxx_can.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/mscan/mpc5xxx_can.c b/drivers/net/can/mscan/mpc5xxx_can.c
index 312b9c8..15377c0 100644
--- a/drivers/net/can/mscan/mpc5xxx_can.c
+++ b/drivers/net/can/mscan/mpc5xxx_can.c
@@ -29,6 +29,7 @@
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <linux/clk.h>
+#include <linux/err.h>
#include <linux/io.h>
#include <asm/mpc52xx.h>
@@ -181,7 +182,7 @@ static u32 __devinit mpc512x_can_get_clock(struct platform_device *ofdev,
if (!clock_name || !strcmp(clock_name, "sys")) {
sys_clk = clk_get(&ofdev->dev, "sys_clk");
- if (!sys_clk) {
+ if (IS_ERR(sys_clk)) {
dev_err(&ofdev->dev, "couldn't get sys_clk\n");
goto exit_unmap;
}
@@ -204,7 +205,7 @@ static u32 __devinit mpc512x_can_get_clock(struct platform_device *ofdev,
if (clocksrc < 0) {
ref_clk = clk_get(&ofdev->dev, "ref_clk");
- if (!ref_clk) {
+ if (IS_ERR(ref_clk)) {
dev_err(&ofdev->dev, "couldn't get ref_clk\n");
goto exit_unmap;
}
--
1.7.3.4
^ permalink raw reply related
* [PATCH 11/16] drivers/net: sh_irda: don't treat NULL clk as an error
From: Jamie Iles @ 2011-01-11 12:43 UTC (permalink / raw)
To: linux-kernel; +Cc: Jamie Iles, Samuel Ortiz, netdev
In-Reply-To: <1294749833-32019-1-git-send-email-jamie@jamieiles.com>
clk_get() returns a struct clk cookie to the driver and some platforms
may return NULL if they only support a single clock. clk_get() has only
failed if it returns a ERR_PTR() encoded pointer.
Cc: Samuel Ortiz <samuel@sortiz.org>
Cc: netdev@vger.kernel.org
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
drivers/net/irda/sh_sir.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/irda/sh_sir.c b/drivers/net/irda/sh_sir.c
index 52a7c86..56ba91a 100644
--- a/drivers/net/irda/sh_sir.c
+++ b/drivers/net/irda/sh_sir.c
@@ -12,6 +12,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/err.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -278,9 +279,9 @@ static int sh_sir_set_baudrate(struct sh_sir_self *self, u32 baudrate)
}
clk = clk_get(NULL, "irda_clk");
- if (!clk) {
+ if (IS_ERR(clk)) {
dev_err(dev, "can not get irda_clk\n");
- return -EIO;
+ return PTR_ERR(clk);
}
clk_set_rate(clk, sh_sir_find_sclk(clk));
--
1.7.3.4
^ permalink raw reply related
* [PATCH 10/16] drivers/net: stmmac: don't treat NULL clk as an error
From: Jamie Iles @ 2011-01-11 12:43 UTC (permalink / raw)
To: linux-kernel; +Cc: Jamie Iles, Giuseppe Cavallaro, netdev
In-Reply-To: <1294749833-32019-1-git-send-email-jamie@jamieiles.com>
clk_get() returns a struct clk cookie to the driver and some platforms
may return NULL if they only support a single clock. clk_get() has only
failed if it returns a ERR_PTR() encoded pointer.
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: netdev@vger.kernel.org
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
---
drivers/net/stmmac/stmmac_timer.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/net/stmmac/stmmac_timer.c b/drivers/net/stmmac/stmmac_timer.c
index 2a0e1ab..ebb1b37 100644
--- a/drivers/net/stmmac/stmmac_timer.c
+++ b/drivers/net/stmmac/stmmac_timer.c
@@ -91,6 +91,7 @@ int stmmac_close_ext_timer(void)
#elif defined(CONFIG_STMMAC_TMU_TIMER)
#include <linux/clk.h>
+#include <linux/err.h>
#define TMU_CHANNEL "tmu2_clk"
static struct clk *timer_clock;
@@ -109,7 +110,7 @@ int stmmac_open_ext_timer(struct net_device *dev, struct stmmac_timer *tm)
{
timer_clock = clk_get(NULL, TMU_CHANNEL);
- if (timer_clock == NULL)
+ if (IS_ERR(timer_clock))
return -1;
if (tmu2_register_user(stmmac_timer_handler, (void *)dev) < 0) {
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH 3/3] netlink: support setting devgroup parameters
From: jamal @ 2011-01-11 12:40 UTC (permalink / raw)
To: Vlad Dogaru; +Cc: netdev, Octavian Purdila
In-Reply-To: <20110111121350.GB26417@cormyr>
On Tue, 2011-01-11 at 14:13 +0200, Vlad Dogaru wrote:
>
> That sounds like a good idea, but, by using the same attribute,
> userspace won't be able to change the group of all the interfaces in a
> group, i.e. no more
> ip l set group 1 devgroup 0
>
> However, I'm not sure that the use case above would be very common.
I think for the simple case we have been discussing this goes beyond
that. So maybe to KISS defer this to a later time.
cheers,
jamal
^ permalink raw reply
* Re: [PATCH 0/3] iproute2: ip link: add support for network device groups
From: jamal @ 2011-01-11 12:38 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: Vlad Dogaru, netdev, Octavian Purdila
In-Reply-To: <20110110084700.17798894@nehalam>
On Mon, 2011-01-10 at 08:47 -0800, Stephen Hemminger wrote:
> I like the idea, but I wonder if we should take it farther?
> Should it be hierarchal tree of groups?
> Should slave devices (ppp, vlan, etc) be automatically assigned
> to group of parent?
I think that would be treading into policy land.
The whole point is that the admin sets this value (just like the
skb->mark) and specifies how it is to be used.
cheers,
jamal
^ permalink raw reply
* Re: [PATCH 3/3] can: at91_can: make can_id of mailbox 0 configurable
From: Marc Kleine-Budde @ 2011-01-11 12:33 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4D2C4CC1.4070109-5Yr1BZd7O62+XT7JhA+gdA@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 2222 bytes --]
On 01/11/2011 01:27 PM, Wolfgang Grandegger wrote:
> On 01/11/2011 12:56 PM, Marc Kleine-Budde wrote:
>> On 01/11/2011 12:45 PM, Wolfgang Grandegger wrote:
>>> On 01/11/2011 11:28 AM, Marc Kleine-Budde wrote:
>>>> Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
>>>> "AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
>>>> 0 may be send under certain conditions (even if disabled or in rx mode).
>>>>
>>>> The workaround in the errata suggests not to use the mailbox and load it
>>>> with a unused identifier.
>>>>
>>>> This patch implements the second part of the workaround. A sysfs entry
>>>> "mb0_id" is introduced. While the interface is down it can be used to
>>>> configure the can_id of mailbox 0. The default value id 0x7ff.
>>>>
>>>> In order to use an extended can_id add the CAN_EFF_FLAG (0x80000000U)
>>>> to the can_id. Example:
>>>>
>>>> - standard id 0x7ff:
>>>> echo 0x7ff > /sys/class/net/can0/mb0_id
>>>>
>>>> - extended if 0x1fffffff:
>> ^^
>> I've fixed the typo on my git repo. I'll send an updated series later.
>>
>>>> echo 0x9fffffff > /sys/class/net/can0/mb0_id
>>>
>>> As this is a device specific property, I think it should go into
>>> /sys/class/net/can0/device/.
>>
>> The attribute goes autoamtically to /sys/class/net/can0 if you add it to
>> the driver via:
>>
>> + dev->sysfs_groups[0] = &at91_sysfs_attr_group;
>>
>> I've copied this from the janz-ican3 driver[1].
>
> Oh, I missed that. And also the Softing driver does it that way :-(. The
> member has the comment:
>
> /* space for optional device, statistics, and wireless sysfs groups */
> const struct attribute_group *sysfs_groups[4];
>
> Therefore it seems to be legal to use it for device specific properties.
I'm not really happy with these sysfs approach, but it's quick
implemented. Is device specific rtnetlink an option here?
cheers, Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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_______________________________________________
Socketcan-core mailing list
Socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org
https://lists.berlios.de/mailman/listinfo/socketcan-core
^ permalink raw reply
* Re: [PATCH net-next-2.6 v4 1/1] can: c_can: Added support for Bosch C_CAN controller
From: Marc Kleine-Budde @ 2011-01-11 12:30 UTC (permalink / raw)
To: Bhupesh Sharma
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1294746592-12144-1-git-send-email-bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 49944 bytes --]
On 01/11/2011 12:49 PM, Bhupesh Sharma wrote:
> Bosch C_CAN controller is a full-CAN implementation which is compliant
> to CAN protocol version 2.0 part A and B. Bosch C_CAN user manual can be
> obtained from:
> http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/
> c_can/users_manual_c_can.pdf
>
> This patch adds the support for this controller.
> The following are the design choices made while writing the controller
> driver:
> 1. Interface Register set IF1 has be used only in the current design.
> 2. Out of the 32 Message objects available, 16 are kept aside for RX
> purposes and the rest for TX purposes.
> 3. NAPI implementation is such that both the TX and RX paths function
> in polling mode.
Can you replace all "dev_<LEVEL>(dev->dev.parent," by
"netdev_<LEVEL>(dev,".
>
> Changes since V3:
> 1. Corrected commenting style.
> 2. Removing *non-required* header files from driver files.
> 3. Removed extra *non-required* outer brackets globally.
> 4. Implemented and used a inline routine to check BUSY status.
> 5. Added a board-specific param *priv* inside the c_can_priv struct.
The changes are usually placed between the "---" and the diffstat, so
that they don't show up in the commit message in the git repo.
>
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/net/can/Kconfig | 2 +
> drivers/net/can/Makefile | 1 +
> drivers/net/can/c_can/Kconfig | 15 +
> drivers/net/can/c_can/Makefile | 8 +
> drivers/net/can/c_can/c_can.c | 953 ++++++++++++++++++++++++++++++++
> drivers/net/can/c_can/c_can.h | 235 ++++++++
> drivers/net/can/c_can/c_can_platform.c | 208 +++++++
> 7 files changed, 1422 insertions(+), 0 deletions(-)
> create mode 100644 drivers/net/can/c_can/Kconfig
> create mode 100644 drivers/net/can/c_can/Makefile
> create mode 100644 drivers/net/can/c_can/c_can.c
> create mode 100644 drivers/net/can/c_can/c_can.h
> create mode 100644 drivers/net/can/c_can/c_can_platform.c
>
> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
> index 9d9e453..50549b5 100644
> --- a/drivers/net/can/Kconfig
> +++ b/drivers/net/can/Kconfig
> @@ -86,6 +86,8 @@ source "drivers/net/can/mscan/Kconfig"
>
> source "drivers/net/can/sja1000/Kconfig"
>
> +source "drivers/net/can/c_can/Kconfig"
> +
> source "drivers/net/can/usb/Kconfig"
>
> config CAN_DEBUG_DEVICES
> diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
> index 0057537..c3efeb3 100644
> --- a/drivers/net/can/Makefile
> +++ b/drivers/net/can/Makefile
> @@ -11,6 +11,7 @@ obj-y += usb/
>
> obj-$(CONFIG_CAN_SJA1000) += sja1000/
> obj-$(CONFIG_CAN_MSCAN) += mscan/
> +obj-$(CONFIG_CAN_C_CAN) += c_can/
> obj-$(CONFIG_CAN_AT91) += at91_can.o
> obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
> obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
> diff --git a/drivers/net/can/c_can/Kconfig b/drivers/net/can/c_can/Kconfig
> new file mode 100644
> index 0000000..ffb9773
> --- /dev/null
> +++ b/drivers/net/can/c_can/Kconfig
> @@ -0,0 +1,15 @@
> +menuconfig CAN_C_CAN
> + tristate "Bosch C_CAN devices"
> + depends on CAN_DEV && HAS_IOMEM
> +
> +if CAN_C_CAN
> +
> +config CAN_C_CAN_PLATFORM
> + tristate "Generic Platform Bus based C_CAN driver"
> + ---help---
> + This driver adds support for the C_CAN chips connected to
> + the "platform bus" (Linux abstraction for directly to the
> + processor attached devices) which can be found on various
> + boards from ST Microelectronics (http://www.st.com)
> + like the SPEAr1310 and SPEAr320 evaluation boards.
> +endif
> diff --git a/drivers/net/can/c_can/Makefile b/drivers/net/can/c_can/Makefile
> new file mode 100644
> index 0000000..9273f6d
> --- /dev/null
> +++ b/drivers/net/can/c_can/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Makefile for the Bosch C_CAN controller drivers.
> +#
> +
> +obj-$(CONFIG_CAN_C_CAN) += c_can.o
> +obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o
> +
> +ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
> diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
> new file mode 100644
> index 0000000..06e1553
> --- /dev/null
> +++ b/drivers/net/can/c_can/c_can.c
> @@ -0,0 +1,953 @@
> +/*
> + * CAN bus driver for Bosch C_CAN controller
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> + *
> + * Borrowed heavily from the C_CAN driver originally written by:
> + * Copyright (C) 2007
> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
> + *
> + * TX and RX NAPI implementation has been borrowed from at91 CAN driver
> + * written by:
I've just cleaned up the RX implementation, have a look at [1] and [2].
> + * Copyright
> + * (C) 2007 by Hans J. Koch <hjk-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
^^^^^^^^^^^^^^^^^^^
Hans has recently changed his email address, it's "hjk-vqZO0P4V72/QD6PfKP4TzA@public.gmane.org"
> + * (C) 2008, 2009 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + *
> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
> + * Bosch C_CAN user manual can be obtained from:
> + * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
> + * users_manual_c_can.pdf
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/version.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/netdevice.h>
> +#include <linux/if_arp.h>
> +#include <linux/if_ether.h>
> +#include <linux/list.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +
> +#include <linux/can.h>
> +#include <linux/can/dev.h>
> +#include <linux/can/error.h>
> +
> +#include "c_can.h"
> +
> +static struct can_bittiming_const c_can_bittiming_const = {
> + .name = KBUILD_MODNAME,
> + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
> + .tseg1_max = 16,
> + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
> + .tseg2_max = 8,
> + .sjw_max = 4,
> + .brp_min = 1,
> + .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
> + .brp_inc = 1,
> +};
> +
> +static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
> +{
> + return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
> + C_CAN_MSG_OBJ_TX_FIRST;
> +}
> +
> +static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
> +{
> + return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
> + C_CAN_MSG_OBJ_TX_FIRST;
> +}
> +
> +static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
> +{
> + u32 val = priv->read_reg(priv, reg);
> + val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
> + return val;
> +}
> +
> +static void c_can_enable_all_interrupts(struct c_can_priv *priv,
> + int enable)
> +{
> + unsigned int cntrl_save = priv->read_reg(priv,
> + &priv->regs->control);
> +
> + if (enable)
> + cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
> + else
> + cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
> +
> + priv->write_reg(priv, &priv->regs->control, cntrl_save);
> +}
> +
> +static inline int c_can_check_busy_status(struct c_can_priv *priv, int iface)
> +{
> + int count = MIN_TIMEOUT_VALUE;
I'd insert a blank line, here.
> + while (count && priv->read_reg(priv,
> + &priv->regs->intf[iface].com_reg) &
> + IF_COMR_BUSY) {
> + count--;
> + udelay(1);
> + }
> +
> + return count;
> +}
> +
> +static inline void c_can_object_get(struct net_device *dev,
> + int iface, int objno, int mask)
> +{
> + int ret;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /*
> + * As per specs, after writting the message object number in the
> + * IF command request register the transfer b/w interface
> + * register and message RAM must be complete in 6 CAN-CLK
> + * period.
> + */
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].com_mask,
> + IFX_WRITE_LOW_16BIT(mask));
> + priv->write_reg(priv, &priv->regs->intf[iface].com_reg,
> + IFX_WRITE_LOW_16BIT(objno + 1));
> +
> + ret = c_can_check_busy_status(priv, iface);
> + if (!ret)
> + dev_err(dev->dev.parent, "timed out in object get\n");
> +}
> +
> +static inline void c_can_object_put(struct net_device *dev,
> + int iface, int objno, int mask)
> +{
> + int ret;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /*
> + * As per specs, after writting the message object number in the
> + * IF command request register the transfer b/w interface
> + * register and message RAM must be complete in 6 CAN-CLK
> + * period.
> + */
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].com_mask,
> + (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
> + priv->write_reg(priv, &priv->regs->intf[iface].com_reg,
> + IFX_WRITE_LOW_16BIT(objno + 1));
> +
> + ret = c_can_check_busy_status(priv, iface);
> + if (!ret)
> + dev_err(dev->dev.parent, "timed out in object put\n");
> +}
> +
> +int c_can_write_msg_object(struct net_device *dev,
> + int iface, struct can_frame *frame, int objno)
> +{
> + int i;
> + u16 flags = 0;
> + unsigned int id;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + if (!(frame->can_id & CAN_RTR_FLAG))
> + flags |= IF_ARB_TRANSMIT;
> +
> + if (frame->can_id & CAN_EFF_FLAG) {
> + id = frame->can_id & CAN_EFF_MASK;
> + flags |= IF_ARB_MSGXTD;
> + } else
> + id = ((frame->can_id & CAN_SFF_MASK) << 18);
> +
> + flags |= IF_ARB_MSGVAL;
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].arb1,
> + IFX_WRITE_LOW_16BIT(id));
> + priv->write_reg(priv, &priv->regs->intf[iface].arb2, flags |
> + IFX_WRITE_HIGH_16BIT(id));
> +
> + for (i = 0; i < frame->can_dlc; i += 2) {
> + priv->write_reg(priv, &priv->regs->intf[iface].data[i / 2],
> + frame->data[i] | (frame->data[i + 1] << 8));
> + }
> +
> + return frame->can_dlc;
> +}
> +
> +static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
> + int iface, int ctrl_mask,
> + int obj)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl,
> + ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
> + c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
> +
> +}
> +
> +static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
> + int iface,
> + int ctrl_mask)
> +{
> + int i;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + for (i = 0; i < C_CAN_MSG_RX_LOW_LAST; i++) {
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl,
> + ctrl_mask & ~(IF_MCONT_MSGLST |
> + IF_MCONT_INTPND | IF_MCONT_NEWDAT));
> + c_can_object_put(dev, iface, i + 1, IF_COMM_CONTROL);
> + }
> +}
> +
> +static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
> + int iface, int ctrl_mask,
> + int obj)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl,
> + ctrl_mask & ~(IF_MCONT_MSGLST |
> + IF_MCONT_INTPND | IF_MCONT_NEWDAT));
> + c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
> +
> +}
> +
> +static void c_can_handle_lost_msg_obj(struct net_device *dev,
> + int iface, int objno)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> + struct sk_buff *skb;
> + struct can_frame *frame;
> +
> + dev_err(dev->dev.parent, "msg lost in buffer %d\n", objno);
> +
> + c_can_object_get(dev, iface, objno, IF_COMM_ALL &
> + ~IF_COMM_TXRQST);
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl,
> + IF_MCONT_CLR_MSGLST);
> +
> + c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
> +
> + /* create an error msg */
> + skb = alloc_can_err_skb(dev, &frame);
> + if (unlikely(!skb))
> + return;
> +
> + frame->can_id |= CAN_ERR_CRTL;
> + frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
> + stats->rx_errors++;
> + stats->rx_over_errors++;
> +
> + netif_receive_skb(skb);
> +}
> +
> +static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl,
> + int objno)
> +{
> + u16 flags, data;
> + int i;
> + unsigned int val;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> + struct sk_buff *skb;
> + struct can_frame *frame;
> +
> + skb = alloc_can_skb(dev, &frame);
> + if (!skb) {
> + stats->rx_dropped++;
> + return -ENOMEM;
> + }
> +
> + frame->can_dlc = get_can_dlc(ctrl & 0x0F);
> +
> + for (i = 0; i < frame->can_dlc; i += 2) {
> + data = priv->read_reg(priv,
> + &priv->regs->intf[iface].data[i / 2]);
> + frame->data[i] = data;
> + frame->data[i + 1] = data >> 8;
> + }
> +
> + flags = priv->read_reg(priv, &priv->regs->intf[iface].arb2);
> + val = priv->read_reg(priv, &priv->regs->intf[iface].arb1) |
> + (flags << 16);
> +
> + if (flags & IF_ARB_MSGXTD)
> + frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
> + else
> + frame->can_id = (val >> 18) & CAN_SFF_MASK;
> +
> + if (flags & IF_ARB_TRANSMIT)
> + frame->can_id |= CAN_RTR_FLAG;
> +
> + netif_receive_skb(skb);
> +
> + stats->rx_packets++;
> + stats->rx_bytes += frame->can_dlc;
> +
> + return 0;
> +}
> +
> +static void c_can_setup_receive_object(struct net_device *dev, int iface,
> + int objno, unsigned int mask,
> + unsigned int id, unsigned int mcont)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].mask1,
> + IFX_WRITE_LOW_16BIT(mask));
> + priv->write_reg(priv, &priv->regs->intf[iface].mask2,
> + IFX_WRITE_HIGH_16BIT(mask));
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].arb1,
> + IFX_WRITE_LOW_16BIT(id));
> + priv->write_reg(priv, &priv->regs->intf[iface].arb2,
> + (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl, mcont);
> + c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
> + dev_dbg(dev->dev.parent, "obj no:%d, msgval:0x%08x\n", objno,
> + c_can_read_reg32(priv, &priv->regs->msgval1));
> +
> +}
> +
> +static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + priv->write_reg(priv, &priv->regs->intf[iface].arb1, 0);
> + priv->write_reg(priv, &priv->regs->intf[iface].arb2, 0);
> + priv->write_reg(priv, &priv->regs->intf[iface].msg_cntrl, 0);
> +
> + c_can_object_put(dev, iface, objno,
> + IF_COMM_ARB | IF_COMM_CONTROL);
> + dev_dbg(dev->dev.parent, "obj no:%d, msgval:0x%08x\n", objno,
> + c_can_read_reg32(priv, &priv->regs->msgval1));
> +
> +}
> +
> +static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
> + struct net_device *dev)
> +{
> + u32 val;
> + u32 msg_obj_no;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct can_frame *frame = (struct can_frame *)skb->data;
> +
> + if (can_dropped_invalid_skb(dev, skb))
> + return NETDEV_TX_OK;
> +
> + msg_obj_no = get_tx_next_msg_obj(priv);
> +
> + /* prepare message object for transmission */
> + val = c_can_write_msg_object(dev, 0, frame, msg_obj_no);
> +
> + /* enable interrupt for this message object */
> + priv->write_reg(priv, &priv->regs->intf[0].msg_cntrl,
> + IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
> + (val & 0xf));
> + c_can_object_put(dev, 0, msg_obj_no, IF_COMM_ALL);
> +
> + can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
> +
> + priv->tx_next++;
> + if ((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
> + netif_stop_queue(dev);
> +
> + return NETDEV_TX_OK;
> +}
> +
> +static int c_can_set_bittiming(struct net_device *dev)
> +{
> + unsigned int reg_btr, reg_brpe, ctrl_save;
> + u8 brp, brpe, sjw, tseg1, tseg2;
> + u32 ten_bit_brp;
> + struct c_can_priv *priv = netdev_priv(dev);
> + const struct can_bittiming *bt = &priv->can.bittiming;
> +
> + /* c_can provides a 6-bit brp and 4-bit brpe fields */
> + ten_bit_brp = bt->brp - 1;
> + brp = ten_bit_brp & BTR_BRP_MASK;
> + brpe = ten_bit_brp >> 6;
> +
> + sjw = bt->sjw - 1;
> + tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
> + tseg2 = bt->phase_seg2 - 1;
> + reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
> + (tseg2 << BTR_TSEG2_SHIFT);
> + reg_brpe = brpe & BRP_EXT_BRPE_MASK;
> +
> + dev_info(dev->dev.parent,
> + "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
> +
> + ctrl_save = priv->read_reg(priv, &priv->regs->control);
> + priv->write_reg(priv, &priv->regs->control,
> + ctrl_save | CONTROL_CCE | CONTROL_INIT);
> + priv->write_reg(priv, &priv->regs->btr, reg_btr);
> + priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe);
> + priv->write_reg(priv, &priv->regs->control, ctrl_save);
> +
> + return 0;
> +}
> +
> +/*
> + * Configure C_CAN message objects for Tx and Rx purposes:
> + * C_CAN provides a total of 32 message objects that can be configured
> + * either for Tx or Rx purposes. Here the first 16 message objects are used as
> + * a reception FIFO. The end of reception FIFO is signified by the EoB bit
> + * being SET. The remaining 16 message objects are kept aside for Tx purposes.
> + * See user guide document for further details on configuring message
> + * objects.
> + */
> +static void c_can_configure_msg_objects(struct net_device *dev)
> +{
> + int i;
> +
> + /* first invalidate all message objects */
> + for (i = 0; i <= C_CAN_NO_OF_OBJECTS; i++)
> + c_can_inval_msg_object(dev, 0, i);
> +
> + /* setup receive message objects */
> + for (i = C_CAN_MSG_OBJ_RX_FIRST + 1 ; i < C_CAN_MSG_OBJ_RX_LAST; i++)
> + c_can_setup_receive_object(dev, 0, i, 0, 0,
> + (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
> +
> + c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
> + IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
> +}
> +
> +/*
> + * Configure C_CAN chip:
> + * - enable/disable auto-retransmission
> + * - set operating mode
> + * - configure message objects
> + */
> +static void c_can_chip_config(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
> + /* disable automatic retransmission */
> + priv->write_reg(priv, &priv->regs->control,
> + CONTROL_DISABLE_AR);
> + else
> + /* enable automatic retransmission */
> + priv->write_reg(priv, &priv->regs->control,
> + CONTROL_ENABLE_AR);
> +
> + if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
> + CAN_CTRLMODE_LOOPBACK)) {
> + /* loopback + silent mode : useful for hot self-test */
> + priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
> + priv->write_reg(priv, &priv->regs->test,
> + TEST_LBACK | TEST_SILENT);
> + } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
> + /* loopback mode : useful for self-test function */
> + priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
> + priv->write_reg(priv, &priv->regs->test, TEST_LBACK);
> + } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
> + /* silent mode : bus-monitoring mode */
> + priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
> + CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
> + priv->write_reg(priv, &priv->regs->test, TEST_SILENT);
> + } else
> + /* normal mode*/
> + priv->write_reg(priv, &priv->regs->control,
> + CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
> +
> + /* configure message objects */
> + c_can_configure_msg_objects(dev);
> +}
> +
> +static void c_can_start(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* enable status change, error and module interrupts */
> + c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
> +
> + /* basic c_can configuration */
> + c_can_chip_config(dev);
> +
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> +
> + /* reset tx helper pointers */
> + priv->tx_next = priv->tx_echo = 0;
> +}
> +
> +static void c_can_stop(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* disable all interrupts */
> + c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> +
> + /* set the state as STOPPED */
> + priv->can.state = CAN_STATE_STOPPED;
> +}
> +
> +static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
> +{
> + switch (mode) {
> + case CAN_MODE_START:
> + c_can_start(dev);
> + netif_wake_queue(dev);
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static int c_can_get_berr_counter(const struct net_device *dev,
> + struct can_berr_counter *bec)
> +{
> + unsigned int reg_err_counter;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
> + bec->rxerr = (reg_err_counter & ERR_COUNTER_REC_MASK) >>
> + ERR_COUNTER_REC_SHIFT;
> + bec->txerr = reg_err_counter & ERR_COUNTER_TEC_MASK;
> +
> + return 0;
> +}
> +
> +/*
> + * theory of operation:
> + *
> + * priv->tx_echo holds the number of the oldest can_frame put for
> + * transmission into the hardware, but not yet ACKed by the CAN tx
> + * complete IRQ.
> + *
> + * We iterate from priv->tx_echo to priv->tx_next and check if the
> + * packet has been transmitted, echo it back to the CAN framework.
> + * If we discover a not yet transmitted package, stop looking for more.
> + */
> +static void c_can_do_tx(struct net_device *dev)
> +{
> + u32 val;
> + u32 msg_obj_no;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> +
> + for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
> + msg_obj_no = get_tx_echo_msg_obj(priv);
> + c_can_inval_msg_object(dev, 0, msg_obj_no);
> + val = c_can_read_reg32(priv, &priv->regs->txrqst1);
> + if (!(val & (1 << msg_obj_no))) {
> + can_get_echo_skb(dev,
> + msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
> + stats->tx_bytes += priv->read_reg(priv,
> + &priv->regs->intf[0].msg_cntrl)
> + & IF_MCONT_DLC_MASK;
> + stats->tx_packets++;
> + }
> + }
> +
> + /* restart queue if wrap-up or if queue stalled on last pkt */
> + if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
> + ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
> + netif_wake_queue(dev);
> +}
> +
> +/*
> + * theory of operation:
> + *
> + * c_can core saves a received CAN message into the first free message
> + * object it finds free (starting with the lowest). Bits NEWDAT and
> + * INTPND are set for this message object indicating that a new message
> + * has arrived. To work-around this issue, we keep two groups of message
> + * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
> + *
> + * To ensure in-order frame reception we use the following
> + * approach while re-activating a message object to receive further
> + * frames:
> + * - if the current message object number is lower than
> + * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
> + * the INTPND bit.
> + * - if the current message object number is equal to
> + * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
> + * receive message objects.
> + * - if the current message object number is greater than
> + * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
> + * only this message object.
> + */
> +static int c_can_do_rx_poll(struct net_device *dev, int quota)
> +{
> + u32 num_rx_pkts = 0;
> + unsigned int msg_obj, msg_ctrl_save;
> + struct c_can_priv *priv = netdev_priv(dev);
> + u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1);
> +
> + for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
> + msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
> + msg_obj++) {
> + if (val & (1 << msg_obj)) {
what about using find_next_bit here?
> + c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
> + ~IF_COMM_TXRQST);
> + msg_ctrl_save = priv->read_reg(priv,
> + &priv->regs->intf[0].msg_cntrl);
> +
> + if (msg_ctrl_save & IF_MCONT_EOB)
> + return num_rx_pkts;
> +
> + if (msg_ctrl_save & IF_MCONT_MSGLST) {
> + c_can_handle_lost_msg_obj(dev, 0, msg_obj);
> + num_rx_pkts++;
> + quota--;
> + continue;
> + }
> +
> + if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
> + continue;
> +
> + /* read the data from the message object */
> + c_can_read_msg_object(dev, 0, msg_ctrl_save, msg_obj);
> +
> + if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
> + c_can_mark_rx_msg_obj(dev, 0,
> + msg_ctrl_save, msg_obj);
> + else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
> + /* activate this msg obj */
> + c_can_activate_rx_msg_obj(dev, 0,
> + msg_ctrl_save, msg_obj);
> + else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
> + /* activate all lower message objects */
> + c_can_activate_all_lower_rx_msg_obj(dev,
> + 0, msg_ctrl_save);
> +
> + num_rx_pkts++;
> + quota--;
> + }
> + val = c_can_read_reg32(priv, &priv->regs->intpnd1);
> + }
> +
> + return num_rx_pkts;
> +}
> +
> +static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
> +{
> + return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
> + (priv->current_status & STATUS_LEC_MASK);
> +}
> +
> +static int c_can_err(struct net_device *dev,
> + enum c_can_bus_error_types error_type,
> + enum c_can_lec_type lec_type)
> +{
> + unsigned int reg_err_counter;
> + unsigned int rx_err_passive;
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct net_device_stats *stats = &dev->stats;
> + struct can_frame *cf;
> + struct sk_buff *skb;
> + struct can_berr_counter bec;
> +
> + /* propogate the error condition to the CAN stack */
> + skb = alloc_can_err_skb(dev, &cf);
> + if (unlikely(!skb))
> + return 0;
> +
> + c_can_get_berr_counter(dev, &bec);
> + reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
> + rx_err_passive = (reg_err_counter & ERR_COUNTER_RP_MASK) >>
> + ERR_COUNTER_RP_SHIFT;
> +
> + if (error_type & C_CAN_ERROR_WARNING) {
> + /* error warning state */
> + priv->can.can_stats.error_warning++;
> + priv->can.state = CAN_STATE_ERROR_WARNING;
> + cf->can_id |= CAN_ERR_CRTL;
> + if (bec.rxerr > 96)
> + cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
> + if (bec.txerr > 96)
> + cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
> + }
> + if (error_type & C_CAN_ERROR_PASSIVE) {
> + /* error passive state */
> + priv->can.can_stats.error_passive++;
> + priv->can.state = CAN_STATE_ERROR_PASSIVE;
> + cf->can_id |= CAN_ERR_CRTL;
> + if (rx_err_passive)
> + cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
> + if (bec.txerr > 127)
> + cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
> + }
> + if (error_type & C_CAN_BUS_OFF) {
> + /* bus-off state */
> + priv->can.state = CAN_STATE_BUS_OFF;
> + cf->can_id |= CAN_ERR_BUSOFF;
> + /*
> + * disable all interrupts in bus-off mode to ensure that
> + * the CPU is not hogged down
> + */
> + c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> + can_bus_off(dev);
> + }
> +
> + /*
> + * check for 'last error code' which tells us the
> + * type of the last error to occur on the CAN bus
> + */
> +
> + /* common for all type of bus errors */
> + priv->can.can_stats.bus_error++;
> + stats->rx_errors++;
> + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
> + cf->data[2] |= CAN_ERR_PROT_UNSPEC;
> +
> + switch (lec_type) {
> + case LEC_STUFF_ERROR:
> + dev_dbg(dev->dev.parent, "stuff error\n");
> + cf->data[2] |= CAN_ERR_PROT_STUFF;
> + break;
> +
> + case LEC_FORM_ERROR:
> + dev_dbg(dev->dev.parent, "form error\n");
> + cf->data[2] |= CAN_ERR_PROT_FORM;
> + break;
> +
> + case LEC_ACK_ERROR:
> + dev_dbg(dev->dev.parent, "ack error\n");
> + cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
> + CAN_ERR_PROT_LOC_ACK_DEL);
> + break;
> +
> + case LEC_BIT1_ERROR:
> + dev_dbg(dev->dev.parent, "bit1 error\n");
> + cf->data[2] |= CAN_ERR_PROT_BIT1;
> + break;
> +
> + case LEC_BIT0_ERROR:
> + dev_dbg(dev->dev.parent, "bit0 error\n");
> + cf->data[2] |= CAN_ERR_PROT_BIT0;
> + break;
> +
> + case LEC_CRC_ERROR:
> + dev_dbg(dev->dev.parent, "CRC error\n");
> + cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
> + CAN_ERR_PROT_LOC_CRC_DEL);
> + break;
> + }
> +
> + netif_receive_skb(skb);
> + stats->rx_packets++;
> + stats->rx_bytes += cf->can_dlc;
> +
> + return 1;
> +}
> +
> +static int c_can_poll(struct napi_struct *napi, int quota)
> +{
> + u16 irqstatus;
> + int lec_type = 0;
> + int work_done = 0;
> + struct net_device *dev = napi->dev;
> + struct c_can_priv *priv = netdev_priv(dev);
> + enum c_can_bus_error_types error_type = C_CAN_NO_ERROR;
> +
> + irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
> +
> + /* status events have the highest priority */
> + if (irqstatus == STATUS_INTERRUPT) {
> + priv->current_status = priv->read_reg(priv,
> + &priv->regs->status);
> +
> + /* handle Tx/Rx events */
> + if (priv->current_status & STATUS_TXOK)
> + priv->write_reg(priv, &priv->regs->status,
> + priv->current_status & ~STATUS_TXOK);
> +
> + if (priv->current_status & STATUS_RXOK)
> + priv->write_reg(priv, &priv->regs->status,
> + priv->current_status & ~STATUS_RXOK);
> +
> + /* handle bus error events */
> + if (priv->current_status & STATUS_EWARN) {
> + dev_dbg(dev->dev.parent,
> + "entered error warning state\n");
> + error_type = C_CAN_ERROR_WARNING;
> + }
> + if ((priv->current_status & STATUS_EPASS) &&
> + (!(priv->last_status & STATUS_EPASS))) {
> + dev_dbg(dev->dev.parent,
> + "entered error passive state\n");
> + error_type = C_CAN_ERROR_PASSIVE;
> + }
> + if ((priv->current_status & STATUS_BOFF) &&
> + (!(priv->last_status & STATUS_BOFF))) {
> + dev_dbg(dev->dev.parent,
> + "entered bus off state\n");
> + error_type = C_CAN_BUS_OFF;
> + }
> +
> + /* handle bus recovery events */
> + if ((!(priv->current_status & STATUS_EPASS)) &&
> + (priv->last_status & STATUS_EPASS)) {
> + dev_dbg(dev->dev.parent,
> + "left error passive state\n");
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> + }
> + if ((!(priv->current_status & STATUS_BOFF)) &&
> + (priv->last_status & STATUS_BOFF)) {
> + dev_dbg(dev->dev.parent,
> + "left bus off state\n");
> + priv->can.state = CAN_STATE_ERROR_ACTIVE;
> + }
> +
> + priv->last_status = priv->current_status;
> +
> + /* handle error on the bus */
> + lec_type = c_can_has_and_handle_berr(priv);
> + if (lec_type && (error_type != C_CAN_NO_ERROR))
> + work_done += c_can_err(dev, error_type, lec_type);
> + } else if ((irqstatus > C_CAN_MSG_OBJ_RX_FIRST) &&
> + (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
> + /* handle events corresponding to receive message objects */
> + work_done += c_can_do_rx_poll(dev, (quota - work_done));
> + } else if ((irqstatus > C_CAN_MSG_OBJ_TX_FIRST) &&
> + (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
> + /* handle events corresponding to transmit message objects */
> + c_can_do_tx(dev);
> + }
> +
> + if (work_done < quota) {
> + napi_complete(napi);
> + /* enable all IRQs */
> + c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
> + }
> +
> + return work_done;
> +}
> +
> +static irqreturn_t c_can_isr(int irq, void *dev_id)
> +{
> + struct net_device *dev = (struct net_device *)dev_id;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* disable all interrupts and schedule the NAPI */
> + c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> + napi_schedule(&priv->napi);
> +
> + return IRQ_HANDLED;
> +}
Have a look at the pch_can interrupt handler, it supports shared irqs.
> +
> +static int c_can_open(struct net_device *dev)
> +{
> + int err;
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* open the can device */
> + err = open_candev(dev);
> + if (err) {
> + dev_err(dev->dev.parent, "failed to open can device\n");
> + return err;
> + }
> +
> + /* register interrupt handler */
> + err = request_irq(dev->irq, &c_can_isr, priv->irq_flags, dev->name,
> + dev);
> + if (err < 0) {
> + dev_err(dev->dev.parent, "failed to request interrupt\n");
> + goto exit_irq_fail;
> + }
> +
> + /* start the c_can controller */
> + c_can_start(dev);
> +
> + napi_enable(&priv->napi);
> + netif_start_queue(dev);
> +
> + return 0;
> +
> +exit_irq_fail:
> + close_candev(dev);
> + return err;
> +}
> +
> +static int c_can_close(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + netif_stop_queue(dev);
> + napi_disable(&priv->napi);
> + c_can_stop(dev);
> + free_irq(dev->irq, dev);
> + close_candev(dev);
> +
> + return 0;
> +}
> +
> +struct net_device *alloc_c_can_dev(void)
Please model after alloc_sja1000_dev:
struct net_device *alloc_sja1000dev(int sizeof_priv)
The private for the _user_ of alloc_c_can_dev is behind the sja1000
private, so you can get rid of the void *priv member in the struct
c_can_priv. (see below)
> +{
> + struct net_device *dev;
> + struct c_can_priv *priv;
> +
> + dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
> + if (!dev)
> + return NULL;
> +
> + priv = netdev_priv(dev);
> + netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
> +
> + priv->dev = dev;
> + priv->can.bittiming_const = &c_can_bittiming_const;
> + priv->can.do_set_bittiming = c_can_set_bittiming;
> + priv->can.do_set_mode = c_can_set_mode;
> + priv->can.do_get_berr_counter = c_can_get_berr_counter;
> + priv->can.ctrlmode_supported = CAN_CTRLMODE_ONE_SHOT |
> + CAN_CTRLMODE_LOOPBACK |
> + CAN_CTRLMODE_LISTENONLY |
> + CAN_CTRLMODE_BERR_REPORTING;
> +
> + return dev;
> +}
> +EXPORT_SYMBOL_GPL(alloc_c_can_dev);
> +
> +void free_c_can_dev(struct net_device *dev)
> +{
> + free_candev(dev);
> +}
> +EXPORT_SYMBOL_GPL(free_c_can_dev);
> +
> +static const struct net_device_ops c_can_netdev_ops = {
> + .ndo_open = c_can_open,
> + .ndo_stop = c_can_close,
> + .ndo_start_xmit = c_can_start_xmit,
> +};
> +
> +int register_c_can_dev(struct net_device *dev)
> +{
> + dev->flags |= IFF_ECHO; /* we support local echo */
> + dev->netdev_ops = &c_can_netdev_ops;
> +
> + return register_candev(dev);
> +}
> +EXPORT_SYMBOL_GPL(register_c_can_dev);
> +
> +void unregister_c_can_dev(struct net_device *dev)
> +{
> + struct c_can_priv *priv = netdev_priv(dev);
> +
> + /* disable all interrupts */
> + c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
> +
> + unregister_candev(dev);
> +}
> +EXPORT_SYMBOL_GPL(unregister_c_can_dev);
> +
> +MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
> diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
> new file mode 100644
> index 0000000..6d24432
> --- /dev/null
> +++ b/drivers/net/can/c_can/c_can.h
> @@ -0,0 +1,235 @@
> +/*
> + * CAN bus driver for Bosch C_CAN controller
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> + *
> + * Borrowed heavily from the C_CAN driver originally written by:
> + * Copyright (C) 2007
> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
> + *
> + * TX and RX NAPI implementation has been borrowed from at91 CAN driver
> + * written by:
> + * Copyright
> + * (C) 2007 by Hans J. Koch <hjk-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
> + * (C) 2008, 2009 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
IMHO you can drop the at91 copyright reference here.
> + *
> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
> + * Bosch C_CAN user manual can be obtained from:
> + * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
> + * users_manual_c_can.pdf
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef C_CAN_H
> +#define C_CAN_H
> +
> +/* control register */
> +#define CONTROL_TEST BIT(7)
> +#define CONTROL_CCE BIT(6)
> +#define CONTROL_DISABLE_AR BIT(5)
> +#define CONTROL_ENABLE_AR (0 << 5)
> +#define CONTROL_EIE BIT(3)
> +#define CONTROL_SIE BIT(2)
> +#define CONTROL_IE BIT(1)
> +#define CONTROL_INIT BIT(0)
> +
> +/* test register */
> +#define TEST_RX BIT(7)
> +#define TEST_TX1 BIT(6)
> +#define TEST_TX2 BIT(5)
> +#define TEST_LBACK BIT(4)
> +#define TEST_SILENT BIT(3)
> +#define TEST_BASIC BIT(2)
> +
> +/* status register */
> +#define STATUS_BOFF BIT(7)
> +#define STATUS_EWARN BIT(6)
> +#define STATUS_EPASS BIT(5)
> +#define STATUS_RXOK BIT(4)
> +#define STATUS_TXOK BIT(3)
> +#define STATUS_LEC_MASK 0x07
> +
> +/* error counter register */
> +#define ERR_COUNTER_TEC_MASK 0xff
> +#define ERR_COUNTER_TEC_SHIFT 0
> +#define ERR_COUNTER_REC_SHIFT 8
> +#define ERR_COUNTER_REC_MASK (0x7f << ERR_COUNTER_REC_SHIFT)
> +#define ERR_COUNTER_RP_SHIFT 15
> +#define ERR_COUNTER_RP_MASK (0x1 << ERR_COUNTER_RP_SHIFT)
> +
> +/* bit-timing register */
> +#define BTR_BRP_MASK 0x3f
> +#define BTR_BRP_SHIFT 0
> +#define BTR_SJW_SHIFT 6
> +#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
> +#define BTR_TSEG1_SHIFT 8
> +#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
> +#define BTR_TSEG2_SHIFT 12
> +#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
> +
> +/* brp extension register */
> +#define BRP_EXT_BRPE_MASK 0x0f
> +#define BRP_EXT_BRPE_SHIFT 0
> +
> +/* IFx command request */
> +#define IF_COMR_BUSY BIT(15)
> +
> +/* IFx command mask */
> +#define IF_COMM_WR BIT(7)
> +#define IF_COMM_MASK BIT(6)
> +#define IF_COMM_ARB BIT(5)
> +#define IF_COMM_CONTROL BIT(4)
> +#define IF_COMM_CLR_INT_PND BIT(3)
> +#define IF_COMM_TXRQST BIT(2)
> +#define IF_COMM_DATAA BIT(1)
> +#define IF_COMM_DATAB BIT(0)
> +#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
> + IF_COMM_CONTROL | IF_COMM_TXRQST | \
> + IF_COMM_DATAA | IF_COMM_DATAB)
> +
> +/* IFx arbitration */
> +#define IF_ARB_MSGVAL BIT(15)
> +#define IF_ARB_MSGXTD BIT(14)
> +#define IF_ARB_TRANSMIT BIT(13)
> +
> +/* IFx message control */
> +#define IF_MCONT_NEWDAT BIT(15)
> +#define IF_MCONT_MSGLST BIT(14)
> +#define IF_MCONT_CLR_MSGLST (0 << 14)
> +#define IF_MCONT_INTPND BIT(13)
> +#define IF_MCONT_UMASK BIT(12)
> +#define IF_MCONT_TXIE BIT(11)
> +#define IF_MCONT_RXIE BIT(10)
> +#define IF_MCONT_RMTEN BIT(9)
> +#define IF_MCONT_TXRQST BIT(8)
> +#define IF_MCONT_EOB BIT(7)
> +#define IF_MCONT_DLC_MASK 0xf
> +
> +/*
> + * IFx register masks:
> + * allow easy operation on 16-bit registers when the
> + * argument is 32-bit instead
> + */
> +#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
> +#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
> +
> +/* message object split */
> +#define C_CAN_NO_OF_OBJECTS 31
> +#define C_CAN_MSG_OBJ_RX_NUM 16
> +#define C_CAN_MSG_OBJ_TX_NUM 16
> +
> +#define C_CAN_MSG_OBJ_RX_FIRST 0
> +#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
> + C_CAN_MSG_OBJ_RX_NUM - 1)
> +
> +#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
> +#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
> + C_CAN_MSG_OBJ_TX_NUM - 1)
> +
> +#define C_CAN_MSG_OBJ_RX_SPLIT 8
> +#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
> +
> +#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
> +#define RECEIVE_OBJECT_BITS 0x0000ffff
> +
> +/* status interrupt */
> +#define STATUS_INTERRUPT 0x8000
> +
> +/* global interrupt masks */
> +#define ENABLE_ALL_INTERRUPTS 1
> +#define DISABLE_ALL_INTERRUPTS 0
> +
> +/* minimum timeout for checking BUSY status */
> +#define MIN_TIMEOUT_VALUE 6
> +
> +/* napi related */
> +#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
> +
> +/* c_can IF registers */
> +struct c_can_if_regs {
> + u16 com_reg;
> + u16 com_mask;
> + u16 mask1;
> + u16 mask2;
> + u16 arb1;
> + u16 arb2;
> + u16 msg_cntrl;
> + u16 data[4];
> + u16 _reserved[13];
> +};
> +
> +/* c_can hardware registers */
> +struct c_can_regs {
> + u16 control;
> + u16 status;
> + u16 err_cnt;
> + u16 btr;
> + u16 interrupt;
> + u16 test;
> + u16 brp_ext;
> + u16 _reserved1;
> + struct c_can_if_regs intf[2]; /* [0] = IF1 and [1] = IF2 */
> + u16 _reserved2[8];
> + u16 txrqst1;
> + u16 txrqst2;
> + u16 _reserved3[6];
> + u16 newdat1;
> + u16 newdat2;
> + u16 _reserved4[6];
> + u16 intpnd1;
> + u16 intpnd2;
> + u16 _reserved5[6];
> + u16 msgval1;
> + u16 msgval2;
> + u16 _reserved6[6];
> +};
> +
> +/* c_can lec values */
> +enum c_can_lec_type {
> + LEC_STUFF_ERROR = 1,
> + LEC_FORM_ERROR,
> + LEC_ACK_ERROR,
> + LEC_BIT1_ERROR,
> + LEC_BIT0_ERROR,
> + LEC_CRC_ERROR,
> +};
> +
> +/*
> + * c_can error types:
> + * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
> + */
> +enum c_can_bus_error_types {
> + C_CAN_NO_ERROR = 0,
> + C_CAN_BUS_OFF,
> + C_CAN_ERROR_WARNING,
> + C_CAN_ERROR_PASSIVE,
> +};
> +
> +/* c_can private data structure */
> +struct c_can_priv {
> + struct can_priv can; /* must be the first member */
> + struct napi_struct napi;
> + struct net_device *dev;
> + int tx_object;
> + int current_status;
> + int last_status;
> + u16 (*read_reg) (struct c_can_priv *priv, void *reg);
> + void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val);
> + struct c_can_regs __iomem *regs;
> + unsigned long irq_flags; /* for request_irq() */
> + unsigned int tx_next;
> + unsigned int tx_echo;
> + void *priv; /* for board-specific data */
^^^^^^^^^^
here
> +};
> +
> +struct net_device *alloc_c_can_dev(void);
> +void free_c_can_dev(struct net_device *dev);
> +int register_c_can_dev(struct net_device *dev);
> +void unregister_c_can_dev(struct net_device *dev);
> +
> +#endif /* C_CAN_H */
> diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
> new file mode 100644
> index 0000000..6ec0471
> --- /dev/null
> +++ b/drivers/net/can/c_can/c_can_platform.c
> @@ -0,0 +1,208 @@
> +/*
> + * Platform CAN bus driver for Bosch C_CAN controller
> + *
> + * Copyright (C) 2010 ST Microelectronics
> + * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
> + *
> + * Borrowed heavily from the C_CAN driver originally written by:
> + * Copyright (C) 2007
> + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
> + * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
> + *
> + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
> + * Bosch C_CAN user manual can be obtained from:
> + * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
> + * users_manual_c_can.pdf
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/version.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/netdevice.h>
> +#include <linux/if_arp.h>
> +#include <linux/if_ether.h>
> +#include <linux/list.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +
> +#include <linux/can/dev.h>
> +
> +#include "c_can.h"
> +
> +/*
> + * 16-bit c_can registers can be arranged differently in the memory
> + * architecture of different implementations. For example: 16-bit
> + * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
> + * Handle the same by providing a common read/write interface.
> + */
> +static u16 c_can_plat_read_reg_aligned_to_16bit(struct c_can_priv *priv,
> + void *reg)
> +{
> + return readw(reg);
> +}
> +
> +static void c_can_plat_write_reg_aligned_to_16bit(struct c_can_priv *priv,
> + void *reg, u16 val)
> +{
> + writew(val, reg);
> +}
> +
> +static u16 c_can_plat_read_reg_aligned_to_32bit(struct c_can_priv *priv,
> + void *reg)
> +{
> + return readw(reg + (long)reg - (long)priv->regs);
> +}
> +
> +static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv,
> + void *reg, u16 val)
> +{
> + writew(val, reg + (long)reg - (long)priv->regs);
> +}
> +
> +static int __devinit c_can_plat_probe(struct platform_device *pdev)
> +{
> + int ret;
> + void __iomem *addr;
> + struct net_device *dev;
> + struct c_can_priv *priv;
> + struct resource *mem, *irq;
> + struct clk *clk;
> +
> + /* get the appropriate clk */
> + clk = clk_get(&pdev->dev, NULL);
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "no clock defined\n");
> + ret = -ENODEV;
> + goto exit;
> + }
> +
> + /* get the platform data */
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
> + if (!mem || (irq <= 0)) {
> + ret = -ENODEV;
> + goto exit_free_clk;
> + }
> +
> + if (!request_mem_region(mem->start, resource_size(mem),
> + KBUILD_MODNAME)) {
> + dev_err(&pdev->dev, "resource unavailable\n");
> + ret = -ENODEV;
> + goto exit_free_clk;
> + }
> +
> + addr = ioremap(mem->start, resource_size(mem));
> + if (!addr) {
> + dev_err(&pdev->dev, "failed to map can port\n");
> + ret = -ENOMEM;
> + goto exit_release_mem;
> + }
> +
> + /* allocate the c_can device */
> + dev = alloc_c_can_dev();
> + if (!dev) {
> + ret = -ENOMEM;
> + goto exit_iounmap;
> + }
> +
> + priv = netdev_priv(dev);
> +
> + dev->irq = irq->start;
> + priv->irq_flags = irq->flags;
> + priv->regs = addr;
> + priv->can.clock.freq = clk_get_rate(clk);
> + priv->priv = clk;
> +
> + switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
> + case IORESOURCE_MEM_32BIT:
> + priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
> + priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
> + break;
> + case IORESOURCE_MEM_16BIT:
> + default:
> + priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
> + priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
> + break;
> + }
> +
> + platform_set_drvdata(pdev, dev);
> + SET_NETDEV_DEV(dev, &pdev->dev);
> +
> + ret = register_c_can_dev(dev);
> + if (ret) {
> + dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
> + KBUILD_MODNAME, ret);
> + goto exit_free_device;
> + }
> +
> + dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
> + KBUILD_MODNAME, priv->regs, dev->irq);
> + return 0;
> +
> +exit_free_device:
> + platform_set_drvdata(pdev, NULL);
> + free_c_can_dev(dev);
> +exit_iounmap:
> + iounmap(addr);
> +exit_release_mem:
> + release_mem_region(mem->start, resource_size(mem));
> +exit_free_clk:
> + clk_put(clk);
> +exit:
> + dev_err(&pdev->dev, "probe failed\n");
> +
> + return ret;
> +}
> +
> +static int __devexit c_can_plat_remove(struct platform_device *pdev)
> +{
> + struct net_device *dev = platform_get_drvdata(pdev);
> + struct c_can_priv *priv = netdev_priv(dev);
> + struct resource *mem;
> +
> + unregister_c_can_dev(dev);
> + platform_set_drvdata(pdev, NULL);
> +
> + free_c_can_dev(dev);
> + iounmap(priv->regs);
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + release_mem_region(mem->start, resource_size(mem));
> +
> + clk_put(priv->priv);
> +
> + return 0;
> +}
> +
> +static struct platform_driver c_can_plat_driver = {
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .owner = THIS_MODULE,
> + },
> + .probe = c_can_plat_probe,
> + .remove = __devexit_p(c_can_plat_remove),
> +};
> +
> +static int __init c_can_plat_init(void)
> +{
> + return platform_driver_register(&c_can_plat_driver);
> +}
> +module_init(c_can_plat_init);
> +
> +static void __exit c_can_plat_exit(void)
> +{
> + platform_driver_unregister(&c_can_plat_driver);
> +}
> +module_exit(c_can_plat_exit);
> +
> +MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
[1]
https://lists.berlios.de/pipermail/socketcan-core/2011-January/005331.html
[2]
http://git.pengutronix.de/?p=mkl/linux-2.6.git;a=commit;h=3df3682c0e2c192714885f67fff89d1d3849d533
regards, Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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Socketcan-core mailing list
Socketcan-core-0fE9KPoRgkgATYTw5x5z8w@public.gmane.org
https://lists.berlios.de/mailman/listinfo/socketcan-core
^ permalink raw reply
* Re: [PATCH 3/3] can: at91_can: make can_id of mailbox 0 configurable
From: Wolfgang Grandegger @ 2011-01-11 12:27 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w,
netdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <4D2C4586.60207-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On 01/11/2011 12:56 PM, Marc Kleine-Budde wrote:
> On 01/11/2011 12:45 PM, Wolfgang Grandegger wrote:
>> On 01/11/2011 11:28 AM, Marc Kleine-Budde wrote:
>>> Due to a chip bug (errata 50.2.6.3 & 50.3.5.3 in
>>> "AT91SAM9263 Preliminary 6249H-ATARM-27-Jul-09") the contents of mailbox
>>> 0 may be send under certain conditions (even if disabled or in rx mode).
>>>
>>> The workaround in the errata suggests not to use the mailbox and load it
>>> with a unused identifier.
>>>
>>> This patch implements the second part of the workaround. A sysfs entry
>>> "mb0_id" is introduced. While the interface is down it can be used to
>>> configure the can_id of mailbox 0. The default value id 0x7ff.
>>>
>>> In order to use an extended can_id add the CAN_EFF_FLAG (0x80000000U)
>>> to the can_id. Example:
>>>
>>> - standard id 0x7ff:
>>> echo 0x7ff > /sys/class/net/can0/mb0_id
>>>
>>> - extended if 0x1fffffff:
> ^^
> I've fixed the typo on my git repo. I'll send an updated series later.
>
>>> echo 0x9fffffff > /sys/class/net/can0/mb0_id
>>
>> As this is a device specific property, I think it should go into
>> /sys/class/net/can0/device/.
>
> The attribute goes autoamtically to /sys/class/net/can0 if you add it to
> the driver via:
>
> + dev->sysfs_groups[0] = &at91_sysfs_attr_group;
>
> I've copied this from the janz-ican3 driver[1].
Oh, I missed that. And also the Softing driver does it that way :-(. The
member has the comment:
/* space for optional device, statistics, and wireless sysfs groups */
const struct attribute_group *sysfs_groups[4];
Therefore it seems to be legal to use it for device specific properties.
Wolfgang.
^ permalink raw reply
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