* Re: [PATCH v2 09/13] can: pruss CAN driver.
From: Kurt Van Dijck @ 2011-02-11 15:20 UTC (permalink / raw)
To: Subhasish Ghosh
Cc: sachi-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/,
davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/,
open list:CAN NETWORK DRIVERS, nsekhar-l0cyMroinI0, open list,
open list:CAN NETWORK DRIVERS,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
m-watkins-l0cyMroinI0, Wolfgang Grandegger
In-Reply-To: <1297435892-28278-10-git-send-email-subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Hi,
I looked a bit at the TX path:
On Fri, Feb 11, 2011 at 08:21:28PM +0530, Subhasish Ghosh wrote:
> +static int omapl_pru_can_set_bittiming(struct net_device *ndev)
> +{
> + struct omapl_pru_can_priv *priv = netdev_priv(ndev);
> + struct can_bittiming *bt = &priv->can.bittiming;
> + long bit_error = 0;
> +
> + if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
> + dev_warn(priv->dev, "WARN: Triple"
> + "sampling not set due to h/w limitations");
You should not have enabled CAN_CTRLMODE_3_SAMPLES in the first place?
> + }
> + if (pru_can_calc_timing(priv->dev, priv->can.clock.freq,
> + bt->bitrate) != 0)
> + return -EINVAL;
> + bit_error =
> + (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
> + bt->bitrate) * 1000) / bt->bitrate;
> + if (bit_error) {
> + bit_error =
> + (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
> + bt->bitrate) * 1000000) / bt->bitrate;
> + printk(KERN_INFO "\nBitrate error %ld.%ld%%\n",
> + bit_error / 10000, bit_error % 1000);
> + } else
> + printk(KERN_INFO "\nBitrate error 0.0%%\n");
> +
> + return 0;
> +}
I wonder how much of this code is duplicated from drivers/net/can/dev.c ?
> +static netdev_tx_t omapl_pru_can_start_xmit(struct sk_buff *skb,
> + struct net_device *ndev)
> +{
> + struct omapl_pru_can_priv *priv = netdev_priv(ndev);
> + struct can_frame *cf = (struct can_frame *)skb->data;
> + int count;
> + u8 *data = cf->data;
> + u8 dlc = cf->can_dlc;
> + u8 *ptr8data = NULL;
> +
most drivers start with:
if (can_dropped_invalid_skb(dev, skb))
return NETDEV_TX_OK;
> + netif_stop_queue(ndev);
why would you stop when you just resumed the queue?
> + if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
> + *((u32 *) &priv->can_tx_hndl.strcanmailbox) =
> + (cf->can_id & CAN_EFF_MASK) | PRU_CANMID_IDE;
> + else /* Standard frame format */
> + *((u32 *) &priv->can_tx_hndl.strcanmailbox) =
> + (cf->can_id & CAN_SFF_MASK) << 18;
> +
> + if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
> + *((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG;
> +
> + ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1);
> + for (count = 0; count < (u8) dlc; count++) {
> + *ptr8data-- = *data++;
> + }
> + *((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc;
> +/*
> + * search for the next available mbx
> + * if the next mbx is busy, then try the next + 1
> + * do this until the head is reached.
> + * if still unable to tx, stop accepting any packets
> + * if able to tx and the head is reached, then reset next to tail, i.e mbx0
> + * if head is not reached, then just point to the next mbx
> + */
> + for (; priv->tx_next <= priv->tx_head; priv->tx_next++) {
> + priv->can_tx_hndl.ecanmailboxnumber =
> + (can_mailbox_number) priv->tx_next;
> + if (-1 == pru_can_write_data_to_mailbox(priv->dev,
> + &priv->can_tx_hndl)) {
> + if (priv->tx_next == priv->tx_head) {
> + priv->tx_next = priv->tx_tail;
> + if (!netif_queue_stopped(ndev))
If you get here, the queue is not stopped. This test is therefore useless.
> + netif_stop_queue(ndev); /* IF stalled */
> + dev_err(priv->dev,
> + "%s: no tx mbx available", __func__);
> + return NETDEV_TX_BUSY;
> + } else
> + continue;
> + } else {
> + /* set transmit request */
> + pru_can_tx(priv->dev, priv->tx_next, CAN_TX_PRU_1);
> + pru_can_tx_mode_set(priv->dev, false, ecanreceive);
> + pru_can_tx_mode_set(priv->dev, true, ecantransmit);
> + pru_can_start_abort_tx(priv->dev, PRU_CAN_START);
> + priv->tx_next++;
> + can_put_echo_skb(skb, ndev, 0);
> + break;
> + }
> + }
> + if (priv->tx_next > priv->tx_head) {
> + priv->tx_next = priv->tx_tail;
> + }
> + return NETDEV_TX_OK;
> +}
> +
> +
> +irqreturn_t omapl_tx_can_intr(int irq, void *dev_id)
> +{
> + struct net_device *ndev = dev_id;
> + struct omapl_pru_can_priv *priv = netdev_priv(ndev);
> + struct net_device_stats *stats = &ndev->stats;
> + u32 bit_set, mbxno;
> +
> + pru_can_get_intr_status(priv->dev, &priv->can_tx_hndl);
> + if ((PRU_CAN_ISR_BIT_CCI & priv->can_tx_hndl.u32interruptstatus)
> + || (PRU_CAN_ISR_BIT_SRDI & priv->can_tx_hndl.u32interruptstatus)) {
> + __can_debug("tx_int_status = 0x%X\n",
> + priv->can_tx_hndl.u32interruptstatus);
> + can_free_echo_skb(ndev, 0);
> + } else {
> + for (bit_set = 0; ((priv->can_tx_hndl.u32interruptstatus & 0xFF)
> + >> bit_set != 0); bit_set++)
> + ;
> + if (0 == bit_set) {
> + __can_err("%s: invalid mailbox number\n", __func__);
> + can_free_echo_skb(ndev, 0);
> + } else {
> + mbxno = bit_set - 1; /* mail box numbering starts from 0 */
> + if (PRU_CAN_ISR_BIT_ESI & priv->can_tx_hndl.
> + u32interruptstatus) {
> + /* read gsr and ack pru */
> + pru_can_get_global_status(priv->dev, &priv->can_tx_hndl);
> + omapl_pru_can_err(ndev,
> + priv->can_tx_hndl.
> + u32interruptstatus,
> + priv->can_tx_hndl.
> + u32globalstatus);
> + } else {
> + stats->tx_packets++;
> + /* stats->tx_bytes += dlc; */
> + /*can_get_echo_skb(ndev, 0);*/
> + }
> + }
> + }
> + if (netif_queue_stopped(ndev))
you can call netif_wake_queue(ndev) multiple times, so there is no need
for netif_queue_stopped()
> + netif_wake_queue(ndev);
> +
> + can_get_echo_skb(ndev, 0);
> + pru_can_tx_mode_set(priv->dev, true, ecanreceive);
> + return IRQ_HANDLED;
> +}
> +
> +static int omapl_pru_can_open(struct net_device *ndev)
> +{
> + struct omapl_pru_can_priv *priv = netdev_priv(ndev);
> + int err;
> +
> + /* register interrupt handler */
> + err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
> + "pru_can_irq", ndev);
you're doing a lot of work _in_ the irq handler. Maybe threaded irq?
> +static int omapl_pru_can_close(struct net_device *ndev)
> +{
> + struct omapl_pru_can_priv *priv = netdev_priv(ndev);
> +
> + if (!netif_queue_stopped(ndev))
check is not needed.
> + netif_stop_queue(ndev);
> +
> + close_candev(ndev);
> +
> + free_irq(priv->trx_irq, ndev);
> + return 0;
> +}
> +
Regards,
Kurt
^ permalink raw reply
* Re: [PATCH v2 09/13] can: pruss CAN driver.
From: Kurt Van Dijck @ 2011-02-11 15:06 UTC (permalink / raw)
To: Subhasish Ghosh
Cc: sachi-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/,
davinci-linux-open-source-VycZQUHpC/PFrsHnngEfi1aTQe2KTcn/,
open list:CAN NETWORK DRIVERS, nsekhar-l0cyMroinI0, open list,
open list:CAN NETWORK DRIVERS,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
m-watkins-l0cyMroinI0, Wolfgang Grandegger
In-Reply-To: <1297435892-28278-10-git-send-email-subhasish-EvXpCiN+lbve9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
On Fri, Feb 11, 2011 at 08:21:28PM +0530, Subhasish Ghosh wrote:
> +config DA8XX_PRU_CANID_MBX0
> + hex "CANID for mailbox 0"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 0
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX1
> + hex "CANID for mailbox 1"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 1
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX2
> + hex "CANID for mailbox 2"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 2
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX3
> + hex "CANID for mailbox 3"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 3
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX4
> + hex "CANID for mailbox 4"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 4
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX5
> + hex "CANID for mailbox 5"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 5
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX6
> + hex "CANID for mailbox 6"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 6
> + Default value is set to 0x123, change this as required.
> +
> +config DA8XX_PRU_CANID_MBX7
> + hex "CANID for mailbox 7"
> + depends on CAN_TI_DA8XX_PRU
> + default "0x123"
> + ---help---
> + Enter the CANID for mailbox 7
> + Default value is set to 0x123, change this as required.
Why is filling the mailboxes the job of kernel config?
Regards,
Kurt
^ permalink raw reply
* [PATCH v2 09/13] can: pruss CAN driver.
From: Subhasish Ghosh @ 2011-02-11 14:51 UTC (permalink / raw)
To: davinci-linux-open-source
Cc: linux-arm-kernel, m-watkins, nsekhar, sachi, Subhasish Ghosh,
Wolfgang Grandegger, open list:CAN NETWORK DRIVERS,
open list:CAN NETWORK DRIVERS, open list
In-Reply-To: <1297435892-28278-1-git-send-email-subhasish@mistralsolutions.com>
This patch adds support for the CAN device emulated on PRUSS.
Signed-off-by: Subhasish Ghosh <subhasish@mistralsolutions.com>
---
drivers/net/can/Kconfig | 1 +
drivers/net/can/Makefile | 1 +
drivers/net/can/da8xx_pruss/Kconfig | 73 ++
drivers/net/can/da8xx_pruss/Makefile | 7 +
drivers/net/can/da8xx_pruss/pruss_can.c | 758 +++++++++++++++++
drivers/net/can/da8xx_pruss/pruss_can_api.c | 1227 +++++++++++++++++++++++++++
drivers/net/can/da8xx_pruss/pruss_can_api.h | 290 +++++++
7 files changed, 2357 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/can/da8xx_pruss/Kconfig
create mode 100644 drivers/net/can/da8xx_pruss/Makefile
create mode 100644 drivers/net/can/da8xx_pruss/pruss_can.c
create mode 100644 drivers/net/can/da8xx_pruss/pruss_can_api.c
create mode 100644 drivers/net/can/da8xx_pruss/pruss_can_api.h
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index d5a9db6..ae8f0f9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -112,6 +112,7 @@ config PCH_CAN
This driver can access CAN bus.
source "drivers/net/can/mscan/Kconfig"
+source "drivers/net/can/da8xx_pruss/Kconfig"
source "drivers/net/can/sja1000/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 07ca159..849cdbf 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CAN_SJA1000) += sja1000/
obj-$(CONFIG_CAN_MSCAN) += mscan/
obj-$(CONFIG_CAN_AT91) += at91_can.o
obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
+obj-$(CONFIG_CAN_TI_DA8XX_PRU) += da8xx_pruss/
obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
obj-$(CONFIG_CAN_BFIN) += bfin_can.o
obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o
diff --git a/drivers/net/can/da8xx_pruss/Kconfig b/drivers/net/can/da8xx_pruss/Kconfig
new file mode 100644
index 0000000..8b68f68
--- /dev/null
+++ b/drivers/net/can/da8xx_pruss/Kconfig
@@ -0,0 +1,73 @@
+#
+# CAN Lite Kernel Configuration
+#
+config CAN_TI_DA8XX_PRU
+ depends on CAN_DEV && ARCH_DAVINCI && ARCH_DAVINCI_DA850
+ tristate "PRU based CAN emulation for DA8XX"
+ ---help---
+ Enable this to emulate a CAN controller on the PRU of DA8XX.
+ If not sure, mark N
+
+config DA8XX_PRU_CANID_MBX0
+ hex "CANID for mailbox 0"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 0
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX1
+ hex "CANID for mailbox 1"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 1
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX2
+ hex "CANID for mailbox 2"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 2
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX3
+ hex "CANID for mailbox 3"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 3
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX4
+ hex "CANID for mailbox 4"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 4
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX5
+ hex "CANID for mailbox 5"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 5
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX6
+ hex "CANID for mailbox 6"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 6
+ Default value is set to 0x123, change this as required.
+
+config DA8XX_PRU_CANID_MBX7
+ hex "CANID for mailbox 7"
+ depends on CAN_TI_DA8XX_PRU
+ default "0x123"
+ ---help---
+ Enter the CANID for mailbox 7
+ Default value is set to 0x123, change this as required.
diff --git a/drivers/net/can/da8xx_pruss/Makefile b/drivers/net/can/da8xx_pruss/Makefile
new file mode 100644
index 0000000..48f3055
--- /dev/null
+++ b/drivers/net/can/da8xx_pruss/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for CAN Lite emulation
+#
+can_emu-objs := pruss_can.o \
+ pruss_can_api.o
+
+obj-$(CONFIG_CAN_TI_DA8XX_PRU) += can_emu.o
diff --git a/drivers/net/can/da8xx_pruss/pruss_can.c b/drivers/net/can/da8xx_pruss/pruss_can.c
new file mode 100644
index 0000000..1b3afde
--- /dev/null
+++ b/drivers/net/can/da8xx_pruss/pruss_can.c
@@ -0,0 +1,758 @@
+/*
+ * TI DA8XX PRU CAN Emulation device driver
+ * Author: subhasish@mistralsolutions.com
+ *
+ * This driver supports TI's PRU CAN Emulation and the
+ * specs for the same is available at <http://www.ti.com>
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/platform_device.h>
+#include <linux/firmware.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+
+#include <linux/can.h>
+#include <linux/can/dev.h>
+#include <linux/can/error.h>
+#include <mach/da8xx.h>
+#include "pruss_can_api.h"
+
+#define DRV_NAME "da8xx_pruss_can"
+#define DRV_DESC "TI PRU CAN Controller Driver v0.1"
+#define PRU_CAN_START 1
+#define PRU_CAN_STOP 0
+#define MB_MIN 0
+#define MB_MAX 7
+
+#define PRU_CANMID_IDE BIT(29) /* Extended frame format */
+
+#define PRU_CAN_ISR_BIT_CCI BIT(15)
+#define PRU_CAN_ISR_BIT_ESI BIT(14)
+#define PRU_CAN_ISR_BIT_SRDI BIT(13)
+#define PRU_CAN_ISR_BIT_RRI BIT(8)
+
+#define PRU_CAN_MBXSR_BIT_STATE BIT(7)
+#define PRU_CAN_MBXSR_BIT_TC BIT(6)
+#define PRU_CAN_MBXSR_BIT_ERR BIT(5)
+#define PRU_CAN_MBXSR_BIT_OF BIT(0)
+
+#define PRU_CAN_GSR_BIT_TXM BIT(7)
+#define PRU_CAN_GSR_BIT_RXM BIT(6)
+#define PRU_CAN_GSR_BIT_CM BIT(5)
+#define PRU_CAN_GSR_BIT_EPM BIT(4)
+#define PRU_CAN_GSR_BIT_BFM BIT(3)
+#define RTR_MBX_NO 8
+#define MAX_INIT_RETRIES 20
+#define L138_PRU_ARM_FREQ 312000
+#define DFLT_PRU_FREQ 156000000
+#define DFLT_PRU_BITRATE 125000
+
+#define CONFIG_DA8XX_PRU_CANID_MBX0 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX1 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX2 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX3 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX4 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX5 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX6 0x123
+#define CONFIG_DA8XX_PRU_CANID_MBX7 0x123
+
+#ifdef __CAN_DEBUG
+#define __can_debug(fmt, args...) printk(KERN_DEBUG "can_debug: " fmt, ## args)
+#else
+#define __can_debug(fmt, args...)
+#endif
+#define __can_err(fmt, args...) printk(KERN_ERR "can_err: " fmt, ## args)
+
+/*
+ * omapl_pru can private data
+ */
+struct omapl_pru_can_priv {
+ struct can_priv can;
+ struct workqueue_struct *pru_can_wQ;
+ struct work_struct rx_work;
+ struct net_device *ndev;
+ struct device *dev; /* pdev->dev */
+ struct clk *clk_timer;
+ u32 timer_freq;
+ can_emu_app_hndl can_tx_hndl;
+ can_emu_app_hndl can_rx_hndl;
+ const struct firmware *fw_rx;
+ const struct firmware *fw_tx;
+ spinlock_t mbox_lock;
+ u32 trx_irq;
+ u32 tx_head;
+ u32 tx_tail;
+ u32 tx_next;
+ u32 rx_next;
+};
+
+static int omapl_pru_can_get_state(const struct net_device *ndev,
+ enum can_state *state)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ *state = priv->can.state;
+ return 0;
+}
+
+static int omapl_pru_can_set_bittiming(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct can_bittiming *bt = &priv->can.bittiming;
+ long bit_error = 0;
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
+ dev_warn(priv->dev, "WARN: Triple"
+ "sampling not set due to h/w limitations");
+ }
+ if (pru_can_calc_timing(priv->dev, priv->can.clock.freq,
+ bt->bitrate) != 0)
+ return -EINVAL;
+ bit_error =
+ (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+ bt->bitrate) * 1000) / bt->bitrate;
+ if (bit_error) {
+ bit_error =
+ (((priv->timer_freq / (priv->timer_freq / bt->bitrate)) -
+ bt->bitrate) * 1000000) / bt->bitrate;
+ printk(KERN_INFO "\nBitrate error %ld.%ld%%\n",
+ bit_error / 10000, bit_error % 1000);
+ } else
+ printk(KERN_INFO "\nBitrate error 0.0%%\n");
+
+ return 0;
+}
+
+static void omapl_pru_can_stop(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ u16 int_mask = 0;
+
+ pru_can_mask_ints(priv->dev, int_mask); /* mask all ints */
+ pru_can_start_abort_tx(priv->dev, PRU_CAN_STOP);
+ priv->can.state = CAN_STATE_STOPPED;
+}
+
+/*
+ * This is to just set the can state to ERROR_ACTIVE
+ * ip link set canX up type can bitrate 125000
+ */
+static void omapl_pru_can_start(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ u16 int_mask = 0xFFFF;
+
+ if (priv->can.state != CAN_STATE_STOPPED)
+ omapl_pru_can_stop(ndev);
+
+ pru_can_mask_ints(priv->dev, int_mask); /* unmask all ints */
+
+ pru_can_get_global_status(priv->dev, &priv->can_tx_hndl);
+ pru_can_get_global_status(priv->dev, &priv->can_rx_hndl);
+
+ if (PRU_CAN_GSR_BIT_EPM & priv->can_tx_hndl.u32globalstatus)
+ priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ else if (PRU_CAN_GSR_BIT_BFM & priv->can_tx_hndl.u32globalstatus)
+ priv->can.state = CAN_STATE_BUS_OFF;
+ else
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+}
+
+static int omapl_pru_can_set_mode(struct net_device *ndev, enum can_mode mode)
+{
+ int ret = 0;
+
+ switch (mode) {
+ case CAN_MODE_START:
+ omapl_pru_can_start(ndev);
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+ break;
+ case CAN_MODE_STOP:
+ omapl_pru_can_stop(ndev);
+ if (!netif_queue_stopped(ndev))
+ netif_stop_queue(ndev);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ return ret;
+}
+
+static netdev_tx_t omapl_pru_can_start_xmit(struct sk_buff *skb,
+ struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct can_frame *cf = (struct can_frame *)skb->data;
+ int count;
+ u8 *data = cf->data;
+ u8 dlc = cf->can_dlc;
+ u8 *ptr8data = NULL;
+
+ netif_stop_queue(ndev);
+ if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) =
+ (cf->can_id & CAN_EFF_MASK) | PRU_CANMID_IDE;
+ else /* Standard frame format */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) =
+ (cf->can_id & CAN_SFF_MASK) << 18;
+
+ if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox) |= CAN_RTR_FLAG;
+
+ ptr8data = &priv->can_tx_hndl.strcanmailbox.u8data7 + (dlc - 1);
+ for (count = 0; count < (u8) dlc; count++) {
+ *ptr8data-- = *data++;
+ }
+ *((u32 *) &priv->can_tx_hndl.strcanmailbox.u16datalength) = (u32) dlc;
+/*
+ * search for the next available mbx
+ * if the next mbx is busy, then try the next + 1
+ * do this until the head is reached.
+ * if still unable to tx, stop accepting any packets
+ * if able to tx and the head is reached, then reset next to tail, i.e mbx0
+ * if head is not reached, then just point to the next mbx
+ */
+ for (; priv->tx_next <= priv->tx_head; priv->tx_next++) {
+ priv->can_tx_hndl.ecanmailboxnumber =
+ (can_mailbox_number) priv->tx_next;
+ if (-1 == pru_can_write_data_to_mailbox(priv->dev,
+ &priv->can_tx_hndl)) {
+ if (priv->tx_next == priv->tx_head) {
+ priv->tx_next = priv->tx_tail;
+ if (!netif_queue_stopped(ndev))
+ netif_stop_queue(ndev); /* IF stalled */
+ dev_err(priv->dev,
+ "%s: no tx mbx available", __func__);
+ return NETDEV_TX_BUSY;
+ } else
+ continue;
+ } else {
+ /* set transmit request */
+ pru_can_tx(priv->dev, priv->tx_next, CAN_TX_PRU_1);
+ pru_can_tx_mode_set(priv->dev, false, ecanreceive);
+ pru_can_tx_mode_set(priv->dev, true, ecantransmit);
+ pru_can_start_abort_tx(priv->dev, PRU_CAN_START);
+ priv->tx_next++;
+ can_put_echo_skb(skb, ndev, 0);
+ break;
+ }
+ }
+ if (priv->tx_next > priv->tx_head) {
+ priv->tx_next = priv->tx_tail;
+ }
+ return NETDEV_TX_OK;
+}
+
+static int omapl_pru_can_rx(struct net_device *ndev, u32 mbxno)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+ u32 pru_can_mbx_data;
+ u8 *data = NULL;
+ u8 *ptr8data = NULL;
+ int count = 0;
+
+ skb = alloc_can_skb(ndev, &cf);
+ if (!skb) {
+ if (printk_ratelimit())
+ dev_err(priv->dev,
+ "alloc_can_skb() failed\n");
+ return -ENOMEM;
+ }
+ data = cf->data;
+ /* get payload */
+ priv->can_rx_hndl.ecanmailboxnumber = (can_mailbox_number) mbxno;
+ if (pru_can_get_data_from_mailbox(priv->dev, &priv->can_rx_hndl)) {
+ __can_err("failed to get data from mailbox\n");
+ return -EAGAIN;
+ }
+ /* give ownweship to pru */
+ pru_can_tx(priv->dev, mbxno, CAN_RX_PRU_0);
+
+ /* get data length code */
+ cf->can_dlc =
+ get_can_dlc(*
+ ((u32 *) &priv->can_rx_hndl.strcanmailbox.
+ u16datalength) & 0xF);
+ if (cf->can_dlc <= 4) {
+ ptr8data =
+ &priv->can_rx_hndl.strcanmailbox.u8data3 + (4 -
+ cf->can_dlc);
+ for (count = 0; count < cf->can_dlc; count++) {
+ *data++ = *ptr8data++;
+ }
+ } else {
+ ptr8data = &priv->can_rx_hndl.strcanmailbox.u8data3;
+ for (count = 0; count < 4; count++) {
+ *data++ = *ptr8data++;
+ }
+ ptr8data =
+ &priv->can_rx_hndl.strcanmailbox.u8data4 - (cf->can_dlc -
+ 5);
+ for (count = 0; count < cf->can_dlc - 4; count++) {
+ *data++ = *ptr8data++;
+ }
+ }
+
+ pru_can_mbx_data = *((u32 *) &priv->can_rx_hndl.strcanmailbox);
+ /* get id extended or std */
+ if (pru_can_mbx_data & PRU_CANMID_IDE)
+ cf->can_id = (pru_can_mbx_data & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ else
+ cf->can_id = (pru_can_mbx_data >> 18) & CAN_SFF_MASK;
+
+ if (pru_can_mbx_data & CAN_RTR_FLAG)
+ cf->can_id |= CAN_RTR_FLAG;
+
+ netif_rx_ni(skb);
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+ return 0;
+}
+
+static int omapl_pru_can_err(struct net_device *ndev, int int_status,
+ int err_status)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+ int tx_err_cnt, rx_err_cnt;
+
+ /* propogate the error condition to the can stack */
+ skb = alloc_can_err_skb(ndev, &cf);
+ if (!skb) {
+ if (printk_ratelimit())
+ dev_err(priv->dev,
+ "alloc_can_err_skb() failed\n");
+ return -ENOMEM;
+ }
+
+ if (err_status & PRU_CAN_GSR_BIT_EPM) { /* error passive int */
+ priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ ++priv->can.can_stats.error_passive;
+ cf->can_id |= CAN_ERR_CRTL;
+ tx_err_cnt = pru_can_get_error_cnt(priv->dev, CAN_TX_PRU_1);
+ rx_err_cnt = pru_can_get_error_cnt(priv->dev, CAN_RX_PRU_0);
+ if (tx_err_cnt > 127)
+ cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+ if (rx_err_cnt > 127)
+ cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+
+ dev_dbg(priv->ndev->dev.parent, "Error passive interrupt\n");
+ }
+
+ if (err_status & PRU_CAN_GSR_BIT_BFM) {
+ priv->can.state = CAN_STATE_BUS_OFF;
+ cf->can_id |= CAN_ERR_BUSOFF;
+ /*
+ * Disable all interrupts in bus-off to avoid int hog
+ * this should be handled by the pru
+ */
+ pru_can_mask_ints(priv->dev, 0xFFFF);
+ can_bus_off(ndev);
+ dev_dbg(priv->ndev->dev.parent, "Bus off mode\n");
+ }
+
+ netif_rx(skb);
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+ return 0;
+}
+
+void omapl_pru_can_rx_wQ(struct work_struct *work)
+{
+ struct omapl_pru_can_priv *priv = container_of(work,
+ struct omapl_pru_can_priv, rx_work);
+ struct net_device *ndev = priv->ndev;
+ u32 bit_set, mbxno = 0;
+
+ if (-1 == pru_can_get_intr_status(priv->dev, &priv->can_rx_hndl))
+ return;
+
+ if (PRU_CAN_ISR_BIT_RRI & priv->can_rx_hndl.u32interruptstatus) {
+ mbxno = RTR_MBX_NO;
+ omapl_pru_can_rx(ndev, mbxno);
+ } else {
+ /* Extract the mboxno from the status */
+ for (bit_set = 0; ((priv->can_rx_hndl.u32interruptstatus & 0xFF)
+ >> bit_set != 0); bit_set++)
+ ;
+ if (0 == bit_set) {
+ dev_err(priv->dev,
+ "%s: invalid mailbox number: %X\n", __func__,
+ priv->can_rx_hndl.u32interruptstatus);
+ } else {
+ mbxno = bit_set - 1;
+ if (PRU_CAN_ISR_BIT_ESI & priv->can_rx_hndl.
+ u32interruptstatus) {
+ pru_can_get_global_status(priv->dev,
+ &priv->can_rx_hndl);
+ omapl_pru_can_err(ndev,
+ priv->can_rx_hndl.u32interruptstatus,
+ priv->can_rx_hndl.u32globalstatus);
+ } else {
+ omapl_pru_can_rx(ndev, mbxno);
+ }
+ }
+ }
+}
+
+irqreturn_t omapl_tx_can_intr(int irq, void *dev_id)
+{
+ struct net_device *ndev = dev_id;
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ struct net_device_stats *stats = &ndev->stats;
+ u32 bit_set, mbxno;
+
+ pru_can_get_intr_status(priv->dev, &priv->can_tx_hndl);
+ if ((PRU_CAN_ISR_BIT_CCI & priv->can_tx_hndl.u32interruptstatus)
+ || (PRU_CAN_ISR_BIT_SRDI & priv->can_tx_hndl.u32interruptstatus)) {
+ __can_debug("tx_int_status = 0x%X\n",
+ priv->can_tx_hndl.u32interruptstatus);
+ can_free_echo_skb(ndev, 0);
+ } else {
+ for (bit_set = 0; ((priv->can_tx_hndl.u32interruptstatus & 0xFF)
+ >> bit_set != 0); bit_set++)
+ ;
+ if (0 == bit_set) {
+ __can_err("%s: invalid mailbox number\n", __func__);
+ can_free_echo_skb(ndev, 0);
+ } else {
+ mbxno = bit_set - 1; /* mail box numbering starts from 0 */
+ if (PRU_CAN_ISR_BIT_ESI & priv->can_tx_hndl.
+ u32interruptstatus) {
+ /* read gsr and ack pru */
+ pru_can_get_global_status(priv->dev, &priv->can_tx_hndl);
+ omapl_pru_can_err(ndev,
+ priv->can_tx_hndl.
+ u32interruptstatus,
+ priv->can_tx_hndl.
+ u32globalstatus);
+ } else {
+ stats->tx_packets++;
+ /* stats->tx_bytes += dlc; */
+ /*can_get_echo_skb(ndev, 0);*/
+ }
+ }
+ }
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
+
+ can_get_echo_skb(ndev, 0);
+ pru_can_tx_mode_set(priv->dev, true, ecanreceive);
+ return IRQ_HANDLED;
+}
+
+irqreturn_t omapl_rx_can_intr(int irq, void *dev_id)
+{
+
+ struct net_device *ndev = dev_id;
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ u32 intc_status = 0;
+
+ intc_status = pru_can_get_intc_status(priv->dev);
+ if (intc_status & 4)
+ return omapl_tx_can_intr(irq, dev_id);
+ if (intc_status & 2) {
+ if (!work_pending(&priv->rx_work))
+ queue_work(priv->pru_can_wQ, &priv->rx_work);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int omapl_pru_can_open(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+ int err;
+
+ /* register interrupt handler */
+ err = request_irq(priv->trx_irq, &omapl_rx_can_intr, IRQF_SHARED,
+ "pru_can_irq", ndev);
+ if (err) {
+ dev_err(priv->dev, "error requesting rx interrupt\n");
+ goto exit_trx_irq;
+ }
+ /* common open */
+ err = open_candev(ndev);
+ if (err) {
+ dev_err(priv->dev, "open_candev() failed %d\n", err);
+ goto exit_open;
+ }
+
+ pru_can_emu_init(priv->dev, priv->can.clock.freq);
+ priv->tx_tail = MB_MIN;
+ priv->tx_head = MB_MAX;
+
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX0, 0);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX1, 1);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX2, 2);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX3, 3);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX4, 4);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX5, 5);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX6, 6);
+ pru_can_rx_id_map(priv->dev, CONFIG_DA8XX_PRU_CANID_MBX7, 7);
+
+ omapl_pru_can_start(ndev);
+ netif_start_queue(ndev);
+ return 0;
+
+exit_open:
+ free_irq(priv->trx_irq, ndev);
+exit_trx_irq:
+ return err;
+}
+
+static int omapl_pru_can_close(struct net_device *ndev)
+{
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+
+ if (!netif_queue_stopped(ndev))
+ netif_stop_queue(ndev);
+
+ close_candev(ndev);
+
+ free_irq(priv->trx_irq, ndev);
+ return 0;
+}
+
+static const struct net_device_ops omapl_pru_can_netdev_ops = {
+ .ndo_open = omapl_pru_can_open,
+ .ndo_stop = omapl_pru_can_close,
+ .ndo_start_xmit = omapl_pru_can_start_xmit,
+};
+
+static int __devinit omapl_pru_can_probe(struct platform_device *pdev)
+{
+ struct net_device *ndev = NULL;
+ const struct da8xx_pru_can_data *pdata;
+ struct omapl_pru_can_priv *priv = NULL;
+ struct device *dev = &pdev->dev;
+ u32 err;
+
+ pdata = dev->platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "platform data not found\n");
+ return -EINVAL;
+ }
+
+ ndev = alloc_candev(sizeof(struct omapl_pru_can_priv), MB_MAX + 1);
+ if (!ndev) {
+ dev_err(&pdev->dev, "alloc_candev failed\n");
+ err = -ENOMEM;
+ goto probe_exit;
+ }
+ priv = netdev_priv(ndev);
+
+ priv->trx_irq = platform_get_irq(to_platform_device(dev->parent), 0);
+ if (!priv->trx_irq) {
+ dev_err(&pdev->dev, "unable to get pru interrupt resources!\n");
+ err = -ENODEV;
+ goto probe_exit;
+ }
+
+ priv->ndev = ndev;
+ priv->dev = dev; /* priv->dev = pdev->dev */
+
+ priv->can.bittiming_const = NULL;
+ priv->can.do_set_bittiming = omapl_pru_can_set_bittiming;
+ priv->can.do_set_mode = omapl_pru_can_set_mode;
+ priv->can.do_get_state = omapl_pru_can_get_state;
+ priv->can_tx_hndl.u8prunumber = CAN_TX_PRU_1;
+ priv->can_rx_hndl.u8prunumber = CAN_RX_PRU_0;
+
+ /* we support local echo, no arp */
+ ndev->flags |= (IFF_ECHO | IFF_NOARP);
+
+ /* pdev->dev->device_private->driver_data = ndev */
+ platform_set_drvdata(pdev, ndev);
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ ndev->netdev_ops = &omapl_pru_can_netdev_ops;
+
+ priv->can.clock.freq = pruss_get_clk_freq(priv->dev);
+
+ priv->clk_timer = clk_get(&pdev->dev, "pll1_sysclk2");
+ if (IS_ERR(priv->clk_timer)) {
+ dev_err(&pdev->dev, "no timer clock available\n");
+ err = PTR_ERR(priv->clk_timer);
+ priv->clk_timer = NULL;
+ goto probe_exit_candev;
+ }
+ priv->timer_freq = clk_get_rate(priv->clk_timer);
+
+ err = register_candev(ndev);
+ if (err) {
+ dev_err(&pdev->dev, "register_candev() failed\n");
+ err = -ENODEV;
+ goto probe_exit_clk;
+ }
+
+ err = request_firmware(&priv->fw_tx, "PRU_CAN_Emulation_Tx.bin",
+ &pdev->dev);
+ if (err) {
+ dev_err(&pdev->dev, "can't load firmware\n");
+ err = -ENODEV;
+ goto probe_exit_clk;
+ }
+
+ dev_info(&pdev->dev, "fw_tx size %d. downloading...\n",
+ priv->fw_tx->size);
+
+ err = request_firmware(&priv->fw_rx, "PRU_CAN_Emulation_Rx.bin",
+ &pdev->dev);
+ if (err) {
+ dev_err(&pdev->dev, "can't load firmware\n");
+ err = -ENODEV;
+ goto probe_release_fw;
+ }
+ dev_info(&pdev->dev, "fw_rx size %d. downloading...\n",
+ priv->fw_rx->size);
+
+ /* init the pru */
+ pru_can_emu_init(priv->dev, priv->can.clock.freq);
+ udelay(200);
+
+ pruss_enable(priv->dev, CAN_RX_PRU_0);
+ pruss_enable(priv->dev, CAN_TX_PRU_1);
+
+ /* download firmware into pru */
+ err = pruss_load(priv->dev, CAN_RX_PRU_0,
+ (u32 *)priv->fw_rx->data, (priv->fw_rx->size / 4));
+ if (err) {
+ dev_err(&pdev->dev, "firmware download error\n");
+ err = -ENODEV;
+ goto probe_release_fw_1;
+ }
+ err = pruss_load(priv->dev, CAN_TX_PRU_1,
+ (u32 *)priv->fw_tx->data, (priv->fw_tx->size / 4));
+ if (err) {
+ dev_err(&pdev->dev, "firmware download error\n");
+ err = -ENODEV;
+ goto probe_release_fw_1;
+ }
+
+ if (pru_can_calc_timing(priv->dev, DFLT_PRU_FREQ,
+ DFLT_PRU_BITRATE) != 0)
+ return -EINVAL;
+
+ pruss_run(priv->dev, CAN_RX_PRU_0);
+ pruss_run(priv->dev, CAN_TX_PRU_1);
+
+ /*Create The Work Queue */
+ priv->pru_can_wQ = create_freezeable_workqueue("omapl_pru_wQ");
+ if (priv->pru_can_wQ == NULL) {
+ dev_err(&pdev->dev, "failed to create work queue\n");
+ err = -ENODEV;
+ goto probe_release_fw_1;
+ }
+
+ INIT_WORK(&priv->rx_work, omapl_pru_can_rx_wQ);
+ dev_info(&pdev->dev,
+ "%s device registered (trx_irq = %d, clk = %d)\n",
+ DRV_NAME, priv->trx_irq, priv->can.clock.freq);
+
+ return 0;
+
+probe_release_fw_1:
+ release_firmware(priv->fw_rx);
+probe_release_fw:
+ release_firmware(priv->fw_tx);
+probe_exit_clk:
+ clk_put(priv->clk_timer);
+probe_exit_candev:
+ if (NULL != ndev)
+ free_candev(ndev);
+probe_exit:
+ return err;
+}
+
+static int __devexit omapl_pru_can_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct omapl_pru_can_priv *priv = netdev_priv(ndev);
+
+ omapl_pru_can_stop(ndev);
+
+ pru_can_emu_exit(priv->dev);
+ release_firmware(priv->fw_tx);
+ release_firmware(priv->fw_rx);
+ clk_put(priv->clk_timer);
+ flush_workqueue(priv->pru_can_wQ);
+ destroy_workqueue(priv->pru_can_wQ);
+ unregister_candev(ndev);
+ free_candev(ndev);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int omapl_pru_can_suspend(struct platform_device *pdev,
+ pm_message_t mesg)
+{
+ dev_info(&pdev->dev, "%s not yet implemented\n", __func__);
+ return 0;
+}
+
+static int omapl_pru_can_resume(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "%s not yet implemented\n", __func__);
+ return 0;
+}
+#else
+#define omapl_pru_can_suspend NULL
+#define omapl_pru_can_resume NULL
+#endif /* CONFIG_PM */
+
+static struct platform_driver omapl_pru_can_driver = {
+ .probe = omapl_pru_can_probe,
+ .remove = __devexit_p(omapl_pru_can_remove),
+ .suspend = omapl_pru_can_suspend,
+ .resume = omapl_pru_can_resume,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init omapl_pru_can_init(void)
+{
+ __can_debug(KERN_INFO DRV_DESC "\n");
+ return platform_driver_register(&omapl_pru_can_driver);
+}
+
+module_init(omapl_pru_can_init);
+
+static void __exit omapl_pru_can_exit(void)
+{
+ __can_debug(KERN_INFO DRV_DESC " unloaded\n");
+ platform_driver_unregister(&omapl_pru_can_driver);
+}
+
+module_exit(omapl_pru_can_exit);
+
+MODULE_AUTHOR("Subhasish Ghosh <subhasish@mistralsolutions.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("omapl pru CAN netdevice driver");
diff --git a/drivers/net/can/da8xx_pruss/pruss_can_api.c b/drivers/net/can/da8xx_pruss/pruss_can_api.c
new file mode 100644
index 0000000..2f7438a
--- /dev/null
+++ b/drivers/net/can/da8xx_pruss/pruss_can_api.c
@@ -0,0 +1,1227 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Wilfred Felix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include "pruss_can_api.h"
+
+static can_emu_drv_inst gstr_can_inst[ecanmaxinst];
+
+/*
+ * pru_can_set_brp() Updates the BRP register of PRU0
+ * and PRU1 of OMAP L138. This API will be called by the
+ * Application to updtae the BRP register of PRU0 and PRU1
+ *
+ * param u16bitrateprescaler The can bus bitrate
+ * prescaler value be set
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_set_brp(struct device *dev, u16 u16bitrateprescaler)
+{
+
+ u32 u32offset;
+
+ if (u16bitrateprescaler > 255) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_CLOCK_BRP_REGISTER);
+ pruss_writel(dev, u32offset, (u32 *) &u16bitrateprescaler, 1);
+
+ u32offset = (PRU_CAN_TX_CLOCK_BRP_REGISTER);
+ pruss_writel(dev, u32offset, (u32 *) &u16bitrateprescaler, 1);
+
+ return 0;
+
+}
+
+/*
+ * pru_can_set_bit_timing() Updates the timing register
+ * of PRU0 and PRU1 of OMAP L138. This API will be called by
+ * the Application to updtae the timing register of PRU0 and PRU1
+ *
+ * param pstrbittiming Pointer to structure holding
+ * the bit timing values for can bus.
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_set_bit_timing(struct device *dev,
+ can_bit_timing_consts *pstrbittiming)
+{
+
+ u32 u32offset;
+ u32 u32serregister;
+
+ u32serregister = 0;
+
+ if (pstrbittiming == NULL) {
+ return -1;
+ }
+
+ if ((pstrbittiming->u8syncjumpwidth > PRU_CAN_MAX_SJW) ||
+ (pstrbittiming->u8phseg1 > PRU_CAN_MAX_PHSEG1) ||
+ (pstrbittiming->u8phseg2 > PRU_CAN_MAX_PHSEG2)) {
+ return -1;
+ }
+
+ u32serregister = u32serregister |
+ ((pstrbittiming->u8syncjumpwidth << 7) |
+ (pstrbittiming->u8phseg1 << 3) |
+ (pstrbittiming->u8phseg2));
+
+ u32offset = (PRU_CAN_TX_TIMING_REGISTER);
+ pruss_writel(dev, u32offset, (u32 *) &u32serregister, 1);
+
+ u32offset = (PRU_CAN_RX_TIMING_REGISTER);
+ pruss_writel(dev, u32offset, (u32 *) &u32serregister, 1);
+
+ return 0;
+}
+
+
+/*
+ * pru_can_calc_timing()
+ * Updates the timing values of PRU0 and PRU1 of OMAP L138.
+ * This API will be called by the
+ * Application to updtae the timing values of PRU0 and PRU1
+ *
+ * return SUCCESS or FAILURE
+ */
+
+s16 pru_can_calc_timing(struct device *dev, u32 pru_freq, u32 bit_rate)
+{
+ u16 u16phaseseg1;
+ u16 u16phaseseg2;
+ u32 u32offset;
+ u32 u32timing_value;
+ u32 u32setup_value;
+ u32timing_value = TIMER_CLK_FREQ / bit_rate;
+ u32offset = (PRU_CAN_TIMING_VAL_TX);
+ pruss_writel(dev, u32offset, (u32 *) &u32timing_value, 4);
+ pruss_readl(dev, u32offset, (u32 *) &u32timing_value, 4);
+ u32setup_value =
+ (GPIO_SETUP_DELAY * (pru_freq / 1000000) / 1000) /
+ DELAY_LOOP_LENGTH;
+ u32offset = (PRU_CAN_TIMING_VAL_TX_SJW);
+ pruss_writel(dev, u32offset, (u32 *) &u32setup_value, 4);
+ u16phaseseg1 = (u16) (u32timing_value / 2);
+ u16phaseseg2 = u32timing_value - u16phaseseg1;
+ u16phaseseg1 -= TIMER_SETUP_DELAY;
+ u16phaseseg2 -= TIMER_SETUP_DELAY;
+ u32setup_value = (u16phaseseg1 << 16) | u16phaseseg2;
+ u32offset = (PRU_CAN_TIMING_VAL_RX);
+ pruss_writel(dev, u32offset, (u32 *) &u32setup_value, 4);
+ u32offset = (PRU_CAN_TIMING_VAL_RX + 4);
+ pruss_writel(dev, u32offset, (u32 *) &u32timing_value, 4);
+
+ return 0;
+}
+
+/*
+ * pru_can_write_data_to_mailbox()
+ * Updates the transmit mailboxes of PRU1 of OMAP L138.
+ * This API will be called by the Application to update
+ * the transmit mailboxes of PRU1
+ *
+ * param pu16canframedata Can mailbox data buffer
+ *
+ * param u8mailboxnum Mailbox to be updated
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_write_data_to_mailbox(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl)
+{
+ s16 s16subrtnretval;
+ u32 u32offset;
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ switch ((u8) pstremuapphndl->ecanmailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_TX_MAILBOX0);
+ break;
+ case 1:
+ u32offset = (PRU_CAN_TX_MAILBOX1);
+ break;
+ case 2:
+ u32offset = (PRU_CAN_TX_MAILBOX2);
+ break;
+ case 3:
+ u32offset = (PRU_CAN_TX_MAILBOX3);
+ break;
+ case 4:
+ u32offset = (PRU_CAN_TX_MAILBOX4);
+ break;
+ case 5:
+ u32offset = (PRU_CAN_TX_MAILBOX5);
+ break;
+ case 6:
+ u32offset = (PRU_CAN_TX_MAILBOX6);
+ break;
+ case 7:
+ u32offset = (PRU_CAN_TX_MAILBOX7);
+ break;
+ default:
+ return -1;
+ }
+
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &(pstremuapphndl->strcanmailbox), 4);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * pru_can_get_data_from_mailbox()
+ * Receive data from the receive mailboxes of PRU0 of OMAP L138.
+ * This API will be called by the Application to get data from
+ * the receive mailboxes of PRU0
+ *
+ * param pu16canframedata Can mailbox data buffer
+ *
+ * param u8mailboxnum Mailbox to be updated
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_get_data_from_mailbox(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl)
+{
+ s16 s16subrtnretval;
+ u32 u32offset;
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ switch ((u8) pstremuapphndl->ecanmailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_RX_MAILBOX0);
+ break;
+ case 1:
+ u32offset = (PRU_CAN_RX_MAILBOX1);
+ break;
+ case 2:
+ u32offset = (PRU_CAN_RX_MAILBOX2);
+ break;
+ case 3:
+ u32offset = (PRU_CAN_RX_MAILBOX3);
+ break;
+ case 4:
+ u32offset = (PRU_CAN_RX_MAILBOX4);
+ break;
+ case 5:
+ u32offset = (PRU_CAN_RX_MAILBOX5);
+ break;
+ case 6:
+ u32offset = (PRU_CAN_RX_MAILBOX6);
+ break;
+ case 7:
+ u32offset = (PRU_CAN_RX_MAILBOX7);
+ break;
+ case 8:
+ u32offset = (PRU_CAN_RX_MAILBOX8);
+ break;
+ default:
+ return -1;
+ }
+
+ s16subrtnretval =
+ pruss_readl(dev, u32offset,
+ (u32 *) &(pstremuapphndl->strcanmailbox),
+ 4);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * pru_can_receive_id_map()
+ * Receive mailboxes ID Mapping of PRU0 of OMAP L138.
+ * This API will be called by the Application
+ * to map the IDs to receive mailboxes of PRU0
+ *
+ * param u32nodeid Can node ID
+ *
+ * param ecanmailboxno Mailbox to be mapped
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_rx_id_map(struct device *dev, u32 u32nodeid,
+ can_mailbox_number ecanmailboxno)
+{
+
+ pruss_writel(dev, (PRU_CAN_ID_MAP +
+ (((u8) ecanmailboxno) * 4)), (u32 *) &u32nodeid, 1);
+
+ return 0;
+}
+
+/*
+ * pru_can_get_intr_status()
+ * Gets the interrupts status register value.
+ * This API will be called by the Application
+ * to get the interrupts status register value
+ *
+ * param u8prunumber PRU number for which IntStatusReg
+ * has to be read
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_get_intr_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl)
+{
+ u32 u32offset;
+ s16 s16subrtnretval = -1;
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+ u32offset = (PRU_CAN_TX_INTERRUPT_STATUS_REGISTER);
+ } else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+ u32offset = (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER);
+ } else {
+ return -1;
+ }
+
+ s16subrtnretval = pruss_readl(dev, u32offset,
+ (u32 *) &pstremuapphndl->u32interruptstatus, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * pru_can_get_global_status() Gets the globalstatus
+ * register value. This API will be called by the Application
+ * to get the global status register value
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_get_global_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl)
+{
+ u32 u32offset;
+ int s16subrtnretval = -1;
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+ u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+ } else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+ u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+ } else {
+ return -1;
+ }
+
+ s16subrtnretval = pruss_readl(dev, u32offset,
+ (u32 *) &pstremuapphndl->u32globalstatus, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * pru_can_get_mailbox_status() Gets the mailbox status
+ * register value. This API will be called by the Application
+ * to get the mailbox status register value
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_get_mailbox_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl)
+{
+ u32 u32offset;
+ s16 s16subrtnretval = -1;
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_1) {
+ switch (pstremuapphndl->ecanmailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER);
+ break;
+ case 1:
+ u32offset = (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER);
+ break;
+ case 2:
+ u32offset = (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER);
+ break;
+ case 3:
+ u32offset = (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER);
+ break;
+ case 4:
+ u32offset = (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER);
+ break;
+ case 5:
+ u32offset = (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER);
+ break;
+ case 6:
+ u32offset = (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER);
+ break;
+ case 7:
+ u32offset = (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER);
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ else if (pstremuapphndl->u8prunumber == DA8XX_PRUCORE_0) {
+ switch (pstremuapphndl->ecanmailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER);
+ break;
+ case 1:
+ u32offset = (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER);
+ break;
+ case 2:
+ u32offset = (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER);
+ break;
+ case 3:
+ u32offset = (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER);
+ break;
+ case 4:
+ u32offset = (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER);
+ break;
+ case 5:
+ u32offset = (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER);
+ break;
+ case 6:
+ u32offset = (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER);
+ break;
+ case 7:
+ u32offset = (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER);
+ break;
+ case 8:
+ u32offset = (PRU_CAN_RX_MAILBOX8_STATUS_REGISTER);
+ break;
+ default:
+ return -1;
+ }
+ }
+
+ else {
+ return -1;
+ }
+
+ s16subrtnretval = pruss_readl(dev, u32offset,
+ (u32 *) &pstremuapphndl->u32mailboxstatus, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ return 0;
+}
+
+s16 pru_can_tx_mode_set(struct device *dev, bool btransfer_flag,
+ can_transfer_direction ecan_trx)
+{
+ u32 u32offset;
+ u32 u32value;
+
+ if (ecan_trx == ecantransmit) {
+ u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+ pruss_readl(dev, u32offset, &u32value, 1);
+ if (btransfer_flag == true) {
+ u32value &= 0x1F;
+ u32value |= 0x80;
+ } else {
+ u32value &= 0x7F;
+ }
+ pruss_writel(dev, u32offset, &u32value, 1);
+ u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+ pruss_writel(dev, u32offset, &u32value, 1);
+ } else if (ecan_trx == ecanreceive) {
+ u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER);
+ pruss_readl(dev, u32offset, &u32value, 1);
+ if (btransfer_flag == true) {
+ u32value &= 0x1F;
+ u32value |= 0x40;
+ } else {
+ u32value &= 0xBF;
+ }
+ pruss_writel(dev, u32offset, &u32value, 1);
+ u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER);
+ pruss_writel(dev, u32offset, &u32value, 1);
+ } else
+ return -1;
+
+ return 0;
+}
+
+/*
+ * pru_can_config_mode_set() Sets the timing value
+ * for data transfer. This API will be called by the Application
+ * to set timing valus for data transfer
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_config_mode_set(struct device *dev, bool bconfigmodeflag)
+{
+
+ u32 u32bitrateprescaler;
+ u32 u32canbittiming;
+
+ pruss_readl(dev, (PRU_CAN_TX_CLOCK_BRP_REGISTER),
+ (u32 *) &u32bitrateprescaler, 1);
+ pruss_readl(dev, (PRU_CAN_TX_TIMING_REGISTER),
+ (u32 *) &u32canbittiming, 1);
+
+ if (bconfigmodeflag == 1) {
+ pru_can_calc_timing(dev, u32canbittiming, u32bitrateprescaler);
+ }
+
+ else {
+ pru_can_calc_timing(dev, 0, 0);
+ }
+
+ return 0;
+}
+
+/*
+ * pru_can_emu_init() Initializes the Can
+ * Emulation Parameters. This API will be called by the Application
+ * to Initialize the Can Emulation Parameters
+ *
+ * param u32pruclock PRU Clock value
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_emu_init(struct device *dev, u32 u32pruclock)
+{
+ u32 u32offset;
+ u32 u32value;
+ s16 s16subrtnretval = -1;
+ u8 u8loop;
+
+ for (u8loop = 0; u8loop < (u8) ecanmaxinst; u8loop++) {
+ gstr_can_inst[u8loop].bcaninststate = (bool) 0;
+ gstr_can_inst[u8loop].ecantransferdirection =
+ (can_transfer_direction) 0;
+ gstr_can_inst[u8loop].u32apphandlerptr = 0;
+ }
+
+ u32offset = (PRU_CAN_TX_GLOBAL_CONTROL_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000040;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000040;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_INTERRUPT_MASK_REGISTER & 0xFFFF);
+ u32value = 0x00004000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_INTERRUPT_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval =
+ pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000001;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_ERROR_COUNTER_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_TIMING_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_CLOCK_BRP_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_TX_ERROR_COUNTER_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_POLARITY0 & 0xFFFF);
+ u32value = 0xFFFFFFFF;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32offset = (PRUSS_INTC_POLARITY1 & 0xFFFF);
+ u32value = 0xFFFFFFFF;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32offset = (PRUSS_INTC_TYPE0 & 0xFFFF);
+ u32value = 0x1C000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32offset = (PRUSS_INTC_TYPE1 & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_HSTINTENIDXCLR & 0xFFFF);
+ u32value = 0x0;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_GLBLEN & 0xFFFF);
+ u32value = 0x1;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ /* tx intr map arm->pru */
+ u32offset = (PRUSS_INTC_HSTINTENIDXSET & 0xFFFF);
+ u32value = 0x0;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_HOSTMAP0 & 0xFFFF);
+ u32value = 0x03020100;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_HOSTMAP1 & 0xFFFF);
+ u32value = 0x07060504;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_HOSTMAP2 & 0xFFFF);
+ u32value = 0x0000908;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_CHANMAP0 & 0xFFFF);
+ u32value = 0;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_CHANMAP8 & 0xFFFF);
+ u32value = 0x00020200;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ u32value = 32;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ u32value = 19;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+ u32value = 19;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ u32value = 18;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+ u32value = 18;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ u32value = 34;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+ u32value = 34;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+ u32value = 32;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRUSS_INTC_HOSTINTEN & 0xFFFF);
+ u32value = 0x5;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+/* PRU0 - Rx Internal Registers Initializations */
+
+ u32offset = (PRU_CAN_RX_GLOBAL_CONTROL_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_GLOBAL_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000040;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_INTERRUPT_MASK_REGISTER & 0xFFFF);
+ u32value = 0x00004000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x0000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_ERROR_COUNTER_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_TIMING_REGISTER & 0xFFFF);
+ u32value = 0x0000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ u32offset = (PRU_CAN_RX_CLOCK_BRP_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset, (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ return 0;
+}
+
+
+/*
+ * pru_can_emu_open() Opens the can emu for
+ * application to use. This API will be called by the Application
+ * to Open the can emu for application to use.
+ *
+ * param pstremuapphndl Pointer to application handler
+ * structure
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_emu_open(struct device *dev, can_emu_app_hndl *pstremuapphndl)
+{
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+
+ if (gstr_can_inst[pstremuapphndl->ecaninstance].bcaninststate == 1) {
+ return -1;
+ }
+
+ gstr_can_inst[(u8) pstremuapphndl->ecaninstance].
+ bcaninststate = (bool)1;
+ gstr_can_inst[(u8) pstremuapphndl->
+ ecaninstance].ecantransferdirection =
+ (can_transfer_direction)(u8)pstremuapphndl->ecantransferdirection;
+ gstr_can_inst[(u8) pstremuapphndl->ecaninstance].
+ u32apphandlerptr = (u32) pstremuapphndl;
+
+ return 0;
+}
+
+
+/*
+ * brief pru_can_emu_close() Closes the can emu for other
+ * applications to use. This API will be called by the Application to Close
+ * the can emu for other applications to use
+ *
+ * param pstremuapphndl Pointer to application handler structure
+ *
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_emu_close(struct device *dev, can_emu_app_hndl *pstremuapphndl)
+{
+
+ if (pstremuapphndl == NULL) {
+ return -1;
+ }
+ if (gstr_can_inst[pstremuapphndl->ecaninstance].bcaninststate == 0) {
+ return -1;
+ }
+ if ((u32) pstremuapphndl != gstr_can_inst[(u8) pstremuapphndl->
+ ecaninstance].u32apphandlerptr){
+ return -1;
+ }
+ gstr_can_inst[(u8) pstremuapphndl->ecaninstance].bcaninststate
+ = (bool) 0;
+ gstr_can_inst[(u8) pstremuapphndl->
+ ecaninstance].ecantransferdirection = (can_transfer_direction) 0;
+ gstr_can_inst[(u8) pstremuapphndl->ecaninstance].u32apphandlerptr = 0;
+
+ return 0;
+}
+
+/*
+ * brief pru_can_emu_exit() Diables all the PRUs
+ * This API will be called by the Application to disable all PRUs
+ * param None
+ * return SUCCESS or FAILURE
+ */
+s16 pru_can_emu_exit(struct device *dev)
+{
+ s16 s16subrtnretval;
+
+ s16subrtnretval = pruss_disable(dev, CAN_RX_PRU_0);
+ if (s16subrtnretval == -1)
+ return -1;
+ s16subrtnretval = pruss_disable(dev, CAN_TX_PRU_1);
+ if (s16subrtnretval == -1)
+ return -1;
+
+ return 0;
+}
+
+s16 pru_can_emu_sreset(struct device *dev)
+{
+ return 0;
+}
+
+s16 pru_can_tx(struct device *dev, u8 u8mailboxnumber, u8 u8prunumber)
+{
+ u32 u32offset = 0;
+ u32 u32value = 0;
+ s16 s16subrtnretval = -1;
+
+ if (DA8XX_PRUCORE_1 == u8prunumber) {
+ switch (u8mailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_TX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 1:
+ u32offset = (PRU_CAN_TX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 2:
+ u32offset = (PRU_CAN_TX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 3:
+ u32offset = (PRU_CAN_TX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 4:
+ u32offset = (PRU_CAN_TX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 5:
+ u32offset = (PRU_CAN_TX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 6:
+ u32offset = (PRU_CAN_TX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 7:
+ u32offset = (PRU_CAN_TX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000080;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ } else {
+
+ u32offset = (PRU_CAN_RX_INTERRUPT_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_readl(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ u32value = u32value & ~(1 << u8mailboxnumber);
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+
+ switch (u8mailboxnumber) {
+ case 0:
+ u32offset = (PRU_CAN_RX_MAILBOX0_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 1:
+ u32offset = (PRU_CAN_RX_MAILBOX1_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 2:
+ u32offset = (PRU_CAN_RX_MAILBOX2_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 3:
+ u32offset = (PRU_CAN_RX_MAILBOX3_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 4:
+ u32offset = (PRU_CAN_RX_MAILBOX4_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 5:
+ u32offset = (PRU_CAN_RX_MAILBOX5_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 6:
+ u32offset = (PRU_CAN_RX_MAILBOX6_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ case 7:
+ u32offset = (PRU_CAN_RX_MAILBOX7_STATUS_REGISTER & 0xFFFF);
+ u32value = 0x00000000;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ }
+ return 0;
+}
+
+s16 pru_can_start_abort_tx(struct device *dev, bool bcantransmitabortflag)
+{
+ u32 u32offset;
+ u32 u32value;
+ s16 s16subrtnretval;
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ u32value = 32;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+
+ u32offset = (PRUSS_INTC_ENIDXSET & 0xFFFF);
+ u32value = 32;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+
+ u32offset = (PRUSS_INTC_STATIDXSET & 0xFFFF);
+ u32value = 32;
+ s16subrtnretval = pruss_writel(dev, u32offset,
+ (u32 *) &u32value, 1);
+ if (s16subrtnretval == -1) {
+ return -1;
+ }
+ return 0;
+}
+
+s16 pru_can_mask_ints(struct device *dev, u32 int_mask)
+{
+ return 0;
+}
+
+int pru_can_get_error_cnt(struct device *dev, u8 u8prunumber)
+{
+ return 0;
+}
+
+int pru_can_get_intc_status(struct device *dev)
+{
+ u32 u32offset = 0;
+ u32 u32getvalue = 0;
+ u32 u32clrvalue = 0;
+
+ u32offset = (PRUSS_INTC_STATCLRINT1 & 0xFFFF);
+ pruss_readl(dev, u32offset, (u32 *) &u32getvalue, 1);
+
+ if (u32getvalue & 4)
+ u32clrvalue = 34; /* CLR Event 34 */
+
+ if (u32getvalue & 2)
+ u32clrvalue = 33; /* CLR Event 33 */
+
+ if (u32clrvalue) {
+ u32offset = (PRUSS_INTC_STATIDXCLR & 0xFFFF);
+ pruss_writel(dev, u32offset, &u32clrvalue, 1);
+ } else
+ return -1;
+
+ return u32getvalue;
+}
diff --git a/drivers/net/can/da8xx_pruss/pruss_can_api.h b/drivers/net/can/da8xx_pruss/pruss_can_api.h
new file mode 100644
index 0000000..7550456
--- /dev/null
+++ b/drivers/net/can/da8xx_pruss/pruss_can_api.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ * Author: Ganeshan N
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef _PRU_CAN_API_H_
+#define _PRU_CAN_API_H_
+
+#include <linux/types.h>
+#include <linux/mfd/pruss/da8xx_pru.h>
+
+
+#define CAN_BIT_TIMINGS (0x273)
+
+/* Timer Clock is sourced from DDR freq (PLL1 SYS CLK 2) */
+#define TIMER_CLK_FREQ 132000000
+
+#define TIMER_SETUP_DELAY 14
+#define GPIO_SETUP_DELAY 150
+
+#define CAN_RX_PRU_0 PRUSS_NUM0
+#define CAN_TX_PRU_1 PRUSS_NUM1
+
+/* Number of Instruction in the Delay loop */
+#define DELAY_LOOP_LENGTH 2
+
+#define PRU1_BASE_ADDR 0x2000
+
+#define PRU_CAN_TX_GLOBAL_CONTROL_REGISTER (PRU1_BASE_ADDR)
+#define PRU_CAN_TX_GLOBAL_STATUS_REGISTER (PRU1_BASE_ADDR + 0x04)
+#define PRU_CAN_TX_INTERRUPT_MASK_REGISTER (PRU1_BASE_ADDR + 0x08)
+#define PRU_CAN_TX_INTERRUPT_STATUS_REGISTER (PRU1_BASE_ADDR + 0x0C)
+#define PRU_CAN_TX_MAILBOX0_STATUS_REGISTER (PRU1_BASE_ADDR + 0x10)
+#define PRU_CAN_TX_MAILBOX1_STATUS_REGISTER (PRU1_BASE_ADDR + 0x14)
+#define PRU_CAN_TX_MAILBOX2_STATUS_REGISTER (PRU1_BASE_ADDR + 0x18)
+#define PRU_CAN_TX_MAILBOX3_STATUS_REGISTER (PRU1_BASE_ADDR + 0x1C)
+#define PRU_CAN_TX_MAILBOX4_STATUS_REGISTER (PRU1_BASE_ADDR + 0x20)
+#define PRU_CAN_TX_MAILBOX5_STATUS_REGISTER (PRU1_BASE_ADDR + 0x24)
+#define PRU_CAN_TX_MAILBOX6_STATUS_REGISTER (PRU1_BASE_ADDR + 0x28)
+#define PRU_CAN_TX_MAILBOX7_STATUS_REGISTER (PRU1_BASE_ADDR + 0x2C)
+#define PRU_CAN_TX_ERROR_COUNTER_REGISTER (PRU1_BASE_ADDR + 0x30)
+#define PRU_CAN_TX_TIMING_REGISTER (PRU1_BASE_ADDR + 0x34)
+#define PRU_CAN_TX_CLOCK_BRP_REGISTER (PRU1_BASE_ADDR + 0x38)
+
+#define PRU_CAN_TX_MAILBOX0 (PRU1_BASE_ADDR + 0x40)
+#define PRU_CAN_TX_MAILBOX1 (PRU1_BASE_ADDR + 0x50)
+#define PRU_CAN_TX_MAILBOX2 (PRU1_BASE_ADDR + 0x60)
+#define PRU_CAN_TX_MAILBOX3 (PRU1_BASE_ADDR + 0x70)
+#define PRU_CAN_TX_MAILBOX4 (PRU1_BASE_ADDR + 0x80)
+#define PRU_CAN_TX_MAILBOX5 (PRU1_BASE_ADDR + 0x90)
+#define PRU_CAN_TX_MAILBOX6 (PRU1_BASE_ADDR + 0xA0)
+#define PRU_CAN_TX_MAILBOX7 (PRU1_BASE_ADDR + 0xB0)
+
+#define PRU_CAN_TIMING_VAL_TX (PRU1_BASE_ADDR + 0xC0)
+#define PRU_CAN_TIMING_VAL_TX_SJW (PRU1_BASE_ADDR + 0xC4)
+#define PRU_CAN_TRANSMIT_FRAME (PRU1_BASE_ADDR + 0xE0)
+
+#define PRU0_BASE_ADDR 0
+
+#define PRU_CAN_RX_GLOBAL_CONTROL_REGISTER (PRU0_BASE_ADDR)
+#define PRU_CAN_RX_GLOBAL_STATUS_REGISTER (PRU0_BASE_ADDR + 0x04)
+#define PRU_CAN_RX_INTERRUPT_MASK_REGISTER (PRU0_BASE_ADDR + 0x08)
+#define PRU_CAN_RX_INTERRUPT_STATUS_REGISTER (PRU0_BASE_ADDR + 0x0C)
+#define PRU_CAN_RX_MAILBOX0_STATUS_REGISTER (PRU0_BASE_ADDR + 0x10)
+#define PRU_CAN_RX_MAILBOX1_STATUS_REGISTER (PRU0_BASE_ADDR + 0x14)
+#define PRU_CAN_RX_MAILBOX2_STATUS_REGISTER (PRU0_BASE_ADDR + 0x18)
+#define PRU_CAN_RX_MAILBOX3_STATUS_REGISTER (PRU0_BASE_ADDR + 0x1C)
+#define PRU_CAN_RX_MAILBOX4_STATUS_REGISTER (PRU0_BASE_ADDR + 0x20)
+#define PRU_CAN_RX_MAILBOX5_STATUS_REGISTER (PRU0_BASE_ADDR + 0x24)
+#define PRU_CAN_RX_MAILBOX6_STATUS_REGISTER (PRU0_BASE_ADDR + 0x28)
+#define PRU_CAN_RX_MAILBOX7_STATUS_REGISTER (PRU0_BASE_ADDR + 0x2C)
+#define PRU_CAN_RX_MAILBOX8_STATUS_REGISTER (PRU0_BASE_ADDR + 0x30)
+#define PRU_CAN_RX_ERROR_COUNTER_REGISTER (PRU0_BASE_ADDR + 0x34)
+#define PRU_CAN_RX_TIMING_REGISTER (PRU0_BASE_ADDR + 0x38)
+#define PRU_CAN_RX_CLOCK_BRP_REGISTER (PRU0_BASE_ADDR + 0x3C)
+
+#define PRU_CAN_RX_MAILBOX0 (PRU0_BASE_ADDR + 0x40)
+#define PRU_CAN_RX_MAILBOX1 (PRU0_BASE_ADDR + 0x50)
+#define PRU_CAN_RX_MAILBOX2 (PRU0_BASE_ADDR + 0x60)
+#define PRU_CAN_RX_MAILBOX3 (PRU0_BASE_ADDR + 0x70)
+#define PRU_CAN_RX_MAILBOX4 (PRU0_BASE_ADDR + 0x80)
+#define PRU_CAN_RX_MAILBOX5 (PRU0_BASE_ADDR + 0x90)
+#define PRU_CAN_RX_MAILBOX6 (PRU0_BASE_ADDR + 0xA0)
+#define PRU_CAN_RX_MAILBOX7 (PRU0_BASE_ADDR + 0xB0)
+#define PRU_CAN_RX_MAILBOX8 (PRU0_BASE_ADDR + 0xC0)
+
+#define PRU_CAN_TIMING_VAL_RX (PRU0_BASE_ADDR + 0xD0)
+#define PRU_CAN_RECEIVE_FRAME (PRU0_BASE_ADDR + 0xD4)
+#define PRU_CAN_ID_MAP (PRU0_BASE_ADDR + 0xF0)
+
+#define PRU_CAN_ERROR_ACTIVE 128
+
+#define CAN_ACK_FAILED 0xE
+#define CAN_ARBTR_FAIL 0xD
+#define CAN_BIT_ERROR 0xC
+#define CAN_TRANSMISSION_SUCCESS 0xA
+
+#define STD_DATA_FRAME 0x1
+#define EXTD_DATA_FRAME 0x2
+#define STD_REMOTE_FRAME 0x3
+#define EXTD_REMOTE_FRAME 0x4
+
+#define PRU_CAN_MAX_SJW 8
+#define PRU_CAN_MAX_PHSEG1 25
+#define PRU_CAN_MAX_PHSEG2 25
+
+#define DA8XX_PRUCANCORE_0_REGS 0x7000
+#define DA8XX_PRUCANCORE_1_REGS 0x7800
+#define PRU0_PROG_RAM_START_OFFSET 0x8000
+#define PRU1_PROG_RAM_START_OFFSET 0xC000
+#define PRU_CAN_INIT_MAX_TIMEOUT 0xFF
+
+typedef enum {
+ ecaninst0 = 0,
+ ecaninst1,
+ ecanmaxinst
+} can_instance_enum;
+
+typedef enum {
+ ecanmailbox0 = 0,
+ ecanmailbox1,
+ ecanmailbox2,
+ ecanmailbox3,
+ ecanmailbox4,
+ ecanmailbox5,
+ ecanmailbox6,
+ ecanmailbox7
+} can_mailbox_number;
+
+typedef enum {
+ ecandirectioninit = 0,
+ ecantransmit,
+ ecanreceive
+} can_transfer_direction;
+
+typedef struct {
+ u16 u16extendedidentifier;
+ u16 u16baseidentifier;
+ u8 u8data7;
+ u8 u8data6;
+ u8 u8data5;
+ u8 u8data4;
+ u8 u8data3;
+ u8 u8data2;
+ u8 u8data1;
+ u8 u8data0;
+ u16 u16datalength;
+ u16 u16crc;
+} can_mail_box_structure;
+
+typedef struct {
+ can_transfer_direction ecantransferdirection;
+} can_mailbox_config;
+
+typedef struct {
+ can_instance_enum ecaninstance;
+ can_transfer_direction ecantransferdirection;
+ can_mail_box_structure strcanmailbox;
+ can_mailbox_number ecanmailboxnumber;
+ u8 u8prunumber;
+ u32 u32globalstatus;
+ u32 u32interruptstatus;
+ u32 u32mailboxstatus;
+} can_emu_app_hndl;
+
+typedef struct {
+ bool bcaninststate;
+ can_transfer_direction ecantransferdirection;
+ u32 u32apphandlerptr;
+} can_emu_drv_inst;
+
+typedef struct {
+ u8 u8syncjumpwidth;
+ u8 u8phseg1;
+ u8 u8phseg2;
+} can_bit_timing_consts;
+
+/* Field Definition Macros */
+
+/* CONTROL */
+
+/*
+ * pru_can_set_brp() Updates the BRP register of PRU.
+ */
+s16 pru_can_set_brp(struct device *dev, u16 u16prescaler);
+
+/*
+ * pru_can_set_bit_timing() Updates the timing register of PRU
+ */
+s16 pru_can_set_bit_timing(struct device *dev,
+ can_bit_timing_consts *pstrbittiming);
+
+/*
+ * pru_can_calc_timing() Updates the timing values of PRU
+ */
+s16 pru_can_calc_timing(struct device *dev,
+ u32 u32bittiming, u32 u32bitrateprescaler);
+
+/*
+ * pru_can_write_data_to_mailbox() Updates the transmit mailboxes of PRU1
+ */
+s16 pru_can_write_data_to_mailbox(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_get_data_from_mailbox() Receive data from receive mailboxes
+ */
+s16 pru_can_get_data_from_mailbox(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_rx_id_map() Receive mailboxes ID Mapping of PRU0
+ */
+s16 pru_can_rx_id_map(struct device *dev,
+ u32 u32nodeid, can_mailbox_number ecanmailboxno);
+
+/*
+ *pru_can_get_intr_status() Get interrupts status register value
+ */
+s16 pru_can_get_intr_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+
+/*
+ * pru_can_get_global_status() Get the globalstatus register value
+ */
+s16 pru_can_get_global_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_get_mailbox_status() Get mailbox status reg value
+ */
+s16 pru_can_get_mailbox_status(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_configuration_mode_set() Sets timing val for data transfer
+ */
+s16 pru_can_config_mode_set(struct device *dev,
+ bool bconfig_modeflag);
+
+/*
+ * pru_can_emu_init() Initializes Can Emulation Parameters
+ */
+s16 pru_can_emu_init(struct device *dev,
+ u32 u32pruclock);
+
+/*
+ * pru_can_emu_open() Opens can emu for application to use
+ */
+s16 pru_can_emu_open(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_emu_close() Closes can emu for applications to use
+ */
+s16 pru_can_emu_close(struct device *dev,
+ can_emu_app_hndl *pstremuapphndl);
+
+/*
+ * pru_can_emu_exit() Diables all the PRUs
+ */
+s16 pru_can_emu_exit(struct device *dev);
+
+s16 pru_can_tx_mode_set(struct device *dev, bool btransfer_flag,
+ can_transfer_direction ecan_trx);
+
+s16 pru_can_emu_sreset(struct device *dev);
+
+s16 pru_can_tx(struct device *dev,
+ u8 u8mailboxnumber, u8 u8prunumber);
+
+s16 pru_can_start_abort_tx(struct device *dev,
+ bool btxabort_flag);
+
+s16 pru_can_mask_ints(struct device *dev, u32 int_mask);
+
+s32 pru_can_get_error_cnt(struct device *dev, u8 u8prunumber);
+
+s32 pru_can_get_intc_status(struct device *dev);
+#endif
--
1.7.2.3
^ permalink raw reply related
* Re: [PATCH v5 0/4] Adding HID Feature Report Support to hidraw
From: Jiri Kosina @ 2011-02-11 14:02 UTC (permalink / raw)
To: Gustavo F. Padovan
Cc: Alan Ott, Marcel Holtmann, David S. Miller, Michael Poole,
Eric Dumazet, linux-input, linux-kernel, linux-usb,
linux-bluetooth, netdev
In-Reply-To: <20110210181441.GB2173@joana>
On Thu, 10 Feb 2011, Gustavo F. Padovan wrote:
> > > This patch adds Feature Report support for USB and Bluetooth HID devices
> > > through hidraw.
> > >
> > > The first two patches prepare the bluetooth side for the change.
> > > a. Make sure the hidp_session() thread is started before
> > > device's probe() functions are called.
> > > b. Wait for ACK/NAK on sent reports, and return proper
> > > error codes.
> > > The third patch is the hidraw core and USB changes.
> > > The fourth patch is the Bluetooth changes.
> > >
> > > Thanks to Antonio Ospite and Bill Good for providing testing and feedback.
> > >
> > >
> > > Alan Ott (4):
> > > bt hidp: Move hid_add_device() call to after hidp_session() has
> > > started.
> > > bt hidp: Wait for ACK on Sent Reports
> > > HID: Add Support for Setting and Getting Feature Reports from hidraw
> > > Bluetooth hidp: Add support for hidraw HIDIOCGFEATURE and
> > > HIDIOCSFEATURE
> > >
> > > drivers/hid/hidraw.c | 106 +++++++++++++++++++-
> > > drivers/hid/usbhid/hid-core.c | 35 +++++++
> > > include/linux/hid.h | 3 +
> > > include/linux/hidraw.h | 3 +
> > > net/bluetooth/hidp/core.c | 214 ++++++++++++++++++++++++++++++++++++++---
> > > net/bluetooth/hidp/hidp.h | 15 +++
> >
> > Before proceeding with these patches, I'd really like to have comment
> > (ideally 'Acked-by') from Marcel on the net/bluetooth/hidp part,
> > obviously.
>
> I have tested it and it seems ok to me and to Marcel. For net/bluetooth/
>
> Acked-by: Gustavo F. Padovan <padovan@profusion.mobi>
Awesome, thanks a lot everyone for having this sorted out finally!
I will be taking the patchset through my tree.
--
Jiri Kosina
SUSE Labs, Novell Inc.
^ permalink raw reply
* Re: [PATCH 02/14] net/fec: release mem_region requested in probe in error path and remove
From: Uwe Kleine-König @ 2011-02-11 11:03 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-2-git-send-email-u.kleine-koenig@pengutronix.de>
Hello,
On Fri, Feb 11, 2011 at 11:32:10AM +0100, Uwe Kleine-König wrote:
> Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
I changed that to Reported-by: in this and the other patches.
(this was Reported-by: Wolfram Sang via irc). The updated patches can
be found at
git://git.pengutronix.de/git/ukl/linux-2.6.git fec
.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH] ip_gre: Add IPPROTO_GRE to flowi in ipgre_tunnel_xmit
From: Changli Gao @ 2011-02-11 10:44 UTC (permalink / raw)
To: Steffen Klassert; +Cc: David Miller, netdev
In-Reply-To: <20110211093040.GB29583@secunet.com>
On Fri, Feb 11, 2011 at 5:30 PM, Steffen Klassert
<steffen.klassert@secunet.com> wrote:
> Commit 5811662b15db018c740c57d037523683fd3e6123 accidentally
> removed the setting of IPPROTO_GRE from the struct flowi
> in ipgre_tunnel_xmit. This patch restores it.
>
> Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Acked-by: Changli Gao <xiaosuo@gmail.com>
--
Regards,
Changli Gao(xiaosuo@gmail.com)
^ permalink raw reply
* [PATCH 13/14] net/fec: postpone unsetting driver data until the hardware is stopped
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 0c984d6..c322971 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1465,8 +1465,6 @@ fec_drv_remove(struct platform_device *pdev)
struct fec_enet_private *fep = netdev_priv(ndev);
struct resource *r;
- platform_set_drvdata(pdev, NULL);
-
fec_stop(ndev);
fec_enet_mii_remove(fep);
clk_disable(fep->clk);
@@ -1479,6 +1477,8 @@ fec_drv_remove(struct platform_device *pdev)
BUG_ON(!r);
release_mem_region(r->start, resource_size(r));
+ platform_set_drvdata(pdev, NULL);
+
return 0;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH 14/14] net/fec: enable flow control and length check on enet-mac
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Also optimize not to reread the value written to FEC_R_CNTRL.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 24 +++++++++++++-----------
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index c322971..74798be 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -339,7 +339,8 @@ fec_restart(struct net_device *ndev, int duplex)
const struct platform_device_id *id_entry =
platform_get_device_id(fep->pdev);
int i;
- u32 val, temp_mac[2];
+ u32 temp_mac[2];
+ u32 rcntl = OPT_FRAME_SIZE | 0x04;
/* Whack a reset. We should wait for this. */
writel(1, fep->hwp + FEC_ECNTRL);
@@ -388,14 +389,14 @@ fec_restart(struct net_device *ndev, int duplex)
/* Enable MII mode */
if (duplex) {
- /* MII enable / FD enable */
- writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
+ /* FD enable */
writel(0x04, fep->hwp + FEC_X_CNTRL);
} else {
- /* MII enable / No Rcv on Xmit */
- writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
+ /* No Rcv on Xmit */
+ rcntl |= 0x02;
writel(0x0, fep->hwp + FEC_X_CNTRL);
}
+
fep->full_duplex = duplex;
/* Set MII speed */
@@ -406,21 +407,21 @@ fec_restart(struct net_device *ndev, int duplex)
* differently on enet-mac.
*/
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
- val = readl(fep->hwp + FEC_R_CNTRL);
+ /* Enable flow control and length check */
+ rcntl |= 0x40000000 | 0x00000020;
/* MII or RMII */
if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
- val |= (1 << 8);
+ rcntl |= (1 << 8);
else
- val &= ~(1 << 8);
+ rcntl &= ~(1 << 8);
/* 10M or 100M */
if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
- val &= ~(1 << 9);
+ rcntl &= ~(1 << 9);
else
- val |= (1 << 9);
+ rcntl |= (1 << 9);
- writel(val, fep->hwp + FEC_R_CNTRL);
} else {
#ifdef FEC_MIIGSK_ENR
if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
@@ -440,6 +441,7 @@ fec_restart(struct net_device *ndev, int duplex)
}
#endif
}
+ writel(rcntl, fep->hwp + FEC_R_CNTRL);
/* And last, enable the transmit and receive processing */
writel(2, fep->hwp + FEC_ECNTRL);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 09/14] net/fec: consistenly name struct net_device pointers "ndev"
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
A variable named "dev" usually (usually subjective) points to a struct
device.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 242 ++++++++++++++++++++++++++--------------------------
1 files changed, 121 insertions(+), 121 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index d3dbff5..c70503a 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -206,11 +206,11 @@ struct fec_enet_private {
};
static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
-static void fec_enet_tx(struct net_device *dev);
-static void fec_enet_rx(struct net_device *dev);
-static int fec_enet_close(struct net_device *dev);
-static void fec_restart(struct net_device *dev, int duplex);
-static void fec_stop(struct net_device *dev);
+static void fec_enet_tx(struct net_device *ndev);
+static void fec_enet_rx(struct net_device *ndev);
+static int fec_enet_close(struct net_device *ndev);
+static void fec_restart(struct net_device *ndev, int duplex);
+static void fec_stop(struct net_device *ndev);
/* FEC MII MMFR bits definition */
#define FEC_MMFR_ST (1 << 30)
@@ -238,9 +238,9 @@ static void *swap_buffer(void *bufaddr, int len)
}
static netdev_tx_t
-fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
platform_get_device_id(fep->pdev);
struct bufdesc *bdp;
@@ -261,9 +261,9 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (status & BD_ENET_TX_READY) {
/* Ooops. All transmit buffers are full. Bail out.
- * This should not happen, since dev->tbusy should be set.
+ * This should not happen, since ndev->tbusy should be set.
*/
- printk("%s: tx queue full!.\n", dev->name);
+ printk("%s: tx queue full!.\n", ndev->name);
spin_unlock_irqrestore(&fep->hw_lock, flags);
return NETDEV_TX_BUSY;
}
@@ -298,13 +298,13 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
/* Save skb pointer */
fep->tx_skbuff[fep->skb_cur] = skb;
- dev->stats.tx_bytes += skb->len;
+ ndev->stats.tx_bytes += skb->len;
fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
/* Push the data cache so the CPM does not get stale memory
* data.
*/
- bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
+ bdp->cbd_bufaddr = dma_map_single(&ndev->dev, bufaddr,
FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
/* Send it on its way. Tell FEC it's ready, interrupt when done,
@@ -325,7 +325,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (bdp == fep->dirty_tx) {
fep->tx_full = 1;
- netif_stop_queue(dev);
+ netif_stop_queue(ndev);
}
fep->cur_tx = bdp;
@@ -336,22 +336,22 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
}
static void
-fec_timeout(struct net_device *dev)
+fec_timeout(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
- dev->stats.tx_errors++;
+ ndev->stats.tx_errors++;
- fec_restart(dev, fep->full_duplex);
- netif_wake_queue(dev);
+ fec_restart(ndev, fep->full_duplex);
+ netif_wake_queue(ndev);
}
static irqreturn_t
-fec_enet_interrupt(int irq, void * dev_id)
+fec_enet_interrupt(int irq, void *dev_id)
{
- struct net_device *dev = dev_id;
- struct fec_enet_private *fep = netdev_priv(dev);
- uint int_events;
+ struct net_device *ndev = dev_id;
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ uint int_events;
irqreturn_t ret = IRQ_NONE;
do {
@@ -360,7 +360,7 @@ fec_enet_interrupt(int irq, void * dev_id)
if (int_events & FEC_ENET_RXF) {
ret = IRQ_HANDLED;
- fec_enet_rx(dev);
+ fec_enet_rx(ndev);
}
/* Transmit OK, or non-fatal error. Update the buffer
@@ -369,7 +369,7 @@ fec_enet_interrupt(int irq, void * dev_id)
*/
if (int_events & FEC_ENET_TXF) {
ret = IRQ_HANDLED;
- fec_enet_tx(dev);
+ fec_enet_tx(ndev);
}
if (int_events & FEC_ENET_MII) {
@@ -383,14 +383,14 @@ fec_enet_interrupt(int irq, void * dev_id)
static void
-fec_enet_tx(struct net_device *dev)
+fec_enet_tx(struct net_device *ndev)
{
struct fec_enet_private *fep;
struct bufdesc *bdp;
unsigned short status;
struct sk_buff *skb;
- fep = netdev_priv(dev);
+ fep = netdev_priv(ndev);
spin_lock(&fep->hw_lock);
bdp = fep->dirty_tx;
@@ -398,7 +398,7 @@ fec_enet_tx(struct net_device *dev)
if (bdp == fep->cur_tx && fep->tx_full == 0)
break;
- dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+ dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
bdp->cbd_bufaddr = 0;
skb = fep->tx_skbuff[fep->skb_dirty];
@@ -406,19 +406,19 @@ fec_enet_tx(struct net_device *dev)
if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
BD_ENET_TX_RL | BD_ENET_TX_UN |
BD_ENET_TX_CSL)) {
- dev->stats.tx_errors++;
+ ndev->stats.tx_errors++;
if (status & BD_ENET_TX_HB) /* No heartbeat */
- dev->stats.tx_heartbeat_errors++;
+ ndev->stats.tx_heartbeat_errors++;
if (status & BD_ENET_TX_LC) /* Late collision */
- dev->stats.tx_window_errors++;
+ ndev->stats.tx_window_errors++;
if (status & BD_ENET_TX_RL) /* Retrans limit */
- dev->stats.tx_aborted_errors++;
+ ndev->stats.tx_aborted_errors++;
if (status & BD_ENET_TX_UN) /* Underrun */
- dev->stats.tx_fifo_errors++;
+ ndev->stats.tx_fifo_errors++;
if (status & BD_ENET_TX_CSL) /* Carrier lost */
- dev->stats.tx_carrier_errors++;
+ ndev->stats.tx_carrier_errors++;
} else {
- dev->stats.tx_packets++;
+ ndev->stats.tx_packets++;
}
if (status & BD_ENET_TX_READY)
@@ -428,7 +428,7 @@ fec_enet_tx(struct net_device *dev)
* but we eventually sent the packet OK.
*/
if (status & BD_ENET_TX_DEF)
- dev->stats.collisions++;
+ ndev->stats.collisions++;
/* Free the sk buffer associated with this last transmit */
dev_kfree_skb_any(skb);
@@ -445,8 +445,8 @@ fec_enet_tx(struct net_device *dev)
*/
if (fep->tx_full) {
fep->tx_full = 0;
- if (netif_queue_stopped(dev))
- netif_wake_queue(dev);
+ if (netif_queue_stopped(ndev))
+ netif_wake_queue(ndev);
}
}
fep->dirty_tx = bdp;
@@ -460,9 +460,9 @@ fec_enet_tx(struct net_device *dev)
* effectively tossing the packet.
*/
static void
-fec_enet_rx(struct net_device *dev)
+fec_enet_rx(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
platform_get_device_id(fep->pdev);
struct bufdesc *bdp;
@@ -496,17 +496,17 @@ fec_enet_rx(struct net_device *dev)
/* Check for errors. */
if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
BD_ENET_RX_CR | BD_ENET_RX_OV)) {
- dev->stats.rx_errors++;
+ ndev->stats.rx_errors++;
if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
/* Frame too long or too short. */
- dev->stats.rx_length_errors++;
+ ndev->stats.rx_length_errors++;
}
if (status & BD_ENET_RX_NO) /* Frame alignment */
- dev->stats.rx_frame_errors++;
+ ndev->stats.rx_frame_errors++;
if (status & BD_ENET_RX_CR) /* CRC Error */
- dev->stats.rx_crc_errors++;
+ ndev->stats.rx_crc_errors++;
if (status & BD_ENET_RX_OV) /* FIFO overrun */
- dev->stats.rx_fifo_errors++;
+ ndev->stats.rx_fifo_errors++;
}
/* Report late collisions as a frame error.
@@ -514,15 +514,15 @@ fec_enet_rx(struct net_device *dev)
* have in the buffer. So, just drop this frame on the floor.
*/
if (status & BD_ENET_RX_CL) {
- dev->stats.rx_errors++;
- dev->stats.rx_frame_errors++;
+ ndev->stats.rx_errors++;
+ ndev->stats.rx_frame_errors++;
goto rx_processing_done;
}
/* Process the incoming frame. */
- dev->stats.rx_packets++;
+ ndev->stats.rx_packets++;
pkt_len = bdp->cbd_datlen;
- dev->stats.rx_bytes += pkt_len;
+ ndev->stats.rx_bytes += pkt_len;
data = (__u8*)__va(bdp->cbd_bufaddr);
dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
@@ -540,13 +540,13 @@ fec_enet_rx(struct net_device *dev)
if (unlikely(!skb)) {
printk("%s: Memory squeeze, dropping packet.\n",
- dev->name);
- dev->stats.rx_dropped++;
+ ndev->name);
+ ndev->stats.rx_dropped++;
} else {
skb_reserve(skb, NET_IP_ALIGN);
skb_put(skb, pkt_len - 4); /* Make room */
skb_copy_to_linear_data(skb, data, pkt_len - 4);
- skb->protocol = eth_type_trans(skb, dev);
+ skb->protocol = eth_type_trans(skb, ndev);
netif_rx(skb);
}
@@ -577,9 +577,9 @@ rx_processing_done:
}
/* ------------------------------------------------------------------------- */
-static void __inline__ fec_get_mac(struct net_device *dev)
+static void __inline__ fec_get_mac(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
unsigned char *iap, tmpaddr[ETH_ALEN];
@@ -615,11 +615,11 @@ static void __inline__ fec_get_mac(struct net_device *dev)
iap = &tmpaddr[0];
}
- memcpy(dev->dev_addr, iap, ETH_ALEN);
+ memcpy(ndev->dev_addr, iap, ETH_ALEN);
/* Adjust MAC if using macaddr */
if (iap == macaddr)
- dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
+ ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
}
/* ------------------------------------------------------------------------- */
@@ -627,9 +627,9 @@ static void __inline__ fec_get_mac(struct net_device *dev)
/*
* Phy section
*/
-static void fec_enet_adjust_link(struct net_device *dev)
+static void fec_enet_adjust_link(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct phy_device *phy_dev = fep->phy_dev;
unsigned long flags;
@@ -646,7 +646,7 @@ static void fec_enet_adjust_link(struct net_device *dev)
/* Duplex link change */
if (phy_dev->link) {
if (fep->full_duplex != phy_dev->duplex) {
- fec_restart(dev, phy_dev->duplex);
+ fec_restart(ndev, phy_dev->duplex);
status_change = 1;
}
}
@@ -655,9 +655,9 @@ static void fec_enet_adjust_link(struct net_device *dev)
if (phy_dev->link != fep->link) {
fep->link = phy_dev->link;
if (phy_dev->link)
- fec_restart(dev, phy_dev->duplex);
+ fec_restart(ndev, phy_dev->duplex);
else
- fec_stop(dev);
+ fec_stop(ndev);
status_change = 1;
}
@@ -726,9 +726,9 @@ static int fec_enet_mdio_reset(struct mii_bus *bus)
return 0;
}
-static int fec_enet_mii_probe(struct net_device *dev)
+static int fec_enet_mii_probe(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct phy_device *phy_dev = NULL;
char mdio_bus_id[MII_BUS_ID_SIZE];
char phy_name[MII_BUS_ID_SIZE + 3];
@@ -753,16 +753,16 @@ static int fec_enet_mii_probe(struct net_device *dev)
if (phy_id >= PHY_MAX_ADDR) {
printk(KERN_INFO "%s: no PHY, assuming direct connection "
- "to switch\n", dev->name);
+ "to switch\n", ndev->name);
strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
phy_id = 0;
}
snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
- phy_dev = phy_connect(dev, phy_name, &fec_enet_adjust_link, 0,
+ phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
PHY_INTERFACE_MODE_MII);
if (IS_ERR(phy_dev)) {
- printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
+ printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
return PTR_ERR(phy_dev);
}
@@ -775,7 +775,7 @@ static int fec_enet_mii_probe(struct net_device *dev)
fep->full_duplex = 0;
printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
- "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
+ "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
fep->phy_dev->irq);
@@ -785,8 +785,8 @@ static int fec_enet_mii_probe(struct net_device *dev)
static int fec_enet_mii_init(struct platform_device *pdev)
{
static struct mii_bus *fec0_mii_bus;
- struct net_device *dev = platform_get_drvdata(pdev);
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
platform_get_device_id(fep->pdev);
int err = -ENXIO, i;
@@ -844,7 +844,7 @@ static int fec_enet_mii_init(struct platform_device *pdev)
for (i = 0; i < PHY_MAX_ADDR; i++)
fep->mii_bus->irq[i] = PHY_POLL;
- platform_set_drvdata(dev, fep->mii_bus);
+ platform_set_drvdata(ndev, fep->mii_bus);
if (mdiobus_register(fep->mii_bus))
goto err_out_free_mdio_irq;
@@ -872,10 +872,10 @@ static void fec_enet_mii_remove(struct fec_enet_private *fep)
mdiobus_free(fep->mii_bus);
}
-static int fec_enet_get_settings(struct net_device *dev,
+static int fec_enet_get_settings(struct net_device *ndev,
struct ethtool_cmd *cmd)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct phy_device *phydev = fep->phy_dev;
if (!phydev)
@@ -884,10 +884,10 @@ static int fec_enet_get_settings(struct net_device *dev,
return phy_ethtool_gset(phydev, cmd);
}
-static int fec_enet_set_settings(struct net_device *dev,
+static int fec_enet_set_settings(struct net_device *ndev,
struct ethtool_cmd *cmd)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct phy_device *phydev = fep->phy_dev;
if (!phydev)
@@ -896,14 +896,14 @@ static int fec_enet_set_settings(struct net_device *dev,
return phy_ethtool_sset(phydev, cmd);
}
-static void fec_enet_get_drvinfo(struct net_device *dev,
+static void fec_enet_get_drvinfo(struct net_device *ndev,
struct ethtool_drvinfo *info)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
strcpy(info->driver, fep->pdev->dev.driver->name);
strcpy(info->version, "Revision: 1.0");
- strcpy(info->bus_info, dev_name(&dev->dev));
+ strcpy(info->bus_info, dev_name(&ndev->dev));
}
static struct ethtool_ops fec_enet_ethtool_ops = {
@@ -913,12 +913,12 @@ static struct ethtool_ops fec_enet_ethtool_ops = {
.get_link = ethtool_op_get_link,
};
-static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct phy_device *phydev = fep->phy_dev;
- if (!netif_running(dev))
+ if (!netif_running(ndev))
return -EINVAL;
if (!phydev)
@@ -927,9 +927,9 @@ static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
return phy_mii_ioctl(phydev, rq, cmd);
}
-static void fec_enet_free_buffers(struct net_device *dev)
+static void fec_enet_free_buffers(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
int i;
struct sk_buff *skb;
struct bufdesc *bdp;
@@ -939,7 +939,7 @@ static void fec_enet_free_buffers(struct net_device *dev)
skb = fep->rx_skbuff[i];
if (bdp->cbd_bufaddr)
- dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
+ dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr,
FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
if (skb)
dev_kfree_skb(skb);
@@ -951,9 +951,9 @@ static void fec_enet_free_buffers(struct net_device *dev)
kfree(fep->tx_bounce[i]);
}
-static int fec_enet_alloc_buffers(struct net_device *dev)
+static int fec_enet_alloc_buffers(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
int i;
struct sk_buff *skb;
struct bufdesc *bdp;
@@ -962,12 +962,12 @@ static int fec_enet_alloc_buffers(struct net_device *dev)
for (i = 0; i < RX_RING_SIZE; i++) {
skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
if (!skb) {
- fec_enet_free_buffers(dev);
+ fec_enet_free_buffers(ndev);
return -ENOMEM;
}
fep->rx_skbuff[i] = skb;
- bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
+ bdp->cbd_bufaddr = dma_map_single(&ndev->dev, skb->data,
FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
bdp->cbd_sc = BD_ENET_RX_EMPTY;
bdp++;
@@ -994,47 +994,47 @@ static int fec_enet_alloc_buffers(struct net_device *dev)
}
static int
-fec_enet_open(struct net_device *dev)
+fec_enet_open(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
int ret;
/* I should reset the ring buffers here, but I don't yet know
* a simple way to do that.
*/
- ret = fec_enet_alloc_buffers(dev);
+ ret = fec_enet_alloc_buffers(ndev);
if (ret)
return ret;
/* Probe and connect to PHY when open the interface */
- ret = fec_enet_mii_probe(dev);
+ ret = fec_enet_mii_probe(ndev);
if (ret) {
- fec_enet_free_buffers(dev);
+ fec_enet_free_buffers(ndev);
return ret;
}
phy_start(fep->phy_dev);
- netif_start_queue(dev);
+ netif_start_queue(ndev);
fep->opened = 1;
return 0;
}
static int
-fec_enet_close(struct net_device *dev)
+fec_enet_close(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
/* Don't know what to do yet. */
fep->opened = 0;
- netif_stop_queue(dev);
- fec_stop(dev);
+ netif_stop_queue(ndev);
+ fec_stop(ndev);
if (fep->phy_dev) {
phy_stop(fep->phy_dev);
phy_disconnect(fep->phy_dev);
}
- fec_enet_free_buffers(dev);
+ fec_enet_free_buffers(ndev);
return 0;
}
@@ -1052,14 +1052,14 @@ fec_enet_close(struct net_device *dev)
#define HASH_BITS 6 /* #bits in hash */
#define CRC32_POLY 0xEDB88320
-static void set_multicast_list(struct net_device *dev)
+static void set_multicast_list(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct netdev_hw_addr *ha;
unsigned int i, bit, data, crc, tmp;
unsigned char hash;
- if (dev->flags & IFF_PROMISC) {
+ if (ndev->flags & IFF_PROMISC) {
tmp = readl(fep->hwp + FEC_R_CNTRL);
tmp |= 0x8;
writel(tmp, fep->hwp + FEC_R_CNTRL);
@@ -1070,7 +1070,7 @@ static void set_multicast_list(struct net_device *dev)
tmp &= ~0x8;
writel(tmp, fep->hwp + FEC_R_CNTRL);
- if (dev->flags & IFF_ALLMULTI) {
+ if (ndev->flags & IFF_ALLMULTI) {
/* Catch all multicast addresses, so set the
* filter to all 1's
*/
@@ -1085,7 +1085,7 @@ static void set_multicast_list(struct net_device *dev)
writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
- netdev_for_each_mc_addr(ha, dev) {
+ netdev_for_each_mc_addr(ha, ndev) {
/* Only support group multicast for now */
if (!(ha->addr[0] & 1))
continue;
@@ -1093,7 +1093,7 @@ static void set_multicast_list(struct net_device *dev)
/* calculate crc32 value of mac address */
crc = 0xffffffff;
- for (i = 0; i < dev->addr_len; i++) {
+ for (i = 0; i < ndev->addr_len; i++) {
data = ha->addr[i];
for (bit = 0; bit < 8; bit++, data >>= 1) {
crc = (crc >> 1) ^
@@ -1120,20 +1120,20 @@ static void set_multicast_list(struct net_device *dev)
/* Set a MAC change in hardware. */
static int
-fec_set_mac_address(struct net_device *dev, void *p)
+fec_set_mac_address(struct net_device *ndev, void *p)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct sockaddr *addr = p;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
+ memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
- writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
- (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
+ writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
+ (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
fep->hwp + FEC_ADDR_LOW);
- writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
+ writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
fep->hwp + FEC_ADDR_HIGH);
return 0;
}
@@ -1154,9 +1154,9 @@ static const struct net_device_ops fec_netdev_ops = {
* XXX: We need to clean up on failure exits here.
*
*/
-static int fec_enet_init(struct net_device *dev)
+static int fec_enet_init(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
struct bufdesc *cbd_base;
struct bufdesc *bdp;
int i;
@@ -1171,19 +1171,19 @@ static int fec_enet_init(struct net_device *dev)
spin_lock_init(&fep->hw_lock);
- fep->netdev = dev;
+ fep->netdev = ndev;
/* Get the Ethernet address */
- fec_get_mac(dev);
+ fec_get_mac(ndev);
/* Set receive and transmit descriptor base. */
fep->rx_bd_base = cbd_base;
fep->tx_bd_base = cbd_base + RX_RING_SIZE;
/* The FEC Ethernet specific entries in the device structure */
- dev->watchdog_timeo = TX_TIMEOUT;
- dev->netdev_ops = &fec_netdev_ops;
- dev->ethtool_ops = &fec_enet_ethtool_ops;
+ ndev->watchdog_timeo = TX_TIMEOUT;
+ ndev->netdev_ops = &fec_netdev_ops;
+ ndev->ethtool_ops = &fec_enet_ethtool_ops;
/* Initialize the receive buffer descriptors. */
bdp = fep->rx_bd_base;
@@ -1212,7 +1212,7 @@ static int fec_enet_init(struct net_device *dev)
bdp--;
bdp->cbd_sc |= BD_SC_WRAP;
- fec_restart(dev, 0);
+ fec_restart(ndev, 0);
return 0;
}
@@ -1222,9 +1222,9 @@ static int fec_enet_init(struct net_device *dev)
* duplex.
*/
static void
-fec_restart(struct net_device *dev, int duplex)
+fec_restart(struct net_device *ndev, int duplex)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
const struct platform_device_id *id_entry =
platform_get_device_id(fep->pdev);
int i;
@@ -1239,7 +1239,7 @@ fec_restart(struct net_device *dev, int duplex)
* so need to reconfigure it.
*/
if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
- memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+ memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
}
@@ -1339,9 +1339,9 @@ fec_restart(struct net_device *dev, int duplex)
}
static void
-fec_stop(struct net_device *dev)
+fec_stop(struct net_device *ndev)
{
- struct fec_enet_private *fep = netdev_priv(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
/* We cannot expect a graceful transmit stop without link !!! */
if (fep->link) {
--
1.7.2.3
^ permalink raw reply related
* [PATCH 07/14] net/fec: consolidate all i.MX options to CONFIG_ARM
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Moreover stop listing all i.MX platforms featuring a FEC, and use
the platform's config symbol that selects registration of a fec device
instead. This might make it easier to add new platforms.
Set default = y for ARMs having a fec to reduce defconfig sizes.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/Kconfig | 3 ++-
drivers/net/fec.c | 5 ++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 0382332..65027a7 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1944,7 +1944,8 @@ config 68360_ENET
config FEC
bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
depends on M523x || M527x || M5272 || M528x || M520x || M532x || \
- MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28
+ IMX_HAVE_PLATFORM_FEC || MXS_HAVE_PLATFORM_FEC
+ default IMX_HAVE_PLATFORM_FEC || MXS_HAVE_PLATFORM_FEC if ARM
select PHYLIB
help
Say Y here if you want to use the built-in 10/100 Fast ethernet
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 14eb660..dd4e580 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -54,7 +54,7 @@
#include "fec.h"
-#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
+#if defined(CONFIG_ARM)
#define FEC_ALIGNMENT 0xf
#else
#define FEC_ALIGNMENT 0x3
@@ -147,8 +147,7 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
* account when setting it.
*/
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
- defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
- defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
+ defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
#else
#define OPT_FRAME_SIZE 0
--
1.7.2.3
^ permalink raw reply related
* [PATCH 02/14] net/fec: release mem_region requested in probe in error path and remove
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 14 ++++++++++++--
1 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 3e6e923..b079826 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1377,8 +1377,10 @@ fec_probe(struct platform_device *pdev)
/* Init network device */
ndev = alloc_etherdev(sizeof(struct fec_enet_private));
- if (!ndev)
- return -ENOMEM;
+ if (!ndev) {
+ ret = -ENOMEM;
+ goto failed_alloc_etherdev;
+ }
SET_NETDEV_DEV(ndev, &pdev->dev);
@@ -1456,6 +1458,8 @@ failed_irq:
iounmap((void __iomem *)ndev->base_addr);
failed_ioremap:
free_netdev(ndev);
+failed_alloc_etherdev:
+ release_mem_region(r->start, resource_size(r));
return ret;
}
@@ -1465,6 +1469,7 @@ fec_drv_remove(struct platform_device *pdev)
{
struct net_device *ndev = platform_get_drvdata(pdev);
struct fec_enet_private *fep = netdev_priv(ndev);
+ struct resource *r;
platform_set_drvdata(pdev, NULL);
@@ -1475,6 +1480,11 @@ fec_drv_remove(struct platform_device *pdev)
iounmap((void __iomem *)ndev->base_addr);
unregister_netdev(ndev);
free_netdev(ndev);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ BUG_ON(!r);
+ release_mem_region(r->start, resource_size(r));
+
return 0;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH 06/14] net/fec: put the ioremap cookie immediately into a void __iomem pointer
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Saving it first into struct net_device->base_addr (which is an unsigned
long) is pointless and only needs to use more casts than necessary.
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 9 ++++-----
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 9a25e1e..14eb660 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1170,7 +1170,6 @@ static int fec_enet_init(struct net_device *dev)
spin_lock_init(&fep->hw_lock);
- fep->hwp = (void __iomem *)dev->base_addr;
fep->netdev = dev;
/* Get the Ethernet address */
@@ -1387,10 +1386,10 @@ fec_probe(struct platform_device *pdev)
/* setup board info structure */
fep = netdev_priv(ndev);
- ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
+ fep->hwp = ioremap(r->start, resource_size(r));
fep->pdev = pdev;
- if (!ndev->base_addr) {
+ if (!fep->hwp) {
ret = -ENOMEM;
goto failed_ioremap;
}
@@ -1453,7 +1452,7 @@ failed_clk:
free_irq(irq, ndev);
}
failed_irq:
- iounmap((void __iomem *)ndev->base_addr);
+ iounmap(fep->hwp);
failed_ioremap:
free_netdev(ndev);
failed_alloc_etherdev:
@@ -1475,7 +1474,7 @@ fec_drv_remove(struct platform_device *pdev)
fec_enet_mii_remove(fep);
clk_disable(fep->clk);
clk_put(fep->clk);
- iounmap((void __iomem *)ndev->base_addr);
+ iounmap(fep->hwp);
unregister_netdev(ndev);
free_netdev(ndev);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 11/14] net/fec: reorder functions a bit allows removing forward declarations
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 353 ++++++++++++++++++++++++++---------------------------
1 files changed, 174 insertions(+), 179 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 4c888f1..3f5dfe2 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -205,13 +205,6 @@ struct fec_enet_private {
struct completion mdio_done;
};
-static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
-static void fec_enet_tx(struct net_device *ndev);
-static void fec_enet_rx(struct net_device *ndev);
-static int fec_enet_close(struct net_device *ndev);
-static void fec_restart(struct net_device *ndev, int duplex);
-static void fec_stop(struct net_device *ndev);
-
/* FEC MII MMFR bits definition */
#define FEC_MMFR_ST (1 << 30)
#define FEC_MMFR_OP_READ (2 << 28)
@@ -335,54 +328,160 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
return NETDEV_TX_OK;
}
+/* This function is called to start or restart the FEC during a link
+ * change. This only happens when switching between half and full
+ * duplex.
+ */
static void
-fec_timeout(struct net_device *ndev)
+fec_restart(struct net_device *ndev, int duplex)
{
struct fec_enet_private *fep = netdev_priv(ndev);
+ const struct platform_device_id *id_entry =
+ platform_get_device_id(fep->pdev);
+ int i;
+ u32 val, temp_mac[2];
- ndev->stats.tx_errors++;
+ /* Whack a reset. We should wait for this. */
+ writel(1, fep->hwp + FEC_ECNTRL);
+ udelay(10);
- fec_restart(ndev, fep->full_duplex);
- netif_wake_queue(ndev);
-}
+ /*
+ * enet-mac reset will reset mac address registers too,
+ * so need to reconfigure it.
+ */
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+ memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
+ writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+ writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+ }
-static irqreturn_t
-fec_enet_interrupt(int irq, void *dev_id)
-{
- struct net_device *ndev = dev_id;
- struct fec_enet_private *fep = netdev_priv(ndev);
- uint int_events;
- irqreturn_t ret = IRQ_NONE;
+ /* Clear any outstanding interrupt. */
+ writel(0xffc00000, fep->hwp + FEC_IEVENT);
- do {
- int_events = readl(fep->hwp + FEC_IEVENT);
- writel(int_events, fep->hwp + FEC_IEVENT);
+ /* Reset all multicast. */
+ writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+ writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
+#ifndef CONFIG_M5272
+ writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
+ writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
+#endif
- if (int_events & FEC_ENET_RXF) {
- ret = IRQ_HANDLED;
- fec_enet_rx(ndev);
- }
+ /* Set maximum receive buffer size. */
+ writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
- /* Transmit OK, or non-fatal error. Update the buffer
- * descriptors. FEC handles all errors, we just discover
- * them as part of the transmit process.
- */
- if (int_events & FEC_ENET_TXF) {
- ret = IRQ_HANDLED;
- fec_enet_tx(ndev);
+ /* Set receive and transmit descriptor base. */
+ writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
+ writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
+ fep->hwp + FEC_X_DES_START);
+
+ fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
+ fep->cur_rx = fep->rx_bd_base;
+
+ /* Reset SKB transmit buffers. */
+ fep->skb_cur = fep->skb_dirty = 0;
+ for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+ if (fep->tx_skbuff[i]) {
+ dev_kfree_skb_any(fep->tx_skbuff[i]);
+ fep->tx_skbuff[i] = NULL;
}
+ }
- if (int_events & FEC_ENET_MII) {
- ret = IRQ_HANDLED;
- complete(&fep->mdio_done);
+ /* Enable MII mode */
+ if (duplex) {
+ /* MII enable / FD enable */
+ writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
+ writel(0x04, fep->hwp + FEC_X_CNTRL);
+ } else {
+ /* MII enable / No Rcv on Xmit */
+ writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
+ writel(0x0, fep->hwp + FEC_X_CNTRL);
+ }
+ fep->full_duplex = duplex;
+
+ /* Set MII speed */
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+
+ /*
+ * The phy interface and speed need to get configured
+ * differently on enet-mac.
+ */
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+ val = readl(fep->hwp + FEC_R_CNTRL);
+
+ /* MII or RMII */
+ if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val |= (1 << 8);
+ else
+ val &= ~(1 << 8);
+
+ /* 10M or 100M */
+ if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
+ val &= ~(1 << 9);
+ else
+ val |= (1 << 9);
+
+ writel(val, fep->hwp + FEC_R_CNTRL);
+ } else {
+#ifdef FEC_MIIGSK_ENR
+ if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ /* disable the gasket and wait */
+ writel(0, fep->hwp + FEC_MIIGSK_ENR);
+ while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
+ udelay(1);
+
+ /*
+ * configure the gasket:
+ * RMII, 50 MHz, no loopback, no echo
+ */
+ writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+
+ /* re-enable the gasket */
+ writel(2, fep->hwp + FEC_MIIGSK_ENR);
}
- } while (int_events);
+#endif
+ }
- return ret;
+ /* And last, enable the transmit and receive processing */
+ writel(2, fep->hwp + FEC_ECNTRL);
+ writel(0, fep->hwp + FEC_R_DES_ACTIVE);
+
+ /* Enable interrupts we wish to service */
+ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+}
+
+static void
+fec_stop(struct net_device *ndev)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ /* We cannot expect a graceful transmit stop without link !!! */
+ if (fep->link) {
+ writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
+ udelay(10);
+ if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
+ printk("fec_stop : Graceful transmit stop did not complete !\n");
+ }
+
+ /* Whack a reset. We should wait for this. */
+ writel(1, fep->hwp + FEC_ECNTRL);
+ udelay(10);
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
}
static void
+fec_timeout(struct net_device *ndev)
+{
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ ndev->stats.tx_errors++;
+
+ fec_restart(ndev, fep->full_duplex);
+ netif_wake_queue(ndev);
+}
+
+static void
fec_enet_tx(struct net_device *ndev)
{
struct fec_enet_private *fep;
@@ -576,6 +675,43 @@ rx_processing_done:
spin_unlock(&fep->hw_lock);
}
+static irqreturn_t
+fec_enet_interrupt(int irq, void *dev_id)
+{
+ struct net_device *ndev = dev_id;
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ uint int_events;
+ irqreturn_t ret = IRQ_NONE;
+
+ do {
+ int_events = readl(fep->hwp + FEC_IEVENT);
+ writel(int_events, fep->hwp + FEC_IEVENT);
+
+ if (int_events & FEC_ENET_RXF) {
+ ret = IRQ_HANDLED;
+ fec_enet_rx(ndev);
+ }
+
+ /* Transmit OK, or non-fatal error. Update the buffer
+ * descriptors. FEC handles all errors, we just discover
+ * them as part of the transmit process.
+ */
+ if (int_events & FEC_ENET_TXF) {
+ ret = IRQ_HANDLED;
+ fec_enet_tx(ndev);
+ }
+
+ if (int_events & FEC_ENET_MII) {
+ ret = IRQ_HANDLED;
+ complete(&fep->mdio_done);
+ }
+ } while (int_events);
+
+ return ret;
+}
+
+
+
/* ------------------------------------------------------------------------- */
static void __inline__ fec_get_mac(struct net_device *ndev)
{
@@ -1217,147 +1353,6 @@ static int fec_enet_init(struct net_device *ndev)
return 0;
}
-/* This function is called to start or restart the FEC during a link
- * change. This only happens when switching between half and full
- * duplex.
- */
-static void
-fec_restart(struct net_device *ndev, int duplex)
-{
- struct fec_enet_private *fep = netdev_priv(ndev);
- const struct platform_device_id *id_entry =
- platform_get_device_id(fep->pdev);
- int i;
- u32 val, temp_mac[2];
-
- /* Whack a reset. We should wait for this. */
- writel(1, fep->hwp + FEC_ECNTRL);
- udelay(10);
-
- /*
- * enet-mac reset will reset mac address registers too,
- * so need to reconfigure it.
- */
- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
- memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
- writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
- writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
- }
-
- /* Clear any outstanding interrupt. */
- writel(0xffc00000, fep->hwp + FEC_IEVENT);
-
- /* Reset all multicast. */
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
-#ifndef CONFIG_M5272
- writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
- writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
-#endif
-
- /* Set maximum receive buffer size. */
- writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
-
- /* Set receive and transmit descriptor base. */
- writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
- writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
- fep->hwp + FEC_X_DES_START);
-
- fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
- fep->cur_rx = fep->rx_bd_base;
-
- /* Reset SKB transmit buffers. */
- fep->skb_cur = fep->skb_dirty = 0;
- for (i = 0; i <= TX_RING_MOD_MASK; i++) {
- if (fep->tx_skbuff[i]) {
- dev_kfree_skb_any(fep->tx_skbuff[i]);
- fep->tx_skbuff[i] = NULL;
- }
- }
-
- /* Enable MII mode */
- if (duplex) {
- /* MII enable / FD enable */
- writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
- writel(0x04, fep->hwp + FEC_X_CNTRL);
- } else {
- /* MII enable / No Rcv on Xmit */
- writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
- writel(0x0, fep->hwp + FEC_X_CNTRL);
- }
- fep->full_duplex = duplex;
-
- /* Set MII speed */
- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
-
- /*
- * The phy interface and speed need to get configured
- * differently on enet-mac.
- */
- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
- val = readl(fep->hwp + FEC_R_CNTRL);
-
- /* MII or RMII */
- if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
- val |= (1 << 8);
- else
- val &= ~(1 << 8);
-
- /* 10M or 100M */
- if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
- val &= ~(1 << 9);
- else
- val |= (1 << 9);
-
- writel(val, fep->hwp + FEC_R_CNTRL);
- } else {
-#ifdef FEC_MIIGSK_ENR
- if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
- /* disable the gasket and wait */
- writel(0, fep->hwp + FEC_MIIGSK_ENR);
- while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
- udelay(1);
-
- /*
- * configure the gasket:
- * RMII, 50 MHz, no loopback, no echo
- */
- writel(1, fep->hwp + FEC_MIIGSK_CFGR);
-
- /* re-enable the gasket */
- writel(2, fep->hwp + FEC_MIIGSK_ENR);
- }
-#endif
- }
-
- /* And last, enable the transmit and receive processing */
- writel(2, fep->hwp + FEC_ECNTRL);
- writel(0, fep->hwp + FEC_R_DES_ACTIVE);
-
- /* Enable interrupts we wish to service */
- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
-}
-
-static void
-fec_stop(struct net_device *ndev)
-{
- struct fec_enet_private *fep = netdev_priv(ndev);
-
- /* We cannot expect a graceful transmit stop without link !!! */
- if (fep->link) {
- writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
- udelay(10);
- if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
- printk("fec_stop : Graceful transmit stop did not complete !\n");
- }
-
- /* Whack a reset. We should wait for this. */
- writel(1, fep->hwp + FEC_ECNTRL);
- udelay(10);
- writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
-}
-
static int __devinit
fec_probe(struct platform_device *pdev)
{
--
1.7.2.3
^ permalink raw reply related
* [PATCH 12/14] net/fec: provide device for dma functions and matching sizes for map and unmap
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
This fixes warnings when CONFIG_DMA_API_DEBUG=y:
NULL NULL: DMA-API: device driver tries to free DMA memory it has not allocated [device address=0x000000004781a020] [size=64 bytes]
net eth0: DMA-API: device driver frees DMA memory with different size [device address=0x000000004781a020] [map size=2048 bytes] [unmap size=64 bytes]
Moreover pass the platform device to dma_{,un}map_single which makes
more sense because the logical network device doesn't know anything
about dma.
Passing the platform device was a suggestion by Lothar Waßmann.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 17 +++++++++--------
1 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 3f5dfe2..0c984d6 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -297,7 +297,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
/* Push the data cache so the CPM does not get stale memory
* data.
*/
- bdp->cbd_bufaddr = dma_map_single(&ndev->dev, bufaddr,
+ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
/* Send it on its way. Tell FEC it's ready, interrupt when done,
@@ -497,7 +497,8 @@ fec_enet_tx(struct net_device *ndev)
if (bdp == fep->cur_tx && fep->tx_full == 0)
break;
- dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
+ FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
bdp->cbd_bufaddr = 0;
skb = fep->tx_skbuff[fep->skb_dirty];
@@ -624,8 +625,8 @@ fec_enet_rx(struct net_device *ndev)
ndev->stats.rx_bytes += pkt_len;
data = (__u8*)__va(bdp->cbd_bufaddr);
- dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
- DMA_FROM_DEVICE);
+ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
+ FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
swap_buffer(data, pkt_len);
@@ -649,8 +650,8 @@ fec_enet_rx(struct net_device *ndev)
netif_rx(skb);
}
- bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
- DMA_FROM_DEVICE);
+ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
+ FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
rx_processing_done:
/* Clear the status flags for this buffer */
status &= ~BD_ENET_RX_STATS;
@@ -1075,7 +1076,7 @@ static void fec_enet_free_buffers(struct net_device *ndev)
skb = fep->rx_skbuff[i];
if (bdp->cbd_bufaddr)
- dma_unmap_single(&ndev->dev, bdp->cbd_bufaddr,
+ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
if (skb)
dev_kfree_skb(skb);
@@ -1103,7 +1104,7 @@ static int fec_enet_alloc_buffers(struct net_device *ndev)
}
fep->rx_skbuff[i] = skb;
- bdp->cbd_bufaddr = dma_map_single(&ndev->dev, skb->data,
+ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
bdp->cbd_sc = BD_ENET_RX_EMPTY;
bdp++;
--
1.7.2.3
^ permalink raw reply related
* [PATCH 03/14] net/fec: don't free an irq that failed to be requested
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
Noticed-by: Lothar Waßmann <LW@KARO-elektronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index b079826..aa1db8e 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1409,10 +1409,9 @@ fec_probe(struct platform_device *pdev)
break;
ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
if (ret) {
- while (i >= 0) {
+ while (--i >= 0) {
irq = platform_get_irq(pdev, i);
free_irq(irq, ndev);
- i--;
}
goto failed_irq;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH 05/14] net/fec: no need to memzero private data
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
alloc_etherdev internally uses kzalloc, so the private data is already
zerod out.
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 8026a16..9a25e1e 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1386,7 +1386,6 @@ fec_probe(struct platform_device *pdev)
/* setup board info structure */
fep = netdev_priv(ndev);
- memset(fep, 0, sizeof(*fep));
ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
fep->pdev = pdev;
--
1.7.2.3
^ permalink raw reply related
* [PATCH 04/14] net/fec: no need to check for validity of ndev in suspend and resume
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
dev_set_drvdata is called unconditionally in the probe function and so
it cannot be NULL.
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 28 ++++++++++++----------------
1 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index aa1db8e..8026a16 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1492,16 +1492,14 @@ static int
fec_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
- struct fec_enet_private *fep;
+ struct fec_enet_private *fep = netdev_priv(ndev);
- if (ndev) {
- fep = netdev_priv(ndev);
- if (netif_running(ndev)) {
- fec_stop(ndev);
- netif_device_detach(ndev);
- }
- clk_disable(fep->clk);
+ if (netif_running(ndev)) {
+ fec_stop(ndev);
+ netif_device_detach(ndev);
}
+ clk_disable(fep->clk);
+
return 0;
}
@@ -1509,16 +1507,14 @@ static int
fec_resume(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
- struct fec_enet_private *fep;
+ struct fec_enet_private *fep = netdev_priv(ndev);
- if (ndev) {
- fep = netdev_priv(ndev);
- clk_enable(fep->clk);
- if (netif_running(ndev)) {
- fec_restart(ndev, fep->full_duplex);
- netif_device_attach(ndev);
- }
+ clk_enable(fep->clk);
+ if (netif_running(ndev)) {
+ fec_restart(ndev, fep->full_duplex);
+ netif_device_attach(ndev);
}
+
return 0;
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH 08/14] net/fec: add phy_stop to fec_enet_close
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
This undoes the effects of phy_start in fec_enet_open.
Noticed-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index dd4e580..d3dbff5 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1029,8 +1029,10 @@ fec_enet_close(struct net_device *dev)
netif_stop_queue(dev);
fec_stop(dev);
- if (fep->phy_dev)
+ if (fep->phy_dev) {
+ phy_stop(fep->phy_dev);
phy_disconnect(fep->phy_dev);
+ }
fec_enet_free_buffers(dev);
--
1.7.2.3
^ permalink raw reply related
* [PATCH 01/14] net/fec: no need to cast arguments for memcpy
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
memcpy takes a const void * as 2nd argument. So the argument is
converted automatically to void * anyhow.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 2a71373..3e6e923 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -284,7 +284,7 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
unsigned int index;
index = bdp - fep->tx_bd_base;
- memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
+ memcpy(fep->tx_bounce[index], skb->data, skb->len);
bufaddr = fep->tx_bounce[index];
}
--
1.7.2.3
^ permalink raw reply related
* [PATCH 10/14] net/fec: some whitespace cleanup
From: Uwe Kleine-König @ 2011-02-11 10:32 UTC (permalink / raw)
To: netdev; +Cc: Shawn Guo, kernel
In-Reply-To: <1297420342-17739-1-git-send-email-u.kleine-koenig@pengutronix.de>
A few of these were found and reported by Lothar Waßmann.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
drivers/net/fec.c | 22 +++++++++++-----------
1 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index c70503a..4c888f1 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -182,7 +182,7 @@ struct fec_enet_private {
struct bufdesc *rx_bd_base;
struct bufdesc *tx_bd_base;
/* The next free ring entry */
- struct bufdesc *cur_rx, *cur_tx;
+ struct bufdesc *cur_rx, *cur_tx;
/* The ring entries to be free()ed */
struct bufdesc *dirty_tx;
@@ -190,15 +190,15 @@ struct fec_enet_private {
/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
spinlock_t hw_lock;
- struct platform_device *pdev;
+ struct platform_device *pdev;
int opened;
/* Phylib and MDIO interface */
- struct mii_bus *mii_bus;
- struct phy_device *phy_dev;
- int mii_timeout;
- uint phy_speed;
+ struct mii_bus *mii_bus;
+ struct phy_device *phy_dev;
+ int mii_timeout;
+ uint phy_speed;
phy_interface_t phy_interface;
int link;
int full_duplex;
@@ -525,8 +525,8 @@ fec_enet_rx(struct net_device *ndev)
ndev->stats.rx_bytes += pkt_len;
data = (__u8*)__va(bdp->cbd_bufaddr);
- dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
- DMA_FROM_DEVICE);
+ dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
+ DMA_FROM_DEVICE);
if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
swap_buffer(data, pkt_len);
@@ -550,7 +550,7 @@ fec_enet_rx(struct net_device *ndev)
netif_rx(skb);
}
- bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
+ bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
DMA_FROM_DEVICE);
rx_processing_done:
/* Clear the status flags for this buffer */
@@ -1034,7 +1034,7 @@ fec_enet_close(struct net_device *ndev)
phy_disconnect(fep->phy_dev);
}
- fec_enet_free_buffers(ndev);
+ fec_enet_free_buffers(ndev);
return 0;
}
@@ -1147,7 +1147,7 @@ static const struct net_device_ops fec_netdev_ops = {
.ndo_validate_addr = eth_validate_addr,
.ndo_tx_timeout = fec_timeout,
.ndo_set_mac_address = fec_set_mac_address,
- .ndo_do_ioctl = fec_enet_ioctl,
+ .ndo_do_ioctl = fec_enet_ioctl,
};
/*
--
1.7.2.3
^ permalink raw reply related
* [PATCH net-next-2.6 v7 1/1] can: c_can: Added support for Bosch C_CAN controller
From: Bhupesh Sharma @ 2011-02-11 10:17 UTC (permalink / raw)
To: netdev-u79uwXL29TY76Z2rM5mHXA; +Cc: Socketcan-core-0fE9KPoRgkgATYTw5x5z8w
Bosch C_CAN controller is a full-CAN implementation which is compliant
to CAN protocol version 2.0 part A and B. Bosch C_CAN user manual can be
obtained from:
http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/
c_can/users_manual_c_can.pdf
This patch adds the support for this controller.
The following are the design choices made while writing the controller
driver:
1. Interface Register set IF1 has be used only in the current design.
2. Out of the 32 Message objects available, 16 are kept aside for RX
purposes and the rest for TX purposes.
3. NAPI implementation is such that both the TX and RX paths function
in polling mode.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
---
Changes since V6:
1. Added check for calling netif_stop_queue() in case next TX object
is busy.
2. Added logic *not* to copy data to rx'ed RTR frames.
3. Moved enums, defines and structs present in c_can.h file to the respective
c-file where they are actually used.
4. Corrected message object busy status routine by using a better name
and design approach.
5. Moved *set_bittiming* call to the *c_can_chip_config* function.
drivers/net/can/Kconfig | 2 +
drivers/net/can/Makefile | 1 +
drivers/net/can/c_can/Kconfig | 15 +
drivers/net/can/c_can/Makefile | 8 +
drivers/net/can/c_can/c_can.c | 1158 ++++++++++++++++++++++++++++++++
drivers/net/can/c_can/c_can.h | 86 +++
drivers/net/can/c_can/c_can_platform.c | 207 ++++++
7 files changed, 1477 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/can/c_can/Kconfig
create mode 100644 drivers/net/can/c_can/Makefile
create mode 100644 drivers/net/can/c_can/c_can.c
create mode 100644 drivers/net/can/c_can/c_can.h
create mode 100644 drivers/net/can/c_can/c_can_platform.c
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 5dec456..1d699e3 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -115,6 +115,8 @@ source "drivers/net/can/mscan/Kconfig"
source "drivers/net/can/sja1000/Kconfig"
+source "drivers/net/can/c_can/Kconfig"
+
source "drivers/net/can/usb/Kconfig"
source "drivers/net/can/softing/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 53c82a7..24ebfe8 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -13,6 +13,7 @@ obj-y += softing/
obj-$(CONFIG_CAN_SJA1000) += sja1000/
obj-$(CONFIG_CAN_MSCAN) += mscan/
+obj-$(CONFIG_CAN_C_CAN) += c_can/
obj-$(CONFIG_CAN_AT91) += at91_can.o
obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
obj-$(CONFIG_CAN_MCP251X) += mcp251x.o
diff --git a/drivers/net/can/c_can/Kconfig b/drivers/net/can/c_can/Kconfig
new file mode 100644
index 0000000..ffb9773
--- /dev/null
+++ b/drivers/net/can/c_can/Kconfig
@@ -0,0 +1,15 @@
+menuconfig CAN_C_CAN
+ tristate "Bosch C_CAN devices"
+ depends on CAN_DEV && HAS_IOMEM
+
+if CAN_C_CAN
+
+config CAN_C_CAN_PLATFORM
+ tristate "Generic Platform Bus based C_CAN driver"
+ ---help---
+ This driver adds support for the C_CAN chips connected to
+ the "platform bus" (Linux abstraction for directly to the
+ processor attached devices) which can be found on various
+ boards from ST Microelectronics (http://www.st.com)
+ like the SPEAr1310 and SPEAr320 evaluation boards.
+endif
diff --git a/drivers/net/can/c_can/Makefile b/drivers/net/can/c_can/Makefile
new file mode 100644
index 0000000..9273f6d
--- /dev/null
+++ b/drivers/net/can/c_can/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the Bosch C_CAN controller drivers.
+#
+
+obj-$(CONFIG_CAN_C_CAN) += c_can.o
+obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o
+
+ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
new file mode 100644
index 0000000..1405078
--- /dev/null
+++ b/drivers/net/can/c_can/c_can.c
@@ -0,0 +1,1158 @@
+/*
+ * CAN bus driver for Bosch C_CAN controller
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
+ *
+ * Borrowed heavily from the C_CAN driver originally written by:
+ * Copyright (C) 2007
+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
+ *
+ * TX and RX NAPI implementation has been borrowed from at91 CAN driver
+ * written by:
+ * Copyright
+ * (C) 2007 by Hans J. Koch <hjk-vqZO0P4V72/QD6PfKP4TzA@public.gmane.org>
+ * (C) 2008, 2009 by Marc Kleine-Budde <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ *
+ * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ * Bosch C_CAN user manual can be obtained from:
+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
+ * users_manual_c_can.pdf
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <linux/can.h>
+#include <linux/can/dev.h>
+#include <linux/can/error.h>
+
+#include "c_can.h"
+
+/* control register */
+#define CONTROL_TEST BIT(7)
+#define CONTROL_CCE BIT(6)
+#define CONTROL_DISABLE_AR BIT(5)
+#define CONTROL_ENABLE_AR (0 << 5)
+#define CONTROL_EIE BIT(3)
+#define CONTROL_SIE BIT(2)
+#define CONTROL_IE BIT(1)
+#define CONTROL_INIT BIT(0)
+
+/* test register */
+#define TEST_RX BIT(7)
+#define TEST_TX1 BIT(6)
+#define TEST_TX2 BIT(5)
+#define TEST_LBACK BIT(4)
+#define TEST_SILENT BIT(3)
+#define TEST_BASIC BIT(2)
+
+/* status register */
+#define STATUS_BOFF BIT(7)
+#define STATUS_EWARN BIT(6)
+#define STATUS_EPASS BIT(5)
+#define STATUS_RXOK BIT(4)
+#define STATUS_TXOK BIT(3)
+
+/* error counter register */
+#define ERR_CNT_TEC_MASK 0xff
+#define ERR_CNT_TEC_SHIFT 0
+#define ERR_CNT_REC_SHIFT 8
+#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
+#define ERR_CNT_RP_SHIFT 15
+#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
+
+/* bit-timing register */
+#define BTR_BRP_MASK 0x3f
+#define BTR_BRP_SHIFT 0
+#define BTR_SJW_SHIFT 6
+#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
+#define BTR_TSEG1_SHIFT 8
+#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
+#define BTR_TSEG2_SHIFT 12
+#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
+
+/* brp extension register */
+#define BRP_EXT_BRPE_MASK 0x0f
+#define BRP_EXT_BRPE_SHIFT 0
+
+/* IFx command request */
+#define IF_COMR_BUSY BIT(15)
+
+/* IFx command mask */
+#define IF_COMM_WR BIT(7)
+#define IF_COMM_MASK BIT(6)
+#define IF_COMM_ARB BIT(5)
+#define IF_COMM_CONTROL BIT(4)
+#define IF_COMM_CLR_INT_PND BIT(3)
+#define IF_COMM_TXRQST BIT(2)
+#define IF_COMM_DATAA BIT(1)
+#define IF_COMM_DATAB BIT(0)
+#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
+ IF_COMM_CONTROL | IF_COMM_TXRQST | \
+ IF_COMM_DATAA | IF_COMM_DATAB)
+
+/* IFx arbitration */
+#define IF_ARB_MSGVAL BIT(15)
+#define IF_ARB_MSGXTD BIT(14)
+#define IF_ARB_TRANSMIT BIT(13)
+
+/* IFx message control */
+#define IF_MCONT_NEWDAT BIT(15)
+#define IF_MCONT_MSGLST BIT(14)
+#define IF_MCONT_CLR_MSGLST (0 << 14)
+#define IF_MCONT_INTPND BIT(13)
+#define IF_MCONT_UMASK BIT(12)
+#define IF_MCONT_TXIE BIT(11)
+#define IF_MCONT_RXIE BIT(10)
+#define IF_MCONT_RMTEN BIT(9)
+#define IF_MCONT_TXRQST BIT(8)
+#define IF_MCONT_EOB BIT(7)
+#define IF_MCONT_DLC_MASK 0xf
+
+/*
+ * IFx register masks:
+ * allow easy operation on 16-bit registers when the
+ * argument is 32-bit instead
+ */
+#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
+#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
+
+/* message object split */
+#define C_CAN_NO_OF_OBJECTS 32
+#define C_CAN_MSG_OBJ_RX_NUM 16
+#define C_CAN_MSG_OBJ_TX_NUM 16
+
+#define C_CAN_MSG_OBJ_RX_FIRST 1
+#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
+ C_CAN_MSG_OBJ_RX_NUM - 1)
+
+#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
+#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
+ C_CAN_MSG_OBJ_TX_NUM - 1)
+
+#define C_CAN_MSG_OBJ_RX_SPLIT 9
+#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
+
+#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
+#define RECEIVE_OBJECT_BITS 0x0000ffff
+
+/* status interrupt */
+#define STATUS_INTERRUPT 0x8000
+
+/* global interrupt masks */
+#define ENABLE_ALL_INTERRUPTS 1
+#define DISABLE_ALL_INTERRUPTS 0
+
+/* minimum timeout for checking BUSY status */
+#define MIN_TIMEOUT_VALUE 6
+
+/* napi related */
+#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
+
+/* c_can lec values */
+enum c_can_lec_type {
+ LEC_NO_ERROR = 0,
+ LEC_STUFF_ERROR,
+ LEC_FORM_ERROR,
+ LEC_ACK_ERROR,
+ LEC_BIT1_ERROR,
+ LEC_BIT0_ERROR,
+ LEC_CRC_ERROR,
+ LEC_UNUSED,
+};
+
+/*
+ * c_can error types:
+ * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
+ */
+enum c_can_bus_error_types {
+ C_CAN_NO_ERROR = 0,
+ C_CAN_BUS_OFF,
+ C_CAN_ERROR_WARNING,
+ C_CAN_ERROR_PASSIVE,
+};
+
+static struct can_bittiming_const c_can_bittiming_const = {
+ .name = KBUILD_MODNAME,
+ .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
+ .tseg1_max = 16,
+ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
+ .tseg2_max = 8,
+ .sjw_max = 4,
+ .brp_min = 1,
+ .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
+ .brp_inc = 1,
+};
+
+static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
+{
+ return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
+ C_CAN_MSG_OBJ_TX_FIRST;
+}
+
+static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
+{
+ return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
+ C_CAN_MSG_OBJ_TX_FIRST;
+}
+
+static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
+{
+ u32 val = priv->read_reg(priv, reg);
+ val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
+ return val;
+}
+
+static void c_can_enable_all_interrupts(struct c_can_priv *priv,
+ int enable)
+{
+ unsigned int cntrl_save = priv->read_reg(priv,
+ &priv->regs->control);
+
+ if (enable)
+ cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
+ else
+ cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
+
+ priv->write_reg(priv, &priv->regs->control, cntrl_save);
+}
+
+static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
+{
+ int count = MIN_TIMEOUT_VALUE;
+
+ while (count && priv->read_reg(priv,
+ &priv->regs->ifregs[iface].com_req) &
+ IF_COMR_BUSY) {
+ count--;
+ udelay(1);
+ }
+
+ if (!count)
+ return 1;
+
+ return 0;
+}
+
+static inline void c_can_object_get(struct net_device *dev,
+ int iface, int objno, int mask)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /*
+ * As per specs, after writting the message object number in the
+ * IF command request register the transfer b/w interface
+ * register and message RAM must be complete in 6 CAN-CLK
+ * period.
+ */
+ priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
+ IFX_WRITE_LOW_16BIT(mask));
+ priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
+ IFX_WRITE_LOW_16BIT(objno));
+
+ if (c_can_msg_obj_is_busy(priv, iface))
+ netdev_err(dev, "timed out in object get\n");
+}
+
+static inline void c_can_object_put(struct net_device *dev,
+ int iface, int objno, int mask)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /*
+ * As per specs, after writting the message object number in the
+ * IF command request register the transfer b/w interface
+ * register and message RAM must be complete in 6 CAN-CLK
+ * period.
+ */
+ priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
+ (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
+ priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
+ IFX_WRITE_LOW_16BIT(objno));
+
+ if (c_can_msg_obj_is_busy(priv, iface))
+ netdev_err(dev, "timed out in object put\n");
+}
+
+static void c_can_write_msg_object(struct net_device *dev,
+ int iface, struct can_frame *frame, int objno)
+{
+ int i;
+ u16 flags = 0;
+ unsigned int id;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ if (!(frame->can_id & CAN_RTR_FLAG))
+ flags |= IF_ARB_TRANSMIT;
+
+ if (frame->can_id & CAN_EFF_FLAG) {
+ id = frame->can_id & CAN_EFF_MASK;
+ flags |= IF_ARB_MSGXTD;
+ } else
+ id = ((frame->can_id & CAN_SFF_MASK) << 18);
+
+ flags |= IF_ARB_MSGVAL;
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
+ IFX_WRITE_LOW_16BIT(id));
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags |
+ IFX_WRITE_HIGH_16BIT(id));
+
+ for (i = 0; i < frame->can_dlc; i += 2) {
+ priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2],
+ frame->data[i] | (frame->data[i + 1] << 8));
+ }
+
+ /* enable interrupt for this message object */
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
+ IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
+ frame->can_dlc);
+ c_can_object_put(dev, iface, objno, IF_COMM_ALL);
+}
+
+static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
+ int iface, int ctrl_mask,
+ int obj)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
+ ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
+ c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
+
+}
+
+static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
+ int iface,
+ int ctrl_mask)
+{
+ int i;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
+ ctrl_mask & ~(IF_MCONT_MSGLST |
+ IF_MCONT_INTPND | IF_MCONT_NEWDAT));
+ c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
+ }
+}
+
+static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
+ int iface, int ctrl_mask,
+ int obj)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
+ ctrl_mask & ~(IF_MCONT_MSGLST |
+ IF_MCONT_INTPND | IF_MCONT_NEWDAT));
+ c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
+}
+
+static void c_can_handle_lost_msg_obj(struct net_device *dev,
+ int iface, int objno)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+ struct sk_buff *skb;
+ struct can_frame *frame;
+
+ netdev_err(dev, "msg lost in buffer %d\n", objno);
+
+ c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
+ IF_MCONT_CLR_MSGLST);
+
+ c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
+
+ /* create an error msg */
+ skb = alloc_can_err_skb(dev, &frame);
+ if (unlikely(!skb))
+ return;
+
+ frame->can_id |= CAN_ERR_CRTL;
+ frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+ stats->rx_errors++;
+ stats->rx_over_errors++;
+
+ netif_receive_skb(skb);
+}
+
+static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
+{
+ u16 flags, data;
+ int i;
+ unsigned int val;
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+ struct sk_buff *skb;
+ struct can_frame *frame;
+
+ skb = alloc_can_skb(dev, &frame);
+ if (!skb) {
+ stats->rx_dropped++;
+ return -ENOMEM;
+ }
+
+ frame->can_dlc = get_can_dlc(ctrl & 0x0F);
+
+ flags = priv->read_reg(priv, &priv->regs->ifregs[iface].arb2);
+ val = priv->read_reg(priv, &priv->regs->ifregs[iface].arb1) |
+ (flags << 16);
+
+ if (flags & IF_ARB_MSGXTD)
+ frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
+ else
+ frame->can_id = (val >> 18) & CAN_SFF_MASK;
+
+ if (flags & IF_ARB_TRANSMIT)
+ frame->can_id |= CAN_RTR_FLAG;
+ else {
+ for (i = 0; i < frame->can_dlc; i += 2) {
+ data = priv->read_reg(priv,
+ &priv->regs->ifregs[iface].data[i / 2]);
+ frame->data[i] = data;
+ frame->data[i + 1] = data >> 8;
+ }
+ }
+
+ netif_receive_skb(skb);
+
+ stats->rx_packets++;
+ stats->rx_bytes += frame->can_dlc;
+
+ return 0;
+}
+
+static void c_can_setup_receive_object(struct net_device *dev, int iface,
+ int objno, unsigned int mask,
+ unsigned int id, unsigned int mcont)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].mask1,
+ IFX_WRITE_LOW_16BIT(mask));
+ priv->write_reg(priv, &priv->regs->ifregs[iface].mask2,
+ IFX_WRITE_HIGH_16BIT(mask));
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
+ IFX_WRITE_LOW_16BIT(id));
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb2,
+ (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont);
+ c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
+
+ netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
+ c_can_read_reg32(priv, &priv->regs->msgval1));
+}
+
+static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 0);
+ priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 0);
+ priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 0);
+
+ c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
+
+ netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
+ c_can_read_reg32(priv, &priv->regs->msgval1));
+}
+
+static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
+{
+ int val = c_can_read_reg32(priv, &priv->regs->txrqst1);
+
+ /*
+ * as transmission request register's bit n-1 corresponds to
+ * message object n, we need to handle the same properly.
+ */
+ if (val & (1 << (objno - 1)))
+ return 1;
+
+ return 0;
+}
+
+static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
+ struct net_device *dev)
+{
+ u32 msg_obj_no;
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct can_frame *frame = (struct can_frame *)skb->data;
+
+ if (can_dropped_invalid_skb(dev, skb))
+ return NETDEV_TX_OK;
+
+ msg_obj_no = get_tx_next_msg_obj(priv);
+
+ /* prepare message object for transmission */
+ c_can_write_msg_object(dev, 0, frame, msg_obj_no);
+ can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
+
+ /*
+ * we have to stop the queue in case of a wrap around or
+ * if the next TX message object is still in use
+ */
+ priv->tx_next++;
+ if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
+ (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
+ netif_stop_queue(dev);
+
+ return NETDEV_TX_OK;
+}
+
+static int c_can_set_bittiming(struct net_device *dev)
+{
+ unsigned int reg_btr, reg_brpe, ctrl_save;
+ u8 brp, brpe, sjw, tseg1, tseg2;
+ u32 ten_bit_brp;
+ struct c_can_priv *priv = netdev_priv(dev);
+ const struct can_bittiming *bt = &priv->can.bittiming;
+
+ /* c_can provides a 6-bit brp and 4-bit brpe fields */
+ ten_bit_brp = bt->brp - 1;
+ brp = ten_bit_brp & BTR_BRP_MASK;
+ brpe = ten_bit_brp >> 6;
+
+ sjw = bt->sjw - 1;
+ tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+ tseg2 = bt->phase_seg2 - 1;
+ reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
+ (tseg2 << BTR_TSEG2_SHIFT);
+ reg_brpe = brpe & BRP_EXT_BRPE_MASK;
+
+ netdev_info(dev,
+ "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
+
+ ctrl_save = priv->read_reg(priv, &priv->regs->control);
+ priv->write_reg(priv, &priv->regs->control,
+ ctrl_save | CONTROL_CCE | CONTROL_INIT);
+ priv->write_reg(priv, &priv->regs->btr, reg_btr);
+ priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe);
+ priv->write_reg(priv, &priv->regs->control, ctrl_save);
+
+ return 0;
+}
+
+/*
+ * Configure C_CAN message objects for Tx and Rx purposes:
+ * C_CAN provides a total of 32 message objects that can be configured
+ * either for Tx or Rx purposes. Here the first 16 message objects are used as
+ * a reception FIFO. The end of reception FIFO is signified by the EoB bit
+ * being SET. The remaining 16 message objects are kept aside for Tx purposes.
+ * See user guide document for further details on configuring message
+ * objects.
+ */
+static void c_can_configure_msg_objects(struct net_device *dev)
+{
+ int i;
+
+ /* first invalidate all message objects */
+ for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
+ c_can_inval_msg_object(dev, 0, i);
+
+ /* setup receive message objects */
+ for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
+ c_can_setup_receive_object(dev, 0, i, 0, 0,
+ (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
+
+ c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
+ IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
+}
+
+/*
+ * Configure C_CAN chip:
+ * - enable/disable auto-retransmission
+ * - set operating mode
+ * - configure message objects
+ */
+static void c_can_chip_config(struct net_device *dev)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
+ /* disable automatic retransmission */
+ priv->write_reg(priv, &priv->regs->control,
+ CONTROL_DISABLE_AR);
+ else
+ /* enable automatic retransmission */
+ priv->write_reg(priv, &priv->regs->control,
+ CONTROL_ENABLE_AR);
+
+ if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
+ CAN_CTRLMODE_LOOPBACK)) {
+ /* loopback + silent mode : useful for hot self-test */
+ priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
+ CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
+ priv->write_reg(priv, &priv->regs->test,
+ TEST_LBACK | TEST_SILENT);
+ } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
+ /* loopback mode : useful for self-test function */
+ priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
+ CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
+ priv->write_reg(priv, &priv->regs->test, TEST_LBACK);
+ } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
+ /* silent mode : bus-monitoring mode */
+ priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
+ CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
+ priv->write_reg(priv, &priv->regs->test, TEST_SILENT);
+ } else
+ /* normal mode*/
+ priv->write_reg(priv, &priv->regs->control,
+ CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
+
+ /* configure message objects */
+ c_can_configure_msg_objects(dev);
+
+ /* set a `lec` value so that we can check for updates later */
+ priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
+
+ /* set bittiming params */
+ c_can_set_bittiming(dev);
+}
+
+static void c_can_start(struct net_device *dev)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /* enable status change, error and module interrupts */
+ c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
+
+ /* basic c_can configuration */
+ c_can_chip_config(dev);
+
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+ /* reset tx helper pointers */
+ priv->tx_next = priv->tx_echo = 0;
+}
+
+static void c_can_stop(struct net_device *dev)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /* disable all interrupts */
+ c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+
+ /* set the state as STOPPED */
+ priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
+{
+ switch (mode) {
+ case CAN_MODE_START:
+ c_can_start(dev);
+ netif_wake_queue(dev);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int c_can_get_berr_counter(const struct net_device *dev,
+ struct can_berr_counter *bec)
+{
+ unsigned int reg_err_counter;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
+ bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
+ ERR_CNT_REC_SHIFT;
+ bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
+
+ return 0;
+}
+
+/*
+ * theory of operation:
+ *
+ * priv->tx_echo holds the number of the oldest can_frame put for
+ * transmission into the hardware, but not yet ACKed by the CAN tx
+ * complete IRQ.
+ *
+ * We iterate from priv->tx_echo to priv->tx_next and check if the
+ * packet has been transmitted, echo it back to the CAN framework.
+ * If we discover a not yet transmitted package, stop looking for more.
+ */
+static void c_can_do_tx(struct net_device *dev)
+{
+ u32 val;
+ u32 msg_obj_no;
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+
+ for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
+ msg_obj_no = get_tx_echo_msg_obj(priv);
+ c_can_inval_msg_object(dev, 0, msg_obj_no);
+ val = c_can_read_reg32(priv, &priv->regs->txrqst1);
+ if (!(val & (1 << msg_obj_no))) {
+ can_get_echo_skb(dev,
+ msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
+ stats->tx_bytes += priv->read_reg(priv,
+ &priv->regs->ifregs[0].msg_cntrl)
+ & IF_MCONT_DLC_MASK;
+ stats->tx_packets++;
+ }
+ }
+
+ /* restart queue if wrap-up or if queue stalled on last pkt */
+ if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
+ ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
+ netif_wake_queue(dev);
+}
+
+/*
+ * theory of operation:
+ *
+ * c_can core saves a received CAN message into the first free message
+ * object it finds free (starting with the lowest). Bits NEWDAT and
+ * INTPND are set for this message object indicating that a new message
+ * has arrived. To work-around this issue, we keep two groups of message
+ * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
+ *
+ * To ensure in-order frame reception we use the following
+ * approach while re-activating a message object to receive further
+ * frames:
+ * - if the current message object number is lower than
+ * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
+ * the INTPND bit.
+ * - if the current message object number is equal to
+ * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
+ * receive message objects.
+ * - if the current message object number is greater than
+ * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
+ * only this message object.
+ */
+static int c_can_do_rx_poll(struct net_device *dev, int quota)
+{
+ u32 num_rx_pkts = 0;
+ unsigned int msg_obj, msg_ctrl_save;
+ struct c_can_priv *priv = netdev_priv(dev);
+ u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1);
+
+ for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
+ msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
+ val = c_can_read_reg32(priv, &priv->regs->intpnd1),
+ msg_obj++) {
+ /*
+ * as interrupt pending register's bit n-1 corresponds to
+ * message object n, we need to handle the same properly.
+ */
+ if (val & (1 << (msg_obj - 1))) {
+ c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
+ ~IF_COMM_TXRQST);
+ msg_ctrl_save = priv->read_reg(priv,
+ &priv->regs->ifregs[0].msg_cntrl);
+
+ if (msg_ctrl_save & IF_MCONT_EOB)
+ return num_rx_pkts;
+
+ if (msg_ctrl_save & IF_MCONT_MSGLST) {
+ c_can_handle_lost_msg_obj(dev, 0, msg_obj);
+ num_rx_pkts++;
+ quota--;
+ continue;
+ }
+
+ if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
+ continue;
+
+ /* read the data from the message object */
+ c_can_read_msg_object(dev, 0, msg_ctrl_save);
+
+ if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
+ c_can_mark_rx_msg_obj(dev, 0,
+ msg_ctrl_save, msg_obj);
+ else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
+ /* activate this msg obj */
+ c_can_activate_rx_msg_obj(dev, 0,
+ msg_ctrl_save, msg_obj);
+ else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
+ /* activate all lower message objects */
+ c_can_activate_all_lower_rx_msg_obj(dev,
+ 0, msg_ctrl_save);
+
+ num_rx_pkts++;
+ quota--;
+ }
+ }
+
+ return num_rx_pkts;
+}
+
+static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
+{
+ return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
+ (priv->current_status & LEC_UNUSED);
+}
+
+static int c_can_handle_state_change(struct net_device *dev,
+ enum c_can_bus_error_types error_type)
+{
+ unsigned int reg_err_counter;
+ unsigned int rx_err_passive;
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+ struct can_berr_counter bec;
+
+ /* propogate the error condition to the CAN stack */
+ skb = alloc_can_err_skb(dev, &cf);
+ if (unlikely(!skb))
+ return 0;
+
+ c_can_get_berr_counter(dev, &bec);
+ reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
+ rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
+ ERR_CNT_RP_SHIFT;
+
+ switch (error_type) {
+ case C_CAN_ERROR_WARNING:
+ /* error warning state */
+ priv->can.can_stats.error_warning++;
+ priv->can.state = CAN_STATE_ERROR_WARNING;
+ cf->can_id |= CAN_ERR_CRTL;
+ cf->data[1] = (bec.txerr > bec.rxerr) ?
+ CAN_ERR_CRTL_TX_WARNING :
+ CAN_ERR_CRTL_RX_WARNING;
+ cf->data[6] = bec.txerr;
+ cf->data[7] = bec.rxerr;
+
+ break;
+ case C_CAN_ERROR_PASSIVE:
+ /* error passive state */
+ priv->can.can_stats.error_passive++;
+ priv->can.state = CAN_STATE_ERROR_PASSIVE;
+ cf->can_id |= CAN_ERR_CRTL;
+ if (rx_err_passive)
+ cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+ if (bec.txerr > 127)
+ cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+
+ cf->data[6] = bec.txerr;
+ cf->data[7] = bec.rxerr;
+ break;
+ case C_CAN_BUS_OFF:
+ /* bus-off state */
+ priv->can.state = CAN_STATE_BUS_OFF;
+ cf->can_id |= CAN_ERR_BUSOFF;
+ /*
+ * disable all interrupts in bus-off mode to ensure that
+ * the CPU is not hogged down
+ */
+ c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ can_bus_off(dev);
+ break;
+ default:
+ break;
+ }
+
+ netif_receive_skb(skb);
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+
+ return 1;
+}
+
+static int c_can_handle_bus_err(struct net_device *dev,
+ enum c_can_lec_type lec_type)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct net_device_stats *stats = &dev->stats;
+ struct can_frame *cf;
+ struct sk_buff *skb;
+
+ /*
+ * early exit if no lec update or no error.
+ * no lec update means that no CAN bus event has been detected
+ * since CPU wrote 0x7 value to status reg.
+ */
+ if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
+ return 0;
+
+ /* propogate the error condition to the CAN stack */
+ skb = alloc_can_err_skb(dev, &cf);
+ if (unlikely(!skb))
+ return 0;
+
+ /*
+ * check for 'last error code' which tells us the
+ * type of the last error to occur on the CAN bus
+ */
+
+ /* common for all type of bus errors */
+ priv->can.can_stats.bus_error++;
+ stats->rx_errors++;
+ cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
+ cf->data[2] |= CAN_ERR_PROT_UNSPEC;
+
+ switch (lec_type) {
+ case LEC_STUFF_ERROR:
+ netdev_dbg(dev, "stuff error\n");
+ cf->data[2] |= CAN_ERR_PROT_STUFF;
+ break;
+ case LEC_FORM_ERROR:
+ netdev_dbg(dev, "form error\n");
+ cf->data[2] |= CAN_ERR_PROT_FORM;
+ break;
+ case LEC_ACK_ERROR:
+ netdev_dbg(dev, "ack error\n");
+ cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
+ CAN_ERR_PROT_LOC_ACK_DEL);
+ break;
+ case LEC_BIT1_ERROR:
+ netdev_dbg(dev, "bit1 error\n");
+ cf->data[2] |= CAN_ERR_PROT_BIT1;
+ break;
+ case LEC_BIT0_ERROR:
+ netdev_dbg(dev, "bit0 error\n");
+ cf->data[2] |= CAN_ERR_PROT_BIT0;
+ break;
+ case LEC_CRC_ERROR:
+ netdev_dbg(dev, "CRC error\n");
+ cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
+ CAN_ERR_PROT_LOC_CRC_DEL);
+ break;
+ default:
+ break;
+ }
+
+ /* set a `lec` value so that we can check for updates later */
+ priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
+
+ netif_receive_skb(skb);
+ stats->rx_packets++;
+ stats->rx_bytes += cf->can_dlc;
+
+ return 1;
+}
+
+static int c_can_poll(struct napi_struct *napi, int quota)
+{
+ u16 irqstatus;
+ int lec_type = 0;
+ int work_done = 0;
+ struct net_device *dev = napi->dev;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
+ if (!irqstatus)
+ goto end;
+
+ /* status events have the highest priority */
+ if (irqstatus == STATUS_INTERRUPT) {
+ priv->current_status = priv->read_reg(priv,
+ &priv->regs->status);
+
+ /* handle Tx/Rx events */
+ if (priv->current_status & STATUS_TXOK)
+ priv->write_reg(priv, &priv->regs->status,
+ priv->current_status & ~STATUS_TXOK);
+
+ if (priv->current_status & STATUS_RXOK)
+ priv->write_reg(priv, &priv->regs->status,
+ priv->current_status & ~STATUS_RXOK);
+
+ /* handle state changes */
+ if ((priv->current_status & STATUS_EWARN) &&
+ (!(priv->last_status & STATUS_EWARN))) {
+ netdev_dbg(dev, "entered error warning state\n");
+ work_done += c_can_handle_state_change(dev,
+ C_CAN_ERROR_WARNING);
+ }
+ if ((priv->current_status & STATUS_EPASS) &&
+ (!(priv->last_status & STATUS_EPASS))) {
+ netdev_dbg(dev, "entered error passive state\n");
+ work_done += c_can_handle_state_change(dev,
+ C_CAN_ERROR_PASSIVE);
+ }
+ if ((priv->current_status & STATUS_BOFF) &&
+ (!(priv->last_status & STATUS_BOFF))) {
+ netdev_dbg(dev, "entered bus off state\n");
+ work_done += c_can_handle_state_change(dev,
+ C_CAN_BUS_OFF);
+ }
+
+ /* handle bus recovery events */
+ if ((!(priv->current_status & STATUS_BOFF)) &&
+ (priv->last_status & STATUS_BOFF)) {
+ netdev_dbg(dev, "left bus off state\n");
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ }
+ if ((!(priv->current_status & STATUS_EPASS)) &&
+ (priv->last_status & STATUS_EPASS)) {
+ netdev_dbg(dev, "left error passive state\n");
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ }
+
+ priv->last_status = priv->current_status;
+
+ /* handle lec errors on the bus */
+ lec_type = c_can_has_and_handle_berr(priv);
+ if (lec_type)
+ work_done += c_can_handle_bus_err(dev, lec_type);
+ } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
+ (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
+ /* handle events corresponding to receive message objects */
+ work_done += c_can_do_rx_poll(dev, (quota - work_done));
+ } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
+ (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
+ /* handle events corresponding to transmit message objects */
+ c_can_do_tx(dev);
+ }
+
+end:
+ if (work_done < quota) {
+ napi_complete(napi);
+ /* enable all IRQs */
+ c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
+ }
+
+ return work_done;
+}
+
+static irqreturn_t c_can_isr(int irq, void *dev_id)
+{
+ u16 irqstatus;
+ struct net_device *dev = (struct net_device *)dev_id;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
+ if (!irqstatus)
+ return IRQ_NONE;
+
+ /* disable all interrupts and schedule the NAPI */
+ c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+ napi_schedule(&priv->napi);
+
+ return IRQ_HANDLED;
+}
+
+static int c_can_open(struct net_device *dev)
+{
+ int err;
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /* open the can device */
+ err = open_candev(dev);
+ if (err) {
+ netdev_err(dev, "failed to open can device\n");
+ return err;
+ }
+
+ /* register interrupt handler */
+ err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
+ dev);
+ if (err < 0) {
+ netdev_err(dev, "failed to request interrupt\n");
+ goto exit_irq_fail;
+ }
+
+ /* start the c_can controller */
+ c_can_start(dev);
+
+ napi_enable(&priv->napi);
+ netif_start_queue(dev);
+
+ return 0;
+
+exit_irq_fail:
+ close_candev(dev);
+ return err;
+}
+
+static int c_can_close(struct net_device *dev)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ netif_stop_queue(dev);
+ napi_disable(&priv->napi);
+ c_can_stop(dev);
+ free_irq(dev->irq, dev);
+ close_candev(dev);
+
+ return 0;
+}
+
+struct net_device *alloc_c_can_dev(void)
+{
+ struct net_device *dev;
+ struct c_can_priv *priv;
+
+ dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
+ if (!dev)
+ return NULL;
+
+ priv = netdev_priv(dev);
+ netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
+
+ priv->dev = dev;
+ priv->can.bittiming_const = &c_can_bittiming_const;
+ priv->can.do_set_mode = c_can_set_mode;
+ priv->can.do_get_berr_counter = c_can_get_berr_counter;
+ priv->can.ctrlmode_supported = CAN_CTRLMODE_ONE_SHOT |
+ CAN_CTRLMODE_LOOPBACK |
+ CAN_CTRLMODE_LISTENONLY |
+ CAN_CTRLMODE_BERR_REPORTING;
+
+ return dev;
+}
+EXPORT_SYMBOL_GPL(alloc_c_can_dev);
+
+void free_c_can_dev(struct net_device *dev)
+{
+ free_candev(dev);
+}
+EXPORT_SYMBOL_GPL(free_c_can_dev);
+
+static const struct net_device_ops c_can_netdev_ops = {
+ .ndo_open = c_can_open,
+ .ndo_stop = c_can_close,
+ .ndo_start_xmit = c_can_start_xmit,
+};
+
+int register_c_can_dev(struct net_device *dev)
+{
+ dev->flags |= IFF_ECHO; /* we support local echo */
+ dev->netdev_ops = &c_can_netdev_ops;
+
+ return register_candev(dev);
+}
+EXPORT_SYMBOL_GPL(register_c_can_dev);
+
+void unregister_c_can_dev(struct net_device *dev)
+{
+ struct c_can_priv *priv = netdev_priv(dev);
+
+ /* disable all interrupts */
+ c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
+
+ unregister_candev(dev);
+}
+EXPORT_SYMBOL_GPL(unregister_c_can_dev);
+
+MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h
new file mode 100644
index 0000000..9b7fbef
--- /dev/null
+++ b/drivers/net/can/c_can/c_can.h
@@ -0,0 +1,86 @@
+/*
+ * CAN bus driver for Bosch C_CAN controller
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
+ *
+ * Borrowed heavily from the C_CAN driver originally written by:
+ * Copyright (C) 2007
+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
+ *
+ * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ * Bosch C_CAN user manual can be obtained from:
+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
+ * users_manual_c_can.pdf
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef C_CAN_H
+#define C_CAN_H
+
+/* c_can IF registers */
+struct c_can_if_regs {
+ u16 com_req;
+ u16 com_mask;
+ u16 mask1;
+ u16 mask2;
+ u16 arb1;
+ u16 arb2;
+ u16 msg_cntrl;
+ u16 data[4];
+ u16 _reserved[13];
+};
+
+/* c_can hardware registers */
+struct c_can_regs {
+ u16 control;
+ u16 status;
+ u16 err_cnt;
+ u16 btr;
+ u16 interrupt;
+ u16 test;
+ u16 brp_ext;
+ u16 _reserved1;
+ struct c_can_if_regs ifregs[2]; /* [0] = IF1 and [1] = IF2 */
+ u16 _reserved2[8];
+ u16 txrqst1;
+ u16 txrqst2;
+ u16 _reserved3[6];
+ u16 newdat1;
+ u16 newdat2;
+ u16 _reserved4[6];
+ u16 intpnd1;
+ u16 intpnd2;
+ u16 _reserved5[6];
+ u16 msgval1;
+ u16 msgval2;
+ u16 _reserved6[6];
+};
+
+/* c_can private data structure */
+struct c_can_priv {
+ struct can_priv can; /* must be the first member */
+ struct napi_struct napi;
+ struct net_device *dev;
+ int tx_object;
+ int current_status;
+ int last_status;
+ u16 (*read_reg) (struct c_can_priv *priv, void *reg);
+ void (*write_reg) (struct c_can_priv *priv, void *reg, u16 val);
+ struct c_can_regs __iomem *regs;
+ unsigned long irq_flags; /* for request_irq() */
+ unsigned int tx_next;
+ unsigned int tx_echo;
+ void *priv; /* for board-specific data */
+};
+
+struct net_device *alloc_c_can_dev(void);
+void free_c_can_dev(struct net_device *dev);
+int register_c_can_dev(struct net_device *dev);
+void unregister_c_can_dev(struct net_device *dev);
+
+#endif /* C_CAN_H */
diff --git a/drivers/net/can/c_can/c_can_platform.c b/drivers/net/can/c_can/c_can_platform.c
new file mode 100644
index 0000000..0fc314e
--- /dev/null
+++ b/drivers/net/can/c_can/c_can_platform.c
@@ -0,0 +1,207 @@
+/*
+ * Platform CAN bus driver for Bosch C_CAN controller
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>
+ *
+ * Borrowed heavily from the C_CAN driver originally written by:
+ * Copyright (C) 2007
+ * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
+ * - Simon Kallweit, intefo AG <simon.kallweit-+G9qxTFKJT/tRgLqZ5aouw@public.gmane.org>
+ *
+ * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
+ * Bosch C_CAN user manual can be obtained from:
+ * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
+ * users_manual_c_can.pdf
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+
+#include <linux/can/dev.h>
+
+#include "c_can.h"
+
+/*
+ * 16-bit c_can registers can be arranged differently in the memory
+ * architecture of different implementations. For example: 16-bit
+ * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
+ * Handle the same by providing a common read/write interface.
+ */
+static u16 c_can_plat_read_reg_aligned_to_16bit(struct c_can_priv *priv,
+ void *reg)
+{
+ return readw(reg);
+}
+
+static void c_can_plat_write_reg_aligned_to_16bit(struct c_can_priv *priv,
+ void *reg, u16 val)
+{
+ writew(val, reg);
+}
+
+static u16 c_can_plat_read_reg_aligned_to_32bit(struct c_can_priv *priv,
+ void *reg)
+{
+ return readw(reg + (long)reg - (long)priv->regs);
+}
+
+static void c_can_plat_write_reg_aligned_to_32bit(struct c_can_priv *priv,
+ void *reg, u16 val)
+{
+ writew(val, reg + (long)reg - (long)priv->regs);
+}
+
+static int __devinit c_can_plat_probe(struct platform_device *pdev)
+{
+ int ret;
+ void __iomem *addr;
+ struct net_device *dev;
+ struct c_can_priv *priv;
+ struct resource *mem, *irq;
+ struct clk *clk;
+
+ /* get the appropriate clk */
+ clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "no clock defined\n");
+ ret = -ENODEV;
+ goto exit;
+ }
+
+ /* get the platform data */
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!mem || (irq <= 0)) {
+ ret = -ENODEV;
+ goto exit_free_clk;
+ }
+
+ if (!request_mem_region(mem->start, resource_size(mem),
+ KBUILD_MODNAME)) {
+ dev_err(&pdev->dev, "resource unavailable\n");
+ ret = -ENODEV;
+ goto exit_free_clk;
+ }
+
+ addr = ioremap(mem->start, resource_size(mem));
+ if (!addr) {
+ dev_err(&pdev->dev, "failed to map can port\n");
+ ret = -ENOMEM;
+ goto exit_release_mem;
+ }
+
+ /* allocate the c_can device */
+ dev = alloc_c_can_dev();
+ if (!dev) {
+ ret = -ENOMEM;
+ goto exit_iounmap;
+ }
+
+ priv = netdev_priv(dev);
+
+ dev->irq = irq->start;
+ priv->regs = addr;
+ priv->can.clock.freq = clk_get_rate(clk);
+ priv->priv = clk;
+
+ switch (mem->flags & IORESOURCE_MEM_TYPE_MASK) {
+ case IORESOURCE_MEM_32BIT:
+ priv->read_reg = c_can_plat_read_reg_aligned_to_32bit;
+ priv->write_reg = c_can_plat_write_reg_aligned_to_32bit;
+ break;
+ case IORESOURCE_MEM_16BIT:
+ default:
+ priv->read_reg = c_can_plat_read_reg_aligned_to_16bit;
+ priv->write_reg = c_can_plat_write_reg_aligned_to_16bit;
+ break;
+ }
+
+ platform_set_drvdata(pdev, dev);
+ SET_NETDEV_DEV(dev, &pdev->dev);
+
+ ret = register_c_can_dev(dev);
+ if (ret) {
+ dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
+ KBUILD_MODNAME, ret);
+ goto exit_free_device;
+ }
+
+ dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
+ KBUILD_MODNAME, priv->regs, dev->irq);
+ return 0;
+
+exit_free_device:
+ platform_set_drvdata(pdev, NULL);
+ free_c_can_dev(dev);
+exit_iounmap:
+ iounmap(addr);
+exit_release_mem:
+ release_mem_region(mem->start, resource_size(mem));
+exit_free_clk:
+ clk_put(clk);
+exit:
+ dev_err(&pdev->dev, "probe failed\n");
+
+ return ret;
+}
+
+static int __devexit c_can_plat_remove(struct platform_device *pdev)
+{
+ struct net_device *dev = platform_get_drvdata(pdev);
+ struct c_can_priv *priv = netdev_priv(dev);
+ struct resource *mem;
+
+ unregister_c_can_dev(dev);
+ platform_set_drvdata(pdev, NULL);
+
+ free_c_can_dev(dev);
+ iounmap(priv->regs);
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(mem->start, resource_size(mem));
+
+ clk_put(priv->priv);
+
+ return 0;
+}
+
+static struct platform_driver c_can_plat_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .owner = THIS_MODULE,
+ },
+ .probe = c_can_plat_probe,
+ .remove = __devexit_p(c_can_plat_remove),
+};
+
+static int __init c_can_plat_init(void)
+{
+ return platform_driver_register(&c_can_plat_driver);
+}
+module_init(c_can_plat_init);
+
+static void __exit c_can_plat_exit(void)
+{
+ platform_driver_unregister(&c_can_plat_driver);
+}
+module_exit(c_can_plat_exit);
+
+MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma-qxv4g6HH51o@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Platform CAN bus driver for Bosch C_CAN controller");
--
1.6.0.2
^ permalink raw reply related
* [PATCH] ip_gre: Add IPPROTO_GRE to flowi in ipgre_tunnel_xmit
From: Steffen Klassert @ 2011-02-11 9:30 UTC (permalink / raw)
To: David Miller; +Cc: Changli Gao, netdev
Commit 5811662b15db018c740c57d037523683fd3e6123 accidentally
removed the setting of IPPROTO_GRE from the struct flowi
in ipgre_tunnel_xmit. This patch restores it.
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
---
net/ipv4/ip_gre.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c
index eb68a0e..6613edf 100644
--- a/net/ipv4/ip_gre.c
+++ b/net/ipv4/ip_gre.c
@@ -775,6 +775,7 @@ static netdev_tx_t ipgre_tunnel_xmit(struct sk_buff *skb, struct net_device *dev
.fl4_dst = dst,
.fl4_src = tiph->saddr,
.fl4_tos = RT_TOS(tos),
+ .proto = IPPROTO_GRE,
.fl_gre_key = tunnel->parms.o_key
};
if (ip_route_output_key(dev_net(dev), &rt, &fl)) {
--
1.7.0.4
^ permalink raw reply related
* [PATCH] stmmac: enable wol via magic frame by default.
From: Peppe CAVALLARO @ 2011-02-11 8:51 UTC (permalink / raw)
To: netdev@vger.kernel.org; +Cc: Peppe CAVALLARO
This patch enables it by default when the driver starts.
This has been required by many people and seems to actually be
useful on STB.
At any rate, the WoL modes can be selected and turned-on/off
by using the ethtool at run-time by users.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
drivers/net/stmmac/stmmac_main.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 34a0af3..0e5f031 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1560,8 +1560,10 @@ static int stmmac_mac_device_setup(struct net_device *dev)
priv->hw = device;
- if (device_can_wakeup(priv->device))
+ if (device_can_wakeup(priv->device)) {
priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
+ enable_irq_wake(dev->irq);
+ }
return 0;
}
--
1.7.4
^ permalink raw reply related
* Re: [PATCH V10 15/15] ptp: Added a clock driver for the National Semiconductor PHYTER.
From: Richard Cochran @ 2011-02-11 8:19 UTC (permalink / raw)
To: john stultz
Cc: linux-kernel, linux-api, netdev, Alan Cox, Arnd Bergmann,
Christoph Lameter, David Miller, Krzysztof Halasa, Peter Zijlstra,
Rodolfo Giometti, Thomas Gleixner, Benjamin Herrenschmidt,
H. Peter Anvin, Ingo Molnar, Mike Frysinger, Paul Mackerras,
Russell King
In-Reply-To: <1296612712.3336.214.camel@work-vm>
On Tue, Feb 01, 2011 at 06:11:52PM -0800, john stultz wrote:
> On Thu, 2011-01-27 at 12:00 +0100, Richard Cochran wrote:
> > This patch adds support for the PTP clock found on the DP83640.
> > The basic clock operations and one external time stamp have
> > been implemented.
> >
> > Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
>
> Acked-by: John Stultz <johnstul@us.ibm.com>
I am going to post the PHC patches one more time, and I want to expand
this driver to support mutiple PHYs. So, I would ask you to please
take a second look at this driver then.
Thanks,
Richard
^ permalink raw reply
* Re: [PATCH V10 12/15] ptp: Added a brand new class driver for ptp clocks.
From: Richard Cochran @ 2011-02-11 8:15 UTC (permalink / raw)
To: John Stultz
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-api-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
Alan Cox, Arnd Bergmann, Christoph Lameter, David Miller,
Krzysztof Halasa, Peter Zijlstra, Rodolfo Giometti,
Thomas Gleixner, Benjamin Herrenschmidt, H. Peter Anvin,
Ingo Molnar, Mike Frysinger, Paul Mackerras, Russell King
In-Reply-To: <1296612031.3336.201.camel@work-vm>
On Tue, Feb 01, 2011 at 06:00:31PM -0800, John Stultz wrote:
> On Thu, 2011-01-27 at 11:59 +0100, Richard Cochran wrote:
> You may want to tweak the kconfig a bit here. If I don't have pps
> enabled, if I go into the "PTP clock support" page, I get an empty
> screen.
>
> Similarly, its not very discoverable to figure out what you need to
> enable to get the driver options to show up, as they depend the drivers
> enabled in the networking device section.
Okay, I'll see what I can come up with.
> > +#define PTP_MAX_ALARMS 4
> > +#define PTP_MAX_CLOCKS (MAX_CLOCKS/2)
>
> Why MAX_CLOCKS/2 ? Should this scale as MAX_CLOCKS is increased?
> Or do you really just mean 8?
This is just left over from when I thought the PHCs would use the
static clock IDs. I'll fix that.
> > +static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
> > + struct ptp_clock_event *src)
> > +{
> > + struct ptp_extts_event *dst;
> > + u32 remainder;
> > +
> > + dst = &queue->buf[queue->tail];
> > +
> > + dst->index = src->index;
> > + dst->t.sec = div_u64_rem(src->timestamp, 1000000000, &remainder);
> > + dst->t.nsec = remainder;
> > +
> > + if (!queue_free(queue))
> > + queue->overflow++;
> > +
> > + queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS;
> > +}
>
> So what is serializing access to the timestamp_event_queue here? I don't
> see any usage of tsevq_mux by the callers. Am I missing it? It looks
> like its called from interrupt context, so do you really need a spinlock
> and not a mutex here?
The external timestamp FIFO is written only from interrupt context.
The readers are from user space via read() or sysfs. The readers must
hold a mutex. As you know, FIFOs with exactly one reader and one
writer don't need locking.
However, looking again at my own code (after spending a long time in
the posicx clock stuff), I notice that, although FIFO overflow is
detected, I do not offer a way for user space to find this out or to
clear the error. I'll fix that.
> > +#define PTP_MAX_TIMESTAMPS 128
> > +
> > +struct timestamp_event_queue {
> > + struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
> > + int head;
> > + int tail;
> > + int overflow;
> > +};
> > +
> > +struct ptp_clock {
> > + struct posix_clock clock;
> > + struct device *dev;
> > + struct ptp_clock_info *info;
> > + dev_t devid;
> > + int index; /* index into clocks.map */
> > + struct pps_device *pps_source;
> > + struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
> > + struct mutex tsevq_mux; /* one process at a time reading the fifo */
> > + wait_queue_head_t tsev_wq;
> > +};
> > +
> > +static inline int queue_cnt(struct timestamp_event_queue *q)
> > +{
> > + int cnt = q->tail - q->head;
> > + return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
> > +}
>
> This probably needs a comment as to its locking rules. Something like
> "Callers must hold tsevq_mux."
I'll add a comment explaining the readers mutex and why no
reader/writer locking is needed.
> > +struct ptp_clock_time {
> > + __s64 sec; /* seconds */
> > + __u32 nsec; /* nanoseconds */
> > + __u32 reserved;
> > +};
> > +
> > +struct ptp_clock_caps {
> > + int max_adj; /* Maximum frequency adjustment in parts per billon. */
> > + int n_alarm; /* Number of programmable alarms. */
> > + int n_ext_ts; /* Number of external time stamp channels. */
> > + int n_per_out; /* Number of programmable periodic signals. */
> > + int pps; /* Whether the clock supports a PPS callback. */
> > +};
> > +
> > +struct ptp_extts_request {
> > + unsigned int index; /* Which channel to configure. */
> > + unsigned int flags; /* Bit field for PTP_xxx flags. */
> > +};
> > +
> > +struct ptp_perout_request {
> > + struct ptp_clock_time start; /* Absolute start time. */
> > + struct ptp_clock_time period; /* Desired period, zero means disable. */
> > + unsigned int index; /* Which channel to configure. */
> > + unsigned int flags; /* Reserved for future use. */
> > +};
>
> Since these are all new API/ABI structures, would it be wise to pad
> these out a bit more? You've got a couple of reserved fields, which is
> good, but if you think we're going to expand this at all, we may want to
> have a bit more wiggle room. The timex structure had something like 12
> unused ints (which came in handy when the tai field was added).
>
> Not sure what the wider opinion is on this though.
Okay, I'll pad them a bit more.
However, I don't intend to ever offer more than simple functionality
here. A general purpose DAQ API is not so easy to define (look at
comedi, for example). Also, the capabilities of the current crop of
clocks varies quite a bit.
So, I think the PHC should offer a PPS, simple period outputs, and
simple external timestamping. If someone want more complex DAQ like
functions, then they can offer that through comedi or whatever.
> > +struct ptp_extts_event {
> > + struct ptp_clock_time t; /* Time event occured. */
> > + unsigned int index; /* Which channel produced the event. */
> > +};
>
> Same padding suggestion for this as well.
Okay, and thanks for the review,
Richard
^ permalink raw reply
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