* [net-next 2/8] e1000e: Minor comment clean-up.
From: Jeff Kirsher @ 2012-04-04 7:55 UTC (permalink / raw)
To: davem; +Cc: Matthew Vick, netdev, gospo, sassmann, Jeff Kirsher
In-Reply-To: <1333526160-24937-1-git-send-email-jeffrey.t.kirsher@intel.com>
From: Matthew Vick <matthew.vick@intel.com>
Move the first phrase of a multi-line comment to the second line.
Signed-off-by: Matthew Vick <matthew.vick@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/e1000e/netdev.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 2c38a65..6b63388 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -1053,7 +1053,8 @@ static void e1000_print_hw_hang(struct work_struct *work)
if (!adapter->tx_hang_recheck &&
(adapter->flags2 & FLAG2_DMA_BURST)) {
- /* May be block on write-back, flush and detect again
+ /*
+ * May be block on write-back, flush and detect again
* flush pending descriptor writebacks to memory
*/
ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
--
1.7.7.6
^ permalink raw reply related
* [net-next 3/8] e1000e: cleanup NAPI routine
From: Jeff Kirsher @ 2012-04-04 7:55 UTC (permalink / raw)
To: davem; +Cc: Bruce Allan, netdev, gospo, sassmann, Jeff Kirsher
In-Reply-To: <1333526160-24937-1-git-send-email-jeffrey.t.kirsher@intel.com>
From: Bruce Allan <bruce.w.allan@intel.com>
Rename NAPI polling routine and a parameter with more appropriate names,
refactor a conditional branch to get rid of an unnecessary goto/label and
fix a line exceeding 80 columns.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/e1000e/netdev.c | 28 +++++++++++++---------------
1 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 6b63388..d88445d 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -2524,33 +2524,31 @@ err:
}
/**
- * e1000_clean - NAPI Rx polling callback
+ * e1000e_poll - NAPI Rx polling callback
* @napi: struct associated with this polling callback
- * @budget: amount of packets driver is allowed to process this poll
+ * @weight: number of packets driver is allowed to process this poll
**/
-static int e1000_clean(struct napi_struct *napi, int budget)
+static int e1000e_poll(struct napi_struct *napi, int weight)
{
- struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
+ struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
+ napi);
struct e1000_hw *hw = &adapter->hw;
struct net_device *poll_dev = adapter->netdev;
int tx_cleaned = 1, work_done = 0;
adapter = netdev_priv(poll_dev);
- if (adapter->msix_entries &&
- !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
- goto clean_rx;
+ if (!adapter->msix_entries ||
+ (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
+ tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
- tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
-
-clean_rx:
- adapter->clean_rx(adapter->rx_ring, &work_done, budget);
+ adapter->clean_rx(adapter->rx_ring, &work_done, weight);
if (!tx_cleaned)
- work_done = budget;
+ work_done = weight;
- /* If budget not fully consumed, exit the polling mode */
- if (work_done < budget) {
+ /* If weight not fully consumed, exit the polling mode */
+ if (work_done < weight) {
if (adapter->itr_setting & 3)
e1000_set_itr(adapter);
napi_complete(napi);
@@ -6201,7 +6199,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
netdev->netdev_ops = &e1000e_netdev_ops;
e1000e_set_ethtool_ops(netdev);
netdev->watchdog_timeo = 5 * HZ;
- netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
+ netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
netdev->mem_start = mmio_start;
--
1.7.7.6
^ permalink raw reply related
* [net-next 0/8][pull request] Intel Wired LAN Driver Update
From: Jeff Kirsher @ 2012-04-04 7:55 UTC (permalink / raw)
To: davem; +Cc: Jeff Kirsher, netdev, gospo, sassmann
This series of patches contains updates for e1000, e1000e, igb and
ixgbe. The e1000 patch finishes up the addition of RXALL support
flag from Ben Greear. The 2 igb patches adds the PTP support
from Richard Cochran. The remaining patches for e1000e and ixgbe
are cleanup patches (and rev the e1000e driver).
The following are changes since commit 68df25d6c556c4df4dad32a0585317eab356e325:
bnx2x: Change to driver version 1.72.10-0
and are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next master
Ben Greear (1):
e1000: Support RX-ALL flag.
Bruce Allan (3):
e1000e: cleanup NAPI routine
e1000e: cleanup indexed register arrays
e1000e: update driver version number
Emil Tantilov (1):
ixgbe: consolidate reporting of MSIX vectors into a single function
Matthew Vick (1):
e1000e: Minor comment clean-up.
Richard Cochran (2):
igb: add PTP Hardware Clock code
igb: offer a PTP Hardware Clock instead of the timecompare method
drivers/net/ethernet/intel/Kconfig | 11 +
drivers/net/ethernet/intel/e1000/e1000_main.c | 26 ++-
drivers/net/ethernet/intel/e1000e/ethtool.c | 52 ++--
drivers/net/ethernet/intel/e1000e/hw.h | 47 ++--
drivers/net/ethernet/intel/e1000e/netdev.c | 81 +++---
drivers/net/ethernet/intel/igb/Makefile | 1 +
drivers/net/ethernet/intel/igb/igb.h | 21 +-
drivers/net/ethernet/intel/igb/igb_main.c | 178 +----------
drivers/net/ethernet/intel/igb/igb_ptp.c | 381 +++++++++++++++++++++++
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 25 +--
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 29 ++-
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h | 2 +-
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 4 +-
13 files changed, 571 insertions(+), 287 deletions(-)
create mode 100644 drivers/net/ethernet/intel/igb/igb_ptp.c
--
1.7.7.6
^ permalink raw reply
* [net-next 1/8] e1000: Support RX-ALL flag.
From: Jeff Kirsher @ 2012-04-04 7:55 UTC (permalink / raw)
To: davem; +Cc: Ben Greear, netdev, gospo, sassmann, Jeff Kirsher
In-Reply-To: <1333526160-24937-1-git-send-email-jeffrey.t.kirsher@intel.com>
From: Ben Greear <greearb@candelatech.com>
This allows the NIC to receive errored frames (bad FCS, etc)
and pass them up the stack. This can be useful when using
sniffers.
Signed-off-by: Ben Greear <greearb@candelatech.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
drivers/net/ethernet/intel/e1000/e1000_main.c | 26 ++++++++++++++++++++++++-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ethernet/intel/e1000/e1000_main.c b/drivers/net/ethernet/intel/e1000/e1000_main.c
index 4348b6f..3d712f2 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_main.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_main.c
@@ -827,9 +827,10 @@ static int e1000_set_features(struct net_device *netdev,
if (changed & NETIF_F_HW_VLAN_RX)
e1000_vlan_mode(netdev, features);
- if (!(changed & NETIF_F_RXCSUM))
+ if (!(changed & (NETIF_F_RXCSUM | NETIF_F_RXALL)))
return 0;
+ netdev->features = features;
adapter->rx_csum = !!(features & NETIF_F_RXCSUM);
if (netif_running(netdev))
@@ -1074,6 +1075,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
netdev->features |= netdev->hw_features;
netdev->hw_features |= NETIF_F_RXCSUM;
+ netdev->hw_features |= NETIF_F_RXALL;
netdev->hw_features |= NETIF_F_RXFCS;
if (pci_using_dac) {
@@ -1841,6 +1843,22 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
break;
}
+ /* This is useful for sniffing bad packets. */
+ if (adapter->netdev->features & NETIF_F_RXALL) {
+ /* UPE and MPE will be handled by normal PROMISC logic
+ * in e1000e_set_rx_mode */
+ rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
+ E1000_RCTL_BAM | /* RX All Bcast Pkts */
+ E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
+
+ rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
+ E1000_RCTL_DPF | /* Allow filtered pause */
+ E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
+ /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
+ * and that breaks VLANs.
+ */
+ }
+
ew32(RCTL, rctl);
}
@@ -4057,6 +4075,8 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
irq_flags);
length--;
} else {
+ if (netdev->features & NETIF_F_RXALL)
+ goto process_skb;
/* recycle both page and skb */
buffer_info->skb = skb;
/* an error means any chain goes out the window
@@ -4069,6 +4089,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
}
#define rxtop rx_ring->rx_skb_top
+process_skb:
if (!(status & E1000_RXD_STAT_EOP)) {
/* this descriptor is only the beginning (or middle) */
if (!rxtop) {
@@ -4276,12 +4297,15 @@ static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
flags);
length--;
} else {
+ if (netdev->features & NETIF_F_RXALL)
+ goto process_skb;
/* recycle */
buffer_info->skb = skb;
goto next_desc;
}
}
+process_skb:
total_rx_bytes += (length - 4); /* don't count FCS */
total_rx_packets++;
--
1.7.7.6
^ permalink raw reply related
* Re: [PATCHv1] ipv6: Fix RTM_GETROUTE's interpretation of RTA_IIF to be consistent with ipv4
From: David Miller @ 2012-04-04 7:54 UTC (permalink / raw)
To: shmulik.ladkani
Cc: netdev, linux-kernel, eric.dumazet, kuznet, jmorris, yoshfuji,
kaber
In-Reply-To: <20120404105204.63122c38@pixies.home.jungo.com>
From: Shmulik Ladkani <shmulik.ladkani@gmail.com>
Date: Wed, 4 Apr 2012 10:52:04 +0300
> In case of 'alloc_skb' failure, shouldn't we issue a
> 'dst_release(&rt->dst)'?
>
> If correct, I'll submit a fix. Should have spotted this earlier.
Yep, we need a release there.
^ permalink raw reply
* Re: [PATCHv1] ipv6: Fix RTM_GETROUTE's interpretation of RTA_IIF to be consistent with ipv4
From: Shmulik Ladkani @ 2012-04-04 7:52 UTC (permalink / raw)
To: David Miller
Cc: netdev, linux-kernel, eric.dumazet, kuznet, jmorris, yoshfuji,
kaber
In-Reply-To: <20120401.173032.1881937766187683052.davem@davemloft.net>
Hi David,
On Sun, 01 Apr 2012 17:30:32 -0400 (EDT) David Miller <davem@davemloft.net> wrote:
> > Fix 'inet6_rtm_getroute()' so that RTA_IIF is interpreted as "lookup a
> > route as if a packet was received on the specified interface", similar
> > to IPv4's 'inet_rtm_getroute()' interpretation.
> >
> > Reported-by: Ami Koren <amikoren@yahoo.com>
> > Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
>
> Applied, thanks.
>
> > 1) An alternative: construction of an skb within 'inet6_rtm_getroute()'
> > and then calling 'ip6_route_input()' with the skb as an argument.
> > Thus, no need to split common code of 'ip6_route_input()'.
> > Less elegant IMO.
>
> Agreed.
>
> > 2) Better name for the new common function 'ip6_route_input_lookup()'
> > Will happily accept any better suggestions.
>
> No, it's fine.
>
> > 3) In IPv4 the 'ip_route_input()' call within 'inet_rtm_getroute()'is
> > protected by a 'local_bh_disable()' since dawn of history.
> > Not sure if similar protection needed within 'inet6_rtm_getroute()'.
>
> Since all the code paths are shared more than on the ipv4 side, both
> output and input route lookups can be done with and without BH
> disabling.
Thanks for the answers.
Looking at the patch again, I suspect I've missed one thing.
After applying patch, the code getting the 'rt' gets placed prior the
'alloc_skb()' - snip of new code:
if (iif) {
// some stuff ...
rt = (struct rt6_info *)ip6_route_input_lookup(net, dev, &fl6,
flags);
} else {
fl6.flowi6_oif = oif;
rt = (struct rt6_info *)ip6_route_output(net, NULL, &fl6);
}
skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL);
if (!skb) {
err = -ENOBUFS;
goto errout;
}
In case of 'alloc_skb' failure, shouldn't we issue a
'dst_release(&rt->dst)'?
If correct, I'll submit a fix. Should have spotted this earlier.
Regards,
Shmulik
^ permalink raw reply
* Re: [V6 PATCH] virtio-net: send gratuitous packets when needed
From: Michael S. Tsirkin @ 2012-04-04 7:51 UTC (permalink / raw)
To: David Miller; +Cc: netdev, qemu-devel, linux-kernel, virtualization
In-Reply-To: <20120403.174905.769295608759578804.davem@davemloft.net>
On Tue, Apr 03, 2012 at 05:49:05PM -0400, David Miller wrote:
> From: Jason Wang <jasowang@redhat.com>
> Date: Wed, 28 Mar 2012 13:44:28 +0800
>
> > As hypervior does not have the knowledge of guest network configuration, it's
> > better to ask guest to send gratuitous packets when needed.
> >
> > Guest tests VIRTIO_NET_S_ANNOUNCE bit during config change interrupt and when it
> > is set, a workqueue is scheduled to send gratuitous packet through
> > NETDEV_NOTIFY_PEERS. This feature is negotiated through bit
> > VIRTIO_NET_F_GUEST_ANNOUNCE.
> ...
> > Signed-off-by: Jason Wang <jasowang@redhat.com>
>
> Michael and others, what's the story with this patch?
It's a new feature so it will be 3.5 material when it's ready.
Sent some comments for now.
Thanks,
MST
> _______________________________________________
> Virtualization mailing list
> Virtualization@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/virtualization
^ permalink raw reply
* Re: [V6 PATCH] virtio-net: send gratuitous packets when needed
From: Michael S. Tsirkin @ 2012-04-04 7:49 UTC (permalink / raw)
To: Jason Wang
Cc: netdev, qemu-devel, linux-kernel, Amit Shah, virtualization,
davem
In-Reply-To: <20120328054428.34415.75432.stgit@amd-6168-8-1.englab.nay.redhat.com>
On Wed, Mar 28, 2012 at 01:44:28PM +0800, Jason Wang wrote:
> As hypervior does not have the knowledge of guest network configuration, it's
> better to ask guest to send gratuitous packets when needed.
>
> Guest tests VIRTIO_NET_S_ANNOUNCE bit during config change interrupt and when it
> is set, a workqueue is scheduled to send gratuitous packet through
> NETDEV_NOTIFY_PEERS. This feature is negotiated through bit
> VIRTIO_NET_F_GUEST_ANNOUNCE.
>
> Changes from v5:
> - notify the chain before acking the link annoucement
> - ack the link announcement notification through control vq
>
> Changes from v4:
> - typos
> - handle workqueue unconditionally
> - move VIRTIO_NET_S_ANNOUNCE to bit 8 to separate rw bits from ro bits
>
> Changes from v3:
> - cancel the workqueue during freeze
>
> Changes from v2:
> - fix the race between unregister_dev() and workqueue
>
> Signed-off-by: Jason Wang <jasowang@redhat.com>
I think this needs some fixes. See below.
Thanks.
> ---
> drivers/net/virtio_net.c | 32 +++++++++++++++++++++++++++++++-
> include/linux/virtio_net.h | 13 +++++++++++++
> 2 files changed, 44 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
> index 4880aa8..0f60da7 100644
> --- a/drivers/net/virtio_net.c
> +++ b/drivers/net/virtio_net.c
> @@ -72,6 +72,9 @@ struct virtnet_info {
> /* Work struct for refilling if we run low on memory. */
> struct delayed_work refill;
>
> + /* Work struct for sending gratuitous packets. */
A bit confusing: it does not send anything itself.
A better comment 'for announcing the existence of device
on the network'.
> + struct work_struct announce;
> +
> /* Chain pages by the private ptr. */
> struct page *pages;
>
> @@ -781,12 +784,30 @@ static bool virtnet_send_command(struct virtnet_info *vi, u8 class, u8 cmd,
> return status == VIRTIO_NET_OK;
> }
>
> +static void virtnet_ack_link_announce(struct virtnet_info *vi)
> +{
> + if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_ANNOUNCE,
> + VIRTIO_NET_CTRL_ANNOUNCE_ACK, NULL,
> + 0, 0)) {
This can run in parallel with other commands. That's pretty bad -
will corrupt the cvq.
Take rtnl lock around calls to this function?
> + dev_warn(&vi->dev->dev, "Failed to ack link nnounce.\n");
announce
> + }
Better to drop {} around a single statement.
> +}
> +
> +static void announce_work(struct work_struct *work)
> +{
> + struct virtnet_info *vi = container_of(work, struct virtnet_info,
> + announce);
> + netif_notify_peers(vi->dev);
> + virtnet_ack_link_announce(vi);
> +}
> +
> static int virtnet_close(struct net_device *dev)
> {
> struct virtnet_info *vi = netdev_priv(dev);
>
> /* Make sure refill_work doesn't re-enable napi! */
> cancel_delayed_work_sync(&vi->refill);
> + cancel_work_sync(&vi->announce);
I think that a config change event can trigger after this point,
so cancel here won't be effective. But why do it here?
virtnet_remove not a better place? We can do it
after remove_vq_common.
> napi_disable(&vi->napi);
>
> return 0;
> @@ -962,11 +983,17 @@ static void virtnet_update_status(struct virtnet_info *vi)
> return;
>
> /* Ignore unknown (future) status bits */
> - v &= VIRTIO_NET_S_LINK_UP;
> + v &= VIRTIO_NET_S_LINK_UP | VIRTIO_NET_S_ANNOUNCE;
The announce bit in vi->status is always clear,
so this is IMO confusing. I would do:
if (v & VIRTIO_NET_S_ANNOUNCE) {
schedule
}
v &= VIRTIO_NET_S_LINK_UP;
and the rest of the logic is not necessary then.
Also, this might run extra ack announce commands after
VIRTIO_NET_S_ANNOUNCE bit is clear. The spec
isn't clear on whether this is legal.
It would be very hard to fix this, so let's add a comment
stating that it's legal, and clarify the spec
in any case.
>
> if (vi->status == v)
> return;
>
> + if (v & VIRTIO_NET_S_ANNOUNCE) {
> + v &= ~VIRTIO_NET_S_ANNOUNCE;
> + if (v & VIRTIO_NET_S_LINK_UP)
> + schedule_work(&vi->announce);
I think we really want an nrt wq here - if this triggers
multiple times there's no good reason to try and run
the ack command many times in parallel.
> + }
> +
> vi->status = v;
>
> if (vi->status & VIRTIO_NET_S_LINK_UP) {
> @@ -1076,6 +1103,7 @@ static int virtnet_probe(struct virtio_device *vdev)
> goto free;
>
> INIT_DELAYED_WORK(&vi->refill, refill_work);
> + INIT_WORK(&vi->announce, announce_work);
> sg_init_table(vi->rx_sg, ARRAY_SIZE(vi->rx_sg));
> sg_init_table(vi->tx_sg, ARRAY_SIZE(vi->tx_sg));
>
> @@ -1187,6 +1215,7 @@ static int virtnet_freeze(struct virtio_device *vdev)
> virtqueue_disable_cb(vi->svq);
> if (virtio_has_feature(vi->vdev, VIRTIO_NET_F_CTRL_VQ))
> virtqueue_disable_cb(vi->cvq);
> + cancel_work_sync(&vi->announce);
A config change event can trigger after this point,
so cancel here won't be effective.
Possibly, we need state like config_enable in the block
device.
Also, what exactly will happen on suspend?
As we reset, ANNOUCE bit will be clear so -
do we forget to announce? Probably not good ...
>
> netif_device_detach(vi->dev);
> cancel_delayed_work_sync(&vi->refill);
> @@ -1233,6 +1262,7 @@ static unsigned int features[] = {
> VIRTIO_NET_F_GUEST_ECN, VIRTIO_NET_F_GUEST_UFO,
> VIRTIO_NET_F_MRG_RXBUF, VIRTIO_NET_F_STATUS, VIRTIO_NET_F_CTRL_VQ,
> VIRTIO_NET_F_CTRL_RX, VIRTIO_NET_F_CTRL_VLAN,
> + VIRTIO_NET_F_GUEST_ANNOUNCE,
> };
>
> static struct virtio_driver virtio_net_driver = {
> diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h
> index 970d5a2..383e8a0 100644
> --- a/include/linux/virtio_net.h
> +++ b/include/linux/virtio_net.h
> @@ -49,8 +49,10 @@
> #define VIRTIO_NET_F_CTRL_RX 18 /* Control channel RX mode support */
> #define VIRTIO_NET_F_CTRL_VLAN 19 /* Control channel VLAN filtering */
> #define VIRTIO_NET_F_CTRL_RX_EXTRA 20 /* Extra RX mode control support */
> +#define VIRTIO_NET_F_GUEST_ANNOUNCE 21 /* Guest can send gratituous packet */
Rusty aligned the comments using tabs so let's do it here too?
A better comment 'can announce device on the network'.
>
> #define VIRTIO_NET_S_LINK_UP 1 /* Link is up */
> +#define VIRTIO_NET_S_ANNOUNCE 2 /* Announcement is needed */
why 3 spaces before the value here?
>
> struct virtio_net_config {
> /* The config defining mac address (if VIRTIO_NET_F_MAC) */
> @@ -152,4 +154,15 @@ struct virtio_net_ctrl_mac {
> #define VIRTIO_NET_CTRL_VLAN_ADD 0
> #define VIRTIO_NET_CTRL_VLAN_DEL 1
>
> +/*
> + * Control link announce acknowledgement
> + *
> + * The command VIRTIO_NET_CTRL_ANNOUNCE_ACK is used to indicate that
> + * driver has recevied the notification and device would clear the
s/recevied/received/
A bit clearer to replace 'and' with ; here.
> + * VIRTIO_NET_S_ANNOUNCE bit in the status filed after it received
s/filed/field/
s/received/receives/
> + * this command.
> + */
> +#define VIRTIO_NET_CTRL_ANNOUNCE 3
> + #define VIRTIO_NET_CTRL_ANNOUNCE_ACK 0
> +
> #endif /* _LINUX_VIRTIO_NET_H */
>
> _______________________________________________
> Virtualization mailing list
> Virtualization@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/virtualization
^ permalink raw reply
* Re: [PATCH] stmmac: re-add IFF_UNICAST_FLT for dwmac1000
From: Marc Kleine-Budde @ 2012-04-04 7:33 UTC (permalink / raw)
To: Eric Dumazet; +Cc: peppe.cavallaro, rayagond, netdev
In-Reply-To: <1333477224.18626.289.camel@edumazet-glaptop>
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On 04/03/2012 08:20 PM, Eric Dumazet wrote:
> On Tue, 2012-04-03 at 19:44 +0200, Marc Kleine-Budde wrote:
>> In commit (bfab27a stmmac: add the experimental PCI support) the
>> IFF_UNICAST_FLT flag has been removed from the stmmac_mac_device_setup()
>> function. This patch re-adds the flag.
>>
>> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
>> ---
>>
>> Just compile time tested, since I don't have the hardware.
>> Applies to net-next/master (and v3.3).
>>
>> regards, Marc
>>
>> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++--
>> 1 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> index e85ffbd..07e0c78 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> @@ -1737,9 +1737,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
>> struct mac_device_info *mac;
>>
>> /* Identify the MAC HW device */
>> - if (priv->plat->has_gmac)
>> + if (priv->plat->has_gmac) {
>> + priv->dev->priv_flags |= IFF_UNICAST_FLT;
>> mac = dwmac1000_setup(priv->ioaddr);
>> - else
>> + } else
>> mac = dwmac100_setup(priv->ioaddr);
>> if (!mac)
>> return -ENOMEM;
>
>
> if (priv->plat->has_gmac) {
> priv->dev->priv_flags |= IFF_UNICAST_FLT;
> mac = dwmac1000_setup(priv->ioaddr);
> } else {
> mac = dwmac100_setup(priv->ioaddr);
> }
>
> (Documentation/CodingStyle line 175)
Thanks for the hint.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* Re: [PATCH v6 0/2] Ethernet drivers for WIZnet chips
From: Mike Sinkovsky @ 2012-04-04 7:25 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, linux-kernel
In-Reply-To: <1333520260.18626.383.camel@edumazet-glaptop>
04.04.2012 12:17, Eric Dumazet написал:
> On Wed, 2012-04-04 at 11:58 +0600, Mike Sinkovsky wrote:
>
>> About races - I can't see any, in this very simple procedure.
>> But maybe I missed something..
>
> Maybe post the code and we can help you.
Posted v7.
But - today I don't see tx_timeout(), even if flow control is enabled!
Weird still...
--
Mike
^ permalink raw reply
* [PATCH v7 2/2] Ethernet driver for the WIZnet W5100 chip
From: Mike Sinkovsky @ 2012-04-04 7:23 UTC (permalink / raw)
To: netdev, linux-kernel, eric.dumazet; +Cc: Mike Sinkovsky
In-Reply-To: <1333450726-24455-1-git-send-email-msink@permonline.ru>
Based on original driver from chip manufacturer, but nearly full rewite.
Tested and used in production with Blackfin BF531 embedded processor.
Signed-off-by: Mike Sinkovsky <msink@permonline.ru>
---
drivers/net/ethernet/wiznet/Kconfig | 12 +
drivers/net/ethernet/wiznet/Makefile | 1 +
drivers/net/ethernet/wiznet/w5100.c | 801 ++++++++++++++++++++++++++++++++++
3 files changed, 814 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ethernet/wiznet/w5100.c
diff --git a/drivers/net/ethernet/wiznet/Kconfig b/drivers/net/ethernet/wiznet/Kconfig
index 364292b..07b6d3d 100644
--- a/drivers/net/ethernet/wiznet/Kconfig
+++ b/drivers/net/ethernet/wiznet/Kconfig
@@ -17,6 +17,18 @@ config NET_VENDOR_WIZNET
if NET_VENDOR_WIZNET
+config WIZNET_W5100
+ tristate "WIZnet W5100 Ethernet support"
+ ---help---
+ Support for WIZnet W5100 chips.
+
+ W5100 is a single chip with integrated 10/100 Ethernet MAC,
+ PHY and hardware TCP/IP stack, but this driver is limited to
+ the MAC and PHY functions only, onchip TCP/IP is unused.
+
+ To compile this driver as a module, choose M here: the module
+ will be called w5100.
+
config WIZNET_W5300
tristate "WIZnet W5300 Ethernet support"
---help---
diff --git a/drivers/net/ethernet/wiznet/Makefile b/drivers/net/ethernet/wiznet/Makefile
index 88e0a3e..c614535 100644
--- a/drivers/net/ethernet/wiznet/Makefile
+++ b/drivers/net/ethernet/wiznet/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_WIZNET_W5100) += w5100.o
obj-$(CONFIG_WIZNET_W5300) += w5300.o
diff --git a/drivers/net/ethernet/wiznet/w5100.c b/drivers/net/ethernet/wiznet/w5100.c
new file mode 100644
index 0000000..2d905f9
--- /dev/null
+++ b/drivers/net/ethernet/wiznet/w5100.c
@@ -0,0 +1,801 @@
+/*
+ * Ethernet driver for the WIZnet W5100 chip.
+ *
+ * Copyright (C) 2006-2008 WIZnet Co.,Ltd.
+ * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/kconfig.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/wiznet.h>
+#include <linux/ethtool.h>
+#include <linux/skbuff.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+
+#define DRV_NAME "w5100"
+#define DRV_VERSION "2012-04-04"
+
+MODULE_DESCRIPTION("WIZnet W5100 Ethernet driver v"DRV_VERSION);
+MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
+MODULE_ALIAS("platform:"DRV_NAME);
+MODULE_LICENSE("GPL");
+
+/*
+ * Registers
+ */
+#define W5100_COMMON_REGS 0x0000
+#define W5100_MR 0x0000 /* Mode Register */
+#define MR_RST 0x80 /* S/W reset */
+#define MR_PB 0x10 /* Ping block */
+#define MR_AI 0x02 /* Address Auto-Increment */
+#define MR_IND 0x01 /* Indirect mode */
+#define W5100_SHAR 0x0009 /* Source MAC address */
+#define W5100_IR 0x0015 /* Interrupt Register */
+#define W5100_IMR 0x0016 /* Interrupt Mask Register */
+#define IR_S0 0x01 /* S0 interrupt */
+#define W5100_RTR 0x0017 /* Retry Time-value Register */
+#define RTR_DEFAULT 2000 /* =0x07d0 (2000) */
+#define W5100_RMSR 0x001a /* Receive Memory Size */
+#define W5100_TMSR 0x001b /* Transmit Memory Size */
+#define W5100_COMMON_REGS_LEN 0x0040
+
+#define W5100_S0_REGS 0x0400
+#define W5100_S0_MR 0x0400 /* S0 Mode Register */
+#define S0_MR_MACRAW 0x04 /* MAC RAW mode (promiscous) */
+#define S0_MR_MACRAW_MF 0x44 /* MAC RAW mode (filtered) */
+#define W5100_S0_CR 0x0401 /* S0 Command Register */
+#define S0_CR_OPEN 0x01 /* OPEN command */
+#define S0_CR_CLOSE 0x10 /* CLOSE command */
+#define S0_CR_SEND 0x20 /* SEND command */
+#define S0_CR_RECV 0x40 /* RECV command */
+#define W5100_S0_IR 0x0402 /* S0 Interrupt Register */
+#define S0_IR_SENDOK 0x10 /* complete sending */
+#define S0_IR_RECV 0x04 /* receiving data */
+#define W5100_S0_SR 0x0403 /* S0 Status Register */
+#define S0_SR_MACRAW 0x42 /* mac raw mode */
+#define W5100_S0_TX_FSR 0x0420 /* S0 Transmit free memory size */
+#define W5100_S0_TX_RD 0x0422 /* S0 Transmit memory read pointer */
+#define W5100_S0_TX_WR 0x0424 /* S0 Transmit memory write pointer */
+#define W5100_S0_RX_RSR 0x0426 /* S0 Receive free memory size */
+#define W5100_S0_RX_RD 0x0428 /* S0 Receive memory read pointer */
+#define W5100_S0_REGS_LEN 0x0040
+
+#define W5100_TX_MEM_START 0x4000
+#define W5100_TX_MEM_END 0x5fff
+#define W5100_TX_MEM_MASK 0x1fff
+#define W5100_RX_MEM_START 0x6000
+#define W5100_RX_MEM_END 0x7fff
+#define W5100_RX_MEM_MASK 0x1fff
+
+/*
+ * Device driver private data structure
+ */
+struct w5100_priv {
+ void __iomem *base;
+ spinlock_t reg_lock;
+ bool indirect;
+ u8 (*read)(struct w5100_priv *priv, u16 addr);
+ void (*write)(struct w5100_priv *priv, u16 addr, u8 data);
+ u16 (*read16)(struct w5100_priv *priv, u16 addr);
+ void (*write16)(struct w5100_priv *priv, u16 addr, u16 data);
+ void (*readbuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
+ void (*writebuf)(struct w5100_priv *priv, u16 addr, u8 *buf, int len);
+ int irq;
+ int link_irq;
+ int link_gpio;
+
+ struct napi_struct napi;
+ struct net_device *ndev;
+ bool promisc;
+ u32 msg_enable;
+};
+
+/************************************************************************
+ *
+ * Lowlevel I/O functions
+ *
+ ***********************************************************************/
+
+/*
+ * In direct address mode host system can directly access W5100 registers
+ * after mapping to Memory-Mapped I/O space.
+ *
+ * 0x8000 bytes are required for memory space.
+ */
+static inline u8 w5100_read_direct(struct w5100_priv *priv, u16 addr)
+{
+ return ioread8(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
+}
+
+static inline void w5100_write_direct(struct w5100_priv *priv,
+ u16 addr, u8 data)
+{
+ iowrite8(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
+}
+
+static u16 w5100_read16_direct(struct w5100_priv *priv, u16 addr)
+{
+ u16 data;
+ data = w5100_read_direct(priv, addr) << 8;
+ data |= w5100_read_direct(priv, addr + 1);
+ return data;
+}
+
+static void w5100_write16_direct(struct w5100_priv *priv, u16 addr, u16 data)
+{
+ w5100_write_direct(priv, addr, data >> 8);
+ w5100_write_direct(priv, addr + 1, data);
+}
+
+static void w5100_readbuf_direct(struct w5100_priv *priv,
+ u16 offset, u8 *buf, int len)
+{
+ u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
+ int i;
+
+ for (i = 0; i < len; i++, addr++) {
+ if (unlikely(addr > W5100_RX_MEM_END))
+ addr = W5100_RX_MEM_START;
+ *buf++ = w5100_read_direct(priv, addr);
+ }
+}
+
+static void w5100_writebuf_direct(struct w5100_priv *priv,
+ u16 offset, u8 *buf, int len)
+{
+ u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
+ int i;
+
+ for (i = 0; i < len; i++, addr++) {
+ if (unlikely(addr > W5100_TX_MEM_END))
+ addr = W5100_TX_MEM_START;
+ w5100_write_direct(priv, addr, *buf++);
+ }
+}
+
+/*
+ * In indirect address mode host system indirectly accesses registers by
+ * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
+ * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
+ * Mode Register (MR) is directly accessible.
+ *
+ * Only 0x04 bytes are required for memory space.
+ */
+#define W5100_IDM_AR 0x01 /* Indirect Mode Address Register */
+#define W5100_IDM_DR 0x03 /* Indirect Mode Data Register */
+
+static u8 w5100_read_indirect(struct w5100_priv *priv, u16 addr)
+{
+ unsigned long flags;
+ u8 data;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ data = w5100_read_direct(priv, W5100_IDM_DR);
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+
+ return data;
+}
+
+static void w5100_write_indirect(struct w5100_priv *priv, u16 addr, u8 data)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ w5100_write_direct(priv, W5100_IDM_DR, data);
+ mmiowb();
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+}
+
+static u16 w5100_read16_indirect(struct w5100_priv *priv, u16 addr)
+{
+ unsigned long flags;
+ u16 data;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ data = w5100_read_direct(priv, W5100_IDM_DR) << 8;
+ data |= w5100_read_direct(priv, W5100_IDM_DR);
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+
+ return data;
+}
+
+static void w5100_write16_indirect(struct w5100_priv *priv, u16 addr, u16 data)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ w5100_write_direct(priv, W5100_IDM_DR, data >> 8);
+ w5100_write_direct(priv, W5100_IDM_DR, data);
+ mmiowb();
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+}
+
+static void w5100_readbuf_indirect(struct w5100_priv *priv,
+ u16 offset, u8 *buf, int len)
+{
+ u16 addr = W5100_RX_MEM_START + (offset & W5100_RX_MEM_MASK);
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+
+ for (i = 0; i < len; i++, addr++) {
+ if (unlikely(addr > W5100_RX_MEM_END)) {
+ addr = W5100_RX_MEM_START;
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ }
+ *buf++ = w5100_read_direct(priv, W5100_IDM_DR);
+ }
+ mmiowb();
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+}
+
+static void w5100_writebuf_indirect(struct w5100_priv *priv,
+ u16 offset, u8 *buf, int len)
+{
+ u16 addr = W5100_TX_MEM_START + (offset & W5100_TX_MEM_MASK);
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+
+ for (i = 0; i < len; i++, addr++) {
+ if (unlikely(addr > W5100_TX_MEM_END)) {
+ addr = W5100_TX_MEM_START;
+ w5100_write16_direct(priv, W5100_IDM_AR, addr);
+ mmiowb();
+ }
+ w5100_write_direct(priv, W5100_IDM_DR, *buf++);
+ }
+ mmiowb();
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+}
+
+#if defined(CONFIG_WIZNET_BUS_DIRECT)
+#define w5100_read w5100_read_direct
+#define w5100_write w5100_write_direct
+#define w5100_read16 w5100_read16_direct
+#define w5100_write16 w5100_write16_direct
+#define w5100_readbuf w5100_readbuf_direct
+#define w5100_writebuf w5100_writebuf_direct
+
+#elif defined(CONFIG_WIZNET_BUS_INDIRECT)
+#define w5100_read w5100_read_indirect
+#define w5100_write w5100_write_indirect
+#define w5100_read16 w5100_read16_indirect
+#define w5100_write16 w5100_write16_indirect
+#define w5100_readbuf w5100_readbuf_indirect
+#define w5100_writebuf w5100_writebuf_indirect
+
+#else /* CONFIG_WIZNET_BUS_ANY */
+#define w5100_read priv->read
+#define w5100_write priv->write
+#define w5100_read16 priv->read16
+#define w5100_write16 priv->write16
+#define w5100_readbuf priv->readbuf
+#define w5100_writebuf priv->writebuf
+#endif
+
+static int w5100_command(struct w5100_priv *priv, u16 cmd)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+ w5100_write(priv, W5100_S0_CR, cmd);
+ mmiowb();
+
+ while (w5100_read(priv, W5100_S0_CR) != 0) {
+ if (time_after(jiffies, timeout))
+ return -EIO;
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static void w5100_write_macaddr(struct w5100_priv *priv)
+{
+ struct net_device *ndev = priv->ndev;
+ int i;
+
+ for (i = 0; i < ETH_ALEN; i++)
+ w5100_write(priv, W5100_SHAR + i, ndev->dev_addr[i]);
+ mmiowb();
+}
+
+static void w5100_hw_reset(struct w5100_priv *priv)
+{
+ w5100_write_direct(priv, W5100_MR, MR_RST);
+ mmiowb();
+ mdelay(5);
+ w5100_write_direct(priv, W5100_MR, priv->indirect ?
+ MR_PB | MR_AI | MR_IND :
+ MR_PB);
+ mmiowb();
+ w5100_write(priv, W5100_IMR, 0);
+ w5100_write_macaddr(priv);
+
+ /* Configure 16K of internal memory
+ * as 8K RX buffer and 8K TX buffer
+ */
+ w5100_write(priv, W5100_RMSR, 0x03);
+ w5100_write(priv, W5100_TMSR, 0x03);
+ mmiowb();
+}
+
+static void w5100_hw_start(struct w5100_priv *priv)
+{
+ w5100_write(priv, W5100_S0_MR, priv->promisc ?
+ S0_MR_MACRAW : S0_MR_MACRAW_MF);
+ mmiowb();
+ w5100_command(priv, S0_CR_OPEN);
+ w5100_write(priv, W5100_IMR, IR_S0);
+ mmiowb();
+}
+
+static void w5100_hw_close(struct w5100_priv *priv)
+{
+ w5100_write(priv, W5100_IMR, 0);
+ mmiowb();
+ w5100_command(priv, S0_CR_CLOSE);
+}
+
+/***********************************************************************
+ *
+ * Device driver functions / callbacks
+ *
+ ***********************************************************************/
+
+static void w5100_get_drvinfo(struct net_device *ndev,
+ struct ethtool_drvinfo *info)
+{
+ strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strlcpy(info->version, DRV_VERSION, sizeof(info->version));
+ strlcpy(info->bus_info, dev_name(ndev->dev.parent),
+ sizeof(info->bus_info));
+}
+
+static u32 w5100_get_link(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ if (gpio_is_valid(priv->link_gpio))
+ return !!gpio_get_value(priv->link_gpio);
+
+ return 1;
+}
+
+static u32 w5100_get_msglevel(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ return priv->msg_enable;
+}
+
+static void w5100_set_msglevel(struct net_device *ndev, u32 value)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ priv->msg_enable = value;
+}
+
+static int w5100_get_regs_len(struct net_device *ndev)
+{
+ return W5100_COMMON_REGS_LEN + W5100_S0_REGS_LEN;
+}
+
+static void w5100_get_regs(struct net_device *ndev,
+ struct ethtool_regs *regs, void *_buf)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+ u8 *buf = _buf;
+ u16 i;
+
+ regs->version = 1;
+ for (i = 0; i < W5100_COMMON_REGS_LEN; i++)
+ *buf++ = w5100_read(priv, W5100_COMMON_REGS + i);
+ for (i = 0; i < W5100_S0_REGS_LEN; i++)
+ *buf++ = w5100_read(priv, W5100_S0_REGS + i);
+}
+
+static void w5100_tx_timeout(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ netif_stop_queue(ndev);
+ w5100_hw_reset(priv);
+ w5100_hw_start(priv);
+ ndev->stats.tx_errors++;
+ ndev->trans_start = jiffies;
+ netif_wake_queue(ndev);
+}
+
+static int w5100_start_tx(struct sk_buff *skb, struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+ u16 offset;
+
+ if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW))
+ netif_stop_queue(ndev);
+
+ offset = w5100_read16(priv, W5100_S0_TX_WR);
+ w5100_writebuf(priv, offset, skb->data, skb->len);
+ w5100_write16(priv, W5100_S0_TX_WR, offset + skb->len);
+ mmiowb();
+ ndev->stats.tx_bytes += skb->len;
+ ndev->stats.tx_packets++;
+ dev_kfree_skb(skb);
+
+ w5100_command(priv, S0_CR_SEND);
+
+ return NETDEV_TX_OK;
+}
+
+static int w5100_napi_poll(struct napi_struct *napi, int budget)
+{
+ struct w5100_priv *priv = container_of(napi, struct w5100_priv, napi);
+ struct net_device *ndev = priv->ndev;
+ struct sk_buff *skb;
+ int rx_count;
+ u16 rx_len;
+ u16 offset;
+ u8 header[2];
+
+ for (rx_count = 0; rx_count < budget; rx_count++) {
+ u16 rx_buf_len = w5100_read16(priv, W5100_S0_RX_RSR);
+ if (rx_buf_len == 0)
+ break;
+
+ offset = w5100_read16(priv, W5100_S0_RX_RD);
+ w5100_readbuf(priv, offset, header, 2);
+ rx_len = get_unaligned_be16(header) - 2;
+
+ skb = netdev_alloc_skb_ip_align(ndev, rx_len);
+ if (unlikely(!skb)) {
+ w5100_write16(priv, W5100_S0_RX_RD,
+ offset + rx_buf_len);
+ w5100_command(priv, S0_CR_RECV);
+ ndev->stats.rx_dropped++;
+ return -ENOMEM;
+ }
+
+ skb_put(skb, rx_len);
+ w5100_readbuf(priv, offset + 2, skb->data, rx_len);
+ w5100_write16(priv, W5100_S0_RX_RD, offset + 2 + rx_len);
+ mmiowb();
+ w5100_command(priv, S0_CR_RECV);
+ skb->protocol = eth_type_trans(skb, ndev);
+
+ netif_receive_skb(skb);
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += rx_len;
+ }
+
+ if (rx_count < budget) {
+ w5100_write(priv, W5100_IMR, IR_S0);
+ mmiowb();
+ napi_complete(napi);
+ }
+
+ return rx_count;
+}
+
+static irqreturn_t w5100_interrupt(int irq, void *ndev_instance)
+{
+ struct net_device *ndev = ndev_instance;
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ int ir = w5100_read(priv, W5100_S0_IR);
+ if (!ir)
+ return IRQ_NONE;
+ w5100_write(priv, W5100_S0_IR, ir);
+ mmiowb();
+
+ if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW) && (ir & S0_IR_SENDOK)) {
+ netif_dbg(priv, tx_done, ndev, "tx done\n");
+ netif_wake_queue(ndev);
+ }
+
+ if (ir & S0_IR_RECV) {
+ if (napi_schedule_prep(&priv->napi)) {
+ w5100_write(priv, W5100_IMR, 0);
+ mmiowb();
+ __napi_schedule(&priv->napi);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t w5100_detect_link(int irq, void *ndev_instance)
+{
+ struct net_device *ndev = ndev_instance;
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ if (netif_running(ndev)) {
+ if (gpio_get_value(priv->link_gpio) != 0) {
+ netif_info(priv, link, ndev, "link is up\n");
+ netif_carrier_on(ndev);
+ } else {
+ netif_info(priv, link, ndev, "link is down\n");
+ netif_carrier_off(ndev);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void w5100_set_rx_mode(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+ bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
+
+ if (priv->promisc != set_promisc) {
+ priv->promisc = set_promisc;
+ w5100_hw_start(priv);
+ }
+}
+
+static int w5100_set_macaddr(struct net_device *ndev, void *addr)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+ struct sockaddr *sock_addr = addr;
+
+ if (!is_valid_ether_addr(sock_addr->sa_data))
+ return -EADDRNOTAVAIL;
+ memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
+ ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
+ w5100_write_macaddr(priv);
+ return 0;
+}
+
+static int w5100_open(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ netif_info(priv, ifup, ndev, "enabling\n");
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ return -EINVAL;
+ w5100_hw_start(priv);
+ napi_enable(&priv->napi);
+ netif_start_queue(ndev);
+ if (!gpio_is_valid(priv->link_gpio) ||
+ gpio_get_value(priv->link_gpio) != 0)
+ netif_carrier_on(ndev);
+ return 0;
+}
+
+static int w5100_stop(struct net_device *ndev)
+{
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ netif_info(priv, ifdown, ndev, "shutting down\n");
+ w5100_hw_close(priv);
+ netif_carrier_off(ndev);
+ netif_stop_queue(ndev);
+ napi_disable(&priv->napi);
+ return 0;
+}
+
+static const struct ethtool_ops w5100_ethtool_ops = {
+ .get_drvinfo = w5100_get_drvinfo,
+ .get_msglevel = w5100_get_msglevel,
+ .set_msglevel = w5100_set_msglevel,
+ .get_link = w5100_get_link,
+ .get_regs_len = w5100_get_regs_len,
+ .get_regs = w5100_get_regs,
+};
+
+static const struct net_device_ops w5100_netdev_ops = {
+ .ndo_open = w5100_open,
+ .ndo_stop = w5100_stop,
+ .ndo_start_xmit = w5100_start_tx,
+ .ndo_tx_timeout = w5100_tx_timeout,
+ .ndo_set_rx_mode = w5100_set_rx_mode,
+ .ndo_set_mac_address = w5100_set_macaddr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+};
+
+static int __devinit w5100_hw_probe(struct platform_device *pdev)
+{
+ struct wiznet_platform_data *data = pdev->dev.platform_data;
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5100_priv *priv = netdev_priv(ndev);
+ const char *name = netdev_name(ndev);
+ struct resource *mem;
+ int mem_size;
+ int irq;
+ int ret;
+
+ if (data && is_valid_ether_addr(data->mac_addr)) {
+ memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
+ } else {
+ random_ether_addr(ndev->dev_addr);
+ ndev->addr_assign_type |= NET_ADDR_RANDOM;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem)
+ return -ENXIO;
+ mem_size = resource_size(mem);
+ if (!devm_request_mem_region(&pdev->dev, mem->start, mem_size, name))
+ return -EBUSY;
+ priv->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
+ if (!priv->base)
+ return -EBUSY;
+
+ spin_lock_init(&priv->reg_lock);
+ priv->indirect = mem_size < W5100_BUS_DIRECT_SIZE;
+ if (priv->indirect) {
+ priv->read = w5100_read_indirect;
+ priv->write = w5100_write_indirect;
+ priv->read16 = w5100_read16_indirect;
+ priv->write16 = w5100_write16_indirect;
+ priv->readbuf = w5100_readbuf_indirect;
+ priv->writebuf = w5100_writebuf_indirect;
+ } else {
+ priv->read = w5100_read_direct;
+ priv->write = w5100_write_direct;
+ priv->read16 = w5100_read16_direct;
+ priv->write16 = w5100_write16_direct;
+ priv->readbuf = w5100_readbuf_direct;
+ priv->writebuf = w5100_writebuf_direct;
+ }
+
+ w5100_hw_reset(priv);
+ if (w5100_read16(priv, W5100_RTR) != RTR_DEFAULT)
+ return -ENODEV;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+ ret = devm_request_irq(&pdev->dev, irq, w5100_interrupt,
+ IRQ_TYPE_LEVEL_LOW, name, ndev);
+ if (ret < 0)
+ return ret;
+ priv->irq = irq;
+
+ priv->link_gpio = data->link_gpio;
+ if (gpio_is_valid(priv->link_gpio)) {
+ char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
+ if (!link_name)
+ return -ENOMEM;
+ snprintf(link_name, 16, "%s-link", name);
+ priv->link_irq = gpio_to_irq(priv->link_gpio);
+ if (devm_request_threaded_irq(&pdev->dev,
+ priv->link_irq, NULL, w5100_detect_link,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ link_name, priv->ndev) < 0)
+ priv->link_gpio = -EINVAL;
+ }
+
+ netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
+ return 0;
+}
+
+static int __devinit w5100_probe(struct platform_device *pdev)
+{
+ struct w5100_priv *priv;
+ struct net_device *ndev;
+ int err;
+
+ ndev = alloc_etherdev(sizeof(*priv));
+ if (!ndev)
+ return -ENOMEM;
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ platform_set_drvdata(pdev, ndev);
+ priv = netdev_priv(ndev);
+ priv->ndev = ndev;
+
+ ether_setup(ndev);
+ ndev->netdev_ops = &w5100_netdev_ops;
+ ndev->ethtool_ops = &w5100_ethtool_ops;
+ ndev->watchdog_timeo = HZ;
+ netif_napi_add(ndev, &priv->napi, w5100_napi_poll, 16);
+
+ /* This chip doesn't support VLAN packets with normal MTU,
+ * so disable VLAN for this device.
+ */
+ ndev->features |= NETIF_F_VLAN_CHALLENGED;
+
+ err = register_netdev(ndev);
+ if (err < 0)
+ goto err_register;
+
+ err = w5100_hw_probe(pdev);
+ if (err < 0)
+ goto err_hw_probe;
+
+ return 0;
+
+err_hw_probe:
+ unregister_netdev(ndev);
+err_register:
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+ return err;
+}
+
+static int __devexit w5100_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ unregister_netdev(ndev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int w5100_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ if (netif_running(ndev)) {
+ netif_carrier_off(ndev);
+ netif_device_detach(ndev);
+
+ w5100_hw_close(priv);
+ }
+ return 0;
+}
+
+static int w5100_resume(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5100_priv *priv = netdev_priv(ndev);
+
+ if (netif_running(ndev)) {
+ w5100_hw_reset(priv);
+ w5100_hw_start(priv);
+
+ netif_device_attach(ndev);
+ if (!gpio_is_valid(priv->link_gpio) ||
+ gpio_get_value(priv->link_gpio) != 0)
+ netif_carrier_on(ndev);
+ }
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static SIMPLE_DEV_PM_OPS(w5100_pm_ops, w5100_suspend, w5100_resume);
+
+static struct platform_driver w5100_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &w5100_pm_ops,
+ },
+ .probe = w5100_probe,
+ .remove = __devexit_p(w5100_remove),
+};
+
+module_platform_driver(w5100_driver);
--
1.6.3.3
^ permalink raw reply related
* [PATCH v7 1/2] Ethernet driver for the WIZnet W5300 chip
From: Mike Sinkovsky @ 2012-04-04 7:23 UTC (permalink / raw)
To: netdev, linux-kernel, eric.dumazet; +Cc: Mike Sinkovsky
In-Reply-To: <1333450726-24455-1-git-send-email-msink@permonline.ru>
Based on original driver from chip manufacturer, but nearly full rewite.
Tested and used in production with Blackfin BF531 embedded processor.
Signed-off-by: Mike Sinkovsky <msink@permonline.ru>
---
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/wiznet/Kconfig | 64 +++
drivers/net/ethernet/wiznet/Makefile | 1 +
drivers/net/ethernet/wiznet/w5300.c | 715 ++++++++++++++++++++++++++++++++++
include/linux/platform_data/wiznet.h | 24 ++
6 files changed, 806 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/ethernet/wiznet/Kconfig
create mode 100644 drivers/net/ethernet/wiznet/Makefile
create mode 100644 drivers/net/ethernet/wiznet/w5300.c
create mode 100644 include/linux/platform_data/wiznet.h
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index c63a64c..a11af5c 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -174,6 +174,7 @@ source "drivers/net/ethernet/tile/Kconfig"
source "drivers/net/ethernet/toshiba/Kconfig"
source "drivers/net/ethernet/tundra/Kconfig"
source "drivers/net/ethernet/via/Kconfig"
+source "drivers/net/ethernet/wiznet/Kconfig"
source "drivers/net/ethernet/xilinx/Kconfig"
source "drivers/net/ethernet/xircom/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 9676a51..878ad32 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -73,5 +73,6 @@ obj-$(CONFIG_TILE_NET) += tile/
obj-$(CONFIG_NET_VENDOR_TOSHIBA) += toshiba/
obj-$(CONFIG_NET_VENDOR_TUNDRA) += tundra/
obj-$(CONFIG_NET_VENDOR_VIA) += via/
+obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/
obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
diff --git a/drivers/net/ethernet/wiznet/Kconfig b/drivers/net/ethernet/wiznet/Kconfig
new file mode 100644
index 0000000..364292b
--- /dev/null
+++ b/drivers/net/ethernet/wiznet/Kconfig
@@ -0,0 +1,64 @@
+#
+# WIZnet devices configuration
+#
+
+config NET_VENDOR_WIZNET
+ bool "WIZnet devices"
+ default y
+ ---help---
+ If you have a network (Ethernet) card belonging to this class, say Y
+ and read the Ethernet-HOWTO, available from
+ <http://www.tldp.org/docs.html#howto>.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about WIZnet devices. If you say Y, you will be asked
+ for your specific card in the following questions.
+
+if NET_VENDOR_WIZNET
+
+config WIZNET_W5300
+ tristate "WIZnet W5300 Ethernet support"
+ ---help---
+ Support for WIZnet W5300 chips.
+
+ W5300 is a single chip with integrated 10/100 Ethernet MAC,
+ PHY and hardware TCP/IP stack, but this driver is limited to
+ the MAC and PHY functions only, onchip TCP/IP is unused.
+
+ To compile this driver as a module, choose M here: the module
+ will be called w5300.
+
+choice
+ prompt "WIZnet interface mode"
+ default WIZNET_BUS_ANY
+
+config WIZNET_BUS_DIRECT
+ bool "Direct address bus mode"
+ ---help---
+ In direct address mode host system can directly access all registers
+ after mapping to Memory-Mapped I/O space.
+
+config WIZNET_BUS_INDIRECT
+ bool "Indirect address bus mode"
+ ---help---
+ In indirect address mode host system indirectly accesses registers
+ using Indirect Mode Address Register and Indirect Mode Data Register,
+ which are directly mapped to Memory-Mapped I/O space.
+
+config WIZNET_BUS_ANY
+ bool "Select interface mode in runtime"
+ ---help---
+ If interface mode is unknown in compile time, it can be selected
+ in runtime from board/platform resources configuration.
+
+ Performance may decrease compared to explicitly selected bus mode.
+endchoice
+
+config WIZNET_TX_FLOW
+ bool "Use transmit flow control"
+ help
+ This enables transmit flow control for WIZnet chips.
+ If unsure, say Y.
+
+endif # NET_VENDOR_WIZNET
diff --git a/drivers/net/ethernet/wiznet/Makefile b/drivers/net/ethernet/wiznet/Makefile
new file mode 100644
index 0000000..88e0a3e
--- /dev/null
+++ b/drivers/net/ethernet/wiznet/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_WIZNET_W5300) += w5300.o
diff --git a/drivers/net/ethernet/wiznet/w5300.c b/drivers/net/ethernet/wiznet/w5300.c
new file mode 100644
index 0000000..5653ce8
--- /dev/null
+++ b/drivers/net/ethernet/wiznet/w5300.c
@@ -0,0 +1,715 @@
+/*
+ * Ethernet driver for the WIZnet W5300 chip.
+ *
+ * Copyright (C) 2008-2009 WIZnet Co.,Ltd.
+ * Copyright (C) 2011 Taehun Kim <kth3321 <at> gmail.com>
+ * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/kconfig.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/wiznet.h>
+#include <linux/ethtool.h>
+#include <linux/skbuff.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+
+#define DRV_NAME "w5300"
+#define DRV_VERSION "2012-04-04"
+
+MODULE_DESCRIPTION("WIZnet W5300 Ethernet driver v"DRV_VERSION);
+MODULE_AUTHOR("Mike Sinkovsky <msink@permonline.ru>");
+MODULE_ALIAS("platform:"DRV_NAME);
+MODULE_LICENSE("GPL");
+
+/*
+ * Registers
+ */
+#define W5300_MR 0x0000 /* Mode Register */
+#define MR_DBW (1 << 15) /* Data bus width */
+#define MR_MPF (1 << 14) /* Mac layer pause frame */
+#define MR_WDF(n) (((n)&7)<<11) /* Write data fetch time */
+#define MR_RDH (1 << 10) /* Read data hold time */
+#define MR_FS (1 << 8) /* FIFO swap */
+#define MR_RST (1 << 7) /* S/W reset */
+#define MR_PB (1 << 4) /* Ping block */
+#define MR_DBS (1 << 2) /* Data bus swap */
+#define MR_IND (1 << 0) /* Indirect mode */
+#define W5300_IR 0x0002 /* Interrupt Register */
+#define W5300_IMR 0x0004 /* Interrupt Mask Register */
+#define IR_S0 0x0001 /* S0 interrupt */
+#define W5300_SHARL 0x0008 /* Source MAC address (0123) */
+#define W5300_SHARH 0x000c /* Source MAC address (45) */
+#define W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */
+#define W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */
+#define W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */
+#define W5300_RMSRH 0x002c /* Receive Memory Size (4567) */
+#define W5300_MTYPE 0x0030 /* Memory Type */
+#define W5300_IDR 0x00fe /* Chip ID register */
+#define IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */
+#define W5300_S0_MR 0x0200 /* S0 Mode Register */
+#define S0_MR_CLOSED 0x0000 /* Close mode */
+#define S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscous) */
+#define S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */
+#define W5300_S0_CR 0x0202 /* S0 Command Register */
+#define S0_CR_OPEN 0x0001 /* OPEN command */
+#define S0_CR_CLOSE 0x0010 /* CLOSE command */
+#define S0_CR_SEND 0x0020 /* SEND command */
+#define S0_CR_RECV 0x0040 /* RECV command */
+#define W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */
+#define W5300_S0_IR 0x0206 /* S0 Interrupt Register */
+#define S0_IR_RECV 0x0004 /* Receive interrupt */
+#define S0_IR_SENDOK 0x0010 /* Send OK interrupt */
+#define W5300_S0_SSR 0x0208 /* S0 Socket Status Register */
+#define W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */
+#define W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */
+#define W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */
+#define W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */
+#define W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */
+#define W5300_REGS_LEN 0x0400
+
+/*
+ * Device driver private data structure
+ */
+struct w5300_priv {
+ void __iomem *base;
+ spinlock_t reg_lock;
+ bool indirect;
+ u16 (*read) (struct w5300_priv *priv, u16 addr);
+ void (*write)(struct w5300_priv *priv, u16 addr, u16 data);
+ int irq;
+ int link_irq;
+ int link_gpio;
+
+ struct napi_struct napi;
+ struct net_device *ndev;
+ bool promisc;
+ u32 msg_enable;
+};
+
+/************************************************************************
+ *
+ * Lowlevel I/O functions
+ *
+ ***********************************************************************/
+
+/*
+ * In direct address mode host system can directly access W5300 registers
+ * after mapping to Memory-Mapped I/O space.
+ *
+ * 0x400 bytes are required for memory space.
+ */
+static inline u16 w5300_read_direct(struct w5300_priv *priv, u16 addr)
+{
+ return ioread16(priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
+}
+
+static inline void w5300_write_direct(struct w5300_priv *priv,
+ u16 addr, u16 data)
+{
+ iowrite16(data, priv->base + (addr << CONFIG_WIZNET_BUS_SHIFT));
+}
+
+/*
+ * In indirect address mode host system indirectly accesses registers by
+ * using Indirect Mode Address Register (IDM_AR) and Indirect Mode Data
+ * Register (IDM_DR), which are directly mapped to Memory-Mapped I/O space.
+ * Mode Register (MR) is directly accessible.
+ *
+ * Only 0x06 bytes are required for memory space.
+ */
+#define W5300_IDM_AR 0x0002 /* Indirect Mode Address */
+#define W5300_IDM_DR 0x0004 /* Indirect Mode Data */
+
+static u16 w5300_read_indirect(struct w5300_priv *priv, u16 addr)
+{
+ unsigned long flags;
+ u16 data;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5300_write_direct(priv, W5300_IDM_AR, addr);
+ mmiowb();
+ data = w5300_read_direct(priv, W5300_IDM_DR);
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+
+ return data;
+}
+
+static void w5300_write_indirect(struct w5300_priv *priv, u16 addr, u16 data)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->reg_lock, flags);
+ w5300_write_direct(priv, W5300_IDM_AR, addr);
+ mmiowb();
+ w5300_write_direct(priv, W5300_IDM_DR, data);
+ mmiowb();
+ spin_unlock_irqrestore(&priv->reg_lock, flags);
+}
+
+#if defined(CONFIG_WIZNET_BUS_DIRECT)
+#define w5300_read w5300_read_direct
+#define w5300_write w5300_write_direct
+
+#elif defined(CONFIG_WIZNET_BUS_INDIRECT)
+#define w5300_read w5300_read_indirect
+#define w5300_write w5300_write_indirect
+
+#else /* CONFIG_WIZNET_BUS_ANY */
+#define w5300_read priv->read
+#define w5300_write priv->write
+#endif
+
+static u32 w5300_read32(struct w5300_priv *priv, u16 addr)
+{
+ u32 data;
+ data = w5300_read(priv, addr) << 16;
+ data |= w5300_read(priv, addr + 2);
+ return data;
+}
+
+static void w5300_write32(struct w5300_priv *priv, u16 addr, u32 data)
+{
+ w5300_write(priv, addr, data >> 16);
+ w5300_write(priv, addr + 2, data);
+}
+
+static int w5300_command(struct w5300_priv *priv, u16 cmd)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(100);
+
+ w5300_write(priv, W5300_S0_CR, cmd);
+ mmiowb();
+
+ while (w5300_read(priv, W5300_S0_CR) != 0) {
+ if (time_after(jiffies, timeout))
+ return -EIO;
+ cpu_relax();
+ }
+
+ return 0;
+}
+
+static void w5300_read_frame(struct w5300_priv *priv, u8 *buf, int len)
+{
+ u16 fifo;
+ int i;
+
+ for (i = 0; i < len; i += 2) {
+ fifo = w5300_read(priv, W5300_S0_RX_FIFO);
+ *buf++ = fifo >> 8;
+ *buf++ = fifo;
+ }
+ fifo = w5300_read(priv, W5300_S0_RX_FIFO);
+ fifo = w5300_read(priv, W5300_S0_RX_FIFO);
+}
+
+static void w5300_write_frame(struct w5300_priv *priv, u8 *buf, int len)
+{
+ u16 fifo;
+ int i;
+
+ for (i = 0; i < len; i += 2) {
+ fifo = *buf++ << 8;
+ fifo |= *buf++;
+ w5300_write(priv, W5300_S0_TX_FIFO, fifo);
+ }
+ w5300_write32(priv, W5300_S0_TX_WRSR, len);
+}
+
+static void w5300_write_macaddr(struct w5300_priv *priv)
+{
+ struct net_device *ndev = priv->ndev;
+ w5300_write32(priv, W5300_SHARL,
+ ndev->dev_addr[0] << 24 |
+ ndev->dev_addr[1] << 16 |
+ ndev->dev_addr[2] << 8 |
+ ndev->dev_addr[3]);
+ w5300_write(priv, W5300_SHARH,
+ ndev->dev_addr[4] << 8 |
+ ndev->dev_addr[5]);
+ mmiowb();
+}
+
+static void w5300_hw_reset(struct w5300_priv *priv)
+{
+ w5300_write_direct(priv, W5300_MR, MR_RST);
+ mmiowb();
+ mdelay(5);
+ w5300_write_direct(priv, W5300_MR, priv->indirect ?
+ MR_WDF(7) | MR_PB | MR_IND :
+ MR_WDF(7) | MR_PB);
+ mmiowb();
+ w5300_write(priv, W5300_IMR, 0);
+ w5300_write_macaddr(priv);
+
+ /* Configure 128K of internal memory
+ * as 64K RX fifo and 64K TX fifo
+ */
+ w5300_write32(priv, W5300_RMSRL, 64 << 24);
+ w5300_write32(priv, W5300_RMSRH, 0);
+ w5300_write32(priv, W5300_TMSRL, 64 << 24);
+ w5300_write32(priv, W5300_TMSRH, 0);
+ w5300_write(priv, W5300_MTYPE, 0x00ff);
+ mmiowb();
+}
+
+static void w5300_hw_start(struct w5300_priv *priv)
+{
+ w5300_write(priv, W5300_S0_MR, priv->promisc ?
+ S0_MR_MACRAW : S0_MR_MACRAW_MF);
+ mmiowb();
+ w5300_command(priv, S0_CR_OPEN);
+ w5300_write(priv, W5300_S0_IMR, IS_ENABLED(CONFIG_WIZNET_TX_FLOW) ?
+ S0_IR_RECV | S0_IR_SENDOK:
+ S0_IR_RECV);
+ w5300_write(priv, W5300_IMR, IR_S0);
+ mmiowb();
+}
+
+static void w5300_hw_close(struct w5300_priv *priv)
+{
+ w5300_write(priv, W5300_IMR, 0);
+ mmiowb();
+ w5300_command(priv, S0_CR_CLOSE);
+}
+
+/***********************************************************************
+ *
+ * Device driver functions / callbacks
+ *
+ ***********************************************************************/
+
+static void w5300_get_drvinfo(struct net_device *ndev,
+ struct ethtool_drvinfo *info)
+{
+ strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
+ strlcpy(info->version, DRV_VERSION, sizeof(info->version));
+ strlcpy(info->bus_info, dev_name(ndev->dev.parent),
+ sizeof(info->bus_info));
+}
+
+static u32 w5300_get_link(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ if (gpio_is_valid(priv->link_gpio))
+ return !!gpio_get_value(priv->link_gpio);
+
+ return 1;
+}
+
+static u32 w5300_get_msglevel(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ return priv->msg_enable;
+}
+
+static void w5300_set_msglevel(struct net_device *ndev, u32 value)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ priv->msg_enable = value;
+}
+
+static int w5300_get_regs_len(struct net_device *ndev)
+{
+ return W5300_REGS_LEN;
+}
+
+static void w5300_get_regs(struct net_device *ndev,
+ struct ethtool_regs *regs, void *_buf)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+ u8 *buf = _buf;
+ u16 addr;
+ u16 data;
+
+ regs->version = 1;
+ for (addr = 0; addr < W5300_REGS_LEN; addr += 2) {
+ switch (addr & 0x23f) {
+ case W5300_S0_TX_FIFO: /* cannot read TX_FIFO */
+ case W5300_S0_RX_FIFO: /* cannot read RX_FIFO */
+ data = 0xffff;
+ break;
+ default:
+ data = w5300_read(priv, addr);
+ break;
+ }
+ *buf++ = data >> 8;
+ *buf++ = data;
+ }
+}
+
+static void w5300_tx_timeout(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ netif_stop_queue(ndev);
+ w5300_hw_reset(priv);
+ w5300_hw_start(priv);
+ ndev->stats.tx_errors++;
+ ndev->trans_start = jiffies;
+ netif_wake_queue(ndev);
+}
+
+static int w5300_start_tx(struct sk_buff *skb, struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW))
+ netif_stop_queue(ndev);
+
+ w5300_write_frame(priv, skb->data, skb->len);
+ mmiowb();
+ ndev->stats.tx_packets++;
+ ndev->stats.tx_bytes += skb->len;
+ dev_kfree_skb(skb);
+ netif_dbg(priv, tx_queued, ndev, "tx queued\n");
+
+ w5300_command(priv, S0_CR_SEND);
+
+ return NETDEV_TX_OK;
+}
+
+static int w5300_napi_poll(struct napi_struct *napi, int budget)
+{
+ struct w5300_priv *priv = container_of(napi, struct w5300_priv, napi);
+ struct net_device *ndev = priv->ndev;
+ struct sk_buff *skb;
+ int rx_count;
+ u16 rx_len;
+
+ for (rx_count = 0; rx_count < budget; rx_count++) {
+ u32 rx_fifo_len = w5300_read32(priv, W5300_S0_RX_RSR);
+ if (rx_fifo_len == 0)
+ break;
+
+ rx_len = w5300_read(priv, W5300_S0_RX_FIFO);
+
+ skb = netdev_alloc_skb_ip_align(ndev, roundup(rx_len, 2));
+ if (unlikely(!skb)) {
+ u32 i;
+ for (i = 0; i < rx_fifo_len; i += 2)
+ w5300_read(priv, W5300_S0_RX_FIFO);
+ ndev->stats.rx_dropped++;
+ return -ENOMEM;
+ }
+
+ skb_put(skb, rx_len);
+ w5300_read_frame(priv, skb->data, rx_len);
+ skb->protocol = eth_type_trans(skb, ndev);
+
+ netif_receive_skb(skb);
+ ndev->stats.rx_packets++;
+ ndev->stats.rx_bytes += rx_len;
+ }
+
+ if (rx_count < budget) {
+ w5300_write(priv, W5300_IMR, IR_S0);
+ mmiowb();
+ napi_complete(napi);
+ }
+
+ return rx_count;
+}
+
+static irqreturn_t w5300_interrupt(int irq, void *ndev_instance)
+{
+ struct net_device *ndev = ndev_instance;
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ int ir = w5300_read(priv, W5300_S0_IR);
+ if (!ir)
+ return IRQ_NONE;
+ w5300_write(priv, W5300_S0_IR, ir);
+ mmiowb();
+
+ if (IS_ENABLED(CONFIG_WIZNET_TX_FLOW) && (ir & S0_IR_SENDOK)) {
+ netif_dbg(priv, tx_done, ndev, "tx done\n");
+ netif_wake_queue(ndev);
+ }
+
+ if (ir & S0_IR_RECV) {
+ if (napi_schedule_prep(&priv->napi)) {
+ w5300_write(priv, W5300_IMR, 0);
+ mmiowb();
+ __napi_schedule(&priv->napi);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t w5300_detect_link(int irq, void *ndev_instance)
+{
+ struct net_device *ndev = ndev_instance;
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ if (netif_running(ndev)) {
+ if (gpio_get_value(priv->link_gpio) != 0) {
+ netif_info(priv, link, ndev, "link is up\n");
+ netif_carrier_on(ndev);
+ } else {
+ netif_info(priv, link, ndev, "link is down\n");
+ netif_carrier_off(ndev);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void w5300_set_rx_mode(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+ bool set_promisc = (ndev->flags & IFF_PROMISC) != 0;
+
+ if (priv->promisc != set_promisc) {
+ priv->promisc = set_promisc;
+ w5300_hw_start(priv);
+ }
+}
+
+static int w5300_set_macaddr(struct net_device *ndev, void *addr)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+ struct sockaddr *sock_addr = addr;
+
+ if (!is_valid_ether_addr(sock_addr->sa_data))
+ return -EADDRNOTAVAIL;
+ memcpy(ndev->dev_addr, sock_addr->sa_data, ETH_ALEN);
+ ndev->addr_assign_type &= ~NET_ADDR_RANDOM;
+ w5300_write_macaddr(priv);
+ return 0;
+}
+
+static int w5300_open(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ netif_info(priv, ifup, ndev, "enabling\n");
+ if (!is_valid_ether_addr(ndev->dev_addr))
+ return -EINVAL;
+ w5300_hw_start(priv);
+ napi_enable(&priv->napi);
+ netif_start_queue(ndev);
+ if (!gpio_is_valid(priv->link_gpio) ||
+ gpio_get_value(priv->link_gpio) != 0)
+ netif_carrier_on(ndev);
+ return 0;
+}
+
+static int w5300_stop(struct net_device *ndev)
+{
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ netif_info(priv, ifdown, ndev, "shutting down\n");
+ w5300_hw_close(priv);
+ netif_carrier_off(ndev);
+ netif_stop_queue(ndev);
+ napi_disable(&priv->napi);
+ return 0;
+}
+
+static const struct ethtool_ops w5300_ethtool_ops = {
+ .get_drvinfo = w5300_get_drvinfo,
+ .get_msglevel = w5300_get_msglevel,
+ .set_msglevel = w5300_set_msglevel,
+ .get_link = w5300_get_link,
+ .get_regs_len = w5300_get_regs_len,
+ .get_regs = w5300_get_regs,
+};
+
+static const struct net_device_ops w5300_netdev_ops = {
+ .ndo_open = w5300_open,
+ .ndo_stop = w5300_stop,
+ .ndo_start_xmit = w5300_start_tx,
+ .ndo_tx_timeout = w5300_tx_timeout,
+ .ndo_set_rx_mode = w5300_set_rx_mode,
+ .ndo_set_mac_address = w5300_set_macaddr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+};
+
+static int __devinit w5300_hw_probe(struct platform_device *pdev)
+{
+ struct wiznet_platform_data *data = pdev->dev.platform_data;
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5300_priv *priv = netdev_priv(ndev);
+ const char *name = netdev_name(ndev);
+ struct resource *mem;
+ int mem_size;
+ int irq;
+ int ret;
+
+ if (data && is_valid_ether_addr(data->mac_addr)) {
+ memcpy(ndev->dev_addr, data->mac_addr, ETH_ALEN);
+ } else {
+ random_ether_addr(ndev->dev_addr);
+ ndev->addr_assign_type |= NET_ADDR_RANDOM;
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem)
+ return -ENXIO;
+ mem_size = resource_size(mem);
+ if (!devm_request_mem_region(&pdev->dev, mem->start, mem_size, name))
+ return -EBUSY;
+ priv->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
+ if (!priv->base)
+ return -EBUSY;
+
+ spin_lock_init(&priv->reg_lock);
+ priv->indirect = mem_size < W5300_BUS_DIRECT_SIZE;
+ if (priv->indirect) {
+ priv->read = w5300_read_indirect;
+ priv->write = w5300_write_indirect;
+ } else {
+ priv->read = w5300_read_direct;
+ priv->write = w5300_write_direct;
+ }
+
+ w5300_hw_reset(priv);
+ if (w5300_read(priv, W5300_IDR) != IDR_W5300)
+ return -ENODEV;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+ ret = devm_request_irq(&pdev->dev, irq, w5300_interrupt,
+ IRQ_TYPE_LEVEL_LOW, name, ndev);
+ if (ret < 0)
+ return ret;
+ priv->irq = irq;
+
+ priv->link_gpio = data->link_gpio;
+ if (gpio_is_valid(priv->link_gpio)) {
+ char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
+ if (!link_name)
+ return -ENOMEM;
+ snprintf(link_name, 16, "%s-link", name);
+ priv->link_irq = gpio_to_irq(priv->link_gpio);
+ if (devm_request_threaded_irq(&pdev->dev,
+ priv->link_irq, NULL, w5300_detect_link,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ link_name, priv->ndev) < 0)
+ priv->link_gpio = -EINVAL;
+ }
+
+ netdev_info(ndev, "at 0x%llx irq %d\n", (u64)mem->start, irq);
+ return 0;
+}
+
+static int __devinit w5300_probe(struct platform_device *pdev)
+{
+ struct w5300_priv *priv;
+ struct net_device *ndev;
+ int err;
+
+ ndev = alloc_etherdev(sizeof(*priv));
+ if (!ndev)
+ return -ENOMEM;
+ SET_NETDEV_DEV(ndev, &pdev->dev);
+ platform_set_drvdata(pdev, ndev);
+ priv = netdev_priv(ndev);
+ priv->ndev = ndev;
+
+ ether_setup(ndev);
+ ndev->netdev_ops = &w5300_netdev_ops;
+ ndev->ethtool_ops = &w5300_ethtool_ops;
+ ndev->watchdog_timeo = HZ;
+ netif_napi_add(ndev, &priv->napi, w5300_napi_poll, 16);
+
+ /* This chip doesn't support VLAN packets with normal MTU,
+ * so disable VLAN for this device.
+ */
+ ndev->features |= NETIF_F_VLAN_CHALLENGED;
+
+ err = register_netdev(ndev);
+ if (err < 0)
+ goto err_register;
+
+ err = w5300_hw_probe(pdev);
+ if (err < 0)
+ goto err_hw_probe;
+
+ return 0;
+
+err_hw_probe:
+ unregister_netdev(ndev);
+err_register:
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+ return err;
+}
+
+static int __devexit w5300_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+ unregister_netdev(ndev);
+ free_netdev(ndev);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int w5300_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ if (netif_running(ndev)) {
+ netif_carrier_off(ndev);
+ netif_device_detach(ndev);
+
+ w5300_hw_close(priv);
+ }
+ return 0;
+}
+
+static int w5300_resume(struct platform_device *pdev)
+{
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct w5300_priv *priv = netdev_priv(ndev);
+
+ if (!netif_running(ndev)) {
+ w5300_hw_reset(priv);
+ w5300_hw_start(priv);
+
+ netif_device_attach(ndev);
+ if (!gpio_is_valid(priv->link_gpio) ||
+ gpio_get_value(priv->link_gpio) != 0)
+ netif_carrier_on(ndev);
+ }
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static SIMPLE_DEV_PM_OPS(w5300_pm_ops, w5300_suspend, w5300_resume);
+
+static struct platform_driver w5300_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &w5300_pm_ops,
+ },
+ .probe = w5300_probe,
+ .remove = __devexit_p(w5300_remove),
+};
+
+module_platform_driver(w5300_driver);
diff --git a/include/linux/platform_data/wiznet.h b/include/linux/platform_data/wiznet.h
new file mode 100644
index 0000000..b5d8c19
--- /dev/null
+++ b/include/linux/platform_data/wiznet.h
@@ -0,0 +1,24 @@
+/*
+ * Ethernet driver for the WIZnet W5x00 chip.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef PLATFORM_DATA_WIZNET_H
+#define PLATFORM_DATA_WIZNET_H
+
+#include <linux/if_ether.h>
+
+struct wiznet_platform_data {
+ int link_gpio;
+ u8 mac_addr[ETH_ALEN];
+};
+
+#ifndef CONFIG_WIZNET_BUS_SHIFT
+#define CONFIG_WIZNET_BUS_SHIFT 0
+#endif
+
+#define W5100_BUS_DIRECT_SIZE (0x8000 << CONFIG_WIZNET_BUS_SHIFT)
+#define W5300_BUS_DIRECT_SIZE (0x0400 << CONFIG_WIZNET_BUS_SHIFT)
+
+#endif /* PLATFORM_DATA_WIZNET_H */
--
1.6.3.3
^ permalink raw reply related
* [PATCH v7 0/2] Ethernet drivers for WIZnet chips
From: Mike Sinkovsky @ 2012-04-04 7:23 UTC (permalink / raw)
To: netdev, linux-kernel, eric.dumazet; +Cc: Mike Sinkovsky
In-Reply-To: <1333450726-24455-1-git-send-email-msink@permonline.ru>
Based on original driver from chip manufacturer, but nearly full rewite.
Tested and used in production with Blackfin BF531 embedded processor.
Signed-off-by: Mike Sinkovsky <msink@permonline.ru>
---
v7:
- new tx flow control, configurable from Kconfig
v6:
- remove (S0_TX_FSR < skb->len) check in TX handler, it doesn't work
anyway. Chip can transmit only one frame with MTU 1500 at a time,
and tx buffer size is bigger.
- move link_gpio from RES_IO resource to wiznet_platform_data
- remove dependency (ARM || BLACKFIN) - should work on any arch
- interrupt handler returns IRQ_NONE if status register is zero
- use devm_request_threaded_irq for request detect_link handler
- remove dev_info if probe failed
v5:
- added driver for WIZnet W5100
- disabled VLAN (NETIF_F_VLAN_CHALLENGED)
v4:
- netif_stop_queue if tx fifo is full, netif_wake_queue in interrupt
- use netif_info macro
v3:
- reading macaddr from platform_data
- ethtool: get_link, get_msglevel, set_msglevel
- more cleanups
v2:
- corrected handling of NET_ADDR_RANDOM flag
- support for WIZNET_BUS_ANY mode
- link detection using gpio
- registers read using ethtool
- more cleanups
^ permalink raw reply
* Re: [PATCH] stmmac: re-add IFF_UNICAST_FLT for dwmac1000
From: Giuseppe CAVALLARO @ 2012-04-04 6:59 UTC (permalink / raw)
To: Marc Kleine-Budde; +Cc: rayagond, netdev
In-Reply-To: <1333475057-3752-1-git-send-email-mkl@pengutronix.de>
On 4/3/2012 7:44 PM, Marc Kleine-Budde wrote:
> In commit (bfab27a stmmac: add the experimental PCI support) the
I get another patch associated to this commit:
git show db8857b
commit db8857bf5bd888d763e1984f9449d0b824b39ee1
Author: Florian Fainelli <florian@openwrt.org>
Date: Mon Jan 9 23:59:20 2012 +0000
stmmac: use an unique MDIO bus name.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
maybe, the commit should be:
git-show bfab27a14
commit bfab27a146ed4d722c6d399f844f955f29cd2b81
Author: Giuseppe CAVALLARO <peppe.cavallaro@st.com>
Date: Wed Dec 21 03:58:19 2011 +0000
stmmac: add the experimental PCI support
> IFF_UNICAST_FLT flag has been removed from the stmmac_mac_device_setup()
> function. This patch re-adds the flag.
Yes this flag was removed by this PCI patch.
So it makes sense to re-add it!
> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>
> Just compile time tested, since I don't have the hardware.
> Applies to net-next/master (and v3.3).
>
> regards, Marc
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++--
> 1 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index e85ffbd..07e0c78 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -1737,9 +1737,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
> struct mac_device_info *mac;
>
> /* Identify the MAC HW device */
> - if (priv->plat->has_gmac)
> + if (priv->plat->has_gmac) {
> + priv->dev->priv_flags |= IFF_UNICAST_FLT;
> mac = dwmac1000_setup(priv->ioaddr);
> - else
> + } else
> mac = dwmac100_setup(priv->ioaddr);
> if (!mac)
> return -ENOMEM;
^ permalink raw reply
* Re: [PATCH] tcp: allow splice() to build full TSO packets
From: David Miller @ 2012-04-04 6:20 UTC (permalink / raw)
To: eric.dumazet
Cc: netdev, ncardwell, therbert, ycheng, hkchu, maze, maheshb,
ilpo.jarvinen, nanditad
In-Reply-To: <1333520128.18626.382.camel@edumazet-glaptop>
From: Eric Dumazet <eric.dumazet@gmail.com>
Date: Wed, 04 Apr 2012 08:15:28 +0200
> On Tue, 2012-04-03 at 18:50 -0400, David Miller wrote:
>
>> Eric, sorry to be a pain, but to clear my conscience can you tell me
>> if the sendfile() path do the right thing with your change too?
>>
>> I'm concerned about returning back into userspace without at least
>> one tcp_push() at the end.
>
> Absolutely, this patch also handles the sendfile() path.
>
> do_sendfile() ->
> do_splice_direct() ->
> splice_direct_to_actor() ->
> ...
> splice_from_pipe() ->
> splice_from_pipe_feed() ->
> pipe_to_sendpage() more = (sd->flags & SPLICE_F_MORE) || sd->len < sd->total_len
> sock_sendpage() if (more) flags |= MSG_MORE;
> kernel_sendpage()
> inet_sendpage()
> tcp_sendpage()
>
> So the push is perfomed at the end (last page doesnt have MSG_MORE flag)
Perfect, thanks for double checking.
^ permalink raw reply
* Re: [PATCH v6 1/2] Ethernet driver for the WIZnet W5300 chip
From: Mike Sinkovsky @ 2012-04-04 6:18 UTC (permalink / raw)
To: Mark Brown; +Cc: netdev, linux-kernel
In-Reply-To: <20120403133619.GA3960@sirena.org.uk>
03.04.2012 19:36, Mark Brown написал:
> On Tue, Apr 03, 2012 at 04:58:45PM +0600, Mike Sinkovsky wrote:
>
>> +static irqreturn_t w5300_detect_link(int irq, void *ndev_instance)
>> +{
>> + struct net_device *ndev = ndev_instance;
>> + struct w5300_priv *priv = netdev_priv(ndev);
>> +
>> + if (netif_running(ndev)) {
>> + if (gpio_get_value(priv->link_gpio) != 0) {
>> + netif_info(priv, link, ndev, "link is up\n");
>> + netif_carrier_on(ndev);
>> + } else {
>> + netif_info(priv, link, ndev, "link is down\n");
>> + netif_carrier_off(ndev);
>> + }
>> + }
>> +
>> + return IRQ_HANDLED;
>> +}
>
> This relies on ndev being valid and on the gpio being requested but...
>
>> + priv->link_gpio = data->link_gpio;
>> + if (gpio_is_valid(priv->link_gpio)) {
>> + char *link_name = devm_kzalloc(&pdev->dev, 16, GFP_KERNEL);
>> + if (!link_name)
>> + return -ENOMEM;
>> + snprintf(link_name, 16, "%s-link", name);
>> + priv->link_irq = gpio_to_irq(priv->link_gpio);
>> + if (devm_request_threaded_irq(&pdev->dev,
>> + priv->link_irq, NULL, w5300_detect_link,
>> + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
>> + link_name, priv->ndev)< 0)
>> + priv->link_gpio = -EINVAL;
>> + }
>
> ...you use devm_request_threaded_irq() here and rely on it for cleanup.
> Are you sure there's no possibility of the interrupt firing after you
> start to tear down the device?
>
> By using a specifically threaded IRQ you're also adding a performance
> overhead for no good reason if you can call netdev_carrier_*() from IRQ
> context and the GPIO is capable of generating a hard IRQ. If you use
> request_any_context_irq() instead then the driver will get a hard IRQ if
> that's supported.
There isn't devm* variant of request_any_context_irq(), and using plain
version looks inconsistent with other resources handling.
Anyway, this is not performance critical procedure, and latency around
100 millisecond is acceptable. Some our boards even don't have this gpio
at all, and nothing bad happens, just userspace doesn't know is carrier
on or off.
Some gpio cannot generate irq at all, and if goal is to support any - I
can easily convert this to background polling from delayed_work
procedure. If it is required for generalized mainstream driver.
--
Mike
^ permalink raw reply
* Re: [PATCH v6 0/2] Ethernet drivers for WIZnet chips
From: Eric Dumazet @ 2012-04-04 6:17 UTC (permalink / raw)
To: Mike Sinkovsky; +Cc: netdev, linux-kernel
In-Reply-To: <4F7BE30B.9020603@permonline.ru>
On Wed, 2012-04-04 at 11:58 +0600, Mike Sinkovsky wrote:
> About races - I can't see any, in this very simple procedure.
> But maybe I missed something..
Maybe post the code and we can help you.
^ permalink raw reply
* Re: [PATCH] tcp: allow splice() to build full TSO packets
From: Eric Dumazet @ 2012-04-04 6:15 UTC (permalink / raw)
To: David Miller
Cc: netdev, ncardwell, therbert, ycheng, hkchu, maze, maheshb,
ilpo.jarvinen, nanditad
In-Reply-To: <20120403.185055.1492466245744649655.davem@davemloft.net>
On Tue, 2012-04-03 at 18:50 -0400, David Miller wrote:
> Eric, sorry to be a pain, but to clear my conscience can you tell me
> if the sendfile() path do the right thing with your change too?
>
> I'm concerned about returning back into userspace without at least
> one tcp_push() at the end.
Absolutely, this patch also handles the sendfile() path.
do_sendfile() ->
do_splice_direct() ->
splice_direct_to_actor() ->
...
splice_from_pipe() ->
splice_from_pipe_feed() ->
pipe_to_sendpage() more = (sd->flags & SPLICE_F_MORE) || sd->len < sd->total_len
sock_sendpage() if (more) flags |= MSG_MORE;
kernel_sendpage()
inet_sendpage()
tcp_sendpage()
So the push is perfomed at the end (last page doesnt have MSG_MORE flag)
Here is what we got _before_ the patch using "netperf -t TCP_SENDFILE --
-m 16K"
07:50:14.097137 IP A > B: Flags [S], seq 2635999430, win 14600, options [mss 1460,sackOK,TS val 56315934 ecr 0,nop,wscale 7], length 0
07:50:14.107211 IP B > A: Flags [S.], seq 2438979637, ack 2635999431, win 14480, options [mss 1460,sackOK,TS val 56315935 ecr 56315934,nop,wscale 7], length 0
07:50:14.117318 IP A > B: Flags [.], ack 1, win 115, options [nop,nop,TS val 56315936 ecr 56315935], length 0
07:50:14.117534 IP A > B: Flags [.], seq 1:2897, ack 1, win 115, options [nop,nop,TS val 56315937 ecr 56315935], length 2896
07:50:14.117543 IP A > B: Flags [.], seq 2897:4345, ack 1, win 115, options [nop,nop,TS val 56315937 ecr 56315935], length 1448
07:50:14.127612 IP B > A: Flags [.], ack 2897, win 136, options [nop,nop,TS val 56315938 ecr 56315937], length 0
07:50:14.127618 IP B > A: Flags [.], ack 4345, win 159, options [nop,nop,TS val 56315938 ecr 56315937], length 0
07:50:14.137698 IP A > B: Flags [.], seq 4345:8689, ack 1, win 115, options [nop,nop,TS val 56315939 ecr 56315938], length 4344
07:50:14.137731 IP A > B: Flags [.], seq 8689:11585, ack 1, win 115, options [nop,nop,TS val 56315939 ecr 56315938], length 2896
07:50:14.147906 IP B > A: Flags [.], ack 8689, win 181, options [nop,nop,TS val 56315940 ecr 56315939], length 0
07:50:14.147910 IP B > A: Flags [.], ack 11585, win 204, options [nop,nop,TS val 56315940 ecr 56315939], length 0
07:50:14.158012 IP A > B: Flags [.], seq 11585:17377, ack 1, win 115, options [nop,nop,TS val 56315941 ecr 56315940], length 5792
07:50:14.158022 IP A > B: Flags [P.], seq 17377:18825, ack 1, win 115, options [nop,nop,TS val 56315941 ecr 56315940], length 1448
07:50:14.158171 IP A > B: Flags [.], seq 18825:21721, ack 1, win 115, options [nop,nop,TS val 56315941 ecr 56315940], length 2896
07:50:14.168361 IP B > A: Flags [.], ack 17377, win 227, options [nop,nop,TS val 56315942 ecr 56315941], length 0
07:50:14.168366 IP B > A: Flags [.], ack 18825, win 249, options [nop,nop,TS val 56315942 ecr 56315941], length 0
07:50:14.168424 IP B > A: Flags [.], ack 21721, win 272, options [nop,nop,TS val 56315942 ecr 56315941], length 0
07:50:14.178460 IP A > B: Flags [.], seq 21721:28961, ack 1, win 115, options [nop,nop,TS val 56315943 ecr 56315942], length 7240
07:50:14.178466 IP A > B: Flags [.], seq 28961:34753, ack 1, win 115, options [nop,nop,TS val 56315943 ecr 56315942], length 5792
07:50:14.188668 IP B > A: Flags [.], ack 28961, win 295, options [nop,nop,TS val 56315944 ecr 56315943], length 0
07:50:14.188675 IP B > A: Flags [.], ack 34753, win 317, options [nop,nop,TS val 56315944 ecr 56315943], length 0
07:50:14.198772 IP A > B: Flags [.], seq 34753:44889, ack 1, win 115, options [nop,nop,TS val 56315945 ecr 56315944], length 10136
07:50:14.198778 IP A > B: Flags [P.], seq 44889:47785, ack 1, win 115, options [nop,nop,TS val 56315945 ecr 56315944], length 2896
07:50:14.208990 IP B > A: Flags [.], ack 44889, win 340, options [nop,nop,TS val 56315946 ecr 56315945], length 0
07:50:14.208995 IP B > A: Flags [.], ack 47785, win 362, options [nop,nop,TS val 56315946 ecr 56315945], length 0
07:50:14.219081 IP A > B: Flags [.], seq 47785:60817, ack 1, win 115, options [nop,nop,TS val 56315947 ecr 56315946], length 13032
07:50:14.219090 IP A > B: Flags [.], seq 60817:68057, ack 1, win 115, options [nop,nop,TS val 56315947 ecr 56315946], length 7240
07:50:14.229357 IP B > A: Flags [.], ack 60817, win 385, options [nop,nop,TS val 56315948 ecr 56315947], length 0
07:50:14.229361 IP B > A: Flags [.], ack 68057, win 408, options [nop,nop,TS val 56315948 ecr 56315947], length 0
07:50:14.239450 IP A > B: Flags [.], seq 68057:73849, ack 1, win 115, options [nop,nop,TS val 56315949 ecr 56315948], length 5792
07:50:14.239458 IP A > B: Flags [.], seq 73849:82537, ack 1, win 115, options [nop,nop,TS val 56315949 ecr 56315948], length 8688
07:50:14.239492 IP A > B: Flags [.], seq 82537:86881, ack 1, win 115, options [nop,nop,TS val 56315949 ecr 56315948], length 4344
07:50:14.249694 IP B > A: Flags [.], ack 73849, win 430, options [nop,nop,TS val 56315950 ecr 56315949], length 0
07:50:14.249699 IP B > A: Flags [.], ack 82537, win 453, options [nop,nop,TS val 56315950 ecr 56315949], length 0
07:50:14.249753 IP B > A: Flags [.], ack 86881, win 476, options [nop,nop,TS val 56315950 ecr 56315949], length 0
07:50:14.259790 IP A > B: Flags [.], seq 86881:98465, ack 1, win 115, options [nop,nop,TS val 56315951 ecr 56315950], length 11584
07:50:14.259796 IP A > B: Flags [.], seq 98465:99913, ack 1, win 115, options [nop,nop,TS val 56315951 ecr 56315950], length 1448
07:50:14.259826 IP A > B: Flags [.], seq 99913:108601, ack 1, win 115, options [nop,nop,TS val 56315951 ecr 56315950], length 8688
07:50:14.259830 IP A > B: Flags [P.], seq 108601:112945, ack 1, win 115, options [nop,nop,TS val 56315951 ecr 56315950], length 4344
^ permalink raw reply
* Re: [PATCH v6 0/2] Ethernet drivers for WIZnet chips
From: Mike Sinkovsky @ 2012-04-04 5:58 UTC (permalink / raw)
To: Eric Dumazet; +Cc: netdev, linux-kernel
In-Reply-To: <1333456156.18626.93.camel@edumazet-glaptop>
03.04.2012 18:29, Eric Dumazet написал:
> On Tue, 2012-04-03 at 18:15 +0600, Mike Sinkovsky wrote:
>> 03.04.2012 17:39, Eric Dumazet написал:
>>> On Tue, 2012-04-03 at 16:58 +0600, Mike Sinkovsky wrote:
>>>> Based on original driver from chip manufacturer, but nearly full rewite.
>>>> Tested and used in production with Blackfin BF531 embedded processor.
>>>>
>>>> Signed-off-by: Mike Sinkovsky<msink@permonline.ru>
>>>> ---
>>>> v6:
>>>> - remove (S0_TX_FSR< skb->len) check in TX handler, it doesn't work
>>>> anyway. Chip can transmit only one frame with MTU 1500 at a time,
>>>> and tx buffer size is bigger.
>>>
>>> So what happens if XXX frames are given to start_xmit() in a flood ?
>>>
>>> You removed any flow control, how can this work ?
>>>
>>> Device has an infinite queue ?
>>
>> As I understand from datasheet, device doesn't have tx queue at all.
>> It have tx buffer, processor must save transmitted frame to it, and then
>> save SEND command to command register. When transmission completed,
>> SENDOK bit in interrupt register will be set to '1', and interrupt
>> handler will be called.
>>
>> So, according to datasheet, driver must stop queue in start_xmit()
>> routine, and wake in interrupt handler of SENDOK bit.
>> I tried this, and it basically works, but SOMETIMES, very rare, I see
>> tx_timeout().
>>
>> And without any flow control - driver works perfectly.
>> Weird, don't know why.
>
> Really this should be fixed, since your driver makes qdisc flow control
> impossible (unless adding a rate limiter like HTB/CBQ)
>
> You probably had a race on your xmit routine, and interrupt routine.
>
> You need proper synchronization : A spinlock to make this easy, or a
> smart barrier game.
I can at least make it configurable from Kconfig with default 'y', and
disable for our boards.
Would it be acceptable?
About races - I can't see any, in this very simple procedure.
But maybe I missed something..
--
Mike
^ permalink raw reply
* Re: [PATCH net-next 0/10] bnx2x: Feature (+semantic) patch series
From: David Miller @ 2012-04-04 5:38 UTC (permalink / raw)
To: yuvalmin; +Cc: netdev, eilong
In-Reply-To: <1333514492-20425-1-git-send-email-yuvalmin@broadcom.com>
From: "Yuval Mintz" <yuvalmin@broadcom.com>
Date: Wed, 4 Apr 2012 07:41:22 +0300
> This patch series contains several patch, some of them semantic in
> nature (removing dead code, fixing styling issues), while others
> include new features, such as support for the new 57811 device and
> remote fault detection.
>
> Please consider applying this patch series to 'net-next'.
All applied, thanks.
Although I wonder about that intx thing. I thought that at
some point it was agreed that the generic PCI code should
bring devices up in INTX mode so that this can be relied
upon in the drivers.
Or I could be mis-remembering :-)
^ permalink raw reply
* Re: [PATCH V3 net-next 00/28] ethtool: support time stamping and phc clocks
From: David Miller @ 2012-04-04 5:36 UTC (permalink / raw)
To: richardcochran
Cc: mporter, e1000-devel, netdev, jacob.e.keller, john.ronciak,
bhutchings
In-Reply-To: <20120404051431.GA3328@netboy.at.omicron.at>
From: Richard Cochran <richardcochran@gmail.com>
Date: Wed, 4 Apr 2012 07:14:32 +0200
> On Tue, Apr 03, 2012 at 04:25:42PM -0400, David Miller wrote:
>
>> If these patches depend upon changes not in my tree, and you haven't
>> even mentioned this, I'm going to be _extremely_ irritated.
>
> Sorry for being so irritating, and not being clear enough about
> this. I did mention that
>
> Patch number 3 applies on top of my recent two igb/phc patches.
> Patch number 12 applies on top of my recent e100 patch.
>
> Jeff accepted all of those 'recent patches' into his queue, so perhaps
> he would take #3 and #12.
>
> Or should I just drop them for now?
Yes, you can drop them and then send them later through Jeff once
the infrastructure hits my tree.
------------------------------------------------------------------------------
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resolution app monitoring today. Free.
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_______________________________________________
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^ permalink raw reply
* Re: [PATCH V3 net-next 00/28] ethtool: support time stamping and phc clocks
From: Richard Cochran @ 2012-04-04 5:14 UTC (permalink / raw)
To: David Miller
Cc: mporter, e1000-devel, netdev, jacob.e.keller, john.ronciak,
bhutchings
In-Reply-To: <20120403.162542.2077088434639546515.davem@davemloft.net>
On Tue, Apr 03, 2012 at 04:25:42PM -0400, David Miller wrote:
> If these patches depend upon changes not in my tree, and you haven't
> even mentioned this, I'm going to be _extremely_ irritated.
Sorry for being so irritating, and not being clear enough about
this. I did mention that
Patch number 3 applies on top of my recent two igb/phc patches.
Patch number 12 applies on top of my recent e100 patch.
Jeff accepted all of those 'recent patches' into his queue, so perhaps
he would take #3 and #12.
Or should I just drop them for now?
Thanks,
Richard
------------------------------------------------------------------------------
Better than sec? Nothing is better than sec when it comes to
monitoring Big Data applications. Try Boundary one-second
resolution app monitoring today. Free.
http://p.sf.net/sfu/Boundary-dev2dev
_______________________________________________
E1000-devel mailing list
E1000-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/e1000-devel
To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
^ permalink raw reply
* [PATCH net-next 9/10] bnx2x: Change comments and white spaces
From: Yuval Mintz @ 2012-04-04 4:41 UTC (permalink / raw)
To: davem, netdev; +Cc: eilong, Yaniv Rosner, Yuval Mintz
In-Reply-To: <1333514492-20425-1-git-send-email-yuvalmin@broadcom.com>
From: Yaniv Rosner <yaniv.rosner@broadcom.com>
A semantic patch, fixing style issues in the bnx2x's link code.
Signed-off-by: Yaniv Rosner <yaniv.rosner@broadcom.com>
Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 660 ++++++++--------------
1 files changed, 241 insertions(+), 419 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 4df6199..08d82ef 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -139,7 +139,6 @@
-/* */
#define SFP_EEPROM_CON_TYPE_ADDR 0x2
#define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
#define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
@@ -405,8 +404,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
- /*
- * mapping between entry priority to client number (0,1,2 -debug and
+ /* mapping between entry priority to client number (0,1,2 -debug and
* management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
* 3bits client num.
* PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -414,8 +412,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
- /*
- * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
* as strict. Bits 0,1,2 - debug and management entries, 3 -
* COS0 entry, 4 - COS1 entry.
* COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
@@ -426,13 +423,11 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
/* defines which entries (clients) are subjected to WFQ arbitration */
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
- /*
- * For strict priority entries defines the number of consecutive
+ /* For strict priority entries defines the number of consecutive
* slots for the highest priority.
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
- /*
- * mapping between the CREDIT_WEIGHT registers and actual client
+ /* mapping between the CREDIT_WEIGHT registers and actual client
* numbers
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
@@ -444,8 +439,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
/* ETS mode disable */
REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
- /*
- * If ETS mode is enabled (there is no strict priority) defines a WFQ
+ /* If ETS mode is enabled (there is no strict priority) defines a WFQ
* weight for COS0/COS1.
*/
REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
@@ -472,10 +466,9 @@ static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
} else
min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
- /**
- * If the link isn't up (static configuration for example ) The
- * link will be according to 20GBPS.
- */
+ /* If the link isn't up (static configuration for example ) The
+ * link will be according to 20GBPS.
+ */
return min_w_val;
}
/******************************************************************************
@@ -539,8 +532,7 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
struct bnx2x *bp = params->bp;
const u8 port = params->port;
const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
- /**
- * mapping between entry priority to client number (0,1,2 -debug and
+ /* Mapping between entry priority to client number (0,1,2 -debug and
* management clients, 3 - COS0 client, 4 - COS1, ... 8 -
* COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
* reset value or init tool
@@ -552,18 +544,14 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
}
- /**
- * For strict priority entries defines the number of consecutive
- * slots for the highest priority.
- */
- /* TODO_ETS - Should be done by reset value or init tool */
+ /* For strict priority entries defines the number of consecutive
+ * slots for the highest priority.
+ */
REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
- /**
- * mapping between the CREDIT_WEIGHT registers and actual client
+ /* Mapping between the CREDIT_WEIGHT registers and actual client
* numbers
*/
- /* TODO_ETS - Should be done by reset value or init tool */
if (port) {
/*Port 1 has 6 COS*/
REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
@@ -575,8 +563,7 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
}
- /**
- * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
* as strict. Bits 0,1,2 - debug and management entries, 3 -
* COS0 entry, 4 - COS1 entry.
* COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
@@ -591,13 +578,12 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
- /**
- * Please notice the register address are note continuous and a
- * for here is note appropriate.In 2 port mode port0 only COS0-5
- * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
- * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
- * are never used for WFQ
- */
+ /* Please notice the register address are note continuous and a
+ * for here is note appropriate.In 2 port mode port0 only COS0-5
+ * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
+ * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
+ * are never used for WFQ
+ */
REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
@@ -634,10 +620,9 @@ static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
u32 base_upper_bound = 0;
u8 max_cos = 0;
u8 i = 0;
- /**
- * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
- * port mode port1 has COS0-2 that can be used for WFQ.
- */
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
+ * port mode port1 has COS0-2 that can be used for WFQ.
+ */
if (!port) {
base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
@@ -667,8 +652,7 @@ static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
u32 base_weight = 0;
u8 max_cos = 0;
- /**
- * mapping between entry priority to client number 0 - COS0
+ /* Mapping between entry priority to client number 0 - COS0
* client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
* TODO_ETS - Should be done by reset value or init tool
*/
@@ -696,10 +680,9 @@ static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
- /**
- * In 2 port mode port0 has COS0-5 that can be used for WFQ.
- * In 4 port mode port1 has COS0-2 that can be used for WFQ.
- */
+ /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
+ * In 4 port mode port1 has COS0-2 that can be used for WFQ.
+ */
if (!port) {
base_weight = PBF_REG_COS0_WEIGHT_P0;
max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
@@ -739,7 +722,7 @@ static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
/******************************************************************************
* Description:
* Disable will return basicly the values to init values.
-*.
+*
******************************************************************************/
int bnx2x_ets_disabled(struct link_params *params,
struct link_vars *vars)
@@ -868,7 +851,7 @@ static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
/******************************************************************************
* Description:
* Calculate the total BW.A value of 0 isn't legal.
-*.
+*
******************************************************************************/
static int bnx2x_ets_e3b0_get_total_bw(
const struct link_params *params,
@@ -880,7 +863,6 @@ static int bnx2x_ets_e3b0_get_total_bw(
u8 is_bw_cos_exist = 0;
*total_bw = 0 ;
-
/* Calculate total BW requested */
for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
@@ -888,10 +870,9 @@ static int bnx2x_ets_e3b0_get_total_bw(
if (!ets_params->cos[cos_idx].params.bw_params.bw) {
DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
"was set to 0\n");
- /*
- * This is to prevent a state when ramrods
+ /* This is to prevent a state when ramrods
* can't be sent
- */
+ */
ets_params->cos[cos_idx].params.bw_params.bw
= 1;
}
@@ -909,8 +890,7 @@ static int bnx2x_ets_e3b0_get_total_bw(
}
DP(NETIF_MSG_LINK,
"bnx2x_ets_E3B0_config total BW should be 100\n");
- /*
- * We can handle a case whre the BW isn't 100 this can happen
+ /* We can handle a case whre the BW isn't 100 this can happen
* if the TC are joined.
*/
}
@@ -920,7 +900,7 @@ static int bnx2x_ets_e3b0_get_total_bw(
/******************************************************************************
* Description:
* Invalidate all the sp_pri_to_cos.
-*.
+*
******************************************************************************/
static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
{
@@ -932,7 +912,7 @@ static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
* Description:
* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
* according to sp_pri_to_cos.
-*.
+*
******************************************************************************/
static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
u8 *sp_pri_to_cos, const u8 pri,
@@ -965,7 +945,7 @@ static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
* Description:
* Returns the correct value according to COS and priority in
* the sp_pri_cli register.
-*.
+*
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
const u8 pri_set,
@@ -982,7 +962,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
* Description:
* Returns the correct value according to COS and priority in the
* sp_pri_cli register for NIG.
-*.
+*
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
{
@@ -998,7 +978,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
* Description:
* Returns the correct value according to COS and priority in the
* sp_pri_cli register for PBF.
-*.
+*
******************************************************************************/
static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
{
@@ -1014,7 +994,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
* Description:
* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
* according to sp_pri_to_cos.(which COS has higher priority)
-*.
+*
******************************************************************************/
static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
u8 *sp_pri_to_cos)
@@ -1150,8 +1130,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
return -EINVAL;
}
- /*
- * Upper bound is set according to current link speed (min_w_val
+ /* Upper bound is set according to current link speed (min_w_val
* should be the same for upper bound and COS credit val).
*/
bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
@@ -1161,8 +1140,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
cos_bw_bitmap |= (1 << cos_entry);
- /*
- * The function also sets the BW in HW(not the mappin
+ /* The function also sets the BW in HW(not the mappin
* yet)
*/
bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
@@ -1218,14 +1196,12 @@ static void bnx2x_ets_bw_limit_common(const struct link_params *params)
/* ETS disabled configuration */
struct bnx2x *bp = params->bp;
DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
- /*
- * defines which entries (clients) are subjected to WFQ arbitration
+ /* Defines which entries (clients) are subjected to WFQ arbitration
* COS0 0x8
* COS1 0x10
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
- /*
- * mapping between the ARB_CREDIT_WEIGHT registers and actual
+ /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
* client numbers (WEIGHT_0 does not actually have to represent
* client 0)
* PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -1243,8 +1219,7 @@ static void bnx2x_ets_bw_limit_common(const struct link_params *params)
/* Defines the number of consecutive slots for the strict priority */
REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
- /*
- * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
* as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
* entry, 4 - COS1 entry.
* COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
@@ -1299,8 +1274,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
u32 val = 0;
DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
- /*
- * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+ /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
* as strict. Bits 0,1,2 - debug and management entries,
* 3 - COS0 entry, 4 - COS1 entry.
* COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
@@ -1308,8 +1282,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
* MCP and debug are strict
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
- /*
- * For strict priority entries defines the number of consecutive slots
+ /* For strict priority entries defines the number of consecutive slots
* for the highest priority.
*/
REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
@@ -1321,8 +1294,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
/* Defines the number of consecutive slots for the strict priority */
REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
- /*
- * mapping between entry priority to client number (0,1,2 -debug and
+ /* Mapping between entry priority to client number (0,1,2 -debug and
* management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
* 3bits client num.
* PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -1357,15 +1329,12 @@ static void bnx2x_update_pfc_xmac(struct link_params *params,
if (!(params->feature_config_flags &
FEATURE_CONFIG_PFC_ENABLED)) {
- /*
- * RX flow control - Process pause frame in receive direction
+ /* RX flow control - Process pause frame in receive direction
*/
if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
- /*
- * TX flow control - Send pause packet when buffer is full
- */
+ /* TX flow control - Send pause packet when buffer is full */
if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
} else {/* PFC support */
@@ -1451,8 +1420,7 @@ void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
{
u32 mode, emac_base;
- /**
- * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
+ /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
* (a value of 49==0x31) and make sure that the AUTO poll is off
*/
@@ -1572,15 +1540,6 @@ static void bnx2x_umac_enable(struct link_params *params,
DP(NETIF_MSG_LINK, "enabling UMAC\n");
- /**
- * This register determines on which events the MAC will assert
- * error on the i/f to the NIG along w/ EOP.
- */
-
- /**
- * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
- * params->port*0x14, 0xfffff.
- */
/* This register opens the gate for the UMAC despite its name */
REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
@@ -1643,8 +1602,7 @@ static void bnx2x_umac_enable(struct link_params *params,
val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
- /*
- * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
+ /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
* length used by the MAC receive logic to check frames.
*/
REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
@@ -1660,8 +1618,7 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
struct bnx2x *bp = params->bp;
u32 is_port4mode = bnx2x_is_4_port_mode(bp);
- /*
- * In 4-port mode, need to set the mode only once, so if XMAC is
+ /* In 4-port mode, need to set the mode only once, so if XMAC is
* already out of reset, it means the mode has already been set,
* and it must not* reset the XMAC again, since it controls both
* ports of the path
@@ -1685,13 +1642,13 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
if (is_port4mode) {
DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
- /* Set the number of ports on the system side to up to 2 */
+ /* Set the number of ports on the system side to up to 2 */
REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
/* Set the number of ports on the Warp Core to 10G */
REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
} else {
- /* Set the number of ports on the system side to 1 */
+ /* Set the number of ports on the system side to 1 */
REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
if (max_speed == SPEED_10000) {
DP(NETIF_MSG_LINK,
@@ -1723,8 +1680,7 @@ static void bnx2x_xmac_disable(struct link_params *params)
if (REG_RD(bp, MISC_REG_RESET_REG_2) &
MISC_REGISTERS_RESET_REG_2_XMAC) {
- /*
- * Send an indication to change the state in the NIG back to XON
+ /* Send an indication to change the state in the NIG back to XON
* Clearing this bit enables the next set of this bit to get
* rising edge
*/
@@ -1749,13 +1705,11 @@ static int bnx2x_xmac_enable(struct link_params *params,
bnx2x_xmac_init(params, vars->line_speed);
- /*
- * This register determines on which events the MAC will assert
+ /* This register determines on which events the MAC will assert
* error on the i/f to the NIG along w/ EOP.
*/
- /*
- * This register tells the NIG whether to send traffic to UMAC
+ /* This register tells the NIG whether to send traffic to UMAC
* or XMAC
*/
REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
@@ -1857,8 +1811,7 @@ static int bnx2x_emac_enable(struct link_params *params,
val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
- /*
- * Setting this bit causes MAC control frames (except for pause
+ /* Setting this bit causes MAC control frames (except for pause
* frames) to be passed on for processing. This setting has no
* affect on the operation of the pause frames. This bit effects
* all packets regardless of RX Parser packet sorting logic.
@@ -1957,8 +1910,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
struct link_vars *vars,
u8 is_lb)
{
- /*
- * Set rx control: Strip CRC and enable BigMAC to relay
+ /* Set rx control: Strip CRC and enable BigMAC to relay
* control packets to the system as well
*/
u32 wb_data[2];
@@ -2010,8 +1962,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
- /*
- * Set Time (based unit is 512 bit time) between automatic
+ /* Set Time (based unit is 512 bit time) between automatic
* re-sending of PP packets amd enable automatic re-send of
* Per-Priroity Packet as long as pp_gen is asserted and
* pp_disable is low.
@@ -2080,7 +2031,7 @@ static int bnx2x_pfc_brb_get_config_params(
config_val->default_class1.full_xon = 0;
if (CHIP_IS_E2(bp)) {
- /* class0 defaults */
+ /* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
@@ -2089,7 +2040,7 @@ static int bnx2x_pfc_brb_get_config_params(
DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
config_val->default_class0.full_xon =
DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
- /* pause able*/
+ /* Pause able*/
config_val->pauseable_th.pause_xoff =
PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
@@ -2108,7 +2059,7 @@ static int bnx2x_pfc_brb_get_config_params(
config_val->non_pauseable_th.full_xon =
PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
} else if (CHIP_IS_E3A0(bp)) {
- /* class0 defaults */
+ /* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
@@ -2117,7 +2068,7 @@ static int bnx2x_pfc_brb_get_config_params(
DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
config_val->default_class0.full_xon =
DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
- /* pause able */
+ /* Pause able */
config_val->pauseable_th.pause_xoff =
PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
config_val->pauseable_th.pause_xon =
@@ -2136,7 +2087,7 @@ static int bnx2x_pfc_brb_get_config_params(
config_val->non_pauseable_th.full_xon =
PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
} else if (CHIP_IS_E3B0(bp)) {
- /* class0 defaults */
+ /* Class0 defaults */
config_val->default_class0.pause_xoff =
DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
config_val->default_class0.pause_xon =
@@ -2299,27 +2250,23 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
reg_th_config = &config_val.non_pauseable_th;
} else
reg_th_config = &config_val.default_class0;
- /*
- * The number of free blocks below which the pause signal to class 0
+ /* The number of free blocks below which the pause signal to class 0
* of MAC #n is asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
reg_th_config->pause_xoff);
- /*
- * The number of free blocks above which the pause signal to class 0
+ /* The number of free blocks above which the pause signal to class 0
* of MAC #n is de-asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
- /*
- * The number of free blocks below which the full signal to class 0
+ /* The number of free blocks below which the full signal to class 0
* of MAC #n is asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
- /*
- * The number of free blocks above which the full signal to class 0
+ /* The number of free blocks above which the full signal to class 0
* of MAC #n is de-asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
@@ -2333,30 +2280,26 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
reg_th_config = &config_val.non_pauseable_th;
} else
reg_th_config = &config_val.default_class1;
- /*
- * The number of free blocks below which the pause signal to
+ /* The number of free blocks below which the pause signal to
* class 1 of MAC #n is asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
reg_th_config->pause_xoff);
- /*
- * The number of free blocks above which the pause signal to
+ /* The number of free blocks above which the pause signal to
* class 1 of MAC #n is de-asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
reg_th_config->pause_xon);
- /*
- * The number of free blocks below which the full signal to
+ /* The number of free blocks below which the full signal to
* class 1 of MAC #n is asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
reg_th_config->full_xoff);
- /*
- * The number of free blocks above which the full signal to
+ /* The number of free blocks above which the full signal to
* class 1 of MAC #n is de-asserted. n=0,1
*/
REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
@@ -2373,49 +2316,41 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
e3b0_val.per_class_guaranty_mode);
- /*
- * The hysteresis on the guarantied buffer space for the Lb
+ /* The hysteresis on the guarantied buffer space for the Lb
* port before signaling XON.
*/
REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
e3b0_val.lb_guarantied_hyst);
- /*
- * The number of free blocks below which the full signal to the
+ /* The number of free blocks below which the full signal to the
* LB port is asserted.
*/
REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
e3b0_val.full_lb_xoff_th);
- /*
- * The number of free blocks above which the full signal to the
+ /* The number of free blocks above which the full signal to the
* LB port is de-asserted.
*/
REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
e3b0_val.full_lb_xon_threshold);
- /*
- * The number of blocks guarantied for the MAC #n port. n=0,1
+ /* The number of blocks guarantied for the MAC #n port. n=0,1
*/
- /* The number of blocks guarantied for the LB port.*/
+ /* The number of blocks guarantied for the LB port. */
REG_WR(bp, BRB1_REG_LB_GUARANTIED,
e3b0_val.lb_guarantied);
- /*
- * The number of blocks guarantied for the MAC #n port.
- */
+ /* The number of blocks guarantied for the MAC #n port. */
REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2 * e3b0_val.mac_0_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2 * e3b0_val.mac_1_class_t_guarantied);
- /*
- * The number of blocks guarantied for class #t in MAC0. t=0,1
+ /* The number of blocks guarantied for class #t in MAC0. t=0,1
*/
REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
e3b0_val.mac_0_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
e3b0_val.mac_0_class_t_guarantied);
- /*
- * The hysteresis on the guarantied buffer space for class in
+ /* The hysteresis on the guarantied buffer space for class in
* MAC0. t=0,1
*/
REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
@@ -2423,15 +2358,13 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
e3b0_val.mac_0_class_t_guarantied_hyst);
- /*
- * The number of blocks guarantied for class #t in MAC1.t=0,1
+ /* The number of blocks guarantied for class #t in MAC1.t=0,1
*/
REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
e3b0_val.mac_1_class_t_guarantied);
REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
e3b0_val.mac_1_class_t_guarantied);
- /*
- * The hysteresis on the guarantied buffer space for class #t
+ /* The hysteresis on the guarantied buffer space for class #t
* in MAC1. t=0,1
*/
REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
@@ -2514,15 +2447,13 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
FEATURE_CONFIG_PFC_ENABLED;
DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
- /*
- * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
+ /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
* MAC control frames (that are not pause packets)
* will be forwarded to the XCM.
*/
xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
NIG_REG_LLH0_XCM_MASK);
- /*
- * nig params will override non PFC params, since it's possible to
+ /* NIG params will override non PFC params, since it's possible to
* do transition from PFC to SAFC
*/
if (set_pfc) {
@@ -2542,7 +2473,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
llfc_out_en = nig_params->llfc_out_en;
llfc_enable = nig_params->llfc_enable;
pause_enable = nig_params->pause_enable;
- } else /*defaul non PFC mode - PAUSE */
+ } else /* Default non PFC mode - PAUSE */
pause_enable = 1;
xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
@@ -2602,8 +2533,7 @@ int bnx2x_update_pfc(struct link_params *params,
struct link_vars *vars,
struct bnx2x_nig_brb_pfc_port_params *pfc_params)
{
- /*
- * The PFC and pause are orthogonal to one another, meaning when
+ /* The PFC and pause are orthogonal to one another, meaning when
* PFC is enabled, the pause are disabled, and when PFC is
* disabled, pause are set according to the pause result.
*/
@@ -3142,7 +3072,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
EMAC_MDIO_STATUS_10MB);
/* address */
-
tmp = ((phy->addr << 21) | (devad << 16) | reg |
EMAC_MDIO_COMM_COMMAND_ADDRESS |
EMAC_MDIO_COMM_START_BUSY);
@@ -3331,8 +3260,7 @@ int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
u8 devad, u16 reg, u16 *ret_val)
{
u8 phy_index;
- /*
- * Probe for the phy according to the given phy_addr, and execute
+ /* Probe for the phy according to the given phy_addr, and execute
* the read request on it
*/
for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
@@ -3349,8 +3277,7 @@ int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
u8 devad, u16 reg, u16 val)
{
u8 phy_index;
- /*
- * Probe for the phy according to the given phy_addr, and execute
+ /* Probe for the phy according to the given phy_addr, and execute
* the write request on it
*/
for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
@@ -3376,7 +3303,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
if (bnx2x_is_4_port_mode(bp)) {
u32 port_swap, port_swap_ovr;
- /*figure out path swap value */
+ /* Figure out path swap value */
path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
if (path_swap_ovr & 0x1)
path_swap = (path_swap_ovr & 0x2);
@@ -3386,7 +3313,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
if (path_swap)
path = path ^ 1;
- /*figure out port swap value */
+ /* Figure out port swap value */
port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
if (port_swap_ovr & 0x1)
port_swap = (port_swap_ovr & 0x2);
@@ -3399,7 +3326,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
lane = (port<<1) + path;
} else { /* two port mode - no port swap */
- /*figure out path swap value */
+ /* Figure out path swap value */
path_swap_ovr =
REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
if (path_swap_ovr & 0x1) {
@@ -3431,8 +3358,7 @@ static void bnx2x_set_aer_mmd(struct link_params *params,
if (USES_WARPCORE(bp)) {
aer_val = bnx2x_get_warpcore_lane(phy, params);
- /*
- * In Dual-lane mode, two lanes are joined together,
+ /* In Dual-lane mode, two lanes are joined together,
* so in order to configure them, the AER broadcast method is
* used here.
* 0x200 is the broadcast address for lanes 0,1
@@ -3512,8 +3438,7 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
{
struct bnx2x *bp = params->bp;
*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
- /**
- * resolve pause mode and advertisement Please refer to Table
+ /* Resolve pause mode and advertisement Please refer to Table
* 28B-3 of the 802.3ab-1999 spec
*/
@@ -3636,6 +3561,7 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
if (pause_result & (1<<1))
vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
+
}
static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
@@ -3665,6 +3591,7 @@ static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
bnx2x_pause_resolve(vars, pause_result);
}
+
static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
struct link_params *params,
struct link_vars *vars)
@@ -3770,9 +3697,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
/* Advertise pause */
bnx2x_ext_phy_set_pause(params, phy, vars);
-
- /*
- * Set KR Autoneg Work-Around flag for Warpcore version older than D108
+ /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
*/
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
@@ -3780,7 +3705,6 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
}
-
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_DIGITAL5_MISC7, &val16);
@@ -3854,7 +3778,7 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
- /*Enable encoded forced speed */
+ /* Enable encoded forced speed */
bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
@@ -4216,8 +4140,7 @@ static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
PORT_HW_CFG_E3_MOD_ABS_MASK) >>
PORT_HW_CFG_E3_MOD_ABS_SHIFT;
- /*
- * Should not happen. This function called upon interrupt
+ /* Should not happen. This function called upon interrupt
* triggered by GPIO ( since EPIO can only generate interrupts
* to MCP).
* So if this function was called and none of the GPIOs was set,
@@ -4317,7 +4240,7 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
"link up, rx_tx_asic_rst 0x%x\n",
vars->rx_tx_asic_rst);
} else {
- /*reset the lane to see if link comes up.*/
+ /* Reset the lane to see if link comes up.*/
bnx2x_warpcore_reset_lane(bp, phy, 1);
bnx2x_warpcore_reset_lane(bp, phy, 0);
@@ -4338,7 +4261,6 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
} /*params->rx_tx_asic_rst*/
}
-
static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
struct link_params *params,
struct link_vars *vars)
@@ -4496,7 +4418,7 @@ static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
/* Update those 1-copy registers */
CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
MDIO_AER_BLOCK_AER_REG, 0);
- /* Enable 1G MDIO (1-copy) */
+ /* Enable 1G MDIO (1-copy) */
bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
&val16);
@@ -4575,43 +4497,43 @@ void bnx2x_sync_link(struct link_params *params,
vars->duplex = DUPLEX_FULL;
switch (vars->link_status &
LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
- case LINK_10THD:
- vars->duplex = DUPLEX_HALF;
- /* fall thru */
- case LINK_10TFD:
- vars->line_speed = SPEED_10;
- break;
+ case LINK_10THD:
+ vars->duplex = DUPLEX_HALF;
+ /* Fall thru */
+ case LINK_10TFD:
+ vars->line_speed = SPEED_10;
+ break;
- case LINK_100TXHD:
- vars->duplex = DUPLEX_HALF;
- /* fall thru */
- case LINK_100T4:
- case LINK_100TXFD:
- vars->line_speed = SPEED_100;
- break;
+ case LINK_100TXHD:
+ vars->duplex = DUPLEX_HALF;
+ /* Fall thru */
+ case LINK_100T4:
+ case LINK_100TXFD:
+ vars->line_speed = SPEED_100;
+ break;
- case LINK_1000THD:
- vars->duplex = DUPLEX_HALF;
- /* fall thru */
- case LINK_1000TFD:
- vars->line_speed = SPEED_1000;
- break;
+ case LINK_1000THD:
+ vars->duplex = DUPLEX_HALF;
+ /* Fall thru */
+ case LINK_1000TFD:
+ vars->line_speed = SPEED_1000;
+ break;
- case LINK_2500THD:
- vars->duplex = DUPLEX_HALF;
- /* fall thru */
- case LINK_2500TFD:
- vars->line_speed = SPEED_2500;
- break;
+ case LINK_2500THD:
+ vars->duplex = DUPLEX_HALF;
+ /* Fall thru */
+ case LINK_2500TFD:
+ vars->line_speed = SPEED_2500;
+ break;
- case LINK_10GTFD:
- vars->line_speed = SPEED_10000;
- break;
- case LINK_20GTFD:
- vars->line_speed = SPEED_20000;
- break;
- default:
- break;
+ case LINK_10GTFD:
+ vars->line_speed = SPEED_10000;
+ break;
+ case LINK_20GTFD:
+ vars->line_speed = SPEED_20000;
+ break;
+ default:
+ break;
}
vars->flow_ctrl = 0;
if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
@@ -4786,9 +4708,8 @@ static void bnx2x_set_swap_lanes(struct link_params *params,
struct bnx2x_phy *phy)
{
struct bnx2x *bp = params->bp;
- /*
- * Each two bits represents a lane number:
- * No swap is 0123 => 0x1b no need to enable the swap
+ /* Each two bits represents a lane number:
+ * No swap is 0123 => 0x1b no need to enable the swap
*/
u16 rx_lane_swap, tx_lane_swap;
@@ -5002,8 +4923,7 @@ static void bnx2x_program_serdes(struct bnx2x_phy *phy,
MDIO_REG_BANK_COMBO_IEEE0,
MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
- /*
- * program speed
+ /* Program speed
* - needed only if the speed is greater than 1G (2.5G or 10G)
*/
CL22_RD_OVER_CL45(bp, phy,
@@ -5038,8 +4958,6 @@ static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
struct bnx2x *bp = params->bp;
u16 val = 0;
- /* configure the 48 bits for BAM AN */
-
/* set extended capabilities */
if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
val |= MDIO_OVER_1G_UP1_2_5G;
@@ -5185,11 +5103,8 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
}
}
-
-/*
- * link management
+/* Link management
*/
-
static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
struct link_params *params)
{
@@ -5334,8 +5249,7 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
"ustat_val(0x8371) = 0x%x\n", ustat_val);
return;
}
- /*
- * Step 3: Check CL37 Message Pages received to indicate LP
+ /* Step 3: Check CL37 Message Pages received to indicate LP
* supports only CL37
*/
CL22_RD_OVER_CL45(bp, phy,
@@ -5352,8 +5266,7 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
cl37_fsm_received);
return;
}
- /*
- * The combined cl37/cl73 fsm state information indicating that
+ /* The combined cl37/cl73 fsm state information indicating that
* we are connected to a device which does not support cl73, but
* does support cl37 BAM. In this case we disable cl73 and
* restart cl37 auto-neg
@@ -5924,8 +5837,7 @@ static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
{
u32 latch_status = 0;
- /*
- * Disable the MI INT ( external phy int ) by writing 1 to the
+ /* Disable the MI INT ( external phy int ) by writing 1 to the
* status register. Link down indication is high-active-signal,
* so in this case we need to write the status to clear the XOR
*/
@@ -5960,8 +5872,7 @@ static void bnx2x_link_int_ack(struct link_params *params,
struct bnx2x *bp = params->bp;
u8 port = params->port;
u32 mask;
- /*
- * First reset all status we assume only one line will be
+ /* First reset all status we assume only one line will be
* change at a time
*/
bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
@@ -5975,8 +5886,7 @@ static void bnx2x_link_int_ack(struct link_params *params,
if (is_10g_plus)
mask = NIG_STATUS_XGXS0_LINK10G;
else if (params->switch_cfg == SWITCH_CFG_10G) {
- /*
- * Disable the link interrupt by writing 1 to
+ /* Disable the link interrupt by writing 1 to
* the relevant lane in the status register
*/
u32 ser_lane =
@@ -6176,8 +6086,7 @@ int bnx2x_set_led(struct link_params *params,
break;
case LED_MODE_OPER:
- /*
- * For all other phys, OPER mode is same as ON, so in case
+ /* For all other phys, OPER mode is same as ON, so in case
* link is down, do nothing
*/
if (!vars->link_up)
@@ -6188,9 +6097,7 @@ int bnx2x_set_led(struct link_params *params,
(params->phy[EXT_PHY1].type ==
PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
CHIP_IS_E2(bp) && params->num_phys == 2) {
- /*
- * This is a work-around for E2+8727 Configurations
- */
+ /* This is a work-around for E2+8727 Configurations */
if (mode == LED_MODE_ON ||
speed == SPEED_10000){
REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
@@ -6199,8 +6106,7 @@ int bnx2x_set_led(struct link_params *params,
tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
EMAC_WR(bp, EMAC_REG_EMAC_LED,
(tmp | EMAC_LED_OVERRIDE));
- /*
- * return here without enabling traffic
+ /* Return here without enabling traffic
* LED blink and setting rate in ON mode.
* In oper mode, enabling LED blink
* and setting rate is needed.
@@ -6209,8 +6115,7 @@ int bnx2x_set_led(struct link_params *params,
return rc;
}
} else if (SINGLE_MEDIA_DIRECT(params)) {
- /*
- * This is a work-around for HW issue found when link
+ /* This is a work-around for HW issue found when link
* is up in CL73
*/
if ((!CHIP_IS_E3(bp)) ||
@@ -6258,10 +6163,7 @@ int bnx2x_set_led(struct link_params *params,
(speed == SPEED_1000) ||
(speed == SPEED_100) ||
(speed == SPEED_10))) {
- /*
- * On Everest 1 Ax chip versions for speeds less than
- * 10G LED scheme is different
- */
+ /* For speeds less than 10G LED scheme is different */
REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ port*4, 1);
REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
@@ -6281,8 +6183,7 @@ int bnx2x_set_led(struct link_params *params,
}
-/*
- * This function comes to reflect the actual link state read DIRECTLY from the
+/* This function comes to reflect the actual link state read DIRECTLY from the
* HW
*/
int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
@@ -6370,16 +6271,14 @@ static int bnx2x_link_initialize(struct link_params *params,
int rc = 0;
u8 phy_index, non_ext_phy;
struct bnx2x *bp = params->bp;
- /*
- * In case of external phy existence, the line speed would be the
+ /* In case of external phy existence, the line speed would be the
* line speed linked up by the external phy. In case it is direct
* only, then the line_speed during initialization will be
* equal to the req_line_speed
*/
vars->line_speed = params->phy[INT_PHY].req_line_speed;
- /*
- * Initialize the internal phy in case this is a direct board
+ /* Initialize the internal phy in case this is a direct board
* (no external phys), or this board has external phy which requires
* to first.
*/
@@ -6411,8 +6310,7 @@ static int bnx2x_link_initialize(struct link_params *params,
} else {
for (phy_index = EXT_PHY1; phy_index < params->num_phys;
phy_index++) {
- /*
- * No need to initialize second phy in case of first
+ /* No need to initialize second phy in case of first
* phy only selection. In case of second phy, we do
* need to initialize the first phy, since they are
* connected.
@@ -6599,8 +6497,7 @@ static int bnx2x_update_link_up(struct link_params *params,
msleep(20);
return rc;
}
-/*
- * The bnx2x_link_update function should be called upon link
+/* The bnx2x_link_update function should be called upon link
* interrupt.
* Link is considered up as follows:
* - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
@@ -6657,8 +6554,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
if (!CHIP_IS_E3(bp))
REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
- /*
- * Step 1:
+ /* Step 1:
* Check external link change only for external phys, and apply
* priority selection between them in case the link on both phys
* is up. Note that instead of the common vars, a temporary
@@ -6689,23 +6585,20 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
switch (bnx2x_phy_selection(params)) {
case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
- /*
- * In this option, the first PHY makes sure to pass the
+ /* In this option, the first PHY makes sure to pass the
* traffic through itself only.
* Its not clear how to reset the link on the second phy
*/
active_external_phy = EXT_PHY1;
break;
case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
- /*
- * In this option, the first PHY makes sure to pass the
+ /* In this option, the first PHY makes sure to pass the
* traffic through the second PHY.
*/
active_external_phy = EXT_PHY2;
break;
default:
- /*
- * Link indication on both PHYs with the following cases
+ /* Link indication on both PHYs with the following cases
* is invalid:
* - FIRST_PHY means that second phy wasn't initialized,
* hence its link is expected to be down
@@ -6722,8 +6615,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
}
}
prev_line_speed = vars->line_speed;
- /*
- * Step 2:
+ /* Step 2:
* Read the status of the internal phy. In case of
* DIRECT_SINGLE_MEDIA board, this link is the external link,
* otherwise this is the link between the 577xx and the first
@@ -6733,8 +6625,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
params->phy[INT_PHY].read_status(
¶ms->phy[INT_PHY],
params, vars);
- /*
- * The INT_PHY flow control reside in the vars. This include the
+ /* The INT_PHY flow control reside in the vars. This include the
* case where the speed or flow control are not set to AUTO.
* Otherwise, the active external phy flow control result is set
* to the vars. The ext_phy_line_speed is needed to check if the
@@ -6743,14 +6634,12 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
*/
if (active_external_phy > INT_PHY) {
vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
- /*
- * Link speed is taken from the XGXS. AN and FC result from
+ /* Link speed is taken from the XGXS. AN and FC result from
* the external phy.
*/
vars->link_status |= phy_vars[active_external_phy].link_status;
- /*
- * if active_external_phy is first PHY and link is up - disable
+ /* if active_external_phy is first PHY and link is up - disable
* disable TX on second external PHY
*/
if (active_external_phy == EXT_PHY1) {
@@ -6787,8 +6676,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
" ext_phy_line_speed = %d\n", vars->flow_ctrl,
vars->link_status, ext_phy_line_speed);
- /*
- * Upon link speed change set the NIG into drain mode. Comes to
+ /* Upon link speed change set the NIG into drain mode. Comes to
* deals with possible FIFO glitch due to clk change when speed
* is decreased without link down indicator
*/
@@ -6813,8 +6701,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
bnx2x_link_int_ack(params, vars, link_10g_plus);
- /*
- * In case external phy link is up, and internal link is down
+ /* In case external phy link is up, and internal link is down
* (not initialized yet probably after link initialization, it
* needs to be initialized.
* Note that after link down-up as result of cable plug, the xgxs
@@ -6842,8 +6729,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
vars);
}
}
- /*
- * Link is up only if both local phy and external phy (in case of
+ /* Link is up only if both local phy and external phy (in case of
* non-direct board) are up and no fault detected on active PHY.
*/
vars->link_up = (vars->phy_link_up &&
@@ -7069,8 +6955,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
}
/* XAUI workaround in 8073 A0: */
- /*
- * After loading the boot ROM and restarting Autoneg, poll
+ /* After loading the boot ROM and restarting Autoneg, poll
* Dev1, Reg $C820:
*/
@@ -7079,8 +6964,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
&val);
- /*
- * If bit [14] = 0 or bit [13] = 0, continue on with
+ /* If bit [14] = 0 or bit [13] = 0, continue on with
* system initialization (XAUI work-around not required, as
* these bits indicate 2.5G or 1G link up).
*/
@@ -7089,8 +6973,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
return 0;
} else if (!(val & (1<<15))) {
DP(NETIF_MSG_LINK, "bit 15 went off\n");
- /*
- * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
+ /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
* MSB (bit15) goes to 1 (indicating that the XAUI
* workaround has completed), then continue on with
* system initialization.
@@ -7240,8 +7123,7 @@ static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
val = (1<<7);
} else if (phy->req_line_speed == SPEED_2500) {
val = (1<<5);
- /*
- * Note that 2.5G works only when used with 1G
+ /* Note that 2.5G works only when used with 1G
* advertisement
*/
} else
@@ -7292,8 +7174,7 @@ static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
/* Add support for CL37 (passive mode) III */
bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
- /*
- * The SNR will improve about 2db by changing BW and FEE main
+ /* The SNR will improve about 2db by changing BW and FEE main
* tap. Rest commands are executed after link is up
* Change FFE main cursor to 5 in EDC register
*/
@@ -7380,8 +7261,7 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
- /*
- * The SNR will improve about 2dbby changing the BW and FEE main
+ /* The SNR will improve about 2dbby changing the BW and FEE main
* tap. The 1st write to change FFE main tap is set before
* restart AN. Change PLL Bandwidth in EDC register
*/
@@ -7428,8 +7308,7 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
bnx2x_cl45_read(bp, phy,
MDIO_XS_DEVAD,
MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
- /*
- * Set bit 3 to invert Rx in 1G mode and clear this bit
+ /* Set bit 3 to invert Rx in 1G mode and clear this bit
* when it`s in 10G mode.
*/
if (vars->line_speed == SPEED_1000) {
@@ -7551,8 +7430,7 @@ static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
u8 pmd_dis)
{
struct bnx2x *bp = params->bp;
- /*
- * Disable transmitter only for bootcodes which can enable it afterwards
+ /* Disable transmitter only for bootcodes which can enable it afterwards
* (for D3 link)
*/
if (pmd_dis) {
@@ -7729,9 +7607,6 @@ static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
u32 data_array[4];
u16 addr32;
struct bnx2x *bp = params->bp;
- /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
- " addr %d, cnt %d\n",
- addr, byte_cnt);*/
if (byte_cnt > 16) {
DP(NETIF_MSG_LINK,
"Reading from eeprom is limited to 16 bytes\n");
@@ -7796,8 +7671,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
0x8002);
- /*
- * Wait appropriate time for two-wire command to finish before
+ /* Wait appropriate time for two-wire command to finish before
* polling the status register
*/
msleep(1);
@@ -7890,8 +7764,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
{
u8 copper_module_type;
phy->media_type = ETH_PHY_DA_TWINAX;
- /*
- * Check if its active cable (includes SFP+ module)
+ /* Check if its active cable (includes SFP+ module)
* of passive cable
*/
if (bnx2x_read_sfp_module_eeprom(phy,
@@ -7968,8 +7841,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
return 0;
}
-/*
- * This function read the relevant field from the module (SFP+), and verify it
+/* This function read the relevant field from the module (SFP+), and verify it
* is compliant with this board
*/
static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
@@ -8049,8 +7921,7 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
u8 val;
struct bnx2x *bp = params->bp;
u16 timeout;
- /*
- * Initialization time after hot-plug may take up to 300ms for
+ /* Initialization time after hot-plug may take up to 300ms for
* some phys type ( e.g. JDSU )
*/
@@ -8072,8 +7943,7 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
u8 is_power_up) {
/* Make sure GPIOs are not using for LED mode */
u16 val;
- /*
- * In the GPIO register, bit 4 is use to determine if the GPIOs are
+ /* In the GPIO register, bit 4 is use to determine if the GPIOs are
* operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
* output
* Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
@@ -8089,8 +7959,7 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
if (is_power_up)
val = (1<<4);
else
- /*
- * Set GPIO control to OUTPUT, and set the power bit
+ /* Set GPIO control to OUTPUT, and set the power bit
* to according to the is_power_up
*/
val = (1<<1);
@@ -8124,8 +7993,7 @@ static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
- /*
- * Changing to LRM mode takes quite few seconds. So do it only
+ /* Changing to LRM mode takes quite few seconds. So do it only
* if current mode is limiting (default is LRM)
*/
if (cur_limiting_mode != EDC_MODE_LIMITING)
@@ -8260,8 +8128,7 @@ static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
struct bnx2x *bp = params->bp;
DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
if (CHIP_IS_E3(bp)) {
- /*
- * Low ==> if SFP+ module is supported otherwise
+ /* Low ==> if SFP+ module is supported otherwise
* High ==> if SFP+ module is not on the approved vendor list
*/
bnx2x_set_e3_module_fault_led(params, gpio_mode);
@@ -8286,8 +8153,7 @@ static void bnx2x_warpcore_power_module(struct link_params *params,
return;
DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
power, pin_cfg);
- /*
- * Low ==> corresponding SFP+ module is powered
+ /* Low ==> corresponding SFP+ module is powered
* high ==> the SFP+ module is powered down
*/
bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
@@ -8421,14 +8287,12 @@ int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
}
- /*
- * Check and set limiting mode / LRM mode on 8726. On 8727 it
+ /* Check and set limiting mode / LRM mode on 8726. On 8727 it
* is done automatically
*/
bnx2x_set_limiting_mode(params, phy, edc_mode);
- /*
- * Enable transmit for this module if the module is approved, or
+ /* Enable transmit for this module if the module is approved, or
* if unapproved modules should also enable the Tx laser
*/
if (rc == 0 ||
@@ -8483,8 +8347,7 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
bnx2x_set_gpio_int(bp, gpio_num,
MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
gpio_port);
- /*
- * Module was plugged out.
+ /* Module was plugged out.
* Disable transmit for this module
*/
phy->media_type = ETH_PHY_NOT_PRESENT;
@@ -8554,8 +8417,7 @@ static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
" link_status 0x%x\n", rx_sd, pcs_status, val2);
- /*
- * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
+ /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
* are set, or if the autoneg bit 1 is set
*/
link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
@@ -8669,8 +8531,7 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
}
bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
- /*
- * If TX Laser is controlled by GPIO_0, do not let PHY go into low
+ /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
* power mode, if TX Laser is disabled
*/
@@ -8780,8 +8641,7 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
bnx2x_8726_external_rom_boot(phy, params);
- /*
- * Need to call module detected on initialization since the module
+ /* Need to call module detected on initialization since the module
* detection triggered by actual module insertion might occur before
* driver is loaded, and when driver is loaded, it reset all
* registers, including the transmitter
@@ -8818,8 +8678,7 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
bnx2x_cl45_write(bp, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
- /*
- * Enable RX-ALARM control to receive interrupt for 1G speed
+ /* Enable RX-ALARM control to receive interrupt for 1G speed
* change
*/
bnx2x_cl45_write(bp, phy,
@@ -8920,8 +8779,7 @@ static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
struct link_params *params) {
u32 swap_val, swap_override;
u8 port;
- /*
- * The PHY reset is controlled by GPIO 1. Fake the port number
+ /* The PHY reset is controlled by GPIO 1. Fake the port number
* to cancel the swap done in set_gpio()
*/
struct bnx2x *bp = params->bp;
@@ -8959,14 +8817,12 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
bnx2x_cl45_write(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
- /*
- * Initially configure MOD_ABS to interrupt when module is
+ /* Initially configure MOD_ABS to interrupt when module is
* presence( bit 8)
*/
bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
- /*
- * Set EDC off by setting OPTXLOS signal input to low (bit 9).
+ /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
* When the EDC is off it locks onto a reference clock and avoids
* becoming 'lost'
*/
@@ -8987,8 +8843,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
if (phy->flags & FLAGS_NOC)
val |= (3<<5);
- /*
- * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
+ /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
* status which reflect SFP+ module over-current
*/
if (!(phy->flags & FLAGS_NOC))
@@ -9014,8 +8869,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
- /*
- * Power down the XAUI until link is up in case of dual-media
+ /* Power down the XAUI until link is up in case of dual-media
* and 1G
*/
if (DUAL_MEDIA(params)) {
@@ -9040,8 +8894,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
bnx2x_cl45_write(bp, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
} else {
- /*
- * Since the 8727 has only single reset pin, need to set the 10G
+ /* Since the 8727 has only single reset pin, need to set the 10G
* registers although it is default
*/
bnx2x_cl45_write(bp, phy,
@@ -9056,8 +8909,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
0x0008);
}
- /*
- * Set 2-wire transfer rate of SFP+ module EEPROM
+ /* Set 2-wire transfer rate of SFP+ module EEPROM
* to 100Khz since some DACs(direct attached cables) do
* not work at 400Khz.
*/
@@ -9080,8 +8932,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
phy->tx_preemphasis[1]);
}
- /*
- * If TX Laser is controlled by GPIO_0, do not let PHY go into low
+ /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
* power mode, if TX Laser is disabled
*/
tx_en_mode = REG_RD(bp, params->shmem_base +
@@ -9121,8 +8972,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK,
"MOD_ABS indication show module is absent\n");
phy->media_type = ETH_PHY_NOT_PRESENT;
- /*
- * 1. Set mod_abs to detect next module
+ /* 1. Set mod_abs to detect next module
* presence event
* 2. Set EDC off by setting OPTXLOS signal input to low
* (bit 9).
@@ -9136,8 +8986,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
- /*
- * Clear RX alarm since it stays up as long as
+ /* Clear RX alarm since it stays up as long as
* the mod_abs wasn't changed
*/
bnx2x_cl45_read(bp, phy,
@@ -9148,8 +8997,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
/* Module is present */
DP(NETIF_MSG_LINK,
"MOD_ABS indication show module is present\n");
- /*
- * First disable transmitter, and if the module is ok, the
+ /* First disable transmitter, and if the module is ok, the
* module_detection will enable it
* 1. Set mod_abs to detect next module absent event ( bit 8)
* 2. Restore the default polarity of the OPRXLOS signal and
@@ -9163,8 +9011,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
- /*
- * Clear RX alarm since it stays up as long as the mod_abs
+ /* Clear RX alarm since it stays up as long as the mod_abs
* wasn't changed. This is need to be done before calling the
* module detection, otherwise it will clear* the link update
* alarm
@@ -9225,8 +9072,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
- /*
- * If a module is present and there is need to check
+ /* If a module is present and there is need to check
* for over current
*/
if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
@@ -9292,8 +9138,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
- /*
- * Bits 0..2 --> speed detected,
+ /* Bits 0..2 --> speed detected,
* Bits 13..15--> link is down
*/
if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
@@ -9336,8 +9181,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD,
MDIO_PMA_REG_8727_PCS_GP, &val1);
- /*
- * In case of dual-media board and 1G, power up the XAUI side,
+ /* In case of dual-media board and 1G, power up the XAUI side,
* otherwise power it down. For 10G it is done automatically
*/
if (link_up)
@@ -9504,8 +9348,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
/* Save spirom version */
bnx2x_save_848xx_spirom_version(phy, bp, params->port);
}
- /*
- * This phy uses the NIG latch mechanism since link indication
+ /* This phy uses the NIG latch mechanism since link indication
* arrives through its LED4 and not via its LASI signal, so we
* get steady signal instead of clear on read
*/
@@ -9610,8 +9453,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
if (phy->req_duplex == DUPLEX_FULL)
autoneg_val |= (1<<8);
- /*
- * Always write this if this is not 84833.
+ /* Always write this if this is not 84833.
* For 84833, write it only when it's a forced speed.
*/
if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
@@ -9850,8 +9692,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
/* Wait for GPHY to come out of reset */
msleep(50);
if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
- /*
- * BCM84823 requires that XGXS links up first @ 10G for normal
+ /* BCM84823 requires that XGXS links up first @ 10G for normal
* behavior.
*/
u16 temp;
@@ -10327,8 +10168,7 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
break;
}
- /*
- * This is a workaround for E3+84833 until autoneg
+ /* This is a workaround for E3+84833 until autoneg
* restart is fixed in f/w
*/
if (CHIP_IS_E3(bp)) {
@@ -10352,8 +10192,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
DP(NETIF_MSG_LINK, "54618SE cfg init\n");
usleep_range(1000, 1000);
- /*
- * This works with E3 only, no need to check the chip
+ /* This works with E3 only, no need to check the chip
* before determining the port.
*/
port = params->port;
@@ -10375,7 +10214,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
MDIO_PMA_REG_CTRL, 0x8000);
bnx2x_wait_reset_complete(bp, phy, params);
- /*wait for GPHY to reset */
+ /* Wait for GPHY to reset */
msleep(50);
/* Configure LED4: set to INTR (0x6). */
@@ -10581,13 +10420,11 @@ static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
u32 cfg_pin;
u8 port;
- /*
- * In case of no EPIO routed to reset the GPHY, put it
+ /* In case of no EPIO routed to reset the GPHY, put it
* in low power mode.
*/
bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
- /*
- * This works with E3 only, no need to check the chip
+ /* This works with E3 only, no need to check the chip
* before determining the port.
*/
port = params->port;
@@ -10696,7 +10533,7 @@ static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
bnx2x_ext_phy_resolve_fc(phy, params, vars);
if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
- /* report LP advertised speeds */
+ /* Report LP advertised speeds */
bnx2x_cl22_read(bp, phy, 0x5, &val);
if (val & (1<<5))
@@ -10761,8 +10598,7 @@ static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
/* This register opens the gate for the UMAC despite its name */
REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
- /*
- * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
+ /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
* length used by the MAC receive logic to check frames.
*/
REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
@@ -11041,17 +10877,17 @@ static struct bnx2x_phy phy_warpcore = {
.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
.mdio_ctrl = 0,
.supported = (SUPPORTED_10baseT_Half |
- SUPPORTED_10baseT_Full |
- SUPPORTED_100baseT_Half |
- SUPPORTED_100baseT_Full |
- SUPPORTED_1000baseT_Full |
- SUPPORTED_10000baseT_Full |
- SUPPORTED_20000baseKR2_Full |
- SUPPORTED_20000baseMLD2_Full |
- SUPPORTED_FIBRE |
- SUPPORTED_Autoneg |
- SUPPORTED_Pause |
- SUPPORTED_Asym_Pause),
+ SUPPORTED_10baseT_Full |
+ SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full |
+ SUPPORTED_1000baseT_Full |
+ SUPPORTED_10000baseT_Full |
+ SUPPORTED_20000baseKR2_Full |
+ SUPPORTED_20000baseMLD2_Full |
+ SUPPORTED_FIBRE |
+ SUPPORTED_Autoneg |
+ SUPPORTED_Pause |
+ SUPPORTED_Asym_Pause),
.media_type = ETH_PHY_UNSPECIFIED,
.ver_addr = 0,
.req_flow_ctrl = 0,
@@ -11405,9 +11241,8 @@ static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
/* Get the 4 lanes xgxs config rx and tx */
u32 rx = 0, tx = 0, i;
for (i = 0; i < 2; i++) {
- /*
- * INT_PHY and EXT_PHY1 share the same value location in the
- * shmem. When num_phys is greater than 1, than this value
+ /* INT_PHY and EXT_PHY1 share the same value location in
+ * the shmem. When num_phys is greater than 1, than this value
* applies only to EXT_PHY1
*/
if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
@@ -11485,8 +11320,7 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
offsetof(struct shmem_region, dev_info.
port_hw_config[port].default_cfg)) &
PORT_HW_CFG_NET_SERDES_IF_MASK);
- /*
- * Set the appropriate supported and flags indications per
+ /* Set the appropriate supported and flags indications per
* interface type of the chip
*/
switch (serdes_net_if) {
@@ -11544,8 +11378,7 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
break;
}
- /*
- * Enable MDC/MDIO work-around for E3 A0 since free running MDC
+ /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
* was not set as expected. For B0, ECO will be enabled so there
* won't be an issue there
*/
@@ -11658,8 +11491,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
- /*
- * The shmem address of the phy version is located on different
+ /* The shmem address of the phy version is located on different
* structures. In case this structure is too old, do not set
* the address
*/
@@ -11693,8 +11525,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
(phy->ver_addr)) {
- /*
- * Remove 100Mb link supported for BCM84833 when phy fw
+ /* Remove 100Mb link supported for BCM84833 when phy fw
* version lower than or equal to 1.39
*/
u32 raw_ver = REG_RD(bp, phy->ver_addr);
@@ -11704,8 +11535,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
SUPPORTED_100baseT_Full);
}
- /*
- * In case mdc/mdio_access of the external phy is different than the
+ /* In case mdc/mdio_access of the external phy is different than the
* mdc/mdio access of the XGXS, a HW lock must be taken in each access
* to prevent one port interfere with another port's CL45 operations.
*/
@@ -11884,8 +11714,7 @@ int bnx2x_phy_probe(struct link_params *params)
dev_info.port_hw_config[params->port].media_type);
media_types = REG_RD(bp, sync_offset);
- /*
- * Update media type for non-PMF sync only for the first time
+ /* Update media type for non-PMF sync only for the first time
* In case the media type changes afterwards, it will be updated
* using the update_status function
*/
@@ -11959,8 +11788,7 @@ void bnx2x_init_xmac_loopback(struct link_params *params,
vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
vars->mac_type = MAC_TYPE_XMAC;
vars->phy_flags = PHY_XGXS_FLAG;
- /*
- * Set WC to loopback mode since link is required to provide clock
+ /* Set WC to loopback mode since link is required to provide clock
* to the XMAC in 20G mode
*/
bnx2x_set_aer_mmd(params, ¶ms->phy[0]);
@@ -12243,7 +12071,8 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
NIG_MASK_MI_INT));
/* Need to take the phy out of low power mode in order
- to write to access its registers */
+ * to write to access its registers
+ */
bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
MISC_REGISTERS_GPIO_OUTPUT_HIGH,
port);
@@ -12291,8 +12120,7 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
(val | 1<<10));
}
- /*
- * Toggle Transmitter: Power down and then up with 600ms delay
+ /* Toggle Transmitter: Power down and then up with 600ms delay
* between
*/
msleep(600);
@@ -12435,8 +12263,7 @@ static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
reset_gpio = MISC_REGISTERS_GPIO_1;
port = 1;
- /*
- * Retrieve the reset gpio/port which control the reset.
+ /* Retrieve the reset gpio/port which control the reset.
* Default is GPIO1, PORT1
*/
bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
@@ -12611,8 +12438,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
- /*
- * GPIO1 affects both ports, so there's need to pull
+ /* GPIO1 affects both ports, so there's need to pull
* it for single port alone
*/
rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
@@ -12620,8 +12446,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
phy_index, chip_id);
break;
case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
- /*
- * GPIO3's are linked, and so both need to be toggled
+ /* GPIO3's are linked, and so both need to be toggled
* to obtain required 2us pulse.
*/
rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
@@ -12735,8 +12560,7 @@ static void bnx2x_analyze_link_error(struct link_params *params,
DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
half_open_conn, lss_status);
- /*
- * a. Update shmem->link_status accordingly
+ /* a. Update shmem->link_status accordingly
* b. Update link_vars->link_up
*/
if (lss_status) {
@@ -12747,8 +12571,7 @@ static void bnx2x_analyze_link_error(struct link_params *params,
/* activate nig drain */
REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
- /*
- * Set LED mode to off since the PHY doesn't know about these
+ /* Set LED mode to off since the PHY doesn't know about these
* errors
*/
led_mode = LED_MODE_OFF;
@@ -12800,8 +12623,7 @@ int bnx2x_check_half_open_conn(struct link_params *params,
(REG_RD(bp, MISC_REG_RESET_REG_2) &
(MISC_REGISTERS_RESET_REG_2_XMAC))) {
/* Check E3 XMAC */
- /*
- * Note that link speed cannot be queried here, since it may be
+ /* Note that link speed cannot be queried here, since it may be
* zero while link is down. In case UMAC is active, LSS will
* simply not be set
*/
--
1.7.9.rc2
^ permalink raw reply related
* [PATCH net-next 8/10] bnx2x: change to the rss engine
From: Yuval Mintz @ 2012-04-04 4:41 UTC (permalink / raw)
To: davem, netdev; +Cc: eilong, Dmitry Kravkov, Yuval Mintz
In-Reply-To: <1333514492-20425-1-git-send-email-yuvalmin@broadcom.com>
From: Dmitry Kravkov <dmitry@broadcom.com>
This patch revises the way by which rss are configured, removing
an unnecessary module paramater and unrequired modes.
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 1 -
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 88 ++++++--------------
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h | 13 +++-
.../net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 7 +-
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 10 +--
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c | 6 --
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h | 3 -
7 files changed, 42 insertions(+), 86 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index 5eecafd..b0803ba 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -1375,7 +1375,6 @@ struct bnx2x {
#define BNX2X_STATE_DIAG 0xe000
#define BNX2X_STATE_ERROR 0xf000
- int multi_mode;
#define BNX2X_MAX_PRIORITY 8
#define BNX2X_MAX_ENTRIES_PER_PRI 16
#define BNX2X_MAX_COS 3
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index 98b82eb..5caba1f 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -1460,20 +1460,11 @@ u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
return __skb_tx_hash(dev, skb, BNX2X_NUM_ETH_QUEUES(bp));
}
+
void bnx2x_set_num_queues(struct bnx2x *bp)
{
- switch (bp->multi_mode) {
- case ETH_RSS_MODE_DISABLED:
- bp->num_queues = 1;
- break;
- case ETH_RSS_MODE_REGULAR:
- bp->num_queues = bnx2x_calc_num_queues(bp);
- break;
-
- default:
- bp->num_queues = 1;
- break;
- }
+ /* RSS queues */
+ bp->num_queues = bnx2x_calc_num_queues(bp);
#ifdef BCM_CNIC
/* override in STORAGE SD mode */
@@ -1572,16 +1563,13 @@ static inline int bnx2x_init_rss_pf(struct bnx2x *bp)
u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
- /*
- * Prepare the inital contents fo the indirection table if RSS is
+ /* Prepare the initial contents fo the indirection table if RSS is
* enabled
*/
- if (bp->multi_mode != ETH_RSS_MODE_DISABLED) {
- for (i = 0; i < sizeof(ind_table); i++)
- ind_table[i] =
- bp->fp->cl_id +
- ethtool_rxfh_indir_default(i, num_eth_queues);
- }
+ for (i = 0; i < sizeof(ind_table); i++)
+ ind_table[i] =
+ bp->fp->cl_id +
+ ethtool_rxfh_indir_default(i, num_eth_queues);
/*
* For 57710 and 57711 SEARCHER configuration (rss_keys) is
@@ -1591,11 +1579,12 @@ static inline int bnx2x_init_rss_pf(struct bnx2x *bp)
* For 57712 and newer on the other hand it's a per-function
* configuration.
*/
- return bnx2x_config_rss_pf(bp, ind_table,
- bp->port.pmf || !CHIP_IS_E1x(bp));
+ return bnx2x_config_rss_eth(bp, ind_table,
+ bp->port.pmf || !CHIP_IS_E1x(bp));
}
-int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash)
+int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
+ u8 *ind_table, bool config_hash)
{
struct bnx2x_config_rss_params params = {NULL};
int i;
@@ -1607,52 +1596,29 @@ int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash)
* bp->multi_mode = ETH_RSS_MODE_DISABLED;
*/
- params.rss_obj = &bp->rss_conf_obj;
+ params.rss_obj = rss_obj;
__set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
- /* RSS mode */
- switch (bp->multi_mode) {
- case ETH_RSS_MODE_DISABLED:
- __set_bit(BNX2X_RSS_MODE_DISABLED, ¶ms.rss_flags);
- break;
- case ETH_RSS_MODE_REGULAR:
- __set_bit(BNX2X_RSS_MODE_REGULAR, ¶ms.rss_flags);
- break;
- case ETH_RSS_MODE_VLAN_PRI:
- __set_bit(BNX2X_RSS_MODE_VLAN_PRI, ¶ms.rss_flags);
- break;
- case ETH_RSS_MODE_E1HOV_PRI:
- __set_bit(BNX2X_RSS_MODE_E1HOV_PRI, ¶ms.rss_flags);
- break;
- case ETH_RSS_MODE_IP_DSCP:
- __set_bit(BNX2X_RSS_MODE_IP_DSCP, ¶ms.rss_flags);
- break;
- default:
- BNX2X_ERR("Unknown multi_mode: %d\n", bp->multi_mode);
- return -EINVAL;
- }
+ __set_bit(BNX2X_RSS_MODE_REGULAR, ¶ms.rss_flags);
- /* If RSS is enabled */
- if (bp->multi_mode != ETH_RSS_MODE_DISABLED) {
- /* RSS configuration */
- __set_bit(BNX2X_RSS_IPV4, ¶ms.rss_flags);
- __set_bit(BNX2X_RSS_IPV4_TCP, ¶ms.rss_flags);
- __set_bit(BNX2X_RSS_IPV6, ¶ms.rss_flags);
- __set_bit(BNX2X_RSS_IPV6_TCP, ¶ms.rss_flags);
+ /* RSS configuration */
+ __set_bit(BNX2X_RSS_IPV4, ¶ms.rss_flags);
+ __set_bit(BNX2X_RSS_IPV4_TCP, ¶ms.rss_flags);
+ __set_bit(BNX2X_RSS_IPV6, ¶ms.rss_flags);
+ __set_bit(BNX2X_RSS_IPV6_TCP, ¶ms.rss_flags);
- /* Hash bits */
- params.rss_result_mask = MULTI_MASK;
+ /* Hash bits */
+ params.rss_result_mask = MULTI_MASK;
- memcpy(params.ind_table, ind_table, sizeof(params.ind_table));
+ memcpy(params.ind_table, ind_table, sizeof(params.ind_table));
- if (config_hash) {
- /* RSS keys */
- for (i = 0; i < sizeof(params.rss_key) / 4; i++)
- params.rss_key[i] = random32();
+ if (config_hash) {
+ /* RSS keys */
+ for (i = 0; i < sizeof(params.rss_key) / 4; i++)
+ params.rss_key[i] = random32();
- __set_bit(BNX2X_RSS_SET_SRCH, ¶ms.rss_flags);
- }
+ __set_bit(BNX2X_RSS_SET_SRCH, ¶ms.rss_flags);
}
return bnx2x_config_rss(bp, ¶ms);
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index 7f3cb81..0c3b2c5 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -86,13 +86,15 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
void bnx2x_send_unload_done(struct bnx2x *bp);
/**
- * bnx2x_config_rss_pf - configure RSS parameters.
+ * bnx2x_config_rss_pf - configure RSS parameters in a PF.
*
* @bp: driver handle
+ * @rss_obj RSS object to use
* @ind_table: indirection table to configure
* @config_hash: re-configure RSS hash keys configuration
*/
-int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash);
+int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
+ u8 *ind_table, bool config_hash);
/**
* bnx2x__init_func_obj - init function object
@@ -967,6 +969,13 @@ static inline int func_by_vn(struct bnx2x *bp, int vn)
return 2 * vn + BP_PORT(bp);
}
+static inline int bnx2x_config_rss_eth(struct bnx2x *bp, u8 *ind_table,
+ bool config_hash)
+{
+ return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, ind_table,
+ config_hash);
+}
+
/**
* bnx2x_func_start - init function
*
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index 93b5fc4..3c7d0cc 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -2393,10 +2393,7 @@ static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
{
- struct bnx2x *bp = netdev_priv(dev);
-
- return (bp->multi_mode == ETH_RSS_MODE_DISABLED ?
- 0 : T_ETH_INDIRECTION_TABLE_SIZE);
+ return T_ETH_INDIRECTION_TABLE_SIZE;
}
static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
@@ -2442,7 +2439,7 @@ static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
ind_table[i] = indir[i] + bp->fp->cl_id;
}
- return bnx2x_config_rss_pf(bp, ind_table, false);
+ return bnx2x_config_rss_eth(bp, ind_table, false);
}
static const struct ethtool_ops bnx2x_ethtool_ops = {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 9e03067..eb4fc787 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -91,15 +91,11 @@ MODULE_FIRMWARE(FW_FILE_NAME_E1);
MODULE_FIRMWARE(FW_FILE_NAME_E1H);
MODULE_FIRMWARE(FW_FILE_NAME_E2);
-static int multi_mode = 1;
-module_param(multi_mode, int, 0);
-MODULE_PARM_DESC(multi_mode, " Multi queue mode "
- "(0 Disable; 1 Enable (default))");
int num_queues;
module_param(num_queues, int, 0);
-MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
- " (default is as a number of CPUs)");
+MODULE_PARM_DESC(num_queues,
+ " Set number of queues (default is as a number of CPUs)");
static int disable_tpa;
module_param(disable_tpa, int, 0);
@@ -9969,8 +9965,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
if (BP_NOMCP(bp) && (func == 0))
dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
- bp->multi_mode = multi_mode;
-
bp->disable_tpa = disable_tpa;
#ifdef BCM_CNIC
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 3f52fad..fc6dc30 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -4090,12 +4090,6 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
rss_mode = ETH_RSS_MODE_DISABLED;
else if (test_bit(BNX2X_RSS_MODE_REGULAR, &p->rss_flags))
rss_mode = ETH_RSS_MODE_REGULAR;
- else if (test_bit(BNX2X_RSS_MODE_VLAN_PRI, &p->rss_flags))
- rss_mode = ETH_RSS_MODE_VLAN_PRI;
- else if (test_bit(BNX2X_RSS_MODE_E1HOV_PRI, &p->rss_flags))
- rss_mode = ETH_RSS_MODE_E1HOV_PRI;
- else if (test_bit(BNX2X_RSS_MODE_IP_DSCP, &p->rss_flags))
- rss_mode = ETH_RSS_MODE_IP_DSCP;
data->rss_mode = rss_mode;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
index 61a7670..dee2f37 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
@@ -685,9 +685,6 @@ enum {
/* RSS_MODE bits are mutually exclusive */
BNX2X_RSS_MODE_DISABLED,
BNX2X_RSS_MODE_REGULAR,
- BNX2X_RSS_MODE_VLAN_PRI,
- BNX2X_RSS_MODE_E1HOV_PRI,
- BNX2X_RSS_MODE_IP_DSCP,
BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
--
1.7.9.rc2
^ permalink raw reply related
* [PATCH net-next 10/10] bnx2x: Change to driver version 1.72.10-0
From: Yuval Mintz @ 2012-04-04 4:41 UTC (permalink / raw)
To: davem, netdev; +Cc: eilong, Yuval Mintz
In-Reply-To: <1333514492-20425-1-git-send-email-yuvalmin@broadcom.com>
Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index b0803ba..6627a5e 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -23,8 +23,8 @@
* (you will need to reboot afterwards) */
/* #define BNX2X_STOP_ON_ERROR */
-#define DRV_MODULE_VERSION "1.72.10-0"
-#define DRV_MODULE_RELDATE "2012/02/20"
+#define DRV_MODULE_VERSION "1.72.17-0"
+#define DRV_MODULE_RELDATE "2012/04/02"
#define BNX2X_BC_VER 0x040200
#if defined(CONFIG_DCB)
--
1.7.9.rc2
^ permalink raw reply related
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