* Re: use-after-free in usbnet
From: Ming Lei @ 2012-04-26 5:02 UTC (permalink / raw)
To: Huajun Li
Cc: Oliver Neukum, Alan Stern, Dave Jones,
netdev-u79uwXL29TY76Z2rM5mHXA, linux-usb-u79uwXL29TY76Z2rM5mHXA,
Fedora Kernel Team
In-Reply-To: <CA+v9cxawVwKakF6c_RpAw2XUGWcbqd8M+ZJqyq76Au9rmNosmQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Huajun,
On Fri, Apr 20, 2012 at 9:37 PM, Huajun Li <huajun.li.lee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
>
> Above patch has already been integrated to mainline. However, maybe
> there still exists another potentail use-after-free issue, here is a
> case:
> After release the lock in unlink_urbs(), defer_bh() may move
> current skb from rxq/txq to dev->done queue, even cause the skb be
> released. Then in next loop cycle, it can't refer to expected skb, and
> may Oops again.
>
> To easily reproduce it, in unlink_urbs(), you can delay a short time
> after usb_put_urb(urb), then disconnect your device while transferring
> data, and repeat it times you will find errors on your screen.
>
> Following is a draft patch to guarantee the queue consistent, and
> refer to expected skb in each loop cycle:
>
> diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
> index b7b3f5b..6da0141 100644
> --- a/drivers/net/usb/usbnet.c
> +++ b/drivers/net/usb/usbnet.c
> @@ -578,16 +578,28 @@ EXPORT_SYMBOL_GPL(usbnet_purge_paused_rxq);
> static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q)
> {
> unsigned long flags;
> - struct sk_buff *skb, *skbnext;
> + struct sk_buff *skb;
> int count = 0;
>
> spin_lock_irqsave (&q->lock, flags);
> - skb_queue_walk_safe(q, skb, skbnext) {
> + while (!skb_queue_empty(q)) {
> struct skb_data *entry;
> struct urb *urb;
> int retval;
>
> - entry = (struct skb_data *) skb->cb;
> + skb_queue_walk(q, skb) {
> + entry = (struct skb_data *)skb->cb;
> + if (entry->state == rx_done ||
> + entry->state == tx_done ||
> + entry->state == rx_cleanup)
> + continue;
> + else
> + break;
> + }
> +
> + if (skb == (struct sk_buff *)(q))
> + break;
> +
> urb = entry->urb;
>
>
After thinking about the issue further, the basic idea of your patch is good,
but not safe(double unlink, also races on accessing entry->state), so I write
a new one based on your patch.
Are you OK this new one?
Thanks,
--
Ming Lei
From 89eb41968caa9523c90c1cf7b7e2259db00e04b8 Mon Sep 17 00:00:00 2001
From: Ming Lei <tom.leiming-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Date: Thu, 26 Apr 2012 11:33:46 +0800
Subject: [PATCH] usbnet: fix skb traversing races during unlink
Commit 4231d47e6fe69f061f96c98c30eaf9fb4c14b96d(net/usbnet: avoid
recursive locking in usbnet_stop()) fixes the recursive locking
problem by releasing the skb queue lock before unlink, but may
cause skb traversing races:
- after URB is unlinked and the queue lock is released,
the refered skb and skb->next may be moved to done queue,
even be released
- in skb_queue_walk_safe, the next skb is still obtained
by next pointer of the last skb
- so maybe trigger oops or other problems
This patch extends the usage of entry->state to describe 'start_unlink'
state, so always holding the queue(rx/tx) lock to change the state if
the referd skb is in rx or tx queue because we need to know if the
refered urb has been started unlinking in unlink_urbs.
Also the patch uses usb_block_urb introduced by Oliver to block
URB resubmit in complete handler if the URB will be unlinked.
The other part of this patch is based on Hugjun's patch:
always traverse from head of the tx/rx queue to get skb which is
to be unlinked but not been started unlinking.
---
drivers/net/usb/usbnet.c | 54 ++++++++++++++++++++++++++++++++------------
include/linux/usb/usbnet.h | 3 ++-
2 files changed, 41 insertions(+), 16 deletions(-)
diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index db99536..dff5e1b 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -281,17 +281,30 @@ int usbnet_change_mtu (struct net_device *net,
int new_mtu)
}
EXPORT_SYMBOL_GPL(usbnet_change_mtu);
+/*The caller must hold list->lock*/
+static void __usbnet_queue_skb(struct sk_buff_head *list,
+ struct sk_buff *newsk, enum skb_state state)
+{
+ struct skb_data *entry = (struct skb_data *) newsk->cb;
+
+ __skb_queue_tail(list, newsk);
+ entry->state = state;
+}
+
/*-------------------------------------------------------------------------*/
/* some LK 2.4 HCDs oopsed if we freed or resubmitted urbs from
* completion callbacks. 2.5 should have fixed those bugs...
*/
-static void defer_bh(struct usbnet *dev, struct sk_buff *skb, struct
sk_buff_head *list)
+static void defer_bh(struct usbnet *dev, struct sk_buff *skb,
+ struct sk_buff_head *list, enum skb_state state)
{
unsigned long flags;
+ struct skb_data *entry = (struct skb_data *) skb->cb;
spin_lock_irqsave(&list->lock, flags);
+ entry->state = state;
__skb_unlink(skb, list);
spin_unlock(&list->lock);
spin_lock(&dev->done.lock);
@@ -339,7 +352,6 @@ static int rx_submit (struct usbnet *dev, struct
urb *urb, gfp_t flags)
entry = (struct skb_data *) skb->cb;
entry->urb = urb;
entry->dev = dev;
- entry->state = rx_start;
entry->length = 0;
usb_fill_bulk_urb (urb, dev->udev, dev->in,
@@ -371,7 +383,7 @@ static int rx_submit (struct usbnet *dev, struct
urb *urb, gfp_t flags)
tasklet_schedule (&dev->bh);
break;
case 0:
- __skb_queue_tail (&dev->rxq, skb);
+ __usbnet_queue_skb(&dev->rxq, skb, rx_start);
}
} else {
netif_dbg(dev, ifdown, dev->net, "rx: stopped\n");
@@ -422,16 +434,17 @@ static void rx_complete (struct urb *urb)
struct skb_data *entry = (struct skb_data *) skb->cb;
struct usbnet *dev = entry->dev;
int urb_status = urb->status;
+ enum skb_state state;
skb_put (skb, urb->actual_length);
- entry->state = rx_done;
+ state = rx_done;
entry->urb = NULL;
switch (urb_status) {
/* success */
case 0:
if (skb->len < dev->net->hard_header_len) {
- entry->state = rx_cleanup;
+ state = rx_cleanup;
dev->net->stats.rx_errors++;
dev->net->stats.rx_length_errors++;
netif_dbg(dev, rx_err, dev->net,
@@ -470,7 +483,7 @@ static void rx_complete (struct urb *urb)
"rx throttle %d\n", urb_status);
}
block:
- entry->state = rx_cleanup;
+ state = rx_cleanup;
entry->urb = urb;
urb = NULL;
break;
@@ -481,13 +494,13 @@ block:
// FALLTHROUGH
default:
- entry->state = rx_cleanup;
+ state = rx_cleanup;
dev->net->stats.rx_errors++;
netif_dbg(dev, rx_err, dev->net, "rx status %d\n", urb_status);
break;
}
- defer_bh(dev, skb, &dev->rxq);
+ defer_bh(dev, skb, &dev->rxq, state);
if (urb) {
if (netif_running (dev->net) &&
@@ -578,16 +591,24 @@ EXPORT_SYMBOL_GPL(usbnet_purge_paused_rxq);
static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q)
{
unsigned long flags;
- struct sk_buff *skb, *skbnext;
+ struct sk_buff *skb;
int count = 0;
spin_lock_irqsave (&q->lock, flags);
- skb_queue_walk_safe(q, skb, skbnext) {
+ while (!skb_queue_empty(q)) {
struct skb_data *entry;
struct urb *urb;
int retval;
- entry = (struct skb_data *) skb->cb;
+ skb_queue_walk(q, skb) {
+ entry = (struct skb_data *) skb->cb;
+ if (entry->state != unlink_start)
+ break;
+ }
+ if (skb == (struct sk_buff *)q)
+ break;
+
+ entry->state = unlink_start;
urb = entry->urb;
/*
@@ -598,6 +619,10 @@ static int unlink_urbs (struct usbnet *dev,
struct sk_buff_head *q)
* handler(include defer_bh).
*/
usb_get_urb(urb);
+
+ /*speedup unlink by blocking resubmit*/
+ usb_block_urb(urb);
+
spin_unlock_irqrestore(&q->lock, flags);
// during some PM-driven resume scenarios,
// these (async) unlinks complete immediately
@@ -606,6 +631,7 @@ static int unlink_urbs (struct usbnet *dev, struct
sk_buff_head *q)
netdev_dbg(dev->net, "unlink urb err, %d\n", retval);
else
count++;
+ usb_unblock_urb(urb);
usb_put_urb(urb);
spin_lock_irqsave(&q->lock, flags);
}
@@ -1039,8 +1065,7 @@ static void tx_complete (struct urb *urb)
}
usb_autopm_put_interface_async(dev->intf);
- entry->state = tx_done;
- defer_bh(dev, skb, &dev->txq);
+ defer_bh(dev, skb, &dev->txq, tx_done);
}
/*-------------------------------------------------------------------------*/
@@ -1096,7 +1121,6 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
entry = (struct skb_data *) skb->cb;
entry->urb = urb;
entry->dev = dev;
- entry->state = tx_start;
entry->length = length;
usb_fill_bulk_urb (urb, dev->udev, dev->out,
@@ -1155,7 +1179,7 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
break;
case 0:
net->trans_start = jiffies;
- __skb_queue_tail (&dev->txq, skb);
+ __usbnet_queue_skb(&dev->txq, skb, tx_start);
if (dev->txq.qlen >= TX_QLEN (dev))
netif_stop_queue (net);
}
diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h
index 605b0aa..76f4396 100644
--- a/include/linux/usb/usbnet.h
+++ b/include/linux/usb/usbnet.h
@@ -191,7 +191,8 @@ extern void usbnet_cdc_status(struct usbnet *,
struct urb *);
enum skb_state {
illegal = 0,
tx_start, tx_done,
- rx_start, rx_done, rx_cleanup
+ rx_start, rx_done, rx_cleanup,
+ unlink_start
};
struct skb_data { /* skb->cb is one of these */
--
1.7.9.5
--
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^ permalink raw reply related
* Re: [PATCH v3 1/2] vhost-net: fix handle_rx buffer size
From: Eric W. Biederman @ 2012-04-26 5:30 UTC (permalink / raw)
To: Basil Gor; +Cc: David S. Miller, netdev
In-Reply-To: <1335373275-336-1-git-send-email-basil.gor@gmail.com>
Basil Gor <basil.gor@gmail.com> writes:
> Take vlan header length into account, when vlan id is stored as
> vlan_tci. Otherwise tagged packets comming from macvtap will be
> truncated.
Better.
In recvmsg you are still missing handling of PACKET_AUXDATA
that includes aux.tp_vlan_tci === vlan_id and
aux.tp_status === TP_STATUS_VLAN_VALID.
That is the way pf_packet sockets report the vlan. Not
in the actual packet itself.
Eric
> Signed-off-by: Basil Gor <basil.gor@gmail.com>
> ---
> drivers/vhost/net.c | 7 ++++++-
> 1 files changed, 6 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c
> index 1f21d2a..5c17010 100644
> --- a/drivers/vhost/net.c
> +++ b/drivers/vhost/net.c
> @@ -24,6 +24,7 @@
> #include <linux/if_arp.h>
> #include <linux/if_tun.h>
> #include <linux/if_macvlan.h>
> +#include <linux/if_vlan.h>
>
> #include <net/sock.h>
>
> @@ -283,8 +284,12 @@ static int peek_head_len(struct sock *sk)
>
> spin_lock_irqsave(&sk->sk_receive_queue.lock, flags);
> head = skb_peek(&sk->sk_receive_queue);
> - if (likely(head))
> + if (likely(head)) {
> len = head->len;
> + if (vlan_tx_tag_present(head))
> + len += VLAN_HLEN;
> + }
> +
> spin_unlock_irqrestore(&sk->sk_receive_queue.lock, flags);
> return len;
> }
^ permalink raw reply
* Re: [PATCH v3 2/2] macvtap: restore vlan header on user read
From: Eric W. Biederman @ 2012-04-26 5:31 UTC (permalink / raw)
To: Basil Gor; +Cc: David S. Miller, netdev
In-Reply-To: <1335373316-612-1-git-send-email-basil.gor@gmail.com>
Basil Gor <basil.gor@gmail.com> writes:
> Vlan tag is restored during buffer transmit to a network device (bridge
> port) in bridging code in case of tun/tap driver. In case of macvtap it
> has to be done explicitly. Otherwise vlan_tci is ignored and user always
> gets untagged packets.
We could quibble about efficiencies but this looks good except for
macvtap_recvmsg which isn't setting the auxdata for the vlan header.
Eric
> Signed-off-by: Basil Gor <basil.gor@gmail.com>
> ---
> drivers/net/macvtap.c | 11 ++++++++++-
> 1 files changed, 10 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
> index 0427c65..28d2678 100644
> --- a/drivers/net/macvtap.c
> +++ b/drivers/net/macvtap.c
> @@ -1,6 +1,7 @@
> #include <linux/etherdevice.h>
> #include <linux/if_macvlan.h>
> #include <linux/interrupt.h>
> +#include <linux/if_vlan.h>
> #include <linux/nsproxy.h>
> #include <linux/compat.h>
> #include <linux/if_tun.h>
> @@ -753,13 +754,21 @@ static ssize_t macvtap_aio_write(struct kiocb *iocb, const struct iovec *iv,
>
> /* Put packet to the user space buffer */
> static ssize_t macvtap_put_user(struct macvtap_queue *q,
> - const struct sk_buff *skb,
> + struct sk_buff *skb,
> const struct iovec *iv, int len)
> {
> struct macvlan_dev *vlan;
> int ret;
> int vnet_hdr_len = 0;
>
> + if (vlan_tx_tag_present(skb)) {
> + skb = __vlan_put_tag(skb, vlan_tx_tag_get(skb));
> + if (unlikely(!skb))
> + return -ENOMEM;
> +
> + skb->vlan_tci = 0;
> + }
> +
> if (q->flags & IFF_VNET_HDR) {
> struct virtio_net_hdr vnet_hdr;
> vnet_hdr_len = q->vnet_hdr_sz;
^ permalink raw reply
* [v2 PATCH 1/1] ipvs: kernel oops - do_ip_vs_get_ctl
From: Hans Schillstrom @ 2012-04-26 5:47 UTC (permalink / raw)
To: horms, ja, wensong, brouer, rohara, lvs-devel, netdev,
netfilter-devel
Cc: hans, Hans Schillstrom
Change order of init so netns init is ready
when register ioctl and netlink.
Ver2
Whitespace fixes and __init added.
Reported-by: "Ryan O'Hara" <rohara@redhat.com>
Signed-off-by: Hans Schillstrom <hans.schillstrom@ericsson.com>
---
include/net/ip_vs.h | 2 +
net/netfilter/ipvs/ip_vs_core.c | 9 ++++++
net/netfilter/ipvs/ip_vs_ctl.c | 52 ++++++++++++++++++++++----------------
3 files changed, 41 insertions(+), 22 deletions(-)
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index f967395..93b81aa 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -1201,6 +1201,8 @@ ip_vs_lookup_real_service(struct net *net, int af, __u16 protocol,
extern int ip_vs_use_count_inc(void);
extern void ip_vs_use_count_dec(void);
+extern int ip_vs_register_nl_ioctl(void);
+extern void ip_vs_unregister_nl_ioctl(void);
extern int ip_vs_control_init(void);
extern void ip_vs_control_cleanup(void);
extern struct ip_vs_dest *
diff --git a/net/netfilter/ipvs/ip_vs_core.c b/net/netfilter/ipvs/ip_vs_core.c
index d8b1d30..c8f36b9 100644
--- a/net/netfilter/ipvs/ip_vs_core.c
+++ b/net/netfilter/ipvs/ip_vs_core.c
@@ -1995,10 +1995,18 @@ static int __init ip_vs_init(void)
goto cleanup_dev;
}
+ ret = ip_vs_register_nl_ioctl();
+ if (ret < 0) {
+ pr_err("can't register netlink/ioctl.\n");
+ goto cleanup_hooks;
+ }
+
pr_info("ipvs loaded.\n");
return ret;
+cleanup_hooks:
+ nf_unregister_hooks(ip_vs_ops, ARRAY_SIZE(ip_vs_ops));
cleanup_dev:
unregister_pernet_device(&ipvs_core_dev_ops);
cleanup_sub:
@@ -2014,6 +2022,7 @@ exit:
static void __exit ip_vs_cleanup(void)
{
+ ip_vs_unregister_nl_ioctl();
nf_unregister_hooks(ip_vs_ops, ARRAY_SIZE(ip_vs_ops));
unregister_pernet_device(&ipvs_core_dev_ops);
unregister_pernet_subsys(&ipvs_core_ops); /* free ip_vs struct */
diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c
index 7131417..efaf484 100644
--- a/net/netfilter/ipvs/ip_vs_ctl.c
+++ b/net/netfilter/ipvs/ip_vs_ctl.c
@@ -3750,21 +3750,10 @@ void __net_exit ip_vs_control_net_cleanup(struct net *net)
free_percpu(ipvs->tot_stats.cpustats);
}
-int __init ip_vs_control_init(void)
+int __init ip_vs_register_nl_ioctl(void)
{
- int idx;
int ret;
- EnterFunction(2);
-
- /* Initialize svc_table, ip_vs_svc_fwm_table, rs_table */
- for(idx = 0; idx < IP_VS_SVC_TAB_SIZE; idx++) {
- INIT_LIST_HEAD(&ip_vs_svc_table[idx]);
- INIT_LIST_HEAD(&ip_vs_svc_fwm_table[idx]);
- }
-
- smp_wmb(); /* Do we really need it now ? */
-
ret = nf_register_sockopt(&ip_vs_sockopts);
if (ret) {
pr_err("cannot register sockopt.\n");
@@ -3776,28 +3765,47 @@ int __init ip_vs_control_init(void)
pr_err("cannot register Generic Netlink interface.\n");
goto err_genl;
}
-
- ret = register_netdevice_notifier(&ip_vs_dst_notifier);
- if (ret < 0)
- goto err_notf;
-
- LeaveFunction(2);
return 0;
-err_notf:
- ip_vs_genl_unregister();
err_genl:
nf_unregister_sockopt(&ip_vs_sockopts);
err_sock:
return ret;
}
+void ip_vs_unregister_nl_ioctl(void)
+{
+ ip_vs_genl_unregister();
+ nf_unregister_sockopt(&ip_vs_sockopts);
+}
+
+int __init ip_vs_control_init(void)
+{
+ int idx;
+ int ret;
+
+ EnterFunction(2);
+
+ /* Initialize svc_table, ip_vs_svc_fwm_table, rs_table */
+ for (idx = 0; idx < IP_VS_SVC_TAB_SIZE; idx++) {
+ INIT_LIST_HEAD(&ip_vs_svc_table[idx]);
+ INIT_LIST_HEAD(&ip_vs_svc_fwm_table[idx]);
+ }
+
+ smp_wmb(); /* Do we really need it now ? */
+
+ ret = register_netdevice_notifier(&ip_vs_dst_notifier);
+ if (ret < 0)
+ return ret;
+
+ LeaveFunction(2);
+ return 0;
+}
+
void ip_vs_control_cleanup(void)
{
EnterFunction(2);
unregister_netdevice_notifier(&ip_vs_dst_notifier);
- ip_vs_genl_unregister();
- nf_unregister_sockopt(&ip_vs_sockopts);
LeaveFunction(2);
}
--
1.7.2.3
^ permalink raw reply related
* Re: [PATCH 1/2] netfilter: ipvs: Verify that IP_VS protocol has been registered
From: Simon Horman @ 2012-04-26 6:15 UTC (permalink / raw)
To: Pablo Neira Ayuso
Cc: lvs-devel, netdev, netfilter-devel, Wensong Zhang,
Julian Anastasov, Sasha Levin
In-Reply-To: <20120425091422.GA15049@1984>
On Wed, Apr 25, 2012 at 11:14:22AM +0200, Pablo Neira Ayuso wrote:
> On Mon, Apr 23, 2012 at 10:12:11PM +0900, Simon Horman wrote:
> > From: Sasha Levin <levinsasha928@gmail.com>
> >
> > The registration of a protocol might fail, there were no checks
> > and all registrations were assumed to be correct. This lead to
> > NULL ptr dereferences when apps tried registering.
> >
> > For example:
> >
> > [ 1293.226051] BUG: unable to handle kernel NULL pointer dereference at 0000000000000018
> > [ 1293.227038] IP: [<ffffffff822aacb0>] tcp_register_app+0x60/0xb0
> > [ 1293.227038] PGD 391de067 PUD 6c20b067 PMD 0
> > [ 1293.227038] Oops: 0000 [#1] PREEMPT SMP
> > [ 1293.227038] CPU 1
> > [ 1293.227038] Pid: 19609, comm: trinity Tainted: G W 3.4.0-rc1-next-20120405-sasha-dirty #57
> > [ 1293.227038] RIP: 0010:[<ffffffff822aacb0>] [<ffffffff822aacb0>] tcp_register_app+0x60/0xb0
> > [ 1293.227038] RSP: 0018:ffff880038c1dd18 EFLAGS: 00010286
> > [ 1293.227038] RAX: ffffffffffffffc0 RBX: 0000000000001500 RCX: 0000000000010000
> > [ 1293.227038] RDX: 0000000000000000 RSI: ffff88003a2d5888 RDI: 0000000000000282
> > [ 1293.227038] RBP: ffff880038c1dd48 R08: 0000000000000000 R09: 0000000000000000
> > [ 1293.227038] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88003a2d5668
> > [ 1293.227038] R13: ffff88003a2d5988 R14: ffff8800696a8ff8 R15: 0000000000000000
> > [ 1293.227038] FS: 00007f01930d9700(0000) GS:ffff88007ce00000(0000) knlGS:0000000000000000
> > [ 1293.227038] CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b
> > [ 1293.227038] CR2: 0000000000000018 CR3: 0000000065dfc000 CR4: 00000000000406e0
> > [ 1293.227038] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> > [ 1293.227038] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
> > [ 1293.227038] Process trinity (pid: 19609, threadinfo ffff880038c1c000, task ffff88002dc73000)
> > [ 1293.227038] Stack:
> > [ 1293.227038] ffff880038c1dd48 00000000fffffff4 ffff8800696aada0 ffff8800694f5580
> > [ 1293.227038] ffffffff8369f1e0 0000000000001500 ffff880038c1dd98 ffffffff822a716b
> > [ 1293.227038] 0000000000000000 ffff8800696a8ff8 0000000000000015 ffff8800694f5580
> > [ 1293.227038] Call Trace:
> > [ 1293.227038] [<ffffffff822a716b>] ip_vs_app_inc_new+0xdb/0x180
> > [ 1293.227038] [<ffffffff822a7258>] register_ip_vs_app_inc+0x48/0x70
> > [ 1293.227038] [<ffffffff822b2fea>] __ip_vs_ftp_init+0xba/0x140
> > [ 1293.227038] [<ffffffff821c9060>] ops_init+0x80/0x90
> > [ 1293.227038] [<ffffffff821c90cb>] setup_net+0x5b/0xe0
> > [ 1293.227038] [<ffffffff821c9416>] copy_net_ns+0x76/0x100
> > [ 1293.227038] [<ffffffff810dc92b>] create_new_namespaces+0xfb/0x190
> > [ 1293.227038] [<ffffffff810dca21>] unshare_nsproxy_namespaces+0x61/0x80
> > [ 1293.227038] [<ffffffff810afd1f>] sys_unshare+0xff/0x290
> > [ 1293.227038] [<ffffffff8187622e>] ? trace_hardirqs_on_thunk+0x3a/0x3f
> > [ 1293.227038] [<ffffffff82665539>] system_call_fastpath+0x16/0x1b
> > [ 1293.227038] Code: 89 c7 e8 34 91 3b 00 89 de 66 c1 ee 04 31 de 83 e6 0f 48 83 c6 22 48 c1 e6 04 4a 8b 14 26 49 8d 34 34 48 8d 42 c0 48 39 d6 74 13 <66> 39 58 58 74 22 48 8b 48 40 48 8d 41 c0 48 39 ce 75 ed 49 8d
> > [ 1293.227038] RIP [<ffffffff822aacb0>] tcp_register_app+0x60/0xb0
> > [ 1293.227038] RSP <ffff880038c1dd18>
> > [ 1293.227038] CR2: 0000000000000018
> > [ 1293.379284] ---[ end trace 364ab40c7011a009 ]---
> > [ 1293.381182] Kernel panic - not syncing: Fatal exception in interrupt
> >
> > Cc: stable@vger.kernel.org
>
> I've removed this above from the patch. I prefer not to add confusing
> information (this means you'll have to rebase, sorry).
Understood.
> > Signed-off-by: Sasha Levin <levinsasha928@gmail.com>
> > Acked-by: Julian Anastasov <ja@ssi.bg>
> > Signed-off-by: Simon Horman <horms@verge.net.au>
>
> Applied. Thanks.
Thanks.
> BTW, did you consider using an array for ipvs->ip_vs_proto_table?
>
> I think a hash table for only 5 protocols is overkill. I know, we'll
> consume more memory but lookups will definitely be faster, but it will
> consume a bit more memory (the space-time tradeoff again).
That sounds reasonable to me.
^ permalink raw reply
* Re: kernel BUG at include/net/netns/generic.h:41
From: Stanislav Kinsbursky @ 2012-04-26 6:25 UTC (permalink / raw)
To: Dave Jones, Myklebust, Trond, Linux Kernel,
netdev@vger.kernel.org
In-Reply-To: <20120425225855.GA5537@redhat.com>
26.04.2012 02:58, Dave Jones написал:
> On Thu, Apr 05, 2012 at 08:14:04PM +0400, Stanislav Kinsbursky wrote:
> > 05.04.2012 20:12, Dave Jones пишет:
> > > On Thu, Apr 05, 2012 at 08:08:31PM +0400, Stanislav Kinsbursky wrote:
> > >
> > > > So, there are few questions to you, Dave:
> > > > 1) can this happen (PipeFS mount attempt before SUNPRC module insertion has
> > > > returned any value) in your case?
> > >
> > > I don't know enough of what systemd is doing to answer this.
> > >
> > > > 2) how often do you experience this problem? Not every boot, I suppose?
> > > > 3) And is it easy for you to reproduce?
> > >
> > > It happens most the time, but not every time.
> > >
> >
> > Ok, I'll send the patch soon.
> > Hope, it will help.
> >
> > --
> > Best regards,
> > Stanislav Kinsbursky
>
> I didn't see a follow-up patch on this, and I'm still seeing the BUG in rc4.
>
> Dave
Dave, search for "SUNRPC: register PipeFS file system after pernet
sybsystem" in your mail.
You are in CC list.
^ permalink raw reply
* [PATCH 01/10] atl1c: remove REG_PHY_STATUS
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
this register is used for l1e(dev=1026)
l1c/l1d/l2cb don't use it.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 7 -------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 2 --
2 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index cc7afa1..459e141 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -293,13 +293,6 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
#define MDIO_AP_EN 0x10000000
#define MDIO_WAIT_TIMES 10
-/* MII PHY Status Register */
-#define REG_PHY_STATUS 0x1418
-#define PHY_GENERAL_STATUS_MASK 0xFFFF
-#define PHY_STATUS_RECV_ENABLE 0x0001
-#define PHY_OE_PWSP_STATUS_MASK 0x07FF
-#define PHY_OE_PWSP_STATUS_SHIFT 16
-#define PHY_STATUS_LPW_STATE 0x80000000
/* BIST Control and Status Register0 (for the Packet Memory) */
#define REG_BIST0_CTRL 0x141c
#define BIST0_NOW 0x1
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index df10637..a6c3f05 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -699,11 +699,9 @@ static void atl1c_set_mac_type(struct atl1c_hw *hw)
static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
{
- u32 phy_status_data;
u32 link_ctrl_data;
atl1c_set_mac_type(hw);
- AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
--
1.7.7
^ permalink raw reply related
* [PATCH 02/10] atl1c: refine phy-register read/write function
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
phy register is read/write via MDIO control module ---
that module will be affected by the hibernate status,
to access phy regs in hib stutus, slow frequency clk must
be selected.
To access phy extension register, the MDIO related
registers are refined/updated, a _core function is
re-wroted for both regular PHY regs and extension regs.
existing PHY r/w function is revised based on the _core.
PHY extension registers will be used for the comming
patches.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 189 ++++++++++++++++++----
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 65 +++++---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 4 +-
3 files changed, 197 insertions(+), 61 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index bd1667c..a17b531 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -278,33 +278,158 @@ void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
}
/*
- * Reads the value from a PHY register
- * hw - Struct containing variables accessed by shared code
- * reg_addr - address of the PHY register to read
+ * wait mdio module be idle
+ * return true: idle
+ * false: still busy
*/
-int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
+bool atl1c_wait_mdio_idle(struct atl1c_hw *hw)
{
u32 val;
int i;
- val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
- MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
- MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
+ for (i = 0; i < MDIO_MAX_AC_TO; i++) {
+ AT_READ_REG(hw, REG_MDIO_CTRL, &val);
+ if (!(val & (MDIO_CTRL_BUSY | MDIO_CTRL_START)))
+ break;
+ udelay(10);
+ }
+
+ return i != MDIO_MAX_AC_TO;
+}
+void atl1c_stop_phy_polling(struct atl1c_hw *hw)
+{
+ if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
+ return;
+
+ AT_WRITE_REG(hw, REG_MDIO_CTRL, 0);
+ atl1c_wait_mdio_idle(hw);
+}
+
+void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel)
+{
+ u32 val;
+
+ if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
+ return;
+
+ val = MDIO_CTRL_SPRES_PRMBL |
+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
+ FIELDX(MDIO_CTRL_REG, 1) |
+ MDIO_CTRL_START |
+ MDIO_CTRL_OP_READ;
AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
+ atl1c_wait_mdio_idle(hw);
+ val |= MDIO_CTRL_AP_EN;
+ val &= ~MDIO_CTRL_START;
+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
+ udelay(30);
+}
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- AT_READ_REG(hw, REG_MDIO_CTRL, &val);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
+
+/*
+ * atl1c_read_phy_core
+ * core funtion to read register in PHY via MDIO control regsiter.
+ * ext: extension register (see IEEE 802.3)
+ * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
+ * reg: reg to read
+ */
+int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
+ u16 reg, u16 *phy_data)
+{
+ u32 val;
+ u16 clk_sel = MDIO_CTRL_CLK_25_4;
+
+ atl1c_stop_phy_polling(hw);
+
+ *phy_data = 0;
+
+ /* only l2c_b2 & l1d_2 could use slow clock */
+ if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) &&
+ hw->hibernate)
+ clk_sel = MDIO_CTRL_CLK_25_128;
+ if (ext) {
+ val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg);
+ AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
+ val = MDIO_CTRL_SPRES_PRMBL |
+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
+ MDIO_CTRL_START |
+ MDIO_CTRL_MODE_EXT |
+ MDIO_CTRL_OP_READ;
+ } else {
+ val = MDIO_CTRL_SPRES_PRMBL |
+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
+ FIELDX(MDIO_CTRL_REG, reg) |
+ MDIO_CTRL_START |
+ MDIO_CTRL_OP_READ;
}
- if (!(val & (MDIO_START | MDIO_BUSY))) {
- *phy_data = (u16)val;
- return 0;
+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
+
+ if (!atl1c_wait_mdio_idle(hw))
+ return -1;
+
+ AT_READ_REG(hw, REG_MDIO_CTRL, &val);
+ *phy_data = (u16)FIELD_GETX(val, MDIO_CTRL_DATA);
+
+ atl1c_start_phy_polling(hw, clk_sel);
+
+ return 0;
+}
+
+/*
+ * atl1c_write_phy_core
+ * core funtion to write to register in PHY via MDIO control regsiter.
+ * ext: extension register (see IEEE 802.3)
+ * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0)
+ * reg: reg to write
+ */
+int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
+ u16 reg, u16 phy_data)
+{
+ u32 val;
+ u16 clk_sel = MDIO_CTRL_CLK_25_4;
+
+ atl1c_stop_phy_polling(hw);
+
+
+ /* only l2c_b2 & l1d_2 could use slow clock */
+ if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) &&
+ hw->hibernate)
+ clk_sel = MDIO_CTRL_CLK_25_128;
+
+ if (ext) {
+ val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg);
+ AT_WRITE_REG(hw, REG_MDIO_EXTN, val);
+ val = MDIO_CTRL_SPRES_PRMBL |
+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
+ FIELDX(MDIO_CTRL_DATA, phy_data) |
+ MDIO_CTRL_START |
+ MDIO_CTRL_MODE_EXT;
+ } else {
+ val = MDIO_CTRL_SPRES_PRMBL |
+ FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) |
+ FIELDX(MDIO_CTRL_DATA, phy_data) |
+ FIELDX(MDIO_CTRL_REG, reg) |
+ MDIO_CTRL_START;
}
+ AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
- return -1;
+ if (!atl1c_wait_mdio_idle(hw))
+ return -1;
+
+ atl1c_start_phy_polling(hw, clk_sel);
+
+ return 0;
+}
+
+/*
+ * Reads the value from a PHY register
+ * hw - Struct containing variables accessed by shared code
+ * reg_addr - address of the PHY register to read
+ */
+int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ return atl1c_read_phy_core(hw, false, 0, reg_addr, phy_data);
}
/*
@@ -315,27 +440,21 @@ int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
*/
int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
{
- int i;
- u32 val;
-
- val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
- (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
- MDIO_SUP_PREAMBLE | MDIO_START |
- MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
-
- AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
-
- for (i = 0; i < MDIO_WAIT_TIMES; i++) {
- udelay(2);
- AT_READ_REG(hw, REG_MDIO_CTRL, &val);
- if (!(val & (MDIO_START | MDIO_BUSY)))
- break;
- }
+ return atl1c_write_phy_core(hw, false, 0, reg_addr, phy_data);
+}
- if (!(val & (MDIO_START | MDIO_BUSY)))
- return 0;
+/* read from PHY extension register */
+int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
+ u16 reg_addr, u16 *phy_data)
+{
+ return atl1c_read_phy_core(hw, true, dev_addr, reg_addr, phy_data);
+}
- return -1;
+/* write to PHY extension register */
+int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
+ u16 reg_addr, u16 phy_data)
+{
+ return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data);
}
/*
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 459e141..cb2d20b 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -49,6 +49,17 @@ int atl1c_phy_init(struct atl1c_hw *hw);
int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
int atl1c_restart_autoneg(struct atl1c_hw *hw);
int atl1c_phy_power_saving(struct atl1c_hw *hw);
+bool atl1c_wait_mdio_idle(struct atl1c_hw *hw);
+void atl1c_stop_phy_polling(struct atl1c_hw *hw);
+void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
+int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
+ u16 reg, u16 *phy_data);
+int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev,
+ u16 reg, u16 phy_data);
+int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
+ u16 reg_addr, u16 *phy_data);
+int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
+ u16 reg_addr, u16 phy_data);
/* register definition */
#define REG_DEVICE_CAP 0x5C
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
@@ -268,30 +279,36 @@ int atl1c_phy_power_saving(struct atl1c_hw *hw);
/* MDIO Control Register */
#define REG_MDIO_CTRL 0x1414
-#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit
- * control data to write to PHY
- * MII management register */
-#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit
- * status data that was read
- * from the PHY MII management register */
-#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
-#define MDIO_REG_ADDR_SHIFT 16
-#define MDIO_RW 0x200000 /* 1: read, 0: write */
-#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
-#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO
- * master. And this bit is self
- * cleared after one cycle */
-#define MDIO_CLK_SEL_SHIFT 24
-#define MDIO_CLK_25_4 0
-#define MDIO_CLK_25_6 2
-#define MDIO_CLK_25_8 3
-#define MDIO_CLK_25_10 4
-#define MDIO_CLK_25_14 5
-#define MDIO_CLK_25_20 6
-#define MDIO_CLK_25_28 7
-#define MDIO_BUSY 0x8000000
-#define MDIO_AP_EN 0x10000000
-#define MDIO_WAIT_TIMES 10
+#define MDIO_CTRL_MODE_EXT BIT(30)
+#define MDIO_CTRL_POST_READ BIT(29)
+#define MDIO_CTRL_AP_EN BIT(28)
+#define MDIO_CTRL_BUSY BIT(27)
+#define MDIO_CTRL_CLK_SEL_MASK 0x7UL
+#define MDIO_CTRL_CLK_SEL_SHIFT 24
+#define MDIO_CTRL_CLK_25_4 0 /* 25MHz divide 4 */
+#define MDIO_CTRL_CLK_25_6 2
+#define MDIO_CTRL_CLK_25_8 3
+#define MDIO_CTRL_CLK_25_10 4
+#define MDIO_CTRL_CLK_25_32 5
+#define MDIO_CTRL_CLK_25_64 6
+#define MDIO_CTRL_CLK_25_128 7
+#define MDIO_CTRL_START BIT(23)
+#define MDIO_CTRL_SPRES_PRMBL BIT(22)
+#define MDIO_CTRL_OP_READ BIT(21) /* 1:read, 0:write */
+#define MDIO_CTRL_REG_MASK 0x1FUL
+#define MDIO_CTRL_REG_SHIFT 16
+#define MDIO_CTRL_DATA_MASK 0xFFFFUL
+#define MDIO_CTRL_DATA_SHIFT 0
+#define MDIO_MAX_AC_TO 120 /* 1.2ms timeout for slow clk */
+
+/* for extension reg access */
+#define REG_MDIO_EXTN 0x1448
+#define MDIO_EXTN_PORTAD_MASK 0x1FUL
+#define MDIO_EXTN_PORTAD_SHIFT 21
+#define MDIO_EXTN_DEVAD_MASK 0x1FUL
+#define MDIO_EXTN_DEVAD_SHIFT 16
+#define MDIO_EXTN_REG_MASK 0xFFFFUL
+#define MDIO_EXTN_REG_SHIFT 0
/* BIST Control and Status Register0 (for the Packet Memory) */
#define REG_BIST0_CTRL 0x141c
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index a6c3f05..1f82880 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -2270,7 +2270,7 @@ static int atl1c_open(struct net_device *netdev)
u32 phy_data;
AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
- phy_data |= MDIO_AP_EN;
+ phy_data |= MDIO_CTRL_AP_EN;
AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
}
return 0;
@@ -2558,7 +2558,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
adapter->mii.mdio_read = atl1c_mdio_read;
adapter->mii.mdio_write = atl1c_mdio_write;
adapter->mii.phy_id_mask = 0x1f;
- adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
+ adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
(unsigned long)adapter);
--
1.7.7
^ permalink raw reply related
* [PATCH 03/10] atl1c: remove PHY contrl in atl1c_reset_pcie
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
atl1c_reset_phy follows atl1c_reset_pcie in the whole driver,
so, it's unnecessary to add PHY control code in atl1c_reset_pcie.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 11 ++---------
1 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 1f82880..f0f348b 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -165,11 +165,6 @@ static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
atl1c_pcie_patch(hw);
if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
atl1c_disable_l0s_l1(hw);
- if (flag & ATL1C_PCIE_PHY_RESET)
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
- else
- AT_WRITE_REG(hw, REG_GPHY_CTRL,
- GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
msleep(5);
}
@@ -2409,8 +2404,7 @@ static int atl1c_resume(struct device *dev)
struct atl1c_adapter *adapter = netdev_priv(netdev);
AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
- atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
- ATL1C_PCIE_PHY_RESET);
+ atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
atl1c_phy_reset(&adapter->hw);
atl1c_reset_mac(&adapter->hw);
@@ -2568,8 +2562,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
dev_err(&pdev->dev, "net device private data init failed\n");
goto err_sw_init;
}
- atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
- ATL1C_PCIE_PHY_RESET);
+ atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
/* Init GPHY as early as possible due to power saving issue */
atl1c_phy_reset(&adapter->hw);
--
1.7.7
^ permalink raw reply related
* [PATCH 05/10] atl1c: remove PHY polling from atl1c_open
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
PHY polling code for FPGA is considered in every MDIO R/W API.
no need to add additional code to atl1c_open.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 7 -------
1 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index cf78287..8a1d2f9 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -2273,13 +2273,6 @@ static int atl1c_open(struct net_device *netdev)
if (unlikely(err))
goto err_up;
- if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
- u32 phy_data;
-
- AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
- phy_data |= MDIO_CTRL_AP_EN;
- AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
- }
return 0;
err_up:
--
1.7.7
^ permalink raw reply related
* [PATCH 06/10] atl1c: update PHY reset related routine
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
Many magic data are re-configured for PHY during its reset operation
based on chip type to get better compability and stability.
REG_PHY_CTRL register may be configured by BIOS before enter OS.
so, the driver can't directly write to it without any Read-Op.
this change also affect suspend and phy_disable routines.
PHY debug ports and extension registers are refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 188 +++++++------
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 323 ++++++++++++++++-------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 23 +-
3 files changed, 340 insertions(+), 194 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index a17b531..9a5b0f3 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -457,6 +457,32 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data);
}
+int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
+{
+ int err;
+
+ err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr);
+ if (unlikely(err))
+ return err;
+ else
+ err = atl1c_read_phy_reg(hw, MII_DBG_DATA, phy_data);
+
+ return err;
+}
+
+int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data)
+{
+ int err;
+
+ err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr);
+ if (unlikely(err))
+ return err;
+ else
+ err = atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
+
+ return err;
+}
+
/*
* Configures PHY autoneg and flow control advertisement settings
*
@@ -499,119 +525,107 @@ static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
void atl1c_phy_disable(struct atl1c_hw *hw)
{
- AT_WRITE_REGW(hw, REG_GPHY_CTRL,
- GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
-}
-
-static void atl1c_phy_magic_data(struct atl1c_hw *hw)
-{
- u16 data;
-
- data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
- ((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
- ANA_INTERVAL_SEL_TIMER_SHIFT);
+ u32 phy_ctrl_data;
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
- ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
- ANA_SERDES_EN_LCKDT;
-
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
- ((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
- ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
- ANA_BP_SMALL_BW;
-
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
- ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
- ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
- ANA_IECHO_ADJ_0_SHIFT);
-
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
- ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
- ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
-
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
- return;
- data &= ~ANA_TOP_PS_EN;
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
-
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
- if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
- return;
- data &= ~ANA_PS_HIB_EN;
- atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
- }
+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
+ phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
+ phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
+ GPHY_CTRL_HIB_EN | GPHY_CTRL_PHY_IDDQ |
+ GPHY_CTRL_PWDOWN_HW;
+ AT_WRITE_REGW(hw, REG_GPHY_CTRL, phy_ctrl_data);
}
+
int atl1c_phy_reset(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = hw->adapter;
struct pci_dev *pdev = adapter->pdev;
u16 phy_data;
- u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
- u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
+ u32 phy_ctrl_data, lpi_ctrl;
int err;
- if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
- phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
-
+ /* reset PHY core */
+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
+ phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_PHY_IDDQ |
+ GPHY_CTRL_GATE_25M_EN | GPHY_CTRL_PWDOWN_HW | GPHY_CTRL_CLS);
+ phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST;
+ if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE))
+ phy_ctrl_data |= (GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE);
+ else
+ phy_ctrl_data &= ~(GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE);
AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
AT_WRITE_FLUSH(hw);
- msleep(40);
- phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
- AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
+ udelay(10);
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data | GPHY_CTRL_EXT_RESET);
AT_WRITE_FLUSH(hw);
- msleep(10);
+ udelay(10 * GPHY_CTRL_EXT_RST_TO); /* delay 800us */
+ /* switch clock */
if (hw->nic_type == athr_l2c_b) {
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
- atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
+ atl1c_read_phy_dbg(hw, MIIDBG_CFGLPSPD, &phy_data);
+ atl1c_write_phy_dbg(hw, MIIDBG_CFGLPSPD,
+ phy_data & ~CFGLPSPD_RSTCNT_CLK125SW);
}
- if (hw->nic_type == athr_l2c_b ||
- hw->nic_type == athr_l2c_b2 ||
- hw->nic_type == athr_l1d ||
- hw->nic_type == athr_l1d_2) {
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
- atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
- msleep(20);
+ /* tx-half amplitude issue fix */
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
+ atl1c_read_phy_dbg(hw, MIIDBG_CABLE1TH_DET, &phy_data);
+ phy_data |= CABLE1TH_DET_EN;
+ atl1c_write_phy_dbg(hw, MIIDBG_CABLE1TH_DET, phy_data);
}
- if (hw->nic_type == athr_l1d) {
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x929D);
+
+ /* clear bit3 of dbgport 3B to lower voltage */
+ if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) {
+ if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) {
+ atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data);
+ phy_data &= ~VOLT_CTRL_SWLOWEST;
+ atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data);
+ }
+ /* power saving config */
+ phy_data =
+ hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ?
+ L1D_LEGCYPS_DEF : L1C_LEGCYPS_DEF;
+ atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, phy_data);
+ /* hib */
+ atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL,
+ SYSMODCTRL_IECHOADJ_DEF);
+ } else {
+ /* disable pws */
+ atl1c_read_phy_dbg(hw, MIIDBG_LEGCYPS, &phy_data);
+ atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS,
+ phy_data & ~LEGCYPS_EN);
+ /* disable hibernate */
+ atl1c_read_phy_dbg(hw, MIIDBG_HIBNEG, &phy_data);
+ atl1c_write_phy_dbg(hw, MIIDBG_HIBNEG,
+ phy_data & HIBNEG_PSHIB_EN);
}
- if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b2
- || hw->nic_type == athr_l2c) {
- atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
- atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
+ /* disable AZ(EEE) by default */
+ if (hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ||
+ hw->nic_type == athr_l2c_b2) {
+ AT_READ_REG(hw, REG_LPI_CTRL, &lpi_ctrl);
+ AT_WRITE_REG(hw, REG_LPI_CTRL, lpi_ctrl & ~LPI_CTRL_EN);
+ atl1c_write_phy_ext(hw, MIIEXT_ANEG, MIIEXT_LOCAL_EEEADV, 0);
+ atl1c_write_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL3,
+ L2CB_CLDCTRL3);
}
- err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
+
+ /* other debug port to set */
+ atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, ANACTRL_DEF);
+ atl1c_write_phy_dbg(hw, MIIDBG_SRDSYSMOD, SRDSYSMOD_DEF);
+ atl1c_write_phy_dbg(hw, MIIDBG_TST10BTCFG, TST10BTCFG_DEF);
+ /* UNH-IOL test issue, set bit7 */
+ atl1c_write_phy_dbg(hw, MIIDBG_TST100BTCFG,
+ TST100BTCFG_DEF | TST100BTCFG_LITCH_EN);
+
+ /* set phy interrupt mask */
+ phy_data = IER_LINK_UP | IER_LINK_DOWN;
+ err = atl1c_write_phy_reg(hw, MII_IER, phy_data);
if (err) {
if (netif_msg_hw(adapter))
dev_err(&pdev->dev,
"Error enable PHY linkChange Interrupt\n");
return err;
}
- if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
- atl1c_phy_magic_data(hw);
return 0;
}
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 113e67b..fba7eb5 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -60,6 +60,9 @@ int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
u16 reg_addr, u16 *phy_data);
int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
u16 reg_addr, u16 phy_data);
+int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
+int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
+
/* register definition */
#define REG_DEVICE_CAP 0x5C
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
@@ -222,41 +225,32 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
#define IRQ_MODRT_RX_TIMER_SHIFT 16
#define REG_GPHY_CTRL 0x140C
-#define GPHY_CTRL_EXT_RESET 0x1
-#define GPHY_CTRL_RTL_MODE 0x2
-#define GPHY_CTRL_LED_MODE 0x4
-#define GPHY_CTRL_ANEG_NOW 0x8
-#define GPHY_CTRL_REV_ANEG 0x10
-#define GPHY_CTRL_GATE_25M_EN 0x20
-#define GPHY_CTRL_LPW_EXIT 0x40
-#define GPHY_CTRL_PHY_IDDQ 0x80
-#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
-#define GPHY_CTRL_GIGA_DIS 0x200
-#define GPHY_CTRL_HIB_EN 0x400
-#define GPHY_CTRL_HIB_PULSE 0x800
-#define GPHY_CTRL_SEL_ANA_RST 0x1000
-#define GPHY_CTRL_PHY_PLL_ON 0x2000
-#define GPHY_CTRL_PWDOWN_HW 0x4000
-#define GPHY_CTRL_PHY_PLL_BYPASS 0x8000
-
-#define GPHY_CTRL_DEFAULT ( \
- GPHY_CTRL_SEL_ANA_RST |\
- GPHY_CTRL_HIB_PULSE |\
- GPHY_CTRL_HIB_EN)
-
-#define GPHY_CTRL_PW_WOL_DIS ( \
- GPHY_CTRL_SEL_ANA_RST |\
- GPHY_CTRL_HIB_PULSE |\
- GPHY_CTRL_HIB_EN |\
- GPHY_CTRL_PWDOWN_HW |\
- GPHY_CTRL_PHY_IDDQ)
-
-#define GPHY_CTRL_POWER_SAVING ( \
- GPHY_CTRL_SEL_ANA_RST |\
- GPHY_CTRL_HIB_EN |\
- GPHY_CTRL_HIB_PULSE |\
- GPHY_CTRL_PWDOWN_HW |\
- GPHY_CTRL_PHY_IDDQ)
+#define GPHY_CTRL_ADDR_MASK 0x1FUL
+#define GPHY_CTRL_ADDR_SHIFT 19
+#define GPHY_CTRL_BP_VLTGSW BIT(18)
+#define GPHY_CTRL_100AB_EN BIT(17)
+#define GPHY_CTRL_10AB_EN BIT(16)
+#define GPHY_CTRL_PHY_PLL_BYPASS BIT(15)
+#define GPHY_CTRL_PWDOWN_HW BIT(14) /* affect MAC&PHY, to low pw */
+#define GPHY_CTRL_PHY_PLL_ON BIT(13) /* 1:pll always on, 0:can sw */
+#define GPHY_CTRL_SEL_ANA_RST BIT(12)
+#define GPHY_CTRL_HIB_PULSE BIT(11)
+#define GPHY_CTRL_HIB_EN BIT(10)
+#define GPHY_CTRL_GIGA_DIS BIT(9)
+#define GPHY_CTRL_PHY_IDDQ_DIS BIT(8) /* pw on RST */
+#define GPHY_CTRL_PHY_IDDQ BIT(7) /* bit8 affect bit7 while rb */
+#define GPHY_CTRL_LPW_EXIT BIT(6)
+#define GPHY_CTRL_GATE_25M_EN BIT(5)
+#define GPHY_CTRL_REV_ANEG BIT(4)
+#define GPHY_CTRL_ANEG_NOW BIT(3)
+#define GPHY_CTRL_LED_MODE BIT(2)
+#define GPHY_CTRL_RTL_MODE BIT(1)
+#define GPHY_CTRL_EXT_RESET BIT(0) /* 1:out of DSP RST status */
+#define GPHY_CTRL_EXT_RST_TO 80 /* 800us atmost */
+#define GPHY_CTRL_CLS (\
+ GPHY_CTRL_LED_MODE |\
+ GPHY_CTRL_100AB_EN |\
+ GPHY_CTRL_PHY_PLL_ON)
/* Block IDLE Status Register */
#define REG_IDLE_STATUS 0x1410
@@ -350,6 +344,26 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
#define SERDES_LOCK_DETECT_EN BIT(1)
#define SERDES_LOCK_DETECT BIT(0)
+#define REG_LPI_DECISN_TIMER 0x143C
+#define L2CB_LPI_DESISN_TIMER 0x7D00
+
+#define REG_LPI_CTRL 0x1440
+#define LPI_CTRL_CHK_DA BIT(31)
+#define LPI_CTRL_ENH_TO_MASK 0x1FFFUL
+#define LPI_CTRL_ENH_TO_SHIFT 12
+#define LPI_CTRL_ENH_TH_MASK 0x1FUL
+#define LPI_CTRL_ENH_TH_SHIFT 6
+#define LPI_CTRL_ENH_EN BIT(5)
+#define LPI_CTRL_CHK_RX BIT(4)
+#define LPI_CTRL_CHK_STATE BIT(3)
+#define LPI_CTRL_GMII BIT(2)
+#define LPI_CTRL_TO_PHY BIT(1)
+#define LPI_CTRL_EN BIT(0)
+
+#define REG_LPI_WAIT 0x1444
+#define LPI_WAIT_TIMER_MASK 0xFFFFUL
+#define LPI_WAIT_TIMER_SHIFT 0
+
/* MAC Control Register */
#define REG_MAC_CTRL 0x1480
#define MAC_CTRL_TX_EN 0x1
@@ -813,73 +827,188 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
#define MII_DBG_ADDR 0x1D
#define MII_DBG_DATA 0x1E
-#define MII_ANA_CTRL_0 0x0
-#define ANA_RESTART_CAL 0x0001
-#define ANA_MANUL_SWICH_ON_SHIFT 0x1
-#define ANA_MANUL_SWICH_ON_MASK 0xF
-#define ANA_MAN_ENABLE 0x0020
-#define ANA_SEL_HSP 0x0040
-#define ANA_EN_HB 0x0080
-#define ANA_EN_HBIAS 0x0100
-#define ANA_OEN_125M 0x0200
-#define ANA_EN_LCKDT 0x0400
-#define ANA_LCKDT_PHY 0x0800
-#define ANA_AFE_MODE 0x1000
-#define ANA_VCO_SLOW 0x2000
-#define ANA_VCO_FAST 0x4000
-#define ANA_SEL_CLK125M_DSP 0x8000
+/***************************** debug port *************************************/
+
+#define MIIDBG_ANACTRL 0x00
+#define ANACTRL_CLK125M_DELAY_EN 0x8000
+#define ANACTRL_VCO_FAST 0x4000
+#define ANACTRL_VCO_SLOW 0x2000
+#define ANACTRL_AFE_MODE_EN 0x1000
+#define ANACTRL_LCKDET_PHY 0x800
+#define ANACTRL_LCKDET_EN 0x400
+#define ANACTRL_OEN_125M 0x200
+#define ANACTRL_HBIAS_EN 0x100
+#define ANACTRL_HB_EN 0x80
+#define ANACTRL_SEL_HSP 0x40
+#define ANACTRL_CLASSA_EN 0x20
+#define ANACTRL_MANUSWON_SWR_MASK 3U
+#define ANACTRL_MANUSWON_SWR_SHIFT 2
+#define ANACTRL_MANUSWON_SWR_2V 0
+#define ANACTRL_MANUSWON_SWR_1P9V 1
+#define ANACTRL_MANUSWON_SWR_1P8V 2
+#define ANACTRL_MANUSWON_SWR_1P7V 3
+#define ANACTRL_MANUSWON_BW3_4M 0x2
+#define ANACTRL_RESTART_CAL 0x1
+#define ANACTRL_DEF 0x02EF
+
+#define MIIDBG_SYSMODCTRL 0x04
+#define SYSMODCTRL_IECHOADJ_PFMH_PHY 0x8000
+#define SYSMODCTRL_IECHOADJ_BIASGEN 0x4000
+#define SYSMODCTRL_IECHOADJ_PFML_PHY 0x2000
+#define SYSMODCTRL_IECHOADJ_PS_MASK 3U
+#define SYSMODCTRL_IECHOADJ_PS_SHIFT 10
+#define SYSMODCTRL_IECHOADJ_PS_40 3
+#define SYSMODCTRL_IECHOADJ_PS_20 2
+#define SYSMODCTRL_IECHOADJ_PS_0 1
+#define SYSMODCTRL_IECHOADJ_10BT_100MV 0x40 /* 1:100mv, 0:200mv */
+#define SYSMODCTRL_IECHOADJ_HLFAP_MASK 3U
+#define SYSMODCTRL_IECHOADJ_HLFAP_SHIFT 4
+#define SYSMODCTRL_IECHOADJ_VDFULBW 0x8
+#define SYSMODCTRL_IECHOADJ_VDBIASHLF 0x4
+#define SYSMODCTRL_IECHOADJ_VDAMPHLF 0x2
+#define SYSMODCTRL_IECHOADJ_VDLANSW 0x1
+#define SYSMODCTRL_IECHOADJ_DEF 0x88BB /* ???? */
+
+/* for l1d & l2cb */
+#define SYSMODCTRL_IECHOADJ_CUR_ADD 0x8000
+#define SYSMODCTRL_IECHOADJ_CUR_MASK 7U
+#define SYSMODCTRL_IECHOADJ_CUR_SHIFT 12
+#define SYSMODCTRL_IECHOADJ_VOL_MASK 0xFU
+#define SYSMODCTRL_IECHOADJ_VOL_SHIFT 8
+#define SYSMODCTRL_IECHOADJ_VOL_17ALL 3
+#define SYSMODCTRL_IECHOADJ_VOL_100M15 1
+#define SYSMODCTRL_IECHOADJ_VOL_10M17 0
+#define SYSMODCTRL_IECHOADJ_BIAS1_MASK 0xFU
+#define SYSMODCTRL_IECHOADJ_BIAS1_SHIFT 4
+#define SYSMODCTRL_IECHOADJ_BIAS2_MASK 0xFU
+#define SYSMODCTRL_IECHOADJ_BIAS2_SHIFT 0
+#define L1D_SYSMODCTRL_IECHOADJ_DEF 0x4FBB
+
+#define MIIDBG_SRDSYSMOD 0x05
+#define SRDSYSMOD_LCKDET_EN 0x2000
+#define SRDSYSMOD_PLL_EN 0x800
+#define SRDSYSMOD_SEL_HSP 0x400
+#define SRDSYSMOD_HLFTXDR 0x200
+#define SRDSYSMOD_TXCLK_DELAY_EN 0x100
+#define SRDSYSMOD_TXELECIDLE 0x80
+#define SRDSYSMOD_DEEMP_EN 0x40
+#define SRDSYSMOD_MS_PAD 0x4
+#define SRDSYSMOD_CDR_ADC_VLTG 0x2
+#define SRDSYSMOD_CDR_DAC_1MA 0x1
+#define SRDSYSMOD_DEF 0x2C46
+
+#define MIIDBG_CFGLPSPD 0x0A
+#define CFGLPSPD_RSTCNT_MASK 3U
+#define CFGLPSPD_RSTCNT_SHIFT 14
+#define CFGLPSPD_RSTCNT_CLK125SW 0x2000
+
+#define MIIDBG_HIBNEG 0x0B
+#define HIBNEG_PSHIB_EN 0x8000
+#define HIBNEG_WAKE_BOTH 0x4000
+#define HIBNEG_ONOFF_ANACHG_SUDEN 0x2000
+#define HIBNEG_HIB_PULSE 0x1000
+#define HIBNEG_GATE_25M_EN 0x800
+#define HIBNEG_RST_80U 0x400
+#define HIBNEG_RST_TIMER_MASK 3U
+#define HIBNEG_RST_TIMER_SHIFT 8
+#define HIBNEG_GTX_CLK_DELAY_MASK 3U
+#define HIBNEG_GTX_CLK_DELAY_SHIFT 5
+#define HIBNEG_BYPSS_BRKTIMER 0x10
+#define HIBNEG_DEF 0xBC40
+
+#define MIIDBG_TST10BTCFG 0x12
+#define TST10BTCFG_INTV_TIMER_MASK 3U
+#define TST10BTCFG_INTV_TIMER_SHIFT 14
+#define TST10BTCFG_TRIGER_TIMER_MASK 3U
+#define TST10BTCFG_TRIGER_TIMER_SHIFT 12
+#define TST10BTCFG_DIV_MAN_MLT3_EN 0x800
+#define TST10BTCFG_OFF_DAC_IDLE 0x400
+#define TST10BTCFG_LPBK_DEEP 0x4 /* 1:deep,0:shallow */
+#define TST10BTCFG_DEF 0x4C04
+
+#define MIIDBG_AZ_ANADECT 0x15
+#define AZ_ANADECT_10BTRX_TH 0x8000
+#define AZ_ANADECT_BOTH_01CHNL 0x4000
+#define AZ_ANADECT_INTV_MASK 0x3FU
+#define AZ_ANADECT_INTV_SHIFT 8
+#define AZ_ANADECT_THRESH_MASK 0xFU
+#define AZ_ANADECT_THRESH_SHIFT 4
+#define AZ_ANADECT_CHNL_MASK 0xFU
+#define AZ_ANADECT_CHNL_SHIFT 0
+#define AZ_ANADECT_DEF 0x3220
+#define AZ_ANADECT_LONG 0xb210
+
+#define MIIDBG_MSE16DB 0x18 /* l1d */
+#define L1D_MSE16DB_UP 0x05EA
+#define L1D_MSE16DB_DOWN 0x02EA
+
+#define MIIDBG_LEGCYPS 0x29
+#define LEGCYPS_EN 0x8000
+#define LEGCYPS_DAC_AMP1000_MASK 7U
+#define LEGCYPS_DAC_AMP1000_SHIFT 12
+#define LEGCYPS_DAC_AMP100_MASK 7U
+#define LEGCYPS_DAC_AMP100_SHIFT 9
+#define LEGCYPS_DAC_AMP10_MASK 7U
+#define LEGCYPS_DAC_AMP10_SHIFT 6
+#define LEGCYPS_UNPLUG_TIMER_MASK 7U
+#define LEGCYPS_UNPLUG_TIMER_SHIFT 3
+#define LEGCYPS_UNPLUG_DECT_EN 0x4
+#define LEGCYPS_ECNC_PS_EN 0x1
+#define L1D_LEGCYPS_DEF 0x129D
+#define L1C_LEGCYPS_DEF 0x36DD
+
+#define MIIDBG_TST100BTCFG 0x36
+#define TST100BTCFG_NORMAL_BW_EN 0x8000
+#define TST100BTCFG_BADLNK_BYPASS 0x4000
+#define TST100BTCFG_SHORTCABL_TH_MASK 0x3FU
+#define TST100BTCFG_SHORTCABL_TH_SHIFT 8
+#define TST100BTCFG_LITCH_EN 0x80
+#define TST100BTCFG_VLT_SW 0x40
+#define TST100BTCFG_LONGCABL_TH_MASK 0x3FU
+#define TST100BTCFG_LONGCABL_TH_SHIFT 0
+#define TST100BTCFG_DEF 0xE12C
+
+#define MIIDBG_VOLT_CTRL 0x3B /* only for l2cb 1 & 2 */
+#define VOLT_CTRL_CABLE1TH_MASK 0x1FFU
+#define VOLT_CTRL_CABLE1TH_SHIFT 7
+#define VOLT_CTRL_AMPCTRL_MASK 3U
+#define VOLT_CTRL_AMPCTRL_SHIFT 5
+#define VOLT_CTRL_SW_BYPASS 0x10
+#define VOLT_CTRL_SWLOWEST 0x8
+#define VOLT_CTRL_DACAMP10_MASK 7U
+#define VOLT_CTRL_DACAMP10_SHIFT 0
+
+#define MIIDBG_CABLE1TH_DET 0x3E
+#define CABLE1TH_DET_EN 0x8000
+
+
+/******* dev 3 *********/
+#define MIIEXT_PCS 3
-#define MII_ANA_CTRL_4 0x4
-#define ANA_IECHO_ADJ_MASK 0xF
-#define ANA_IECHO_ADJ_3_SHIFT 0
-#define ANA_IECHO_ADJ_2_SHIFT 4
-#define ANA_IECHO_ADJ_1_SHIFT 8
-#define ANA_IECHO_ADJ_0_SHIFT 12
+#define MIIEXT_CLDCTRL3 0x8003
+#define CLDCTRL3_BP_CABLE1TH_DET_GT 0x8000
+#define CLDCTRL3_AZ_DISAMP 0x1000
+#define L2CB_CLDCTRL3 0x4D19
+#define L1D_CLDCTRL3 0xDD19
-#define MII_ANA_CTRL_5 0x5
-#define ANA_SERDES_CDR_BW_SHIFT 0
-#define ANA_SERDES_CDR_BW_MASK 0x3
-#define ANA_MS_PAD_DBG 0x0004
-#define ANA_SPEEDUP_DBG 0x0008
-#define ANA_SERDES_TH_LOS_SHIFT 4
-#define ANA_SERDES_TH_LOS_MASK 0x3
-#define ANA_SERDES_EN_DEEM 0x0040
-#define ANA_SERDES_TXELECIDLE 0x0080
-#define ANA_SERDES_BEACON 0x0100
-#define ANA_SERDES_HALFTXDR 0x0200
-#define ANA_SERDES_SEL_HSP 0x0400
-#define ANA_SERDES_EN_PLL 0x0800
-#define ANA_SERDES_EN 0x1000
-#define ANA_SERDES_EN_LCKDT 0x2000
+#define MIIEXT_CLDCTRL6 0x8006
+#define CLDCTRL6_CAB_LEN_MASK 0x1FFU
+#define CLDCTRL6_CAB_LEN_SHIFT 0
+#define CLDCTRL6_CAB_LEN_SHORT 0x50
-#define MII_ANA_CTRL_11 0xB
-#define ANA_PS_HIB_EN 0x8000
+/********* dev 7 **********/
+#define MIIEXT_ANEG 7
-#define MII_ANA_CTRL_18 0x12
-#define ANA_TEST_MODE_10BT_01SHIFT 0
-#define ANA_TEST_MODE_10BT_01MASK 0x3
-#define ANA_LOOP_SEL_10BT 0x0004
-#define ANA_RGMII_MODE_SW 0x0008
-#define ANA_EN_LONGECABLE 0x0010
-#define ANA_TEST_MODE_10BT_2 0x0020
-#define ANA_EN_10BT_IDLE 0x0400
-#define ANA_EN_MASK_TB 0x0800
-#define ANA_TRIGGER_SEL_TIMER_SHIFT 12
-#define ANA_TRIGGER_SEL_TIMER_MASK 0x3
-#define ANA_INTERVAL_SEL_TIMER_SHIFT 14
-#define ANA_INTERVAL_SEL_TIMER_MASK 0x3
+#define MIIEXT_LOCAL_EEEADV 0x3C
+#define LOCAL_EEEADV_1000BT 0x4
+#define LOCAL_EEEADV_100BT 0x2
-#define MII_ANA_CTRL_41 0x29
-#define ANA_TOP_PS_EN 0x8000
+#define MIIEXT_REMOTE_EEEADV 0x3D
+#define REMOTE_EEEADV_1000BT 0x4
+#define REMOTE_EEEADV_100BT 0x2
-#define MII_ANA_CTRL_54 0x36
-#define ANA_LONG_CABLE_TH_100_SHIFT 0
-#define ANA_LONG_CABLE_TH_100_MASK 0x3F
-#define ANA_DESERVED 0x0040
-#define ANA_EN_LIT_CH 0x0080
-#define ANA_SHORT_CABLE_TH_100_SHIFT 8
-#define ANA_SHORT_CABLE_TH_100_MASK 0x3F
-#define ANA_BP_BAD_LINK_ACCUM 0x4000
-#define ANA_BP_SMALL_BW 0x8000
+#define MIIEXT_EEE_ANEG 0x8000
+#define EEE_ANEG_1000M 0x4
+#define EEE_ANEG_100M 0x2
#endif /*_ATL1C_HW_H_*/
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 8a1d2f9..995da22 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -2314,6 +2314,7 @@ static int atl1c_suspend(struct device *dev)
u32 wol_ctrl_data = 0;
u16 mii_intr_status_data = 0;
u32 wufc = adapter->wol;
+ u32 phy_ctrl_data;
atl1c_disable_l0s_l1(hw);
if (netif_running(netdev)) {
@@ -2328,6 +2329,7 @@ static int atl1c_suspend(struct device *dev)
AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
@@ -2336,9 +2338,13 @@ static int atl1c_suspend(struct device *dev)
MAC_CTRL_PRMLEN_SHIFT);
mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
mac_ctrl_data &= ~MAC_CTRL_DUPLX;
+ phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
+ phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
+ GPHY_CTRL_HIB_EN;
if (wufc) {
mac_ctrl_data |= MAC_CTRL_RX_EN;
+ phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
if (adapter->link_speed == SPEED_1000 ||
adapter->link_speed == SPEED_0) {
mac_ctrl_data |= atl1c_mac_speed_1000 <<
@@ -2381,23 +2387,20 @@ static int atl1c_suspend(struct device *dev)
dev_dbg(&pdev->dev,
"%s: suspend MAC=0x%x\n",
atl1c_driver_name, mac_ctrl_data);
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
- AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
-
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
- GPHY_CTRL_EXT_RESET);
} else {
- AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
mac_ctrl_data |= MAC_CTRL_DUPLX;
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
- AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
+ phy_ctrl_data |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW;
+ wol_ctrl_data = 0;
hw->phy_configured = false; /* re-init PHY when resume */
}
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
+ AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
+
return 0;
}
--
1.7.7
^ permalink raw reply related
* [PATCH 00/10] atl1c: update hardware settings - v3
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
This update contains a serial of patches, most of them are hardware
settings related. register definitions are refined (or removed if
meaningless) for each patch.
This is the third serial patches, after reviewed/applied the fourth
serial will be out.
The patches have addressed all sparse and checkpatch warnings.
Following NICs are tested:
AR8131/AR8132/AR8151A/AR8152A/AR8152B
Test item includes:
build/install/uninstall/dhcp/ping/iperf/wol/reboot/etc.
xiong (10):
atl1c: remove REG_PHY_STATUS
atl1c: refine phy-register read/write function
atl1c: remove PHY contrl in atl1c_reset_pcie
atl1c: refine SERDES-clock related code
atl1c: remove PHY polling from atl1c_open
atl1c: update PHY reset related routine
atl1c: remove PHY reset/init for link down event
atl1c: add function atl1c_power_saving
atl1c: refine start/enable code for MAC module
atl1c: add flag of PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c | 2 +-
drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 428 ++++++++++++-----
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 501 +++++++++++++-------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 240 +++-------
4 files changed, 700 insertions(+), 471 deletions(-)
--
1.7.7
^ permalink raw reply
* [PATCH 04/10] atl1c: refine SERDES-clock related code
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
bit 17/18 of reg1424 must be clear for l2cb 1.x, or it will cause
the write-reg operation fail without cable connected.
so, please do connect the cable when apply this patch to the driver
to make sure these 2bits are cleared by new driver.
The revised code is move to al1c_reset_mac.
SERDES register definition is refined as well.
when do reset MAC, speed/duplex control right should be transferred
to software before do PHY auto-neg -- by bit MASTER_CTRL_SPEED_MODE_SW.
SERDES register definition is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c | 2 +-
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 34 +++++++++++------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 40 +++++++++++++-------
3 files changed, 49 insertions(+), 27 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
index 3feb846..859ea84 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_ethtool.c
@@ -153,7 +153,7 @@ static void atl1c_get_regs(struct net_device *netdev,
AT_READ_REG(hw, REG_LINK_CTRL, p++);
AT_READ_REG(hw, REG_IDLE_STATUS, p++);
AT_READ_REG(hw, REG_MDIO_CTRL, p++);
- AT_READ_REG(hw, REG_SERDES_LOCK, p++);
+ AT_READ_REG(hw, REG_SERDES, p++);
AT_READ_REG(hw, REG_MAC_CTRL, p++);
AT_READ_REG(hw, REG_MAC_IPG_IFG, p++);
AT_READ_REG(hw, REG_MAC_STA_ADDR, p++);
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index cb2d20b..113e67b 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -327,18 +327,28 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
#define BIST1_FUSE_FLAG 0x4
/* SerDes Lock Detect Control and Status Register */
-#define REG_SERDES_LOCK 0x1424
-#define SERDES_LOCK_DETECT 0x1 /* SerDes lock detected. This signal
- * comes from Analog SerDes */
-#define SERDES_LOCK_DETECT_EN 0x2 /* 1: Enable SerDes Lock detect function */
-#define SERDES_LOCK_STS_SELFB_PLL_SHIFT 0xE
-#define SERDES_LOCK_STS_SELFB_PLL_MASK 0x3
-#define SERDES_OVCLK_18_25 0x0
-#define SERDES_OVCLK_12_18 0x1
-#define SERDES_OVCLK_0_4 0x2
-#define SERDES_OVCLK_4_12 0x3
-#define SERDES_MAC_CLK_SLOWDOWN 0x20000
-#define SERDES_PYH_CLK_SLOWDOWN 0x40000
+#define REG_SERDES 0x1424
+#define SERDES_PHY_CLK_SLOWDOWN BIT(18)
+#define SERDES_MAC_CLK_SLOWDOWN BIT(17)
+#define SERDES_SELFB_PLL_MASK 0x3UL
+#define SERDES_SELFB_PLL_SHIFT 14
+#define SERDES_PHYCLK_SEL_GTX BIT(13) /* 1:gtx_clk, 0:25M */
+#define SERDES_PCIECLK_SEL_SRDS BIT(12) /* 1:serdes,0:25M */
+#define SERDES_BUFS_RX_EN BIT(11)
+#define SERDES_PD_RX BIT(10)
+#define SERDES_PLL_EN BIT(9)
+#define SERDES_EN BIT(8)
+#define SERDES_SELFB_PLL_SEL_CSR BIT(6) /* 0:state-machine,1:csr */
+#define SERDES_SELFB_PLL_CSR_MASK 0x3UL
+#define SERDES_SELFB_PLL_CSR_SHIFT 4
+#define SERDES_SELFB_PLL_CSR_4 3 /* 4-12% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_0 2 /* 0-4% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_12 1 /* 12-18% OV-CLK */
+#define SERDES_SELFB_PLL_CSR_18 0 /* 18-25% OV-CLK */
+#define SERDES_VCO_SLOW BIT(3)
+#define SERDES_VCO_FAST BIT(2)
+#define SERDES_LOCK_DETECT_EN BIT(1)
+#define SERDES_LOCK_DETECT BIT(0)
/* MAC Control Register */
#define REG_MAC_CTRL 0x1480
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index f0f348b..cf78287 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -1008,7 +1008,6 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
adapter->tpd_ring;
- u32 data;
/* TPD */
AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
@@ -1052,13 +1051,6 @@ static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
}
- if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
- /* Power Saving for L2c_B */
- AT_READ_REG(hw, REG_SERDES_LOCK, &data);
- data |= SERDES_MAC_CLK_SLOWDOWN;
- data |= SERDES_PYH_CLK_SLOWDOWN;
- AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
- }
/* Load all of base address above */
AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
}
@@ -1177,7 +1169,7 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
struct pci_dev *pdev = adapter->pdev;
- u32 master_ctrl_data = 0;
+ u32 ctrl_data = 0;
AT_WRITE_REG(hw, REG_IMR, 0);
AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
@@ -1189,10 +1181,9 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
- AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
- master_ctrl_data |= MASTER_CTRL_OOB_DIS;
- AT_WRITE_REG(hw, REG_MASTER_CTRL,
- master_ctrl_data | MASTER_CTRL_SOFT_RST);
+ AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
+ ctrl_data |= MASTER_CTRL_OOB_DIS;
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
AT_WRITE_FLUSH(hw);
msleep(10);
@@ -1204,7 +1195,28 @@ static int atl1c_reset_mac(struct atl1c_hw *hw)
" disabled for 10ms second\n");
return -1;
}
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
+
+ /* driver control speed/duplex */
+ AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
+
+ /* clk switch setting */
+ AT_READ_REG(hw, REG_SERDES, &ctrl_data);
+ switch (hw->nic_type) {
+ case athr_l2c_b:
+ ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
+ SERDES_MAC_CLK_SLOWDOWN);
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
+ break;
+ case athr_l2c_b2:
+ case athr_l1d_2:
+ ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
+ AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
+ break;
+ default:
+ break;
+ }
return 0;
}
--
1.7.7
^ permalink raw reply related
* [PATCH 07/10] atl1c: remove PHY reset/init for link down event
From: xiong @ 2012-04-26 6:27 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335421638-16304-1-git-send-email-xiong@qca.qualcomm.com>
it's unnecessary to reset/init phy when link down.
Only L1/L2 chip (supported by atlx) need such action.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 995da22..cb3b3c4 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -270,8 +270,6 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
atl1c_set_aspm(hw, SPEED_0);
netif_carrier_off(netdev);
netif_stop_queue(netdev);
- atl1c_phy_reset(hw);
- atl1c_phy_init(&adapter->hw);
} else {
/* Link Up */
hw->hibernate = false;
--
1.7.7
^ permalink raw reply related
* [PATCH 09/10] atl1c: refine start/enable code for MAC module
From: xiong @ 2012-04-26 6:41 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335422461-16588-1-git-send-email-xiong@qca.qualcomm.com>
merge TXQ/RXQ/MAC start/enable code to one function as they
are started/enabled at the same time, just like stop/disable them
in the function of atl1c_stop_mac.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 89 +++++++----------------
1 files changed, 28 insertions(+), 61 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index d03112c..25b7b00 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -53,11 +53,9 @@ MODULE_LICENSE("GPL");
MODULE_VERSION(ATL1C_DRV_VERSION);
static int atl1c_stop_mac(struct atl1c_hw *hw);
-static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
-static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
-static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
+static void atl1c_start_mac(struct atl1c_adapter *adapter);
static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
int *work_done, int work_to_do);
static int atl1c_up(struct atl1c_adapter *adapter);
@@ -276,9 +274,7 @@ static void atl1c_check_link_status(struct atl1c_adapter *adapter)
adapter->link_speed = speed;
adapter->link_duplex = duplex;
atl1c_set_aspm(hw, speed);
- atl1c_enable_tx_ctrl(hw);
- atl1c_enable_rx_ctrl(hw);
- atl1c_setup_mac_ctrl(adapter);
+ atl1c_start_mac(adapter);
if (netif_msg_link(adapter))
dev_info(&pdev->dev,
"%s: %s NIC Link is Up<%d Mbps %s>\n",
@@ -1132,22 +1128,36 @@ static int atl1c_stop_mac(struct atl1c_hw *hw)
IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
}
-static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
+static void atl1c_start_mac(struct atl1c_adapter *adapter)
{
- u32 data;
+ struct atl1c_hw *hw = &adapter->hw;
+ u32 mac, txq, rxq;
- AT_READ_REG(hw, REG_RXQ_CTRL, &data);
- data |= RXQ_CTRL_EN;
- AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
-}
+ hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
+ hw->mac_speed = adapter->link_speed == SPEED_1000 ?
+ atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
-static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
-{
- u32 data;
+ AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
+ AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
+ AT_READ_REG(hw, REG_MAC_CTRL, &mac);
- AT_READ_REG(hw, REG_TXQ_CTRL, &data);
- data |= TXQ_CTRL_EN;
- AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
+ txq |= TXQ_CTRL_EN;
+ rxq |= RXQ_CTRL_EN;
+ mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
+ MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
+ MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
+ MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
+ MAC_CTRL_HASH_ALG_CRC32;
+ if (hw->mac_duplex)
+ mac |= MAC_CTRL_DUPLX;
+ else
+ mac &= ~MAC_CTRL_DUPLX;
+ mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
+ mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
+
+ AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
+ AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
}
/*
@@ -1296,49 +1306,6 @@ static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
return;
}
-static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
-{
- struct atl1c_hw *hw = &adapter->hw;
- struct net_device *netdev = adapter->netdev;
- u32 mac_ctrl_data;
-
- mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
- mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
-
- if (adapter->link_duplex == FULL_DUPLEX) {
- hw->mac_duplex = true;
- mac_ctrl_data |= MAC_CTRL_DUPLX;
- }
-
- if (adapter->link_speed == SPEED_1000)
- hw->mac_speed = atl1c_mac_speed_1000;
- else
- hw->mac_speed = atl1c_mac_speed_10_100;
-
- mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
- MAC_CTRL_SPEED_SHIFT;
-
- mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
- mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
- MAC_CTRL_PRMLEN_SHIFT);
-
- __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
-
- mac_ctrl_data |= MAC_CTRL_BC_EN;
- if (netdev->flags & IFF_PROMISC)
- mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
- if (netdev->flags & IFF_ALLMULTI)
- mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
-
- mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
- if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
- hw->nic_type == athr_l1d_2) {
- mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
- mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
- }
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
-}
-
/*
* atl1c_configure - Configure Transmit&Receive Unit after Reset
* @adapter: board private structure
--
1.7.7
^ permalink raw reply related
* [PATCH 08/10] atl1c: add function atl1c_power_saving
From: xiong @ 2012-04-26 6:40 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
This function is used for suspend of S1/S3/S4 and driver remove.
It sets MAC/PHY based on the WoL configuation to get lower power
consumption.
atl1c_phy_power_saving is renamed to atl1c_phy_to_ps_link, this
function is just make PHY enter a link/speed mode to eat less
power.
REG_MAC_CTRL register is refined as well.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.c | 73 ++++++++++++++++---
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h | 72 +++++++++++--------
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 89 +----------------------
3 files changed, 108 insertions(+), 126 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
index 9a5b0f3..07f017f 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
@@ -525,14 +525,7 @@ static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
void atl1c_phy_disable(struct atl1c_hw *hw)
{
- u32 phy_ctrl_data;
-
- AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
- phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
- phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
- GPHY_CTRL_HIB_EN | GPHY_CTRL_PHY_IDDQ |
- GPHY_CTRL_PWDOWN_HW;
- AT_WRITE_REGW(hw, REG_GPHY_CTRL, phy_ctrl_data);
+ atl1c_power_saving(hw, 0);
}
@@ -722,7 +715,8 @@ int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
return 0;
}
-int atl1c_phy_power_saving(struct atl1c_hw *hw)
+/* select one link mode to get lower power consumption */
+int atl1c_phy_to_ps_link(struct atl1c_hw *hw)
{
struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
struct pci_dev *pdev = adapter->pdev;
@@ -793,3 +787,64 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw)
return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
}
+
+int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc)
+{
+ struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
+ struct pci_dev *pdev = adapter->pdev;
+ u32 master_ctrl, mac_ctrl, phy_ctrl;
+ u32 wol_ctrl, speed;
+ u16 phy_data;
+
+ wol_ctrl = 0;
+ speed = adapter->link_speed == SPEED_1000 ?
+ MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100;
+
+ AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl);
+ AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl);
+ AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl);
+
+ master_ctrl &= ~MASTER_CTRL_CLK_SEL_DIS;
+ mac_ctrl = FIELD_SETX(mac_ctrl, MAC_CTRL_SPEED, speed);
+ mac_ctrl &= ~(MAC_CTRL_DUPLX | MAC_CTRL_RX_EN | MAC_CTRL_TX_EN);
+ if (adapter->link_duplex == FULL_DUPLEX)
+ mac_ctrl |= MAC_CTRL_DUPLX;
+ phy_ctrl &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
+ phy_ctrl |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
+ GPHY_CTRL_HIB_EN;
+ if (!wufc) { /* without WoL */
+ master_ctrl |= MASTER_CTRL_CLK_SEL_DIS;
+ phy_ctrl |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW;
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
+ AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
+ hw->phy_configured = false; /* re-init PHY when resume */
+ return 0;
+ }
+ phy_ctrl |= GPHY_CTRL_EXT_RESET;
+ if (wufc & AT_WUFC_MAG) {
+ mac_ctrl |= MAC_CTRL_RX_EN | MAC_CTRL_BC_EN;
+ wol_ctrl |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
+ if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V11)
+ wol_ctrl |= WOL_PATTERN_EN | WOL_PATTERN_PME_EN;
+ }
+ if (wufc & AT_WUFC_LNKC) {
+ wol_ctrl |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
+ if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
+ dev_dbg(&pdev->dev, "%s: write phy MII_IER faild.\n",
+ atl1c_driver_name);
+ }
+ }
+ /* clear PHY interrupt */
+ atl1c_read_phy_reg(hw, MII_ISR, &phy_data);
+
+ dev_dbg(&pdev->dev, "%s: suspend MAC=%x,MASTER=%x,PHY=0x%x,WOL=%x\n",
+ atl1c_driver_name, mac_ctrl, master_ctrl, phy_ctrl, wol_ctrl);
+ AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl);
+ AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl);
+ AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl);
+ AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl);
+
+ return 0;
+}
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index fba7eb5..0adb341 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -48,7 +48,8 @@ bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value);
int atl1c_phy_init(struct atl1c_hw *hw);
int atl1c_check_eeprom_exist(struct atl1c_hw *hw);
int atl1c_restart_autoneg(struct atl1c_hw *hw);
-int atl1c_phy_power_saving(struct atl1c_hw *hw);
+int atl1c_phy_to_ps_link(struct atl1c_hw *hw);
+int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc);
bool atl1c_wait_mdio_idle(struct atl1c_hw *hw);
void atl1c_stop_phy_polling(struct atl1c_hw *hw);
void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
@@ -63,6 +64,16 @@ int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr,
int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data);
int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
+/* hw-ids */
+#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
+#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
+#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
+#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
+#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
+#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
+#define L2CB_V10 0xc0
+#define L2CB_V11 0xc1
+
/* register definition */
#define REG_DEVICE_CAP 0x5C
#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
@@ -366,35 +377,36 @@ int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data);
/* MAC Control Register */
#define REG_MAC_CTRL 0x1480
-#define MAC_CTRL_TX_EN 0x1
-#define MAC_CTRL_RX_EN 0x2
-#define MAC_CTRL_TX_FLOW 0x4
-#define MAC_CTRL_RX_FLOW 0x8
-#define MAC_CTRL_LOOPBACK 0x10
-#define MAC_CTRL_DUPLX 0x20
-#define MAC_CTRL_ADD_CRC 0x40
-#define MAC_CTRL_PAD 0x80
-#define MAC_CTRL_LENCHK 0x100
-#define MAC_CTRL_HUGE_EN 0x200
-#define MAC_CTRL_PRMLEN_SHIFT 10
-#define MAC_CTRL_PRMLEN_MASK 0xf
-#define MAC_CTRL_RMV_VLAN 0x4000
-#define MAC_CTRL_PROMIS_EN 0x8000
-#define MAC_CTRL_TX_PAUSE 0x10000
-#define MAC_CTRL_SCNT 0x20000
-#define MAC_CTRL_SRST_TX 0x40000
-#define MAC_CTRL_TX_SIMURST 0x80000
-#define MAC_CTRL_SPEED_SHIFT 20
-#define MAC_CTRL_SPEED_MASK 0x3
-#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
-#define MAC_CTRL_TX_HUGE 0x800000
-#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
-#define MAC_CTRL_MC_ALL_EN 0x2000000
-#define MAC_CTRL_BC_EN 0x4000000
-#define MAC_CTRL_DBG 0x8000000
-#define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
-#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
-#define MAC_CTRL_SPEED_MODE_SW 0x40000000
+#define MAC_CTRL_SPEED_MODE_SW BIT(30) /* 0:phy,1:sw */
+#define MAC_CTRL_HASH_ALG_CRC32 BIT(29) /* 1:legacy,0:lw_5b */
+#define MAC_CTRL_SINGLE_PAUSE_EN BIT(28)
+#define MAC_CTRL_DBG BIT(27)
+#define MAC_CTRL_BC_EN BIT(26)
+#define MAC_CTRL_MC_ALL_EN BIT(25)
+#define MAC_CTRL_RX_CHKSUM_EN BIT(24)
+#define MAC_CTRL_TX_HUGE BIT(23)
+#define MAC_CTRL_DBG_TX_BKPRESURE BIT(22)
+#define MAC_CTRL_SPEED_MASK 3UL
+#define MAC_CTRL_SPEED_SHIFT 20
+#define MAC_CTRL_SPEED_10_100 1
+#define MAC_CTRL_SPEED_1000 2
+#define MAC_CTRL_TX_SIMURST BIT(19)
+#define MAC_CTRL_SCNT BIT(17)
+#define MAC_CTRL_TX_PAUSE BIT(16)
+#define MAC_CTRL_PROMIS_EN BIT(15)
+#define MAC_CTRL_RMV_VLAN BIT(14)
+#define MAC_CTRL_PRMLEN_MASK 0xFUL
+#define MAC_CTRL_PRMLEN_SHIFT 10
+#define MAC_CTRL_HUGE_EN BIT(9)
+#define MAC_CTRL_LENCHK BIT(8)
+#define MAC_CTRL_PAD BIT(7)
+#define MAC_CTRL_ADD_CRC BIT(6)
+#define MAC_CTRL_DUPLX BIT(5)
+#define MAC_CTRL_LOOPBACK BIT(4)
+#define MAC_CTRL_RX_FLOW BIT(3)
+#define MAC_CTRL_TX_FLOW BIT(2)
+#define MAC_CTRL_RX_EN BIT(1)
+#define MAC_CTRL_TX_EN BIT(0)
/* MAC IPG/IFG Control Register */
#define REG_MAC_IPG_IFG 0x1484
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index cb3b3c4..d03112c 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -24,14 +24,6 @@
#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
char atl1c_driver_name[] = "atl1c";
char atl1c_driver_version[] = ATL1C_DRV_VERSION;
-#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
-#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
-#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
-#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
-#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
-#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
-#define L2CB_V10 0xc0
-#define L2CB_V11 0xc1
/*
* atl1c_pci_tbl - PCI Device ID Table
@@ -2307,12 +2299,7 @@ static int atl1c_suspend(struct device *dev)
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1c_adapter *adapter = netdev_priv(netdev);
struct atl1c_hw *hw = &adapter->hw;
- u32 mac_ctrl_data = 0;
- u32 master_ctrl_data = 0;
- u32 wol_ctrl_data = 0;
- u16 mii_intr_status_data = 0;
u32 wufc = adapter->wol;
- u32 phy_ctrl_data;
atl1c_disable_l0s_l1(hw);
if (netif_running(netdev)) {
@@ -2322,82 +2309,10 @@ static int atl1c_suspend(struct device *dev)
netif_device_detach(netdev);
if (wufc)
- if (atl1c_phy_power_saving(hw) != 0)
+ if (atl1c_phy_to_ps_link(hw) != 0)
dev_dbg(&pdev->dev, "phy power saving failed");
- AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
- AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
- AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
-
- master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
- mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
- mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
- MAC_CTRL_PRMLEN_MASK) <<
- MAC_CTRL_PRMLEN_SHIFT);
- mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
- mac_ctrl_data &= ~MAC_CTRL_DUPLX;
- phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
- phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
- GPHY_CTRL_HIB_EN;
-
- if (wufc) {
- mac_ctrl_data |= MAC_CTRL_RX_EN;
- phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
- if (adapter->link_speed == SPEED_1000 ||
- adapter->link_speed == SPEED_0) {
- mac_ctrl_data |= atl1c_mac_speed_1000 <<
- MAC_CTRL_SPEED_SHIFT;
- mac_ctrl_data |= MAC_CTRL_DUPLX;
- } else
- mac_ctrl_data |= atl1c_mac_speed_10_100 <<
- MAC_CTRL_SPEED_SHIFT;
-
- if (adapter->link_duplex == DUPLEX_FULL)
- mac_ctrl_data |= MAC_CTRL_DUPLX;
-
- /* turn on magic packet wol */
- if (wufc & AT_WUFC_MAG) {
- wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
- if (hw->nic_type == athr_l2c_b &&
- hw->revision_id == L2CB_V11) {
- wol_ctrl_data |=
- WOL_PATTERN_EN | WOL_PATTERN_PME_EN;
- }
- }
- if (wufc & AT_WUFC_LNKC) {
- wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
- /* only link up can wake up */
- if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
- dev_dbg(&pdev->dev, "%s: read write phy "
- "register failed.\n",
- atl1c_driver_name);
- }
- }
- /* clear phy interrupt */
- atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
- /* Config MAC Ctrl register */
- __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
-
- /* magic packet maybe Broadcast&multicast&Unicast frame */
- if (wufc & AT_WUFC_MAG)
- mac_ctrl_data |= MAC_CTRL_BC_EN;
-
- dev_dbg(&pdev->dev,
- "%s: suspend MAC=0x%x\n",
- atl1c_driver_name, mac_ctrl_data);
- } else {
- master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
- mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
- mac_ctrl_data |= MAC_CTRL_DUPLX;
- phy_ctrl_data |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW;
- wol_ctrl_data = 0;
- hw->phy_configured = false; /* re-init PHY when resume */
- }
-
- AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
- AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
- AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
- AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
+ atl1c_power_saving(hw, wufc);
return 0;
}
--
1.7.7
^ permalink raw reply related
* [PATCH 10/10] atl1c: add flag of PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
From: xiong @ 2012-04-26 6:41 UTC (permalink / raw)
To: davem, netdev, linux-kernel; +Cc: qca-linux-team, nic-devel, xiong
In-Reply-To: <1335422461-16588-1-git-send-email-xiong@qca.qualcomm.com>
supported devices all have one issue that msi interrupt doesn't assert
if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set.
that bit should be effect only for INTx style interrupt.
Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
---
drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
index 25b7b00..07b6018 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
@@ -2434,6 +2434,7 @@ static int __devinit atl1c_probe(struct pci_dev *pdev,
dev_err(&pdev->dev, "cannot map device registers\n");
goto err_ioremap;
}
+ pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
/* init mii data */
adapter->mii.dev = netdev;
--
1.7.7
^ permalink raw reply related
* Re: [PATCH 1/8] isdn/gigaset: ratelimit CAPI message dumps
From: Karsten Keil @ 2012-04-26 6:39 UTC (permalink / raw)
To: Tilman Schmidt
Cc: Karsten Keil, David Miller, Hansjoerg Lipp, i4ldeveloper, netdev,
linux-kernel
In-Reply-To: <20120425-patch-gigaset-01.tilman@imap.cc>
Am 26.04.2012 01:02, schrieb Tilman Schmidt:
> Introduce a global ratelimit for CAPI message dumps to protect
> against possible log flood.
> Drop the ratelimit for ignored messages which is now covered by the
> global one.
>
Hmm, I think the only CAPI messages which would need a ratelimit are
related to the DATA_B3 messages. If you need CAPI debug messages in most
cases you do not need all of the DATA_B3, but you do not want to miss
any other message related to the call control. With a general rate limit
you do not have the control, which messages are logged and which are not.
And here maybe some cases, when even the DATA_B3 are important (e.g.
searching bugs in flow control), so I would make it still conditional
to allow to print all messages.
And I'm not sure, if this is really something for stable.
> Signed-off-by: Tilman Schmidt <tilman@imap.cc>
> CC: stable <stable@kernel.org>
> ---
> drivers/isdn/gigaset/capi.c | 22 +++++++++-------------
> 1 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/isdn/gigaset/capi.c b/drivers/isdn/gigaset/capi.c
> index 343b5c8..292ca2f 100644
> --- a/drivers/isdn/gigaset/capi.c
> +++ b/drivers/isdn/gigaset/capi.c
> @@ -14,6 +14,7 @@
> #include "gigaset.h"
> #include <linux/proc_fs.h>
> #include <linux/seq_file.h>
> +#include <linux/ratelimit.h>
> #include <linux/isdn/capilli.h>
> #include <linux/isdn/capicmd.h>
> #include <linux/isdn/capiutil.h>
> @@ -223,10 +224,14 @@ get_appl(struct gigaset_capi_ctr *iif, u16 appl)
> static inline void dump_cmsg(enum debuglevel level, const char *tag, _cmsg *p)
> {
> #ifdef CONFIG_GIGASET_DEBUG
> + /* dump at most 20 messages in 20 secs */
> + static DEFINE_RATELIMIT_STATE(msg_dump_ratelimit, 20 * HZ, 20);
> _cdebbuf *cdb;
>
> if (!(gigaset_debuglevel & level))
> return;
> + if (!___ratelimit(&msg_dump_ratelimit, tag))
> + return;
>
> cdb = capi_cmsg2str(p);
> if (cdb) {
> @@ -2059,12 +2064,6 @@ static void do_reset_b3_req(struct gigaset_capi_ctr *iif,
> }
>
> /*
> - * dump unsupported/ignored messages at most twice per minute,
> - * some apps send those very frequently
> - */
> -static unsigned long ignored_msg_dump_time;
> -
> -/*
> * unsupported CAPI message handler
> */
> static void do_unsupported(struct gigaset_capi_ctr *iif,
> @@ -2073,8 +2072,7 @@ static void do_unsupported(struct gigaset_capi_ctr *iif,
> {
> /* decode message */
> capi_message2cmsg(&iif->acmsg, skb->data);
> - if (printk_timed_ratelimit(&ignored_msg_dump_time, 30 * 1000))
> - dump_cmsg(DEBUG_CMD, __func__, &iif->acmsg);
> + dump_cmsg(DEBUG_CMD, __func__, &iif->acmsg);
> send_conf(iif, ap, skb, CapiMessageNotSupportedInCurrentState);
> }
>
> @@ -2085,11 +2083,9 @@ static void do_nothing(struct gigaset_capi_ctr *iif,
> struct gigaset_capi_appl *ap,
> struct sk_buff *skb)
> {
> - if (printk_timed_ratelimit(&ignored_msg_dump_time, 30 * 1000)) {
> - /* decode message */
> - capi_message2cmsg(&iif->acmsg, skb->data);
> - dump_cmsg(DEBUG_CMD, __func__, &iif->acmsg);
> - }
> + /* decode message */
> + capi_message2cmsg(&iif->acmsg, skb->data);
> + dump_cmsg(DEBUG_CMD, __func__, &iif->acmsg);
> dev_kfree_skb_any(skb);
> }
>
--
Karsten Keil
Linux Kernel Development
Tel: +49 175 7249132
Mail: keil@b1-systems.de
B1 Systems GmbH
Osterfeldstraße 7 / 85088 Vohburg / http://www.b1-systems.de
GF: Ralph Dehner / Unternehmenssitz: Vohburg / AG: Ingolstadt,HRB 3537
^ permalink raw reply
* [PATCH 4/4] mISDN: DSP scheduling fix (version 2)
From: Karsten Keil @ 2012-04-26 6:54 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Karsten Keil
From: Karsten Keil <isdn@linux-pingi.de>
dsp_spl_jiffies need to be the same datatype as jiffies (which is ulong).
If not, on 64 bit systems it will fallback to schedule the DSP every jiffie
tic as soon jiffies become > 2^32.
Signed-off-by: Karsten Keil <kkeil@linux-pingi.de>
---
drivers/isdn/mISDN/dsp.h | 4 +++-
drivers/isdn/mISDN/dsp_cmx.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/isdn/mISDN/dsp.h b/drivers/isdn/mISDN/dsp.h
index afe4173..e020957 100644
--- a/drivers/isdn/mISDN/dsp.h
+++ b/drivers/isdn/mISDN/dsp.h
@@ -76,7 +76,9 @@ extern u8 dsp_silence;
#define MAX_SECONDS_JITTER_CHECK 5
extern struct timer_list dsp_spl_tl;
-extern u32 dsp_spl_jiffies;
+
+/* the datatype need to match jiffies datatype */
+extern unsigned long dsp_spl_jiffies;
/* the structure of conferences:
*
diff --git a/drivers/isdn/mISDN/dsp_cmx.c b/drivers/isdn/mISDN/dsp_cmx.c
index 0c104b9..3a3b3a5 100644
--- a/drivers/isdn/mISDN/dsp_cmx.c
+++ b/drivers/isdn/mISDN/dsp_cmx.c
@@ -1624,7 +1624,7 @@ send_packet:
static u32 jittercount; /* counter for jitter check */
struct timer_list dsp_spl_tl;
-u32 dsp_spl_jiffies; /* calculate the next time to fire */
+unsigned long dsp_spl_jiffies; /* calculate the next time to fire */
static u16 dsp_count; /* last sample count */
static int dsp_count_valid; /* if we have last sample count */
--
1.7.3.4
^ permalink raw reply related
* Re: [RFC v4] Add TCP encap_rcv hook (repost)
From: Simon Horman @ 2012-04-26 7:13 UTC (permalink / raw)
To: Jesse Gross
Cc: dev-yBygre7rU0TnMu66kgdUjQ, eric.dumazet-Re5JQEeQqe8AvxtiuMwx3w,
netdev-u79uwXL29TY76Z2rM5mHXA, jhs-jkUAjuhPggJWk0Htik3J/w,
shemminger-ZtmgI6mnKB3QT0dZR+AlfA, David Miller
In-Reply-To: <CAEP_g=8DmQ_-8+ZbATdVhNJKiDSr0HdUgB-+oaqwU1=SqqzXfQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Wed, Apr 25, 2012 at 10:17:25AM -0700, Jesse Gross wrote:
> On Wed, Apr 25, 2012 at 1:39 AM, Simon Horman <horms@verge.net.au> wrote:
> >
> > Hi Kyle,
> >
> > the component that is of most interest to me is enabling OVS to use in-tree
> > tunnelling code - as it seems that makes most sense for an implementation
> > of STT. I have taken a brief look over your vxlan work and it isn't clear
> > to me if it is moving towards being an in-tree implementation. Moreover,
> > I'm a rather unclear on what changes need to be made to OVS in order for
> > in-tree tunneling to be used.
> >
> > My recollection is that OVS did make use of in-tree tunnelling code
> > but this was removed in favour of the current implementation for various
> > reasons (performance being one IIRC). I gather that revisiting in-tree
> > tunnelling won't revisit the previous set of problems. But I'm unclear how.
> >
> > Jesse, is it possible for you to describe that in a little detail
> > or point me to some information?
>
> This was what I had originally written a while back, although it's
> more about OVS internally and less about how to connect to the in-tree
> code:
> http://openvswitch.org/pipermail/dev/2012-February/014779.html
>
> In order to flexibly implement support for current and future tunnel
> protocols OVS needs to be able to get/set information about the outer
> tunnel header when processing the inner packet. At the very least
> this is src/dst IP addresses and the key/ID/VNI/etc. In the upstream
> tunnel implementations those are implicitly encoded in the device that
> sends or receives the packet. However, this has a two problems:
> number of devices and ability to handle unknown values. We addressed
> part of this problem by allowing the tunnel ID to be set and matched
> through the OVS flow table and an action. In order to do this with
> the in-tree tunneling code, we obviously need a way of passing this
> information around since it would currently get lost as we pass
> through the Linux device layer.
>
> The plan to deal with that is to add a function to the in-tree
> tunneling code that allows a skb to be encapsulated with specific
> parameters and conversely a hook to receive decapsulated packets along
> with header info. This would make all of the kernel tunneling code
> common, while still giving OVS userspace the ability to implement
> essentially any type of tunneling policy. In many ways, this is very
> similar to how vlans look in OVS today.
>
> While it would be possible to implement the hook to use the in-tree
> tunnel code today without a lot of changes, we already know that we
> want to move away from port-based model in the OVS kernel module
> towards the flow model. As we push this upstream the userspace/kernel
> API should be the correct one, so that's why these two things are tied
> together.
Thanks, that explanation along with Kyle's response helps a lot.
It seems to me that something I could help out with is the implementation
of the set_tunnel action which extents and replaces the tun_id action.
It seems that is a requirement for the scheme you describe above.
http://openvswitch.org/pipermail/dev/2012-April/016239.html
_______________________________________________
dev mailing list
dev@openvswitch.org
http://openvswitch.org/mailman/listinfo/dev
^ permalink raw reply
* Re: [PATCH 4/4] mISDN: DSP scheduling fix (version 2)
From: David Miller @ 2012-04-26 7:14 UTC (permalink / raw)
To: kkeil; +Cc: netdev, isdn
In-Reply-To: <1335423288-30702-1-git-send-email-kkeil@linux-pingi.de>
All 4 patches applied to net-next, thanks.
^ permalink raw reply
* [v2 PATCH 1/2] ipvs: null check of net->ipvs in lblc(r) shedulers
From: Hans Schillstrom @ 2012-04-26 7:45 UTC (permalink / raw)
To: horms, ja, wensong, lvs-devel, netdev, netfilter-devel
Cc: hans, Hans Schillstrom
In-Reply-To: <1335426335-5093-1-git-send-email-hans.schillstrom@ericsson.com>
Avoid crash when registering shedulers after
the IPVS core initialization for netns fails. Do this by
checking for present core (net->ipvs).
Ver 2
-
Signed-off-by: Hans Schillstrom <hans.schillstrom@ericsson.com>
---
net/netfilter/ipvs/ip_vs_lblc.c | 3 +++
net/netfilter/ipvs/ip_vs_lblcr.c | 3 +++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/net/netfilter/ipvs/ip_vs_lblc.c b/net/netfilter/ipvs/ip_vs_lblc.c
index 222b6cb..df646cc 100644
--- a/net/netfilter/ipvs/ip_vs_lblc.c
+++ b/net/netfilter/ipvs/ip_vs_lblc.c
@@ -551,6 +551,9 @@ static int __net_init __ip_vs_lblc_init(struct net *net)
{
struct netns_ipvs *ipvs = net_ipvs(net);
+ if (!ipvs)
+ return -ENOENT;
+
if (!net_eq(net, &init_net)) {
ipvs->lblc_ctl_table = kmemdup(vs_vars_table,
sizeof(vs_vars_table),
diff --git a/net/netfilter/ipvs/ip_vs_lblcr.c b/net/netfilter/ipvs/ip_vs_lblcr.c
index 30c476f..570e31e 100644
--- a/net/netfilter/ipvs/ip_vs_lblcr.c
+++ b/net/netfilter/ipvs/ip_vs_lblcr.c
@@ -745,6 +745,9 @@ static int __net_init __ip_vs_lblcr_init(struct net *net)
{
struct netns_ipvs *ipvs = net_ipvs(net);
+ if (!ipvs)
+ return -ENOENT;
+
if (!net_eq(net, &init_net)) {
ipvs->lblcr_ctl_table = kmemdup(vs_vars_table,
sizeof(vs_vars_table),
--
1.7.2.3
^ permalink raw reply related
* [v2 PATCH 0/2] ipvs: netns avoid crash at netns init
From: Hans Schillstrom @ 2012-04-26 7:45 UTC (permalink / raw)
To: horms, ja, wensong, lvs-devel, netdev, netfilter-devel
Cc: hans, Hans Schillstrom
Two simple patches that avoid crashes for no memory at netns init.
- Check return value of protocoll init.
- Null check of net-ipvs in shedulers.
Signed-off-by: Hans Schillstrom <hans.schillstrom@ericsson.com>
--
1.7.2.3
^ permalink raw reply
* [v2 PATCH 2/2] ipvs: take care of return value from protocol init_netns
From: Hans Schillstrom @ 2012-04-26 7:45 UTC (permalink / raw)
To: horms, ja, wensong, lvs-devel, netdev, netfilter-devel
Cc: hans, Hans Schillstrom
In-Reply-To: <1335426335-5093-1-git-send-email-hans.schillstrom@ericsson.com>
ip_vs_create_timeout_table() can return NULL
All functions protocol init_netns is affected of this patch.
Ver 2
unlink pd before free.
Signed-off-by: Hans Schillstrom <hans.schillstrom@ericsson.com>
---
include/net/ip_vs.h | 2 +-
net/netfilter/ipvs/ip_vs_proto.c | 11 +++++++++--
net/netfilter/ipvs/ip_vs_proto_sctp.c | 5 ++++-
net/netfilter/ipvs/ip_vs_proto_tcp.c | 5 ++++-
net/netfilter/ipvs/ip_vs_proto_udp.c | 5 ++++-
5 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 990216d..f967395 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -392,7 +392,7 @@ struct ip_vs_protocol {
void (*exit)(struct ip_vs_protocol *pp);
- void (*init_netns)(struct net *net, struct ip_vs_proto_data *pd);
+ int (*init_netns)(struct net *net, struct ip_vs_proto_data *pd);
void (*exit_netns)(struct net *net, struct ip_vs_proto_data *pd);
diff --git a/net/netfilter/ipvs/ip_vs_proto.c b/net/netfilter/ipvs/ip_vs_proto.c
index 6a8d176..4238be9 100644
--- a/net/netfilter/ipvs/ip_vs_proto.c
+++ b/net/netfilter/ipvs/ip_vs_proto.c
@@ -78,8 +78,15 @@ register_ip_vs_proto_netns(struct net *net, struct ip_vs_protocol *pp)
ipvs->proto_data_table[hash] = pd;
atomic_set(&pd->appcnt, 0); /* Init app counter */
- if (pp->init_netns != NULL)
- pp->init_netns(net, pd);
+ if (pp->init_netns != NULL) {
+ int ret = pp->init_netns(net, pd);
+ if (ret) {
+ /* unlink an free proto data */
+ ipvs->proto_data_table[hash] = pd->next;
+ kfree(pd);
+ return ret;
+ }
+ }
return 0;
}
diff --git a/net/netfilter/ipvs/ip_vs_proto_sctp.c b/net/netfilter/ipvs/ip_vs_proto_sctp.c
index 1fbf7a2..9f3fb75 100644
--- a/net/netfilter/ipvs/ip_vs_proto_sctp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_sctp.c
@@ -1090,7 +1090,7 @@ out:
* timeouts is netns related now.
* ---------------------------------------------
*/
-static void __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
{
struct netns_ipvs *ipvs = net_ipvs(net);
@@ -1098,6 +1098,9 @@ static void __ip_vs_sctp_init(struct net *net, struct ip_vs_proto_data *pd)
spin_lock_init(&ipvs->sctp_app_lock);
pd->timeout_table = ip_vs_create_timeout_table((int *)sctp_timeouts,
sizeof(sctp_timeouts));
+ if (!pd->timeout_table)
+ return -ENOMEM;
+ return 0;
}
static void __ip_vs_sctp_exit(struct net *net, struct ip_vs_proto_data *pd)
diff --git a/net/netfilter/ipvs/ip_vs_proto_tcp.c b/net/netfilter/ipvs/ip_vs_proto_tcp.c
index ef8641f..cd609cc 100644
--- a/net/netfilter/ipvs/ip_vs_proto_tcp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_tcp.c
@@ -677,7 +677,7 @@ void ip_vs_tcp_conn_listen(struct net *net, struct ip_vs_conn *cp)
* timeouts is netns related now.
* ---------------------------------------------
*/
-static void __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
{
struct netns_ipvs *ipvs = net_ipvs(net);
@@ -685,7 +685,10 @@ static void __ip_vs_tcp_init(struct net *net, struct ip_vs_proto_data *pd)
spin_lock_init(&ipvs->tcp_app_lock);
pd->timeout_table = ip_vs_create_timeout_table((int *)tcp_timeouts,
sizeof(tcp_timeouts));
+ if (!pd->timeout_table)
+ return -ENOMEM;
pd->tcp_state_table = tcp_states;
+ return 0;
}
static void __ip_vs_tcp_exit(struct net *net, struct ip_vs_proto_data *pd)
diff --git a/net/netfilter/ipvs/ip_vs_proto_udp.c b/net/netfilter/ipvs/ip_vs_proto_udp.c
index f4b7262..2fedb2d 100644
--- a/net/netfilter/ipvs/ip_vs_proto_udp.c
+++ b/net/netfilter/ipvs/ip_vs_proto_udp.c
@@ -467,7 +467,7 @@ udp_state_transition(struct ip_vs_conn *cp, int direction,
cp->timeout = pd->timeout_table[IP_VS_UDP_S_NORMAL];
}
-static void __udp_init(struct net *net, struct ip_vs_proto_data *pd)
+static int __udp_init(struct net *net, struct ip_vs_proto_data *pd)
{
struct netns_ipvs *ipvs = net_ipvs(net);
@@ -475,6 +475,9 @@ static void __udp_init(struct net *net, struct ip_vs_proto_data *pd)
spin_lock_init(&ipvs->udp_app_lock);
pd->timeout_table = ip_vs_create_timeout_table((int *)udp_timeouts,
sizeof(udp_timeouts));
+ if (!pd->timeout_table)
+ return -ENOMEM;
+ return 0;
}
static void __udp_exit(struct net *net, struct ip_vs_proto_data *pd)
--
1.7.2.3
^ permalink raw reply related
* Re: [net-next 1/4 (V3)] net: ethtool: add the EEE support
From: Giuseppe CAVALLARO @ 2012-04-26 7:48 UTC (permalink / raw)
To: Ben Hutchings; +Cc: netdev, rayagond, davem
In-Reply-To: <1334849401.2426.73.camel@bwh-desktop.uk.solarflarecom.com>
Hello Ben
On 4/19/2012 5:30 PM, Ben Hutchings wrote:
[snip]
>> I'm changing the code for getting/setting the EEE capability and trying
>> to follow your suggestions.
>>
>> The "get" will show the following things; this is a bit different of the
>> points "a" "b" and "c" we had discussed. Maybe, this could also be a
>> more complete (*) .
>> The ethtool (see output below as example) could report the phy
>> (supported/advertised/lp_advertised) and mac eee capabilities separately.
>
> Sounds reasonable.
>
>> The "set" will be useful for some eth devices (like the stmmac) that can
>> stop/enable internally the eee capability (at mac level).
>
> I don't know much about EEE, but shouldn't the driver take care of
> configuring the MAC for this whenever the PHY is set to advertise EEE
> capability?
Yes indeed this can be done at driver level. So could I definitely
remove it from ethtool? What do you suggest?
In case of the stmmac I could add a specific driver option via sys to
enable/disable the eee and set timer.
>> [snip]
>>
>> Current message level: 0x0000003f (63)
>> drv probe link timer ifdown ifup
>> Link detected: yes
>> Energy-Efficient Ethernet: -------------------------
>> MAC supports: yes |-> related to MAC side |
>> phy supports modes: ... |-> from MMD 3.20 |
>> phy advertising modes: ... |-> from MMD 7.60 |
>> LP advertising modes: ... |-> from MMD 7.61 |
>> --------------------------
>> (*)
>> PS. The "..." above means that we can actually dump: 100BASE-TX EEE etc
>> for each advertising modes and also for phy support (reg 3.20).
>
> Yes, that's the sort of information I would expect to see (but try to be
> consistent with the wording used for AN).:
e.g. SUPPORTED_100baseT_EEE ... ADVERTISED_<...>
> The EEE advertising mask presumably should be changeable similarly to
> the AN advertising mask ('ethtool -s <devname> eeeadv <mask>'). But I
> don't know how the two advertising masks interact. Is one supposed to
> be a subset of the other? Currently ethtool automatically changes the
> AN advertising mask in response to a speed/duplex change; should it also
> try to change the EEE advertising mask?
I've just verified the IEEE (Table 45–150a—EEE advertisement register
(Register 7.60) bit definitions) and sorry for my delay in reply but I
was in trouble because looking at the registers for the phy (I am using)
the reg 7.60 was in RO and I couldn't understand how to set the mask.
I confirm that the Adv reg from the std is R/W and the mask as you
suggest could be set according to the speed.
The EEE should work on duplex mode only.
I wonder so if if the final patch I should have no new option for the
ethtool command and EEE info are directly passed from the kernel like
speed and duplex when call get_settings.
Peppe
>
> Ben.
>
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