* [PATCH 8/8] mISDN: Add 2MBit mode for HFC E1 card
From: Karsten Keil @ 2012-04-28 11:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Karsten Keil
In-Reply-To: <1335613404-10187-1-git-send-email-kkeil@linux-pingi.de>
From: Karsten Keil <isdn@linux-pingi.de>
The new mode allows to receive and transmit full transparent
or HDLC data of all timeslots via one FIFO.
Change some register names to match the latest manual for
the E1 chip.
Signed-off-by: Karsten Keil <kkeil@linux-pingi.de>
---
drivers/isdn/hardware/mISDN/hfc_multi.h | 79 +++---
drivers/isdn/hardware/mISDN/hfcmulti.c | 426 ++++++++++++++++++++++++++-----
include/linux/mISDNif.h | 57 +++--
3 files changed, 440 insertions(+), 122 deletions(-)
diff --git a/drivers/isdn/hardware/mISDN/hfc_multi.h b/drivers/isdn/hardware/mISDN/hfc_multi.h
index c601f88..9dc0543 100644
--- a/drivers/isdn/hardware/mISDN/hfc_multi.h
+++ b/drivers/isdn/hardware/mISDN/hfc_multi.h
@@ -12,6 +12,7 @@
#define DEBUG_HFCMULTI_FILL 0x00800000
#define DEBUG_HFCMULTI_SYNC 0x01000000
#define DEBUG_HFCMULTI_DTMF 0x02000000
+#define DEBUG_HFCMULTI_TIMER 0x04000000
#define DEBUG_HFCMULTI_LOCK 0x80000000
#define PCI_ENA_REGIO 0x01
@@ -71,7 +72,10 @@ struct hfcm_hw {
u_char r_dtmf;
u_char r_st_sync;
u_char r_sci_msk;
- u_char r_tx0, r_tx1;
+ u_char r_tx0;
+ u_char r_tx1;
+ u_char r_rx_sl0_cfg0;
+ u_char r_tx_sl0_cfg1;
u_char a_st_ctrl0[8];
u_char r_bert_wd_md;
timer_t timer;
@@ -114,6 +118,7 @@ struct hfcm_hw {
/* hw */
#define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */
#define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */
+#define HFC_CHIP_2MBITRAW 16 /* mode to access full 32 byte data */
#define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */
#define HFC_IO_MODE_REGIO 0x01 /* PCI io access */
@@ -334,24 +339,23 @@ struct hfc_multi {
#define R_LOS0 0x22
#define R_LOS1 0x23
#define R_RX0 0x24
-#define R_RX_FR0 0x25
-#define R_RX_FR1 0x26
+#define R_RX_SL0_CFG0 0x25
+#define R_RX_SL0_CFG1 0x26
#define R_TX0 0x28
#define R_TX1 0x29
-#define R_TX_FR0 0x2C
-
-#define R_TX_FR1 0x2D
-#define R_TX_FR2 0x2E
-#define R_JATT_ATT 0x2F /* undocumented */
+#define R_TX_SL0_CFG0 0x2C
+#define R_TX_SL0 0x2D
+#define R_TX_SL0_CFG1 0x2E
+#define R_JATT_CFG 0x2F
#define A_ST_RD_STATE 0x30
#define A_ST_WR_STATE 0x30
-#define R_RX_OFF 0x30
+#define R_RX_OFFS 0x30
#define A_ST_CTRL0 0x31
#define R_SYNC_OUT 0x31
#define A_ST_CTRL1 0x32
#define A_ST_CTRL2 0x33
#define A_ST_SQ_WR 0x34
-#define R_TX_OFF 0x34
+#define R_TX_OFFS 0x34
#define R_SYNC_CTRL 0x35
#define A_ST_CLK_DLY 0x37
#define R_PWM0 0x38
@@ -414,8 +418,8 @@ struct hfc_multi {
#define R_RX_SL0_0 0x25
#define R_RX_SL0_1 0x26
#define R_RX_SL0_2 0x27
-#define R_JATT_DIR 0x2b /* undocumented */
-#define R_SLIP 0x2c
+#define R_JATT_STA 0x2B
+#define R_SLIP 0x2C
#define A_ST_RD_STA 0x30
#define R_FAS_EC 0x30
#define R_FAS_ECL 0x30
@@ -430,12 +434,12 @@ struct hfc_multi {
#define R_E_EC 0x36
#define R_E_ECL 0x36
#define R_E_ECH 0x37
-#define R_SA6_SA13_EC 0x38
-#define R_SA6_SA13_ECL 0x38
-#define R_SA6_SA13_ECH 0x39
-#define R_SA6_SA23_EC 0x3A
-#define R_SA6_SA23_ECL 0x3A
-#define R_SA6_SA23_ECH 0x3B
+#define R_SA6_VAL13_EC 0x38
+#define R_SA6_VAL13_ECL 0x38
+#define R_SA6_VAL13_ECH 0x39
+#define R_SA6_VAL23_EC 0x3A
+#define R_SA6_VAL23_ECL 0x3A
+#define R_SA6_VAL23_ECH 0x3B
#define A_ST_B1_RX 0x3C
#define A_ST_B2_RX 0x3D
#define A_ST_D_RX 0x3E
@@ -624,7 +628,7 @@ struct hfc_multi {
#define V_RX_INV_CLK 0x20
#define V_RX_INV_DATA 0x40
#define V_AIS_ITU 0x80
-/* R_RX_FR0 */
+/* R_RX_SL0_CFG0 */
#define V_NO_INSYNC 0x01
#define V_AUTO_RESYNC 0x02
#define V_AUTO_RECO 0x04
@@ -633,7 +637,7 @@ struct hfc_multi {
#define V_XCRC_SYNC 0x20
#define V_MF_RESYNC 0x40
#define V_RESYNC 0x80
-/* R_RX_FR1 */
+/* R_RX_SL0_CFG1 */
#define V_RX_MF 0x01
#define V_RX_MF_SYNC 0x02
#define V_RX_SL0_RAM 0x04
@@ -654,17 +658,17 @@ struct hfc_multi {
#define V_ATX 0x20
#define V_NTRI 0x40
#define V_AUTO_ERR_RES 0x80
-/* R_TX_FR0 */
+/* R_TX_SL0_CFG0 */
#define V_TRP_FAS 0x01
#define V_TRP_NFAS 0x02
#define V_TRP_RAL 0x04
#define V_TRP_SA 0x08
-/* R_TX_FR1 */
+/* R_TX_SL0 */
#define V_TX_FAS 0x01
#define V_TX_NFAS 0x02
#define V_TX_RAL 0x04
#define V_TX_SA 0x08
-/* R_TX_FR2 */
+/* R_TX_SL0_CFG1 */
#define V_TX_MF 0x01
#define V_TRP_SL0 0x02
#define V_TX_SL0_RAM 0x04
@@ -672,7 +676,7 @@ struct hfc_multi {
#define V_NEG_E 0x20
#define V_XS12_ON 0x40
#define V_XS15_ON 0x80
-/* R_RX_OFF */
+/* R_RX_OFFS */
#define V_RX_SZ 0x01
#define V_RX_INIT 0x04
/* R_SYNC_OUT */
@@ -680,7 +684,7 @@ struct hfc_multi {
#define V_IPATS0 0x20
#define V_IPATS1 0x40
#define V_IPATS2 0x80
-/* R_TX_OFF */
+/* R_TX_OFFS */
#define V_TX_SZ 0x01
#define V_TX_INIT 0x04
/* R_SYNC_CTRL */
@@ -1119,20 +1123,20 @@ struct hfc_register_names {
{"R_LOS0", 0x22},
{"R_LOS1", 0x23},
{"R_RX0", 0x24},
- {"R_RX_FR0", 0x25},
- {"R_RX_FR1", 0x26},
+ {"R_RX_SL0_CFG0", 0x25},
+ {"R_RX_SL0_CFG1", 0x26},
{"R_TX0", 0x28},
{"R_TX1", 0x29},
- {"R_TX_FR0", 0x2C},
- {"R_TX_FR1", 0x2D},
- {"R_TX_FR2", 0x2E},
+ {"R_TX_SL0_CFG0", 0x2C},
+ {"R_TX_SL0", 0x2D},
+ {"R_TX_SL0_CFG1", 0x2E},
{"R_JATT_ATT", 0x2F},
- {"A_ST_xx_STA/R_RX_OFF", 0x30},
+ {"A_ST_xx_STA/R_RX_OFFS", 0x30},
{"A_ST_CTRL0/R_SYNC_OUT", 0x31},
{"A_ST_CTRL1", 0x32},
{"A_ST_CTRL2", 0x33},
{"A_ST_SQ_WR", 0x34},
- {"R_TX_OFF", 0x34},
+ {"R_TX_OFFS", 0x34},
{"R_SYNC_CTRL", 0x35},
{"A_ST_CLK_DLY", 0x37},
{"R_PWM0", 0x38},
@@ -1194,8 +1198,9 @@ struct hfc_register_names {
{"R_RX_SL0_0", 0x25},
{"R_RX_SL0_1", 0x26},
{"R_RX_SL0_2", 0x27},
- {"R_JATT_DIR", 0x2b},
+ {"R_JATT_STA", 0x2b},
{"R_SLIP", 0x2c},
+ {"R_JATT_CFG", 0x2f},
{"A_ST_RD_STA", 0x30},
{"R_FAS_ECL", 0x30},
{"R_FAS_ECH", 0x31},
@@ -1205,10 +1210,10 @@ struct hfc_register_names {
{"R_CRC_ECH", 0x35},
{"R_E_ECL", 0x36},
{"R_E_ECH", 0x37},
- {"R_SA6_SA13_ECL", 0x38},
- {"R_SA6_SA13_ECH", 0x39},
- {"R_SA6_SA23_ECL", 0x3A},
- {"R_SA6_SA23_ECH", 0x3B},
+ {"R_SA6_VAL13_ECL", 0x38},
+ {"R_SA6_VAL13_ECH", 0x39},
+ {"R_SA6_VAL23_ECL", 0x3A},
+ {"R_SA6_VAL23_ECH", 0x3B},
{"A_ST_B1_RX", 0x3C},
{"A_ST_B2_RX", 0x3D},
{"A_ST_D_RX", 0x3E},
diff --git a/drivers/isdn/hardware/mISDN/hfcmulti.c b/drivers/isdn/hardware/mISDN/hfcmulti.c
index 4301331..06be60c 100644
--- a/drivers/isdn/hardware/mISDN/hfcmulti.c
+++ b/drivers/isdn/hardware/mISDN/hfcmulti.c
@@ -64,7 +64,7 @@
*
* HFC-E1 only bits:
* Bit 0 = 0x0001 = interface: 0=copper, 1=optical
- * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
+ * Bit 1 = 0x0002 = 32 B-channels bundle mode (one channel)
* Bit 2 = 0x0004 = Report LOS
* Bit 3 = 0x0008 = Report AIS
* Bit 4 = 0x0010 = Report SLIP
@@ -1269,11 +1269,10 @@ init_chip(struct hfc_multi *hc)
if (debug & DEBUG_HFCMULTI_INIT)
printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
__func__);
- } else
- if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
+ } else if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
if (debug & DEBUG_HFCMULTI_INIT)
printk(KERN_DEBUG "%s: setting PCM into master mode\n",
- __func__);
+ __func__);
hc->hw.r_pcm_md0 |= V_PCM_MD;
} else {
if (debug & DEBUG_HFCMULTI_INIT)
@@ -1288,7 +1287,18 @@ init_chip(struct hfc_multi *hc)
0x11 /* 16 Bytes TX/RX */);
else
HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
- HFC_outb(hc, R_FIFO_MD, 0);
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip) &&
+ (hc->ctype == HFC_TYPE_E1)) {
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG "%s: setting 2MBit raw mode\n",
+ __func__);
+ HFC_outb(hc, R_FIFO_MD, 0x0c);
+ hc->Flen = 0x10;
+ hc->Zmin = 0x80;
+ hc->Zlen = 384;
+
+ } else
+ HFC_outb(hc, R_FIFO_MD, 0);
if (hc->ctype == HFC_TYPE_XHFC)
hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES;
else
@@ -1334,7 +1344,8 @@ init_chip(struct hfc_multi *hc)
if (hc->slots == 128)
HFC_outb(hc, R_PCM_MD1, 0x20);
HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
- if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
+ if (test_bit(HFC_CHIP_PLXSD, &hc->chip) ||
+ test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
else if (test_bit(HFC_CHIP_EMBSD, &hc->chip))
HFC_outb(hc, R_PCM_MD2, 0x10); /* V_C2O_EN */
@@ -1956,7 +1967,10 @@ hfcmulti_tx(struct hfc_multi *hc, int ch)
int *idxp;
bch = hc->chan[ch].bch;
- dch = hc->chan[ch].dch;
+ if (!bch)
+ dch = hc->chan[ch].dch;
+ else
+ dch = NULL;
if ((!dch) && (!bch))
return;
@@ -2205,7 +2219,11 @@ hfcmulti_rx(struct hfc_multi *hc, int ch)
int maxlen;
bch = hc->chan[ch].bch;
- dch = hc->chan[ch].dch;
+ if (!bch)
+ dch = hc->chan[ch].dch;
+ else
+ dch = NULL;
+
if ((!dch) && (!bch))
return;
if (dch) {
@@ -2264,20 +2282,20 @@ next_frame:
if (Zsize <= 0)
return;
- if (*sp == NULL) {
- *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
- if (*sp == NULL) {
- printk(KERN_DEBUG "%s: No mem for rx_skb\n",
- __func__);
- return;
- }
- }
/* show activity */
if (dch)
hc->activity_rx |= 1 << hc->chan[ch].port;
/* empty fifo with what we have */
if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
+ if (*sp == NULL) {
+ *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
+ if (*sp == NULL) {
+ printk(KERN_DEBUG "%s: No mem for rx_skb\n",
+ __func__);
+ return;
+ }
+ }
if (debug & DEBUG_HFCMULTI_FIFO)
printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
"bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
@@ -2355,24 +2373,18 @@ next_frame:
/* there is an incomplete frame */
} else {
/* transparent */
+ if (*sp == NULL) {
+ *sp = mI_alloc_skb(Zsize, GFP_ATOMIC);
+ if (*sp == NULL) {
+ printk(KERN_DEBUG "%s: No mem for rx_skb\n",
+ __func__);
+ return;
+ }
+ }
if (Zsize > skb_tailroom(*sp))
Zsize = skb_tailroom(*sp);
hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
- if (((*sp)->len) < MISDN_COPY_SIZE) {
- skb = *sp;
- *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
- if (*sp) {
- memcpy(skb_put(*sp, skb->len),
- skb->data, skb->len);
- skb_trim(skb, 0);
- } else {
- printk(KERN_DEBUG "%s: No mem\n", __func__);
- *sp = skb;
- skb = NULL;
- }
- } else {
- skb = NULL;
- }
+ skb = NULL;
if (debug & DEBUG_HFCMULTI_FIFO)
printk(KERN_DEBUG
"%s(card %d): fifo(%d) reading %d bytes "
@@ -2409,7 +2421,7 @@ signal_state_up(struct dchannel *dch, int info, char *msg)
static inline void
handle_timer_irq(struct hfc_multi *hc)
{
- int ch, temp;
+ int ch, temp, ch_activ = 0;
struct dchannel *dch;
u_long flags;
@@ -2443,10 +2455,33 @@ handle_timer_irq(struct hfc_multi *hc)
hc->e1_resync = 0;
spin_unlock_irqrestore(&HFClock, flags);
}
-
- if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1)
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip)) {
+ ch = 0;
+ if (hc->created[hc->chan[ch].port] && hc->chan[ch].bch &&
+ test_bit(FLG_ACTIVE, &hc->chan[ch].bch->Flags)) {
+ ch_activ++;
+ hfcmulti_tx(hc, ch);
+ hfcmulti_rx(hc, ch);
+ if (hc->chan[ch].dch &&
+ hc->chan[ch].nt_timer > -1) {
+ dch = hc->chan[ch].dch;
+ if (!(--hc->chan[ch].nt_timer)) {
+ schedule_event(dch,
+ FLG_PHCHANGE);
+ if (debug &
+ DEBUG_HFCMULTI_STATE)
+ printk(KERN_DEBUG
+ "%s: nt_timer at "
+ "state %x\n",
+ __func__,
+ dch->state);
+ }
+ }
+ }
+ } else if (hc->ctype != HFC_TYPE_E1 || hc->e1_state == 1) {
for (ch = 0; ch <= 31; ch++) {
if (hc->created[hc->chan[ch].port]) {
+ ch_activ++;
hfcmulti_tx(hc, ch);
/* fifo is started when switching to rx-fifo */
hfcmulti_rx(hc, ch);
@@ -2467,6 +2502,11 @@ handle_timer_irq(struct hfc_multi *hc)
}
}
}
+ }
+ if (debug & DEBUG_HFCMULTI_TIMER)
+ printk(KERN_DEBUG "Timer IRQ id%dp%d st%d activ %d\n",
+ hc->id, hc->ports, hc->e1_state, ch_activ);
+
if (hc->ctype == HFC_TYPE_E1 && hc->created[0]) {
dch = hc->chan[hc->dnum[0]].dch;
/* LOS */
@@ -2515,7 +2555,7 @@ handle_timer_irq(struct hfc_multi *hc)
"RDI gone");
hc->chan[hc->dnum[0]].rdi = temp;
}
- temp = HFC_inb_nodebug(hc, R_JATT_DIR);
+ temp = HFC_inb_nodebug(hc, R_JATT_STA);
switch (hc->chan[hc->dnum[0]].sync) {
case 0:
if ((temp & 0x60) == 0x60) {
@@ -2524,9 +2564,9 @@ handle_timer_irq(struct hfc_multi *hc)
"%s: (id=%d) E1 now "
"in clock sync\n",
__func__, hc->id);
- HFC_outb(hc, R_RX_OFF,
+ HFC_outb(hc, R_RX_OFFS,
hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
- HFC_outb(hc, R_TX_OFF,
+ HFC_outb(hc, R_TX_OFFS,
hc->chan[hc->dnum[0]].jitter | V_RX_INIT);
hc->chan[hc->dnum[0]].sync = 1;
goto check_framesync;
@@ -2660,6 +2700,8 @@ fifo_irq(struct hfc_multi *hc, int block)
r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
j = 0;
+ printk(KERN_DEBUG "%s: block %d fifo_bl %02x\n", __func__,
+ block, r_irq_fifo_bl);
while (j < 8) {
ch = (block << 2) + (j >> 1);
dch = hc->chan[ch].dch;
@@ -2870,6 +2912,52 @@ hfcmulti_dbusy_timer(struct hfc_multi *hc)
{
}
+/* special mode to transmit/revceive full frame (all timeslots) in fifo 0 */
+
+static int set_2MBit_mode(struct hfc_multi *hc, int prot)
+{
+ u8 ch, lim;
+
+ for (ch = 0; ch < 64; ch++) {
+ /* Reset all fifo */
+ HFC_outb(hc, R_FIFO, ch);
+ HFC_wait(hc);
+ HFC_outb(hc, R_INC_RES_FIFO, 6);
+ }
+
+ HFC_outb(hc, R_FIRST_FIFO, 0x0);
+ lim = 63;
+ for (ch = 0; ch < 64; ch++) {
+ HFC_outb(hc, R_FSM_IDX, ch);
+ HFC_wait(hc);
+ HFC_outb(hc, A_CHANNEL, ch);
+ HFC_outb(hc, A_FIFO_SEQ, (ch + 1) % 2);
+ if (prot == ISDN_P_B_HDLC)
+ HFC_outb(hc, A_CON_HDLC, 0x4);
+ else
+ HFC_outb(hc, A_CON_HDLC, 0x6);
+ HFC_outb(hc, A_SUBCH_CFG, 0);
+ if (ch == lim)
+ break;
+ }
+ HFC_outb(hc, A_FIFO_SEQ, 0x40);
+
+ for (ch = 0; ch < 64; ch++) {
+ u8 ach, asc, ac, afs, ais, af1, af2;
+ HFC_outb(hc, R_FIFO, ch);
+ HFC_wait(hc);
+ ach = HFC_inb(hc, A_CON_HDLC);
+ asc = HFC_inb(hc, A_SUBCH_CFG);
+ ac = HFC_inb(hc, A_CHANNEL);
+ afs = HFC_inb(hc, A_FIFO_SEQ);
+ ais = HFC_inb(hc, A_IRQ_MSK);
+ af1 = HFC_inb(hc, A_F1);
+ af2 = HFC_inb(hc, A_F2);
+ printk(KERN_DEBUG "R_FIFO %02d: %02x/%02x/%02x/%02x/%02x %d/%d\n",
+ ch, ach, asc, ac, afs, ais, af1, af2);
+ }
+ return 0;
+}
/*
* activate/deactivate hardware for selected channels and mode
@@ -3514,12 +3602,24 @@ handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
/* activate B-channel if not already activated */
if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
hc->chan[bch->slot].txpending = 0;
- ret = mode_hfcmulti(hc, bch->slot,
- ch->protocol,
- hc->chan[bch->slot].slot_tx,
- hc->chan[bch->slot].bank_tx,
- hc->chan[bch->slot].slot_rx,
- hc->chan[bch->slot].bank_rx);
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip)) {
+ ret = set_2MBit_mode(hc, ch->protocol);
+ /* The default content for these registers can
+ * be changed via a MISDN_CTRL_L1_TS0_MODE ctrl
+ * request
+ */
+ HFC_outb(hc, R_RX_SL0_CFG0,
+ hc->hw.r_rx_sl0_cfg0);
+ HFC_outb(hc, R_TX_SL0_CFG1,
+ hc->hw.r_tx_sl0_cfg1);
+ } else {
+ ret = mode_hfcmulti(hc, bch->slot,
+ ch->protocol,
+ hc->chan[bch->slot].slot_tx,
+ hc->chan[bch->slot].bank_tx,
+ hc->chan[bch->slot].slot_rx,
+ hc->chan[bch->slot].bank_rx);
+ }
if (!ret) {
if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
&& test_bit(HFC_CHIP_DTMF, &hc->chip)) {
@@ -3591,11 +3691,13 @@ channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
int slot_rx;
int bank_rx;
int num;
+ u8 v1, v2;
switch (cq->op) {
case MISDN_CTRL_GETOP:
- cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
- | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
+ cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP |
+ MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY |
+ MISDN_CTRL_L1_TESTS;
break;
case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
hc->chan[bch->slot].rx_off = !!cq->p1;
@@ -3702,6 +3804,38 @@ channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
else
ret = -EINVAL;
break;
+ case MISDN_CTRL_L1_TS0_MODE:
+ if (hc->ctype == HFC_TYPE_E1) {
+ v1 = hc->hw.r_rx_sl0_cfg0;
+ v2 = hc->hw.r_tx_sl0_cfg1;
+ if (cq->p1 > -1) {
+ hc->hw.r_rx_sl0_cfg0 = cq->p1 & 0xff;
+ HFC_outb(hc, R_RX_SL0_CFG0, cq->p1 & 0xff);
+ printk(KERN_DEBUG "RX_SL0_CFG0 = %x\n", cq->p1);
+ } else
+ printk(KERN_DEBUG "RX_SL0_CFG0 not modified\n");
+ if (cq->p2 > -1) {
+ hc->hw.r_tx_sl0_cfg1 = cq->p2 & 0xff;
+ HFC_outb(hc, R_TX_SL0_CFG1, cq->p2 & 0xff);
+ printk(KERN_DEBUG "TX_SL0_CFG1 = %x\n", cq->p2);
+ } else
+ printk(KERN_DEBUG "TX_SL0_CFG1 not modified\n");
+ cq->p1 = v1;
+ cq->p2 = v2;
+ } else {
+ printk(KERN_DEBUG "Not E1\n");
+ ret = -EINVAL;
+ }
+ break;
+ case MISDN_CTRL_L1_GET_SYNC_INFO:
+ cq->p1 = HFC_inb(hc, R_E1_RD_STA);
+ cq->p1 |= (HFC_inb(hc, R_SYNC_STA) << 8);
+ cq->p2 = HFC_inb(hc, R_RX_SL0_0);
+ cq->p2 |= (HFC_inb(hc, R_RX_SL0_1) << 8);
+ cq->p2 |= (HFC_inb(hc, R_RX_SL0_2) << 16);
+ cq->p3 = HFC_inb(hc, R_JATT_STA);
+ cq->p3 |= (HFC_inb(hc, R_SLIP) << 8);
+ break;
default:
printk(KERN_WARNING "%s: unknown Op %x\n",
__func__, cq->op);
@@ -3776,6 +3910,12 @@ ph_state_change(struct dchannel *dch)
}
switch (dch->state) {
case (1):
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip)) {
+ if (debug & DEBUG_HFCMULTI_STATE)
+ printk(KERN_DEBUG
+ "2 MBIT Raw state 1 reached\n");
+ break;
+ }
if (hc->e1_state != 1) {
for (i = 1; i <= 31; i++) {
/* reset fifos on e1 activation */
@@ -3874,6 +4014,113 @@ ph_state_change(struct dchannel *dch)
}
}
+int init_2MBit_mode(struct hfc_multi *hc, int nr)
+{
+ u_char r_e1_wr_sta;
+ int pt;
+
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG "%s: ch%d entered\n", __func__, nr);
+
+ if (nr != 0) {
+ printk(KERN_ERR "Only ch0 supports 2MBit card%d\n", hc->id);
+ return -EINVAL;
+ }
+
+ pt = hc->chan[nr].port;
+ if (pt != 0) {
+ printk(KERN_ERR "Only port 0 in 2MBit mode %d\n", hc->id);
+ return -EINVAL;
+ }
+
+ hc->chan[nr].slot_tx = -1;
+ hc->chan[nr].slot_rx = -1;
+ hc->chan[nr].conf = -1;
+ mode_hfcmulti(hc, nr, ISDN_P_NONE, -1, 0, -1, 0);
+
+ if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[nr].cfg)) {
+ HFC_outb(hc, R_LOS0, 255); /* 2 ms */
+ HFC_outb(hc, R_LOS1, 255); /* 512 ms */
+ }
+ if (test_bit(HFC_CFG_OPTICAL, &hc->chan[nr].cfg)) {
+ HFC_outb(hc, R_RX0, 0);
+ hc->hw.r_tx0 = 0 | V_OUT_EN;
+ } else {
+ HFC_outb(hc, R_RX0, 1);
+ hc->hw.r_tx0 = 1 | V_OUT_EN;
+ }
+ hc->hw.r_tx1 = V_ATX | V_NTRI;
+ HFC_outb(hc, R_TX0, hc->hw.r_tx0);
+ HFC_outb(hc, R_TX1, hc->hw.r_tx1);
+ HFC_outb(hc, R_TX_SL0_CFG0, 0x00);
+ HFC_outb(hc, R_TX_SL0, 0xf8);
+
+ HFC_outb(hc, R_TX_SL0_CFG1, V_TX_MF | V_TX_E | V_NEG_E);
+ /* set transparent SL0 is set on ACTIVATE */
+ hc->hw.r_tx_sl0_cfg1 = V_TX_MF | V_TRP_SL0;
+
+ HFC_outb(hc, R_RX_SL0_CFG0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
+
+ hc->hw.r_rx_sl0_cfg0 = 0x1;
+
+ if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
+ HFC_outb(hc, R_RX_SL0_CFG1, V_RX_MF | V_RX_MF_SYNC);
+
+ /* Default TE mode and clock from interface */
+ r_e1_wr_sta = 1;
+ hc->e1_getclock = 1;
+ if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
+ HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
+ else
+ HFC_outb(hc, R_SYNC_OUT, 0);
+
+ if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
+ hc->e1_getclock = 1;
+ if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
+ hc->e1_getclock = 0;
+ if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
+ /* SLAVE (clock master) */
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG
+ "%s: E1 port is clock master (clock from PCM)\n",
+ __func__);
+ HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
+ } else {
+ if (hc->e1_getclock) {
+ /* MASTER (clock slave) */
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG
+ "%s: E1 port is clock slave (clock to PCM)\n",
+ __func__);
+ HFC_outb(hc, R_SYNC_CTRL, 0);
+ } else {
+ /* MASTER (clock master) */
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG
+ "%s: E1 port is clock master (clock from QUARTZ)\n",
+ __func__);
+ HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
+ V_PCM_SYNC | V_JATT_OFF);
+ HFC_outb(hc, R_SYNC_OUT, 0);
+ }
+ }
+ HFC_outb(hc, R_JATT_CFG, 0x9c);
+ HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
+ HFC_outb(hc, R_PWM0, 0x50);
+ HFC_outb(hc, R_PWM1, 0xff);
+
+ /* state machine setup */
+ HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
+ udelay(10); /* wait at least 5,21us */
+ if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
+ hc->syncronized = 0;
+ plxsd_checksync(hc, 0);
+ }
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk("%s: done\n", __func__);
+ return 0;
+}
+
/*
* called for card mode init message
*/
@@ -3928,16 +4175,19 @@ hfcmulti_initmode(struct dchannel *dch)
hc->hw.r_tx1 = V_ATX | V_NTRI;
HFC_outb(hc, R_TX0, hc->hw.r_tx0);
HFC_outb(hc, R_TX1, hc->hw.r_tx1);
- HFC_outb(hc, R_TX_FR0, 0x00);
- HFC_outb(hc, R_TX_FR1, 0xf8);
+ HFC_outb(hc, R_TX_SL0_CFG0, 0x00);
+ HFC_outb(hc, R_TX_SL0, 0xf8);
- if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
- HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
+ if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg)) {
+ hc->hw.r_tx_sl0_cfg1 = V_TX_MF | V_TX_E | V_NEG_E;
+ HFC_outb(hc, R_TX_SL0_CFG1, hc->hw.r_tx_sl0_cfg1);
+ }
- HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
+ hc->hw.r_rx_sl0_cfg0 = V_AUTO_RESYNC | V_AUTO_RECO;
+ HFC_outb(hc, R_RX_SL0_CFG0, hc->hw.r_rx_sl0_cfg0);
if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dnum[0]].cfg))
- HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
+ HFC_outb(hc, R_RX_SL0_CFG1, V_RX_MF | V_RX_MF_SYNC);
if (dch->dev.D.protocol == ISDN_P_NT_E1) {
if (debug & DEBUG_HFCMULTI_INIT)
@@ -3987,7 +4237,7 @@ hfcmulti_initmode(struct dchannel *dch)
HFC_outb(hc, R_SYNC_OUT, 0);
}
}
- HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
+ HFC_outb(hc, R_JATT_CFG, 0x9c); /* undoc register */
HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
HFC_outb(hc, R_PWM0, 0x50);
HFC_outb(hc, R_PWM1, 0xff);
@@ -4086,6 +4336,9 @@ open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
if (debug & DEBUG_HW_OPEN)
printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
dch->dev.id, __builtin_return_address(0));
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip) &&
+ (hc->ctype == HFC_TYPE_E1)) /* No Dchannel in this mode */
+ return -EINVAL;
if (rq->protocol == ISDN_P_NONE)
return -EINVAL;
if ((dch->dev.D.protocol != ISDN_P_NONE) &&
@@ -4122,15 +4375,20 @@ open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
struct channel_req *rq)
{
struct bchannel *bch;
- int ch;
+ int ret, ch;
if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
return -EINVAL;
if (rq->protocol == ISDN_P_NONE)
return -EINVAL;
- if (hc->ctype == HFC_TYPE_E1)
+ if (hc->ctype == HFC_TYPE_E1) {
ch = rq->adr.channel;
- else
+ if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip)) {
+ ret = init_2MBit_mode(hc, ch);
+ if (ret)
+ return ret;
+ }
+ } else
ch = (rq->adr.channel - 1) + (dch->slot - 2);
bch = hc->chan[ch].bch;
if (!bch) {
@@ -4141,6 +4399,7 @@ open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
if (test_and_set_bit(FLG_OPEN, &bch->Flags))
return -EBUSY; /* b-channel can be only open once */
test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
+
bch->ch.protocol = rq->protocol;
hc->chan[ch].rx_off = 0;
rq->ch = &bch->ch;
@@ -4158,10 +4417,11 @@ channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
struct hfc_multi *hc = dch->hw;
int ret = 0;
int wd_mode, wd_cnt;
+ u_char reg, reg1;
switch (cq->op) {
case MISDN_CTRL_GETOP:
- cq->op = MISDN_CTRL_HFC_OP;
+ cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_L1_TESTS;
break;
case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
wd_cnt = cq->p1 & 0xf;
@@ -4191,6 +4451,42 @@ channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
__func__);
HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
break;
+ case MISDN_CTRL_L1_STATE_TEST:
+ if (hc->ctype == HFC_TYPE_E1) {
+ /* undocumented: status changes during read */
+ reg = HFC_inb_nodebug(hc, R_E1_RD_STA);
+ while (reg != (reg1 =
+ HFC_inb_nodebug(hc, R_E1_RD_STA))) {
+ if (debug & DEBUG_HFCMULTI_STATE)
+ printk(KERN_DEBUG
+ "%s: reread STATE because %d!=%d\n",
+ __func__, reg, reg1);
+ reg = reg1; /* repeat */
+ }
+ printk(KERN_DEBUG "Old L1 state %02x\n", reg);
+ reg &= 0x07;
+ if (cq->p1 < 0 || cq->p1 > 6) /* reset auto mode */
+ HFC_outb(hc, R_E1_WR_STA, reg);
+ else {/* force new state state */
+ reg = cq->p1 & 0x07;
+ HFC_outb(hc, R_E1_WR_STA, reg | V_E1_LD_STA);
+ printk(KERN_DEBUG "New L1 state %02x\n", reg);
+ }
+ } else
+ ret = -EINVAL;
+ break;
+ case MISDN_CTRL_L1_AIS_TEST:
+ if (hc->ctype == HFC_TYPE_E1) {
+ printk(KERN_DEBUG "Old AIS state %02x\n", hc->hw.r_tx1);
+ if (cq->p1)
+ hc->hw.r_tx1 |= V_AIS_OUT;
+ else
+ hc->hw.r_tx1 &= ~V_AIS_OUT;
+ HFC_outb(hc, R_TX1, hc->hw.r_tx1);
+ printk(KERN_DEBUG "New AIS state %02x\n", hc->hw.r_tx1);
+ } else
+ ret = -EINVAL;
+ break;
default:
printk(KERN_WARNING "%s: unknown Op %x\n",
__func__, cq->op);
@@ -4843,7 +5139,18 @@ init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
dch->debug = debug;
mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
dch->hw = hc;
- dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
+ if (port[Port_cnt] & 0x0002) {
+ if (debug & DEBUG_HFCMULTI_INIT)
+ printk(KERN_DEBUG
+ "%s: PORT 2MBit raw mode E1: card(%d) port(%d)\n",
+ __func__, HFC_cnt + 1, 1);
+ test_and_set_bit(HFC_CHIP_2MBITRAW, &hc->chip);
+ dch->dev.Dprotocols = (1 << ISDN_P_NONE);
+ hc->dnum[pt] = 0;
+ hc->bmask[pt] = 1;
+ } else
+ dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
+
dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
(1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
dch->dev.D.send = handle_dmsg;
@@ -4852,8 +5159,9 @@ init_e1_port(struct hfc_multi *hc, struct hm_map *m, int pt)
hc->chan[hc->dnum[pt]].dch = dch;
hc->chan[hc->dnum[pt]].port = pt;
hc->chan[hc->dnum[pt]].nt_timer = -1;
- for (ch = 1; ch <= 31; ch++) {
- if (!((1 << ch) & hc->bmask[pt])) /* skip unused channel */
+ for (ch = 0; ch <= 31; ch++) {
+ /* skip unused channel */
+ if (!((1 << ch) & hc->bmask[pt]))
continue;
bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
if (!bch) {
diff --git a/include/linux/mISDNif.h b/include/linux/mISDNif.h
index f474f40..850fe1f 100644
--- a/include/linux/mISDNif.h
+++ b/include/linux/mISDNif.h
@@ -37,7 +37,7 @@
*/
#define MISDN_MAJOR_VERSION 1
#define MISDN_MINOR_VERSION 1
-#define MISDN_RELEASE 28
+#define MISDN_RELEASE 29
/* primitives for information exchange
* generell format
@@ -363,31 +363,36 @@ clear_channelmap(u_int nr, u_char *map)
}
/* CONTROL_CHANNEL parameters */
-#define MISDN_CTRL_GETOP 0x0000
-#define MISDN_CTRL_LOOP 0x0001
-#define MISDN_CTRL_CONNECT 0x0002
-#define MISDN_CTRL_DISCONNECT 0x0004
-#define MISDN_CTRL_GET_PCM_SLOTS 0x0010
-#define MISDN_CTRL_SET_PCM_SLOTS 0x0020
-#define MISDN_CTRL_SETPEER 0x0040
-#define MISDN_CTRL_UNSETPEER 0x0080
-#define MISDN_CTRL_RX_OFF 0x0100
-#define MISDN_CTRL_FILL_EMPTY 0x0200
-#define MISDN_CTRL_GETPEER 0x0400
-#define MISDN_CTRL_L1_TIMER3 0x0800
-#define MISDN_CTRL_HW_FEATURES_OP 0x2000
-#define MISDN_CTRL_HW_FEATURES 0x2001
-#define MISDN_CTRL_HFC_OP 0x4000
-#define MISDN_CTRL_HFC_PCM_CONN 0x4001
-#define MISDN_CTRL_HFC_PCM_DISC 0x4002
-#define MISDN_CTRL_HFC_CONF_JOIN 0x4003
-#define MISDN_CTRL_HFC_CONF_SPLIT 0x4004
-#define MISDN_CTRL_HFC_RECEIVE_OFF 0x4005
-#define MISDN_CTRL_HFC_RECEIVE_ON 0x4006
-#define MISDN_CTRL_HFC_ECHOCAN_ON 0x4007
-#define MISDN_CTRL_HFC_ECHOCAN_OFF 0x4008
-#define MISDN_CTRL_HFC_WD_INIT 0x4009
-#define MISDN_CTRL_HFC_WD_RESET 0x400A
+#define MISDN_CTRL_GETOP 0x00000000
+#define MISDN_CTRL_LOOP 0x00000001
+#define MISDN_CTRL_CONNECT 0x00000002
+#define MISDN_CTRL_DISCONNECT 0x00000004
+#define MISDN_CTRL_GET_PCM_SLOTS 0x00000010
+#define MISDN_CTRL_SET_PCM_SLOTS 0x00000020
+#define MISDN_CTRL_SETPEER 0x00000040
+#define MISDN_CTRL_UNSETPEER 0x00000080
+#define MISDN_CTRL_RX_OFF 0x00000100
+#define MISDN_CTRL_FILL_EMPTY 0x00000200
+#define MISDN_CTRL_GETPEER 0x00000400
+#define MISDN_CTRL_L1_TIMER3 0x00000800
+#define MISDN_CTRL_HW_FEATURES_OP 0x00002000
+#define MISDN_CTRL_HW_FEATURES 0x00002001
+#define MISDN_CTRL_HFC_OP 0x00004000
+#define MISDN_CTRL_HFC_PCM_CONN 0x00004001
+#define MISDN_CTRL_HFC_PCM_DISC 0x00004002
+#define MISDN_CTRL_HFC_CONF_JOIN 0x00004003
+#define MISDN_CTRL_HFC_CONF_SPLIT 0x00004004
+#define MISDN_CTRL_HFC_RECEIVE_OFF 0x00004005
+#define MISDN_CTRL_HFC_RECEIVE_ON 0x00004006
+#define MISDN_CTRL_HFC_ECHOCAN_ON 0x00004007
+#define MISDN_CTRL_HFC_ECHOCAN_OFF 0x00004008
+#define MISDN_CTRL_HFC_WD_INIT 0x00004009
+#define MISDN_CTRL_HFC_WD_RESET 0x0000400A
+#define MISDN_CTRL_L1_TESTS 0x00010000
+#define MISDN_CTRL_L1_STATE_TEST 0x00010001
+#define MISDN_CTRL_L1_AIS_TEST 0x00010002
+#define MISDN_CTRL_L1_TS0_MODE 0x00010003
+#define MISDN_CTRL_L1_GET_SYNC_INFO 0x00010004
/* special PCM slot numbers */
#define MISDN_PCM_SLOT_DISABLE -1 /* PCM disabled */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 2/8] mISDN: Fix refcounting bug
From: Karsten Keil @ 2012-04-28 11:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Karsten Keil
In-Reply-To: <1335613404-10187-1-git-send-email-kkeil@linux-pingi.de>
From: Karsten Keil <isdn@linux-pingi.de>
Under some configs it was still not possible to unload the driver,
because the module use count was srewed up.
Signed-off-by: Karsten Keil <keil@b1-systems.de>
---
drivers/isdn/mISDN/tei.c | 52 +++++++++++++++++++++++++++++++++------------
1 files changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/isdn/mISDN/tei.c b/drivers/isdn/mISDN/tei.c
index 969766f..25ed826 100644
--- a/drivers/isdn/mISDN/tei.c
+++ b/drivers/isdn/mISDN/tei.c
@@ -790,18 +790,22 @@ tei_ph_data_ind(struct teimgr *tm, u_int mt, u_char *dp, int len)
static struct layer2 *
create_new_tei(struct manager *mgr, int tei, int sapi)
{
- u_long opt = 0;
- u_long flags;
- int id;
- struct layer2 *l2;
+ u_long opt = 0;
+ u_long flags;
+ int id;
+ struct layer2 *l2;
+ struct channel_req rq;
if (!mgr->up)
return NULL;
if ((tei >= 0) && (tei < 64))
test_and_set_bit(OPTION_L2_FIXEDTEI, &opt);
- if (mgr->ch.st->dev->Dprotocols
- & ((1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1)))
+ if (mgr->ch.st->dev->Dprotocols & ((1 << ISDN_P_TE_E1) |
+ (1 << ISDN_P_NT_E1))) {
test_and_set_bit(OPTION_L2_PMX, &opt);
+ rq.protocol = ISDN_P_NT_E1;
+ } else
+ rq.protocol = ISDN_P_NT_S0;
l2 = create_l2(mgr->up, ISDN_P_LAPD_NT, opt, tei, sapi);
if (!l2) {
printk(KERN_WARNING "%s:no memory for layer2\n", __func__);
@@ -836,6 +840,14 @@ create_new_tei(struct manager *mgr, int tei, int sapi)
l2->ch.recv = mgr->ch.recv;
l2->ch.peer = mgr->ch.peer;
l2->ch.ctrl(&l2->ch, OPEN_CHANNEL, NULL);
+ /* We need open here L1 for the manager as well (refcounting) */
+ rq.adr.dev = mgr->ch.st->dev->id;
+ id = mgr->ch.st->own.ctrl(&mgr->ch.st->own, OPEN_CHANNEL, &rq);
+ if (id < 0) {
+ printk(KERN_WARNING "%s: cannot open L1\n", __func__);
+ l2->ch.ctrl(&l2->ch, CLOSE_CHANNEL, NULL);
+ l2 = NULL;
+ }
}
return l2;
}
@@ -978,10 +990,11 @@ TEIrelease(struct layer2 *l2)
static int
create_teimgr(struct manager *mgr, struct channel_req *crq)
{
- struct layer2 *l2;
- u_long opt = 0;
- u_long flags;
- int id;
+ struct layer2 *l2;
+ u_long opt = 0;
+ u_long flags;
+ int id;
+ struct channel_req l1rq;
if (*debug & DEBUG_L2_TEI)
printk(KERN_DEBUG "%s: %s proto(%x) adr(%d %d %d %d)\n",
@@ -1016,6 +1029,7 @@ create_teimgr(struct manager *mgr, struct channel_req *crq)
if (crq->protocol == ISDN_P_LAPD_TE)
test_and_set_bit(MGR_OPT_USER, &mgr->options);
}
+ l1rq.adr = crq->adr;
if (mgr->ch.st->dev->Dprotocols
& ((1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1)))
test_and_set_bit(OPTION_L2_PMX, &opt);
@@ -1055,24 +1069,34 @@ create_teimgr(struct manager *mgr, struct channel_req *crq)
l2->tm->tei_m.fsm = &teifsmu;
l2->tm->tei_m.state = ST_TEI_NOP;
l2->tm->tval = 1000; /* T201 1 sec */
+ if (test_bit(OPTION_L2_PMX, &opt))
+ l1rq.protocol = ISDN_P_TE_E1;
+ else
+ l1rq.protocol = ISDN_P_TE_S0;
} else {
l2->tm->tei_m.fsm = &teifsmn;
l2->tm->tei_m.state = ST_TEI_NOP;
l2->tm->tval = 2000; /* T202 2 sec */
+ if (test_bit(OPTION_L2_PMX, &opt))
+ l1rq.protocol = ISDN_P_NT_E1;
+ else
+ l1rq.protocol = ISDN_P_NT_S0;
}
mISDN_FsmInitTimer(&l2->tm->tei_m, &l2->tm->timer);
write_lock_irqsave(&mgr->lock, flags);
id = get_free_id(mgr);
list_add_tail(&l2->list, &mgr->layer2);
write_unlock_irqrestore(&mgr->lock, flags);
- if (id < 0) {
- l2->ch.ctrl(&l2->ch, CLOSE_CHANNEL, NULL);
- } else {
+ if (id >= 0) {
l2->ch.nr = id;
l2->up->nr = id;
crq->ch = &l2->ch;
- id = 0;
+ /* We need open here L1 for the manager as well (refcounting) */
+ id = mgr->ch.st->own.ctrl(&mgr->ch.st->own, OPEN_CHANNEL,
+ &l1rq);
}
+ if (id < 0)
+ l2->ch.ctrl(&l2->ch, CLOSE_CHANNEL, NULL);
return id;
}
--
1.7.3.4
^ permalink raw reply related
* [PATCH 5/8] mISDN: Make layer1 timer 3 value configurable
From: Karsten Keil @ 2012-04-28 11:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Karsten Keil
In-Reply-To: <1335613404-10187-1-git-send-email-kkeil@linux-pingi.de>
From: Karsten Keil <isdn@linux-pingi.de>
For certification test it is very useful to change the layer1
timer3 value on runtime.
Signed-off-by: Karsten Keil <kkeil@linux-pingi.de>
---
drivers/isdn/mISDN/layer1.c | 16 ++++++++++++++--
include/linux/mISDNhw.h | 3 +++
include/linux/mISDNif.h | 3 ++-
3 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/isdn/mISDN/layer1.c b/drivers/isdn/mISDN/layer1.c
index 0fc49b3..ff05153 100644
--- a/drivers/isdn/mISDN/layer1.c
+++ b/drivers/isdn/mISDN/layer1.c
@@ -30,11 +30,12 @@ struct layer1 {
struct FsmInst l1m;
struct FsmTimer timer;
int delay;
+ int t3_value;
struct dchannel *dch;
dchannel_l1callback *dcb;
};
-#define TIMER3_VALUE 7000
+#define TIMER3_DEFAULT_VALUE 7000
static
struct Fsm l1fsm_s = {NULL, 0, 0, NULL, NULL};
@@ -233,7 +234,7 @@ l1_activate_s(struct FsmInst *fi, int event, void *arg)
{
struct layer1 *l1 = fi->userdata;
- mISDN_FsmRestartTimer(&l1->timer, TIMER3_VALUE, EV_TIMER3, NULL, 2);
+ mISDN_FsmRestartTimer(&l1->timer, l1->t3_value, EV_TIMER3, NULL, 2);
test_and_set_bit(FLG_L1_T3RUN, &l1->Flags);
l1->dcb(l1->dch, HW_RESET_REQ);
}
@@ -356,6 +357,16 @@ l1_event(struct layer1 *l1, u_int event)
release_l1(l1);
break;
default:
+ if ((event & ~HW_TIMER3_VMASK) == HW_TIMER3_VALUE) {
+ int val = event & HW_TIMER3_VMASK;
+
+ if (val < 5)
+ val = 5;
+ if (val > 30)
+ val = 30;
+ l1->t3_value = val;
+ break;
+ }
if (*debug & DEBUG_L1)
printk(KERN_DEBUG "%s %x unhandled\n",
__func__, event);
@@ -377,6 +388,7 @@ create_l1(struct dchannel *dch, dchannel_l1callback *dcb) {
nl1->l1m.fsm = &l1fsm_s;
nl1->l1m.state = ST_L1_F3;
nl1->Flags = 0;
+ nl1->t3_value = TIMER3_DEFAULT_VALUE;
nl1->l1m.debug = *debug & DEBUG_L1_FSM;
nl1->l1m.userdata = nl1;
nl1->l1m.userint = 0;
diff --git a/include/linux/mISDNhw.h b/include/linux/mISDNhw.h
index 74d5734..7075753 100644
--- a/include/linux/mISDNhw.h
+++ b/include/linux/mISDNhw.h
@@ -136,6 +136,9 @@ extern int create_l1(struct dchannel *, dchannel_l1callback *);
#define HW_TESTRX_RAW 0x9602
#define HW_TESTRX_HDLC 0x9702
#define HW_TESTRX_OFF 0x9802
+#define HW_TIMER3_IND 0x9902
+#define HW_TIMER3_VALUE 0x9a00
+#define HW_TIMER3_VMASK 0x00FF
struct layer1;
extern int l1_event(struct layer1 *, u_int);
diff --git a/include/linux/mISDNif.h b/include/linux/mISDNif.h
index b7457e8..322d316 100644
--- a/include/linux/mISDNif.h
+++ b/include/linux/mISDNif.h
@@ -37,7 +37,7 @@
*/
#define MISDN_MAJOR_VERSION 1
#define MISDN_MINOR_VERSION 1
-#define MISDN_RELEASE 26
+#define MISDN_RELEASE 27
/* primitives for information exchange
* generell format
@@ -374,6 +374,7 @@ clear_channelmap(u_int nr, u_char *map)
#define MISDN_CTRL_RX_OFF 0x0100
#define MISDN_CTRL_FILL_EMPTY 0x0200
#define MISDN_CTRL_GETPEER 0x0400
+#define MISDN_CTRL_L1_TIMER3 0x0800
#define MISDN_CTRL_HW_FEATURES_OP 0x2000
#define MISDN_CTRL_HW_FEATURES 0x2001
#define MISDN_CTRL_HFC_OP 0x4000
--
1.7.3.4
^ permalink raw reply related
* [PATCH 0/8] mISDN: Collection of patches for layer1/layer2
From: Karsten Keil @ 2012-04-28 11:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev
These patches are mainly the outcome of a TBR3 recertification done
within BT labs.
The patches itself are very well tested more as 10000 valid/invalid
call setup were done in preparartion for the TBR3 aproval.
For net-next.
Andreas Eversberg (1):
mISDN: Added PH_* state info to tei manager.
Karsten Keil (7):
mISDN: Fix refcounting bug
Sometimes the ISDN chip only controls the D-channel
mISDN: L2 timeouts need to be queued as L2 event
mISDN: Make layer1 timer 3 value configurable
mISDN: Layer1 statemachine fix
mISDN: Help to identify the card
mISDN: Add 2MBit mode for HFC E1 card
drivers/isdn/hardware/mISDN/hfc_multi.h | 79 +++---
drivers/isdn/hardware/mISDN/hfcmulti.c | 426 ++++++++++++++++++++++++++-----
drivers/isdn/mISDN/core.c | 16 ++
drivers/isdn/mISDN/layer1.c | 37 ++-
drivers/isdn/mISDN/layer2.c | 119 +++++++---
drivers/isdn/mISDN/socket.c | 3 +
drivers/isdn/mISDN/tei.c | 71 ++++--
include/linux/mISDNhw.h | 6 +
include/linux/mISDNif.h | 71 ++++--
9 files changed, 649 insertions(+), 179 deletions(-)
--
1.7.3.4
^ permalink raw reply
* [PATCH 4/8] mISDN: L2 timeouts need to be queued as L2 event
From: Karsten Keil @ 2012-04-28 11:43 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Karsten Keil
In-Reply-To: <1335613404-10187-1-git-send-email-kkeil@linux-pingi.de>
From: Karsten Keil <isdn@linux-pingi.de>
To be full preemptiv safe, we cannot handle a L2 timeout in the timer
context itself, we should do all actions via the D-channel thread.
Signed-off-by: Karsten Keil <kkeil@linux-pingi.de>
---
drivers/isdn/mISDN/layer2.c | 58 +++++++++++++++++++++++++++++++++++++++---
drivers/isdn/mISDN/tei.c | 13 +++++++--
include/linux/mISDNif.h | 9 ++++++-
3 files changed, 71 insertions(+), 9 deletions(-)
diff --git a/drivers/isdn/mISDN/layer2.c b/drivers/isdn/mISDN/layer2.c
index 39d7375..d421495 100644
--- a/drivers/isdn/mISDN/layer2.c
+++ b/drivers/isdn/mISDN/layer2.c
@@ -58,6 +58,8 @@ enum {
EV_L1_DEACTIVATE,
EV_L2_T200,
EV_L2_T203,
+ EV_L2_T200I,
+ EV_L2_T203I,
EV_L2_SET_OWN_BUSY,
EV_L2_CLEAR_OWN_BUSY,
EV_L2_FRAME_ERROR,
@@ -86,6 +88,8 @@ static char *strL2Event[] =
"EV_L1_DEACTIVATE",
"EV_L2_T200",
"EV_L2_T203",
+ "EV_L2_T200I",
+ "EV_L2_T203I",
"EV_L2_SET_OWN_BUSY",
"EV_L2_CLEAR_OWN_BUSY",
"EV_L2_FRAME_ERROR",
@@ -276,6 +280,31 @@ ph_data_confirm(struct layer2 *l2, struct mISDNhead *hh, struct sk_buff *skb) {
return ret;
}
+static void
+l2_timeout(struct FsmInst *fi, int event, void *arg)
+{
+ struct layer2 *l2 = fi->userdata;
+ struct sk_buff *skb;
+ struct mISDNhead *hh;
+
+ skb = mI_alloc_skb(0, GFP_ATOMIC);
+ if (!skb) {
+ printk(KERN_WARNING "L2(%d,%d) nr:%x timer %s lost - no skb\n",
+ l2->sapi, l2->tei, l2->ch.nr, event == EV_L2_T200 ?
+ "T200" : "T203");
+ return;
+ }
+ hh = mISDN_HEAD_P(skb);
+ hh->prim = event == EV_L2_T200 ? DL_TIMER200_IND : DL_TIMER203_IND;
+ hh->id = l2->ch.nr;
+ if (*debug & DEBUG_TIMER)
+ printk(KERN_DEBUG "L2(%d,%d) nr:%x timer %s expired\n",
+ l2->sapi, l2->tei, l2->ch.nr, event == EV_L2_T200 ?
+ "T200" : "T203");
+ if (l2->ch.st)
+ l2->ch.st->own.recv(&l2->ch.st->own, skb);
+}
+
static int
l2mgr(struct layer2 *l2, u_int prim, void *arg) {
long c = (long)arg;
@@ -1814,11 +1843,16 @@ static struct FsmNode L2FnList[] =
{ST_L2_8, EV_L2_SUPER, l2_st8_got_super},
{ST_L2_7, EV_L2_I, l2_got_iframe},
{ST_L2_8, EV_L2_I, l2_got_iframe},
- {ST_L2_5, EV_L2_T200, l2_st5_tout_200},
- {ST_L2_6, EV_L2_T200, l2_st6_tout_200},
- {ST_L2_7, EV_L2_T200, l2_st7_tout_200},
- {ST_L2_8, EV_L2_T200, l2_st8_tout_200},
- {ST_L2_7, EV_L2_T203, l2_st7_tout_203},
+ {ST_L2_5, EV_L2_T200, l2_timeout},
+ {ST_L2_6, EV_L2_T200, l2_timeout},
+ {ST_L2_7, EV_L2_T200, l2_timeout},
+ {ST_L2_8, EV_L2_T200, l2_timeout},
+ {ST_L2_7, EV_L2_T203, l2_timeout},
+ {ST_L2_5, EV_L2_T200I, l2_st5_tout_200},
+ {ST_L2_6, EV_L2_T200I, l2_st6_tout_200},
+ {ST_L2_7, EV_L2_T200I, l2_st7_tout_200},
+ {ST_L2_8, EV_L2_T200I, l2_st8_tout_200},
+ {ST_L2_7, EV_L2_T203I, l2_st7_tout_203},
{ST_L2_7, EV_L2_ACK_PULL, l2_pull_iqueue},
{ST_L2_7, EV_L2_SET_OWN_BUSY, l2_set_own_busy},
{ST_L2_8, EV_L2_SET_OWN_BUSY, l2_set_own_busy},
@@ -1932,6 +1966,14 @@ l2_send(struct mISDNchannel *ch, struct sk_buff *skb)
if (*debug & DEBUG_L2_RECV)
printk(KERN_DEBUG "%s: prim(%x) id(%x) sapi(%d) tei(%d)\n",
__func__, hh->prim, hh->id, l2->sapi, l2->tei);
+ if (hh->prim == DL_INTERN_MSG) {
+ struct mISDNhead *chh = hh + 1; /* saved copy */
+
+ *hh = *chh;
+ if (*debug & DEBUG_L2_RECV)
+ printk(KERN_DEBUG "%s: prim(%x) id(%x) internal msg\n",
+ __func__, hh->prim, hh->id);
+ }
switch (hh->prim) {
case PH_DATA_IND:
ret = ph_data_indication(l2, hh, skb);
@@ -1987,6 +2029,12 @@ l2_send(struct mISDNchannel *ch, struct sk_buff *skb)
ret = mISDN_FsmEvent(&l2->l2m, EV_L2_DL_RELEASE_REQ,
skb);
break;
+ case DL_TIMER200_IND:
+ mISDN_FsmEvent(&l2->l2m, EV_L2_T200I, NULL);
+ break;
+ case DL_TIMER203_IND:
+ mISDN_FsmEvent(&l2->l2m, EV_L2_T203I, NULL);
+ break;
default:
if (*debug & DEBUG_L2)
l2m_debug(&l2->l2m, "l2 unknown pr %04x",
diff --git a/drivers/isdn/mISDN/tei.c b/drivers/isdn/mISDN/tei.c
index 25ed826..c7f6bea 100644
--- a/drivers/isdn/mISDN/tei.c
+++ b/drivers/isdn/mISDN/tei.c
@@ -1293,7 +1293,7 @@ static int
mgr_bcast(struct mISDNchannel *ch, struct sk_buff *skb)
{
struct manager *mgr = container_of(ch, struct manager, bcast);
- struct mISDNhead *hh = mISDN_HEAD_P(skb);
+ struct mISDNhead *hhc, *hh = mISDN_HEAD_P(skb);
struct sk_buff *cskb = NULL;
struct layer2 *l2;
u_long flags;
@@ -1308,10 +1308,17 @@ mgr_bcast(struct mISDNchannel *ch, struct sk_buff *skb)
skb = NULL;
} else {
if (!cskb)
- cskb = skb_copy(skb, GFP_KERNEL);
+ cskb = skb_copy(skb, GFP_ATOMIC);
}
if (cskb) {
- ret = l2->ch.send(&l2->ch, cskb);
+ hhc = mISDN_HEAD_P(cskb);
+ /* save original header behind normal header */
+ hhc++;
+ *hhc = *hh;
+ hhc--;
+ hhc->prim = DL_INTERN_MSG;
+ hhc->id = l2->ch.nr;
+ ret = ch->st->own.recv(&ch->st->own, cskb);
if (ret) {
if (*debug & DEBUG_SEND_ERR)
printk(KERN_DEBUG
diff --git a/include/linux/mISDNif.h b/include/linux/mISDNif.h
index bdda647..b7457e8 100644
--- a/include/linux/mISDNif.h
+++ b/include/linux/mISDNif.h
@@ -37,7 +37,7 @@
*/
#define MISDN_MAJOR_VERSION 1
#define MISDN_MINOR_VERSION 1
-#define MISDN_RELEASE 24
+#define MISDN_RELEASE 26
/* primitives for information exchange
* generell format
@@ -115,6 +115,11 @@
#define MDL_ERROR_IND 0x1F04
#define MDL_ERROR_RSP 0x5F04
+/* intern layer 2 */
+#define DL_TIMER200_IND 0x7004
+#define DL_TIMER203_IND 0x7304
+#define DL_INTERN_MSG 0x7804
+
/* DL_INFORMATION_IND types */
#define DL_INFO_L2_CONNECT 0x0001
#define DL_INFO_L2_REMOVED 0x0002
@@ -289,6 +294,8 @@ struct mISDNversion {
unsigned short release;
};
+#define MAX_DEVICE_ID 63
+
struct mISDN_devinfo {
u_int id;
u_int Dprotocols;
--
1.7.3.4
^ permalink raw reply related
* [PATCH] RPS: Sparse connection optimizations
From: Deng-Cheng Zhu @ 2012-04-28 10:10 UTC (permalink / raw)
To: davem, therbert, netdev; +Cc: dczhu
From: Deng-Cheng Zhu <dczhu@mips.com>
Currently, choosing target CPU to process the incoming packet is based on
skb->rxhash. In the case of sparse connections, this could lead to
relatively low and inconsistent bandwidth while doing network throughput
tests -- CPU selection in the RPS map is imbalanced. Even with the same
hash value, 2 packets could come from different devices. Besides, on
architectures like MIPS with multi-threaded cores, siblings of CPU0 should
not be selected when others are not saturated.
This patch introduces a feature that allows some flows to select their CPUs
by looping the RPS CPU maps. Some tests were performed on the MIPS Malta
1004K platform (2 cores, each with 2 VPEs) at 25Mhz with 2 Intel Pro/1000
NICs. The Malta board works as a router between 2 PCs. Using iperf, here
are results:
| Original Kernel | Patched Kernel |
-------|-----------------------------|-----------------------------|-------
| SUM SUM SUM2 SUM3 | SUM SUM SUM2 SUM3 | SUM3
| 1->2 2->1 | 1->2 2->1 | Delta
-------|-----------------------------|-----------------------------|-------
1x 1 | 33.70 29.10 62.80 657.40 | 46.70 46.30 93.00 928.80 | 41.28%
2 | 46.20 29.30 75.50 | 46.80 46.20 93.00 |
3 | 25.50 17.60 43.10 | 46.70 45.90 92.60 |
4 | 38.00 29.10 67.10 | 46.80 46.20 93.00 |
5 | 46.10 17.30 63.40 | 46.80 46.40 93.20 |
6 | 36.80 29.00 65.80 | 46.60 46.20 92.80 |
7 | 46.10 28.10 74.20 | 46.70 46.20 92.90 |
8 | 46.10 27.90 74.00 | 46.70 46.00 92.70 |
9 | 36.70 27.80 64.50 | 46.80 46.20 93.00 |
10 | 38.00 29.00 67.00 | 46.60 46.00 92.60 |
-------|-----------------------------|-----------------------------|-------
2x 1 | 30.90 35.60 66.50 674.32 | 47.40 44.60 92.00 902.80 | 33.88%
2 | 36.80 17.81 54.61 | 46.30 39.20 85.50 |
3 | 41.10 17.35 58.45 | 47.40 44.70 92.10 |
4 | 41.10 35.50 76.60 | 47.50 45.20 92.70 |
5 | 41.20 35.70 76.90 | 47.50 39.00 86.50 |
6 | 36.70 40.20 76.90 | 47.40 44.90 92.30 |
7 | 29.40 18.06 47.46 | 46.90 45.20 92.10 |
8 | 34.50 40.10 74.60 | 47.00 44.80 91.80 |
9 | 34.00 35.80 69.80 | 46.40 45.00 91.40 |
10 | 37.00 35.50 72.50 | 47.40 39.00 86.40 |
-------|-----------------------------|-----------------------------|-------
3x 1 | 45.40 36.90 82.30 774.89 | 45.30 46.90 92.20 895.50 | 15.56%
2 | 44.00 19.12 63.12 | 45.20 46.50 91.70 |
3 | 36.90 38.20 75.10 | 45.90 40.60 86.50 |
4 | 39.20 37.30 76.50 | 45.50 40.30 85.80 |
5 | 43.30 39.43 82.73 | 45.60 46.10 91.70 |
6 | 42.70 39.55 82.25 | 45.40 46.30 91.70 |
7 | 41.20 39.56 80.76 | 45.60 46.20 91.80 |
8 | 44.60 38.00 82.60 | 45.30 40.30 85.60 |
9 | 35.43 37.30 72.73 | 45.50 40.50 86.00 |
10 | 39.70 37.10 76.80 | 45.80 46.70 92.50 |
-------|-----------------------------|-----------------------------|-------
4x 1 | 41.07 35.09 76.16 738.34 | 41.79 45.70 87.49 845.24 | 14.48%
2 | 38.40 34.92 73.32 | 42.30 40.21 82.51 |
3 | 33.18 34.76 67.94 | 41.95 44.70 86.65 |
4 | 41.18 34.81 75.99 | 41.44 39.69 81.13 |
5 | 34.52 34.46 68.98 | 41.07 39.61 80.68 |
6 | 41.72 34.15 75.87 | 40.76 45.40 86.16 |
7 | 38.81 39.43 78.24 | 42.40 45.30 87.70 |
8 | 40.86 38.08 78.94 | 41.58 44.02 85.60 |
9 | 34.80 38.82 73.62 | 42.20 39.95 82.15 |
10 | 30.48 38.80 69.28 | 41.37 43.80 85.17 |
-------|-----------------------------|-----------------------------|-------
6x 1 | 35.59 34.10 69.69 706.58 | 37.28 41.59 78.87 772.02 | 9.26%
2 | 35.53 39.02 74.55 | 39.42 38.47 77.89 |
3 | 40.74 31.54 72.28 | 37.12 36.17 73.29 |
4 | 37.64 35.66 73.30 | 39.16 41.60 80.76 |
5 | 36.87 31.35 68.22 | 39.83 38.03 77.86 |
6 | 37.65 34.99 72.64 | 39.72 39.56 79.28 |
7 | 37.05 38.70 75.75 | 35.72 36.13 71.85 |
8 | 35.56 34.15 69.71 | 38.24 41.17 79.41 |
9 | 29.18 31.16 60.34 | 39.81 37.39 77.20 |
10 | 34.09 36.01 70.10 | 39.88 35.73 75.61 |
-------|-----------------------------|-----------------------------|-------
8x 1 | 31.38 36.37 67.75 677.76 | 38.25 37.38 75.63 739.60 | 9.12%
2 | 35.77 34.04 69.81 | 36.37 41.39 77.76 |
3 | 32.53 32.83 65.36 | 34.64 34.54 69.18 |
4 | 29.67 36.76 66.43 | 38.37 37.45 75.82 |
5 | 33.99 34.77 68.76 | 35.39 36.71 72.10 |
6 | 32.31 34.05 66.36 | 34.23 37.65 71.88 |
7 | 33.37 38.29 71.66 | 38.28 35.32 73.60 |
8 | 30.83 36.18 67.01 | 38.26 37.32 75.58 |
9 | 34.37 33.14 67.51 | 35.01 37.81 72.82 |
10 | 32.74 34.37 67.11 | 34.20 41.03 75.23 |
-------|-----------------------------|-----------------------------|-------
12x 1 | 31.22 32.81 64.03 649.48 | 30.47 37.07 67.54 681.10 | 4.87%
2 | 29.63 34.46 64.09 | 34.98 35.63 70.61 |
3 | 32.47 28.61 61.08 | 33.09 35.88 68.97 |
4 | 32.22 31.01 63.23 | 32.89 36.09 68.98 |
5 | 29.49 35.92 65.41 | 32.92 33.48 66.40 |
6 | 32.07 34.29 66.36 | 32.56 34.62 67.18 |
7 | 31.13 35.65 66.78 | 35.22 36.62 71.84 |
8 | 32.96 37.00 69.96 | 32.53 37.08 69.61 |
9 | 28.85 32.59 61.44 | 32.67 34.46 67.13 |
10 | 32.71 34.39 67.10 | 30.94 31.90 62.84 |
-------|-----------------------------|-----------------------------|-------
16x 1 | 29.55 35.64 65.19 634.00 | 30.03 34.37 64.40 643.42 | 1.49%
2 | 29.13 32.61 61.74 | 30.86 30.66 61.52 |
3 | 29.87 34.52 64.39 | 29.53 36.59 66.12 |
4 | 28.16 30.54 58.70 | 29.01 35.66 64.67 |
5 | 30.04 34.35 64.39 | 30.72 35.18 65.90 |
6 | 27.45 36.73 64.18 | 30.81 28.83 59.64 |
7 | 28.34 38.18 66.52 | 30.71 33.56 64.27 |
8 | 27.11 38.22 65.33 | 32.35 35.85 68.20 |
9 | 28.53 32.93 61.46 | 31.21 32.35 63.56 |
10 | 28.77 33.33 62.10 | 30.99 34.15 65.14 |
-------|-----------------------------|-----------------------------|-------
20x 1 | 30.57 36.96 67.53 641.27 | 30.27 34.99 65.26 617.18 | -3.76%
2 | 26.23 36.64 62.87 | 28.85 32.50 61.35 |
3 | 28.84 36.58 65.42 | 28.97 33.79 62.76 |
4 | 30.59 31.27 61.86 | 27.34 32.83 60.17 |
5 | 27.91 32.32 60.23 | 28.32 32.82 61.14 |
6 | 28.77 33.32 62.09 | 26.95 33.08 60.03 |
7 | 29.60 38.10 67.70 | 28.14 35.74 63.88 |
8 | 29.84 36.38 66.22 | 29.00 30.01 59.01 |
9 | 28.68 35.84 64.52 | 27.67 31.44 59.11 |
10 | 28.16 34.67 62.83 | 30.54 33.93 64.47 |
-------|-----------------------------|-----------------------------|-------
24x 1 | 30.89 34.15 65.05 617.21 | 28.75 33.91 62.66 618.79 | 0.26%
2 | 30.53 34.38 64.91 | 29.39 31.85 61.24 |
3 | 28.13 35.20 63.33 | 28.36 34.01 62.37 |
4 | 29.21 30.46 59.67 | 25.12 34.24 59.36 |
5 | 24.72 35.46 60.18 | 29.38 32.60 61.98 |
6 | 28.52 27.00 55.52 | 30.23 35.08 65.32 |
7 | 25.12 35.46 60.57 | 28.44 31.91 60.35 |
8 | 27.46 35.93 63.39 | 29.10 34.27 63.37 |
9 | 27.62 32.56 60.18 | 27.85 34.83 62.68 |
10 | 30.44 33.99 64.42 | 28.61 30.84 59.46 |
-------|-----------------------------|-----------------------------|-------
28x 1 | 28.30 30.15 58.45 613.21 | 26.97 30.28 57.25 592.80 | -3.33%
2 | 30.78 31.02 61.80 | 28.27 30.33 58.61 |
3 | 26.76 34.01 60.77 | 27.89 31.18 59.07 |
4 | 27.18 32.31 59.49 | 29.42 33.19 62.61 |
5 | 30.44 35.69 66.13 | 25.56 32.96 58.52 |
6 | 27.70 30.55 58.25 | 27.94 32.19 60.12 |
7 | 28.60 34.18 62.77 | 25.18 31.26 56.44 |
8 | 29.40 31.41 60.81 | 28.78 28.71 57.49 |
9 | 27.11 34.13 61.24 | 28.65 32.48 61.13 |
10 | 30.07 33.43 63.50 | 25.99 35.59 61.57 |
-------|-----------------------------|-----------------------------|-------
32x 1 | 27.41 29.16 56.58 590.24 | 27.94 30.75 58.69 584.15 | -1.03%
2 | 26.54 27.85 54.39 | 28.92 34.46 63.37 |
3 | 26.68 34.18 60.86 | 25.71 31.12 56.83 |
4 | 27.31 34.72 62.03 | 26.70 31.35 58.04 |
5 | 28.82 32.89 61.71 | 27.45 33.83 61.28 |
6 | 25.49 28.59 54.08 | 27.94 32.06 60.00 |
7 | 25.80 34.75 60.55 | 26.63 33.22 59.85 |
8 | 24.39 32.44 56.83 | 26.17 32.27 58.43 |
9 | 29.33 35.19 64.53 | 24.11 26.43 50.54 |
10 | 28.02 30.66 58.68 | 25.45 31.67 57.11 |
Note:
1. Data unit: Mbits/sec
2. 1x, 2x...32x: N iperf instances were running in parallel.
3. SUM 1->2: PC1 is the iperf client and PC2 is the iperf server. The sum
of all instances. Bidirectional tests were performed as well.
4. Tested with iptables/NAT + RPS (RPS CPU mask is 0xe for both NICs, which
means CPU1/2/3 are covered).
5. CONFIG_NR_RPS_MAP_LOOPS == 4 by default.
6. Duration for each test: 100 seconds.
7. The results show that the overhead brought in by this feature is limited
as the number of connections goes higher.
Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com>
---
net/Kconfig | 22 ++++++++++++++++
net/core/dev.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 0 deletions(-)
diff --git a/net/Kconfig b/net/Kconfig
index e07272d..d5aa682 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -222,6 +222,28 @@ config RPS
depends on SMP && SYSFS && USE_GENERIC_SMP_HELPERS
default y
+config RPS_SPARSE_FLOW_OPTIMIZATION
+ bool "RPS optimizations for sparse flows"
+ depends on RPS
+ default n
+ ---help---
+ This feature will try to map some network flows to consecutive
+ CPUs in the RPS map. It will bring in some per packet overhead
+ but should be able to do good to network throughput in the case
+ of low number of connections while not much affecting other
+ cases. (e.g. relatively consistent and high bandwidth in single
+ connection tests).
+
+config NR_RPS_MAP_LOOPS
+ int "Number of loops walking RPS map before hash indexing (1-5)"
+ range 1 5
+ depends on RPS_SPARSE_FLOW_OPTIMIZATION
+ default "4"
+ ---help---
+ It defines how many loops to go through the RPS map while
+ determing target CPU to process the incoming packet. After that,
+ the decision will fall back on hash indexing the RPS map.
+
config RFS_ACCEL
boolean
depends on RPS && GENERIC_HARDIRQS
diff --git a/net/core/dev.c b/net/core/dev.c
index c25d453..82633df 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -2698,6 +2698,79 @@ set_rps_cpu(struct net_device *dev, struct sk_buff *skb,
return rflow;
}
+#ifdef CONFIG_RPS_SPARSE_FLOW_OPTIMIZATION
+struct cpu_flow {
+ struct net_device *dev;
+ u32 rxhash;
+ unsigned long ts;
+};
+
+static struct cpu_flow flow[CONFIG_NR_RPS_MAP_LOOPS][NR_CPUS];
+static unsigned long hash_active;
+
+#define FLOW_INACTIVE(now, base) (time_after((now), (base) + HZ) || \
+ unlikely(time_before((now), (base))))
+
+static int find_cpu(const struct rps_map *map, const struct sk_buff *skb)
+{
+ int i, l, cpu, do_alloc = 0;
+ unsigned long now = jiffies;
+
+retry:
+ for (l = 0; l < CONFIG_NR_RPS_MAP_LOOPS; l++) {
+ for (i = map->len - 1; i >= 0; i--) {
+ cpu = map->cpus[i];
+
+/*
+ * We've got CONFIG_SMP to do RPS, so only arch define is needed here to access
+ * sibling specific information.
+ */
+#if defined(CONFIG_MIPS)
+ /*
+ * Some architectures like MIPS have multithreaded
+ * cores. When CPU0 serves NIC IRQs, its siblings, e.g.
+ * CPU1, have less horsepower than CPUs in other cores
+ * in the RPS CPU map. We simply leave them alone here.
+ */
+ if (cpu_isset(cpu, cpu_sibling_map[0]))
+ continue;
+#endif
+
+ if (do_alloc) {
+ if (flow[l][cpu].dev == NULL ||
+ FLOW_INACTIVE(now, flow[l][cpu].ts)) {
+ flow[l][cpu].dev = skb->dev;
+ flow[l][cpu].rxhash = skb->rxhash;
+ flow[l][cpu].ts = now;
+ return cpu;
+ }
+ } else {
+ /*
+ * Unlike hash indexing, this avoids packet
+ * processing imbalance across CPUs.
+ */
+ if (flow[l][cpu].rxhash == skb->rxhash &&
+ flow[l][cpu].dev == skb->dev &&
+ !FLOW_INACTIVE(now, flow[l][cpu].ts)) {
+ flow[l][cpu].ts = now;
+ return cpu;
+ }
+ }
+ }
+ }
+
+ if (FLOW_INACTIVE(now, hash_active) && do_alloc == 0) {
+ do_alloc = 1;
+ goto retry;
+ }
+
+ /* For all other flows */
+ hash_active = now;
+
+ return map->cpus[((u64) skb->rxhash * map->len) >> 32];
+}
+#endif
+
/*
* get_rps_cpu is called from netif_receive_skb and returns the target
* CPU from the RPS map of the receiving queue for a given skb.
@@ -2780,7 +2853,11 @@ static int get_rps_cpu(struct net_device *dev, struct sk_buff *skb,
}
if (map) {
+#ifdef CONFIG_RPS_SPARSE_FLOW_OPTIMIZATION
+ tcpu = find_cpu(map, skb);
+#else
tcpu = map->cpus[((u64) skb->rxhash * map->len) >> 32];
+#endif
if (cpu_online(tcpu)) {
cpu = tcpu;
--
1.7.1
^ permalink raw reply related
* Re: [RFT] sky2: fix status length check on older chips
From: Niccolò Belli @ 2012-04-28 10:25 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev
In-Reply-To: <20120427194635.0b65b0ee@nehalam.linuxnetplumber.net>
Il 28/04/2012 04:46, Stephen Hemminger ha scritto:
> Are you using VLAN's? the whole problem report only applies if using VLAN
> on old hardware.
No, I don't use VLANs. There are VLANs in my network but I simply
connect to the default one from my laptop.
Niccolò
^ permalink raw reply
* Re: [PATCH 23/28] mISDN: Fix compiler warnings
From: Karsten Keil @ 2012-04-28 10:03 UTC (permalink / raw)
To: David Laight; +Cc: Karsten Keil, David Miller, netdev, isdn4linux
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6026B6EEE@saturn3.aculab.com>
Hi David,
thanks for the review.
Am 24.04.2012 10:24, schrieb David Laight:
>
>> diff --git a/drivers/isdn/hardware/mISDN/hfcmulti.c
>> b/drivers/isdn/hardware/mISDN/hfcmulti.c
>> index 884c090..144c35a 100644
>> --- a/drivers/isdn/hardware/mISDN/hfcmulti.c
>> +++ b/drivers/isdn/hardware/mISDN/hfcmulti.c
>> @@ -2456,12 +2456,12 @@ handle_timer_irq(struct hfc_multi *hc)
>> spin_unlock_irqrestore(&HFClock, flags);
>> }
>> if (test_bit(HFC_CHIP_2MBITRAW, &hc->chip)) {
>> - if (hc->created[hc->chan[0].port] && hc->chan[ch].bch &&
>> + ch = 0;
>> + if (hc->created[hc->chan[ch].port] &&
>> hc->chan[ch].bch &&
>> test_bit(FLG_ACTIVE, &hc->chan[ch].bch->Flags)) {
>> ch_activ++;
>> - hfcmulti_tx(hc, 0);
>> - hfcmulti_rx(hc, 0);
>> - ch = 1;
>> + hfcmulti_tx(hc, ch);
>> + hfcmulti_rx(hc, ch);
>> if (hc->chan[ch].dch &&
>> hc->chan[ch].nt_timer > -1) {
>> dch = hc->chan[ch].dch;
>
> That seems to change the fields checked in the final 'if'.
> Not sure it is the intended behaviour.
>
Yes it is the correct behavior, it was wrong before. If the
HFC_CHIP_2MBITRAW flag is set, only hc->chan[0] should be used.
This did not make trouble, because you normally do not use any
D-channnel in 2 MBit mode, calling the D-Channel specific functions
still makes sense for the L1 state machine, when using this
mode to emulate a E1 Layer1 tester, which was the main reson to
implement this mode.
Karsten
^ permalink raw reply
* RE: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable for MSI interrupt
From: Huang, Xiong @ 2012-04-28 9:53 UTC (permalink / raw)
To: Rodriguez, Luis
Cc: davem@davemloft.net, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, qca-linux-team, nic-devel
In-Reply-To: <20120428020510.GJ14465@tux>
Thanks Luis, just one question:
I don't know which kernel version contains the updated pci/quirks.c, so,
if I write the patch file (a 58-drivers-pci-quirks.patch) as:
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
+ pdev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
+#endif
It seems not good for the kernel with updated pci/quirks.c
Any better suggestion ? thanks
-Xiong
> -----Original Message-----
> From: Luis R. Rodriguez [mailto:mcgrof@gmail.com] On Behalf Of Luis R.
> Rodriguez
> Sent: Saturday, April 28, 2012 10:05
> To: Huang, Xiong
> Cc: davem@davemloft.net; netdev@vger.kernel.org; linux-
> kernel@vger.kernel.org; qca-linux-team; nic-devel
> Subject: Re: [PATCH 01/10] atl1c: add workaround for issue of bit INTX-disable
> for MSI interrupt
>
> On Sat, Apr 28, 2012 at 09:58:36AM +0800, xiong wrote:
> > All supported devices have one issue that msi interrupt doesn't assert
> > if pci command register bit (PCI_COMMAND_INTX_DISABLE) is set.
> > Add workaround in drivers/pci/quirks.c
> >
> > Signed-off-by: xiong <xiong@qca.qualcomm.com>
> > ---
> > drivers/pci/quirks.c | 12 ++++++++++++
> > 1 files changed, 12 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index
> > 4bf7102..953ec3f 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -2626,6 +2626,18 @@
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,
> > 0x4374, DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
> > quirk_msi_intx_disable_bug);
> >
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
> > + quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
> > + quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
> > + quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
> > + quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
> > + quirk_msi_intx_disable_bug);
> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
> > + quirk_msi_intx_disable_bug);
> > #endif /* CONFIG_PCI_MSI */
>
> Xiong -- just a heads up, I think to backport these then you can send me patches
> for compat-wireless to do the work around itself on the driver on a patch under
> patches/ you can say create a 58-drivers-pci-quirks.patch which pathces your
> driver there.
>
> Luis
^ permalink raw reply
* Re: [PATCH 1/8] isdn/gigaset: ratelimit CAPI message dumps
From: Karsten Keil @ 2012-04-28 9:29 UTC (permalink / raw)
To: Tilman Schmidt
Cc: Karsten Keil, David Miller, Hansjoerg Lipp, i4ldeveloper, netdev,
linux-kernel
In-Reply-To: <4F9A7510.5010808@imap.cc>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Am 27.04.2012 12:29, schrieb Tilman Schmidt:
> Am 26.04.2012 08:39, schrieb Karsten Keil:
>> Am 26.04.2012 01:02, schrieb Tilman Schmidt:
>>> Introduce a global ratelimit for CAPI message dumps to protect
>>> against possible log flood. Drop the ratelimit for ignored
>>> messages which is now covered by the global one.
>>
>> Hmm, I think the only CAPI messages which would need a ratelimit
>> are related to the DATA_B3 messages. If you need CAPI debug
>> messages in most cases you do not need all of the DATA_B3, but
>> you do not want to miss any other message related to the call
>> control. With a general rate limit you do not have the control,
>> which messages are logged and which are not.
>
> The ratelimit introduced by this patch only applies to messages
> other than DATA_B3. Logging DATA_B3 messages is not done via
> dump_cmsg().
>
Thanks for the clarification, forget about my objection.
I ack this patch now.
> I'd like to ratelimit specifically non-DATA_B3 messages because I
> saw a (possibly buggy) CAPI application flooding the log with
> FACILITY messages. Equally important, I'd like to make the
> ratelimit in do_nothing() / do_unsupported() bursty because I had
> a case where I needed to see several ignored/unhandled CAPI
> messages in quick succession. So this patch is killing two birds
> with one stone for me.
>
> The burst limit of 20 messages in 20 seconds is chosen to allow a
> complete call setup sequence to be logged, while limiting to one
> message per second in the long run.
>
>> And here maybe some cases, when even the DATA_B3 are important
>> (e.g. searching bugs in flow control), so I would make it still
>> conditional to allow to print all messages.
>
> DATA_B3 dumps produce an enormous amount of log data and are
> therefore controlled separately by the DEBUG_MCMD flag. Someone
> who enables that should know what she or he does. But if you need
> them, you need them all. A ratelimit doesn't make sense there in
> my experience.
>
>> And I'm not sure, if this is really something for stable.
>
> It's pretty simple and localized, a net simplification, and only
> affects generation of debugging messages, so I think it's safe.
> But if you see a problem there I can drop the "CC: stable" line.
>
I let the decision about it to you and the stable maintainers.
- --
Karsten Keil
Linux Kernel Development
Tel: +49 175 7249132
Mail: keil@b1-systems.de
B1 Systems GmbH
Osterfeldstraße 7 / 85088 Vohburg / http://www.b1-systems.de
GF: Ralph Dehner / Unternehmenssitz: Vohburg / AG: Ingolstadt,HRB 3537
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.16 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/
iEYEARECAAYFAk+buHwACgkQo5VVC52CNcRoygCfWwPlWZ+A48OwEkr/MtK6PeNG
0UEAnipdxPSZDKa4s99LlGYwvggWIIAJ
=CLr6
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^ permalink raw reply
* Re: [PATCH 1/4 net-next] net: allow skb->head to be a page fragment
From: David Miller @ 2012-04-28 9:22 UTC (permalink / raw)
To: alexander.duyck
Cc: eric.dumazet, alexander.h.duyck, netdev, ilpo.jarvinen, ncardwell,
therbert, maze, jeffrey.t.kirsher, bhutchings, mcarlson, mchan,
herbert
In-Reply-To: <CAKgT0Uc9B0Zrocw=mtb1oS2tHL73tdB4Vj7rKdb7xcikeJxp2g@mail.gmail.com>
From: Alexander Duyck <alexander.duyck@gmail.com>
Date: Sat, 28 Apr 2012 01:27:24 -0700
> I was thinking there would be a bigger gain with a change like this
> but essentially all you are doing is making the packets more mergable
> resulting in you being able to drop the 256 bytes for the sk_buff in
> either GRO or when it gets queued for the socket.
He's also avoiding the SLUB slow path almost all of the time.
^ permalink raw reply
* Re: [PATCH] 9p: disconnect channel when PCI device is removed
From: Sasha Levin @ 2012-04-28 8:55 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: davem, ericvh, jvrao, rusty, netdev, linux-kernel, davej
In-Reply-To: <87ehrodjt6.fsf@skywalker.in.ibm.com>
On Mon, Apr 16, 2012 at 12:59 PM, Aneesh Kumar K.V
<aneesh.kumar@linux.vnet.ibm.com> wrote:
> Sasha Levin <levinsasha928@gmail.com> writes:
>
>> On Sun, Apr 15, 2012 at 2:27 PM, Aneesh Kumar K.V
>> <aneesh.kumar@linux.vnet.ibm.com> wrote:
>>> Sasha Levin <levinsasha928@gmail.com> writes:
>>>
>>>> When a virtio_9p pci device is being removed, we should close down any
>>>> active channels and free up resources, we're not supposed to BUG() if there's
>>>> still an open channel since it's a valid case when removing the PCI device.
>>>>
>>>> Otherwise, removing the PCI device with an open channel would cause the
>>>> following BUG():
>>>>
>>> ...
>>>
>>>> diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c
>>>> index 3d43206..5af18d1 100644
>>>> --- a/net/9p/trans_virtio.c
>>>> +++ b/net/9p/trans_virtio.c
>>>> @@ -615,7 +615,8 @@ static void p9_virtio_remove(struct virtio_device *vdev)
>>>> {
>>>> struct virtio_chan *chan = vdev->priv;
>>>>
>>>> - BUG_ON(chan->inuse);
>>>> + if (chan->inuse)
>>>> + p9_virtio_close(chan->client);
>>>> vdev->config->del_vqs(vdev);
>>>>
>>>> mutex_lock(&virtio_9p_lock);
>>>
>>> But an umount should have resulted in p9_virtio_close ? How are you
>>> removing the device ? Are you removing the device with file system
>>> mounted ?. In that case may be we should return EBUSY ?
>>
>> I signal the underlying PCI device to remove (echo 1 >
>> /sys/devices/pci0000\:00/[...]/remove), we can't really prevent that
>> thing so we must clean up ourselves.
>
> What does that mean for the mounted file system ? What would happen to
> the pending fs operations in that case ?
I'm guessing that all of them should be canceled. virtio-pci simulates
a PCI device, if the PCI device is unplugged there's not much to do
about the filesystem or pending requests.
^ permalink raw reply
* Re: [PATCH 1/4 net-next] net: allow skb->head to be a page fragment
From: Alexander Duyck @ 2012-04-28 8:27 UTC (permalink / raw)
To: Eric Dumazet
Cc: Alexander Duyck, David Miller, netdev, Ilpo Järvinen,
Neal Cardwell, Tom Herbert, Maciej Żenczykowski,
Jeff Kirsher, Ben Hutchings, Matt Carlson, Michael Chan,
Herbert Xu
In-Reply-To: <1335597403.2900.29.camel@edumazet-glaptop>
On Sat, Apr 28, 2012 at 12:16 AM, Eric Dumazet <eric.dumazet@gmail.com> wrote:
> On Fri, 2012-04-27 at 17:27 -0700, Alexander Duyck wrote:
>> On 04/27/2012 03:33 AM, Eric Dumazet wrote:
>> > From: Eric Dumazet <edumazet@google.com>
>> >
>
>> > +struct sk_buff *build_skb(void *data, unsigned int frag_size)
>> > {
>> > struct skb_shared_info *shinfo;
>> > struct sk_buff *skb;
>> > - unsigned int size;
>> > + unsigned int size = frag_size ? : ksize(data);
>> >
>> > skb = kmem_cache_alloc(skbuff_head_cache, GFP_ATOMIC);
>> > if (!skb)
>> > return NULL;
>> >
>> > - size = ksize(data) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
>> > + size -= SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
>> >
>> > memset(skb, 0, offsetof(struct sk_buff, tail));
>> > skb->truesize = SKB_TRUESIZE(size);
>> > + skb->head_frag = frag_size != 0;
>> > atomic_set(&skb->users, 1);
>> > skb->head = data;
>> > skb->data = data;
>>
>> This doesn't seem right to me. You are only counting the piece of the
>> page that got filled with data and the piece that will get overwritten
>> with the shared info. What about the rest of the page? It looks like
>> in the tg3 patch you have the driver using a half page. Based on this
>> function I suspect the resultant truesize would be something like 64 +
>> 256 + 320 for an ack. Shouldn't your truesize in that case be 2048 + 256?
>
> Re-reading your mail, I think you missed fact that tg3 driver currently
> uses a kmalloc(64+1500+14+SKB_DATA_ALIGN(sizeof(struct
> skb_shared_info)) , so basically does a kmalloc(2048). But this is done
> before NIC fills the frame in it, so we cant know what will be the frame
> length...
>
> So build_skb() does later a ksize(data) and this gives 2048, even for a
> small ACK packet ...
>
> So the spirit of this patch is not to change any truesize.
>
> tg3 for example splits a PAGE_SIZE into 2048 bytes frags (2 frags on x86
> for example). Its done about the same in Intel IGB driver (IGB assumes
> PAGE_SIZE is 4096 since it uses PAGE_SIZE/2)
>
> The only thing that is changed here is where skb->head is allocated
> from : kmalloc() caches or a frag from a page (and one reference to
> page->_count)
>
> Hope this clears your concern ?
I had misread what was happening here. I didn't fully understand what
build_skb was doing before reading the patch and that is what led me
astray.
I was thinking there would be a bigger gain with a change like this
but essentially all you are doing is making the packets more mergable
resulting in you being able to drop the 256 bytes for the sk_buff in
either GRO or when it gets queued for the socket.
What caught my eye about all this is that I could probably cut a lot
of work out of the ixgbe driver and FCoE path by modifying things so
that FCoE packets could be received as a page, and then treated as a
linear skb without needing calls to skb_linearize.
Thanks,
Alex
^ permalink raw reply
* Re: [PATCH 4/4] forcedeth: add transmit timestamping support
From: Eric Dumazet @ 2012-04-28 7:49 UTC (permalink / raw)
To: Willem de Bruijn; +Cc: davem, netdev, jeffrey.t.kirscher, eilong, aabdulla
In-Reply-To: <1335553447-11964-5-git-send-email-willemb@google.com>
On Fri, 2012-04-27 at 15:04 -0400, Willem de Bruijn wrote:
> Insert an skb_tx_timestamp call in both ndo_start_xmit routines
> Tested to work for the nv_start_xmit_optimized case
>
> Signed-off-by: Willem de Bruijn <willemb@google.com>
> ---
> drivers/net/ethernet/nvidia/forcedeth.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/ethernet/nvidia/forcedeth.c b/drivers/net/ethernet/nvidia/forcedeth.c
> index d93a088..928913c 100644
> --- a/drivers/net/ethernet/nvidia/forcedeth.c
> +++ b/drivers/net/ethernet/nvidia/forcedeth.c
> @@ -2279,6 +2279,8 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
>
> netdev_sent_queue(np->dev, skb->len);
>
> + skb_tx_timestamp(skb);
> +
> np->put_tx.orig = put_tx;
>
> spin_unlock_irqrestore(&np->lock, flags);
> @@ -2426,6 +2428,8 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
>
> netdev_sent_queue(np->dev, skb->len);
>
> + skb_tx_timestamp(skb);
> +
> np->put_tx.ex = put_tx;
>
> spin_unlock_irqrestore(&np->lock, flags);
Acked-by: Eric Dumazet <edumazet@google.com>
^ permalink raw reply
* Re: [PATCH 3/4] bnx2x: add transmit timestamping support
From: Eric Dumazet @ 2012-04-28 7:48 UTC (permalink / raw)
To: Willem de Bruijn; +Cc: davem, netdev, jeffrey.t.kirscher, eilong, aabdulla
In-Reply-To: <1335553447-11964-4-git-send-email-willemb@google.com>
On Fri, 2012-04-27 at 15:04 -0400, Willem de Bruijn wrote:
> Signed-off-by: Willem de Bruijn <willemb@google.com>
> ---
> drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
> index 60d5b54..afa6cbb 100644
> --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
> +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
> @@ -2953,6 +2953,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
>
> netdev_tx_sent_queue(txq, skb->len);
>
> + skb_tx_timestamp(skb);
> +
> txdata->tx_pkt_prod++;
> /*
> * Make sure that the BD data is updated before updating the producer
Acked-by: Eric Dumazet <edumazet@google.com>
^ permalink raw reply
* Re: [PATCH 2/4] e1000e: add transmit timestamping support
From: Eric Dumazet @ 2012-04-28 7:47 UTC (permalink / raw)
To: Willem de Bruijn; +Cc: davem, netdev, jeffrey.t.kirscher, eilong, aabdulla
In-Reply-To: <1335553447-11964-3-git-send-email-willemb@google.com>
On Fri, 2012-04-27 at 15:04 -0400, Willem de Bruijn wrote:
> Signed-off-by: Willem de Bruijn <willemb@google.com>
> ---
> drivers/net/ethernet/intel/e1000e/netdev.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
> index 851f793..c5d9ad7 100644
> --- a/drivers/net/ethernet/intel/e1000e/netdev.c
> +++ b/drivers/net/ethernet/intel/e1000e/netdev.c
> @@ -5150,6 +5150,8 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
> /* if count is 0 then mapping error has occurred */
> count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
> if (count) {
> + skb_tx_timestamp(skb);
> +
> netdev_sent_queue(netdev, skb->len);
> e1000_tx_queue(tx_ring, tx_flags, count);
> /* Make sure there is space in the ring for the next send. */
Acked-by: Eric Dumazet <edumazet@google.com>
^ permalink raw reply
* Re: [PATCH 1/4] e1000: add transmit timestamping support
From: Eric Dumazet @ 2012-04-28 7:47 UTC (permalink / raw)
To: Willem de Bruijn; +Cc: davem, netdev, jeffrey.t.kirscher, eilong, aabdulla
In-Reply-To: <1335553447-11964-2-git-send-email-willemb@google.com>
On Fri, 2012-04-27 at 15:04 -0400, Willem de Bruijn wrote:
> Signed-off-by: Willem de Bruijn <willemb@google.com>
> ---
> drivers/net/ethernet/intel/e1000/e1000_main.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/e1000/e1000_main.c b/drivers/net/ethernet/intel/e1000/e1000_main.c
> index 3d712f2..40438ea 100644
> --- a/drivers/net/ethernet/intel/e1000/e1000_main.c
> +++ b/drivers/net/ethernet/intel/e1000/e1000_main.c
> @@ -3261,6 +3261,8 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
> nr_frags, mss);
>
> if (count) {
> + skb_tx_timestamp(skb);
> +
> e1000_tx_queue(adapter, tx_ring, tx_flags, count);
> /* Make sure there is space in the ring for the next send. */
> e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
Acked-by: Eric Dumazet <edumazet@google.com>
^ permalink raw reply
* [PATCH net-next] bnx2x: remove some bloat
From: Eric Dumazet @ 2012-04-28 7:39 UTC (permalink / raw)
To: David Miller
Cc: netdev, Neal Cardwell, Tom Herbert, Maciej Żenczykowski,
Jeff Kirsher, Ben Hutchings, Matt Carlson, Michael Chan,
Herbert Xu, Eilon Greenstein
From: Eric Dumazet <edumazet@google.com>
Before doing skb->head_frag work on bnx2x driver, I found too much stuff
was inlined in bnx2x/bnx2x_cmn.h for no good reason and made my work not
very easy.
Move some big functions out of this include file to the respective .c
file.
A lot of inline keywords are not needed at all in this huge driver.
text data bss dec hex filename
490083 1270 56 491409 77f91 bnx2x/bnx2x.ko.before
484206 1270 56 485532 7689c bnx2x/bnx2x.ko
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Eilon Greenstein <eilong@broadcom.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Cc: Maciej Żenczykowski <maze@google.com>
Cc: Neal Cardwell <ncardwell@google.com>
Cc: Tom Herbert <therbert@google.com>
Cc: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Cc: Ben Hutchings <bhutchings@solarflare.com>
Cc: Matt Carlson <mcarlson@broadcom.com>
Cc: Michael Chan <mchan@broadcom.com>
---
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 285 +++++++
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h | 362 ----------
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 24
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 325 ++++++--
drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c | 2
5 files changed, 499 insertions(+), 499 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index 9c5bc5d..276bc1c 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -358,8 +358,8 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
* Approximate value of the MSS for this aggregation calculated using
* the first packet of it.
*/
-static inline u16 bnx2x_set_lro_mss(struct bnx2x *bp, u16 parsing_flags,
- u16 len_on_bd)
+static u16 bnx2x_set_lro_mss(struct bnx2x *bp, u16 parsing_flags,
+ u16 len_on_bd)
{
/*
* TPA arrgregation won't have either IP options or TCP options
@@ -385,6 +385,36 @@ static inline u16 bnx2x_set_lro_mss(struct bnx2x *bp, u16 parsing_flags,
return len_on_bd - hdrs_len;
}
+static int bnx2x_alloc_rx_sge(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp, u16 index)
+{
+ struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
+ struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
+ struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
+ dma_addr_t mapping;
+
+ if (unlikely(page == NULL)) {
+ BNX2X_ERR("Can't alloc sge\n");
+ return -ENOMEM;
+ }
+
+ mapping = dma_map_page(&bp->pdev->dev, page, 0,
+ SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
+ __free_pages(page, PAGES_PER_SGE_SHIFT);
+ BNX2X_ERR("Can't map sge\n");
+ return -ENOMEM;
+ }
+
+ sw_buf->page = page;
+ dma_unmap_addr_set(sw_buf, mapping, mapping);
+
+ sge->addr_hi = cpu_to_le32(U64_HI(mapping));
+ sge->addr_lo = cpu_to_le32(U64_LO(mapping));
+
+ return 0;
+}
+
static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
struct bnx2x_agg_info *tpa_info,
u16 pages,
@@ -483,11 +513,11 @@ static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
return 0;
}
-static inline void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
- struct bnx2x_agg_info *tpa_info,
- u16 pages,
- struct eth_end_agg_rx_cqe *cqe,
- u16 cqe_idx)
+static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+ struct bnx2x_agg_info *tpa_info,
+ u16 pages,
+ struct eth_end_agg_rx_cqe *cqe,
+ u16 cqe_idx)
{
struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
u8 pad = tpa_info->placement_offset;
@@ -557,6 +587,36 @@ drop:
fp->eth_q_stats.rx_skb_alloc_failed++;
}
+static int bnx2x_alloc_rx_data(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp, u16 index)
+{
+ u8 *data;
+ struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
+ struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
+ dma_addr_t mapping;
+
+ data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
+ if (unlikely(data == NULL))
+ return -ENOMEM;
+
+ mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
+ fp->rx_buf_size,
+ DMA_FROM_DEVICE);
+ if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
+ kfree(data);
+ BNX2X_ERR("Can't map rx data\n");
+ return -ENOMEM;
+ }
+
+ rx_buf->data = data;
+ dma_unmap_addr_set(rx_buf, mapping, mapping);
+
+ rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
+ rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
+
+ return 0;
+}
+
int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
{
@@ -870,8 +930,8 @@ u16 bnx2x_get_mf_speed(struct bnx2x *bp)
*
* It uses a none-atomic bit operations because is called under the mutex.
*/
-static inline void bnx2x_fill_report_data(struct bnx2x *bp,
- struct bnx2x_link_report_data *data)
+static void bnx2x_fill_report_data(struct bnx2x *bp,
+ struct bnx2x_link_report_data *data)
{
u16 line_speed = bnx2x_get_mf_speed(bp);
@@ -989,6 +1049,47 @@ void __bnx2x_link_report(struct bnx2x *bp)
}
}
+static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
+{
+ int i;
+
+ for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
+ struct eth_rx_sge *sge;
+
+ sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
+ sge->addr_hi =
+ cpu_to_le32(U64_HI(fp->rx_sge_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
+
+ sge->addr_lo =
+ cpu_to_le32(U64_LO(fp->rx_sge_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
+ }
+}
+
+static void bnx2x_free_tpa_pool(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp, int last)
+{
+ int i;
+
+ for (i = 0; i < last; i++) {
+ struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
+ struct sw_rx_bd *first_buf = &tpa_info->first_buf;
+ u8 *data = first_buf->data;
+
+ if (data == NULL) {
+ DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
+ continue;
+ }
+ if (tpa_info->tpa_state == BNX2X_TPA_START)
+ dma_unmap_single(&bp->pdev->dev,
+ dma_unmap_addr(first_buf, mapping),
+ fp->rx_buf_size, DMA_FROM_DEVICE);
+ kfree(data);
+ first_buf->data = NULL;
+ }
+}
+
void bnx2x_init_rx_rings(struct bnx2x *bp)
{
int func = BP_FUNC(bp);
@@ -1362,7 +1463,7 @@ static int bnx2x_req_irq(struct bnx2x *bp)
return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
}
-static inline int bnx2x_setup_irqs(struct bnx2x *bp)
+static int bnx2x_setup_irqs(struct bnx2x *bp)
{
int rc = 0;
if (bp->flags & USING_MSIX_FLAG &&
@@ -1392,7 +1493,7 @@ static inline int bnx2x_setup_irqs(struct bnx2x *bp)
return 0;
}
-static inline void bnx2x_napi_enable(struct bnx2x *bp)
+static void bnx2x_napi_enable(struct bnx2x *bp)
{
int i;
@@ -1400,7 +1501,7 @@ static inline void bnx2x_napi_enable(struct bnx2x *bp)
napi_enable(&bnx2x_fp(bp, i, napi));
}
-static inline void bnx2x_napi_disable(struct bnx2x *bp)
+static void bnx2x_napi_disable(struct bnx2x *bp)
{
int i;
@@ -1487,7 +1588,7 @@ void bnx2x_set_num_queues(struct bnx2x *bp)
* bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
* will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
*/
-static inline int bnx2x_set_real_num_queues(struct bnx2x *bp)
+static int bnx2x_set_real_num_queues(struct bnx2x *bp)
{
int rc, tx, rx;
@@ -1519,7 +1620,7 @@ static inline int bnx2x_set_real_num_queues(struct bnx2x *bp)
return rc;
}
-static inline void bnx2x_set_rx_buf_size(struct bnx2x *bp)
+static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
{
int i;
@@ -1547,7 +1648,7 @@ static inline void bnx2x_set_rx_buf_size(struct bnx2x *bp)
}
}
-static inline int bnx2x_init_rss_pf(struct bnx2x *bp)
+static int bnx2x_init_rss_pf(struct bnx2x *bp)
{
int i;
u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
@@ -1614,7 +1715,7 @@ int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
return bnx2x_config_rss(bp, ¶ms);
}
-static inline int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
+static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
{
struct bnx2x_func_state_params func_params = {NULL};
@@ -1723,6 +1824,87 @@ bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err)
return true;
}
+/**
+ * bnx2x_bz_fp - zero content of the fastpath structure.
+ *
+ * @bp: driver handle
+ * @index: fastpath index to be zeroed
+ *
+ * Makes sure the contents of the bp->fp[index].napi is kept
+ * intact.
+ */
+static void bnx2x_bz_fp(struct bnx2x *bp, int index)
+{
+ struct bnx2x_fastpath *fp = &bp->fp[index];
+ struct napi_struct orig_napi = fp->napi;
+ /* bzero bnx2x_fastpath contents */
+ if (bp->stats_init)
+ memset(fp, 0, sizeof(*fp));
+ else {
+ /* Keep Queue statistics */
+ struct bnx2x_eth_q_stats *tmp_eth_q_stats;
+ struct bnx2x_eth_q_stats_old *tmp_eth_q_stats_old;
+
+ tmp_eth_q_stats = kzalloc(sizeof(struct bnx2x_eth_q_stats),
+ GFP_KERNEL);
+ if (tmp_eth_q_stats)
+ memcpy(tmp_eth_q_stats, &fp->eth_q_stats,
+ sizeof(struct bnx2x_eth_q_stats));
+
+ tmp_eth_q_stats_old =
+ kzalloc(sizeof(struct bnx2x_eth_q_stats_old),
+ GFP_KERNEL);
+ if (tmp_eth_q_stats_old)
+ memcpy(tmp_eth_q_stats_old, &fp->eth_q_stats_old,
+ sizeof(struct bnx2x_eth_q_stats_old));
+
+ memset(fp, 0, sizeof(*fp));
+
+ if (tmp_eth_q_stats) {
+ memcpy(&fp->eth_q_stats, tmp_eth_q_stats,
+ sizeof(struct bnx2x_eth_q_stats));
+ kfree(tmp_eth_q_stats);
+ }
+
+ if (tmp_eth_q_stats_old) {
+ memcpy(&fp->eth_q_stats_old, tmp_eth_q_stats_old,
+ sizeof(struct bnx2x_eth_q_stats_old));
+ kfree(tmp_eth_q_stats_old);
+ }
+
+ }
+
+ /* Restore the NAPI object as it has been already initialized */
+ fp->napi = orig_napi;
+
+ fp->bp = bp;
+ fp->index = index;
+ if (IS_ETH_FP(fp))
+ fp->max_cos = bp->max_cos;
+ else
+ /* Special queues support only one CoS */
+ fp->max_cos = 1;
+
+ /*
+ * set the tpa flag for each queue. The tpa flag determines the queue
+ * minimal size so it must be set prior to queue memory allocation
+ */
+ fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
+ (bp->flags & GRO_ENABLE_FLAG &&
+ bnx2x_mtu_allows_gro(bp->dev->mtu)));
+ if (bp->flags & TPA_ENABLE_FLAG)
+ fp->mode = TPA_MODE_LRO;
+ else if (bp->flags & GRO_ENABLE_FLAG)
+ fp->mode = TPA_MODE_GRO;
+
+#ifdef BCM_CNIC
+ /* We don't want TPA on an FCoE L2 ring */
+ if (IS_FCOE_FP(fp))
+ fp->disable_tpa = 1;
+#endif
+}
+
+
/* must be called with rtnl_lock */
int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
{
@@ -3167,7 +3349,7 @@ void bnx2x_free_fp_mem(struct bnx2x *bp)
bnx2x_free_fp_mem_at(bp, i);
}
-static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
+static void set_sb_shortcuts(struct bnx2x *bp, int index)
{
union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
if (!CHIP_IS_E1x(bp)) {
@@ -3183,6 +3365,63 @@ static inline void set_sb_shortcuts(struct bnx2x *bp, int index)
}
}
+/* Returns the number of actually allocated BDs */
+static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
+ int rx_ring_size)
+{
+ struct bnx2x *bp = fp->bp;
+ u16 ring_prod, cqe_ring_prod;
+ int i, failure_cnt = 0;
+
+ fp->rx_comp_cons = 0;
+ cqe_ring_prod = ring_prod = 0;
+
+ /* This routine is called only during fo init so
+ * fp->eth_q_stats.rx_skb_alloc_failed = 0
+ */
+ for (i = 0; i < rx_ring_size; i++) {
+ if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
+ failure_cnt++;
+ continue;
+ }
+ ring_prod = NEXT_RX_IDX(ring_prod);
+ cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
+ WARN_ON(ring_prod <= (i - failure_cnt));
+ }
+
+ if (failure_cnt)
+ BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
+ i - failure_cnt, fp->index);
+
+ fp->rx_bd_prod = ring_prod;
+ /* Limit the CQE producer by the CQE ring size */
+ fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
+ cqe_ring_prod);
+ fp->rx_pkt = fp->rx_calls = 0;
+
+ fp->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
+
+ return i - failure_cnt;
+}
+
+static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
+{
+ int i;
+
+ for (i = 1; i <= NUM_RCQ_RINGS; i++) {
+ struct eth_rx_cqe_next_page *nextpg;
+
+ nextpg = (struct eth_rx_cqe_next_page *)
+ &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
+ nextpg->addr_hi =
+ cpu_to_le32(U64_HI(fp->rx_comp_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
+ nextpg->addr_lo =
+ cpu_to_le32(U64_LO(fp->rx_comp_mapping +
+ BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
+ }
+}
+
static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
{
union host_hc_status_block *sb;
@@ -3672,9 +3911,9 @@ void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
}
-static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
- u8 fw_sb_id, u8 sb_index,
- u8 ticks)
+static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
+ u8 fw_sb_id, u8 sb_index,
+ u8 ticks)
{
u32 addr = BAR_CSTRORM_INTMEM +
@@ -3685,9 +3924,9 @@ static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
port, fw_sb_id, sb_index, ticks);
}
-static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
- u16 fw_sb_id, u8 sb_index,
- u8 disable)
+static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
+ u16 fw_sb_id, u8 sb_index,
+ u8 disable)
{
u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
u32 addr = BAR_CSTRORM_INTMEM +
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index cec993b..7cd99b7 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -612,53 +612,6 @@ static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
barrier();
}
-static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
- u8 idu_sb_id, bool is_Pf)
-{
- u32 data, ctl, cnt = 100;
- u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
- u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
- u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
- u32 sb_bit = 1 << (idu_sb_id%32);
- u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
- u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
-
- /* Not supported in BC mode */
- if (CHIP_INT_MODE_IS_BC(bp))
- return;
-
- data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
- << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
- IGU_REGULAR_CLEANUP_SET |
- IGU_REGULAR_BCLEANUP;
-
- ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
- func_encode << IGU_CTRL_REG_FID_SHIFT |
- IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
-
- DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
- data, igu_addr_data);
- REG_WR(bp, igu_addr_data, data);
- mmiowb();
- barrier();
- DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
- ctl, igu_addr_ctl);
- REG_WR(bp, igu_addr_ctl, ctl);
- mmiowb();
- barrier();
-
- /* wait for clean up to finish */
- while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
- msleep(20);
-
-
- if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
- DP(NETIF_MSG_HW,
- "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
- idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
- }
-}
-
static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
u8 storm, u16 index, u8 op, u8 update)
{
@@ -885,66 +838,6 @@ static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
bnx2x_clear_sge_mask_next_elems(fp);
}
-static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
- struct bnx2x_fastpath *fp, u16 index)
-{
- struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
- struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
- struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
- dma_addr_t mapping;
-
- if (unlikely(page == NULL)) {
- BNX2X_ERR("Can't alloc sge\n");
- return -ENOMEM;
- }
-
- mapping = dma_map_page(&bp->pdev->dev, page, 0,
- SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
- if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
- __free_pages(page, PAGES_PER_SGE_SHIFT);
- BNX2X_ERR("Can't map sge\n");
- return -ENOMEM;
- }
-
- sw_buf->page = page;
- dma_unmap_addr_set(sw_buf, mapping, mapping);
-
- sge->addr_hi = cpu_to_le32(U64_HI(mapping));
- sge->addr_lo = cpu_to_le32(U64_LO(mapping));
-
- return 0;
-}
-
-static inline int bnx2x_alloc_rx_data(struct bnx2x *bp,
- struct bnx2x_fastpath *fp, u16 index)
-{
- u8 *data;
- struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
- struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
- dma_addr_t mapping;
-
- data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
- if (unlikely(data == NULL))
- return -ENOMEM;
-
- mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
- fp->rx_buf_size,
- DMA_FROM_DEVICE);
- if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
- kfree(data);
- BNX2X_ERR("Can't map rx data\n");
- return -ENOMEM;
- }
-
- rx_buf->data = data;
- dma_unmap_addr_set(rx_buf, mapping, mapping);
-
- rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
- rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
-
- return 0;
-}
-
/* note that we are not allocating a new buffer,
* we are just moving one from cons to prod
* we are not creating a new mapping,
@@ -1042,66 +935,6 @@ static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
bnx2x_free_rx_sge(bp, fp, i);
}
-static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
- struct bnx2x_fastpath *fp, int last)
-{
- int i;
-
- for (i = 0; i < last; i++) {
- struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
- struct sw_rx_bd *first_buf = &tpa_info->first_buf;
- u8 *data = first_buf->data;
-
- if (data == NULL) {
- DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
- continue;
- }
- if (tpa_info->tpa_state == BNX2X_TPA_START)
- dma_unmap_single(&bp->pdev->dev,
- dma_unmap_addr(first_buf, mapping),
- fp->rx_buf_size, DMA_FROM_DEVICE);
- kfree(data);
- first_buf->data = NULL;
- }
-}
-
-static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
-{
- int i;
-
- for (i = 1; i <= NUM_TX_RINGS; i++) {
- struct eth_tx_next_bd *tx_next_bd =
- &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
-
- tx_next_bd->addr_hi =
- cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
- BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
- tx_next_bd->addr_lo =
- cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
- BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
- }
-
- SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
- txdata->tx_db.data.zero_fill1 = 0;
- txdata->tx_db.data.prod = 0;
-
- txdata->tx_pkt_prod = 0;
- txdata->tx_pkt_cons = 0;
- txdata->tx_bd_prod = 0;
- txdata->tx_bd_cons = 0;
- txdata->tx_pkt = 0;
-}
-
-static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
-{
- int i;
- u8 cos;
-
- for_each_tx_queue(bp, i)
- for_each_cos_in_tx_queue(&bp->fp[i], cos)
- bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]);
-}
-
static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
{
int i;
@@ -1119,80 +952,6 @@ static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
}
}
-static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
-{
- int i;
-
- for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
- struct eth_rx_sge *sge;
-
- sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
- sge->addr_hi =
- cpu_to_le32(U64_HI(fp->rx_sge_mapping +
- BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
-
- sge->addr_lo =
- cpu_to_le32(U64_LO(fp->rx_sge_mapping +
- BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
- }
-}
-
-static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
-{
- int i;
- for (i = 1; i <= NUM_RCQ_RINGS; i++) {
- struct eth_rx_cqe_next_page *nextpg;
-
- nextpg = (struct eth_rx_cqe_next_page *)
- &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
- nextpg->addr_hi =
- cpu_to_le32(U64_HI(fp->rx_comp_mapping +
- BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
- nextpg->addr_lo =
- cpu_to_le32(U64_LO(fp->rx_comp_mapping +
- BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
- }
-}
-
-/* Returns the number of actually allocated BDs */
-static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
- int rx_ring_size)
-{
- struct bnx2x *bp = fp->bp;
- u16 ring_prod, cqe_ring_prod;
- int i, failure_cnt = 0;
-
- fp->rx_comp_cons = 0;
- cqe_ring_prod = ring_prod = 0;
-
- /* This routine is called only during fo init so
- * fp->eth_q_stats.rx_skb_alloc_failed = 0
- */
- for (i = 0; i < rx_ring_size; i++) {
- if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
- failure_cnt++;
- continue;
- }
- ring_prod = NEXT_RX_IDX(ring_prod);
- cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
- WARN_ON(ring_prod <= (i - failure_cnt));
- }
-
- if (failure_cnt)
- BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
- i - failure_cnt, fp->index);
-
- fp->rx_bd_prod = ring_prod;
- /* Limit the CQE producer by the CQE ring size */
- fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
- cqe_ring_prod);
- fp->rx_pkt = fp->rx_calls = 0;
-
- fp->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
-
- return i - failure_cnt;
-}
-
/* Statistics ID are global per chip/path, while Client IDs for E1x are per
* port.
*/
@@ -1421,47 +1180,6 @@ static inline void __storm_memset_struct(struct bnx2x *bp,
REG_WR(bp, addr + (i * 4), data[i]);
}
-static inline void storm_memset_func_cfg(struct bnx2x *bp,
- struct tstorm_eth_function_common_config *tcfg,
- u16 abs_fid)
-{
- size_t size = sizeof(struct tstorm_eth_function_common_config);
-
- u32 addr = BAR_TSTRORM_INTMEM +
- TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
-
- __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
-}
-
-static inline void storm_memset_cmng(struct bnx2x *bp,
- struct cmng_init *cmng,
- u8 port)
-{
- int vn;
- size_t size = sizeof(struct cmng_struct_per_port);
-
- u32 addr = BAR_XSTRORM_INTMEM +
- XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
-
- __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
-
- for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
- int func = func_by_vn(bp, vn);
-
- addr = BAR_XSTRORM_INTMEM +
- XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
- size = sizeof(struct rate_shaping_vars_per_vn);
- __storm_memset_struct(bp, addr, size,
- (u32 *)&cmng->vnic.vnic_max_rate[vn]);
-
- addr = BAR_XSTRORM_INTMEM +
- XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
- size = sizeof(struct fairness_vars_per_vn);
- __storm_memset_struct(bp, addr, size,
- (u32 *)&cmng->vnic.vnic_min_rate[vn]);
- }
-}
-
/**
* bnx2x_wait_sp_comp - wait for the outstanding SP commands.
*
@@ -1544,86 +1262,6 @@ static inline bool bnx2x_mtu_allows_gro(int mtu)
*/
return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS;
}
-/**
- * bnx2x_bz_fp - zero content of the fastpath structure.
- *
- * @bp: driver handle
- * @index: fastpath index to be zeroed
- *
- * Makes sure the contents of the bp->fp[index].napi is kept
- * intact.
- */
-static inline void bnx2x_bz_fp(struct bnx2x *bp, int index)
-{
- struct bnx2x_fastpath *fp = &bp->fp[index];
- struct napi_struct orig_napi = fp->napi;
- /* bzero bnx2x_fastpath contents */
- if (bp->stats_init)
- memset(fp, 0, sizeof(*fp));
- else {
- /* Keep Queue statistics */
- struct bnx2x_eth_q_stats *tmp_eth_q_stats;
- struct bnx2x_eth_q_stats_old *tmp_eth_q_stats_old;
-
- tmp_eth_q_stats = kzalloc(sizeof(struct bnx2x_eth_q_stats),
- GFP_KERNEL);
- if (tmp_eth_q_stats)
- memcpy(tmp_eth_q_stats, &fp->eth_q_stats,
- sizeof(struct bnx2x_eth_q_stats));
-
- tmp_eth_q_stats_old =
- kzalloc(sizeof(struct bnx2x_eth_q_stats_old),
- GFP_KERNEL);
- if (tmp_eth_q_stats_old)
- memcpy(tmp_eth_q_stats_old, &fp->eth_q_stats_old,
- sizeof(struct bnx2x_eth_q_stats_old));
-
- memset(fp, 0, sizeof(*fp));
-
- if (tmp_eth_q_stats) {
- memcpy(&fp->eth_q_stats, tmp_eth_q_stats,
- sizeof(struct bnx2x_eth_q_stats));
- kfree(tmp_eth_q_stats);
- }
-
- if (tmp_eth_q_stats_old) {
- memcpy(&fp->eth_q_stats_old, tmp_eth_q_stats_old,
- sizeof(struct bnx2x_eth_q_stats_old));
- kfree(tmp_eth_q_stats_old);
- }
-
- }
-
- /* Restore the NAPI object as it has been already initialized */
- fp->napi = orig_napi;
-
- fp->bp = bp;
- fp->index = index;
- if (IS_ETH_FP(fp))
- fp->max_cos = bp->max_cos;
- else
- /* Special queues support only one CoS */
- fp->max_cos = 1;
-
- /*
- * set the tpa flag for each queue. The tpa flag determines the queue
- * minimal size so it must be set prior to queue memory allocation
- */
- fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
- (bp->flags & GRO_ENABLE_FLAG &&
- bnx2x_mtu_allows_gro(bp->dev->mtu)));
- if (bp->flags & TPA_ENABLE_FLAG)
- fp->mode = TPA_MODE_LRO;
- else if (bp->flags & GRO_ENABLE_FLAG)
- fp->mode = TPA_MODE_GRO;
-
-#ifdef BCM_CNIC
- /* We don't want TPA on an FCoE L2 ring */
- if (IS_FCOE_FP(fp))
- fp->disable_tpa = 1;
-#endif
-}
-
#ifdef BCM_CNIC
/**
* bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index faf8abd..ddc18ee 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -592,8 +592,8 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
-static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
- const struct reg_addr *reg_info)
+static bool bnx2x_is_reg_online(struct bnx2x *bp,
+ const struct reg_addr *reg_info)
{
if (CHIP_IS_E1(bp))
return IS_E1_ONLINE(reg_info->info);
@@ -610,7 +610,7 @@ static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
}
/******* Paged registers info selectors ********/
-static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
+static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_vals_e2;
@@ -620,7 +620,7 @@ static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
return NULL;
}
-static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
+static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_MODE_VALUES_E2;
@@ -630,7 +630,7 @@ static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
return 0;
}
-static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
+static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_write_regs_e2;
@@ -640,7 +640,7 @@ static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
return NULL;
}
-static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
+static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_WRITE_REGS_E2;
@@ -650,7 +650,7 @@ static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
return 0;
}
-static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
+static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return page_read_regs_e2;
@@ -660,7 +660,7 @@ static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
return NULL;
}
-static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
+static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
{
if (CHIP_IS_E2(bp))
return PAGE_READ_REGS_E2;
@@ -670,7 +670,7 @@ static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
return 0;
}
-static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
+static int __bnx2x_get_regs_len(struct bnx2x *bp)
{
int num_pages = __bnx2x_get_page_reg_num(bp);
int page_write_num = __bnx2x_get_page_write_num(bp);
@@ -715,7 +715,7 @@ static int bnx2x_get_regs_len(struct net_device *dev)
* ("read address"). There may be more than one write address per "page" and
* more than one read address per write address.
*/
-static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
+static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
{
u32 i, j, k, n;
/* addresses of the paged registers */
@@ -744,7 +744,7 @@ static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
}
}
-static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
+static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
{
u32 i, j;
@@ -2209,7 +2209,7 @@ static void bnx2x_self_test(struct net_device *dev,
/* ethtool statistics are displayed for all regular ethernet queues and the
* fcoe L2 queue if not disabled
*/
-static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
+static int bnx2x_num_stat_queues(struct bnx2x *bp)
{
return BNX2X_NUM_ETH_QUEUES(bp);
}
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 0708cb8..35b82e0 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -226,15 +226,15 @@ static LIST_HEAD(bnx2x_prev_list);
* General service functions
****************************************************************************/
-static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
+static void __storm_memset_dma_mapping(struct bnx2x *bp,
u32 addr, dma_addr_t mapping)
{
REG_WR(bp, addr, U64_LO(mapping));
REG_WR(bp, addr + 4, U64_HI(mapping));
}
-static inline void storm_memset_spq_addr(struct bnx2x *bp,
- dma_addr_t mapping, u16 abs_fid)
+static void storm_memset_spq_addr(struct bnx2x *bp,
+ dma_addr_t mapping, u16 abs_fid)
{
u32 addr = XSEM_REG_FAST_MEMORY +
XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
@@ -242,8 +242,8 @@ static inline void storm_memset_spq_addr(struct bnx2x *bp,
__storm_memset_dma_mapping(bp, addr, mapping);
}
-static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
- u16 pf_id)
+static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
+ u16 pf_id)
{
REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
pf_id);
@@ -255,8 +255,8 @@ static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
pf_id);
}
-static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
- u8 enable)
+static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
+ u8 enable)
{
REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
enable);
@@ -268,8 +268,8 @@ static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
enable);
}
-static inline void storm_memset_eq_data(struct bnx2x *bp,
- struct event_ring_data *eq_data,
+static void storm_memset_eq_data(struct bnx2x *bp,
+ struct event_ring_data *eq_data,
u16 pfid)
{
size_t size = sizeof(struct event_ring_data);
@@ -279,8 +279,8 @@ static inline void storm_memset_eq_data(struct bnx2x *bp,
__storm_memset_struct(bp, addr, size, (u32 *)eq_data);
}
-static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
- u16 pfid)
+static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
+ u16 pfid)
{
u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
REG_WR16(bp, addr, eq_prod);
@@ -676,7 +676,7 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
printk("%s" "end of fw dump\n", lvl);
}
-static inline void bnx2x_fw_dump(struct bnx2x *bp)
+static void bnx2x_fw_dump(struct bnx2x *bp)
{
bnx2x_fw_dump_lvl(bp, KERN_ERR);
}
@@ -996,8 +996,8 @@ static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
}
-static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
- u32 expected, u32 poll_count)
+static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
+ u32 expected, u32 poll_count)
{
u32 cur_cnt = poll_count;
u32 val;
@@ -1008,8 +1008,8 @@ static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
return val;
}
-static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
- char *msg, u32 poll_cnt)
+static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
+ char *msg, u32 poll_cnt)
{
u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
if (val != 0) {
@@ -1106,7 +1106,7 @@ static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
(((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
-static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
+static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
u32 poll_cnt)
{
struct sdm_op_gen op_gen = {0};
@@ -1140,7 +1140,7 @@ static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
return ret;
}
-static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
+static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
{
int pos;
u16 status;
@@ -1550,7 +1550,7 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
* Returns the recovery leader resource id according to the engine this function
* belongs to. Currently only only 2 engines is supported.
*/
-static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
+static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
{
if (BP_PATH(bp))
return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
@@ -1563,9 +1563,9 @@ static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
*
* @bp: driver handle
*
- * Tries to aquire a leader lock for cuurent engine.
+ * Tries to aquire a leader lock for current engine.
*/
-static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
+static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
{
return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
}
@@ -2331,6 +2331,35 @@ static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
"rate shaping and fairness are disabled\n");
}
+static void storm_memset_cmng(struct bnx2x *bp,
+ struct cmng_init *cmng,
+ u8 port)
+{
+ int vn;
+ size_t size = sizeof(struct cmng_struct_per_port);
+
+ u32 addr = BAR_XSTRORM_INTMEM +
+ XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
+
+ __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
+
+ for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
+ int func = func_by_vn(bp, vn);
+
+ addr = BAR_XSTRORM_INTMEM +
+ XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
+ size = sizeof(struct rate_shaping_vars_per_vn);
+ __storm_memset_struct(bp, addr, size,
+ (u32 *)&cmng->vnic.vnic_max_rate[vn]);
+
+ addr = BAR_XSTRORM_INTMEM +
+ XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
+ size = sizeof(struct fairness_vars_per_vn);
+ __storm_memset_struct(bp, addr, size,
+ (u32 *)&cmng->vnic.vnic_min_rate[vn]);
+ }
+}
+
/* This function is called upon link interrupt */
static void bnx2x_link_attn(struct bnx2x *bp)
{
@@ -2671,6 +2700,18 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
}
+static void storm_memset_func_cfg(struct bnx2x *bp,
+ struct tstorm_eth_function_common_config *tcfg,
+ u16 abs_fid)
+{
+ size_t size = sizeof(struct tstorm_eth_function_common_config);
+
+ u32 addr = BAR_TSTRORM_INTMEM +
+ TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
+
+ __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
+}
+
void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
{
if (CHIP_IS_E1x(bp)) {
@@ -2700,9 +2741,9 @@ void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
*
* Return the flags that are common for the Tx-only and not normal connections.
*/
-static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
- struct bnx2x_fastpath *fp,
- bool zero_stats)
+static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp,
+ bool zero_stats)
{
unsigned long flags = 0;
@@ -2722,9 +2763,9 @@ static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
return flags;
}
-static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
- struct bnx2x_fastpath *fp,
- bool leading)
+static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
+ struct bnx2x_fastpath *fp,
+ bool leading)
{
unsigned long flags = 0;
@@ -3117,7 +3158,7 @@ static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
* configure FW
* notify others function about the change
*/
-static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
+static void bnx2x_config_mf_bw(struct bnx2x *bp)
{
if (bp->link_vars.link_up) {
bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
@@ -3126,7 +3167,7 @@ static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
}
-static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
+static void bnx2x_set_mf_bw(struct bnx2x *bp)
{
bnx2x_config_mf_bw(bp);
bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
@@ -3213,7 +3254,7 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
}
/* must be called under the spq lock */
-static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
+static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
{
struct eth_spe *next_spe = bp->spq_prod_bd;
@@ -3229,7 +3270,7 @@ static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
}
/* must be called under the spq lock */
-static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
+static void bnx2x_sp_prod_update(struct bnx2x *bp)
{
int func = BP_FUNC(bp);
@@ -3251,7 +3292,7 @@ static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
* @cmd: command to check
* @cmd_type: command type
*/
-static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
+static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
{
if ((cmd_type == NONE_CONNECTION_TYPE) ||
(cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
@@ -3385,7 +3426,7 @@ static void bnx2x_release_alr(struct bnx2x *bp)
#define BNX2X_DEF_SB_ATT_IDX 0x0001
#define BNX2X_DEF_SB_IDX 0x0002
-static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
+static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
{
struct host_sp_status_block *def_sb = bp->def_status_blk;
u16 rc = 0;
@@ -3517,7 +3558,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
}
}
-static inline void bnx2x_fan_failure(struct bnx2x *bp)
+static void bnx2x_fan_failure(struct bnx2x *bp)
{
int port = BP_PORT(bp);
u32 ext_phy_config;
@@ -3547,7 +3588,7 @@ static inline void bnx2x_fan_failure(struct bnx2x *bp)
}
-static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
+static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
{
int port = BP_PORT(bp);
int reg_offset;
@@ -3587,7 +3628,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
}
}
-static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
+static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
{
u32 val;
@@ -3618,7 +3659,7 @@ static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
}
}
-static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
+static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
{
u32 val;
@@ -3662,7 +3703,7 @@ static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
}
}
-static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
+static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
{
u32 val;
@@ -3792,7 +3833,7 @@ void bnx2x_set_reset_global(struct bnx2x *bp)
*
* Should be run under rtnl lock
*/
-static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
+static void bnx2x_clear_reset_global(struct bnx2x *bp)
{
u32 val;
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
@@ -3806,7 +3847,7 @@ static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
*
* should be run under rtnl lock
*/
-static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
+static bool bnx2x_reset_is_global(struct bnx2x *bp)
{
u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
@@ -3819,7 +3860,7 @@ static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
*
* Should be run under rtnl lock
*/
-static inline void bnx2x_set_reset_done(struct bnx2x *bp)
+static void bnx2x_set_reset_done(struct bnx2x *bp)
{
u32 val;
u32 bit = BP_PATH(bp) ?
@@ -3944,7 +3985,7 @@ bool bnx2x_clear_pf_load(struct bnx2x *bp)
*
* should be run under rtnl lock
*/
-static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
+static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
{
u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
BNX2X_PATH0_LOAD_CNT_MASK);
@@ -3965,7 +4006,7 @@ static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
/*
* Reset the load status for the current engine.
*/
-static inline void bnx2x_clear_load_status(struct bnx2x *bp)
+static void bnx2x_clear_load_status(struct bnx2x *bp)
{
u32 val;
u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
@@ -3976,13 +4017,13 @@ static inline void bnx2x_clear_load_status(struct bnx2x *bp)
bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
}
-static inline void _print_next_block(int idx, const char *blk)
+static void _print_next_block(int idx, const char *blk)
{
pr_cont("%s%s", idx ? ", " : "", blk);
}
-static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
- bool print)
+static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
+ bool print)
{
int i = 0;
u32 cur_bit = 0;
@@ -4029,8 +4070,8 @@ static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
return par_num;
}
-static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
- bool *global, bool print)
+static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
+ bool *global, bool print)
{
int i = 0;
u32 cur_bit = 0;
@@ -4115,8 +4156,8 @@ static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
return par_num;
}
-static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
- bool print)
+static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
+ bool print)
{
int i = 0;
u32 cur_bit = 0;
@@ -4167,8 +4208,8 @@ static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
return par_num;
}
-static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
- bool *global, bool print)
+static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
+ bool *global, bool print)
{
int i = 0;
u32 cur_bit = 0;
@@ -4209,8 +4250,8 @@ static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
return par_num;
}
-static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
- bool print)
+static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
+ bool print)
{
int i = 0;
u32 cur_bit = 0;
@@ -4236,8 +4277,8 @@ static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
return par_num;
}
-static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
- u32 *sig)
+static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
+ u32 *sig)
{
if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
(sig[1] & HW_PRTY_ASSERT_SET_1) ||
@@ -4308,7 +4349,7 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
}
-static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
+static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
{
u32 val;
if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
@@ -4500,7 +4541,7 @@ void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
igu_addr);
}
-static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
+static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
{
/* No memory barriers */
storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
@@ -4531,7 +4572,7 @@ static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
}
#endif
-static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
+static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
{
struct bnx2x_mcast_ramrod_params rparam;
int rc;
@@ -4556,8 +4597,8 @@ static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
netif_addr_unlock_bh(bp->dev);
}
-static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
- union event_ring_elem *elem)
+static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
+ union event_ring_elem *elem)
{
unsigned long ramrod_flags = 0;
int rc = 0;
@@ -4604,7 +4645,7 @@ static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
#endif
-static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
+static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
{
netif_addr_lock_bh(bp->dev);
@@ -4625,7 +4666,7 @@ static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
netif_addr_unlock_bh(bp->dev);
}
-static inline void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
+static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
union event_ring_elem *elem)
{
if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
@@ -4642,7 +4683,7 @@ static inline void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
}
/* called with rtnl_lock */
-static inline void bnx2x_after_function_update(struct bnx2x *bp)
+static void bnx2x_after_function_update(struct bnx2x *bp)
{
int q, rc;
struct bnx2x_fastpath *fp;
@@ -4712,7 +4753,7 @@ static inline void bnx2x_after_function_update(struct bnx2x *bp)
#endif /* BCM_CNIC */
}
-static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
+static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
struct bnx2x *bp, u32 cid)
{
DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
@@ -5056,7 +5097,7 @@ static void bnx2x_timer(unsigned long data)
* nic init service functions
*/
-static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
+static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
{
u32 i;
if (!(len%4) && !(addr%4))
@@ -5069,10 +5110,10 @@ static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
}
/* helper: writes FP SP data to FW - data_size in dwords */
-static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
- int fw_sb_id,
- u32 *sb_data_p,
- u32 data_size)
+static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
+ int fw_sb_id,
+ u32 *sb_data_p,
+ u32 data_size)
{
int index;
for (index = 0; index < data_size; index++)
@@ -5082,7 +5123,7 @@ static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
*(sb_data_p + index));
}
-static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
+static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
{
u32 *sb_data_p;
u32 data_size = 0;
@@ -5115,7 +5156,7 @@ static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
}
/* helper: writes SP SB data to FW */
-static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
+static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
struct hc_sp_status_block_data *sp_sb_data)
{
int func = BP_FUNC(bp);
@@ -5127,7 +5168,7 @@ static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
*((u32 *)sp_sb_data + i));
}
-static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
+static void bnx2x_zero_sp_sb(struct bnx2x *bp)
{
int func = BP_FUNC(bp);
struct hc_sp_status_block_data sp_sb_data;
@@ -5148,8 +5189,7 @@ static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
}
-static inline
-void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
+static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
int igu_sb_id, int igu_seg_id)
{
hc_sm->igu_sb_id = igu_sb_id;
@@ -5160,8 +5200,7 @@ void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
/* allocates state machine ids. */
-static inline
-void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
+static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
{
/* zero out state machine indices */
/* rx indices */
@@ -5569,7 +5608,7 @@ static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
}
-static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
+static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
{
if (CHIP_IS_E1x(fp->bp))
return BP_L_ID(fp->bp) + fp->index;
@@ -5630,6 +5669,43 @@ static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
bnx2x_update_fpsb_idx(fp);
}
+static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
+{
+ int i;
+
+ for (i = 1; i <= NUM_TX_RINGS; i++) {
+ struct eth_tx_next_bd *tx_next_bd =
+ &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
+
+ tx_next_bd->addr_hi =
+ cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
+ tx_next_bd->addr_lo =
+ cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
+ BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
+ }
+
+ SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
+ txdata->tx_db.data.zero_fill1 = 0;
+ txdata->tx_db.data.prod = 0;
+
+ txdata->tx_pkt_prod = 0;
+ txdata->tx_pkt_cons = 0;
+ txdata->tx_bd_prod = 0;
+ txdata->tx_bd_cons = 0;
+ txdata->tx_pkt = 0;
+}
+
+static void bnx2x_init_tx_rings(struct bnx2x *bp)
+{
+ int i;
+ u8 cos;
+
+ for_each_tx_queue(bp, i)
+ for_each_cos_in_tx_queue(&bp->fp[i], cos)
+ bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]);
+}
+
void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
{
int i;
@@ -6154,7 +6230,7 @@ void bnx2x_pf_disable(struct bnx2x *bp)
REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
}
-static inline void bnx2x__common_init_phy(struct bnx2x *bp)
+static void bnx2x__common_init_phy(struct bnx2x *bp)
{
u32 shmem_base[2], shmem2_base[2];
shmem_base[0] = bp->common.shmem_base;
@@ -6882,12 +6958,59 @@ static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
REG_WR_DMAE(bp, reg, wb_write, 2);
}
-static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
+static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
+ u8 idu_sb_id, bool is_Pf)
+{
+ u32 data, ctl, cnt = 100;
+ u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
+ u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
+ u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
+ u32 sb_bit = 1 << (idu_sb_id%32);
+ u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
+ u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
+
+ /* Not supported in BC mode */
+ if (CHIP_INT_MODE_IS_BC(bp))
+ return;
+
+ data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
+ << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
+ IGU_REGULAR_CLEANUP_SET |
+ IGU_REGULAR_BCLEANUP;
+
+ ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
+ func_encode << IGU_CTRL_REG_FID_SHIFT |
+ IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
+
+ DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
+ data, igu_addr_data);
+ REG_WR(bp, igu_addr_data, data);
+ mmiowb();
+ barrier();
+ DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
+ ctl, igu_addr_ctl);
+ REG_WR(bp, igu_addr_ctl, ctl);
+ mmiowb();
+ barrier();
+
+ /* wait for clean up to finish */
+ while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
+ msleep(20);
+
+
+ if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
+ DP(NETIF_MSG_HW,
+ "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
+ idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
+ }
+}
+
+static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
{
bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
}
-static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
+static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
{
u32 i, base = FUNC_ILT_BASE(func);
for (i = base; i < base + ILT_PER_FUNC; i++)
@@ -7238,7 +7361,7 @@ void bnx2x_free_mem(struct bnx2x *bp)
BCM_PAGE_SIZE * NUM_EQ_PAGES);
}
-static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
+static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
{
int num_groups;
int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
@@ -7604,7 +7727,7 @@ void bnx2x_ilt_set_info(struct bnx2x *bp)
* - HC configuration
* - Queue's CDU context
*/
-static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
+static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
{
@@ -7954,7 +8077,7 @@ static void bnx2x_reset_port(struct bnx2x *bp)
/* TODO: Close Doorbell port? */
}
-static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
+static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
{
struct bnx2x_func_state_params func_params = {NULL};
@@ -7969,7 +8092,7 @@ static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
return bnx2x_func_state_change(bp, &func_params);
}
-static inline int bnx2x_func_stop(struct bnx2x *bp)
+static int bnx2x_func_stop(struct bnx2x *bp)
{
struct bnx2x_func_state_params func_params = {NULL};
int rc;
@@ -8084,7 +8207,7 @@ void bnx2x_send_unload_done(struct bnx2x *bp)
bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
}
-static inline int bnx2x_func_wait_started(struct bnx2x *bp)
+static int bnx2x_func_wait_started(struct bnx2x *bp)
{
int tout = 50;
int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
@@ -8394,7 +8517,7 @@ static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
*
* @bp: driver handle
*/
-static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
+static void bnx2x_mcp_wait_one(struct bnx2x *bp)
{
/* special handling for emulation and FPGA,
wait 10 times longer */
@@ -8730,7 +8853,7 @@ exit_leader_reset:
return rc;
}
-static inline void bnx2x_recovery_failed(struct bnx2x *bp)
+static void bnx2x_recovery_failed(struct bnx2x *bp)
{
netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
@@ -10803,8 +10926,8 @@ static int bnx2x_close(struct net_device *dev)
return 0;
}
-static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
- struct bnx2x_mcast_ramrod_params *p)
+static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
+ struct bnx2x_mcast_ramrod_params *p)
{
int mc_count = netdev_mc_count(bp->dev);
struct bnx2x_mcast_list_elem *mc_mac =
@@ -10827,7 +10950,7 @@ static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
return 0;
}
-static inline void bnx2x_free_mcast_macs_list(
+static void bnx2x_free_mcast_macs_list(
struct bnx2x_mcast_ramrod_params *p)
{
struct bnx2x_mcast_list_elem *mc_mac =
@@ -10845,7 +10968,7 @@ static inline void bnx2x_free_mcast_macs_list(
*
* We will use zero (0) as a MAC type for these MACs.
*/
-static inline int bnx2x_set_uc_list(struct bnx2x *bp)
+static int bnx2x_set_uc_list(struct bnx2x *bp)
{
int rc;
struct net_device *dev = bp->dev;
@@ -10876,7 +10999,7 @@ static inline int bnx2x_set_uc_list(struct bnx2x *bp)
BNX2X_UC_LIST_MAC, &ramrod_flags);
}
-static inline int bnx2x_set_mc_list(struct bnx2x *bp)
+static int bnx2x_set_mc_list(struct bnx2x *bp)
{
struct net_device *dev = bp->dev;
struct bnx2x_mcast_ramrod_params rparam = {NULL};
@@ -11062,7 +11185,7 @@ static const struct net_device_ops bnx2x_netdev_ops = {
#endif
};
-static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
+static int bnx2x_set_coherency_mask(struct bnx2x *bp)
{
struct device *dev = &bp->pdev->dev;
@@ -11328,7 +11451,7 @@ static int bnx2x_check_firmware(struct bnx2x *bp)
return 0;
}
-static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
{
const __be32 *source = (const __be32 *)_source;
u32 *target = (u32 *)_target;
@@ -11342,7 +11465,7 @@ static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
Ops array is stored in the following format:
{op(8bit), offset(24bit, big endian), data(32bit, big endian)}
*/
-static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
+static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
{
const __be32 *source = (const __be32 *)_source;
struct raw_op *target = (struct raw_op *)_target;
@@ -11360,7 +11483,7 @@ static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
* IRO array is stored in the following format:
* {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
*/
-static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
+static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
{
const __be32 *source = (const __be32 *)_source;
struct iro *target = (struct iro *)_target;
@@ -11380,7 +11503,7 @@ static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
}
}
-static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
+static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
{
const __be16 *source = (const __be16 *)_source;
u16 *target = (u16 *)_target;
@@ -11523,7 +11646,7 @@ void bnx2x__init_func_obj(struct bnx2x *bp)
}
/* must be called after sriov-enable */
-static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
+static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
{
int cid_count = BNX2X_L2_CID_COUNT(bp);
@@ -11539,7 +11662,7 @@ static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
* @dev: pci device
*
*/
-static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
+static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
{
int pos;
u16 control;
@@ -12015,7 +12138,7 @@ module_exit(bnx2x_cleanup);
* This function will wait until the ramdord completion returns.
* Return 0 if success, -ENODEV if ramrod doesn't return.
*/
-static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
+static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
{
unsigned long ramrod_flags = 0;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
index 7366e92..1e2785c 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
@@ -1316,7 +1316,7 @@ static void bnx2x_port_stats_base_init(struct bnx2x *bp)
*
* @param bp
*/
-static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
+static void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
{
int i;
int first_queue_query_index;
^ permalink raw reply related
* Re: [PATCH 1/4 net-next] net: allow skb->head to be a page fragment
From: Eric Dumazet @ 2012-04-28 7:16 UTC (permalink / raw)
To: Alexander Duyck
Cc: David Miller, netdev, Ilpo Järvinen, Neal Cardwell,
Tom Herbert, Maciej Żenczykowski, Jeff Kirsher,
Ben Hutchings, Matt Carlson, Michael Chan, Herbert Xu
In-Reply-To: <4F9B3980.1080605@intel.com>
On Fri, 2012-04-27 at 17:27 -0700, Alexander Duyck wrote:
> On 04/27/2012 03:33 AM, Eric Dumazet wrote:
> > From: Eric Dumazet <edumazet@google.com>
> >
> > +struct sk_buff *build_skb(void *data, unsigned int frag_size)
> > {
> > struct skb_shared_info *shinfo;
> > struct sk_buff *skb;
> > - unsigned int size;
> > + unsigned int size = frag_size ? : ksize(data);
> >
> > skb = kmem_cache_alloc(skbuff_head_cache, GFP_ATOMIC);
> > if (!skb)
> > return NULL;
> >
> > - size = ksize(data) - SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
> > + size -= SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
> >
> > memset(skb, 0, offsetof(struct sk_buff, tail));
> > skb->truesize = SKB_TRUESIZE(size);
> > + skb->head_frag = frag_size != 0;
> > atomic_set(&skb->users, 1);
> > skb->head = data;
> > skb->data = data;
>
> This doesn't seem right to me. You are only counting the piece of the
> page that got filled with data and the piece that will get overwritten
> with the shared info. What about the rest of the page? It looks like
> in the tg3 patch you have the driver using a half page. Based on this
> function I suspect the resultant truesize would be something like 64 +
> 256 + 320 for an ack. Shouldn't your truesize in that case be 2048 + 256?
Re-reading your mail, I think you missed fact that tg3 driver currently
uses a kmalloc(64+1500+14+SKB_DATA_ALIGN(sizeof(struct
skb_shared_info)) , so basically does a kmalloc(2048). But this is done
before NIC fills the frame in it, so we cant know what will be the frame
length...
So build_skb() does later a ksize(data) and this gives 2048, even for a
small ACK packet ...
So the spirit of this patch is not to change any truesize.
tg3 for example splits a PAGE_SIZE into 2048 bytes frags (2 frags on x86
for example). Its done about the same in Intel IGB driver (IGB assumes
PAGE_SIZE is 4096 since it uses PAGE_SIZE/2)
The only thing that is changed here is where skb->head is allocated
from : kmalloc() caches or a frag from a page (and one reference to
page->_count)
Hope this clears your concern ?
^ permalink raw reply
* Re: [PATCH 1/4 net-next] net: allow skb->head to be a page fragment
From: Eric Dumazet @ 2012-04-28 6:30 UTC (permalink / raw)
To: Alexander Duyck
Cc: David Miller, netdev, Ilpo Järvinen, Neal Cardwell,
Tom Herbert, Maciej Żenczykowski, Jeff Kirsher,
Ben Hutchings, Matt Carlson, Michael Chan, Herbert Xu
In-Reply-To: <4F9B3980.1080605@intel.com>
On Fri, 2012-04-27 at 17:27 -0700, Alexander Duyck wrote:
> This doesn't seem right to me. You are only counting the piece of the
> page that got filled with data and the piece that will get overwritten
> with the shared info. What about the rest of the page? It looks like
> in the tg3 patch you have the driver using a half page. Based on this
> function I suspect the resultant truesize would be something like 64 +
> 256 + 320 for an ack. Shouldn't your truesize in that case be 2048 + 256?
Hi Alex
Not sure what you mean, since there is no such change in this patch.
driver must pass the truesize of the fragment, not the used one to
build_skb(). This is what I did in tg3 patch.
Therefore, all packets will have truesize = 2048 + 256.
The tg3 patch could be generalized to take care of special MTU, and be
able to use 1024 or 4096 as well for the frag size.
Lets discuss of the existing truesize problem.
There is one problem with fragments : We track the used length of them,
not their truesize.
So for example, GRO is not able to track resulting truesize.
We could split the "__u32 size;" to :
__u32 size:24;
__u32 truesizelog:8;
this_frag_truesize = max(1U << frag->truesizelog, frag->size);
^ permalink raw reply
* Re: [PATCH v2 0/2] drop_monitor: misc fixes for some recently reported bugs
From: David Miller @ 2012-04-28 6:19 UTC (permalink / raw)
To: nhorman; +Cc: netdev, eric.dumazet
In-Reply-To: <1335557509-32726-1-git-send-email-nhorman@tuxdriver.com>
From: Neil Horman <nhorman@tuxdriver.com>
Date: Fri, 27 Apr 2012 16:11:47 -0400
> Eric was using dropwatch recently and reported a few bugs to me that he
> had noted. This short series should fix them all up.
>
> Change Notes:
> V2)
> renamed trace_state_lock to trace_state_mutex
> cleaned up rcu write side access to use rcu_dereference_protected
> handled some NULL allocation failure cases
Both applied, but in the second patch I had to fix the spelling
of the "initialized" variable :-)
Thanks Neil.
^ permalink raw reply
* Re: [PATCH v2 2/2] drop_monitor: Make updating data->skb smp safe
From: Eric Dumazet @ 2012-04-28 6:13 UTC (permalink / raw)
To: Neil Horman; +Cc: netdev, David Miller
In-Reply-To: <1335557509-32726-3-git-send-email-nhorman@tuxdriver.com>
On Fri, 2012-04-27 at 16:11 -0400, Neil Horman wrote:
> Eric Dumazet pointed out to me that the drop_monitor protocol has some holes in
> its smp protections. Specifically, its possible to replace data->skb while its
> being written. This patch corrects that by making data->skb and rcu protected
> variable. That will prevent it from being overwritten while a tracepoint is
> modifying it.
>
> Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
> Reported-by: Eric Dumazet <eric.dumazet@gmail.com>
> CC: David Miller <davem@davemloft.net>
> ---
> net/core/drop_monitor.c | 70 ++++++++++++++++++++++++++++++++++++-----------
> 1 files changed, 54 insertions(+), 16 deletions(-)
Acked-by: Eric Dumazet <edumazet@google.com>
Thanks Neil
^ permalink raw reply
* Re: [PATCH v2 1/2] drop_monitor: fix sleeping in invalid context warning
From: Eric Dumazet @ 2012-04-28 6:11 UTC (permalink / raw)
To: Neil Horman; +Cc: netdev, David Miller
In-Reply-To: <1335557509-32726-2-git-send-email-nhorman@tuxdriver.com>
On Fri, 2012-04-27 at 16:11 -0400, Neil Horman wrote:
> Eric Dumazet pointed out this warning in the drop_monitor protocol to me:
>
> It stems from holding a spinlock (trace_state_lock) while attempting to register
> or unregister tracepoint hooks, making in_atomic() true in this context, leading
> to the warning when the tracepoint calls might_sleep() while its taking a mutex.
> Since we only use the trace_state_lock to prevent trace protocol state races, as
> well as hardware stat list updates on an rcu write side, we can just convert the
> spinlock to a mutex to avoid this problem.
>
> Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
> Reported-by: Eric Dumazet <eric.dumazet@gmail.com>
> CC: David Miller <davem@davemloft.net>
> ---
Acked-by: Eric Dumazet <edumazet@google.com>
Thanks Neil
^ permalink raw reply
* [PATCH net-next] pch_gbe: reprogram multicast address register on reset
From: roy.qing.li @ 2012-04-28 5:53 UTC (permalink / raw)
To: netdev; +Cc: richardcochran, tshimizu818
From: RongQing.Li <roy.qing.li@gmail.com>
The reset logic after a Rx FIFO overrun will clear the programmed
multicast addresses. This patch fixes the issue by reprogramming the
registers after the reset.
The commit eefc48b tried to fix this problem, but it introduces
unnecessary codes. In fact, all multicast addresses have been saved
in netdev->mc, So we can call pch_gbe_set_multi() directly after
reset_hw and reset_rx.
This commit kills 50+ line codes
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Takahiro Shimizu <tshimizu818@gmail.com>
Signed-off-by: RongQing.Li <roy.qing.li@gmail.com>
---
.../net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 60 ++------------------
1 files changed, 5 insertions(+), 55 deletions(-)
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 107f41a..c9c182b 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -120,6 +120,7 @@ static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
int data);
+static void pch_gbe_set_multi(struct net_device *netdev);
#ifdef CONFIG_PCH_PTP
static struct sock_filter ptp_filter[] = {
@@ -391,58 +392,13 @@ static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
}
/**
- * pch_gbe_mac_save_mac_addr_regs - Save MAC addresse registers
- * @hw: Pointer to the HW structure
- * @addr: Pointer to the MAC address
- * @index: MAC address array register
- */
-static void
-pch_gbe_mac_save_mac_addr_regs(struct pch_gbe_hw *hw,
- struct pch_gbe_regs_mac_adr *mac_adr, u32 index)
-{
- mac_adr->high = ioread32(&hw->reg->mac_adr[index].high);
- mac_adr->low = ioread32(&hw->reg->mac_adr[index].low);
-}
-
-/**
- * pch_gbe_mac_store_mac_addr_regs - Store MAC addresse registers
- * @hw: Pointer to the HW structure
- * @addr: Pointer to the MAC address
- * @index: MAC address array register
- */
-static void
-pch_gbe_mac_store_mac_addr_regs(struct pch_gbe_hw *hw,
- struct pch_gbe_regs_mac_adr *mac_adr, u32 index)
-{
- u32 adrmask;
-
- adrmask = ioread32(&hw->reg->ADDR_MASK);
- iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
- /* wait busy */
- pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
- /* Set the MAC address to the MAC address xA/xB register */
- iowrite32(mac_adr->high, &hw->reg->mac_adr[index].high);
- iowrite32(mac_adr->low, &hw->reg->mac_adr[index].low);
- iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
- /* wait busy */
- pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
-}
-
-#define MAC_ADDR_LIST_NUM 16
-/**
* pch_gbe_mac_reset_hw - Reset hardware
* @hw: Pointer to the HW structure
*/
static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
{
- struct pch_gbe_regs_mac_adr mac_addr_list[MAC_ADDR_LIST_NUM];
- int i;
-
/* Read the MAC address. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
- /* Read other MAC addresses */
- for (i = 1; i < MAC_ADDR_LIST_NUM; i++)
- pch_gbe_mac_save_mac_addr_regs(hw, &mac_addr_list[i], i);
iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
#ifdef PCH_GBE_MAC_IFOP_RGMII
iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
@@ -450,26 +406,17 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
/* Setup the receive addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
- for (i = 1; i < MAC_ADDR_LIST_NUM; i++)
- pch_gbe_mac_store_mac_addr_regs(hw, &mac_addr_list[i], i);
return;
}
static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw)
{
- struct pch_gbe_regs_mac_adr mac_addr_list[MAC_ADDR_LIST_NUM];
- int i;
-
/* Read the MAC addresses. and store to the private data */
pch_gbe_mac_read_mac_addr(hw);
- for (i = 1; i < MAC_ADDR_LIST_NUM; i++)
- pch_gbe_mac_save_mac_addr_regs(hw, &mac_addr_list[i], i);
iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET);
pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST);
/* Setup the MAC addresses */
pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
- for (i = 1; i < MAC_ADDR_LIST_NUM; i++)
- pch_gbe_mac_store_mac_addr_regs(hw, &mac_addr_list[i], i);
return;
}
@@ -836,6 +783,8 @@ void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
void pch_gbe_reset(struct pch_gbe_adapter *adapter)
{
pch_gbe_mac_reset_hw(&adapter->hw);
+ /* reprogram multicast address register after reset */
+ pch_gbe_set_multi(adapter->netdev);
/* Setup the receive address. */
pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
if (pch_gbe_hal_init_hw(&adapter->hw))
@@ -1398,6 +1347,8 @@ static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter)
/* Stop Receive */
pch_gbe_mac_reset_rx(hw);
}
+ /* reprogram multicast address register after reset */
+ pch_gbe_set_multi(adapter->netdev);
}
static void pch_gbe_start_receive(struct pch_gbe_hw *hw)
@@ -1980,7 +1931,6 @@ static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
}
-static void pch_gbe_set_multi(struct net_device *netdev);
/**
* pch_gbe_up - Up GbE network device
* @adapter: Board private structure
--
1.7.1
^ permalink raw reply related
* Re: [PATCH] sky2: fix receive length error in mixed non-VLAN/VLAN traffic
From: Stephen Hemminger @ 2012-04-28 3:05 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: Niccolò Belli, netdev
In-Reply-To: <20120427200310.60325fb1@nehalam.linuxnetplumber.net>
On Fri, 27 Apr 2012 20:03:10 -0700
Stephen Hemminger <shemminger@vyatta.com> wrote:
> Bug: The VLAN bit of the MAC RX Status Word is unreliable in several older
> supported chips. Sometimes the VLAN bit is not set for valid VLAN packets
> and also sometimes the VLAN bit is set for non-VLAN packets that came after
> a VLAN packet. This results in a receive length error when VLAN hardware
> tagging is enabled.
>
> Fix: The driver uses only VLAN information included in VLAN status list elements,
> that signals that the VLAN tag field is valid. It must ignore the VLAN bit in the
> MAC RX Status Word. An additional variable set when evaluating the VLAN opcodes
> is used to indicate that the received packet is a VLAN packet and a packet length
> correction (subtraction of VLAN header length) must be done.
>
> This is an alternative to Mirko's patch that relies on the new method of
> encoding VLAN tag, and therefore means extra code can be removed.
>
> Testing: Tested with regular and VLAN traffic on 88E8056, but this chip
> does not have the bug, just proves that the alternative method of handling
> VLAN tag will work.
>
> Reported-by: Mirko Lindner <mlindner@marvell.com>
> Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
>
This doesn't work. Furthur testing just crapped out with lots
of rx length errors in mixed vlan/non-vlan traffic case.
^ permalink raw reply
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