* [PATCH iproute2/net-next 2/2] tc: flower: Support matching ARP
From: Simon Horman @ 2017-01-12 8:11 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: Dinan Gunawardena, netdev, Simon Horman
In-Reply-To: <1484208719-1581-1-git-send-email-simon.horman@netronome.com>
Support matching on ARP operation, and hardware and protocol addresses
for Ethernet hardware and IPv4 protocol addresses.
Example usage:
tc qdisc add dev eth0 ingress
tc filter add dev eth0 protocol arp parent ffff: flower indev eth0 \ arp_op request arp_sip 10.0.0.1 action drop
tc filter add dev eth0 protocol rarp parent ffff: flower indev eth0 \ arp_op reply arp_tha 52:54:3f:00:00:00/24 action drop
Signed-off-by: Simon Horman <simon.horman@netronome.com>
---
man/man8/tc-flower.8 | 41 +++++++++-
tc/f_flower.c | 208 +++++++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 232 insertions(+), 17 deletions(-)
diff --git a/man/man8/tc-flower.8 b/man/man8/tc-flower.8
index 5904a9ecafdf..2dd2c5e6e4a5 100644
--- a/man/man8/tc-flower.8
+++ b/man/man8/tc-flower.8
@@ -34,7 +34,13 @@ flower \- flow based traffic control filter
.BR dst_ip " | " src_ip " } "
.IR PREFIX " | { "
.BR dst_port " | " src_port " } "
-.IR port_number " } | "
+.IR port_number " } | { "
+.BR arp_tip " | " arp_sip " } "
+.IR PREFIX " | "
+.BR arp_op " { " request " | " reply " | "
+.IR OP " } | { "
+.BR arp_tha " | " arp_sha " } "
+.IR MASKED_LLADDR " | "
.B enc_key_id
.IR KEY-ID " | {"
.BR enc_dst_ip " | " enc_src_ip " } { "
@@ -131,6 +137,36 @@ Match on ICMP type or code. Only available for
.BR ip_proto " values " icmp " and " icmpv6
which have to be specified in beforehand.
.TP
+.BI arp_tip " PREFIX"
+.TQ
+.BI arp_sip " PREFIX"
+Match on ARP or RARP sender or target IP address.
+.I PREFIX
+must be a valid IPv4 address optionally followed by a slash and the prefix
+length. If the prefix is missing, \fBtc\fR assumes a full-length host
+match.
+.TP
+.BI arp_op " ARP_OP"
+Match on ARP or RARP operation.
+.I ARP_OP
+may be
+.BR request ", " reply
+or an integer value 0, 1 or 2. A mask may be optionally provided to limit
+the bits of the operation which are matched. A mask is provided by
+following the address with a slash and then the mask. It may be provided as
+an unsigned 8 bit value representing a bitwise mask. If the mask is missing
+then a match on all bits is assumed.
+.TP
+.BI arp_sha " MASKED_LLADDR"
+.TQ
+.BI arp_tha " MASKED_LLADDR"
+Match on ARP or RARP sender or target MAC address. A mask may be optionally
+provided to limit the bits of the address which are matched. A mask is
+provided by following the address with a slash and then the mask. It may be
+provided in LLADDR format, in which case it is a bitwise mask, or as a
+number of high bits to match. If the mask is missing then a match on all
+bits is assumed.
+.TP
.BI enc_key_id " NUMBER"
.TQ
.BI enc_dst_ip " PREFIX"
@@ -152,7 +188,8 @@ As stated above where applicable, matches of a certain layer implicitly depend
on the matches of the next lower layer. Precisely, layer one and two matches
(\fBindev\fR, \fBdst_mac\fR and \fBsrc_mac\fR)
have no dependency, layer three matches
-(\fBip_proto\fR, \fBdst_ip\fR and \fBsrc_ip\fR)
+(\fBip_proto\fR, \fBdst_ip\fR, \fBsrc_ip\fR, \fBarp_tip\fR, \fBarp_sip\fR,
+\fBarp_op\fR, \fBarp_tha\fR and \fBarp_sha\fR)
depend on the
.B protocol
option of tc filter, layer four port matches
diff --git a/tc/f_flower.c b/tc/f_flower.c
index 99f5f8163ee0..d301db36a549 100644
--- a/tc/f_flower.c
+++ b/tc/f_flower.c
@@ -15,6 +15,7 @@
#include <syslog.h>
#include <string.h>
#include <net/if.h>
+#include <linux/if_arp.h>
#include <linux/if_ether.h>
#include <linux/ip.h>
#include <linux/tc_act/tc_vlan.h>
@@ -54,6 +55,11 @@ static void explain(void)
" src_port PORT-NUMBER |\n"
" type ICMP-TYPE |\n"
" code ICMP-CODE |\n"
+ " arp_tip PREFIX |\n"
+ " arp_sip PREFIX |\n"
+ " arp_op [ request | reply | OP ] |\n"
+ " arp_tha MASKED-LLADDR |\n"
+ " arp_sha MASKED-LLADDR |\n"
" enc_dst_ip [ IPV4-ADDR | IPV6-ADDR ] |\n"
" enc_src_ip [ IPV4-ADDR | IPV6-ADDR ] |\n"
" enc_key_id [ KEY-ID ] |\n"
@@ -192,27 +198,16 @@ err:
return -1;
}
-static int flower_parse_ip_addr(char *str, __be16 eth_type,
- int addr4_type, int mask4_type,
- int addr6_type, int mask6_type,
- struct nlmsghdr *n)
+static int __flower_parse_ip_addr(char *str, int family,
+ int addr4_type, int mask4_type,
+ int addr6_type, int mask6_type,
+ struct nlmsghdr *n)
{
int ret;
inet_prefix addr;
- int family;
int bits;
int i;
- if (eth_type == htons(ETH_P_IP)) {
- family = AF_INET;
- } else if (eth_type == htons(ETH_P_IPV6)) {
- family = AF_INET6;
- } else if (!eth_type) {
- family = AF_UNSPEC;
- } else {
- return -1;
- }
-
ret = get_prefix(&addr, str, family);
if (ret)
return -1;
@@ -245,6 +240,89 @@ static int flower_parse_ip_addr(char *str, __be16 eth_type,
return 0;
}
+static int flower_parse_ip_addr(char *str, __be16 eth_type,
+ int addr4_type, int mask4_type,
+ int addr6_type, int mask6_type,
+ struct nlmsghdr *n)
+{
+ int family;
+
+ if (eth_type == htons(ETH_P_IP)) {
+ family = AF_INET;
+ } else if (eth_type == htons(ETH_P_IPV6)) {
+ family = AF_INET6;
+ } else if (!eth_type) {
+ family = AF_UNSPEC;
+ } else {
+ return -1;
+ }
+
+ return __flower_parse_ip_addr(str, family, addr4_type, addr6_type,
+ mask4_type, mask6_type, n);
+}
+
+static bool flower_eth_type_arp(__be16 eth_type)
+{
+ return eth_type == htons(ETH_P_ARP) || eth_type == htons(ETH_P_RARP);
+}
+
+static int flower_parse_arp_ip_addr(char *str, __be16 eth_type,
+ int addr_type, int mask_type,
+ struct nlmsghdr *n)
+{
+ if (!flower_eth_type_arp(eth_type))
+ return -1;
+
+ return __flower_parse_ip_addr(str, AF_INET, addr_type, mask_type,
+ TCA_FLOWER_UNSPEC, TCA_FLOWER_UNSPEC, n);
+}
+
+static int flower_parse_arp_op(char *str, __be16 eth_type,
+ int op_type, int mask_type,
+ struct nlmsghdr *n)
+{
+ char *slash;
+ int ret, err = -1;
+ uint8_t value, mask;
+
+ slash = strchr(str, '/');
+ if (slash)
+ *slash = '\0';
+
+ if (!flower_eth_type_arp(eth_type))
+ goto err;
+
+ if (!strcmp(str, "request")) {
+ value = ARPOP_REQUEST;
+ } else if (!strcmp(str, "reply")) {
+ value = ARPOP_REPLY;
+ } else {
+ ret = get_u8(&value, str, 10);
+ if (ret)
+ goto err;
+ if (value && value != ARPOP_REQUEST && value != ARPOP_REPLY)
+ goto err;
+ }
+
+ if (slash) {
+ ret = get_u8(&mask, slash + 1, 10);
+ if (ret)
+ goto err;
+ }
+ else {
+ mask = UINT8_MAX;
+ }
+
+ addattr8(n, MAX_MSG, op_type, value);
+ addattr8(n, MAX_MSG, mask_type, mask);
+
+ err = 0;
+err:
+ if (slash)
+ *slash = '/';
+ return err;
+}
+
static int flower_icmp_attr_type(__be16 eth_type, __u8 ip_proto,
enum flower_icmp_field field)
{
@@ -530,6 +608,59 @@ static int flower_parse_opt(struct filter_util *qu, char *handle,
fprintf(stderr, "Illegal \"icmp code\"\n");
return -1;
}
+ } else if (matches(*argv, "arp_tip") == 0) {
+ NEXT_ARG();
+ ret = flower_parse_arp_ip_addr(*argv, vlan_ethtype ?
+ vlan_ethtype : eth_type,
+ TCA_FLOWER_KEY_ARP_TIP,
+ TCA_FLOWER_KEY_ARP_TIP_MASK,
+ n);
+ if (ret < 0) {
+ fprintf(stderr, "Illegal \"arp_tip\"\n");
+ return -1;
+ }
+ } else if (matches(*argv, "arp_sip") == 0) {
+ NEXT_ARG();
+ ret = flower_parse_arp_ip_addr(*argv, vlan_ethtype ?
+ vlan_ethtype : eth_type,
+ TCA_FLOWER_KEY_ARP_SIP,
+ TCA_FLOWER_KEY_ARP_SIP_MASK,
+ n);
+ if (ret < 0) {
+ fprintf(stderr, "Illegal \"arp_sip\"\n");
+ return -1;
+ }
+ } else if (matches(*argv, "arp_op") == 0) {
+ NEXT_ARG();
+ ret = flower_parse_arp_op(*argv, vlan_ethtype ?
+ vlan_ethtype : eth_type,
+ TCA_FLOWER_KEY_ARP_OP,
+ TCA_FLOWER_KEY_ARP_OP_MASK,
+ n);
+ if (ret < 0) {
+ fprintf(stderr, "Illegal \"arp_op\"\n");
+ return -1;
+ }
+ } else if (matches(*argv, "arp_tha") == 0) {
+ NEXT_ARG();
+ ret = flower_parse_eth_addr(*argv,
+ TCA_FLOWER_KEY_ARP_THA,
+ TCA_FLOWER_KEY_ARP_THA_MASK,
+ n);
+ if (ret < 0) {
+ fprintf(stderr, "Illegal \"arp_tha\"\n");
+ return -1;
+ }
+ } else if (matches(*argv, "arp_sha") == 0) {
+ NEXT_ARG();
+ ret = flower_parse_eth_addr(*argv,
+ TCA_FLOWER_KEY_ARP_SHA,
+ TCA_FLOWER_KEY_ARP_SHA_MASK,
+ n);
+ if (ret < 0) {
+ fprintf(stderr, "Illegal \"arp_sha\"\n");
+ return -1;
+ }
} else if (matches(*argv, "enc_dst_ip") == 0) {
NEXT_ARG();
ret = flower_parse_ip_addr(*argv, 0,
@@ -662,6 +793,10 @@ static void flower_print_eth_type(FILE *f, __be16 *p_eth_type,
fprintf(f, "ipv4");
else if (eth_type == htons(ETH_P_IPV6))
fprintf(f, "ipv6");
+ else if (eth_type == htons(ETH_P_ARP))
+ fprintf(f, "arp");
+ else if (eth_type == htons(ETH_P_RARP))
+ fprintf(f, "rarp");
else
fprintf(f, "%04x", ntohs(eth_type));
*p_eth_type = eth_type;
@@ -739,6 +874,13 @@ static void flower_print_ip_addr(FILE *f, char *name, __be16 eth_type,
else if (bits < len * 8)
fprintf(f, "/%d", bits);
}
+static void flower_print_ip4_addr(FILE *f, char *name,
+ struct rtattr *addr_attr,
+ struct rtattr *mask_attr)
+{
+ return flower_print_ip_addr(f, name, htons(ETH_P_IP),
+ addr_attr, mask_attr, 0, 0);
+}
static void flower_print_port(FILE *f, char *name, struct rtattr *attr)
{
@@ -759,6 +901,31 @@ static void flower_print_icmp(FILE *f, char *name, struct rtattr *attr)
fprintf(f, "\n %s %d", name, rta_getattr_u8(attr));
}
+static void flower_print_arp_op(FILE *f, char *name,
+ struct rtattr *op_attr,
+ struct rtattr *mask_attr)
+{
+ uint8_t op, mask;
+
+ if (!op_attr)
+ return;
+
+ op = rta_getattr_u8(op_attr);
+ mask = mask_attr ? rta_getattr_u8(mask_attr) : UINT8_MAX;
+
+ fprintf(f, "\n %s ", name);
+
+ if (mask == UINT8_MAX && op == ARPOP_REQUEST)
+ fprintf(f, "request");
+ else if (mask == UINT8_MAX && op == ARPOP_REPLY)
+ fprintf(f, "reply");
+ else
+ fprintf(f, "%d", op);
+
+ if (mask != UINT8_MAX)
+ fprintf(f, "/%d", mask);
+}
+
static int flower_print_opt(struct filter_util *qu, FILE *f,
struct rtattr *opt, __u32 handle)
{
@@ -834,6 +1001,17 @@ static int flower_print_opt(struct filter_util *qu, FILE *f,
if (nl_type >= 0)
flower_print_icmp(f, "icmp_code", tb[nl_type]);
+ flower_print_ip4_addr(f, "arp_sip", tb[TCA_FLOWER_KEY_ARP_SIP],
+ tb[TCA_FLOWER_KEY_ARP_SIP_MASK]);
+ flower_print_ip4_addr(f, "arp_tip", tb[TCA_FLOWER_KEY_ARP_TIP],
+ tb[TCA_FLOWER_KEY_ARP_TIP_MASK]);
+ flower_print_arp_op(f, "arp_op", tb[TCA_FLOWER_KEY_ARP_OP],
+ tb[TCA_FLOWER_KEY_ARP_OP_MASK]);
+ flower_print_eth_addr(f, "arp_sha", tb[TCA_FLOWER_KEY_ARP_SHA],
+ tb[TCA_FLOWER_KEY_ARP_SHA_MASK]);
+ flower_print_eth_addr(f, "arp_tha", tb[TCA_FLOWER_KEY_ARP_THA],
+ tb[TCA_FLOWER_KEY_ARP_THA_MASK]);
+
flower_print_ip_addr(f, "enc_dst_ip",
tb[TCA_FLOWER_KEY_ENC_IPV4_DST_MASK] ?
htons(ETH_P_IP) : htons(ETH_P_IPV6),
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* Re: [PATCH] can: Fix kernel panic at security_sock_rcv_skb
From: Oliver Hartkopp @ 2017-01-12 8:22 UTC (permalink / raw)
To: Liu ShuoX, linux-kernel
Cc: yanmin_zhang, shuox.liu, Zhang Yanmin, He, Bo, Marc Kleine-Budde,
David S. Miller, open list:CAN NETWORK LAYER,
open list:NETWORKING [GENERAL]
In-Reply-To: <1484202799-7287-1-git-send-email-shuo.a.liu@intel.com>
On 01/12/2017 07:33 AM, Liu ShuoX wrote:
> From: Zhang Yanmin <yanmin.zhang@intel.com>
>
> The patch is for fix the below kernel panic:
> BUG: unable to handle kernel NULL pointer dereference at (null)
> IP: [<ffffffff81495e25>] selinux_socket_sock_rcv_skb+0x65/0x2a0
>
> Call Trace:
> <IRQ>
> [<ffffffff81485d8c>] security_sock_rcv_skb+0x4c/0x60
> [<ffffffff81d55771>] sk_filter+0x41/0x210
> [<ffffffff81d12913>] sock_queue_rcv_skb+0x53/0x3a0
> [<ffffffff81f0a2b3>] raw_rcv+0x2a3/0x3c0
> [<ffffffff81f06eab>] can_rcv_filter+0x12b/0x370
> [<ffffffff81f07af9>] can_receive+0xd9/0x120
> [<ffffffff81f07beb>] can_rcv+0xab/0x100
> [<ffffffff81d362ac>] __netif_receive_skb_core+0xd8c/0x11f0
> [<ffffffff81d36734>] __netif_receive_skb+0x24/0xb0
> [<ffffffff81d37f67>] process_backlog+0x127/0x280
> [<ffffffff81d36f7b>] net_rx_action+0x33b/0x4f0
> [<ffffffff810c88d4>] __do_softirq+0x184/0x440
> [<ffffffff81f9e86c>] do_softirq_own_stack+0x1c/0x30
> <EOI>
> [<ffffffff810c76fb>] do_softirq.part.18+0x3b/0x40
> [<ffffffff810c8bed>] do_softirq+0x1d/0x20
> [<ffffffff81d30085>] netif_rx_ni+0xe5/0x110
> [<ffffffff8199cc87>] slcan_receive_buf+0x507/0x520
> [<ffffffff8167ef7c>] flush_to_ldisc+0x21c/0x230
> [<ffffffff810e3baf>] process_one_work+0x24f/0x670
> [<ffffffff810e44ed>] worker_thread+0x9d/0x6f0
> [<ffffffff810e4450>] ? rescuer_thread+0x480/0x480
> [<ffffffff810ebafc>] kthread+0x12c/0x150
> [<ffffffff81f9ccef>] ret_from_fork+0x3f/0x70
>
> The sk dereferenced in panic has been released. After the rcu_call in
> can_rx_unregister, receiver was protected by RCU but inner data was
> not, then later sk will be freed while other CPU is still using it.
> We need wait here to make sure sk referenced via receiver was safe.
>
> => security_sk_free
> => sk_destruct
> => __sk_free
> => sk_free
> => raw_release
> => sock_release
> => sock_close
> => __fput
> => ____fput
> => task_work_run
> => exit_to_usermode_loop
> => syscall_return_slowpath
> => int_ret_from_sys_call
>
> Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com>
> Signed-off-by: He, Bo <bo.he@intel.com>
> Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
> ---
> net/can/af_can.c | 14 ++++++++------
> net/can/af_can.h | 1 -
> 2 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/net/can/af_can.c b/net/can/af_can.c
> index 1108079..fcbe971 100644
> --- a/net/can/af_can.c
> +++ b/net/can/af_can.c
> @@ -517,10 +517,8 @@ int can_rx_register(struct net_device *dev, canid_t can_id, canid_t mask,
> /*
> * can_rx_delete_receiver - rcu callback for single receiver entry removal
> */
> -static void can_rx_delete_receiver(struct rcu_head *rp)
> +static void can_rx_delete_receiver(struct receiver *r)
> {
> - struct receiver *r = container_of(rp, struct receiver, rcu);
> -
> kmem_cache_free(rcv_cache, r);
> }
>
> @@ -595,9 +593,13 @@ void can_rx_unregister(struct net_device *dev, canid_t can_id, canid_t mask,
> out:
> spin_unlock(&can_rcvlists_lock);
>
> - /* schedule the receiver item for deletion */
> - if (r)
> - call_rcu(&r->rcu, can_rx_delete_receiver);
> + /* synchronize_rcu to wait until a grace period has elapsed, to make
> + * sure all receiver's sk dereferenced by others.
> + */
> + if (r) {
> + synchronize_rcu();
> + can_rx_delete_receiver(r);
Nitpick: When can_rx_delete_receiver() just contains
kmem_cache_free(rcv_cache, r), then the function definition should be
removed.
But my main concern is:
The reason why can_rx_delete_receiver() was introduced was the need to
remove a huge number of receivers with can_rx_unregister().
When you call synchronize_rcu() after each receiver removal this would
potentially lead to a big performance issue when e.g. closing CAN_RAW
sockets with a high number of receivers.
So the idea was to remove/unlink the receiver hlist_del_rcu(&r->list)
and also kmem_cache_free(rcv_cache, r) by some rcu mechanism - so that
all elements are cleaned up by rcu at a later point.
Is it possible that the problems emerge due to hlist_del_rcu(&r->list)
and you accidently fix it with your introduced synchronize_rcu()?
Regards,
Oliver
> + }
> }
> EXPORT_SYMBOL(can_rx_unregister);
>
> diff --git a/net/can/af_can.h b/net/can/af_can.h
> index fca0fe9..a0cbf83 100644
> --- a/net/can/af_can.h
> +++ b/net/can/af_can.h
> @@ -50,7 +50,6 @@
>
> struct receiver {
> struct hlist_node list;
> - struct rcu_head rcu;
> canid_t can_id;
> canid_t mask;
> unsigned long matches;
>
^ permalink raw reply
* Re: [PATCH net-next 2/2] bpf: allow b/h/w/dw access for bpf's cb in ctx
From: Quentin Monnet @ 2017-01-12 8:25 UTC (permalink / raw)
To: Daniel Borkmann, davem; +Cc: alexei.starovoitov, netdev
In-Reply-To: <fff467f83e48c6c15053a7637893bf247c9be102.1484182858.git.daniel@iogearbox.net>
Hi Daniel,
2017-01-12 (02:21 +0100) ~ Daniel Borkmann <daniel@iogearbox.net>
> When structs are used to store temporary state in cb[] buffer that is
> used with programs and among tail calls, then the generated code will
> not always access the buffer in bpf_w chunks. We can ease programming
> of it and let this act more natural by allowing for aligned b/h/w/dw
> sized access for cb[] ctx member. Various test cases are attached as
> well for the selftest suite. Potentially, this can also be reused for
> other program types to pass data around.
>
> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
> Acked-by: Alexei Starovoitov <ast@kernel.org>
> ---
> kernel/bpf/verifier.c | 8 +-
> net/core/filter.c | 41 ++-
> tools/testing/selftests/bpf/test_verifier.c | 442 +++++++++++++++++++++++++++-
> 3 files changed, 478 insertions(+), 13 deletions(-)
>
[...]
> diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c
> index 9bb4534..f664bed 100644
> --- a/tools/testing/selftests/bpf/test_verifier.c
> +++ b/tools/testing/selftests/bpf/test_verifier.c
> @@ -859,15 +859,451 @@ struct test_val {
[...]
> + {
> + "check cb access: doulbe, oob 5",
> + .insns = {
> + BPF_MOV64_IMM(BPF_REG_0, 0),
> + BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
> + offsetof(struct __sk_buff, cb[4]) + 8),
> + BPF_EXIT_INSN(),
> + },
> + .errstr = "invalid bpf_context access",
> + .result = REJECT,
> + },
Nitpicking: typo ("doulbe").
Regards,
Quentin
^ permalink raw reply
* Re: [PATCH] [net] net/mlx5e: fix another -Wmaybe-uninitialized warning
From: Or Gerlitz @ 2017-01-12 8:30 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Saeed Mahameed, Hadar Hen Zion, David S . Miller, netdev,
linux-kernel
In-Reply-To: <20170111211451.2705705-1-arnd@arndb.de>
On 1/11/2017 11:14 PM, Arnd Bergmann wrote:
> @@ -666,14 +666,15 @@ static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
> struct rtable *rt;
> struct neighbour *n = NULL;
> int ttl;
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_INET))
> + return -EOPNOTSUPP;
>
> -#if IS_ENABLED(CONFIG_INET)
> rt = ip_route_output_key(dev_net(mirred_dev), fl4);
> - if (IS_ERR(rt))
> - return PTR_ERR(rt);
> -#else
> - return -EOPNOTSUPP;
> -#endif
> + ret = PTR_ERR_OR_ZERO(rt);
> + if (ret)
> + return ret;
but this means that if we got NULL from ip_route_output_key, we will
return success (0) here which is wrong.
^ permalink raw reply
* Re: [PATCH iproute2 1/3] sr: add header files for SR-IPv6
From: David Lebrun @ 2017-01-12 8:35 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev
In-Reply-To: <20170110103328.726fc537@xeon-e3>
[-- Attachment #1: Type: text/plain, Size: 441 bytes --]
On 01/10/2017 07:33 PM, Stephen Hemminger wrote:
> I get all headers from santized kernel headers generated by
> $ make headers_install
> but the segmentation stuff is missing.
>
> When you added segment routing headers you forgot to export them.
> Please send a patch to include/uapi/linux/Kbuild, after that is merged
> I will pick them up.
>
> Also this patch is only for net-next.
Oops ! Will do that, thanks
David
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^ permalink raw reply
* Re: [PATCH] wext: handle NULL exta data in iwe_stream_add_point better
From: Johannes Berg @ 2017-01-12 8:37 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linux-wireless, David S. Miller, Networking, linux-kernel
In-Reply-To: <3292373.oxnXTOSWCQ@wuerfel>
On Wed, 2017-01-11 at 21:39 +0100, Arnd Bergmann wrote:
> On Wednesday, January 11, 2017 4:06:17 PM CET Johannes Berg wrote:
> >
> > Applied. Also fixed the typo in the subject :)
>
> Thanks! Unfortunately I now got another warning for the same
> function, and though I would have expected the patch to fix it, that
> did not work:
I've come to expect better of you (i.e. testing your own patches) ;-)
Come to think of it, I'm thinking I should drop this patch and the
driver should just use iwe_stream_add_event() instead? It'll be
somewhat tricky to get the length correct though.
Alternatively, perhaps we should just uninline all the crap and then
the compiler can't bother us :)
johannes
^ permalink raw reply
* [PATCH/RFC net] ravb: Remove Rx overflow log messages
From: Simon Horman @ 2017-01-12 8:41 UTC (permalink / raw)
To: David Miller, Sergei Shtylyov; +Cc: Magnus Damm, netdev, linux-renesas-soc
From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Remove Rx overflow log messages as in an environment where logging results
in network traffic logging may cause further overflows.
Fixes: c156633f1353 ("Renesas Ethernet AVB driver proper")
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[simon: reworked changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/net/ethernet/renesas/ravb_main.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 92d7692c840d..5e5ad978eab9 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -926,14 +926,10 @@ static int ravb_poll(struct napi_struct *napi, int budget)
/* Receive error message handling */
priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
- if (priv->rx_over_errors != ndev->stats.rx_over_errors) {
+ if (priv->rx_over_errors != ndev->stats.rx_over_errors)
ndev->stats.rx_over_errors = priv->rx_over_errors;
- netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n");
- }
- if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) {
+ if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
- netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n");
- }
out:
return budget - quota;
}
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* Re: [Patch net] atm: remove an unnecessary loop
From: Michal Hocko @ 2017-01-12 8:43 UTC (permalink / raw)
To: Cong Wang; +Cc: netdev, romieu, 3chas3, andreyknvl
In-Reply-To: <1484197322-958-1-git-send-email-xiyou.wangcong@gmail.com>
On Wed 11-01-17 21:02:01, Cong Wang wrote:
> alloc_tx() is already inside a wait loop for a successful skb
> allocation, this loop inside alloc_tx() is quite unnecessary
> and actually problematic.
I am not familiar with this code at all but vcc_sendmsg seems to be one
of those cases where open coding __GFP_NOFAIL semantic makes sense as
there is an allocation fallback strategy implemented.
> Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com>
I cannot give my reviewed-by because I am not familiar with the code but
this looks like an improvement to me.
> ---
> net/atm/common.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/net/atm/common.c b/net/atm/common.c
> index a3ca922..7ec3bbc 100644
> --- a/net/atm/common.c
> +++ b/net/atm/common.c
> @@ -72,10 +72,11 @@ static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
> sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
> return NULL;
> }
> - while (!(skb = alloc_skb(size, GFP_KERNEL)))
> - schedule();
> - pr_debug("%d += %d\n", sk_wmem_alloc_get(sk), skb->truesize);
> - atomic_add(skb->truesize, &sk->sk_wmem_alloc);
> + skb = alloc_skb(size, GFP_KERNEL);
> + if (skb) {
> + pr_debug("%d += %d\n", sk_wmem_alloc_get(sk), skb->truesize);
> + atomic_add(skb->truesize, &sk->sk_wmem_alloc);
> + }
> return skb;
> }
>
> --
> 2.5.5
--
Michal Hocko
SUSE Labs
^ permalink raw reply
* Re: wl1251 & mac address & calibration data
From: Pavel Machek @ 2017-01-12 8:50 UTC (permalink / raw)
To: Kalle Valo
Cc: Arend Van Spriel, Pali Rohár, Daniel Wagner,
Luis R. Rodriguez, Tom Gundersen, Johannes Berg, Ming Lei,
Mimi Zohar, Bjorn Andersson, Rafał Miłecki,
Sebastian Reichel, Michal Kazior, Ivaylo Dimitrov, Aaro Koskinen,
Tony Lindgren, linux-wireless, Network Development,
linux-kernel@vger.kernel.org
In-Reply-To: <87shpiu8j8.fsf@kamboji.qca.qualcomm.com>
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Hi!
> >> But overwriting that one file is not possible as it next update of
> >> linux-firmware package will overwrite it back. It break any normal usage
> >> of package management.
> >>
> >> Also it is ridiculously broken by design if some "boot" files needs to
> >> be overwritten to initialize hardware properly. To not break booting you
> >> need to overwrite that file before first boot. But without booting
> >> device you cannot read calibration data. So some hack with autoreboot
> >> after boot is needed.
>
> Providing the calibration data via Device Tree is the proper way to
> solve this. Yes yes, I know N900 doesn't support it but that's a
> deficiency in N900, not Linux.
Linux has to work with whatever hardware provides. You may not like
N900 design, but we have to support it, anyway.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply
* Re: [PATCH] [v2] net: qcom/emac: grab a reference to the phydev on ACPI systems
From: Johan Hovold @ 2017-01-12 9:07 UTC (permalink / raw)
To: Timur Tabi; +Cc: David Miller, netdev, johan
In-Reply-To: <1484174751-19036-1-git-send-email-timur@codeaurora.org>
On Wed, Jan 11, 2017 at 04:45:51PM -0600, Timur Tabi wrote:
> Commit 6ffe1c4cd0a7 ("net: qcom/emac: fix of_node and phydev leaks")
> fixed the problem with reference leaks on phydev, but the fix is
> device-tree specific. When the driver unloads, the reference is
> dropped only on DT systems.
>
> Instead, it's cleaner if up grab an reference on ACPI systems.
> When the driver unloads, we can drop the reference without having
> to check whether we're on a DT system.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Johan Hovold <johan@kernel.org>
^ permalink raw reply
* Re: [PATCH/RFC v2 net-next] ravb: unmap descriptors when freeing rings
From: Simon Horman @ 2017-01-12 9:11 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: David Miller, Magnus Damm, netdev, linux-renesas-soc
In-Reply-To: <6fcec500-bed6-ffa3-2887-d45b34703682@cogentembedded.com>
On Fri, Jan 06, 2017 at 10:02:36PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 01/05/2017 01:43 PM, Simon Horman wrote:
>
> >From: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> >
> >"swiotlb buffer is full" errors occur after repeated initialisation of a
> >device - f.e. suspend/resume or ip link set up/down. This is because memory
> >mapped using dma_map_single() in ravb_ring_format() and ravb_start_xmit()
> >is not released. Resolve this problem by unmapping descriptors when
> >freeing rings.
> >
> >Note, ravb_tx_free() is moved but not otherwise modified by this patch.
> >
> >Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
> >[simon: reworked]
> >Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >--
> >v1 [Kazuya Mizuguchi]
> >
> >v2 [Simon Horman]
> >* As suggested by Sergei Shtylyov
> > - Use dma_mapping_error() and rx_desc->ds_cc when unmapping RX descriptors;
> > this is consistent with the way that they are mapped
> > - Use ravb_tx_free() to clear TX descriptors
>
> Not sure that was good idea (sorry)... ravb_tx_ring() only unmaps the
> transmitted buffers, while we need to unmap everything...
>
> >* Reduce scope of new local variable
> >---
> > drivers/net/ethernet/renesas/ravb_main.c | 89 ++++++++++++++++++--------------
> > 1 file changed, 51 insertions(+), 38 deletions(-)
> >
> >diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> >index 92d7692c840d..1797c48e3176 100644
> >--- a/drivers/net/ethernet/renesas/ravb_main.c
> >+++ b/drivers/net/ethernet/renesas/ravb_main.c
> >@@ -179,6 +179,44 @@ static struct mdiobb_ops bb_ops = {
> > .get_mdio_data = ravb_get_mdio_data,
> > };
> >
> >+/* Free TX skb function for AVB-IP */
> >+static int ravb_tx_free(struct net_device *ndev, int q)
> >+{
> >+ struct ravb_private *priv = netdev_priv(ndev);
> >+ struct net_device_stats *stats = &priv->stats[q];
> >+ struct ravb_tx_desc *desc;
> >+ int free_num = 0;
> >+ int entry;
> >+ u32 size;
> >+
> >+ for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
> >+ entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
> >+ NUM_TX_DESC);
> >+ desc = &priv->tx_ring[q][entry];
> >+ if (desc->die_dt != DT_FEMPTY)
>
> Here, it stop once an untransmitted buffer is encountered...
Yes, I see that now.
I wonder if we should:
a) paramatise ravb_tx_free() so it may either clear all transmitted buffers
(current behaviour) or all buffers (new behaviour).
b) provide a different version of this loop in ravb_ring_free()
What are your thoughts?
> >+ break;
> >+ /* Descriptor type must be checked before all other reads */
> >+ dma_rmb();
> >+ size = le16_to_cpu(desc->ds_tagl) & TX_DS;
> >+ /* Free the original skb. */
> >+ if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
> >+ dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
> >+ size, DMA_TO_DEVICE);
> >+ /* Last packet descriptor? */
> >+ if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
> >+ entry /= NUM_TX_DESC;
> >+ dev_kfree_skb_any(priv->tx_skb[q][entry]);
> >+ priv->tx_skb[q][entry] = NULL;
> >+ stats->tx_packets++;
> >+ }
> >+ free_num++;
> >+ }
> >+ stats->tx_bytes += size;
> >+ desc->die_dt = DT_EEMPTY;
> >+ }
> >+ return free_num;
> >+}
> >+
> > /* Free skb's and DMA buffers for Ethernet AVB */
> > static void ravb_ring_free(struct net_device *ndev, int q)
> > {
> >@@ -207,6 +245,18 @@ static void ravb_ring_free(struct net_device *ndev, int q)
> > priv->tx_align[q] = NULL;
> >
> > if (priv->rx_ring[q]) {
> >+ for (i = 0; i < priv->num_rx_ring[q]; i++) {
> >+ struct ravb_ex_rx_desc *rx_desc = &priv->rx_ring[q][i];
> >+
> >+ if (!dma_mapping_error(ndev->dev.parent,
> >+ rx_desc->dptr)) {
>
> You forgot le32_to_cpu() here, we can't use the raw descriptor fields.
Thanks, I will fix that.
> >+ dma_unmap_single(ndev->dev.parent,
> >+ le32_to_cpu(rx_desc->dptr),
> >+ PKT_BUF_SZ,
> >+ DMA_FROM_DEVICE);
> >+ rx_desc->ds_cc = cpu_to_le16(0);
>
> You don't check it anyway, not sure what that buys...
Thanks, I will see about dropping that.
^ permalink raw reply
* Re: [PATCH] wext: handle NULL exta data in iwe_stream_add_point better
From: Johannes Berg @ 2017-01-12 9:13 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linux-wireless, David S. Miller, Networking, linux-kernel
In-Reply-To: <1484210226.5391.1.camel@sipsolutions.net>
> Come to think of it, I'm thinking I should drop this patch and the
> driver should just use iwe_stream_add_event() instead? It'll be
> somewhat tricky to get the length correct though.
No, turns out that's basically impossible with all the compat etc.
stuff here.
johannes
^ permalink raw reply
* Re: [PATCH] wext: handle NULL exta data in iwe_stream_add_point better
From: Johannes Berg @ 2017-01-12 9:16 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linux-wireless, David S. Miller, Networking, linux-kernel
In-Reply-To: <3292373.oxnXTOSWCQ@wuerfel>
On Wed, 2017-01-11 at 21:39 +0100, Arnd Bergmann wrote:
> On Wednesday, January 11, 2017 4:06:17 PM CET Johannes Berg wrote:
> >
> > Applied. Also fixed the typo in the subject :)
>
> Thanks! Unfortunately I now got another warning for the same
> function, and though I would have expected the patch to fix it, that
> did not work:
>
> In file included from /git/arm-
> soc/drivers/net/wireless/intersil/prism54/islpci_dev.h:27:0,
> from /git/arm-
> soc/drivers/net/wireless/intersil/prism54/isl_ioctl.h:24,
> from /git/arm-
> soc/drivers/net/wireless/intersil/prism54/isl_ioctl.c:32:
> /git/arm-soc/drivers/net/wireless/intersil/prism54/isl_ioctl.c: In
> function 'prism54_get_scan':
> /git/arm-soc/include/net/iw_handler.h:560:4: error: argument 2 null
> where non-null expected [-Werror=nonnull]
> memcpy(stream + point_len, extra, iwe->u.data.length);
And I realized only now that this was a different place ...
I've just added the check you suggested - spent way too much time
already on this old crap :)
johannes
^ permalink raw reply
* Re: [PATCH] wext: handle NULL exta data in iwe_stream_add_point better
From: Arnd Bergmann @ 2017-01-12 9:44 UTC (permalink / raw)
To: Johannes Berg; +Cc: linux-wireless, David S. Miller, Networking, linux-kernel
In-Reply-To: <1484212560.5391.3.camel@sipsolutions.net>
On Thursday, January 12, 2017 10:16:00 AM CET Johannes Berg wrote:
> And I realized only now that this was a different place ...
Right, it was a few hundred randconfigs later after I had confirmed
that the first patch fixed all the configurations that were broken
at first.
> I've just added the check you suggested - spent way too much time
> already on this old crap
Ok, thanks! Let's hope it doesn't come back once more.
I'm still trying to categorize the newly added warnings in gcc-7,
there a number of very useful warnings that got added, but some of
them are rather noisy and find both a number of real bugs and
false positives. The NULL check had only a few findings that all
seemed worth fixing.
Arnd
^ permalink raw reply
* Re: [PATCH v2 2/2] stmmac: rename it to synopsys
From: Joao Pinto @ 2017-01-12 9:43 UTC (permalink / raw)
To: Florian Fainelli, Joao Pinto, davem
Cc: lars.persson, niklass, peppe.cavallaro, alexandre.torgue, netdev
In-Reply-To: <5b5a3231-eed4-ef29-b32a-a19077681dad@gmail.com>
Hi Florian,
Às 9:14 PM de 1/11/2017, Florian Fainelli escreveu:
> On 01/10/2017 06:52 AM, Joao Pinto wrote:
>> This patch renames stmicro/stmmac to synopsys/ since it is a standard
>> ethernet software package regarding synopsys ethernet controllers, supporting
>> the majority of Synopsys Ethernet IPs. The config IDs remain the same, for
>> retro-compatibility, only the description was changed.
>
> Do re really have to do this? ST Micro were the first to upstream
> support for a Synopsys IP, and it was later on identified as being
> "stmicro" instead of "synopsys" (during the big driver move under
> drivers/net/ethernet) whichever came first in the driver essentially "wins".
>
> As mentioned before, although git is able to track renames, git log does
> not automatically have --follow, so it can be hard for people to track
> down the (new) history of the driver.
>
> Personally, I don't see much value in doing this rename, especially when
> all the driver internal structures are still going to be named with
> stmmac (and please don't even think about doing a s/stmmac/snps/ inside
> the driver ;)).
>
> My 2 cents.
>
First of all, I am suggesting an alternative way of organizing the code, and
that's it, I have no second intentions about anything :).
Please don't see this as a take-over or erase Stmicro from credits, please... it
makes no sense. You can leave STMicro license and all the credits fine by me and
I insist on it. But lets name it for something that makes sense... lets call it
dwc (designware controllers), I am totally open to suggestions.
I don't understand the hostility of some comments, honestly.
The easiest way is to keep things like they are today, and believe me I have a
lot of things to do, like adding the support of multi-queues / multi-channels to
stmmac, so I not suggesting this because it is fun.
I am suggesting this because it is what I am used to seeing in other subsystems.
USB has dwc2 and dwc3 folders that clearly identifies that they are Designware
(synopsys) extensions to the USB 2.0 and 3.0. The author of dwc3 was Texas
Instruments, and they did not name it ti/usb. For example I use an AXS101
Development board that does not have a stmicro SoC but has a Designware Ethernet
IP in it, so uses stmicro/stmmac. For me it is confusing.
Lets not name it synopsys, for me it is totally fine, but naming it
stmicro/stmmac is not the right way because it seems like it is a driver just
for stmicro products, which is not, is for products that use Designware Ethernet
IPs.
I am volunteering to do this work, let's discuss this.
Thanks,
Joao
^ permalink raw reply
* [PATCH] synopsys: remove dwc_eth_qos driver
From: Joao Pinto @ 2017-01-12 9:56 UTC (permalink / raw)
To: davem
Cc: lars.persson, niklass, peppe.cavallaro, alexandre.torgue, netdev,
Joao Pinto
This driver is no longer necessary since it was merged into stmmac.
Acked-by: Lars Persson <larper@axis.com>
Signed-off-by: Joao Pinto <jpinto@synopsys.com>
---
MAINTAINERS | 7 -
arch/arm/configs/multi_v7_defconfig | 3 +-
drivers/net/ethernet/Kconfig | 1 -
drivers/net/ethernet/Makefile | 1 -
drivers/net/ethernet/synopsys/Kconfig | 27 -
drivers/net/ethernet/synopsys/Makefile | 5 -
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 2996 ---------------------------
7 files changed, 2 insertions(+), 3038 deletions(-)
delete mode 100644 drivers/net/ethernet/synopsys/Kconfig
delete mode 100644 drivers/net/ethernet/synopsys/Makefile
delete mode 100644 drivers/net/ethernet/synopsys/dwc_eth_qos.c
diff --git a/MAINTAINERS b/MAINTAINERS
index c8df0e1..acfb0a0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10865,13 +10865,6 @@ F: include/linux/dma/dw.h
F: include/linux/platform_data/dma-dw.h
F: drivers/dma/dw/
-SYNOPSYS DESIGNWARE ETHERNET QOS 4.10a driver
-M: Lars Persson <lars.persson@axis.com>
-L: netdev@vger.kernel.org
-S: Supported
-F: Documentation/devicetree/bindings/net/snps,dwc-qos-ethernet.txt
-F: drivers/net/ethernet/synopsys/dwc_eth_qos.c
-
SYNOPSYS DESIGNWARE I2C DRIVER
M: Jarkko Nikula <jarkko.nikula@linux.intel.com>
R: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index b01a438..64f4419 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -253,7 +253,8 @@ CONFIG_R8169=y
CONFIG_SH_ETH=y
CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y
-CONFIG_SYNOPSYS_DWC_ETH_QOS=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y
CONFIG_AT803X_PHY=y
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index e4c28fe..afc07d4 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -170,7 +170,6 @@ source "drivers/net/ethernet/sgi/Kconfig"
source "drivers/net/ethernet/smsc/Kconfig"
source "drivers/net/ethernet/stmicro/Kconfig"
source "drivers/net/ethernet/sun/Kconfig"
-source "drivers/net/ethernet/synopsys/Kconfig"
source "drivers/net/ethernet/tehuti/Kconfig"
source "drivers/net/ethernet/ti/Kconfig"
source "drivers/net/ethernet/tile/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 24330f4..e7861a8 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -81,7 +81,6 @@ obj-$(CONFIG_NET_VENDOR_SGI) += sgi/
obj-$(CONFIG_NET_VENDOR_SMSC) += smsc/
obj-$(CONFIG_NET_VENDOR_STMICRO) += stmicro/
obj-$(CONFIG_NET_VENDOR_SUN) += sun/
-obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/
obj-$(CONFIG_NET_VENDOR_TEHUTI) += tehuti/
obj-$(CONFIG_NET_VENDOR_TI) += ti/
obj-$(CONFIG_TILE_NET) += tile/
diff --git a/drivers/net/ethernet/synopsys/Kconfig b/drivers/net/ethernet/synopsys/Kconfig
deleted file mode 100644
index 8276ee5..0000000
--- a/drivers/net/ethernet/synopsys/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Synopsys network device configuration
-#
-
-config NET_VENDOR_SYNOPSYS
- bool "Synopsys devices"
- default y
- ---help---
- If you have a network (Ethernet) device belonging to this class, say Y.
-
- Note that the answer to this question doesn't directly affect the
- kernel: saying N will just cause the configurator to skip all
- the questions about Synopsys devices. If you say Y, you will be asked
- for your specific device in the following questions.
-
-if NET_VENDOR_SYNOPSYS
-
-config SYNOPSYS_DWC_ETH_QOS
- tristate "Sypnopsys DWC Ethernet QOS v4.10a support"
- select PHYLIB
- select CRC32
- select MII
- depends on OF && HAS_DMA
- ---help---
- This driver supports the DWC Ethernet QoS from Synopsys
-
-endif # NET_VENDOR_SYNOPSYS
diff --git a/drivers/net/ethernet/synopsys/Makefile b/drivers/net/ethernet/synopsys/Makefile
deleted file mode 100644
index 7a37572..0000000
--- a/drivers/net/ethernet/synopsys/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Synopsys network device drivers.
-#
-
-obj-$(CONFIG_SYNOPSYS_DWC_ETH_QOS) += dwc_eth_qos.o
diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
deleted file mode 100644
index 467dcc5..0000000
--- a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
+++ /dev/null
@@ -1,2996 +0,0 @@
-/* Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
- *
- * This is a driver for the Synopsys DWC Ethernet QoS IP version 4.10a (GMAC).
- * This version introduced a lot of changes which breaks backwards
- * compatibility the non-QoS IP from Synopsys (used in the ST Micro drivers).
- * Some fields differ between version 4.00a and 4.10a, mainly the interrupt
- * bit fields. The driver could be made compatible with 4.00, if all relevant
- * HW erratas are handled.
- *
- * The GMAC is highly configurable at synthesis time. This driver has been
- * developed for a subset of the total available feature set. Currently
- * it supports:
- * - TSO
- * - Checksum offload for RX and TX.
- * - Energy efficient ethernet.
- * - GMII phy interface.
- * - The statistics module.
- * - Single RX and TX queue.
- *
- * Copyright (C) 2015 Axis Communications AB.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ethtool.h>
-#include <linux/stat.h>
-#include <linux/types.h>
-
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-
-#include <linux/phy.h>
-#include <linux/mii.h>
-#include <linux/dma-mapping.h>
-#include <linux/vmalloc.h>
-
-#include <linux/device.h>
-#include <linux/bitrev.h>
-#include <linux/crc32.h>
-
-#include <linux/of.h>
-#include <linux/interrupt.h>
-#include <linux/clocksource.h>
-#include <linux/net_tstamp.h>
-#include <linux/pm_runtime.h>
-#include <linux/of_net.h>
-#include <linux/of_address.h>
-#include <linux/of_mdio.h>
-#include <linux/timer.h>
-#include <linux/tcp.h>
-
-#define DRIVER_NAME "dwceqos"
-#define DRIVER_DESCRIPTION "Synopsys DWC Ethernet QoS driver"
-#define DRIVER_VERSION "0.9"
-
-#define DWCEQOS_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
- NETIF_MSG_LINK | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
-
-#define DWCEQOS_TX_TIMEOUT 5 /* Seconds */
-
-#define DWCEQOS_LPI_TIMER_MIN 8
-#define DWCEQOS_LPI_TIMER_MAX ((1 << 20) - 1)
-
-#define DWCEQOS_RX_BUF_SIZE 2048
-
-#define DWCEQOS_RX_DCNT 256
-#define DWCEQOS_TX_DCNT 256
-
-#define DWCEQOS_HASH_TABLE_SIZE 64
-
-/* The size field in the DMA descriptor is 14 bits */
-#define BYTES_PER_DMA_DESC 16376
-
-/* Hardware registers */
-#define START_MAC_REG_OFFSET 0x0000
-#define MAX_MAC_REG_OFFSET 0x0bd0
-#define START_MTL_REG_OFFSET 0x0c00
-#define MAX_MTL_REG_OFFSET 0x0d7c
-#define START_DMA_REG_OFFSET 0x1000
-#define MAX_DMA_REG_OFFSET 0x117C
-
-#define REG_SPACE_SIZE 0x1800
-
-/* DMA */
-#define REG_DWCEQOS_DMA_MODE 0x1000
-#define REG_DWCEQOS_DMA_SYSBUS_MODE 0x1004
-#define REG_DWCEQOS_DMA_IS 0x1008
-#define REG_DWCEQOS_DMA_DEBUG_ST0 0x100c
-
-/* DMA channel registers */
-#define REG_DWCEQOS_DMA_CH0_CTRL 0x1100
-#define REG_DWCEQOS_DMA_CH0_TX_CTRL 0x1104
-#define REG_DWCEQOS_DMA_CH0_RX_CTRL 0x1108
-#define REG_DWCEQOS_DMA_CH0_TXDESC_LIST 0x1114
-#define REG_DWCEQOS_DMA_CH0_RXDESC_LIST 0x111c
-#define REG_DWCEQOS_DMA_CH0_TXDESC_TAIL 0x1120
-#define REG_DWCEQOS_DMA_CH0_RXDESC_TAIL 0x1128
-#define REG_DWCEQOS_DMA_CH0_TXDESC_LEN 0x112c
-#define REG_DWCEQOS_DMA_CH0_RXDESC_LEN 0x1130
-#define REG_DWCEQOS_DMA_CH0_IE 0x1134
-#define REG_DWCEQOS_DMA_CH0_CUR_TXDESC 0x1144
-#define REG_DWCEQOS_DMA_CH0_CUR_RXDESC 0x114c
-#define REG_DWCEQOS_DMA_CH0_CUR_TXBUF 0x1154
-#define REG_DWCEQOS_DMA_CH0_CUR_RXBUG 0x115c
-#define REG_DWCEQOS_DMA_CH0_STA 0x1160
-
-#define DWCEQOS_DMA_MODE_TXPR BIT(11)
-#define DWCEQOS_DMA_MODE_DA BIT(1)
-
-#define DWCEQOS_DMA_SYSBUS_MODE_EN_LPI BIT(31)
-#define DWCEQOS_DMA_SYSBUS_MODE_FB BIT(0)
-#define DWCEQOS_DMA_SYSBUS_MODE_AAL BIT(12)
-
-#define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(x) \
- (((x) << 16) & 0x000F0000)
-#define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_DEFAULT 3
-#define DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_MASK GENMASK(19, 16)
-
-#define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(x) \
- (((x) << 24) & 0x0F000000)
-#define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_DEFAULT 3
-#define DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_MASK GENMASK(27, 24)
-
-#define DWCEQOS_DMA_SYSBUS_MODE_BURST_MASK GENMASK(7, 1)
-#define DWCEQOS_DMA_SYSBUS_MODE_BURST(x) \
- (((x) << 1) & DWCEQOS_DMA_SYSBUS_MODE_BURST_MASK)
-#define DWCEQOS_DMA_SYSBUS_MODE_BURST_DEFAULT GENMASK(3, 1)
-
-#define DWCEQOS_DMA_CH_CTRL_PBLX8 BIT(16)
-#define DWCEQOS_DMA_CH_CTRL_DSL(x) ((x) << 18)
-
-#define DWCEQOS_DMA_CH_CTRL_PBL(x) ((x) << 16)
-#define DWCEQOS_DMA_CH_CTRL_START BIT(0)
-#define DWCEQOS_DMA_CH_RX_CTRL_BUFSIZE(x) ((x) << 1)
-#define DWCEQOS_DMA_CH_TX_OSP BIT(4)
-#define DWCEQOS_DMA_CH_TX_TSE BIT(12)
-
-#define DWCEQOS_DMA_CH0_IE_NIE BIT(15)
-#define DWCEQOS_DMA_CH0_IE_AIE BIT(14)
-#define DWCEQOS_DMA_CH0_IE_RIE BIT(6)
-#define DWCEQOS_DMA_CH0_IE_TIE BIT(0)
-#define DWCEQOS_DMA_CH0_IE_FBEE BIT(12)
-#define DWCEQOS_DMA_CH0_IE_RBUE BIT(7)
-
-#define DWCEQOS_DMA_IS_DC0IS BIT(0)
-#define DWCEQOS_DMA_IS_MTLIS BIT(16)
-#define DWCEQOS_DMA_IS_MACIS BIT(17)
-
-#define DWCEQOS_DMA_CH0_IS_TI BIT(0)
-#define DWCEQOS_DMA_CH0_IS_RI BIT(6)
-#define DWCEQOS_DMA_CH0_IS_RBU BIT(7)
-#define DWCEQOS_DMA_CH0_IS_FBE BIT(12)
-#define DWCEQOS_DMA_CH0_IS_CDE BIT(13)
-#define DWCEQOS_DMA_CH0_IS_AIS BIT(14)
-
-#define DWCEQOS_DMA_CH0_IS_TEB GENMASK(18, 16)
-#define DWCEQOS_DMA_CH0_IS_TX_ERR_READ BIT(16)
-#define DWCEQOS_DMA_CH0_IS_TX_ERR_DESCR BIT(17)
-
-#define DWCEQOS_DMA_CH0_IS_REB GENMASK(21, 19)
-#define DWCEQOS_DMA_CH0_IS_RX_ERR_READ BIT(19)
-#define DWCEQOS_DMA_CH0_IS_RX_ERR_DESCR BIT(20)
-
-/* DMA descriptor bits for RX normal descriptor (read format) */
-#define DWCEQOS_DMA_RDES3_OWN BIT(31)
-#define DWCEQOS_DMA_RDES3_INTE BIT(30)
-#define DWCEQOS_DMA_RDES3_BUF2V BIT(25)
-#define DWCEQOS_DMA_RDES3_BUF1V BIT(24)
-
-/* DMA descriptor bits for RX normal descriptor (write back format) */
-#define DWCEQOS_DMA_RDES1_IPCE BIT(7)
-#define DWCEQOS_DMA_RDES3_ES BIT(15)
-#define DWCEQOS_DMA_RDES3_E_JT BIT(14)
-#define DWCEQOS_DMA_RDES3_PL(x) ((x) & 0x7fff)
-#define DWCEQOS_DMA_RDES1_PT 0x00000007
-#define DWCEQOS_DMA_RDES1_PT_UDP BIT(0)
-#define DWCEQOS_DMA_RDES1_PT_TCP BIT(1)
-#define DWCEQOS_DMA_RDES1_PT_ICMP 0x00000003
-
-/* DMA descriptor bits for TX normal descriptor (read format) */
-#define DWCEQOS_DMA_TDES2_IOC BIT(31)
-#define DWCEQOS_DMA_TDES3_OWN BIT(31)
-#define DWCEQOS_DMA_TDES3_CTXT BIT(30)
-#define DWCEQOS_DMA_TDES3_FD BIT(29)
-#define DWCEQOS_DMA_TDES3_LD BIT(28)
-#define DWCEQOS_DMA_TDES3_CIPH BIT(16)
-#define DWCEQOS_DMA_TDES3_CIPP BIT(17)
-#define DWCEQOS_DMA_TDES3_CA 0x00030000
-#define DWCEQOS_DMA_TDES3_TSE BIT(18)
-#define DWCEQOS_DMA_DES3_THL(x) ((x) << 19)
-#define DWCEQOS_DMA_DES2_B2L(x) ((x) << 16)
-
-#define DWCEQOS_DMA_TDES3_TCMSSV BIT(26)
-
-/* DMA channel states */
-#define DMA_TX_CH_STOPPED 0
-#define DMA_TX_CH_SUSPENDED 6
-
-#define DMA_GET_TX_STATE_CH0(status0) ((status0 & 0xF000) >> 12)
-
-/* MTL */
-#define REG_DWCEQOS_MTL_OPER 0x0c00
-#define REG_DWCEQOS_MTL_DEBUG_ST 0x0c0c
-#define REG_DWCEQOS_MTL_TXQ0_DEBUG_ST 0x0d08
-#define REG_DWCEQOS_MTL_RXQ0_DEBUG_ST 0x0d38
-
-#define REG_DWCEQOS_MTL_IS 0x0c20
-#define REG_DWCEQOS_MTL_TXQ0_OPER 0x0d00
-#define REG_DWCEQOS_MTL_RXQ0_OPER 0x0d30
-#define REG_DWCEQOS_MTL_RXQ0_MIS_CNT 0x0d34
-#define REG_DWCEQOS_MTL_RXQ0_CTRL 0x0d3c
-
-#define REG_DWCEQOS_MTL_Q0_ISCTRL 0x0d2c
-
-#define DWCEQOS_MTL_SCHALG_STRICT 0x00000060
-
-#define DWCEQOS_MTL_TXQ_TXQEN BIT(3)
-#define DWCEQOS_MTL_TXQ_TSF BIT(1)
-#define DWCEQOS_MTL_TXQ_FTQ BIT(0)
-#define DWCEQOS_MTL_TXQ_TTC512 0x00000070
-
-#define DWCEQOS_MTL_TXQ_SIZE(x) ((((x) - 256) & 0xff00) << 8)
-
-#define DWCEQOS_MTL_RXQ_SIZE(x) ((((x) - 256) & 0xff00) << 12)
-#define DWCEQOS_MTL_RXQ_EHFC BIT(7)
-#define DWCEQOS_MTL_RXQ_DIS_TCP_EF BIT(6)
-#define DWCEQOS_MTL_RXQ_FEP BIT(4)
-#define DWCEQOS_MTL_RXQ_FUP BIT(3)
-#define DWCEQOS_MTL_RXQ_RSF BIT(5)
-#define DWCEQOS_MTL_RXQ_RTC32 BIT(0)
-
-/* MAC */
-#define REG_DWCEQOS_MAC_CFG 0x0000
-#define REG_DWCEQOS_MAC_EXT_CFG 0x0004
-#define REG_DWCEQOS_MAC_PKT_FILT 0x0008
-#define REG_DWCEQOS_MAC_WD_TO 0x000c
-#define REG_DWCEQOS_HASTABLE_LO 0x0010
-#define REG_DWCEQOS_HASTABLE_HI 0x0014
-#define REG_DWCEQOS_MAC_IS 0x00b0
-#define REG_DWCEQOS_MAC_IE 0x00b4
-#define REG_DWCEQOS_MAC_STAT 0x00b8
-#define REG_DWCEQOS_MAC_MDIO_ADDR 0x0200
-#define REG_DWCEQOS_MAC_MDIO_DATA 0x0204
-#define REG_DWCEQOS_MAC_MAC_ADDR0_HI 0x0300
-#define REG_DWCEQOS_MAC_MAC_ADDR0_LO 0x0304
-#define REG_DWCEQOS_MAC_RXQ0_CTRL0 0x00a0
-#define REG_DWCEQOS_MAC_HW_FEATURE0 0x011c
-#define REG_DWCEQOS_MAC_HW_FEATURE1 0x0120
-#define REG_DWCEQOS_MAC_HW_FEATURE2 0x0124
-#define REG_DWCEQOS_MAC_HASHTABLE_LO 0x0010
-#define REG_DWCEQOS_MAC_HASHTABLE_HI 0x0014
-#define REG_DWCEQOS_MAC_LPI_CTRL_STATUS 0x00d0
-#define REG_DWCEQOS_MAC_LPI_TIMERS_CTRL 0x00d4
-#define REG_DWCEQOS_MAC_LPI_ENTRY_TIMER 0x00d8
-#define REG_DWCEQOS_MAC_1US_TIC_COUNTER 0x00dc
-#define REG_DWCEQOS_MAC_RX_FLOW_CTRL 0x0090
-#define REG_DWCEQOS_MAC_Q0_TX_FLOW 0x0070
-
-#define DWCEQOS_MAC_CFG_ACS BIT(20)
-#define DWCEQOS_MAC_CFG_JD BIT(17)
-#define DWCEQOS_MAC_CFG_JE BIT(16)
-#define DWCEQOS_MAC_CFG_PS BIT(15)
-#define DWCEQOS_MAC_CFG_FES BIT(14)
-#define DWCEQOS_MAC_CFG_DM BIT(13)
-#define DWCEQOS_MAC_CFG_DO BIT(10)
-#define DWCEQOS_MAC_CFG_TE BIT(1)
-#define DWCEQOS_MAC_CFG_IPC BIT(27)
-#define DWCEQOS_MAC_CFG_RE BIT(0)
-
-#define DWCEQOS_ADDR_HIGH(reg) (0x00000300 + (reg * 8))
-#define DWCEQOS_ADDR_LOW(reg) (0x00000304 + (reg * 8))
-
-#define DWCEQOS_MAC_IS_LPI_INT BIT(5)
-#define DWCEQOS_MAC_IS_MMC_INT BIT(8)
-
-#define DWCEQOS_MAC_RXQ_EN BIT(1)
-#define DWCEQOS_MAC_MAC_ADDR_HI_EN BIT(31)
-#define DWCEQOS_MAC_PKT_FILT_RA BIT(31)
-#define DWCEQOS_MAC_PKT_FILT_HPF BIT(10)
-#define DWCEQOS_MAC_PKT_FILT_SAF BIT(9)
-#define DWCEQOS_MAC_PKT_FILT_SAIF BIT(8)
-#define DWCEQOS_MAC_PKT_FILT_DBF BIT(5)
-#define DWCEQOS_MAC_PKT_FILT_PM BIT(4)
-#define DWCEQOS_MAC_PKT_FILT_DAIF BIT(3)
-#define DWCEQOS_MAC_PKT_FILT_HMC BIT(2)
-#define DWCEQOS_MAC_PKT_FILT_HUC BIT(1)
-#define DWCEQOS_MAC_PKT_FILT_PR BIT(0)
-
-#define DWCEQOS_MAC_MDIO_ADDR_CR(x) (((x & 15)) << 8)
-#define DWCEQOS_MAC_MDIO_ADDR_CR_20 2
-#define DWCEQOS_MAC_MDIO_ADDR_CR_35 3
-#define DWCEQOS_MAC_MDIO_ADDR_CR_60 0
-#define DWCEQOS_MAC_MDIO_ADDR_CR_100 1
-#define DWCEQOS_MAC_MDIO_ADDR_CR_150 4
-#define DWCEQOS_MAC_MDIO_ADDR_CR_250 5
-#define DWCEQOS_MAC_MDIO_ADDR_GOC_READ 0x0000000c
-#define DWCEQOS_MAC_MDIO_ADDR_GOC_WRITE BIT(2)
-#define DWCEQOS_MAC_MDIO_ADDR_GB BIT(0)
-
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIEN BIT(0)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIEX BIT(1)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIEN BIT(2)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIEX BIT(3)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIST BIT(8)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIST BIT(9)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_LPIEN BIT(16)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_PLS BIT(17)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_PLSEN BIT(18)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA BIT(19)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_LPITE BIT(20)
-#define DWCEQOS_MAC_LPI_CTRL_STATUS_LPITCSE BIT(21)
-
-#define DWCEQOS_MAC_1US_TIC_COUNTER_VAL(x) ((x) & GENMASK(11, 0))
-
-#define DWCEQOS_LPI_CTRL_ENABLE_EEE (DWCEQOS_MAC_LPI_CTRL_STATUS_LPITE | \
- DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA | \
- DWCEQOS_MAC_LPI_CTRL_STATUS_LPIEN)
-
-#define DWCEQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
-
-#define DWCEQOS_MAC_Q0_TX_FLOW_TFE BIT(1)
-#define DWCEQOS_MAC_Q0_TX_FLOW_PT(time) ((time) << 16)
-#define DWCEQOS_MAC_Q0_TX_FLOW_PLT_4_SLOTS (0 << 4)
-
-/* Features */
-#define DWCEQOS_MAC_HW_FEATURE0_RXCOESEL BIT(16)
-#define DWCEQOS_MAC_HW_FEATURE0_TXCOESEL BIT(14)
-#define DWCEQOS_MAC_HW_FEATURE0_HDSEL BIT(2)
-#define DWCEQOS_MAC_HW_FEATURE0_EEESEL BIT(13)
-#define DWCEQOS_MAC_HW_FEATURE0_GMIISEL BIT(1)
-#define DWCEQOS_MAC_HW_FEATURE0_MIISEL BIT(0)
-
-#define DWCEQOS_MAC_HW_FEATURE1_TSOEN BIT(18)
-#define DWCEQOS_MAC_HW_FEATURE1_TXFIFOSIZE(x) ((128 << ((x) & 0x7c0)) >> 6)
-#define DWCEQOS_MAC_HW_FEATURE1_RXFIFOSIZE(x) (128 << ((x) & 0x1f))
-
-#define DWCEQOS_MAX_PERFECT_ADDRESSES(feature1) \
- (1 + (((feature1) & 0x1fc0000) >> 18))
-
-#define DWCEQOS_MDIO_PHYADDR(x) (((x) & 0x1f) << 21)
-#define DWCEQOS_MDIO_PHYREG(x) (((x) & 0x1f) << 16)
-
-#define DWCEQOS_DMA_MODE_SWR BIT(0)
-
-#define DWCEQOS_DWCEQOS_RX_BUF_SIZE 2048
-
-/* Mac Management Counters */
-#define REG_DWCEQOS_MMC_CTRL 0x0700
-#define REG_DWCEQOS_MMC_RXIRQ 0x0704
-#define REG_DWCEQOS_MMC_TXIRQ 0x0708
-#define REG_DWCEQOS_MMC_RXIRQMASK 0x070c
-#define REG_DWCEQOS_MMC_TXIRQMASK 0x0710
-
-#define DWCEQOS_MMC_CTRL_CNTRST BIT(0)
-#define DWCEQOS_MMC_CTRL_RSTONRD BIT(2)
-
-#define DWC_MMC_TXLPITRANSCNTR 0x07F0
-#define DWC_MMC_TXLPIUSCNTR 0x07EC
-#define DWC_MMC_TXOVERSIZE_G 0x0778
-#define DWC_MMC_TXVLANPACKETS_G 0x0774
-#define DWC_MMC_TXPAUSEPACKETS 0x0770
-#define DWC_MMC_TXEXCESSDEF 0x076C
-#define DWC_MMC_TXPACKETCOUNT_G 0x0768
-#define DWC_MMC_TXOCTETCOUNT_G 0x0764
-#define DWC_MMC_TXCARRIERERROR 0x0760
-#define DWC_MMC_TXEXCESSCOL 0x075C
-#define DWC_MMC_TXLATECOL 0x0758
-#define DWC_MMC_TXDEFERRED 0x0754
-#define DWC_MMC_TXMULTICOL_G 0x0750
-#define DWC_MMC_TXSINGLECOL_G 0x074C
-#define DWC_MMC_TXUNDERFLOWERROR 0x0748
-#define DWC_MMC_TXBROADCASTPACKETS_GB 0x0744
-#define DWC_MMC_TXMULTICASTPACKETS_GB 0x0740
-#define DWC_MMC_TXUNICASTPACKETS_GB 0x073C
-#define DWC_MMC_TX1024TOMAXOCTETS_GB 0x0738
-#define DWC_MMC_TX512TO1023OCTETS_GB 0x0734
-#define DWC_MMC_TX256TO511OCTETS_GB 0x0730
-#define DWC_MMC_TX128TO255OCTETS_GB 0x072C
-#define DWC_MMC_TX65TO127OCTETS_GB 0x0728
-#define DWC_MMC_TX64OCTETS_GB 0x0724
-#define DWC_MMC_TXMULTICASTPACKETS_G 0x0720
-#define DWC_MMC_TXBROADCASTPACKETS_G 0x071C
-#define DWC_MMC_TXPACKETCOUNT_GB 0x0718
-#define DWC_MMC_TXOCTETCOUNT_GB 0x0714
-
-#define DWC_MMC_RXLPITRANSCNTR 0x07F8
-#define DWC_MMC_RXLPIUSCNTR 0x07F4
-#define DWC_MMC_RXCTRLPACKETS_G 0x07E4
-#define DWC_MMC_RXRCVERROR 0x07E0
-#define DWC_MMC_RXWATCHDOG 0x07DC
-#define DWC_MMC_RXVLANPACKETS_GB 0x07D8
-#define DWC_MMC_RXFIFOOVERFLOW 0x07D4
-#define DWC_MMC_RXPAUSEPACKETS 0x07D0
-#define DWC_MMC_RXOUTOFRANGETYPE 0x07CC
-#define DWC_MMC_RXLENGTHERROR 0x07C8
-#define DWC_MMC_RXUNICASTPACKETS_G 0x07C4
-#define DWC_MMC_RX1024TOMAXOCTETS_GB 0x07C0
-#define DWC_MMC_RX512TO1023OCTETS_GB 0x07BC
-#define DWC_MMC_RX256TO511OCTETS_GB 0x07B8
-#define DWC_MMC_RX128TO255OCTETS_GB 0x07B4
-#define DWC_MMC_RX65TO127OCTETS_GB 0x07B0
-#define DWC_MMC_RX64OCTETS_GB 0x07AC
-#define DWC_MMC_RXOVERSIZE_G 0x07A8
-#define DWC_MMC_RXUNDERSIZE_G 0x07A4
-#define DWC_MMC_RXJABBERERROR 0x07A0
-#define DWC_MMC_RXRUNTERROR 0x079C
-#define DWC_MMC_RXALIGNMENTERROR 0x0798
-#define DWC_MMC_RXCRCERROR 0x0794
-#define DWC_MMC_RXMULTICASTPACKETS_G 0x0790
-#define DWC_MMC_RXBROADCASTPACKETS_G 0x078C
-#define DWC_MMC_RXOCTETCOUNT_G 0x0788
-#define DWC_MMC_RXOCTETCOUNT_GB 0x0784
-#define DWC_MMC_RXPACKETCOUNT_GB 0x0780
-
-static int debug = -1;
-module_param(debug, int, 0);
-MODULE_PARM_DESC(debug, "DWC_eth_qos debug level (0=none,...,16=all)");
-
-/* DMA ring descriptor. These are used as support descriptors for the HW DMA */
-struct ring_desc {
- struct sk_buff *skb;
- dma_addr_t mapping;
- size_t len;
-};
-
-/* DMA hardware descriptor */
-struct dwceqos_dma_desc {
- u32 des0;
- u32 des1;
- u32 des2;
- u32 des3;
-} ____cacheline_aligned;
-
-struct dwceqos_mmc_counters {
- __u64 txlpitranscntr;
- __u64 txpiuscntr;
- __u64 txoversize_g;
- __u64 txvlanpackets_g;
- __u64 txpausepackets;
- __u64 txexcessdef;
- __u64 txpacketcount_g;
- __u64 txoctetcount_g;
- __u64 txcarriererror;
- __u64 txexcesscol;
- __u64 txlatecol;
- __u64 txdeferred;
- __u64 txmulticol_g;
- __u64 txsinglecol_g;
- __u64 txunderflowerror;
- __u64 txbroadcastpackets_gb;
- __u64 txmulticastpackets_gb;
- __u64 txunicastpackets_gb;
- __u64 tx1024tomaxoctets_gb;
- __u64 tx512to1023octets_gb;
- __u64 tx256to511octets_gb;
- __u64 tx128to255octets_gb;
- __u64 tx65to127octets_gb;
- __u64 tx64octets_gb;
- __u64 txmulticastpackets_g;
- __u64 txbroadcastpackets_g;
- __u64 txpacketcount_gb;
- __u64 txoctetcount_gb;
-
- __u64 rxlpitranscntr;
- __u64 rxlpiuscntr;
- __u64 rxctrlpackets_g;
- __u64 rxrcverror;
- __u64 rxwatchdog;
- __u64 rxvlanpackets_gb;
- __u64 rxfifooverflow;
- __u64 rxpausepackets;
- __u64 rxoutofrangetype;
- __u64 rxlengtherror;
- __u64 rxunicastpackets_g;
- __u64 rx1024tomaxoctets_gb;
- __u64 rx512to1023octets_gb;
- __u64 rx256to511octets_gb;
- __u64 rx128to255octets_gb;
- __u64 rx65to127octets_gb;
- __u64 rx64octets_gb;
- __u64 rxoversize_g;
- __u64 rxundersize_g;
- __u64 rxjabbererror;
- __u64 rxrunterror;
- __u64 rxalignmenterror;
- __u64 rxcrcerror;
- __u64 rxmulticastpackets_g;
- __u64 rxbroadcastpackets_g;
- __u64 rxoctetcount_g;
- __u64 rxoctetcount_gb;
- __u64 rxpacketcount_gb;
-};
-
-/* Ethtool statistics */
-
-struct dwceqos_stat {
- const char stat_name[ETH_GSTRING_LEN];
- int offset;
-};
-
-#define STAT_ITEM(name, var) \
- {\
- name,\
- offsetof(struct dwceqos_mmc_counters, var),\
- }
-
-static const struct dwceqos_stat dwceqos_ethtool_stats[] = {
- STAT_ITEM("tx_bytes", txoctetcount_gb),
- STAT_ITEM("tx_packets", txpacketcount_gb),
- STAT_ITEM("tx_unicst_packets", txunicastpackets_gb),
- STAT_ITEM("tx_broadcast_packets", txbroadcastpackets_gb),
- STAT_ITEM("tx_multicast_packets", txmulticastpackets_gb),
- STAT_ITEM("tx_pause_packets", txpausepackets),
- STAT_ITEM("tx_up_to_64_byte_packets", tx64octets_gb),
- STAT_ITEM("tx_65_to_127_byte_packets", tx65to127octets_gb),
- STAT_ITEM("tx_128_to_255_byte_packets", tx128to255octets_gb),
- STAT_ITEM("tx_256_to_511_byte_packets", tx256to511octets_gb),
- STAT_ITEM("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
- STAT_ITEM("tx_1024_to_maxsize_packets", tx1024tomaxoctets_gb),
- STAT_ITEM("tx_underflow_errors", txunderflowerror),
- STAT_ITEM("tx_lpi_count", txlpitranscntr),
-
- STAT_ITEM("rx_bytes", rxoctetcount_gb),
- STAT_ITEM("rx_packets", rxpacketcount_gb),
- STAT_ITEM("rx_unicast_packets", rxunicastpackets_g),
- STAT_ITEM("rx_broadcast_packets", rxbroadcastpackets_g),
- STAT_ITEM("rx_multicast_packets", rxmulticastpackets_g),
- STAT_ITEM("rx_vlan_packets", rxvlanpackets_gb),
- STAT_ITEM("rx_pause_packets", rxpausepackets),
- STAT_ITEM("rx_up_to_64_byte_packets", rx64octets_gb),
- STAT_ITEM("rx_65_to_127_byte_packets", rx65to127octets_gb),
- STAT_ITEM("rx_128_to_255_byte_packets", rx128to255octets_gb),
- STAT_ITEM("rx_256_to_511_byte_packets", rx256to511octets_gb),
- STAT_ITEM("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
- STAT_ITEM("rx_1024_to_maxsize_packets", rx1024tomaxoctets_gb),
- STAT_ITEM("rx_fifo_overflow_errors", rxfifooverflow),
- STAT_ITEM("rx_oversize_packets", rxoversize_g),
- STAT_ITEM("rx_undersize_packets", rxundersize_g),
- STAT_ITEM("rx_jabbers", rxjabbererror),
- STAT_ITEM("rx_align_errors", rxalignmenterror),
- STAT_ITEM("rx_crc_errors", rxcrcerror),
- STAT_ITEM("rx_lpi_count", rxlpitranscntr),
-};
-
-/* Configuration of AXI bus parameters.
- * These values depend on the parameters set on the MAC core as well
- * as the AXI interconnect.
- */
-struct dwceqos_bus_cfg {
- /* Enable AXI low-power interface. */
- bool en_lpi;
- /* Limit on number of outstanding AXI write requests. */
- u32 write_requests;
- /* Limit on number of outstanding AXI read requests. */
- u32 read_requests;
- /* Bitmap of allowed AXI burst lengths, 4-256 beats. */
- u32 burst_map;
- /* DMA Programmable burst length*/
- u32 tx_pbl;
- u32 rx_pbl;
-};
-
-struct dwceqos_flowcontrol {
- int autoneg;
- int rx;
- int rx_current;
- int tx;
- int tx_current;
-};
-
-struct net_local {
- void __iomem *baseaddr;
- struct clk *phy_ref_clk;
- struct clk *apb_pclk;
-
- struct device_node *phy_node;
- struct net_device *ndev;
- struct platform_device *pdev;
-
- u32 msg_enable;
-
- struct tasklet_struct tx_bdreclaim_tasklet;
- struct workqueue_struct *txtimeout_handler_wq;
- struct work_struct txtimeout_reinit;
-
- phy_interface_t phy_interface;
- struct mii_bus *mii_bus;
-
- unsigned int link;
- unsigned int speed;
- unsigned int duplex;
-
- struct napi_struct napi;
-
- /* DMA Descriptor Areas */
- struct ring_desc *rx_skb;
- struct ring_desc *tx_skb;
-
- struct dwceqos_dma_desc *tx_descs;
- struct dwceqos_dma_desc *rx_descs;
-
- /* DMA Mapped Descriptor areas*/
- dma_addr_t tx_descs_addr;
- dma_addr_t rx_descs_addr;
- dma_addr_t tx_descs_tail_addr;
- dma_addr_t rx_descs_tail_addr;
-
- size_t tx_free;
- size_t tx_next;
- size_t rx_cur;
- size_t tx_cur;
-
- /* Spinlocks for accessing DMA Descriptors */
- spinlock_t tx_lock;
-
- /* Spinlock for register read-modify-writes. */
- spinlock_t hw_lock;
-
- u32 feature0;
- u32 feature1;
- u32 feature2;
-
- struct dwceqos_bus_cfg bus_cfg;
- bool en_tx_lpi_clockgating;
-
- int eee_enabled;
- int eee_active;
- int csr_val;
- u32 gso_size;
-
- struct dwceqos_mmc_counters mmc_counters;
- /* Protect the mmc_counter updates. */
- spinlock_t stats_lock;
- u32 mmc_rx_counters_mask;
- u32 mmc_tx_counters_mask;
-
- struct dwceqos_flowcontrol flowcontrol;
-
- /* Tracks the intermediate state of phy started but hardware
- * init not finished yet.
- */
- bool phy_defer;
-};
-
-static void dwceqos_read_mmc_counters(struct net_local *lp, u32 rx_mask,
- u32 tx_mask);
-
-static void dwceqos_set_umac_addr(struct net_local *lp, unsigned char *addr,
- unsigned int reg_n);
-static int dwceqos_stop(struct net_device *ndev);
-static int dwceqos_open(struct net_device *ndev);
-static void dwceqos_tx_poll_demand(struct net_local *lp);
-
-static void dwceqos_set_rx_flowcontrol(struct net_local *lp, bool enable);
-static void dwceqos_set_tx_flowcontrol(struct net_local *lp, bool enable);
-
-static void dwceqos_reset_state(struct net_local *lp);
-
-#define dwceqos_read(lp, reg) \
- readl_relaxed(((void __iomem *)((lp)->baseaddr)) + (reg))
-#define dwceqos_write(lp, reg, val) \
- writel_relaxed((val), ((void __iomem *)((lp)->baseaddr)) + (reg))
-
-static void dwceqos_reset_state(struct net_local *lp)
-{
- lp->link = 0;
- lp->speed = 0;
- lp->duplex = DUPLEX_UNKNOWN;
- lp->flowcontrol.rx_current = 0;
- lp->flowcontrol.tx_current = 0;
- lp->eee_active = 0;
- lp->eee_enabled = 0;
-}
-
-static void print_descriptor(struct net_local *lp, int index, int tx)
-{
- struct dwceqos_dma_desc *dd;
-
- if (tx)
- dd = (struct dwceqos_dma_desc *)&lp->tx_descs[index];
- else
- dd = (struct dwceqos_dma_desc *)&lp->rx_descs[index];
-
- pr_info("%s DMA Descriptor #%d@%p Contents:\n", tx ? "TX" : "RX",
- index, dd);
- pr_info("0x%08x 0x%08x 0x%08x 0x%08x\n", dd->des0, dd->des1, dd->des2,
- dd->des3);
-}
-
-static void print_status(struct net_local *lp)
-{
- size_t desci, i;
-
- pr_info("tx_free %zu, tx_cur %zu, tx_next %zu\n", lp->tx_free,
- lp->tx_cur, lp->tx_next);
-
- print_descriptor(lp, lp->rx_cur, 0);
-
- for (desci = (lp->tx_cur - 10) % DWCEQOS_TX_DCNT, i = 0;
- i < DWCEQOS_TX_DCNT;
- ++i) {
- print_descriptor(lp, desci, 1);
- desci = (desci + 1) % DWCEQOS_TX_DCNT;
- }
-
- pr_info("DMA_Debug_Status0: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_DMA_DEBUG_ST0));
- pr_info("DMA_CH0_Status: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_DMA_IS));
- pr_info("DMA_CH0_Current_App_TxDesc: 0x%08x\n",
- dwceqos_read(lp, 0x1144));
- pr_info("DMA_CH0_Current_App_TxBuff: 0x%08x\n",
- dwceqos_read(lp, 0x1154));
- pr_info("MTL_Debug_Status: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_MTL_DEBUG_ST));
- pr_info("MTL_TXQ0_Debug_Status: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_MTL_TXQ0_DEBUG_ST));
- pr_info("MTL_RXQ0_Debug_Status: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_DEBUG_ST));
- pr_info("Current TX DMA: 0x%08x, RX DMA: 0x%08x\n",
- dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_CUR_TXDESC),
- dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_CUR_RXDESC));
-}
-
-static void dwceqos_mdio_set_csr(struct net_local *lp)
-{
- int rate = clk_get_rate(lp->apb_pclk);
-
- if (rate <= 20000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_20;
- else if (rate <= 35000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_35;
- else if (rate <= 60000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_60;
- else if (rate <= 100000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_100;
- else if (rate <= 150000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_150;
- else if (rate <= 250000000)
- lp->csr_val = DWCEQOS_MAC_MDIO_ADDR_CR_250;
-}
-
-/* Simple MDIO functions implementing mii_bus */
-static int dwceqos_mdio_read(struct mii_bus *bus, int mii_id, int phyreg)
-{
- struct net_local *lp = bus->priv;
- u32 regval;
- int i;
- int data;
-
- regval = DWCEQOS_MDIO_PHYADDR(mii_id) |
- DWCEQOS_MDIO_PHYREG(phyreg) |
- DWCEQOS_MAC_MDIO_ADDR_CR(lp->csr_val) |
- DWCEQOS_MAC_MDIO_ADDR_GB |
- DWCEQOS_MAC_MDIO_ADDR_GOC_READ;
- dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval);
-
- for (i = 0; i < 5; ++i) {
- usleep_range(64, 128);
- if (!(dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_ADDR) &
- DWCEQOS_MAC_MDIO_ADDR_GB))
- break;
- }
-
- data = dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_DATA);
- if (i == 5) {
- netdev_warn(lp->ndev, "MDIO read timed out\n");
- data = 0xffff;
- }
-
- return data & 0xffff;
-}
-
-static int dwceqos_mdio_write(struct mii_bus *bus, int mii_id, int phyreg,
- u16 value)
-{
- struct net_local *lp = bus->priv;
- u32 regval;
- int i;
-
- dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_DATA, value);
-
- regval = DWCEQOS_MDIO_PHYADDR(mii_id) |
- DWCEQOS_MDIO_PHYREG(phyreg) |
- DWCEQOS_MAC_MDIO_ADDR_CR(lp->csr_val) |
- DWCEQOS_MAC_MDIO_ADDR_GB |
- DWCEQOS_MAC_MDIO_ADDR_GOC_WRITE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval);
-
- for (i = 0; i < 5; ++i) {
- usleep_range(64, 128);
- if (!(dwceqos_read(lp, REG_DWCEQOS_MAC_MDIO_ADDR) &
- DWCEQOS_MAC_MDIO_ADDR_GB))
- break;
- }
- if (i == 5)
- netdev_warn(lp->ndev, "MDIO write timed out\n");
- return 0;
-}
-
-static int dwceqos_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
-{
- struct net_local *lp = netdev_priv(ndev);
- struct phy_device *phydev = ndev->phydev;
-
- if (!netif_running(ndev))
- return -EINVAL;
-
- if (!phydev)
- return -ENODEV;
-
- switch (cmd) {
- case SIOCGMIIPHY:
- case SIOCGMIIREG:
- case SIOCSMIIREG:
- return phy_mii_ioctl(phydev, rq, cmd);
- default:
- dev_info(&lp->pdev->dev, "ioctl %X not implemented.\n", cmd);
- return -EOPNOTSUPP;
- }
-}
-
-static void dwceqos_link_down(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
-
- /* Indicate link down to the LPI state machine */
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- regval &= ~DWCEQOS_MAC_LPI_CTRL_STATUS_PLS;
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_link_up(struct net_local *lp)
-{
- struct net_device *ndev = lp->ndev;
- u32 regval;
- unsigned long flags;
-
- /* Indicate link up to the LPI state machine */
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- regval |= DWCEQOS_MAC_LPI_CTRL_STATUS_PLS;
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-
- lp->eee_active = !phy_init_eee(ndev->phydev, 0);
-
- /* Check for changed EEE capability */
- if (!lp->eee_active && lp->eee_enabled) {
- lp->eee_enabled = 0;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- regval &= ~DWCEQOS_LPI_CTRL_ENABLE_EEE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
- }
-}
-
-static void dwceqos_set_speed(struct net_local *lp)
-{
- struct net_device *ndev = lp->ndev;
- struct phy_device *phydev = ndev->phydev;
- u32 regval;
-
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
- regval &= ~(DWCEQOS_MAC_CFG_PS | DWCEQOS_MAC_CFG_FES |
- DWCEQOS_MAC_CFG_DM);
-
- if (phydev->duplex)
- regval |= DWCEQOS_MAC_CFG_DM;
- if (phydev->speed == SPEED_10) {
- regval |= DWCEQOS_MAC_CFG_PS;
- } else if (phydev->speed == SPEED_100) {
- regval |= DWCEQOS_MAC_CFG_PS |
- DWCEQOS_MAC_CFG_FES;
- } else if (phydev->speed != SPEED_1000) {
- netdev_err(lp->ndev,
- "unknown PHY speed %d\n",
- phydev->speed);
- return;
- }
-
- dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, regval);
-}
-
-static void dwceqos_adjust_link(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
- struct phy_device *phydev = ndev->phydev;
- int status_change = 0;
-
- if (lp->phy_defer)
- return;
-
- if (phydev->link) {
- if ((lp->speed != phydev->speed) ||
- (lp->duplex != phydev->duplex)) {
- dwceqos_set_speed(lp);
-
- lp->speed = phydev->speed;
- lp->duplex = phydev->duplex;
- status_change = 1;
- }
-
- if (lp->flowcontrol.autoneg) {
- lp->flowcontrol.rx = phydev->pause ||
- phydev->asym_pause;
- lp->flowcontrol.tx = phydev->pause ||
- phydev->asym_pause;
- }
-
- if (lp->flowcontrol.rx != lp->flowcontrol.rx_current) {
- if (netif_msg_link(lp))
- netdev_dbg(ndev, "set rx flow to %d\n",
- lp->flowcontrol.rx);
- dwceqos_set_rx_flowcontrol(lp, lp->flowcontrol.rx);
- lp->flowcontrol.rx_current = lp->flowcontrol.rx;
- }
- if (lp->flowcontrol.tx != lp->flowcontrol.tx_current) {
- if (netif_msg_link(lp))
- netdev_dbg(ndev, "set tx flow to %d\n",
- lp->flowcontrol.tx);
- dwceqos_set_tx_flowcontrol(lp, lp->flowcontrol.tx);
- lp->flowcontrol.tx_current = lp->flowcontrol.tx;
- }
- }
-
- if (phydev->link != lp->link) {
- lp->link = phydev->link;
- status_change = 1;
- }
-
- if (status_change) {
- if (phydev->link) {
- netif_trans_update(lp->ndev);
- dwceqos_link_up(lp);
- } else {
- dwceqos_link_down(lp);
- }
- phy_print_status(phydev);
- }
-}
-
-static int dwceqos_mii_probe(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
- struct phy_device *phydev = NULL;
-
- if (lp->phy_node) {
- phydev = of_phy_connect(lp->ndev,
- lp->phy_node,
- &dwceqos_adjust_link,
- 0,
- lp->phy_interface);
-
- if (!phydev) {
- netdev_err(ndev, "no PHY found\n");
- return -1;
- }
- } else {
- netdev_err(ndev, "no PHY configured\n");
- return -ENODEV;
- }
-
- if (netif_msg_probe(lp))
- phy_attached_info(phydev);
-
- phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
- SUPPORTED_Asym_Pause;
-
- lp->link = 0;
- lp->speed = 0;
- lp->duplex = DUPLEX_UNKNOWN;
- lp->flowcontrol.autoneg = AUTONEG_ENABLE;
-
- return 0;
-}
-
-static void dwceqos_alloc_rxring_desc(struct net_local *lp, int index)
-{
- struct sk_buff *new_skb;
- dma_addr_t new_skb_baddr = 0;
-
- new_skb = netdev_alloc_skb(lp->ndev, DWCEQOS_RX_BUF_SIZE);
- if (!new_skb) {
- netdev_err(lp->ndev, "alloc_skb error for desc %d\n", index);
- goto err_out;
- }
-
- new_skb_baddr = dma_map_single(lp->ndev->dev.parent,
- new_skb->data, DWCEQOS_RX_BUF_SIZE,
- DMA_FROM_DEVICE);
- if (dma_mapping_error(lp->ndev->dev.parent, new_skb_baddr)) {
- netdev_err(lp->ndev, "DMA map error\n");
- dev_kfree_skb(new_skb);
- new_skb = NULL;
- goto err_out;
- }
-
- lp->rx_descs[index].des0 = new_skb_baddr;
- lp->rx_descs[index].des1 = 0;
- lp->rx_descs[index].des2 = 0;
- lp->rx_descs[index].des3 = DWCEQOS_DMA_RDES3_INTE |
- DWCEQOS_DMA_RDES3_BUF1V |
- DWCEQOS_DMA_RDES3_OWN;
-
- lp->rx_skb[index].mapping = new_skb_baddr;
- lp->rx_skb[index].len = DWCEQOS_RX_BUF_SIZE;
-
-err_out:
- lp->rx_skb[index].skb = new_skb;
-}
-
-static void dwceqos_clean_rings(struct net_local *lp)
-{
- int i;
-
- if (lp->rx_skb) {
- for (i = 0; i < DWCEQOS_RX_DCNT; i++) {
- if (lp->rx_skb[i].skb) {
- dma_unmap_single(lp->ndev->dev.parent,
- lp->rx_skb[i].mapping,
- lp->rx_skb[i].len,
- DMA_FROM_DEVICE);
-
- dev_kfree_skb(lp->rx_skb[i].skb);
- lp->rx_skb[i].skb = NULL;
- lp->rx_skb[i].mapping = 0;
- }
- }
- }
-
- if (lp->tx_skb) {
- for (i = 0; i < DWCEQOS_TX_DCNT; i++) {
- if (lp->tx_skb[i].skb) {
- dev_kfree_skb(lp->tx_skb[i].skb);
- lp->tx_skb[i].skb = NULL;
- }
- if (lp->tx_skb[i].mapping) {
- dma_unmap_single(lp->ndev->dev.parent,
- lp->tx_skb[i].mapping,
- lp->tx_skb[i].len,
- DMA_TO_DEVICE);
- lp->tx_skb[i].mapping = 0;
- }
- }
- }
-}
-
-static void dwceqos_descriptor_free(struct net_local *lp)
-{
- int size;
-
- dwceqos_clean_rings(lp);
-
- kfree(lp->tx_skb);
- lp->tx_skb = NULL;
- kfree(lp->rx_skb);
- lp->rx_skb = NULL;
-
- size = DWCEQOS_RX_DCNT * sizeof(struct dwceqos_dma_desc);
- if (lp->rx_descs) {
- dma_free_coherent(lp->ndev->dev.parent, size,
- (void *)(lp->rx_descs), lp->rx_descs_addr);
- lp->rx_descs = NULL;
- }
-
- size = DWCEQOS_TX_DCNT * sizeof(struct dwceqos_dma_desc);
- if (lp->tx_descs) {
- dma_free_coherent(lp->ndev->dev.parent, size,
- (void *)(lp->tx_descs), lp->tx_descs_addr);
- lp->tx_descs = NULL;
- }
-}
-
-static int dwceqos_descriptor_init(struct net_local *lp)
-{
- int size;
- u32 i;
-
- lp->gso_size = 0;
-
- lp->tx_skb = NULL;
- lp->rx_skb = NULL;
- lp->rx_descs = NULL;
- lp->tx_descs = NULL;
-
- /* Reset the DMA indexes */
- lp->rx_cur = 0;
- lp->tx_cur = 0;
- lp->tx_next = 0;
- lp->tx_free = DWCEQOS_TX_DCNT;
-
- /* Allocate Ring descriptors */
- size = DWCEQOS_RX_DCNT * sizeof(struct ring_desc);
- lp->rx_skb = kzalloc(size, GFP_KERNEL);
- if (!lp->rx_skb)
- goto err_out;
-
- size = DWCEQOS_TX_DCNT * sizeof(struct ring_desc);
- lp->tx_skb = kzalloc(size, GFP_KERNEL);
- if (!lp->tx_skb)
- goto err_out;
-
- /* Allocate DMA descriptors */
- size = DWCEQOS_RX_DCNT * sizeof(struct dwceqos_dma_desc);
- lp->rx_descs = dma_alloc_coherent(lp->ndev->dev.parent, size,
- &lp->rx_descs_addr, GFP_KERNEL);
- if (!lp->rx_descs)
- goto err_out;
- lp->rx_descs_tail_addr = lp->rx_descs_addr +
- sizeof(struct dwceqos_dma_desc) * DWCEQOS_RX_DCNT;
-
- size = DWCEQOS_TX_DCNT * sizeof(struct dwceqos_dma_desc);
- lp->tx_descs = dma_alloc_coherent(lp->ndev->dev.parent, size,
- &lp->tx_descs_addr, GFP_KERNEL);
- if (!lp->tx_descs)
- goto err_out;
- lp->tx_descs_tail_addr = lp->tx_descs_addr +
- sizeof(struct dwceqos_dma_desc) * DWCEQOS_TX_DCNT;
-
- /* Initialize RX Ring Descriptors and buffers */
- for (i = 0; i < DWCEQOS_RX_DCNT; ++i) {
- dwceqos_alloc_rxring_desc(lp, i);
- if (!(lp->rx_skb[lp->rx_cur].skb))
- goto err_out;
- }
-
- /* Initialize TX Descriptors */
- for (i = 0; i < DWCEQOS_TX_DCNT; ++i) {
- lp->tx_descs[i].des0 = 0;
- lp->tx_descs[i].des1 = 0;
- lp->tx_descs[i].des2 = 0;
- lp->tx_descs[i].des3 = 0;
- }
-
- /* Make descriptor writes visible to the DMA. */
- wmb();
-
- return 0;
-
-err_out:
- dwceqos_descriptor_free(lp);
- return -ENOMEM;
-}
-
-static int dwceqos_packet_avail(struct net_local *lp)
-{
- return !(lp->rx_descs[lp->rx_cur].des3 & DWCEQOS_DMA_RDES3_OWN);
-}
-
-static void dwceqos_get_hwfeatures(struct net_local *lp)
-{
- lp->feature0 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE0);
- lp->feature1 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE1);
- lp->feature2 = dwceqos_read(lp, REG_DWCEQOS_MAC_HW_FEATURE2);
-}
-
-static void dwceqos_dma_enable_txirq(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
- regval |= DWCEQOS_DMA_CH0_IE_TIE;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_dma_disable_txirq(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
- regval &= ~DWCEQOS_DMA_CH0_IE_TIE;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_dma_enable_rxirq(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
- regval |= DWCEQOS_DMA_CH0_IE_RIE;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_dma_disable_rxirq(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_IE);
- regval &= ~DWCEQOS_DMA_CH0_IE_RIE;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_enable_mmc_interrupt(struct net_local *lp)
-{
- dwceqos_write(lp, REG_DWCEQOS_MMC_RXIRQMASK, 0);
- dwceqos_write(lp, REG_DWCEQOS_MMC_TXIRQMASK, 0);
-}
-
-static int dwceqos_mii_init(struct net_local *lp)
-{
- int ret = -ENXIO;
- struct resource res;
- struct device_node *mdionode;
-
- mdionode = of_get_child_by_name(lp->pdev->dev.of_node, "mdio");
-
- if (!mdionode)
- return 0;
-
- lp->mii_bus = mdiobus_alloc();
- if (!lp->mii_bus) {
- ret = -ENOMEM;
- goto err_out;
- }
-
- lp->mii_bus->name = "DWCEQOS MII bus";
- lp->mii_bus->read = &dwceqos_mdio_read;
- lp->mii_bus->write = &dwceqos_mdio_write;
- lp->mii_bus->priv = lp;
- lp->mii_bus->parent = &lp->pdev->dev;
-
- of_address_to_resource(lp->pdev->dev.of_node, 0, &res);
- snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%.8llx",
- (unsigned long long)res.start);
- if (of_mdiobus_register(lp->mii_bus, mdionode))
- goto err_out_free_mdiobus;
-
- return 0;
-
-err_out_free_mdiobus:
- mdiobus_free(lp->mii_bus);
-err_out:
- of_node_put(mdionode);
- return ret;
-}
-
-/* DMA reset. When issued also resets all MTL and MAC registers as well */
-static void dwceqos_reset_hw(struct net_local *lp)
-{
- /* Wait (at most) 0.5 seconds for DMA reset*/
- int i = 5000;
- u32 reg;
-
- /* Force gigabit to guarantee a TX clock for GMII. */
- reg = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
- reg &= ~(DWCEQOS_MAC_CFG_PS | DWCEQOS_MAC_CFG_FES);
- reg |= DWCEQOS_MAC_CFG_DM;
- dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, reg);
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_MODE, DWCEQOS_DMA_MODE_SWR);
-
- do {
- udelay(100);
- i--;
- reg = dwceqos_read(lp, REG_DWCEQOS_DMA_MODE);
- } while ((reg & DWCEQOS_DMA_MODE_SWR) && i);
- /* We might experience a timeout if the chip clock mux is broken */
- if (!i)
- netdev_err(lp->ndev, "DMA reset timed out!\n");
-}
-
-static void dwceqos_fatal_bus_error(struct net_local *lp, u32 dma_status)
-{
- if (dma_status & DWCEQOS_DMA_CH0_IS_TEB) {
- netdev_err(lp->ndev, "txdma bus error %s %s (status=%08x)\n",
- dma_status & DWCEQOS_DMA_CH0_IS_TX_ERR_READ ?
- "read" : "write",
- dma_status & DWCEQOS_DMA_CH0_IS_TX_ERR_DESCR ?
- "descr" : "data",
- dma_status);
-
- print_status(lp);
- }
- if (dma_status & DWCEQOS_DMA_CH0_IS_REB) {
- netdev_err(lp->ndev, "rxdma bus error %s %s (status=%08x)\n",
- dma_status & DWCEQOS_DMA_CH0_IS_RX_ERR_READ ?
- "read" : "write",
- dma_status & DWCEQOS_DMA_CH0_IS_RX_ERR_DESCR ?
- "descr" : "data",
- dma_status);
-
- print_status(lp);
- }
-}
-
-static void dwceqos_mmc_interrupt(struct net_local *lp)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&lp->stats_lock, flags);
-
- /* A latched mmc interrupt can not be masked, we must read
- * all the counters with an interrupt pending.
- */
- dwceqos_read_mmc_counters(lp,
- dwceqos_read(lp, REG_DWCEQOS_MMC_RXIRQ),
- dwceqos_read(lp, REG_DWCEQOS_MMC_TXIRQ));
-
- spin_unlock_irqrestore(&lp->stats_lock, flags);
-}
-
-static void dwceqos_mac_interrupt(struct net_local *lp)
-{
- u32 cause;
-
- cause = dwceqos_read(lp, REG_DWCEQOS_MAC_IS);
-
- if (cause & DWCEQOS_MAC_IS_MMC_INT)
- dwceqos_mmc_interrupt(lp);
-}
-
-static irqreturn_t dwceqos_interrupt(int irq, void *dev_id)
-{
- struct net_device *ndev = dev_id;
- struct net_local *lp = netdev_priv(ndev);
-
- u32 cause;
- u32 dma_status;
- irqreturn_t ret = IRQ_NONE;
-
- cause = dwceqos_read(lp, REG_DWCEQOS_DMA_IS);
- /* DMA Channel 0 Interrupt */
- if (cause & DWCEQOS_DMA_IS_DC0IS) {
- dma_status = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_STA);
-
- /* Transmit Interrupt */
- if (dma_status & DWCEQOS_DMA_CH0_IS_TI) {
- tasklet_schedule(&lp->tx_bdreclaim_tasklet);
- dwceqos_dma_disable_txirq(lp);
- }
-
- /* Receive Interrupt */
- if (dma_status & DWCEQOS_DMA_CH0_IS_RI) {
- /* Disable RX IRQs */
- dwceqos_dma_disable_rxirq(lp);
- napi_schedule(&lp->napi);
- }
-
- /* Fatal Bus Error interrupt */
- if (unlikely(dma_status & DWCEQOS_DMA_CH0_IS_FBE)) {
- dwceqos_fatal_bus_error(lp, dma_status);
-
- /* errata 9000831707 */
- dma_status |= DWCEQOS_DMA_CH0_IS_TEB |
- DWCEQOS_DMA_CH0_IS_REB;
- }
-
- /* Ack all DMA Channel 0 IRQs */
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_STA, dma_status);
- ret = IRQ_HANDLED;
- }
-
- if (cause & DWCEQOS_DMA_IS_MTLIS) {
- u32 val = dwceqos_read(lp, REG_DWCEQOS_MTL_Q0_ISCTRL);
-
- dwceqos_write(lp, REG_DWCEQOS_MTL_Q0_ISCTRL, val);
- ret = IRQ_HANDLED;
- }
-
- if (cause & DWCEQOS_DMA_IS_MACIS) {
- dwceqos_mac_interrupt(lp);
- ret = IRQ_HANDLED;
- }
- return ret;
-}
-
-static void dwceqos_set_rx_flowcontrol(struct net_local *lp, bool enable)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
-
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_RX_FLOW_CTRL);
- if (enable)
- regval |= DWCEQOS_MAC_RX_FLOW_CTRL_RFE;
- else
- regval &= ~DWCEQOS_MAC_RX_FLOW_CTRL_RFE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_RX_FLOW_CTRL, regval);
-
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_set_tx_flowcontrol(struct net_local *lp, bool enable)
-{
- u32 regval;
- unsigned long flags;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
-
- /* MTL flow control */
- regval = dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_OPER);
- if (enable)
- regval |= DWCEQOS_MTL_RXQ_EHFC;
- else
- regval &= ~DWCEQOS_MTL_RXQ_EHFC;
-
- dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
-
- /* MAC flow control */
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW);
- if (enable)
- regval |= DWCEQOS_MAC_Q0_TX_FLOW_TFE;
- else
- regval &= ~DWCEQOS_MAC_Q0_TX_FLOW_TFE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW, regval);
-
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_configure_flow_control(struct net_local *lp)
-{
- u32 regval;
- unsigned long flags;
- int RQS, RFD, RFA;
-
- spin_lock_irqsave(&lp->hw_lock, flags);
-
- regval = dwceqos_read(lp, REG_DWCEQOS_MTL_RXQ0_OPER);
-
- /* The queue size is in units of 256 bytes. We want 512 bytes units for
- * the threshold fields.
- */
- RQS = ((regval >> 20) & 0x3FF) + 1;
- RQS /= 2;
-
- /* The thresholds are relative to a full queue, with a bias
- * of 1 KiByte below full.
- */
- RFD = RQS / 2 - 2;
- RFA = RQS / 8 - 2;
-
- regval = (regval & 0xFFF000FF) | (RFD << 14) | (RFA << 8);
-
- if (RFD >= 0 && RFA >= 0) {
- dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
- } else {
- netdev_warn(lp->ndev,
- "FIFO too small for flow control.");
- }
-
- regval = DWCEQOS_MAC_Q0_TX_FLOW_PT(256) |
- DWCEQOS_MAC_Q0_TX_FLOW_PLT_4_SLOTS;
-
- dwceqos_write(lp, REG_DWCEQOS_MAC_Q0_TX_FLOW, regval);
-
- spin_unlock_irqrestore(&lp->hw_lock, flags);
-}
-
-static void dwceqos_configure_clock(struct net_local *lp)
-{
- unsigned long rate_mhz = clk_get_rate(lp->apb_pclk) / 1000000;
-
- BUG_ON(!rate_mhz);
-
- dwceqos_write(lp,
- REG_DWCEQOS_MAC_1US_TIC_COUNTER,
- DWCEQOS_MAC_1US_TIC_COUNTER_VAL(rate_mhz - 1));
-}
-
-static void dwceqos_configure_bus(struct net_local *lp)
-{
- u32 sysbus_reg;
-
- /* N.B. We do not support the Fixed Burst mode because it
- * opens a race window by making HW access to DMA descriptors
- * non-atomic.
- */
-
- sysbus_reg = DWCEQOS_DMA_SYSBUS_MODE_AAL;
-
- if (lp->bus_cfg.en_lpi)
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_EN_LPI;
-
- if (lp->bus_cfg.burst_map)
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_BURST(
- lp->bus_cfg.burst_map);
- else
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_BURST(
- DWCEQOS_DMA_SYSBUS_MODE_BURST_DEFAULT);
-
- if (lp->bus_cfg.read_requests)
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(
- lp->bus_cfg.read_requests - 1);
- else
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT(
- DWCEQOS_DMA_SYSBUS_MODE_RD_OSR_LIMIT_DEFAULT);
-
- if (lp->bus_cfg.write_requests)
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(
- lp->bus_cfg.write_requests - 1);
- else
- sysbus_reg |= DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT(
- DWCEQOS_DMA_SYSBUS_MODE_WR_OSR_LIMIT_DEFAULT);
-
- if (netif_msg_hw(lp))
- netdev_dbg(lp->ndev, "SysbusMode %#X\n", sysbus_reg);
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_SYSBUS_MODE, sysbus_reg);
-}
-
-static void dwceqos_init_hw(struct net_local *lp)
-{
- struct net_device *ndev = lp->ndev;
- u32 regval;
- u32 buswidth;
- u32 dma_skip;
-
- /* Software reset */
- dwceqos_reset_hw(lp);
-
- dwceqos_configure_bus(lp);
-
- /* Probe data bus width, 32/64/128 bits. */
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL, 0xF);
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL);
- buswidth = (regval ^ 0xF) + 1;
-
- /* Cache-align dma descriptors. */
- dma_skip = (sizeof(struct dwceqos_dma_desc) - 16) / buswidth;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_CTRL,
- DWCEQOS_DMA_CH_CTRL_DSL(dma_skip) |
- DWCEQOS_DMA_CH_CTRL_PBLX8);
-
- /* Initialize DMA Channel 0 */
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_LEN, DWCEQOS_TX_DCNT - 1);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_LEN, DWCEQOS_RX_DCNT - 1);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_LIST,
- (u32)lp->tx_descs_addr);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_LIST,
- (u32)lp->rx_descs_addr);
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL,
- lp->tx_descs_tail_addr);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_TAIL,
- lp->rx_descs_tail_addr);
-
- if (lp->bus_cfg.tx_pbl)
- regval = DWCEQOS_DMA_CH_CTRL_PBL(lp->bus_cfg.tx_pbl);
- else
- regval = DWCEQOS_DMA_CH_CTRL_PBL(2);
-
- /* Enable TSO if the HW support it */
- if (lp->feature1 & DWCEQOS_MAC_HW_FEATURE1_TSOEN)
- regval |= DWCEQOS_DMA_CH_TX_TSE;
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL, regval);
-
- if (lp->bus_cfg.rx_pbl)
- regval = DWCEQOS_DMA_CH_CTRL_PBL(lp->bus_cfg.rx_pbl);
- else
- regval = DWCEQOS_DMA_CH_CTRL_PBL(2);
-
- regval |= DWCEQOS_DMA_CH_RX_CTRL_BUFSIZE(DWCEQOS_DWCEQOS_RX_BUF_SIZE);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RX_CTRL, regval);
-
- regval |= DWCEQOS_DMA_CH_CTRL_START;
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RX_CTRL, regval);
-
- /* Initialize MTL Queues */
- regval = DWCEQOS_MTL_SCHALG_STRICT;
- dwceqos_write(lp, REG_DWCEQOS_MTL_OPER, regval);
-
- regval = DWCEQOS_MTL_TXQ_SIZE(
- DWCEQOS_MAC_HW_FEATURE1_TXFIFOSIZE(lp->feature1)) |
- DWCEQOS_MTL_TXQ_TXQEN | DWCEQOS_MTL_TXQ_TSF |
- DWCEQOS_MTL_TXQ_TTC512;
- dwceqos_write(lp, REG_DWCEQOS_MTL_TXQ0_OPER, regval);
-
- regval = DWCEQOS_MTL_RXQ_SIZE(
- DWCEQOS_MAC_HW_FEATURE1_RXFIFOSIZE(lp->feature1)) |
- DWCEQOS_MTL_RXQ_FUP | DWCEQOS_MTL_RXQ_FEP | DWCEQOS_MTL_RXQ_RSF;
- dwceqos_write(lp, REG_DWCEQOS_MTL_RXQ0_OPER, regval);
-
- dwceqos_configure_flow_control(lp);
-
- /* Initialize MAC */
- dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
-
- lp->eee_enabled = 0;
-
- dwceqos_configure_clock(lp);
-
- /* MMC counters */
-
- /* probe implemented counters */
- dwceqos_write(lp, REG_DWCEQOS_MMC_RXIRQMASK, ~0u);
- dwceqos_write(lp, REG_DWCEQOS_MMC_TXIRQMASK, ~0u);
- lp->mmc_rx_counters_mask = dwceqos_read(lp, REG_DWCEQOS_MMC_RXIRQMASK);
- lp->mmc_tx_counters_mask = dwceqos_read(lp, REG_DWCEQOS_MMC_TXIRQMASK);
-
- dwceqos_write(lp, REG_DWCEQOS_MMC_CTRL, DWCEQOS_MMC_CTRL_CNTRST |
- DWCEQOS_MMC_CTRL_RSTONRD);
- dwceqos_enable_mmc_interrupt(lp);
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE, 0);
- dwceqos_write(lp, REG_DWCEQOS_MAC_IE, 0);
-
- dwceqos_write(lp, REG_DWCEQOS_MAC_CFG, DWCEQOS_MAC_CFG_IPC |
- DWCEQOS_MAC_CFG_DM | DWCEQOS_MAC_CFG_TE | DWCEQOS_MAC_CFG_RE);
-
- /* Start TX DMA */
- regval = dwceqos_read(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL);
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TX_CTRL,
- regval | DWCEQOS_DMA_CH_CTRL_START);
-
- /* Enable MAC TX/RX */
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_CFG);
- dwceqos_write(lp, REG_DWCEQOS_MAC_CFG,
- regval | DWCEQOS_MAC_CFG_TE | DWCEQOS_MAC_CFG_RE);
-
- lp->phy_defer = false;
- mutex_lock(&ndev->phydev->lock);
- phy_read_status(ndev->phydev);
- dwceqos_adjust_link(lp->ndev);
- mutex_unlock(&ndev->phydev->lock);
-}
-
-static void dwceqos_tx_reclaim(unsigned long data)
-{
- struct net_device *ndev = (struct net_device *)data;
- struct net_local *lp = netdev_priv(ndev);
- unsigned int tx_bytes = 0;
- unsigned int tx_packets = 0;
-
- spin_lock(&lp->tx_lock);
-
- while (lp->tx_free < DWCEQOS_TX_DCNT) {
- struct dwceqos_dma_desc *dd = &lp->tx_descs[lp->tx_cur];
- struct ring_desc *rd = &lp->tx_skb[lp->tx_cur];
-
- /* Descriptor still being held by DMA ? */
- if (dd->des3 & DWCEQOS_DMA_TDES3_OWN)
- break;
-
- if (rd->mapping)
- dma_unmap_single(ndev->dev.parent, rd->mapping, rd->len,
- DMA_TO_DEVICE);
-
- if (unlikely(rd->skb)) {
- ++tx_packets;
- tx_bytes += rd->skb->len;
- dev_consume_skb_any(rd->skb);
- }
-
- rd->skb = NULL;
- rd->mapping = 0;
- lp->tx_free++;
- lp->tx_cur = (lp->tx_cur + 1) % DWCEQOS_TX_DCNT;
-
- if ((dd->des3 & DWCEQOS_DMA_TDES3_LD) &&
- (dd->des3 & DWCEQOS_DMA_RDES3_ES)) {
- if (netif_msg_tx_err(lp))
- netdev_err(ndev, "TX Error, TDES3 = 0x%x\n",
- dd->des3);
- if (netif_msg_hw(lp))
- print_status(lp);
- }
- }
- spin_unlock(&lp->tx_lock);
-
- netdev_completed_queue(ndev, tx_packets, tx_bytes);
-
- dwceqos_dma_enable_txirq(lp);
- netif_wake_queue(ndev);
-}
-
-static int dwceqos_rx(struct net_local *lp, int budget)
-{
- struct sk_buff *skb;
- u32 tot_size = 0;
- unsigned int n_packets = 0;
- unsigned int n_descs = 0;
- u32 len;
-
- struct dwceqos_dma_desc *dd;
- struct sk_buff *new_skb;
- dma_addr_t new_skb_baddr = 0;
-
- while (n_descs < budget) {
- if (!dwceqos_packet_avail(lp))
- break;
-
- new_skb = netdev_alloc_skb(lp->ndev, DWCEQOS_RX_BUF_SIZE);
- if (!new_skb) {
- netdev_err(lp->ndev, "no memory for new sk_buff\n");
- break;
- }
-
- /* Get dma handle of skb->data */
- new_skb_baddr = (u32)dma_map_single(lp->ndev->dev.parent,
- new_skb->data,
- DWCEQOS_RX_BUF_SIZE,
- DMA_FROM_DEVICE);
- if (dma_mapping_error(lp->ndev->dev.parent, new_skb_baddr)) {
- netdev_err(lp->ndev, "DMA map error\n");
- dev_kfree_skb(new_skb);
- break;
- }
-
- /* Read descriptor data after reading owner bit. */
- dma_rmb();
-
- dd = &lp->rx_descs[lp->rx_cur];
- len = DWCEQOS_DMA_RDES3_PL(dd->des3);
- skb = lp->rx_skb[lp->rx_cur].skb;
-
- /* Unmap old buffer */
- dma_unmap_single(lp->ndev->dev.parent,
- lp->rx_skb[lp->rx_cur].mapping,
- lp->rx_skb[lp->rx_cur].len, DMA_FROM_DEVICE);
-
- /* Discard packet on reception error or bad checksum */
- if ((dd->des3 & DWCEQOS_DMA_RDES3_ES) ||
- (dd->des1 & DWCEQOS_DMA_RDES1_IPCE)) {
- dev_kfree_skb(skb);
- skb = NULL;
- } else {
- skb_put(skb, len);
- skb->protocol = eth_type_trans(skb, lp->ndev);
- switch (dd->des1 & DWCEQOS_DMA_RDES1_PT) {
- case DWCEQOS_DMA_RDES1_PT_UDP:
- case DWCEQOS_DMA_RDES1_PT_TCP:
- case DWCEQOS_DMA_RDES1_PT_ICMP:
- skb->ip_summed = CHECKSUM_UNNECESSARY;
- break;
- default:
- skb->ip_summed = CHECKSUM_NONE;
- break;
- }
- }
-
- if (unlikely(!skb)) {
- if (netif_msg_rx_err(lp))
- netdev_dbg(lp->ndev, "rx error: des3=%X\n",
- lp->rx_descs[lp->rx_cur].des3);
- } else {
- tot_size += skb->len;
- n_packets++;
-
- netif_receive_skb(skb);
- }
-
- lp->rx_descs[lp->rx_cur].des0 = new_skb_baddr;
- lp->rx_descs[lp->rx_cur].des1 = 0;
- lp->rx_descs[lp->rx_cur].des2 = 0;
- /* The DMA must observe des0/1/2 written before des3. */
- wmb();
- lp->rx_descs[lp->rx_cur].des3 = DWCEQOS_DMA_RDES3_INTE |
- DWCEQOS_DMA_RDES3_OWN |
- DWCEQOS_DMA_RDES3_BUF1V;
-
- lp->rx_skb[lp->rx_cur].mapping = new_skb_baddr;
- lp->rx_skb[lp->rx_cur].len = DWCEQOS_RX_BUF_SIZE;
- lp->rx_skb[lp->rx_cur].skb = new_skb;
-
- n_descs++;
- lp->rx_cur = (lp->rx_cur + 1) % DWCEQOS_RX_DCNT;
- }
-
- /* Make sure any ownership update is written to the descriptors before
- * DMA wakeup.
- */
- wmb();
-
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_STA, DWCEQOS_DMA_CH0_IS_RI);
- /* Wake up RX by writing tail pointer */
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_RXDESC_TAIL,
- lp->rx_descs_tail_addr);
-
- return n_descs;
-}
-
-static int dwceqos_rx_poll(struct napi_struct *napi, int budget)
-{
- struct net_local *lp = container_of(napi, struct net_local, napi);
- int work_done = 0;
-
- work_done = dwceqos_rx(lp, budget - work_done);
-
- if (!dwceqos_packet_avail(lp) && work_done < budget) {
- napi_complete(napi);
- dwceqos_dma_enable_rxirq(lp);
- } else {
- work_done = budget;
- }
-
- return work_done;
-}
-
-/* Reinitialize function if a TX timed out */
-static void dwceqos_reinit_for_txtimeout(struct work_struct *data)
-{
- struct net_local *lp = container_of(data, struct net_local,
- txtimeout_reinit);
-
- netdev_err(lp->ndev, "transmit timeout %d s, resetting...\n",
- DWCEQOS_TX_TIMEOUT);
-
- if (netif_msg_hw(lp))
- print_status(lp);
-
- rtnl_lock();
- dwceqos_stop(lp->ndev);
- dwceqos_open(lp->ndev);
- rtnl_unlock();
-}
-
-/* DT Probing function called by main probe */
-static inline int dwceqos_probe_config_dt(struct platform_device *pdev)
-{
- struct net_device *ndev;
- struct net_local *lp;
- const void *mac_address;
- struct dwceqos_bus_cfg *bus_cfg;
- struct device_node *np = pdev->dev.of_node;
-
- ndev = platform_get_drvdata(pdev);
- lp = netdev_priv(ndev);
- bus_cfg = &lp->bus_cfg;
-
- /* Set the MAC address. */
- mac_address = of_get_mac_address(pdev->dev.of_node);
- if (mac_address)
- ether_addr_copy(ndev->dev_addr, mac_address);
-
- /* These are all optional parameters */
- lp->en_tx_lpi_clockgating = of_property_read_bool(np,
- "snps,en-tx-lpi-clockgating");
- bus_cfg->en_lpi = of_property_read_bool(np, "snps,en-lpi");
- of_property_read_u32(np, "snps,write-requests",
- &bus_cfg->write_requests);
- of_property_read_u32(np, "snps,read-requests", &bus_cfg->read_requests);
- of_property_read_u32(np, "snps,burst-map", &bus_cfg->burst_map);
- of_property_read_u32(np, "snps,txpbl", &bus_cfg->tx_pbl);
- of_property_read_u32(np, "snps,rxpbl", &bus_cfg->rx_pbl);
-
- netdev_dbg(ndev, "BusCfg: lpi:%u wr:%u rr:%u bm:%X rxpbl:%u txpbl:%d\n",
- bus_cfg->en_lpi,
- bus_cfg->write_requests,
- bus_cfg->read_requests,
- bus_cfg->burst_map,
- bus_cfg->rx_pbl,
- bus_cfg->tx_pbl);
-
- return 0;
-}
-
-static int dwceqos_open(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
- int res;
-
- dwceqos_reset_state(lp);
- res = dwceqos_descriptor_init(lp);
- if (res) {
- netdev_err(ndev, "Unable to allocate DMA memory, rc %d\n", res);
- return res;
- }
- netdev_reset_queue(ndev);
-
- /* The dwceqos reset state machine requires all phy clocks to complete,
- * hence the unusual init order with phy_start first.
- */
- lp->phy_defer = true;
- phy_start(ndev->phydev);
- dwceqos_init_hw(lp);
- napi_enable(&lp->napi);
-
- netif_start_queue(ndev);
- tasklet_enable(&lp->tx_bdreclaim_tasklet);
-
- /* Enable Interrupts -- do this only after we enable NAPI and the
- * tasklet.
- */
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_IE,
- DWCEQOS_DMA_CH0_IE_NIE |
- DWCEQOS_DMA_CH0_IE_RIE | DWCEQOS_DMA_CH0_IE_TIE |
- DWCEQOS_DMA_CH0_IE_AIE |
- DWCEQOS_DMA_CH0_IE_FBEE);
-
- return 0;
-}
-
-static bool dweqos_is_tx_dma_suspended(struct net_local *lp)
-{
- u32 reg;
-
- reg = dwceqos_read(lp, REG_DWCEQOS_DMA_DEBUG_ST0);
- reg = DMA_GET_TX_STATE_CH0(reg);
-
- return reg == DMA_TX_CH_SUSPENDED;
-}
-
-static void dwceqos_drain_dma(struct net_local *lp)
-{
- /* Wait for all pending TX buffers to be sent. Upper limit based
- * on max frame size on a 10 Mbit link.
- */
- size_t limit = (DWCEQOS_TX_DCNT * 1250) / 100;
-
- while (!dweqos_is_tx_dma_suspended(lp) && limit--)
- usleep_range(100, 200);
-}
-
-static int dwceqos_stop(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
-
- tasklet_disable(&lp->tx_bdreclaim_tasklet);
- napi_disable(&lp->napi);
-
- /* Stop all tx before we drain the tx dma. */
- netif_tx_lock_bh(lp->ndev);
- netif_stop_queue(ndev);
- netif_tx_unlock_bh(lp->ndev);
-
- dwceqos_drain_dma(lp);
- dwceqos_reset_hw(lp);
- phy_stop(ndev->phydev);
-
- dwceqos_descriptor_free(lp);
-
- return 0;
-}
-
-static void dwceqos_dmadesc_set_ctx(struct net_local *lp,
- unsigned short gso_size)
-{
- struct dwceqos_dma_desc *dd = &lp->tx_descs[lp->tx_next];
-
- dd->des0 = 0;
- dd->des1 = 0;
- dd->des2 = gso_size;
- dd->des3 = DWCEQOS_DMA_TDES3_CTXT | DWCEQOS_DMA_TDES3_TCMSSV;
-
- lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
-}
-
-static void dwceqos_tx_poll_demand(struct net_local *lp)
-{
- dwceqos_write(lp, REG_DWCEQOS_DMA_CH0_TXDESC_TAIL,
- lp->tx_descs_tail_addr);
-}
-
-struct dwceqos_tx {
- size_t nr_descriptors;
- size_t initial_descriptor;
- size_t last_descriptor;
- size_t prev_gso_size;
- size_t network_header_len;
-};
-
-static void dwceqos_tx_prepare(struct sk_buff *skb, struct net_local *lp,
- struct dwceqos_tx *tx)
-{
- size_t n = 1;
- size_t i;
-
- if (skb_is_gso(skb) && skb_shinfo(skb)->gso_size != lp->gso_size)
- ++n;
-
- for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
- skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-
- n += (skb_frag_size(frag) + BYTES_PER_DMA_DESC - 1) /
- BYTES_PER_DMA_DESC;
- }
-
- tx->nr_descriptors = n;
- tx->initial_descriptor = lp->tx_next;
- tx->last_descriptor = lp->tx_next;
- tx->prev_gso_size = lp->gso_size;
-
- tx->network_header_len = skb_transport_offset(skb);
- if (skb_is_gso(skb))
- tx->network_header_len += tcp_hdrlen(skb);
-}
-
-static int dwceqos_tx_linear(struct sk_buff *skb, struct net_local *lp,
- struct dwceqos_tx *tx)
-{
- struct ring_desc *rd;
- struct dwceqos_dma_desc *dd;
- size_t payload_len;
- dma_addr_t dma_handle;
-
- if (skb_is_gso(skb) && skb_shinfo(skb)->gso_size != lp->gso_size) {
- dwceqos_dmadesc_set_ctx(lp, skb_shinfo(skb)->gso_size);
- lp->gso_size = skb_shinfo(skb)->gso_size;
- }
-
- dma_handle = dma_map_single(lp->ndev->dev.parent, skb->data,
- skb_headlen(skb), DMA_TO_DEVICE);
-
- if (dma_mapping_error(lp->ndev->dev.parent, dma_handle)) {
- netdev_err(lp->ndev, "TX DMA Mapping error\n");
- return -ENOMEM;
- }
-
- rd = &lp->tx_skb[lp->tx_next];
- dd = &lp->tx_descs[lp->tx_next];
-
- rd->skb = NULL;
- rd->len = skb_headlen(skb);
- rd->mapping = dma_handle;
-
- /* Set up DMA Descriptor */
- dd->des0 = dma_handle;
-
- if (skb_is_gso(skb)) {
- payload_len = skb_headlen(skb) - tx->network_header_len;
-
- if (payload_len)
- dd->des1 = dma_handle + tx->network_header_len;
- dd->des2 = tx->network_header_len |
- DWCEQOS_DMA_DES2_B2L(payload_len);
- dd->des3 = DWCEQOS_DMA_TDES3_TSE |
- DWCEQOS_DMA_DES3_THL((tcp_hdrlen(skb) / 4)) |
- (skb->len - tx->network_header_len);
- } else {
- dd->des1 = 0;
- dd->des2 = skb_headlen(skb);
- dd->des3 = skb->len;
-
- switch (skb->ip_summed) {
- case CHECKSUM_PARTIAL:
- dd->des3 |= DWCEQOS_DMA_TDES3_CA;
- case CHECKSUM_NONE:
- case CHECKSUM_UNNECESSARY:
- case CHECKSUM_COMPLETE:
- default:
- break;
- }
- }
-
- dd->des3 |= DWCEQOS_DMA_TDES3_FD;
- if (lp->tx_next != tx->initial_descriptor)
- dd->des3 |= DWCEQOS_DMA_TDES3_OWN;
-
- tx->last_descriptor = lp->tx_next;
- lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
-
- return 0;
-}
-
-static int dwceqos_tx_frags(struct sk_buff *skb, struct net_local *lp,
- struct dwceqos_tx *tx)
-{
- struct ring_desc *rd = NULL;
- struct dwceqos_dma_desc *dd;
- dma_addr_t dma_handle;
- size_t i;
-
- /* Setup more ring and DMA descriptor if the packet is fragmented */
- for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
- skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
- size_t frag_size;
- size_t consumed_size;
-
- /* Map DMA Area */
- dma_handle = skb_frag_dma_map(lp->ndev->dev.parent, frag, 0,
- skb_frag_size(frag),
- DMA_TO_DEVICE);
- if (dma_mapping_error(lp->ndev->dev.parent, dma_handle)) {
- netdev_err(lp->ndev, "DMA Mapping error\n");
- return -ENOMEM;
- }
-
- /* order-3 fragments span more than one descriptor. */
- frag_size = skb_frag_size(frag);
- consumed_size = 0;
- while (consumed_size < frag_size) {
- size_t dma_size = min_t(size_t, 16376,
- frag_size - consumed_size);
-
- rd = &lp->tx_skb[lp->tx_next];
- memset(rd, 0, sizeof(*rd));
-
- dd = &lp->tx_descs[lp->tx_next];
-
- /* Set DMA Descriptor fields */
- dd->des0 = dma_handle + consumed_size;
- dd->des1 = 0;
- dd->des2 = dma_size;
-
- if (skb_is_gso(skb))
- dd->des3 = (skb->len - tx->network_header_len);
- else
- dd->des3 = skb->len;
-
- dd->des3 |= DWCEQOS_DMA_TDES3_OWN;
-
- tx->last_descriptor = lp->tx_next;
- lp->tx_next = (lp->tx_next + 1) % DWCEQOS_TX_DCNT;
- consumed_size += dma_size;
- }
-
- rd->len = skb_frag_size(frag);
- rd->mapping = dma_handle;
- }
-
- return 0;
-}
-
-static void dwceqos_tx_finalize(struct sk_buff *skb, struct net_local *lp,
- struct dwceqos_tx *tx)
-{
- lp->tx_descs[tx->last_descriptor].des3 |= DWCEQOS_DMA_TDES3_LD;
- lp->tx_descs[tx->last_descriptor].des2 |= DWCEQOS_DMA_TDES2_IOC;
-
- lp->tx_skb[tx->last_descriptor].skb = skb;
-
- /* Make all descriptor updates visible to the DMA before setting the
- * owner bit.
- */
- wmb();
-
- lp->tx_descs[tx->initial_descriptor].des3 |= DWCEQOS_DMA_TDES3_OWN;
-
- /* Make the owner bit visible before TX wakeup. */
- wmb();
-
- dwceqos_tx_poll_demand(lp);
-}
-
-static void dwceqos_tx_rollback(struct net_local *lp, struct dwceqos_tx *tx)
-{
- size_t i = tx->initial_descriptor;
-
- while (i != lp->tx_next) {
- if (lp->tx_skb[i].mapping)
- dma_unmap_single(lp->ndev->dev.parent,
- lp->tx_skb[i].mapping,
- lp->tx_skb[i].len,
- DMA_TO_DEVICE);
-
- lp->tx_skb[i].mapping = 0;
- lp->tx_skb[i].skb = NULL;
-
- memset(&lp->tx_descs[i], 0, sizeof(lp->tx_descs[i]));
-
- i = (i + 1) % DWCEQOS_TX_DCNT;
- }
-
- lp->tx_next = tx->initial_descriptor;
- lp->gso_size = tx->prev_gso_size;
-}
-
-static int dwceqos_start_xmit(struct sk_buff *skb, struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
- struct dwceqos_tx trans;
- int err;
-
- dwceqos_tx_prepare(skb, lp, &trans);
- if (lp->tx_free < trans.nr_descriptors) {
- netif_stop_queue(ndev);
- return NETDEV_TX_BUSY;
- }
-
- err = dwceqos_tx_linear(skb, lp, &trans);
- if (err)
- goto tx_error;
-
- err = dwceqos_tx_frags(skb, lp, &trans);
- if (err)
- goto tx_error;
-
- WARN_ON(lp->tx_next !=
- ((trans.initial_descriptor + trans.nr_descriptors) %
- DWCEQOS_TX_DCNT));
-
- spin_lock_bh(&lp->tx_lock);
- lp->tx_free -= trans.nr_descriptors;
- dwceqos_tx_finalize(skb, lp, &trans);
- netdev_sent_queue(ndev, skb->len);
- spin_unlock_bh(&lp->tx_lock);
-
- netif_trans_update(ndev);
- return 0;
-
-tx_error:
- dwceqos_tx_rollback(lp, &trans);
- dev_kfree_skb_any(skb);
- return 0;
-}
-
-/* Set MAC address and then update HW accordingly */
-static int dwceqos_set_mac_address(struct net_device *ndev, void *addr)
-{
- struct net_local *lp = netdev_priv(ndev);
- struct sockaddr *hwaddr = (struct sockaddr *)addr;
-
- if (netif_running(ndev))
- return -EBUSY;
-
- if (!is_valid_ether_addr(hwaddr->sa_data))
- return -EADDRNOTAVAIL;
-
- memcpy(ndev->dev_addr, hwaddr->sa_data, ndev->addr_len);
-
- dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
- return 0;
-}
-
-static void dwceqos_tx_timeout(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
-
- queue_work(lp->txtimeout_handler_wq, &lp->txtimeout_reinit);
-}
-
-static void dwceqos_set_umac_addr(struct net_local *lp, unsigned char *addr,
- unsigned int reg_n)
-{
- unsigned long data;
-
- data = (addr[5] << 8) | addr[4];
- dwceqos_write(lp, DWCEQOS_ADDR_HIGH(reg_n),
- data | DWCEQOS_MAC_MAC_ADDR_HI_EN);
- data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
- dwceqos_write(lp, DWCEQOS_ADDR_LOW(reg_n), data);
-}
-
-static void dwceqos_disable_umac_addr(struct net_local *lp, unsigned int reg_n)
-{
- /* Do not disable MAC address 0 */
- if (reg_n != 0)
- dwceqos_write(lp, DWCEQOS_ADDR_HIGH(reg_n), 0);
-}
-
-static void dwceqos_set_rx_mode(struct net_device *ndev)
-{
- struct net_local *lp = netdev_priv(ndev);
- u32 regval = 0;
- u32 mc_filter[2];
- int reg = 1;
- struct netdev_hw_addr *ha;
- unsigned int max_mac_addr;
-
- max_mac_addr = DWCEQOS_MAX_PERFECT_ADDRESSES(lp->feature1);
-
- if (ndev->flags & IFF_PROMISC) {
- regval = DWCEQOS_MAC_PKT_FILT_PR;
- } else if (((netdev_mc_count(ndev) > DWCEQOS_HASH_TABLE_SIZE) ||
- (ndev->flags & IFF_ALLMULTI))) {
- regval = DWCEQOS_MAC_PKT_FILT_PM;
- dwceqos_write(lp, REG_DWCEQOS_HASTABLE_LO, 0xffffffff);
- dwceqos_write(lp, REG_DWCEQOS_HASTABLE_HI, 0xffffffff);
- } else if (!netdev_mc_empty(ndev)) {
- regval = DWCEQOS_MAC_PKT_FILT_HMC;
- memset(mc_filter, 0, sizeof(mc_filter));
- netdev_for_each_mc_addr(ha, ndev) {
- /* The upper 6 bits of the calculated CRC are used to
- * index the contens of the hash table
- */
- int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
- /* The most significant bit determines the register
- * to use (H/L) while the other 5 bits determine
- * the bit within the register.
- */
- mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
- }
- dwceqos_write(lp, REG_DWCEQOS_HASTABLE_LO, mc_filter[0]);
- dwceqos_write(lp, REG_DWCEQOS_HASTABLE_HI, mc_filter[1]);
- }
- if (netdev_uc_count(ndev) > max_mac_addr) {
- regval |= DWCEQOS_MAC_PKT_FILT_PR;
- } else {
- netdev_for_each_uc_addr(ha, ndev) {
- dwceqos_set_umac_addr(lp, ha->addr, reg);
- reg++;
- }
- for (; reg < DWCEQOS_MAX_PERFECT_ADDRESSES(lp->feature1); reg++)
- dwceqos_disable_umac_addr(lp, reg);
- }
- dwceqos_write(lp, REG_DWCEQOS_MAC_PKT_FILT, regval);
-}
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-static void dwceqos_poll_controller(struct net_device *ndev)
-{
- disable_irq(ndev->irq);
- dwceqos_interrupt(ndev->irq, ndev);
- enable_irq(ndev->irq);
-}
-#endif
-
-static void dwceqos_read_mmc_counters(struct net_local *lp, u32 rx_mask,
- u32 tx_mask)
-{
- if (tx_mask & BIT(27))
- lp->mmc_counters.txlpitranscntr +=
- dwceqos_read(lp, DWC_MMC_TXLPITRANSCNTR);
- if (tx_mask & BIT(26))
- lp->mmc_counters.txpiuscntr +=
- dwceqos_read(lp, DWC_MMC_TXLPIUSCNTR);
- if (tx_mask & BIT(25))
- lp->mmc_counters.txoversize_g +=
- dwceqos_read(lp, DWC_MMC_TXOVERSIZE_G);
- if (tx_mask & BIT(24))
- lp->mmc_counters.txvlanpackets_g +=
- dwceqos_read(lp, DWC_MMC_TXVLANPACKETS_G);
- if (tx_mask & BIT(23))
- lp->mmc_counters.txpausepackets +=
- dwceqos_read(lp, DWC_MMC_TXPAUSEPACKETS);
- if (tx_mask & BIT(22))
- lp->mmc_counters.txexcessdef +=
- dwceqos_read(lp, DWC_MMC_TXEXCESSDEF);
- if (tx_mask & BIT(21))
- lp->mmc_counters.txpacketcount_g +=
- dwceqos_read(lp, DWC_MMC_TXPACKETCOUNT_G);
- if (tx_mask & BIT(20))
- lp->mmc_counters.txoctetcount_g +=
- dwceqos_read(lp, DWC_MMC_TXOCTETCOUNT_G);
- if (tx_mask & BIT(19))
- lp->mmc_counters.txcarriererror +=
- dwceqos_read(lp, DWC_MMC_TXCARRIERERROR);
- if (tx_mask & BIT(18))
- lp->mmc_counters.txexcesscol +=
- dwceqos_read(lp, DWC_MMC_TXEXCESSCOL);
- if (tx_mask & BIT(17))
- lp->mmc_counters.txlatecol +=
- dwceqos_read(lp, DWC_MMC_TXLATECOL);
- if (tx_mask & BIT(16))
- lp->mmc_counters.txdeferred +=
- dwceqos_read(lp, DWC_MMC_TXDEFERRED);
- if (tx_mask & BIT(15))
- lp->mmc_counters.txmulticol_g +=
- dwceqos_read(lp, DWC_MMC_TXMULTICOL_G);
- if (tx_mask & BIT(14))
- lp->mmc_counters.txsinglecol_g +=
- dwceqos_read(lp, DWC_MMC_TXSINGLECOL_G);
- if (tx_mask & BIT(13))
- lp->mmc_counters.txunderflowerror +=
- dwceqos_read(lp, DWC_MMC_TXUNDERFLOWERROR);
- if (tx_mask & BIT(12))
- lp->mmc_counters.txbroadcastpackets_gb +=
- dwceqos_read(lp, DWC_MMC_TXBROADCASTPACKETS_GB);
- if (tx_mask & BIT(11))
- lp->mmc_counters.txmulticastpackets_gb +=
- dwceqos_read(lp, DWC_MMC_TXMULTICASTPACKETS_GB);
- if (tx_mask & BIT(10))
- lp->mmc_counters.txunicastpackets_gb +=
- dwceqos_read(lp, DWC_MMC_TXUNICASTPACKETS_GB);
- if (tx_mask & BIT(9))
- lp->mmc_counters.tx1024tomaxoctets_gb +=
- dwceqos_read(lp, DWC_MMC_TX1024TOMAXOCTETS_GB);
- if (tx_mask & BIT(8))
- lp->mmc_counters.tx512to1023octets_gb +=
- dwceqos_read(lp, DWC_MMC_TX512TO1023OCTETS_GB);
- if (tx_mask & BIT(7))
- lp->mmc_counters.tx256to511octets_gb +=
- dwceqos_read(lp, DWC_MMC_TX256TO511OCTETS_GB);
- if (tx_mask & BIT(6))
- lp->mmc_counters.tx128to255octets_gb +=
- dwceqos_read(lp, DWC_MMC_TX128TO255OCTETS_GB);
- if (tx_mask & BIT(5))
- lp->mmc_counters.tx65to127octets_gb +=
- dwceqos_read(lp, DWC_MMC_TX65TO127OCTETS_GB);
- if (tx_mask & BIT(4))
- lp->mmc_counters.tx64octets_gb +=
- dwceqos_read(lp, DWC_MMC_TX64OCTETS_GB);
- if (tx_mask & BIT(3))
- lp->mmc_counters.txmulticastpackets_g +=
- dwceqos_read(lp, DWC_MMC_TXMULTICASTPACKETS_G);
- if (tx_mask & BIT(2))
- lp->mmc_counters.txbroadcastpackets_g +=
- dwceqos_read(lp, DWC_MMC_TXBROADCASTPACKETS_G);
- if (tx_mask & BIT(1))
- lp->mmc_counters.txpacketcount_gb +=
- dwceqos_read(lp, DWC_MMC_TXPACKETCOUNT_GB);
- if (tx_mask & BIT(0))
- lp->mmc_counters.txoctetcount_gb +=
- dwceqos_read(lp, DWC_MMC_TXOCTETCOUNT_GB);
-
- if (rx_mask & BIT(27))
- lp->mmc_counters.rxlpitranscntr +=
- dwceqos_read(lp, DWC_MMC_RXLPITRANSCNTR);
- if (rx_mask & BIT(26))
- lp->mmc_counters.rxlpiuscntr +=
- dwceqos_read(lp, DWC_MMC_RXLPIUSCNTR);
- if (rx_mask & BIT(25))
- lp->mmc_counters.rxctrlpackets_g +=
- dwceqos_read(lp, DWC_MMC_RXCTRLPACKETS_G);
- if (rx_mask & BIT(24))
- lp->mmc_counters.rxrcverror +=
- dwceqos_read(lp, DWC_MMC_RXRCVERROR);
- if (rx_mask & BIT(23))
- lp->mmc_counters.rxwatchdog +=
- dwceqos_read(lp, DWC_MMC_RXWATCHDOG);
- if (rx_mask & BIT(22))
- lp->mmc_counters.rxvlanpackets_gb +=
- dwceqos_read(lp, DWC_MMC_RXVLANPACKETS_GB);
- if (rx_mask & BIT(21))
- lp->mmc_counters.rxfifooverflow +=
- dwceqos_read(lp, DWC_MMC_RXFIFOOVERFLOW);
- if (rx_mask & BIT(20))
- lp->mmc_counters.rxpausepackets +=
- dwceqos_read(lp, DWC_MMC_RXPAUSEPACKETS);
- if (rx_mask & BIT(19))
- lp->mmc_counters.rxoutofrangetype +=
- dwceqos_read(lp, DWC_MMC_RXOUTOFRANGETYPE);
- if (rx_mask & BIT(18))
- lp->mmc_counters.rxlengtherror +=
- dwceqos_read(lp, DWC_MMC_RXLENGTHERROR);
- if (rx_mask & BIT(17))
- lp->mmc_counters.rxunicastpackets_g +=
- dwceqos_read(lp, DWC_MMC_RXUNICASTPACKETS_G);
- if (rx_mask & BIT(16))
- lp->mmc_counters.rx1024tomaxoctets_gb +=
- dwceqos_read(lp, DWC_MMC_RX1024TOMAXOCTETS_GB);
- if (rx_mask & BIT(15))
- lp->mmc_counters.rx512to1023octets_gb +=
- dwceqos_read(lp, DWC_MMC_RX512TO1023OCTETS_GB);
- if (rx_mask & BIT(14))
- lp->mmc_counters.rx256to511octets_gb +=
- dwceqos_read(lp, DWC_MMC_RX256TO511OCTETS_GB);
- if (rx_mask & BIT(13))
- lp->mmc_counters.rx128to255octets_gb +=
- dwceqos_read(lp, DWC_MMC_RX128TO255OCTETS_GB);
- if (rx_mask & BIT(12))
- lp->mmc_counters.rx65to127octets_gb +=
- dwceqos_read(lp, DWC_MMC_RX65TO127OCTETS_GB);
- if (rx_mask & BIT(11))
- lp->mmc_counters.rx64octets_gb +=
- dwceqos_read(lp, DWC_MMC_RX64OCTETS_GB);
- if (rx_mask & BIT(10))
- lp->mmc_counters.rxoversize_g +=
- dwceqos_read(lp, DWC_MMC_RXOVERSIZE_G);
- if (rx_mask & BIT(9))
- lp->mmc_counters.rxundersize_g +=
- dwceqos_read(lp, DWC_MMC_RXUNDERSIZE_G);
- if (rx_mask & BIT(8))
- lp->mmc_counters.rxjabbererror +=
- dwceqos_read(lp, DWC_MMC_RXJABBERERROR);
- if (rx_mask & BIT(7))
- lp->mmc_counters.rxrunterror +=
- dwceqos_read(lp, DWC_MMC_RXRUNTERROR);
- if (rx_mask & BIT(6))
- lp->mmc_counters.rxalignmenterror +=
- dwceqos_read(lp, DWC_MMC_RXALIGNMENTERROR);
- if (rx_mask & BIT(5))
- lp->mmc_counters.rxcrcerror +=
- dwceqos_read(lp, DWC_MMC_RXCRCERROR);
- if (rx_mask & BIT(4))
- lp->mmc_counters.rxmulticastpackets_g +=
- dwceqos_read(lp, DWC_MMC_RXMULTICASTPACKETS_G);
- if (rx_mask & BIT(3))
- lp->mmc_counters.rxbroadcastpackets_g +=
- dwceqos_read(lp, DWC_MMC_RXBROADCASTPACKETS_G);
- if (rx_mask & BIT(2))
- lp->mmc_counters.rxoctetcount_g +=
- dwceqos_read(lp, DWC_MMC_RXOCTETCOUNT_G);
- if (rx_mask & BIT(1))
- lp->mmc_counters.rxoctetcount_gb +=
- dwceqos_read(lp, DWC_MMC_RXOCTETCOUNT_GB);
- if (rx_mask & BIT(0))
- lp->mmc_counters.rxpacketcount_gb +=
- dwceqos_read(lp, DWC_MMC_RXPACKETCOUNT_GB);
-}
-
-static void
-dwceqos_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *s)
-{
- unsigned long flags;
- struct net_local *lp = netdev_priv(ndev);
- struct dwceqos_mmc_counters *hwstats = &lp->mmc_counters;
-
- spin_lock_irqsave(&lp->stats_lock, flags);
- dwceqos_read_mmc_counters(lp, lp->mmc_rx_counters_mask,
- lp->mmc_tx_counters_mask);
- spin_unlock_irqrestore(&lp->stats_lock, flags);
-
- s->rx_packets = hwstats->rxpacketcount_gb;
- s->rx_bytes = hwstats->rxoctetcount_gb;
- s->rx_errors = hwstats->rxpacketcount_gb -
- hwstats->rxbroadcastpackets_g -
- hwstats->rxmulticastpackets_g -
- hwstats->rxunicastpackets_g;
- s->multicast = hwstats->rxmulticastpackets_g;
- s->rx_length_errors = hwstats->rxlengtherror;
- s->rx_crc_errors = hwstats->rxcrcerror;
- s->rx_fifo_errors = hwstats->rxfifooverflow;
-
- s->tx_packets = hwstats->txpacketcount_gb;
- s->tx_bytes = hwstats->txoctetcount_gb;
-
- if (lp->mmc_tx_counters_mask & BIT(21))
- s->tx_errors = hwstats->txpacketcount_gb -
- hwstats->txpacketcount_g;
- else
- s->tx_errors = hwstats->txunderflowerror +
- hwstats->txcarriererror;
-}
-
-static void
-dwceqos_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *ed)
-{
- const struct net_local *lp = netdev_priv(ndev);
-
- strcpy(ed->driver, lp->pdev->dev.driver->name);
- strcpy(ed->version, DRIVER_VERSION);
-}
-
-static void dwceqos_get_pauseparam(struct net_device *ndev,
- struct ethtool_pauseparam *pp)
-{
- const struct net_local *lp = netdev_priv(ndev);
-
- pp->autoneg = lp->flowcontrol.autoneg;
- pp->tx_pause = lp->flowcontrol.tx;
- pp->rx_pause = lp->flowcontrol.rx;
-}
-
-static int dwceqos_set_pauseparam(struct net_device *ndev,
- struct ethtool_pauseparam *pp)
-{
- struct net_local *lp = netdev_priv(ndev);
- int ret = 0;
-
- lp->flowcontrol.autoneg = pp->autoneg;
- if (pp->autoneg) {
- ndev->phydev->advertising |= ADVERTISED_Pause;
- ndev->phydev->advertising |= ADVERTISED_Asym_Pause;
- } else {
- ndev->phydev->advertising &= ~ADVERTISED_Pause;
- ndev->phydev->advertising &= ~ADVERTISED_Asym_Pause;
- lp->flowcontrol.rx = pp->rx_pause;
- lp->flowcontrol.tx = pp->tx_pause;
- }
-
- if (netif_running(ndev))
- ret = phy_start_aneg(ndev->phydev);
-
- return ret;
-}
-
-static void dwceqos_get_strings(struct net_device *ndev, u32 stringset,
- u8 *data)
-{
- size_t i;
-
- if (stringset != ETH_SS_STATS)
- return;
-
- for (i = 0; i < ARRAY_SIZE(dwceqos_ethtool_stats); ++i) {
- memcpy(data, dwceqos_ethtool_stats[i].stat_name,
- ETH_GSTRING_LEN);
- data += ETH_GSTRING_LEN;
- }
-}
-
-static void dwceqos_get_ethtool_stats(struct net_device *ndev,
- struct ethtool_stats *stats, u64 *data)
-{
- struct net_local *lp = netdev_priv(ndev);
- unsigned long flags;
- size_t i;
- u8 *mmcstat = (u8 *)&lp->mmc_counters;
-
- spin_lock_irqsave(&lp->stats_lock, flags);
- dwceqos_read_mmc_counters(lp, lp->mmc_rx_counters_mask,
- lp->mmc_tx_counters_mask);
- spin_unlock_irqrestore(&lp->stats_lock, flags);
-
- for (i = 0; i < ARRAY_SIZE(dwceqos_ethtool_stats); ++i) {
- memcpy(data,
- mmcstat + dwceqos_ethtool_stats[i].offset,
- sizeof(u64));
- data++;
- }
-}
-
-static int dwceqos_get_sset_count(struct net_device *ndev, int sset)
-{
- if (sset == ETH_SS_STATS)
- return ARRAY_SIZE(dwceqos_ethtool_stats);
-
- return -EOPNOTSUPP;
-}
-
-static void dwceqos_get_regs(struct net_device *dev, struct ethtool_regs *regs,
- void *space)
-{
- const struct net_local *lp = netdev_priv(dev);
- u32 *reg_space = (u32 *)space;
- int reg_offset;
- int reg_ix = 0;
-
- /* MAC registers */
- for (reg_offset = START_MAC_REG_OFFSET;
- reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) {
- reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
- reg_ix++;
- }
- /* MTL registers */
- for (reg_offset = START_MTL_REG_OFFSET;
- reg_offset <= MAX_MTL_REG_OFFSET; reg_offset += 4) {
- reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
- reg_ix++;
- }
-
- /* DMA registers */
- for (reg_offset = START_DMA_REG_OFFSET;
- reg_offset <= MAX_DMA_REG_OFFSET; reg_offset += 4) {
- reg_space[reg_ix] = dwceqos_read(lp, reg_offset);
- reg_ix++;
- }
-
- BUG_ON(4 * reg_ix > REG_SPACE_SIZE);
-}
-
-static int dwceqos_get_regs_len(struct net_device *dev)
-{
- return REG_SPACE_SIZE;
-}
-
-static inline const char *dwceqos_get_rx_lpi_state(u32 lpi_ctrl)
-{
- return (lpi_ctrl & DWCEQOS_MAC_LPI_CTRL_STATUS_RLPIST) ? "on" : "off";
-}
-
-static inline const char *dwceqos_get_tx_lpi_state(u32 lpi_ctrl)
-{
- return (lpi_ctrl & DWCEQOS_MAC_LPI_CTRL_STATUS_TLPIST) ? "on" : "off";
-}
-
-static int dwceqos_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
-{
- struct net_local *lp = netdev_priv(ndev);
- u32 lpi_status;
- u32 lpi_enabled;
-
- if (!(lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_EEESEL))
- return -EOPNOTSUPP;
-
- edata->eee_active = lp->eee_active;
- edata->eee_enabled = lp->eee_enabled;
- edata->tx_lpi_timer = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_ENTRY_TIMER);
- lpi_status = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- lpi_enabled = !!(lpi_status & DWCEQOS_MAC_LPI_CTRL_STATUS_LIPTXA);
- edata->tx_lpi_enabled = lpi_enabled;
-
- if (netif_msg_hw(lp)) {
- u32 regval;
-
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
-
- netdev_info(lp->ndev, "MAC LPI State: RX:%s TX:%s\n",
- dwceqos_get_rx_lpi_state(regval),
- dwceqos_get_tx_lpi_state(regval));
- }
-
- return phy_ethtool_get_eee(ndev->phydev, edata);
-}
-
-static int dwceqos_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
-{
- struct net_local *lp = netdev_priv(ndev);
- u32 regval;
- unsigned long flags;
-
- if (!(lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_EEESEL))
- return -EOPNOTSUPP;
-
- if (edata->eee_enabled && !lp->eee_active)
- return -EOPNOTSUPP;
-
- if (edata->tx_lpi_enabled) {
- if (edata->tx_lpi_timer < DWCEQOS_LPI_TIMER_MIN ||
- edata->tx_lpi_timer > DWCEQOS_LPI_TIMER_MAX)
- return -EINVAL;
- }
-
- lp->eee_enabled = edata->eee_enabled;
-
- if (edata->eee_enabled && edata->tx_lpi_enabled) {
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_ENTRY_TIMER,
- edata->tx_lpi_timer);
-
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- regval |= DWCEQOS_LPI_CTRL_ENABLE_EEE;
- if (lp->en_tx_lpi_clockgating)
- regval |= DWCEQOS_MAC_LPI_CTRL_STATUS_LPITCSE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
- } else {
- spin_lock_irqsave(&lp->hw_lock, flags);
- regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS);
- regval &= ~DWCEQOS_LPI_CTRL_ENABLE_EEE;
- dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval);
- spin_unlock_irqrestore(&lp->hw_lock, flags);
- }
-
- return phy_ethtool_set_eee(ndev->phydev, edata);
-}
-
-static u32 dwceqos_get_msglevel(struct net_device *ndev)
-{
- const struct net_local *lp = netdev_priv(ndev);
-
- return lp->msg_enable;
-}
-
-static void dwceqos_set_msglevel(struct net_device *ndev, u32 msglevel)
-{
- struct net_local *lp = netdev_priv(ndev);
-
- lp->msg_enable = msglevel;
-}
-
-static const struct ethtool_ops dwceqos_ethtool_ops = {
- .get_drvinfo = dwceqos_get_drvinfo,
- .get_link = ethtool_op_get_link,
- .get_pauseparam = dwceqos_get_pauseparam,
- .set_pauseparam = dwceqos_set_pauseparam,
- .get_strings = dwceqos_get_strings,
- .get_ethtool_stats = dwceqos_get_ethtool_stats,
- .get_sset_count = dwceqos_get_sset_count,
- .get_regs = dwceqos_get_regs,
- .get_regs_len = dwceqos_get_regs_len,
- .get_eee = dwceqos_get_eee,
- .set_eee = dwceqos_set_eee,
- .get_msglevel = dwceqos_get_msglevel,
- .set_msglevel = dwceqos_set_msglevel,
- .get_link_ksettings = phy_ethtool_get_link_ksettings,
- .set_link_ksettings = phy_ethtool_set_link_ksettings,
-};
-
-static const struct net_device_ops netdev_ops = {
- .ndo_open = dwceqos_open,
- .ndo_stop = dwceqos_stop,
- .ndo_start_xmit = dwceqos_start_xmit,
- .ndo_set_rx_mode = dwceqos_set_rx_mode,
- .ndo_set_mac_address = dwceqos_set_mac_address,
-#ifdef CONFIG_NET_POLL_CONTROLLER
- .ndo_poll_controller = dwceqos_poll_controller,
-#endif
- .ndo_do_ioctl = dwceqos_ioctl,
- .ndo_tx_timeout = dwceqos_tx_timeout,
- .ndo_get_stats64 = dwceqos_get_stats64,
-};
-
-static const struct of_device_id dwceq_of_match[] = {
- { .compatible = "snps,dwc-qos-ethernet-4.10", },
- {}
-};
-MODULE_DEVICE_TABLE(of, dwceq_of_match);
-
-static int dwceqos_probe(struct platform_device *pdev)
-{
- struct resource *r_mem = NULL;
- struct net_device *ndev;
- struct net_local *lp;
- int ret = -ENXIO;
-
- r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r_mem) {
- dev_err(&pdev->dev, "no IO resource defined.\n");
- return -ENXIO;
- }
-
- ndev = alloc_etherdev(sizeof(*lp));
- if (!ndev) {
- dev_err(&pdev->dev, "etherdev allocation failed.\n");
- return -ENOMEM;
- }
-
- SET_NETDEV_DEV(ndev, &pdev->dev);
-
- lp = netdev_priv(ndev);
- lp->ndev = ndev;
- lp->pdev = pdev;
- lp->msg_enable = netif_msg_init(debug, DWCEQOS_MSG_DEFAULT);
-
- spin_lock_init(&lp->tx_lock);
- spin_lock_init(&lp->hw_lock);
- spin_lock_init(&lp->stats_lock);
-
- lp->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
- if (IS_ERR(lp->apb_pclk)) {
- dev_err(&pdev->dev, "apb_pclk clock not found.\n");
- ret = PTR_ERR(lp->apb_pclk);
- goto err_out_free_netdev;
- }
-
- ret = clk_prepare_enable(lp->apb_pclk);
- if (ret) {
- dev_err(&pdev->dev, "Unable to enable APER clock.\n");
- goto err_out_free_netdev;
- }
-
- lp->baseaddr = devm_ioremap_resource(&pdev->dev, r_mem);
- if (IS_ERR(lp->baseaddr)) {
- dev_err(&pdev->dev, "failed to map baseaddress.\n");
- ret = PTR_ERR(lp->baseaddr);
- goto err_out_clk_dis_aper;
- }
-
- ndev->irq = platform_get_irq(pdev, 0);
- ndev->watchdog_timeo = DWCEQOS_TX_TIMEOUT * HZ;
- ndev->netdev_ops = &netdev_ops;
- ndev->ethtool_ops = &dwceqos_ethtool_ops;
- ndev->base_addr = r_mem->start;
-
- dwceqos_get_hwfeatures(lp);
- dwceqos_mdio_set_csr(lp);
-
- ndev->hw_features = NETIF_F_SG;
-
- if (lp->feature1 & DWCEQOS_MAC_HW_FEATURE1_TSOEN)
- ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
-
- if (lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_TXCOESEL)
- ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
-
- if (lp->feature0 & DWCEQOS_MAC_HW_FEATURE0_RXCOESEL)
- ndev->hw_features |= NETIF_F_RXCSUM;
-
- ndev->features = ndev->hw_features;
-
- lp->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref_clk");
- if (IS_ERR(lp->phy_ref_clk)) {
- dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
- ret = PTR_ERR(lp->phy_ref_clk);
- goto err_out_clk_dis_aper;
- }
-
- ret = clk_prepare_enable(lp->phy_ref_clk);
- if (ret) {
- dev_err(&pdev->dev, "Unable to enable device clock.\n");
- goto err_out_clk_dis_aper;
- }
-
- lp->phy_node = of_parse_phandle(lp->pdev->dev.of_node,
- "phy-handle", 0);
- if (!lp->phy_node && of_phy_is_fixed_link(lp->pdev->dev.of_node)) {
- ret = of_phy_register_fixed_link(lp->pdev->dev.of_node);
- if (ret < 0) {
- dev_err(&pdev->dev, "invalid fixed-link");
- goto err_out_clk_dis_phy;
- }
-
- lp->phy_node = of_node_get(lp->pdev->dev.of_node);
- }
-
- ret = of_get_phy_mode(lp->pdev->dev.of_node);
- if (ret < 0) {
- dev_err(&lp->pdev->dev, "error in getting phy i/f\n");
- goto err_out_deregister_fixed_link;
- }
-
- lp->phy_interface = ret;
-
- ret = dwceqos_mii_init(lp);
- if (ret) {
- dev_err(&lp->pdev->dev, "error in dwceqos_mii_init\n");
- goto err_out_deregister_fixed_link;
- }
-
- ret = dwceqos_mii_probe(ndev);
- if (ret != 0) {
- netdev_err(ndev, "mii_probe fail.\n");
- ret = -ENXIO;
- goto err_out_deregister_fixed_link;
- }
-
- dwceqos_set_umac_addr(lp, lp->ndev->dev_addr, 0);
-
- tasklet_init(&lp->tx_bdreclaim_tasklet, dwceqos_tx_reclaim,
- (unsigned long)ndev);
- tasklet_disable(&lp->tx_bdreclaim_tasklet);
-
- lp->txtimeout_handler_wq = alloc_workqueue(DRIVER_NAME,
- WQ_MEM_RECLAIM, 0);
- INIT_WORK(&lp->txtimeout_reinit, dwceqos_reinit_for_txtimeout);
-
- platform_set_drvdata(pdev, ndev);
- ret = dwceqos_probe_config_dt(pdev);
- if (ret) {
- dev_err(&lp->pdev->dev, "Unable to retrieve DT, error %d\n",
- ret);
- goto err_out_deregister_fixed_link;
- }
- dev_info(&lp->pdev->dev, "pdev->id %d, baseaddr 0x%08lx, irq %d\n",
- pdev->id, ndev->base_addr, ndev->irq);
-
- ret = devm_request_irq(&pdev->dev, ndev->irq, &dwceqos_interrupt, 0,
- ndev->name, ndev);
- if (ret) {
- dev_err(&lp->pdev->dev, "Unable to request IRQ %d, error %d\n",
- ndev->irq, ret);
- goto err_out_deregister_fixed_link;
- }
-
- if (netif_msg_probe(lp))
- netdev_dbg(ndev, "net_local@%p\n", lp);
-
- netif_napi_add(ndev, &lp->napi, dwceqos_rx_poll, NAPI_POLL_WEIGHT);
-
- ret = register_netdev(ndev);
- if (ret) {
- dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
- goto err_out_deregister_fixed_link;
- }
-
- return 0;
-
-err_out_deregister_fixed_link:
- if (of_phy_is_fixed_link(pdev->dev.of_node))
- of_phy_deregister_fixed_link(pdev->dev.of_node);
-err_out_clk_dis_phy:
- clk_disable_unprepare(lp->phy_ref_clk);
-err_out_clk_dis_aper:
- clk_disable_unprepare(lp->apb_pclk);
-err_out_free_netdev:
- of_node_put(lp->phy_node);
- free_netdev(ndev);
- platform_set_drvdata(pdev, NULL);
- return ret;
-}
-
-static int dwceqos_remove(struct platform_device *pdev)
-{
- struct net_device *ndev = platform_get_drvdata(pdev);
- struct net_local *lp;
-
- if (ndev) {
- lp = netdev_priv(ndev);
-
- if (ndev->phydev) {
- phy_disconnect(ndev->phydev);
- if (of_phy_is_fixed_link(pdev->dev.of_node))
- of_phy_deregister_fixed_link(pdev->dev.of_node);
- }
- mdiobus_unregister(lp->mii_bus);
- mdiobus_free(lp->mii_bus);
-
- unregister_netdev(ndev);
-
- clk_disable_unprepare(lp->phy_ref_clk);
- clk_disable_unprepare(lp->apb_pclk);
-
- free_netdev(ndev);
- }
-
- return 0;
-}
-
-static struct platform_driver dwceqos_driver = {
- .probe = dwceqos_probe,
- .remove = dwceqos_remove,
- .driver = {
- .name = DRIVER_NAME,
- .of_match_table = dwceq_of_match,
- },
-};
-
-module_platform_driver(dwceqos_driver);
-
-MODULE_DESCRIPTION("DWC Ethernet QoS v4.10a driver");
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Andreas Irestaal <andreas.irestal@axis.com>");
-MODULE_AUTHOR("Lars Persson <lars.persson@axis.com>");
--
2.9.3
^ permalink raw reply related
* Re: [PATCH] [net] net/mlx5e: fix another -Wmaybe-uninitialized warning
From: Arnd Bergmann @ 2017-01-12 10:10 UTC (permalink / raw)
To: Or Gerlitz
Cc: Saeed Mahameed, Hadar Hen Zion, David S . Miller, netdev,
linux-kernel
In-Reply-To: <5cc9060f-6802-8634-f144-4637e9576ef1@mellanox.com>
On Thursday, January 12, 2017 10:30:24 AM CET Or Gerlitz wrote:
> On 1/11/2017 11:14 PM, Arnd Bergmann wrote:
> > @@ -666,14 +666,15 @@ static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
> > struct rtable *rt;
> > struct neighbour *n = NULL;
> > int ttl;
> > + int ret;
> > +
> > + if (!IS_ENABLED(CONFIG_INET))
> > + return -EOPNOTSUPP;
> >
> > -#if IS_ENABLED(CONFIG_INET)
> > rt = ip_route_output_key(dev_net(mirred_dev), fl4);
> > - if (IS_ERR(rt))
> > - return PTR_ERR(rt);
> > -#else
> > - return -EOPNOTSUPP;
> > -#endif
> > + ret = PTR_ERR_OR_ZERO(rt);
> > + if (ret)
> > + return ret;
>
> but this means that if we got NULL from ip_route_output_key, we will
> return success (0) here which is wrong.
I don't think so: if 'rt' is NULL or a valid pointer, then 'ret' is zero
and we will not return here.
Arnd
^ permalink raw reply
* Re: [PATCH v2 2/2] stmmac: rename it to synopsys
From: Alexandre Torgue @ 2017-01-12 10:11 UTC (permalink / raw)
To: Joao Pinto, Florian Fainelli, davem
Cc: lars.persson, niklass, peppe.cavallaro, netdev
In-Reply-To: <a2d2e457-47e5-bb73-a059-0cb907a29ae0@synopsys.com>
Hi Joao
On 01/12/2017 10:43 AM, Joao Pinto wrote:
>
> Hi Florian,
>
> Às 9:14 PM de 1/11/2017, Florian Fainelli escreveu:
>> On 01/10/2017 06:52 AM, Joao Pinto wrote:
>>> This patch renames stmicro/stmmac to synopsys/ since it is a standard
>>> ethernet software package regarding synopsys ethernet controllers, supporting
>>> the majority of Synopsys Ethernet IPs. The config IDs remain the same, for
>>> retro-compatibility, only the description was changed.
>>
>> Do re really have to do this? ST Micro were the first to upstream
>> support for a Synopsys IP, and it was later on identified as being
>> "stmicro" instead of "synopsys" (during the big driver move under
>> drivers/net/ethernet) whichever came first in the driver essentially "wins".
>>
>> As mentioned before, although git is able to track renames, git log does
>> not automatically have --follow, so it can be hard for people to track
>> down the (new) history of the driver.
>>
>> Personally, I don't see much value in doing this rename, especially when
>> all the driver internal structures are still going to be named with
>> stmmac (and please don't even think about doing a s/stmmac/snps/ inside
>> the driver ;)).
>>
>> My 2 cents.
>>
>
> First of all, I am suggesting an alternative way of organizing the code, and
> that's it, I have no second intentions about anything :).
>
> Please don't see this as a take-over or erase Stmicro from credits, please... it
> makes no sense. You can leave STMicro license and all the credits fine by me and
> I insist on it. But lets name it for something that makes sense... lets call it
> dwc (designware controllers), I am totally open to suggestions.
>
> I don't understand the hostility of some comments, honestly.
>
> The easiest way is to keep things like they are today, and believe me I have a
> lot of things to do, like adding the support of multi-queues / multi-channels to
> stmmac, so I not suggesting this because it is fun.
>
> I am suggesting this because it is what I am used to seeing in other subsystems.
> USB has dwc2 and dwc3 folders that clearly identifies that they are Designware
> (synopsys) extensions to the USB 2.0 and 3.0. The author of dwc3 was Texas
> Instruments, and they did not name it ti/usb. For example I use an AXS101
> Development board that does not have a stmicro SoC but has a Designware Ethernet
> IP in it, so uses stmicro/stmmac. For me it is confusing.
>
> Lets not name it synopsys, for me it is totally fine, but naming it
> stmicro/stmmac is not the right way because it seems like it is a driver just
> for stmicro products, which is not, is for products that use Designware Ethernet
> IPs.
>
> I am volunteering to do this work, let's discuss this.
For me it makes no sens to rename only folder (stmicro/stmmac by
synopsys) and keep stmmac* inside a synopsys folder (that is very
confusing). If you propose that you have to change all.
BUT doing that, we will lose all stmmac driver story and we don't want
that.
>
> Thanks,
> Joao
>
>
^ permalink raw reply
* Re: net/atm: warning in alloc_tx/__might_sleep
From: Chas Williams @ 2017-01-12 10:40 UTC (permalink / raw)
To: Cong Wang, Michal Hocko
Cc: Andrey Konovalov, David S. Miller, Alexey Kuznetsov, James Morris,
Hideaki YOSHIFUJI, Patrick McHardy, netdev, LKML, Al Viro,
Dmitry Vyukov, Kostya Serebryany, Eric Dumazet, syzkaller
In-Reply-To: <CAM_iQpWqCaHp2OxdaTOvJrf5vuvPn=rVGTvpGuZMEoBNC95EEQ@mail.gmail.com>
On Wed, 2017-01-11 at 20:36 -0800, Cong Wang wrote:
> On Wed, Jan 11, 2017 at 11:46 AM, Michal Hocko <mhocko@kernel.org> wrote:
> > On Wed 11-01-17 20:45:25, Michal Hocko wrote:
> >> On Wed 11-01-17 09:37:06, Chas Williams wrote:
> >> > On Mon, 2017-01-09 at 18:20 +0100, Andrey Konovalov wrote:
> >> > > Hi!
> >> > >
> >> > > I've got the following error report while running the syzkaller fuzzer.
> >> > >
> >> > > On commit a121103c922847ba5010819a3f250f1f7fc84ab8 (4.10-rc3).
> >> > >
> >> > > A reproducer is attached.
> >> > >
> >> > > ------------[ cut here ]------------
> >> > > WARNING: CPU: 0 PID: 4114 at kernel/sched/core.c:7737 __might_sleep+0x149/0x1a0
> >> > > do not call blocking ops when !TASK_RUNNING; state=1 set at
> >> > > [<ffffffff813fcb22>] prepare_to_wait+0x182/0x530
> >> > > Modules linked in:
> >> > > CPU: 0 PID: 4114 Comm: a.out Not tainted 4.10.0-rc3+ #59
> >> > > Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Bochs 01/01/2011
> >> > > Call Trace:
> >> > > __dump_stack lib/dump_stack.c:15
> >> > > dump_stack+0x292/0x398 lib/dump_stack.c:51
> >> > > __warn+0x19f/0x1e0 kernel/panic.c:547
> >> > > warn_slowpath_fmt+0xc5/0x110 kernel/panic.c:562
> >> > > __might_sleep+0x149/0x1a0 kernel/sched/core.c:7732
> >> > > slab_pre_alloc_hook mm/slab.h:408
> >> > > slab_alloc_node mm/slub.c:2634
> >> > > kmem_cache_alloc_node+0x14a/0x280 mm/slub.c:2744
> >> > > __alloc_skb+0x10f/0x800 net/core/skbuff.c:219
> >> > > alloc_skb ./include/linux/skbuff.h:926
> >> > > alloc_tx net/atm/common.c:75
> >> >
> >> > This is likely alloc_skb(..., GFP_KERNEL) in alloc_tx(). The simplest
> >> > fix for this would be simply to switch this GFP_ATOMIC. See if this is
> >> > any better.
> >> >
> >> > diff --git a/net/atm/common.c b/net/atm/common.c
> >> > index a3ca922..d84220c 100644
> >> > --- a/net/atm/common.c
> >> > +++ b/net/atm/common.c
> >> > @@ -72,7 +72,7 @@ static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
> >> > sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
> >> > return NULL;
> >> > }
> >> > - while (!(skb = alloc_skb(size, GFP_KERNEL)))
> >> > + while (!(skb = alloc_skb(size, GFP_ATOMIC)))
> >> > schedule();
> >> > pr_debug("%d += %d\n", sk_wmem_alloc_get(sk), skb->truesize);
> >> > atomic_add(skb->truesize, &sk->sk_wmem_alloc);
> >>
> >> Blee, this code is just horrendous. But the "fix" is obviously broken!
> >> schedule() is just a noop if you do not change the task state and what
> >> you are just asking for is a never failing non sleeping allocation - aka
> >> a busy loop in the kernel!
> >
> > And btw. this while loop should be really turned into GFP_KERNEL |
> > __GFP_NOFAIL with and explanation why this allocation cannot possibly
> > fail.
>
> I think a nested loop is quite unnecessary, probably due to the code itself
> is pretty old. The alloc_tx() is in the outer loop, the alloc_skb() is
> in the inner
> loop, both seem to wait for a successful GFP allocation. The inner one
> is even more unnecessary.
>
> Of course, I am not surprised MM may already have a mechanism to do
> the similar logic.
>
> There maybe some reason ATM needs such a logic, although other proto
> could handle skb allocation failure quite well in ->sendmsg().
I can't think of any particular reason that it needs this loop here. I suspect
that the loop for alloc_tx() predates the wait logic in ->sendmsg() and that the
original looping was in alloc_tx() initially and was simply never removed. Changes
here would date back to before the git conversion.
^ permalink raw reply
* Re: [v5,1/5] soc: qcom: smem_state: Fix include for ERR_PTR()
From: Kalle Valo @ 2017-01-12 10:47 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Eugene Krasnikov, Kalle Valo, Andy Gross, wcn36xx, linux-wireless,
netdev, linux-kernel, linux-arm-msm
In-Reply-To: <1479190014-11297-1-git-send-email-bjorn.andersson@linaro.org>
Bjorn Andersson <bjorn.andersson@linaro.org> wrote:
> The correct include file for getting errno constants and ERR_PTR() is
> linux/err.h, rather than linux/errno.h, so fix the include.
>
> Fixes: e8b123e60084 ("soc: qcom: smem_state: Add stubs for disabled smem_state")
> Acked-by: Andy Gross <andy.gross@linaro.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
5 patches applied to ath-next branch of ath.git, thanks.
6c0b2e833f14 soc: qcom: smem_state: Fix include for ERR_PTR()
f303a9311065 wcn36xx: Transition driver to SMD client
886039036c20 wcn36xx: Implement firmware assisted scan
43efa3c0f241 wcn36xx: Implement print_reg indication
d53628882255 wcn36xx: Don't use the destroyed hal_mutex
--
https://patchwork.kernel.org/patch/9429045/
Documentation about submitting wireless patches and checking status
from patchwork:
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* [PATCH net-next v2 2/2] bpf: allow b/h/w/dw access for bpf's cb in ctx
From: Daniel Borkmann @ 2017-01-12 10:51 UTC (permalink / raw)
To: davem; +Cc: alexei.starovoitov, netdev, Daniel Borkmann
In-Reply-To: <cover.1484214889.git.daniel@iogearbox.net>
When structs are used to store temporary state in cb[] buffer that is
used with programs and among tail calls, then the generated code will
not always access the buffer in bpf_w chunks. We can ease programming
of it and let this act more natural by allowing for aligned b/h/w/dw
sized access for cb[] ctx member. Various test cases are attached as
well for the selftest suite. Potentially, this can also be reused for
other program types to pass data around.
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Alexei Starovoitov <ast@kernel.org>
---
kernel/bpf/verifier.c | 8 +-
net/core/filter.c | 41 ++-
tools/testing/selftests/bpf/test_verifier.c | 442 +++++++++++++++++++++++++++-
3 files changed, 478 insertions(+), 13 deletions(-)
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index df7e472..d60e12c 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3165,10 +3165,14 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env)
insn = env->prog->insnsi + delta;
for (i = 0; i < insn_cnt; i++, insn++) {
- if (insn->code == (BPF_LDX | BPF_MEM | BPF_W) ||
+ if (insn->code == (BPF_LDX | BPF_MEM | BPF_B) ||
+ insn->code == (BPF_LDX | BPF_MEM | BPF_H) ||
+ insn->code == (BPF_LDX | BPF_MEM | BPF_W) ||
insn->code == (BPF_LDX | BPF_MEM | BPF_DW))
type = BPF_READ;
- else if (insn->code == (BPF_STX | BPF_MEM | BPF_W) ||
+ else if (insn->code == (BPF_STX | BPF_MEM | BPF_B) ||
+ insn->code == (BPF_STX | BPF_MEM | BPF_H) ||
+ insn->code == (BPF_STX | BPF_MEM | BPF_W) ||
insn->code == (BPF_STX | BPF_MEM | BPF_DW))
type = BPF_WRITE;
else
diff --git a/net/core/filter.c b/net/core/filter.c
index 8cfbdef..9038386 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -2776,11 +2776,33 @@ static bool __is_valid_access(int off, int size)
{
if (off < 0 || off >= sizeof(struct __sk_buff))
return false;
+
/* The verifier guarantees that size > 0. */
if (off % size != 0)
return false;
- if (size != sizeof(__u32))
- return false;
+
+ switch (off) {
+ case offsetof(struct __sk_buff, cb[0]) ...
+ offsetof(struct __sk_buff, cb[4]) + sizeof(__u32) - 1:
+ if (size == sizeof(__u16) &&
+ off > offsetof(struct __sk_buff, cb[4]) + sizeof(__u16))
+ return false;
+ if (size == sizeof(__u32) &&
+ off > offsetof(struct __sk_buff, cb[4]))
+ return false;
+ if (size == sizeof(__u64) &&
+ off > offsetof(struct __sk_buff, cb[2]))
+ return false;
+ if (size != sizeof(__u8) &&
+ size != sizeof(__u16) &&
+ size != sizeof(__u32) &&
+ size != sizeof(__u64))
+ return false;
+ break;
+ default:
+ if (size != sizeof(__u32))
+ return false;
+ }
return true;
}
@@ -2799,7 +2821,7 @@ static bool sk_filter_is_valid_access(int off, int size,
if (type == BPF_WRITE) {
switch (off) {
case offsetof(struct __sk_buff, cb[0]) ...
- offsetof(struct __sk_buff, cb[4]):
+ offsetof(struct __sk_buff, cb[4]) + sizeof(__u32) - 1:
break;
default:
return false;
@@ -2823,7 +2845,7 @@ static bool lwt_is_valid_access(int off, int size,
case offsetof(struct __sk_buff, mark):
case offsetof(struct __sk_buff, priority):
case offsetof(struct __sk_buff, cb[0]) ...
- offsetof(struct __sk_buff, cb[4]):
+ offsetof(struct __sk_buff, cb[4]) + sizeof(__u32) - 1:
break;
default:
return false;
@@ -2915,7 +2937,7 @@ static bool tc_cls_act_is_valid_access(int off, int size,
case offsetof(struct __sk_buff, tc_index):
case offsetof(struct __sk_buff, priority):
case offsetof(struct __sk_buff, cb[0]) ...
- offsetof(struct __sk_buff, cb[4]):
+ offsetof(struct __sk_buff, cb[4]) + sizeof(__u32) - 1:
case offsetof(struct __sk_buff, tc_classid):
break;
default:
@@ -3066,8 +3088,11 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type,
si->dst_reg, si->src_reg, insn);
case offsetof(struct __sk_buff, cb[0]) ...
- offsetof(struct __sk_buff, cb[4]):
+ offsetof(struct __sk_buff, cb[4]) + sizeof(__u32) - 1:
BUILD_BUG_ON(FIELD_SIZEOF(struct qdisc_skb_cb, data) < 20);
+ BUILD_BUG_ON((offsetof(struct sk_buff, cb) +
+ offsetof(struct qdisc_skb_cb, data)) %
+ sizeof(__u64));
prog->cb_access = 1;
off = si->off;
@@ -3075,10 +3100,10 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type,
off += offsetof(struct sk_buff, cb);
off += offsetof(struct qdisc_skb_cb, data);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg,
+ *insn++ = BPF_STX_MEM(BPF_SIZE(si->code), si->dst_reg,
si->src_reg, off);
else
- *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg,
+ *insn++ = BPF_LDX_MEM(BPF_SIZE(si->code), si->dst_reg,
si->src_reg, off);
break;
diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c
index 9bb4534..1aa7324 100644
--- a/tools/testing/selftests/bpf/test_verifier.c
+++ b/tools/testing/selftests/bpf/test_verifier.c
@@ -859,15 +859,451 @@ struct test_val {
.result = REJECT,
},
{
- "check non-u32 access to cb",
+ "check cb access: byte",
.insns = {
- BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_1,
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 1),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 2),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 3),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1]) + 1),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1]) + 2),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1]) + 3),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2]) + 1),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2]) + 2),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2]) + 3),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3]) + 1),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3]) + 2),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3]) + 3),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 1),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 2),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 3),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) + 1),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) + 2),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) + 3),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1]) + 1),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1]) + 2),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1]) + 3),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2]) + 1),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2]) + 2),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2]) + 3),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3]) + 1),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3]) + 2),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3]) + 3),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 1),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 2),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 3),
+ BPF_EXIT_INSN(),
+ },
+ .result = ACCEPT,
+ },
+ {
+ "check cb access: byte, oob 1",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 4),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: byte, oob 2",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) - 1),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: byte, oob 3",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 4),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: byte, oob 4",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_B, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) - 1),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: byte, wrong type",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_B, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ .prog_type = BPF_PROG_TYPE_CGROUP_SOCK,
+ },
+ {
+ "check cb access: half",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 2),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1]) + 2),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2]) + 2),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3]) + 2),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 2),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) + 2),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1]) + 2),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2]) + 2),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3]) + 2),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 2),
+ BPF_EXIT_INSN(),
+ },
+ .result = ACCEPT,
+ },
+ {
+ "check cb access: half, unaligned",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 1),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: half, oob 1",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 4),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: half, oob 2",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) - 2),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: half, oob 3",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 4),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: half, oob 4",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_H, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) - 2),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: half, wrong type",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_H, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ .prog_type = BPF_PROG_TYPE_CGROUP_SOCK,
+ },
+ {
+ "check cb access: word",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_LDX_MEM(BPF_W, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_EXIT_INSN(),
+ },
+ .result = ACCEPT,
+ },
+ {
+ "check cb access: word, unaligned 1",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) + 2),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: word, unaligned 2",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 1),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: word, unaligned 3",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 2),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: word, unaligned 4",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_W, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 3),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0])),
+ BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[2])),
+ BPF_EXIT_INSN(),
+ },
+ .result = ACCEPT,
+ },
+ {
+ "check cb access: double, unaligned 1",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[1])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, unaligned 2",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[3])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "misaligned access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 1",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 2",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[4]) + 8),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 3",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
+ offsetof(struct __sk_buff, cb[0]) - 8),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 4",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4])),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 5",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[4]) + 8),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, oob 6",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_LDX_MEM(BPF_DW, BPF_REG_0, BPF_REG_1,
+ offsetof(struct __sk_buff, cb[0]) - 8),
+ BPF_EXIT_INSN(),
+ },
+ .errstr = "invalid bpf_context access",
+ .result = REJECT,
+ },
+ {
+ "check cb access: double, wrong type",
+ .insns = {
+ BPF_MOV64_IMM(BPF_REG_0, 0),
+ BPF_STX_MEM(BPF_DW, BPF_REG_1, BPF_REG_0,
offsetof(struct __sk_buff, cb[0])),
BPF_EXIT_INSN(),
},
.errstr = "invalid bpf_context access",
- .errstr_unpriv = "R1 leaks addr",
.result = REJECT,
+ .prog_type = BPF_PROG_TYPE_CGROUP_SOCK,
},
{
"check out of range skb->cb access",
--
1.9.3
^ permalink raw reply related
* [PATCH net-next v2 1/2] bpf: pass original insn directly to convert_ctx_access
From: Daniel Borkmann @ 2017-01-12 10:51 UTC (permalink / raw)
To: davem; +Cc: alexei.starovoitov, netdev, Daniel Borkmann
In-Reply-To: <cover.1484214889.git.daniel@iogearbox.net>
Currently, when calling convert_ctx_access() callback for the various
program types, we pass in insn->dst_reg, insn->src_reg, insn->off from
the original instruction. This information is needed to rewrite the
instruction that is based on the user ctx structure into a kernel
representation for the ctx. As we'd like to allow access size beyond
just BPF_W, we'd need also insn->code for that in order to decode the
original access size. Given that, lets just pass insn directly to the
convert_ctx_access() callback and work on that to not clutter the
callback with even more arguments we need to pass when everything is
already contained in insn. So lets go through that once, no functional
change.
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Acked-by: Alexei Starovoitov <ast@kernel.org>
---
include/linux/bpf.h | 7 ++-
kernel/bpf/verifier.c | 3 +-
kernel/trace/bpf_trace.c | 15 ++---
net/core/filter.c | 139 +++++++++++++++++++++++++----------------------
4 files changed, 87 insertions(+), 77 deletions(-)
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index 94ea8d2..f8c3560 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -161,9 +161,10 @@ struct bpf_verifier_ops {
enum bpf_reg_type *reg_type);
int (*gen_prologue)(struct bpf_insn *insn, bool direct_write,
const struct bpf_prog *prog);
- u32 (*convert_ctx_access)(enum bpf_access_type type, int dst_reg,
- int src_reg, int ctx_off,
- struct bpf_insn *insn, struct bpf_prog *prog);
+ u32 (*convert_ctx_access)(enum bpf_access_type type,
+ const struct bpf_insn *src,
+ struct bpf_insn *dst,
+ struct bpf_prog *prog);
};
struct bpf_prog_type_list {
diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
index 2efdc91..df7e472 100644
--- a/kernel/bpf/verifier.c
+++ b/kernel/bpf/verifier.c
@@ -3177,8 +3177,7 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env)
if (env->insn_aux_data[i].ptr_type != PTR_TO_CTX)
continue;
- cnt = ops->convert_ctx_access(type, insn->dst_reg, insn->src_reg,
- insn->off, insn_buf, env->prog);
+ cnt = ops->convert_ctx_access(type, insn, insn_buf, env->prog);
if (cnt == 0 || cnt >= ARRAY_SIZE(insn_buf)) {
verbose("bpf verifier is misconfigured\n");
return -EINVAL;
diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index f883c43..1860e7f 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -572,28 +572,29 @@ static bool pe_prog_is_valid_access(int off, int size, enum bpf_access_type type
return true;
}
-static u32 pe_prog_convert_ctx_access(enum bpf_access_type type, int dst_reg,
- int src_reg, int ctx_off,
+static u32 pe_prog_convert_ctx_access(enum bpf_access_type type,
+ const struct bpf_insn *si,
struct bpf_insn *insn_buf,
struct bpf_prog *prog)
{
struct bpf_insn *insn = insn_buf;
- switch (ctx_off) {
+ switch (si->off) {
case offsetof(struct bpf_perf_event_data, sample_period):
BUILD_BUG_ON(FIELD_SIZEOF(struct perf_sample_data, period) != sizeof(u64));
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_perf_event_data_kern,
- data), dst_reg, src_reg,
+ data), si->dst_reg, si->src_reg,
offsetof(struct bpf_perf_event_data_kern, data));
- *insn++ = BPF_LDX_MEM(BPF_DW, dst_reg, dst_reg,
+ *insn++ = BPF_LDX_MEM(BPF_DW, si->dst_reg, si->dst_reg,
offsetof(struct perf_sample_data, period));
break;
default:
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct bpf_perf_event_data_kern,
- regs), dst_reg, src_reg,
+ regs), si->dst_reg, si->src_reg,
offsetof(struct bpf_perf_event_data_kern, regs));
- *insn++ = BPF_LDX_MEM(BPF_SIZEOF(long), dst_reg, dst_reg, ctx_off);
+ *insn++ = BPF_LDX_MEM(BPF_SIZEOF(long), si->dst_reg, si->dst_reg,
+ si->off);
break;
}
diff --git a/net/core/filter.c b/net/core/filter.c
index f4d16a9..8cfbdef 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -2972,32 +2972,33 @@ void bpf_warn_invalid_xdp_action(u32 act)
}
EXPORT_SYMBOL_GPL(bpf_warn_invalid_xdp_action);
-static u32 sk_filter_convert_ctx_access(enum bpf_access_type type, int dst_reg,
- int src_reg, int ctx_off,
+static u32 sk_filter_convert_ctx_access(enum bpf_access_type type,
+ const struct bpf_insn *si,
struct bpf_insn *insn_buf,
struct bpf_prog *prog)
{
struct bpf_insn *insn = insn_buf;
+ int off;
- switch (ctx_off) {
+ switch (si->off) {
case offsetof(struct __sk_buff, len):
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, len));
break;
case offsetof(struct __sk_buff, protocol):
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, protocol) != 2);
- *insn++ = BPF_LDX_MEM(BPF_H, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, protocol));
break;
case offsetof(struct __sk_buff, vlan_proto):
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_proto) != 2);
- *insn++ = BPF_LDX_MEM(BPF_H, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, vlan_proto));
break;
@@ -3005,17 +3006,17 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type, int dst_reg,
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, priority) != 4);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, priority));
else
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, priority));
break;
case offsetof(struct __sk_buff, ingress_ifindex):
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, skb_iif) != 4);
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, skb_iif));
break;
@@ -3023,17 +3024,17 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type, int dst_reg,
BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, ifindex) != 4);
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_buff, dev),
- dst_reg, src_reg,
+ si->dst_reg, si->src_reg,
offsetof(struct sk_buff, dev));
- *insn++ = BPF_JMP_IMM(BPF_JEQ, dst_reg, 0, 1);
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, dst_reg,
+ *insn++ = BPF_JMP_IMM(BPF_JEQ, si->dst_reg, 0, 1);
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->dst_reg,
offsetof(struct net_device, ifindex));
break;
case offsetof(struct __sk_buff, hash):
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, hash));
break;
@@ -3041,63 +3042,74 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type, int dst_reg,
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, mark));
else
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, mark));
break;
case offsetof(struct __sk_buff, pkt_type):
- return convert_skb_access(SKF_AD_PKTTYPE, dst_reg, src_reg, insn);
+ return convert_skb_access(SKF_AD_PKTTYPE, si->dst_reg,
+ si->src_reg, insn);
case offsetof(struct __sk_buff, queue_mapping):
- return convert_skb_access(SKF_AD_QUEUE, dst_reg, src_reg, insn);
+ return convert_skb_access(SKF_AD_QUEUE, si->dst_reg,
+ si->src_reg, insn);
case offsetof(struct __sk_buff, vlan_present):
return convert_skb_access(SKF_AD_VLAN_TAG_PRESENT,
- dst_reg, src_reg, insn);
+ si->dst_reg, si->src_reg, insn);
case offsetof(struct __sk_buff, vlan_tci):
return convert_skb_access(SKF_AD_VLAN_TAG,
- dst_reg, src_reg, insn);
+ si->dst_reg, si->src_reg, insn);
case offsetof(struct __sk_buff, cb[0]) ...
offsetof(struct __sk_buff, cb[4]):
BUILD_BUG_ON(FIELD_SIZEOF(struct qdisc_skb_cb, data) < 20);
prog->cb_access = 1;
- ctx_off -= offsetof(struct __sk_buff, cb[0]);
- ctx_off += offsetof(struct sk_buff, cb);
- ctx_off += offsetof(struct qdisc_skb_cb, data);
+ off = si->off;
+ off -= offsetof(struct __sk_buff, cb[0]);
+ off += offsetof(struct sk_buff, cb);
+ off += offsetof(struct qdisc_skb_cb, data);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_W, dst_reg, src_reg, ctx_off);
+ *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg,
+ si->src_reg, off);
else
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg, ctx_off);
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg,
+ si->src_reg, off);
break;
case offsetof(struct __sk_buff, tc_classid):
- ctx_off -= offsetof(struct __sk_buff, tc_classid);
- ctx_off += offsetof(struct sk_buff, cb);
- ctx_off += offsetof(struct qdisc_skb_cb, tc_classid);
+ BUILD_BUG_ON(FIELD_SIZEOF(struct qdisc_skb_cb, tc_classid) != 2);
+
+ off = si->off;
+ off -= offsetof(struct __sk_buff, tc_classid);
+ off += offsetof(struct sk_buff, cb);
+ off += offsetof(struct qdisc_skb_cb, tc_classid);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_H, dst_reg, src_reg, ctx_off);
+ *insn++ = BPF_STX_MEM(BPF_H, si->dst_reg,
+ si->src_reg, off);
else
- *insn++ = BPF_LDX_MEM(BPF_H, dst_reg, src_reg, ctx_off);
+ *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg,
+ si->src_reg, off);
break;
case offsetof(struct __sk_buff, data):
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_buff, data),
- dst_reg, src_reg,
+ si->dst_reg, si->src_reg,
offsetof(struct sk_buff, data));
break;
case offsetof(struct __sk_buff, data_end):
- ctx_off -= offsetof(struct __sk_buff, data_end);
- ctx_off += offsetof(struct sk_buff, cb);
- ctx_off += offsetof(struct bpf_skb_data_end, data_end);
- *insn++ = BPF_LDX_MEM(BPF_SIZEOF(void *), dst_reg, src_reg,
- ctx_off);
+ off = si->off;
+ off -= offsetof(struct __sk_buff, data_end);
+ off += offsetof(struct sk_buff, cb);
+ off += offsetof(struct bpf_skb_data_end, data_end);
+ *insn++ = BPF_LDX_MEM(BPF_SIZEOF(void *), si->dst_reg,
+ si->src_reg, off);
break;
case offsetof(struct __sk_buff, tc_index):
@@ -3105,110 +3117,107 @@ static u32 sk_filter_convert_ctx_access(enum bpf_access_type type, int dst_reg,
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, tc_index) != 2);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_H, dst_reg, src_reg,
+ *insn++ = BPF_STX_MEM(BPF_H, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, tc_index));
else
- *insn++ = BPF_LDX_MEM(BPF_H, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg,
offsetof(struct sk_buff, tc_index));
- break;
#else
if (type == BPF_WRITE)
- *insn++ = BPF_MOV64_REG(dst_reg, dst_reg);
+ *insn++ = BPF_MOV64_REG(si->dst_reg, si->dst_reg);
else
- *insn++ = BPF_MOV64_IMM(dst_reg, 0);
- break;
+ *insn++ = BPF_MOV64_IMM(si->dst_reg, 0);
#endif
+ break;
}
return insn - insn_buf;
}
static u32 sock_filter_convert_ctx_access(enum bpf_access_type type,
- int dst_reg, int src_reg,
- int ctx_off,
+ const struct bpf_insn *si,
struct bpf_insn *insn_buf,
struct bpf_prog *prog)
{
struct bpf_insn *insn = insn_buf;
- switch (ctx_off) {
+ switch (si->off) {
case offsetof(struct bpf_sock, bound_dev_if):
BUILD_BUG_ON(FIELD_SIZEOF(struct sock, sk_bound_dev_if) != 4);
if (type == BPF_WRITE)
- *insn++ = BPF_STX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_STX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sock, sk_bound_dev_if));
else
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sock, sk_bound_dev_if));
break;
case offsetof(struct bpf_sock, family):
BUILD_BUG_ON(FIELD_SIZEOF(struct sock, sk_family) != 2);
- *insn++ = BPF_LDX_MEM(BPF_H, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_H, si->dst_reg, si->src_reg,
offsetof(struct sock, sk_family));
break;
case offsetof(struct bpf_sock, type):
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sock, __sk_flags_offset));
- *insn++ = BPF_ALU32_IMM(BPF_AND, dst_reg, SK_FL_TYPE_MASK);
- *insn++ = BPF_ALU32_IMM(BPF_RSH, dst_reg, SK_FL_TYPE_SHIFT);
+ *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_TYPE_MASK);
+ *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_TYPE_SHIFT);
break;
case offsetof(struct bpf_sock, protocol):
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, src_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->src_reg,
offsetof(struct sock, __sk_flags_offset));
- *insn++ = BPF_ALU32_IMM(BPF_AND, dst_reg, SK_FL_PROTO_MASK);
- *insn++ = BPF_ALU32_IMM(BPF_RSH, dst_reg, SK_FL_PROTO_SHIFT);
+ *insn++ = BPF_ALU32_IMM(BPF_AND, si->dst_reg, SK_FL_PROTO_MASK);
+ *insn++ = BPF_ALU32_IMM(BPF_RSH, si->dst_reg, SK_FL_PROTO_SHIFT);
break;
}
return insn - insn_buf;
}
-static u32 tc_cls_act_convert_ctx_access(enum bpf_access_type type, int dst_reg,
- int src_reg, int ctx_off,
+static u32 tc_cls_act_convert_ctx_access(enum bpf_access_type type,
+ const struct bpf_insn *si,
struct bpf_insn *insn_buf,
struct bpf_prog *prog)
{
struct bpf_insn *insn = insn_buf;
- switch (ctx_off) {
+ switch (si->off) {
case offsetof(struct __sk_buff, ifindex):
BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, ifindex) != 4);
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct sk_buff, dev),
- dst_reg, src_reg,
+ si->dst_reg, si->src_reg,
offsetof(struct sk_buff, dev));
- *insn++ = BPF_LDX_MEM(BPF_W, dst_reg, dst_reg,
+ *insn++ = BPF_LDX_MEM(BPF_W, si->dst_reg, si->dst_reg,
offsetof(struct net_device, ifindex));
break;
default:
- return sk_filter_convert_ctx_access(type, dst_reg, src_reg,
- ctx_off, insn_buf, prog);
+ return sk_filter_convert_ctx_access(type, si, insn_buf, prog);
}
return insn - insn_buf;
}
-static u32 xdp_convert_ctx_access(enum bpf_access_type type, int dst_reg,
- int src_reg, int ctx_off,
+static u32 xdp_convert_ctx_access(enum bpf_access_type type,
+ const struct bpf_insn *si,
struct bpf_insn *insn_buf,
struct bpf_prog *prog)
{
struct bpf_insn *insn = insn_buf;
- switch (ctx_off) {
+ switch (si->off) {
case offsetof(struct xdp_md, data):
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct xdp_buff, data),
- dst_reg, src_reg,
+ si->dst_reg, si->src_reg,
offsetof(struct xdp_buff, data));
break;
case offsetof(struct xdp_md, data_end):
*insn++ = BPF_LDX_MEM(BPF_FIELD_SIZEOF(struct xdp_buff, data_end),
- dst_reg, src_reg,
+ si->dst_reg, si->src_reg,
offsetof(struct xdp_buff, data_end));
break;
}
--
1.9.3
^ permalink raw reply related
* [PATCH net-next v2 0/2] More flexible BPF cb access
From: Daniel Borkmann @ 2017-01-12 10:51 UTC (permalink / raw)
To: davem; +Cc: alexei.starovoitov, netdev, Daniel Borkmann
This patch improves BPF's cb access by allowing b/h/w/dw
access variants on it. For details, please see individual
patches.
Thanks!
v1 -> v2:
- Fix typo in test case description spotted by Quentin
- Rest as-is
Daniel Borkmann (2):
bpf: pass original insn directly to convert_ctx_access
bpf: allow b/h/w/dw access for bpf's cb in ctx
include/linux/bpf.h | 7 +-
kernel/bpf/verifier.c | 11 +-
kernel/trace/bpf_trace.c | 15 +-
net/core/filter.c | 176 ++++++-----
tools/testing/selftests/bpf/test_verifier.c | 442 +++++++++++++++++++++++++++-
5 files changed, 563 insertions(+), 88 deletions(-)
--
1.9.3
^ permalink raw reply
* Re: net: wireless: ath: wil6210: constify cfg80211_ops structures
From: Kalle Valo @ 2017-01-12 10:55 UTC (permalink / raw)
To: Bhumika Goyal
Cc: julia.lawall, qca_merez, kvalo, linux-wireless, wil6210, netdev,
linux-kernel, Bhumika Goyal
In-Reply-To: <1482014667-27082-1-git-send-email-bhumirks@gmail.com>
Bhumika Goyal <bhumirks@gmail.com> wrote:
> cfg80211_ops structures are only passed as an argument to the function
> wiphy_new. This argument is of type const, so cfg80211_ops strutures
> having this property can be declared as const.
> Done using Coccinelle
>
> @r1 disable optional_qualifier @
> identifier i;
> position p;
> @@
> static struct cfg80211_ops i@p = {...};
>
> @ok1@
> identifier r1.i;
> position p;
> @@
> wiphy_new(&i@p,...)
>
> @bad@
> position p!={r1.p,ok1.p};
> identifier r1.i;
> @@
> i@p
>
> @depends on !bad disable optional_qualifier@
> identifier r1.i;
> @@
> +const
> struct cfg80211_ops i;
>
> File size before:
> text data bss dec hex filename
> 18133 6632 0 24765 60bd wireless/ath/wil6210/cfg80211.o
>
> File size after:
> text data bss dec hex filename
> 18933 5832 0 24765 60bd wireless/ath/wil6210/cfg80211.o
>
> Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Patch applied to ath-next branch of ath.git, thanks.
b59eb96181e7 wil6210: constify cfg80211_ops structures
--
https://patchwork.kernel.org/patch/9479127/
Documentation about submitting wireless patches and checking status
from patchwork:
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* Re: [1/2] ath9k: ar9002_mac: kill off ACCESS_ONCE()
From: Kalle Valo @ 2017-01-12 11:00 UTC (permalink / raw)
To: Mark Rutland
Cc: linux-kernel, ath9k-devel, kvalo, linux-wireless, ath9k-devel,
netdev, Mark Rutland
In-Reply-To: <1482864599-19995-2-git-send-email-mark.rutland@arm.com>
Mark Rutland <mark.rutland@arm.com> wrote:
> For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
> preference to ACCESS_ONCE(), and new code is expected to use one of the
> former. So far, there's been no reason to change most existing uses of
> ACCESS_ONCE(), as these aren't currently harmful.
>
> However, for some new features (e.g. KTSAN / Kernel Thread Sanitizer),
> it is necessary to instrument reads and writes separately, which is not
> possible with ACCESS_ONCE(). This distinction is critical to correct
> operation.
>
> It's possible to transform the bulk of kernel code using the Coccinelle
> script below. However, for some files (including the ath9k ar9002 mac
> driver), this mangles the formatting. As a preparatory step, this patch
> converts the driver to use {READ,WRITE}_ONCE() without said mangling.
>
> ----
> virtual patch
>
> @ depends on patch @
> expression E1, E2;
> @@
>
> - ACCESS_ONCE(E1) = E2
> + WRITE_ONCE(E1, E2)
>
> @ depends on patch @
> expression E;
> @@
>
> - ACCESS_ONCE(E)
> + READ_ONCE(E)
> ----
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: ath9k-devel@qca.qualcomm.com
> Cc: Kalle Valo <kvalo@codeaurora.org>
> Cc: linux-wireless@vger.kernel.org
> Cc: ath9k-devel@lists.ath9k.org
> Cc: netdev@vger.kernel.org
2 patches applied to ath-next branch of ath.git, thanks.
d5a3a76a9cb8 ath9k: ar9002_mac: kill off ACCESS_ONCE()
50f3818196f5 ath9k: ar9003_mac: kill off ACCESS_ONCE()
--
https://patchwork.kernel.org/patch/9489799/
Documentation about submitting wireless patches and checking status
from patchwork:
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
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