* Re: [net] Revert "net: core: maybe return -EEXIST in __dev_alloc_name"
From: Michael Ellerman @ 2017-12-19 12:28 UTC (permalink / raw)
To: Johannes Berg
Cc: netdev@vger.kernel.org, Jouni Malinen, Rasmus Villemoes,
Johannes Berg, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20171202074155.29146-1-johannes@sipsolutions.net>
Hi Johannes,
> From: Johannes Berg <johannes.berg@intel.com>
>
> This reverts commit d6f295e9def0; some userspace (in the case
> we noticed it's wpa_supplicant), is relying on the current
> error code to determine that a fixed name interface already
> exists.
>
> Reported-by: Jouni Malinen <j@w1.fi>
> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
> ---
> net/core/dev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
This revert seems to have broken networking on one of my powerpc
machines, according to git bisect.
The symptom is DHCP fails and I don't get a link, I didn't dig any
further than that. I can if it's helpful.
I think the problem is that 87c320e51519 ("net: core: dev_get_valid_name
is now the same as dev_alloc_name_ns") only makes sense while
d6f295e9def0 remains in the tree.
ie. before the entire series, dev_get_valid_name() would return EEXIST,
and that was retained when 87c320e51519 was merged, but now that
d6f295e9def0 has been reverted dev_get_valid_name() is returning ENFILE.
I can get the network up again if I also revert 87c320e51519 ("net:
core: dev_get_valid_name is now the same as dev_alloc_name_ns"), or with
the gross patch below.
cheers
diff --git a/net/core/dev.c b/net/core/dev.c
index f47e96b62308..d0304461ad32 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1146,7 +1146,11 @@ EXPORT_SYMBOL(dev_alloc_name);
int dev_get_valid_name(struct net *net, struct net_device *dev,
const char *name)
{
- return dev_alloc_name_ns(net, dev, name);
+ int rc = dev_alloc_name_ns(net, dev, name);
+ if (rc == -ENFILE)
+ rc = -EEXIST;
+
+ return rc;
}
EXPORT_SYMBOL(dev_get_valid_name);
^ permalink raw reply related
* Re: [PATCHv3 net-next 00/14] net: sched: sch: introduce extack support
From: Jamal Hadi Salim @ 2017-12-19 12:45 UTC (permalink / raw)
To: Alexander Aring; +Cc: xiyou.wangcong, jiri, davem, netdev, kernel, David Ahern
In-Reply-To: <20171218224513.29836-1-aring@mojatatu.com>
Saw some tiny typos in the commit log but lets please not hold
back the submission so we can have the rest of the
(many) outstanding patches coming in. So for this patch set:
Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
cheers,
jamal
On 17-12-18 05:44 PM, Alexander Aring wrote:
> Hi,
>
> this patch series basically add support for extack in common qdisc handling.
> Additional it adds extack pointer to common qdisc callback handling this
> offers per qdisc implementation to setting the extack message for each
> failure over netlink.
>
> The extack message will be set deeper in qdisc functions but going not
> deeper as net core api. For qdisc module callback handling, the extack
> will not be set. This will be part of per qdisc extack handling.
>
> I also want to prepare patches to handle extack per qdisc module...
> so there will come a lot of more patches, just cut them down to make
> it reviewable.
>
> There are some above 80-chars width warnings, which I ignore because
> it looks more ugly otherwise.
>
> This patch-series based on patches by David Ahren which gave me some
> hints how to deal with extack support.
>
> Cc: David Ahern <dsahern@gmail.com>
>
> changes since v3:
> - remove patch 2/2 lib: nlattr: set extack msg if validate_nla fails since
> David Ahren has a better solution
> - Remove check on net admin permission since -EPERM indicates it already
> - Change rtab to "rate table" - this is what it's stands for
> - Fix cbs *not* support messages
> - Fix tcf block error message for allocation, allocation will be still there
> because there are multiple places which returns -ENOMEM
> - Finnally also took care about sch_atm, sorry somehow I forgot this one and
> I hope I didn't forgot any sch implementation to add new callback parameters
>
> changes since v2:
> - add fix coding style patch to catch all checkpatch warnings
> - add patch for setting netlink extack msg if validate_nla fails
> - changes in handle generic qdisc errors
> - remove NL_SET_ERR_MSG from memory allocation errors
> - remove NL_SET_ERR_MSG from device not found
> - change STAB to table size
> - add various new patches to add extack support for common
> TC functions like qdisc_get_rtab, tcf_block_get, qdisc_alloc
> and qdisc_create_dflt - users which are interessted in the
> detailed error messages can assign extack, otherwise NULL.
> - Add sch_cbq as example for qdisc_ops callback: init,
> qdisc_class_ops callbacks: change and graft
> - Add sch_cbs as example for qdisc_ops callback: change
> - Add sch_drr as example for qdisc_class ops callbacks: tcf_block
>
> - Alex
>
> Alexander Aring (14):
> net: sched: fix coding style issues
> net: sched: sch_api: handle generic qdisc errors
> net: sched: sch: add extack for init callback
> net: sched: sch: add extack for change qdisc ops
> net: sched: sch: add extack to change class
> net: sched: sch: add extack for block callback
> net: sched: sch: add extack for graft callback
> net: sch: api: add extack support in qdisc_get_rtab
> net: sch: api: add extack support in tcf_block_get
> net: sch: api: add extack support in qdisc_alloc
> net: sch: api: add extack support in qdisc_create_dflt
> net: sch: sch_cbq: add extack support
> net: sch: sch_cbs: add extack support
> net: sch: sch_drr: add extack support
>
> include/net/pkt_cls.h | 6 +-
> include/net/pkt_sched.h | 6 +-
> include/net/sch_generic.h | 21 ++++--
> net/sched/act_police.c | 4 +-
> net/sched/cls_api.c | 17 +++--
> net/sched/sch_api.c | 172 ++++++++++++++++++++++++++++++++--------------
> net/sched/sch_atm.c | 23 ++++---
> net/sched/sch_cbq.c | 78 ++++++++++++++-------
> net/sched/sch_cbs.c | 31 ++++++---
> net/sched/sch_choke.c | 8 ++-
> net/sched/sch_codel.c | 8 ++-
> net/sched/sch_drr.c | 40 +++++++----
> net/sched/sch_dsmark.c | 19 +++--
> net/sched/sch_fifo.c | 11 +--
> net/sched/sch_fq.c | 8 ++-
> net/sched/sch_fq_codel.c | 13 ++--
> net/sched/sch_generic.c | 25 ++++---
> net/sched/sch_gred.c | 13 ++--
> net/sched/sch_hfsc.c | 28 ++++----
> net/sched/sch_hhf.c | 8 ++-
> net/sched/sch_htb.c | 29 ++++----
> net/sched/sch_ingress.c | 20 ++++--
> net/sched/sch_mq.c | 8 ++-
> net/sched/sch_mqprio.c | 7 +-
> net/sched/sch_multiq.c | 19 ++---
> net/sched/sch_netem.c | 10 +--
> net/sched/sch_pie.c | 8 ++-
> net/sched/sch_plug.c | 6 +-
> net/sched/sch_prio.c | 18 +++--
> net/sched/sch_qfq.c | 22 +++---
> net/sched/sch_red.c | 13 ++--
> net/sched/sch_sfb.c | 20 +++---
> net/sched/sch_sfq.c | 8 ++-
> net/sched/sch_tbf.c | 21 +++---
> net/sched/sch_teql.c | 3 +-
> 35 files changed, 486 insertions(+), 265 deletions(-)
>
^ permalink raw reply
* Re: INFO: task hung in cleanup_net
From: Dmitry Vyukov @ 2017-12-19 12:47 UTC (permalink / raw)
To: syzbot
Cc: LKML, Ingo Molnar, Peter Zijlstra, syzkaller-bugs, David Miller,
dsahern, Florian Westphal, Daniel Borkmann, Xin Long,
jakub.kicinski, mschiffer, Vladislav Yasevich, Jiri Benc, netdev
In-Reply-To: <001a113eca40eaee1c0560b0aad0@google.com>
On Tue, Dec 19, 2017 at 1:33 PM, syzbot
<bot+b17f10c8a8c693b40723d40d6553fbc54d197679@syzkaller.appspotmail.com>
wrote:
> Hello,
>
> syzkaller hit the following crash on
> e40fd8d6b4d9f59b160faa1736f78fc07533ff37
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console output is attached.
>
> Unfortunately, I don't have any reproducer for this bug yet.
>
>
> sctp: sctp_transport_update_pmtu: Reported pmtu 508 too low, using default
> minimum of 512
> sctp: sctp_transport_update_pmtu: Reported pmtu 508 too low, using default
> minimum of 512
> sctp: sctp_transport_update_pmtu: Reported pmtu 508 too low, using default
> minimum of 512
> INFO: task kworker/u4:11:3785 blocked for more than 120 seconds.
> Not tainted 4.15.0-rc2-next-20171207+ #61
> "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
> kworker/u4:11 D16448 3785 2 0x80000000
> Workqueue: netns cleanup_net
> Call Trace:
> context_switch kernel/sched/core.c:2800 [inline]
> __schedule+0x8eb/0x2060 kernel/sched/core.c:3376
> schedule+0xf5/0x430 kernel/sched/core.c:3435
> schedule_preempt_disabled+0x10/0x20 kernel/sched/core.c:3493
> __mutex_lock_common kernel/locking/mutex.c:833 [inline]
> __mutex_lock+0xaad/0x1a80 kernel/locking/mutex.c:893
> mutex_lock_nested+0x16/0x20 kernel/locking/mutex.c:908
> rtnl_lock+0x17/0x20 net/core/rtnetlink.c:74
> cleanup_net+0x24c/0xb60 net/core/net_namespace.c:453
> process_one_work+0xbfd/0x1bc0 kernel/workqueue.c:2113
> worker_thread+0x223/0x1990 kernel/workqueue.c:2247
> kthread+0x37a/0x440 kernel/kthread.c:238
> ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:524
>
> Showing all locks held in the system:
> 2 locks held by khungtaskd/672:
> #0: (rcu_read_lock){....}, at: [<00000000b9bef8ab>]
> check_hung_uninterruptible_tasks kernel/hung_task.c:175 [inline]
> #0: (rcu_read_lock){....}, at: [<00000000b9bef8ab>] watchdog+0x1c5/0xd60
> kernel/hung_task.c:249
> #1: (tasklist_lock){.+.+}, at: [<000000006d6acf8b>]
> debug_show_all_locks+0xd3/0x400 kernel/locking/lockdep.c:4554
> 1 lock held by rsyslogd/2970:
> #0: (&f->f_pos_lock){+.+.}, at: [<000000001cede688>]
> __fdget_pos+0x131/0x1a0 fs/file.c:765
> 2 locks held by getty/3052:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3053:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3054:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3055:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3056:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3057:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3058:
> #0: (&tty->ldisc_sem){++++}, at: [<000000004e0245ba>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000ff863b18>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 1 lock held by syz-executor2/3320:
> #0: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 4 locks held by kworker/u4:11/3785:
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> __write_once_size include/linux/compiler.h:212 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> atomic64_set arch/x86/include/asm/atomic64_64.h:34 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> atomic_long_set include/asm-generic/atomic-long.h:57 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> set_work_data kernel/workqueue.c:619 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> set_work_pool_and_clear_pending kernel/workqueue.c:646 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<0000000087d81703>]
> process_one_work+0xad4/0x1bc0 kernel/workqueue.c:2084
> #1: (net_cleanup_work){+.+.}, at: [<000000008a817b5c>]
> process_one_work+0xb2f/0x1bc0 kernel/workqueue.c:2088
> #2: (net_mutex){+.+.}, at: [<0000000079150fd8>] cleanup_net+0x247/0xb60
> net/core/net_namespace.c:450
> #3: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 3 locks held by kworker/0:6/14978:
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> __write_once_size include/linux/compiler.h:212 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> atomic64_set arch/x86/include/asm/atomic64_64.h:34 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> atomic_long_set include/asm-generic/atomic-long.h:57 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> set_work_data kernel/workqueue.c:619 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> set_work_pool_and_clear_pending kernel/workqueue.c:646 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<0000000087d81703>]
> process_one_work+0xad4/0x1bc0 kernel/workqueue.c:2084
> #1: ((addr_chk_work).work){+.+.}, at: [<000000008a817b5c>]
> process_one_work+0xb2f/0x1bc0 kernel/workqueue.c:2088
> #2: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 1 lock held by syz-executor2/15852:
> #0: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 1 lock held by syz-executor7/15958:
> #0: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 1 lock held by syz-executor7/15961:
> #0: (rtnl_mutex){+.+.}, at: [<0000000063c47ced>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
>
> =============================================
>
> NMI backtrace for cpu 1
> CPU: 1 PID: 672 Comm: khungtaskd Not tainted 4.15.0-rc2-next-20171207+ #61
> Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
> Google 01/01/2011
> Call Trace:
> __dump_stack lib/dump_stack.c:17 [inline]
> dump_stack+0x194/0x257 lib/dump_stack.c:53
> nmi_cpu_backtrace+0x1d2/0x210 lib/nmi_backtrace.c:103
> nmi_trigger_cpumask_backtrace+0x122/0x180 lib/nmi_backtrace.c:62
> arch_trigger_cpumask_backtrace+0x14/0x20 arch/x86/kernel/apic/hw_nmi.c:38
> trigger_all_cpu_backtrace include/linux/nmi.h:138 [inline]
> check_hung_task kernel/hung_task.c:132 [inline]
> check_hung_uninterruptible_tasks kernel/hung_task.c:190 [inline]
> watchdog+0x90c/0xd60 kernel/hung_task.c:249
> kthread+0x37a/0x440 kernel/kthread.c:238
> ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:524
> Sending NMI from CPU 1 to CPUs 0:
> NMI backtrace for cpu 0
> CPU: 0 PID: 15938 Comm: syz-executor7 Not tainted 4.15.0-rc2-next-20171207+
> #61
> Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
> Google 01/01/2011
> RIP: 0010:inb arch/x86/include/asm/io.h:348 [inline]
> RIP: 0010:io_serial_in+0x6b/0x90 drivers/tty/serial/8250/8250_port.c:434
> RSP: 0018:ffff8801c1c173e8 EFLAGS: 00000002
> RAX: dffffc0000000000 RBX: 00000000000003fd RCX: 0000000000000000
> RDX: 00000000000003fd RSI: ffffc90001c88000 RDI: ffffffff880fa9c0
> RBP: ffff8801c1c173f8 R08: 0000000000000002 R09: 000000000000000c
> R10: 0000000000000000 R11: ffffffff87896d20 R12: ffffffff880fa980
> R13: 0000000000000020 R14: fffffbfff101f577 R15: fffffbfff101f53a
> FS: 00007f1ef8fad700(0000) GS:ffff8801db200000(0000) knlGS:0000000000000000
> CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> CR2: 00007fbea91b6000 CR3: 00000001d0aaa000 CR4: 00000000001406f0
> DR0: 0000000020001000 DR1: 0000000020001000 DR2: 0000000020001020
> DR3: 0000000020000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600
> Call Trace:
> serial_in drivers/tty/serial/8250/8250.h:111 [inline]
> wait_for_xmitr+0x93/0x1e0 drivers/tty/serial/8250/8250_port.c:2033
> serial8250_console_putchar+0x1f/0x60
> drivers/tty/serial/8250/8250_port.c:3170
> uart_console_write+0xac/0xe0 drivers/tty/serial/serial_core.c:1858
> serial8250_console_write+0x647/0xa20
> drivers/tty/serial/8250/8250_port.c:3236
> univ8250_console_write+0x5f/0x70 drivers/tty/serial/8250/8250_core.c:590
> call_console_drivers kernel/printk/printk.c:1574 [inline]
> console_unlock+0x788/0xd70 kernel/printk/printk.c:2233
> vprintk_emit+0x4ad/0x590 kernel/printk/printk.c:1757
> vprintk_default+0x28/0x30 kernel/printk/printk.c:1796
> vprintk_func+0x57/0xc0 kernel/printk/printk_safe.c:379
> printk+0xaa/0xca kernel/printk/printk.c:1829
> __dev_set_promiscuity+0x2a4/0x630 net/core/dev.c:6609
> __dev_change_flags+0x559/0x990 net/core/dev.c:6826
> dev_change_flags+0x88/0x140 net/core/dev.c:6886
> dev_ifsioc+0x60d/0x9b0 net/core/dev_ioctl.c:257
> dev_ioctl+0x2c2/0xf90 net/core/dev_ioctl.c:566
> sock_do_ioctl+0x94/0xb0 net/socket.c:971
> sock_ioctl+0x2c2/0x440 net/socket.c:1061
> vfs_ioctl fs/ioctl.c:46 [inline]
> do_vfs_ioctl+0x1b1/0x1530 fs/ioctl.c:686
> SYSC_ioctl fs/ioctl.c:701 [inline]
> SyS_ioctl+0x8f/0xc0 fs/ioctl.c:692
> entry_SYSCALL_64_fastpath+0x1f/0x96
> RIP: 0033:0x452a39
> RSP: 002b:00007f1ef8facc58 EFLAGS: 00000212 ORIG_RAX: 0000000000000010
> RAX: ffffffffffffffda RBX: 00007f1ef8fad700 RCX: 0000000000452a39
> RDX: 00000000208a3fe0 RSI: 0000000000008914 RDI: 0000000000000019
> RBP: 0000000000a6f880 R08: 0000000000000000 R09: 0000000000000000
> R10: 0000000000000000 R11: 0000000000000212 R12: 0000000000000000
> R13: 0000000000a6f7ff R14: 00007f1ef8fad9c0 R15: 0000000000000002
> Code: 24 d9 00 00 00 49 8d 7c 24 40 48 b8 00 00 00 00 00 fc ff df 48 89 fa
> 48 c1 ea 03 d3 e3 80 3c 02 00 75 17 41 03 5c 24 40 89 da ec <5b> 0f b6 c0 41
> 5c 5d c3 e8 88 ad 18 ff eb c2 e8 e1 ad 18 ff eb
This looks like +rtnetlink issue.
> ---
> This bug is generated by a dumb bot. It may contain errors.
> See https://goo.gl/tpsmEJ for details.
> Direct all questions to syzkaller@googlegroups.com.
> Please credit me with: Reported-by: syzbot <syzkaller@googlegroups.com>
>
> syzbot will keep track of this bug report.
> Once a fix for this bug is merged into any tree, reply to this email with:
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> To mark this as a duplicate of another syzbot report, please reply with:
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^ permalink raw reply
* Re: INFO: task hung in bpf_exit_net
From: Dmitry Vyukov @ 2017-12-19 12:47 UTC (permalink / raw)
To: syzbot
Cc: LKML, Ingo Molnar, Peter Zijlstra, syzkaller-bugs, David Miller,
dsahern, Florian Westphal, Daniel Borkmann, Xin Long,
jakub.kicinski, mschiffer, Vladislav Yasevich, Jiri Benc, netdev
In-Reply-To: <001a1143fd00a8cc790560b0b552@google.com>
On Tue, Dec 19, 2017 at 1:36 PM, syzbot
<bot+21b498fc12cf2041655f8e1eeae0733807d794b3@syzkaller.appspotmail.com>
wrote:
> Hello,
>
> syzkaller hit the following crash on
> 7ceb97a071e80f1b5e4cd5a36de135612a836388
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
> compiler: gcc (GCC) 7.1.1 20170620
> .config is attached
> Raw console output is attached.
>
> Unfortunately, I don't have any reproducer for this bug yet.
>
>
> sctp: sctp_transport_update_pmtu: Reported pmtu 508 too low, using default
> minimum of 512
> INFO: task kworker/u4:0:5 blocked for more than 120 seconds.
> Not tainted 4.15.0-rc2-next-20171205+ #59
> "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
> kworker/u4:0 D15808 5 2 0x80000000
> Workqueue: netns cleanup_net
> Call Trace:
> context_switch kernel/sched/core.c:2800 [inline]
> __schedule+0x8eb/0x2060 kernel/sched/core.c:3376
> schedule+0xf5/0x430 kernel/sched/core.c:3435
> schedule_preempt_disabled+0x10/0x20 kernel/sched/core.c:3493
> __mutex_lock_common kernel/locking/mutex.c:833 [inline]
> __mutex_lock+0xaad/0x1a80 kernel/locking/mutex.c:893
> mutex_lock_nested+0x16/0x20 kernel/locking/mutex.c:908
> rtnl_lock+0x17/0x20 net/core/rtnetlink.c:74
> tc_action_net_exit include/net/act_api.h:125 [inline]
> bpf_exit_net+0x1a2/0x340 net/sched/act_bpf.c:408
> ops_exit_list.isra.6+0xae/0x150 net/core/net_namespace.c:142
> cleanup_net+0x5c7/0xb60 net/core/net_namespace.c:484
> process_one_work+0xbfd/0x1bc0 kernel/workqueue.c:2113
> worker_thread+0x223/0x1990 kernel/workqueue.c:2247
> kthread+0x37a/0x440 kernel/kthread.c:238
> ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:517
>
> Showing all locks held in the system:
> 4 locks held by kworker/u4:0/5:
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> __write_once_size include/linux/compiler.h:212 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> atomic64_set arch/x86/include/asm/atomic64_64.h:34 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> atomic_long_set include/asm-generic/atomic-long.h:57 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> set_work_data kernel/workqueue.c:619 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> set_work_pool_and_clear_pending kernel/workqueue.c:646 [inline]
> #0: ((wq_completion)"%s""netns"){+.+.}, at: [<00000000b9f061a2>]
> process_one_work+0xad4/0x1bc0 kernel/workqueue.c:2084
> #1: (net_cleanup_work){+.+.}, at: [<000000006c7c48a3>]
> process_one_work+0xb2f/0x1bc0 kernel/workqueue.c:2088
> #2: (net_mutex){+.+.}, at: [<00000000bf4709f3>] cleanup_net+0x247/0xb60
> net/core/net_namespace.c:450
> #3: (rtnl_mutex){+.+.}, at: [<0000000053390f0b>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 3 locks held by kworker/1:0/17:
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> __write_once_size include/linux/compiler.h:212 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> atomic64_set arch/x86/include/asm/atomic64_64.h:34 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> atomic_long_set include/asm-generic/atomic-long.h:57 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> set_work_data kernel/workqueue.c:619 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> set_work_pool_and_clear_pending kernel/workqueue.c:646 [inline]
> #0: ((wq_completion)"%s"("ipv6_addrconf")){+.+.}, at: [<00000000b9f061a2>]
> process_one_work+0xad4/0x1bc0 kernel/workqueue.c:2084
> #1: ((addr_chk_work).work){+.+.}, at: [<000000006c7c48a3>]
> process_one_work+0xb2f/0x1bc0 kernel/workqueue.c:2088
> #2: (rtnl_mutex){+.+.}, at: [<0000000053390f0b>] rtnl_lock+0x17/0x20
> net/core/rtnetlink.c:74
> 2 locks held by khungtaskd/675:
> #0: (rcu_read_lock){....}, at: [<00000000587c8471>]
> check_hung_uninterruptible_tasks kernel/hung_task.c:175 [inline]
> #0: (rcu_read_lock){....}, at: [<00000000587c8471>] watchdog+0x1c5/0xd60
> kernel/hung_task.c:249
> #1: (tasklist_lock){.+.+}, at: [<000000005288685e>]
> debug_show_all_locks+0xd3/0x400 kernel/locking/lockdep.c:4554
> 1 lock held by rsyslogd/2974:
> #0: (&f->f_pos_lock){+.+.}, at: [<0000000011e00499>]
> __fdget_pos+0x131/0x1a0 fs/file.c:770
> 2 locks held by getty/3056:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3057:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3058:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3059:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3060:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3061:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
> 2 locks held by getty/3062:
> #0: (&tty->ldisc_sem){++++}, at: [<00000000b9fd70a9>]
> ldsem_down_read+0x37/0x40 drivers/tty/tty_ldsem.c:365
> #1: (&ldata->atomic_read_lock){+.+.}, at: [<00000000abb3bd08>]
> n_tty_read+0x2f2/0x1a10 drivers/tty/n_tty.c:2131
>
> =============================================
>
> NMI backtrace for cpu 0
> CPU: 0 PID: 675 Comm: khungtaskd Not tainted 4.15.0-rc2-next-20171205+ #59
> Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
> Google 01/01/2011
> Call Trace:
> __dump_stack lib/dump_stack.c:17 [inline]
> dump_stack+0x194/0x257 lib/dump_stack.c:53
> nmi_cpu_backtrace+0x1d2/0x210 lib/nmi_backtrace.c:103
> nmi_trigger_cpumask_backtrace+0x122/0x180 lib/nmi_backtrace.c:62
> arch_trigger_cpumask_backtrace+0x14/0x20 arch/x86/kernel/apic/hw_nmi.c:38
> trigger_all_cpu_backtrace include/linux/nmi.h:138 [inline]
> check_hung_task kernel/hung_task.c:132 [inline]
> check_hung_uninterruptible_tasks kernel/hung_task.c:190 [inline]
> watchdog+0x90c/0xd60 kernel/hung_task.c:249
> kthread+0x37a/0x440 kernel/kthread.c:238
> ret_from_fork+0x24/0x30 arch/x86/entry/entry_64.S:517
> Sending NMI from CPU 0 to CPUs 1:
> NMI backtrace for cpu 1
> CPU: 1 PID: 13156 Comm: syz-executor7 Not tainted 4.15.0-rc2-next-20171205+
> #59
> Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
> Google 01/01/2011
> task: 000000005209c120 task.stack: 00000000ffaab0e8
> RIP: 0010:inb arch/x86/include/asm/io.h:348 [inline]
> RIP: 0010:io_serial_in+0x6b/0x90 drivers/tty/serial/8250/8250_port.c:434
> RSP: 0018:ffff8801c0a16e70 EFLAGS: 00000002
> RAX: dffffc0000000000 RBX: 00000000000003fd RCX: 0000000000000000
> RDX: 00000000000003fd RSI: ffffc90003745000 RDI: ffffffff87cf1a40
> RBP: ffff8801c0a16e80 R08: 0000000000000005 R09: 000000000000000c
> R10: 0000000000000000 R11: ffffffff8748dd20 R12: ffffffff87cf1a00
> R13: 0000000000000020 R14: fffffbfff0f9e387 R15: fffffbfff0f9e34a
> FS: 00007f6d52e3f700(0000) GS:ffff8801db500000(0000) knlGS:0000000000000000
> CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> CR2: 000000c42005de80 CR3: 00000001c368a000 CR4: 00000000001406e0
> DR0: 0000000020000000 DR1: 0000000000000000 DR2: 0000000000000000
> DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600
> Call Trace:
> serial_in drivers/tty/serial/8250/8250.h:111 [inline]
> wait_for_xmitr+0x93/0x1e0 drivers/tty/serial/8250/8250_port.c:2033
> serial8250_console_putchar+0x1f/0x60
> drivers/tty/serial/8250/8250_port.c:3170
> uart_console_write+0xac/0xe0 drivers/tty/serial/serial_core.c:1858
> serial8250_console_write+0x647/0xa20
> drivers/tty/serial/8250/8250_port.c:3236
> univ8250_console_write+0x5f/0x70 drivers/tty/serial/8250/8250_core.c:590
> call_console_drivers kernel/printk/printk.c:1574 [inline]
> console_unlock+0x788/0xd70 kernel/printk/printk.c:2233
> vprintk_emit+0x4ad/0x590 kernel/printk/printk.c:1757
> vprintk_default+0x28/0x30 kernel/printk/printk.c:1796
> vprintk_func+0x57/0xc0 kernel/printk/printk_safe.c:379
> printk+0xaa/0xca kernel/printk/printk.c:1829
> nla_parse+0x374/0x3d0 lib/nlattr.c:257
> nlmsg_parse include/net/netlink.h:398 [inline]
> nl80211_dump_wiphy_parse.isra.37.constprop.83+0x138/0x5c0
> net/wireless/nl80211.c:1920
> nl80211_dump_interface+0x596/0x820 net/wireless/nl80211.c:2660
> genl_lock_dumpit+0x68/0x90 net/netlink/genetlink.c:480
> netlink_dump+0x48c/0xce0 net/netlink/af_netlink.c:2186
> __netlink_dump_start+0x4f0/0x6d0 net/netlink/af_netlink.c:2283
> genl_family_rcv_msg+0xd27/0xfc0 net/netlink/genetlink.c:548
> genl_rcv_msg+0xb2/0x140 net/netlink/genetlink.c:624
> netlink_rcv_skb+0x216/0x440 net/netlink/af_netlink.c:2405
> genl_rcv+0x28/0x40 net/netlink/genetlink.c:635
> netlink_unicast_kernel net/netlink/af_netlink.c:1272 [inline]
> netlink_unicast+0x4e8/0x6f0 net/netlink/af_netlink.c:1298
> netlink_sendmsg+0xa4a/0xe70 net/netlink/af_netlink.c:1861
> sock_sendmsg_nosec net/socket.c:636 [inline]
> sock_sendmsg+0xca/0x110 net/socket.c:646
> sock_write_iter+0x320/0x5e0 net/socket.c:915
> call_write_iter include/linux/fs.h:1776 [inline]
> new_sync_write fs/read_write.c:469 [inline]
> __vfs_write+0x68a/0x970 fs/read_write.c:482
> vfs_write+0x18f/0x510 fs/read_write.c:544
> SYSC_write fs/read_write.c:589 [inline]
> SyS_write+0xef/0x220 fs/read_write.c:581
> entry_SYSCALL_64_fastpath+0x1f/0x96
> RIP: 0033:0x4529d9
> RSP: 002b:00007f6d52e3ec58 EFLAGS: 00000212 ORIG_RAX: 0000000000000001
> RAX: ffffffffffffffda RBX: 00007f6d52e3f700 RCX: 00000000004529d9
> RDX: 0000000000000024 RSI: 0000000020454000 RDI: 0000000000000016
> RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000
> R10: 0000000000000000 R11: 0000000000000212 R12: 0000000000000000
> R13: 0000000000a6f7ff R14: 00007f6d52e3f9c0 R15: 0000000000000000
> Code: 24 d9 00 00 00 49 8d 7c 24 40 48 b8 00 00 00 00 00 fc ff df 48 89 fa
> 48 c1 ea 03 d3 e3 80 3c 02 00 75 17 41 03 5c 24 40 89 da ec <5b> 0f b6 c0 41
> 5c 5d c3 e8 38 b0 18 ff eb c2 e8 91 b0 18 ff eb
>
>
> ---
> This bug is generated by a dumb bot. It may contain errors.
> See https://goo.gl/tpsmEJ for details.
> Direct all questions to syzkaller@googlegroups.com.
> Please credit me with: Reported-by: syzbot <syzkaller@googlegroups.com>
>
> syzbot will keep track of this bug report.
> Once a fix for this bug is merged into any tree, reply to this email with:
> #syz fix: exact-commit-title
> To mark this as a duplicate of another syzbot report, please reply with:
> #syz dup: exact-subject-of-another-report
> If it's a one-off invalid bug report, please reply with:
> #syz invalid
> Note: if the crash happens again, it will cause creation of a new bug
> report.
> Note: all commands must start from beginning of the line in the email body.
>
> --
> You received this message because you are subscribed to the Google Groups
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> To view this discussion on the web visit
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> For more options, visit https://groups.google.com/d/optout.
This looks like +rtnetlink issue.
^ permalink raw reply
* BUG: unable to handle kernel NULL pointer dereference in tc_fill_qdisc
From: syzbot @ 2017-12-19 12:49 UTC (permalink / raw)
To: davem, jhs, jiri, linux-kernel, netdev, syzkaller-bugs,
xiyou.wangcong
[-- Attachment #1: Type: text/plain, Size: 4129 bytes --]
Hello,
syzkaller hit the following crash on
6084b576dca2e898f5c101baef151f7bfdbb606d
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
compiler: gcc (GCC) 7.1.1 20170620
.config is attached
Raw console output is attached.
Unfortunately, I don't have any reproducer for this bug yet.
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: qdisc_dev include/net/sch_generic.h:379 [inline]
IP: tc_fill_qdisc+0xc8/0x4b0 net/sched/sch_api.c:792
PGD 1dc5d4067 P4D 1dc5d4067 PUD 1db5fa067 PMD 0
Oops: 0000 [#1] SMP
Dumping ftrace buffer:
(ftrace buffer empty)
Modules linked in:
CPU: 0 PID: 7609 Comm: syz-executor4 Not tainted 4.15.0-rc3-next-20171214+
#67
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
Google 01/01/2011
RIP: 0010:qdisc_dev include/net/sch_generic.h:379 [inline]
RIP: 0010:tc_fill_qdisc+0xc8/0x4b0 net/sched/sch_api.c:792
RSP: 0018:ffffc90000ea38c8 EFLAGS: 00010212
RAX: 0000000000000000 RBX: ffff880216ac3c00 RCX: ffffffff8212563c
RDX: 0000000000000a02 RSI: ffffc90004f53000 RDI: ffff8801dc6a20b0
RBP: ffffc90000ea3970 R08: 0000000000000014 R09: ffff8801dc6a20b0
R10: ffffc90000ea37d8 R11: 0000000000000002 R12: ffff880214161b00
R13: ffff8801dc6a208c R14: 0000000000000000 R15: 0000000000000002
FS: 00007f6db5bc5700(0000) GS:ffff88021fc00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000000 CR3: 00000001dc75a000 CR4: 00000000001426f0
DR0: 0000000020000000 DR1: 0000000000000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600
Call Trace:
tc_dump_qdisc_root+0x1f1/0x220 net/sched/sch_api.c:1474
tc_dump_qdisc+0x1a1/0x280 net/sched/sch_api.c:1540
netlink_dump+0x14e/0x360 net/netlink/af_netlink.c:2222
__netlink_dump_start+0x1bb/0x210 net/netlink/af_netlink.c:2319
netlink_dump_start include/linux/netlink.h:214 [inline]
rtnetlink_rcv_msg+0x44f/0x5d0 net/core/rtnetlink.c:4485
netlink_rcv_skb+0x92/0x160 net/netlink/af_netlink.c:2441
rtnetlink_rcv+0x1c/0x20 net/core/rtnetlink.c:4540
netlink_unicast_kernel net/netlink/af_netlink.c:1308 [inline]
netlink_unicast+0x1d4/0x290 net/netlink/af_netlink.c:1334
netlink_sendmsg+0x345/0x470 net/netlink/af_netlink.c:1897
sock_sendmsg_nosec net/socket.c:636 [inline]
sock_sendmsg+0x51/0x70 net/socket.c:646
___sys_sendmsg+0x35e/0x3b0 net/socket.c:2026
__sys_sendmsg+0x50/0x90 net/socket.c:2060
SYSC_sendmsg net/socket.c:2071 [inline]
SyS_sendmsg+0x2d/0x50 net/socket.c:2067
entry_SYSCALL_64_fastpath+0x1f/0x96
RIP: 0033:0x452a39
RSP: 002b:00007f6db5bc4c58 EFLAGS: 00000212 ORIG_RAX: 000000000000002e
RAX: ffffffffffffffda RBX: 0000000000758020 RCX: 0000000000452a39
RDX: 0000000000000000 RSI: 000000002061efc8 RDI: 000000000000001c
RBP: 0000000000000343 R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000212 R12: 00000000006f2ee8
R13: 00000000ffffffff R14: 00007f6db5bc56d4 R15: 0000000000000000
Code: 41 b8 14 00 00 00 4c 89 e7 e8 05 17 01 00 48 85 c0 49 89 c5 0f 84 cb
02 00 00 e8 04 4d 19 ff 41 c7 45 10 00 00 00 00 48 8b 43 40 <48> 8b 00 8b
80 08 01 00 00 45 89 75 1c 41 89 45 14 8b 43 38 41
RIP: qdisc_dev include/net/sch_generic.h:379 [inline] RSP: ffffc90000ea38c8
RIP: tc_fill_qdisc+0xc8/0x4b0 net/sched/sch_api.c:792 RSP: ffffc90000ea38c8
CR2: 0000000000000000
---[ end trace dffd1876816a33a6 ]---
---
This bug is generated by a dumb bot. It may contain errors.
See https://goo.gl/tpsmEJ for details.
Direct all questions to syzkaller@googlegroups.com.
Please credit me with: Reported-by: syzbot <syzkaller@googlegroups.com>
syzbot will keep track of this bug report.
Once a fix for this bug is merged into any tree, reply to this email with:
#syz fix: exact-commit-title
To mark this as a duplicate of another syzbot report, please reply with:
#syz dup: exact-subject-of-another-report
If it's a one-off invalid bug report, please reply with:
#syz invalid
Note: if the crash happens again, it will cause creation of a new bug
report.
Note: all commands must start from beginning of the line in the email body.
[-- Attachment #2: config.txt --]
[-- Type: text/plain, Size: 126475 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/x86 4.15.0-rc2 Kernel Configuration
#
CONFIG_64BIT=y
CONFIG_X86_64=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf64-x86-64"
CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=28
CONFIG_ARCH_MMAP_RND_BITS_MAX=32
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ZONE_DMA32=y
CONFIG_AUDIT_ARCH=y
CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000
CONFIG_HAVE_INTEL_TXT=y
CONFIG_X86_64_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y
CONFIG_AUDIT_WATCH=y
CONFIG_AUDIT_TREE=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_CPU_ISOLATION is not set
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
# CONFIG_TASKS_RCU is not set
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# CONFIG_BUILD_BIN2C is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_NUMA_BALANCING=y
CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_SWAP_ENABLED=y
CONFIG_BLK_CGROUP=y
# CONFIG_DEBUG_BLK_CGROUP is not set
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_CFS_BANDWIDTH is not set
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
CONFIG_USERFAULTFD=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
# CONFIG_OPROFILE is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_OPROFILE_NMI_TIMER=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_OPTPROBES=y
CONFIG_UPROBES=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
CONFIG_GCC_PLUGIN_SANCOV=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_CC_STACKPROTECTOR_NONE=y
# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
# CONFIG_CC_STACKPROTECTOR_STRONG is not set
CONFIG_THIN_ARCHIVES=y
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_SOFT_DIRTY=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=28
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_STACK_VALIDATION=y
# CONFIG_HAVE_ARCH_HASH is not set
# CONFIG_ISA_BUS_API is not set
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
# CONFIG_CPU_NO_EFFICIENT_FFS is not set
CONFIG_HAVE_ARCH_VMAP_STACK=y
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_REFCOUNT=y
CONFIG_REFCOUNT_FULL=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
# CONFIG_BLK_CMDLINE_PARSER is not set
CONFIG_BLK_WBT=y
# CONFIG_BLK_WBT_SQ is not set
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_BLK_SED_OPAL is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
# CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CFQ_GROUP_IOSCHED=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_FREEZER=y
#
# Processor type and features
#
CONFIG_ZONE_DMA=y
CONFIG_SMP=y
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_FAST_FEATURE_TESTS=y
CONFIG_X86_X2APIC=y
CONFIG_X86_MPPARSE=y
# CONFIG_GOLDFISH is not set
# CONFIG_INTEL_RDT is not set
CONFIG_X86_EXTENDED_PLATFORM=y
# CONFIG_X86_NUMACHIP is not set
# CONFIG_X86_VSMP is not set
# CONFIG_X86_UV is not set
# CONFIG_X86_GOLDFISH is not set
# CONFIG_X86_INTEL_MID is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_DEBUG=y
CONFIG_PARAVIRT_SPINLOCKS=y
# CONFIG_QUEUED_LOCK_STAT is not set
CONFIG_XEN=y
CONFIG_XEN_PV=y
CONFIG_XEN_PV_SMP=y
CONFIG_XEN_DOM0=y
CONFIG_XEN_PVHVM=y
CONFIG_XEN_PVHVM_SMP=y
CONFIG_XEN_512GB=y
CONFIG_XEN_SAVE_RESTORE=y
# CONFIG_XEN_DEBUG_FS is not set
CONFIG_XEN_PVH=y
CONFIG_KVM_GUEST=y
# CONFIG_KVM_DEBUG_FS is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
CONFIG_NO_BOOTMEM=y
# CONFIG_MK8 is not set
# CONFIG_MPSC is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_GENERIC_CPU=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=64
CONFIG_X86_DEBUGCTLMSR=y
# CONFIG_PROCESSOR_SELECT is not set
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
# CONFIG_GART_IOMMU is not set
CONFIG_CALGARY_IOMMU=y
CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y
# CONFIG_MAXSMP is not set
CONFIG_NR_CPUS=64
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_MC_PRIO=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
CONFIG_X86_MCE=y
# CONFIG_X86_MCELOG_LEGACY is not set
CONFIG_X86_MCE_INTEL=y
CONFIG_X86_MCE_AMD=y
CONFIG_X86_MCE_THRESHOLD=y
CONFIG_X86_MCE_INJECT=y
CONFIG_X86_THERMAL_VECTOR=y
#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
CONFIG_PERF_EVENTS_INTEL_CSTATE=y
# CONFIG_PERF_EVENTS_AMD_POWER is not set
# CONFIG_VM86 is not set
CONFIG_X86_16BIT=y
CONFIG_X86_ESPFIX64=y
CONFIG_X86_VSYSCALL_EMULATION=y
# CONFIG_I8K is not set
CONFIG_MICROCODE=y
CONFIG_MICROCODE_INTEL=y
CONFIG_MICROCODE_AMD=y
CONFIG_MICROCODE_OLD_INTERFACE=y
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y
# CONFIG_X86_5LEVEL is not set
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_X86_DIRECT_GBPAGES=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
# CONFIG_AMD_MEM_ENCRYPT is not set
CONFIG_NUMA=y
CONFIG_AMD_NUMA=y
CONFIG_X86_64_ACPI_NUMA=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_NUMA_EMU is not set
CONFIG_NODES_SHIFT=6
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_NEED_MULTIPLE_NODES=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_GENERIC_GUP=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_THP_SWAP=y
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
# CONFIG_CMA is not set
# CONFIG_MEM_SOFT_DIRTY is not set
# CONFIG_ZPOOL is not set
# CONFIG_ZBUD is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_ZONE_DEVICE=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_HAS_PKEYS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_X86_PMEM_LEGACY is not set
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
CONFIG_X86_RESERVE_LOW=64
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_ARCH_RANDOM=y
CONFIG_X86_SMAP=y
# CONFIG_X86_INTEL_UMIP is not set
CONFIG_X86_INTEL_MPX=y
CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
CONFIG_EFI=y
# CONFIG_EFI_STUB is not set
CONFIG_SECCOMP=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
CONFIG_SCHED_HRTICK=y
CONFIG_KEXEC=y
# CONFIG_KEXEC_FILE is not set
CONFIG_CRASH_DUMP=y
# CONFIG_KEXEC_JUMP is not set
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
# CONFIG_COMPAT_VDSO is not set
# CONFIG_LEGACY_VSYSCALL_NATIVE is not set
CONFIG_LEGACY_VSYSCALL_EMULATE=y
# CONFIG_LEGACY_VSYSCALL_NONE is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_MODIFY_LDT_SYSCALL=y
CONFIG_HAVE_LIVEPATCH=y
CONFIG_ARCH_HAS_ADD_PAGES=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
#
# Power management and ACPI options
#
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_LPIT=y
CONFIG_ACPI_SLEEP=y
# CONFIG_ACPI_PROCFS_POWER is not set
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_NUMA=y
# CONFIG_ACPI_CUSTOM_DSDT is not set
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_X86_PM_TIMER=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_BGRT is not set
# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
# CONFIG_ACPI_NFIT is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_DPTF_POWER is not set
# CONFIG_ACPI_EXTLOG is not set
# CONFIG_PMIC_OPREGION is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_SFI is not set
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
#
# CPU frequency scaling drivers
#
CONFIG_X86_INTEL_PSTATE=y
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_ACPI_CPUFREQ=y
CONFIG_X86_ACPI_CPUFREQ_CPB=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
# CONFIG_X86_P4_CLOCKMOD is not set
#
# shared options
#
# CONFIG_X86_SPEEDSTEP_LIB is not set
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
# CONFIG_INTEL_IDLE is not set
#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_XEN=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCI_CNB20LE_QUIRK is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_HOTPLUG_PCI_PCIE is not set
CONFIG_PCIEAER=y
# CONFIG_PCIE_ECRC is not set
# CONFIG_PCIEAER_INJECT is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEBUG is not set
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_BUS_ADDR_T_64BIT=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
# CONFIG_PCI_STUB is not set
CONFIG_XEN_PCIDEV_FRONTEND=y
CONFIG_PCI_ATS=y
CONFIG_PCI_LOCKLESS_CONFIG=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_ACPI is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
#
# DesignWare PCI Core Support
#
# CONFIG_PCIE_DW_PLAT is not set
#
# PCI host controller drivers
#
# CONFIG_VMD is not set
#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# CONFIG_ISA_BUS is not set
CONFIG_ISA_DMA_API=y
CONFIG_AMD_NB=y
CONFIG_PCCARD=y
CONFIG_PCMCIA=y
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_CARDBUS=y
#
# PC-card bridges
#
CONFIG_YENTA=y
CONFIG_YENTA_O2=y
CONFIG_YENTA_RICOH=y
CONFIG_YENTA_TI=y
CONFIG_YENTA_ENE_TUNE=y
CONFIG_YENTA_TOSHIBA=y
# CONFIG_PD6729 is not set
# CONFIG_I82092 is not set
CONFIG_PCCARD_NONSTATIC=y
# CONFIG_RAPIDIO is not set
# CONFIG_X86_SYSFB is not set
#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
CONFIG_IA32_EMULATION=y
# CONFIG_IA32_AOUT is not set
# CONFIG_X86_X32 is not set
CONFIG_COMPAT_32=y
CONFIG_COMPAT=y
CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_X86_DEV_DMA_OPS=y
CONFIG_NET=y
CONFIG_NET_INGRESS=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
CONFIG_TLS=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
CONFIG_IP_MROUTE=y
# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
# CONFIG_NET_IPVTI is not set
CONFIG_NET_UDP_TUNNEL=y
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
CONFIG_TCP_CONG_CUBIC=y
# CONFIG_TCP_CONG_WESTWOOD is not set
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_TCP_CONG_HSTCP is not set
# CONFIG_TCP_CONG_HYBLA is not set
# CONFIG_TCP_CONG_VEGAS is not set
# CONFIG_TCP_CONG_NV is not set
# CONFIG_TCP_CONG_SCALABLE is not set
# CONFIG_TCP_CONG_LP is not set
# CONFIG_TCP_CONG_VENO is not set
# CONFIG_TCP_CONG_YEAH is not set
# CONFIG_TCP_CONG_ILLINOIS is not set
# CONFIG_TCP_CONG_DCTCP is not set
# CONFIG_TCP_CONG_CDG is not set
# CONFIG_TCP_CONG_BBR is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=y
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_ILA is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
CONFIG_INET6_TUNNEL=y
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
CONFIG_INET6_XFRM_MODE_TUNNEL=y
CONFIG_INET6_XFRM_MODE_BEET=y
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
# CONFIG_IPV6_FOU is not set
# CONFIG_IPV6_FOU_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
CONFIG_IPV6_MROUTE=y
# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
# CONFIG_IPV6_PIMSM_V2 is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
CONFIG_NETLABEL=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=y
# CONFIG_NF_LOG_NETDEV is not set
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_IRC=y
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CT_NETLINK=y
# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
CONFIG_NF_NAT=y
CONFIG_NF_NAT_NEEDED=y
# CONFIG_NF_NAT_AMANDA is not set
CONFIG_NF_NAT_FTP=y
CONFIG_NF_NAT_IRC=y
CONFIG_NF_NAT_SIP=y
# CONFIG_NF_NAT_TFTP is not set
# CONFIG_NF_NAT_REDIRECT is not set
# CONFIG_NF_TABLES is not set
CONFIG_NETFILTER_XTABLES=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_NAT=y
# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_CONNTRACK_IPV4=y
# CONFIG_NF_SOCKET_IPV4 is not set
# CONFIG_NF_DUP_IPV4 is not set
CONFIG_NF_LOG_ARP=y
CONFIG_NF_LOG_IPV4=y
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_IPV4=y
CONFIG_NF_NAT_MASQUERADE_IPV4=y
# CONFIG_NF_NAT_PPTP is not set
# CONFIG_NF_NAT_H323 is not set
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_RAW is not set
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_CONNTRACK_IPV6=y
# CONFIG_NF_SOCKET_IPV6 is not set
# CONFIG_NF_DUP_IPV6 is not set
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_IPV6HEADER=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_MANGLE=y
# CONFIG_IP6_NF_RAW is not set
# CONFIG_BRIDGE_NF_EBTABLES is not set
CONFIG_IP_DCCP=y
#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# CONFIG_NET_DCCPPROBE is not set
CONFIG_IP_SCTP=y
# CONFIG_NET_SCTPPROBE is not set
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_RDS=y
CONFIG_RDS_TCP=y
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=y
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=y
CONFIG_ATM_MPOA=y
CONFIG_ATM_BR2684=y
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=y
# CONFIG_L2TP_DEBUGFS is not set
# CONFIG_L2TP_V3 is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
# CONFIG_BRIDGE_VLAN_FILTERING is not set
CONFIG_HAVE_NET_DSA=y
CONFIG_NET_DSA=y
CONFIG_VLAN_8021Q=y
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
CONFIG_LLC2=y
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
# CONFIG_NET_SCH_CBQ is not set
# CONFIG_NET_SCH_HTB is not set
# CONFIG_NET_SCH_HFSC is not set
# CONFIG_NET_SCH_ATM is not set
# CONFIG_NET_SCH_PRIO is not set
# CONFIG_NET_SCH_MULTIQ is not set
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFB is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_CBS is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
# CONFIG_NET_SCH_NETEM is not set
# CONFIG_NET_SCH_DRR is not set
# CONFIG_NET_SCH_MQPRIO is not set
# CONFIG_NET_SCH_CHOKE is not set
# CONFIG_NET_SCH_QFQ is not set
# CONFIG_NET_SCH_CODEL is not set
# CONFIG_NET_SCH_FQ_CODEL is not set
# CONFIG_NET_SCH_FQ is not set
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_INGRESS is not set
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_DEFAULT is not set
#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=y
# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_ROUTE4 is not set
# CONFIG_NET_CLS_FW is not set
# CONFIG_NET_CLS_U32 is not set
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
# CONFIG_NET_CLS_FLOW is not set
# CONFIG_NET_CLS_CGROUP is not set
CONFIG_NET_CLS_BPF=y
# CONFIG_NET_CLS_FLOWER is not set
# CONFIG_NET_CLS_MATCHALL is not set
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
# CONFIG_NET_EMATCH_CMP is not set
# CONFIG_NET_EMATCH_NBYTE is not set
# CONFIG_NET_EMATCH_U32 is not set
# CONFIG_NET_EMATCH_META is not set
# CONFIG_NET_EMATCH_TEXT is not set
CONFIG_NET_CLS_ACT=y
# CONFIG_NET_ACT_POLICE is not set
# CONFIG_NET_ACT_GACT is not set
# CONFIG_NET_ACT_MIRRED is not set
CONFIG_NET_ACT_SAMPLE=y
# CONFIG_NET_ACT_IPT is not set
# CONFIG_NET_ACT_NAT is not set
# CONFIG_NET_ACT_PEDIT is not set
# CONFIG_NET_ACT_SIMP is not set
# CONFIG_NET_ACT_SKBEDIT is not set
# CONFIG_NET_ACT_CSUM is not set
# CONFIG_NET_ACT_VLAN is not set
CONFIG_NET_ACT_BPF=y
# CONFIG_NET_ACT_SKBMOD is not set
# CONFIG_NET_ACT_IFE is not set
# CONFIG_NET_ACT_TUNNEL_KEY is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
CONFIG_VSOCKETS=y
CONFIG_VSOCKETS_DIAG=y
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS_COMMON=y
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_TCPPROBE is not set
# CONFIG_NET_DROP_MONITOR is not set
CONFIG_HAMRADIO=y
#
# Packet Radio protocols
#
# CONFIG_AX25 is not set
# CONFIG_CAN is not set
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_LEDS=y
# CONFIG_BT_SELFTEST is not set
# CONFIG_BT_DEBUGFS is not set
#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=y
CONFIG_BT_RTL=y
CONFIG_BT_HCIBTUSB=y
# CONFIG_BT_HCIBTUSB_BCM is not set
CONFIG_BT_HCIBTUSB_RTL=y
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIDTL1 is not set
# CONFIG_BT_HCIBT3C is not set
# CONFIG_BT_HCIBLUECARD is not set
# CONFIG_BT_HCIBTUART is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_BT_ATH3K is not set
# CONFIG_AF_RXRPC is not set
CONFIG_AF_KCM=y
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_CFG80211=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
# CONFIG_LIB80211 is not set
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL_HT=y
# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_WIMAX=y
CONFIG_WIMAX_DEBUG_LEVEL=8
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_9P_XEN=y
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
CONFIG_NFC=y
CONFIG_NFC_DIGITAL=y
CONFIG_NFC_NCI=y
CONFIG_NFC_NCI_UART=y
CONFIG_NFC_HCI=y
CONFIG_NFC_SHDLC=y
#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_SIM=y
# CONFIG_NFC_PORT100 is not set
CONFIG_NFC_FDP=y
# CONFIG_NFC_FDP_I2C is not set
# CONFIG_NFC_PN544_I2C is not set
# CONFIG_NFC_PN533_USB is not set
# CONFIG_NFC_PN533_I2C is not set
# CONFIG_NFC_MICROREAD_I2C is not set
# CONFIG_NFC_MRVL_USB is not set
# CONFIG_NFC_MRVL_UART is not set
# CONFIG_NFC_ST21NFCA_I2C is not set
# CONFIG_NFC_ST_NCI_I2C is not set
# CONFIG_NFC_NXP_NCI is not set
# CONFIG_NFC_S3FWRN5_I2C is not set
CONFIG_PSAMPLE=y
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
CONFIG_HAVE_EBPF_JIT=y
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_SYS_HYPERVISOR=y
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
#
# Bus devices
#
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
# CONFIG_OF is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=y
# CONFIG_BLK_DEV_FD is not set
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_XEN_BLKDEV_FRONTEND=y
# CONFIG_XEN_BLKDEV_BACKEND is not set
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_BLK_SCSI=y
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set
#
# NVME Support
#
# CONFIG_BLK_DEV_NVME is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set
#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_SRAM is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_INTEL_MEI is not set
# CONFIG_INTEL_MEI_ME is not set
# CONFIG_INTEL_MEI_TXE is not set
# CONFIG_VMWARE_VMCI is not set
#
# Intel MIC & related support
#
#
# Intel MIC Bus Driver
#
# CONFIG_INTEL_MIC_BUS is not set
#
# SCIF Bus Driver
#
# CONFIG_SCIF_BUS is not set
#
# VOP Bus Driver
#
# CONFIG_VOP_BUS is not set
#
# Intel MIC Host Driver
#
#
# Intel MIC Card Driver
#
#
# SCIF Driver
#
#
# Intel MIC Coprocessor State Management (COSM) Drivers
#
#
# VOP Driver
#
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_CXL_BASE is not set
# CONFIG_CXL_AFU_DRIVER_OPS is not set
# CONFIG_CXL_LIB is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_MQ_DEFAULT is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=y
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_VMWARE_PVSCSI is not set
# CONFIG_XEN_SCSI_FRONTEND is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_ISCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=y
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y
#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y
#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y
#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
CONFIG_PATA_AMD=y
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
CONFIG_PATA_OLDPIIX=y
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
CONFIG_PATA_SCH=y
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PCMCIA is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set
#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID10 is not set
# CONFIG_MD_RAID456 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
# CONFIG_BCACHE is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_MQ_DEFAULT is not set
# CONFIG_DM_DEBUG is not set
# CONFIG_DM_CRYPT is not set
# CONFIG_DM_SNAPSHOT is not set
# CONFIG_DM_THIN_PROVISIONING is not set
# CONFIG_DM_CACHE is not set
# CONFIG_DM_ERA is not set
CONFIG_DM_MIRROR=y
# CONFIG_DM_LOG_USERSPACE is not set
# CONFIG_DM_RAID is not set
CONFIG_DM_ZERO=y
# CONFIG_DM_MULTIPATH is not set
# CONFIG_DM_DELAY is not set
# CONFIG_DM_UEVENT is not set
# CONFIG_DM_FLAKEY is not set
# CONFIG_DM_VERITY is not set
# CONFIG_DM_SWITCH is not set
# CONFIG_DM_LOG_WRITES is not set
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_ZONED is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_MAC_EMUMOUSEBTN=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_IFB is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
CONFIG_NETCONSOLE=y
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=y
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y
# CONFIG_NLMON is not set
# CONFIG_ARCNET is not set
CONFIG_ATM_DRIVERS=y
# CONFIG_ATM_DUMMY is not set
CONFIG_ATM_TCP=y
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_FIRESTREAM is not set
# CONFIG_ATM_ZATM is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_AMBASSADOR is not set
# CONFIG_ATM_HORIZON is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E is not set
# CONFIG_ATM_HE is not set
# CONFIG_ATM_SOLOS is not set
#
# CAIF transport drivers
#
#
# Distributed Switch Architecture drivers
#
# CONFIG_B53 is not set
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_MT7530 is not set
# CONFIG_NET_DSA_MV88E6060 is not set
# CONFIG_MICROCHIP_KSZ is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_QCA8K is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_VORTEX is not set
# CONFIG_TYPHOON is not set
CONFIG_NET_VENDOR_ADAPTEC=y
# CONFIG_ADAPTEC_STARFIRE is not set
CONFIG_NET_VENDOR_AGERE=y
# CONFIG_ET131X is not set
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALTEON=y
# CONFIG_ACENIC is not set
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_PCNET32 is not set
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_AMD_XGBE is not set
# CONFIG_AMD_XGBE_HAVE_ECC is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
# CONFIG_NET_VENDOR_AURORA is not set
CONFIG_NET_CADENCE=y
# CONFIG_MACB is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BNX2 is not set
# CONFIG_CNIC is not set
CONFIG_TIGON3=y
CONFIG_TIGON3_HWMON=y
# CONFIG_BNX2X is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
CONFIG_NET_VENDOR_CAVIUM=y
# CONFIG_THUNDER_NIC_PF is not set
# CONFIG_THUNDER_NIC_VF is not set
# CONFIG_THUNDER_NIC_BGX is not set
# CONFIG_THUNDER_NIC_RGX is not set
# CONFIG_LIQUIDIO is not set
# CONFIG_LIQUIDIO_VF is not set
CONFIG_NET_VENDOR_CHELSIO=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
# CONFIG_CHELSIO_T4VF is not set
CONFIG_NET_VENDOR_CISCO=y
# CONFIG_ENIC is not set
# CONFIG_CX_ECAT is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_DEC=y
CONFIG_NET_TULIP=y
# CONFIG_DE2104X is not set
# CONFIG_TULIP is not set
# CONFIG_DE4X5 is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_DM9102 is not set
# CONFIG_ULI526X is not set
# CONFIG_PCMCIA_XIRCOM is not set
CONFIG_NET_VENDOR_DLINK=y
# CONFIG_DL2K is not set
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
# CONFIG_BE2NET is not set
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_NET_VENDOR_EXAR=y
# CONFIG_S2IO is not set
# CONFIG_VXGE is not set
CONFIG_NET_VENDOR_FUJITSU=y
# CONFIG_PCMCIA_FMVJ18X is not set
CONFIG_NET_VENDOR_HP=y
# CONFIG_HP100 is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_E1000E_HWTS=y
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_FM10K is not set
CONFIG_NET_VENDOR_I825XX=y
# CONFIG_JME is not set
CONFIG_NET_VENDOR_MARVELL=y
# CONFIG_MVMDIO is not set
# CONFIG_SKGE is not set
CONFIG_SKY2=y
# CONFIG_SKY2_DEBUG is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLX4_EN is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_KSZ884X_PCI is not set
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
# CONFIG_FEALNX is not set
CONFIG_NET_VENDOR_NATSEMI=y
# CONFIG_NATSEMI is not set
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_PCMCIA_AXNET is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_PCMCIA_PCNET is not set
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=y
CONFIG_NET_VENDOR_OKI=y
# CONFIG_ETHOC is not set
CONFIG_NET_PACKET_ENGINE=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_NET_VENDOR_QLOGIC=y
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_QLGE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_QED is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
CONFIG_8139TOO=y
CONFIG_8139TOO_PIO=y
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_8139_OLD_RX_RESET is not set
# CONFIG_R8169 is not set
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_RDC=y
# CONFIG_R6040 is not set
CONFIG_NET_VENDOR_ROCKER=y
# CONFIG_ROCKER is not set
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
# CONFIG_SC92031 is not set
CONFIG_NET_VENDOR_SIS=y
# CONFIG_SIS900 is not set
# CONFIG_SIS190 is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SMSC911X is not set
# CONFIG_SMSC9420 is not set
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_SUN=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NIU is not set
CONFIG_NET_VENDOR_TEHUTI=y
# CONFIG_TEHUTI is not set
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_ALE is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
CONFIG_NET_VENDOR_XIRCOM=y
# CONFIG_PCMCIA_XIRC2PS is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_FDDI=y
# CONFIG_DEFXX is not set
# CONFIG_SKFP is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_THUNDER is not set
CONFIG_PHYLIB=y
# CONFIG_LED_TRIGGER_PHY is not set
#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_HSO is not set
# CONFIG_USB_IPHETH is not set
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
CONFIG_WLAN_VENDOR_ADMTEK=y
# CONFIG_ADM8211 is not set
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
# CONFIG_ATH9K is not set
# CONFIG_ATH9K_HTC is not set
# CONFIG_CARL9170 is not set
# CONFIG_ATH6KL is not set
# CONFIG_AR5523 is not set
# CONFIG_WIL6210 is not set
# CONFIG_ATH10K is not set
# CONFIG_WCN36XX is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
# CONFIG_AT76C50X_USB is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_BRCMSMAC is not set
# CONFIG_BRCMFMAC is not set
CONFIG_WLAN_VENDOR_CISCO=y
# CONFIG_AIRO is not set
# CONFIG_AIRO_CS is not set
CONFIG_WLAN_VENDOR_INTEL=y
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
# CONFIG_IWL4965 is not set
# CONFIG_IWL3945 is not set
# CONFIG_IWLWIFI is not set
CONFIG_WLAN_VENDOR_INTERSIL=y
# CONFIG_HOSTAP is not set
# CONFIG_HERMES is not set
# CONFIG_P54_COMMON is not set
# CONFIG_PRISM54 is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# CONFIG_LIBERTAS is not set
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_MWIFIEX is not set
# CONFIG_MWL8K is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
# CONFIG_MT7601U is not set
CONFIG_WLAN_VENDOR_RALINK=y
# CONFIG_RT2X00 is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
# CONFIG_RTL8187 is not set
CONFIG_RTL_CARDS=y
# CONFIG_RTL8192CE is not set
# CONFIG_RTL8192SE is not set
# CONFIG_RTL8192DE is not set
# CONFIG_RTL8723AE is not set
# CONFIG_RTL8723BE is not set
# CONFIG_RTL8188EE is not set
# CONFIG_RTL8192EE is not set
# CONFIG_RTL8821AE is not set
# CONFIG_RTL8192CU is not set
# CONFIG_RTL8XXXU is not set
CONFIG_WLAN_VENDOR_RSI=y
# CONFIG_RSI_91X is not set
CONFIG_WLAN_VENDOR_ST=y
# CONFIG_CW1200 is not set
CONFIG_WLAN_VENDOR_TI=y
# CONFIG_WL1251 is not set
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
# CONFIG_WLCORE is not set
CONFIG_WLAN_VENDOR_ZYDAS=y
# CONFIG_USB_ZD1201 is not set
# CONFIG_ZD1211RW is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_PCMCIA_RAYCS is not set
# CONFIG_PCMCIA_WL3501 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
#
# WiMAX Wireless Broadband devices
#
# CONFIG_WIMAX_I2400M_USB is not set
# CONFIG_WAN is not set
CONFIG_XEN_NETDEV_FRONTEND=y
# CONFIG_XEN_NETDEV_BACKEND is not set
# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_ISDN is not set
# CONFIG_NVM is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MATRIXKMAP is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
# CONFIG_MOUSE_PS2_VMMOUSE is not set
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
# CONFIG_JOYSTICK_IFORCE is not set
# CONFIG_JOYSTICK_WARRIOR is not set
# CONFIG_JOYSTICK_MAGELLAN is not set
# CONFIG_JOYSTICK_SPACEORB is not set
# CONFIG_JOYSTICK_SPACEBALL is not set
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
# CONFIG_JOYSTICK_XPAD is not set
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_USB_ACECAD is not set
# CONFIG_TABLET_USB_AIPTEK is not set
# CONFIG_TABLET_USB_GTCO is not set
# CONFIG_TABLET_USB_HANWANG is not set
# CONFIG_TABLET_USB_KBTAB is not set
# CONFIG_TABLET_USB_PEGASUS is not set
# CONFIG_TABLET_SERIAL_WACOM4 is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_PCSPKR is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_APANEL is not set
# CONFIG_INPUT_ATLAS_BTNS is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_CMA3000 is not set
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_ROCKETPORT is not set
# CONFIG_CYCLADES is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_SYNCLINK is not set
# CONFIG_SYNCLINKMP is not set
# CONFIG_SYNCLINK_GT is not set
# CONFIG_NOZOMI is not set
# CONFIG_ISI is not set
# CONFIG_N_HDLC is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVMEM=y
# CONFIG_DEVKMEM is not set
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
# CONFIG_SERIAL_8250_EXAR is not set
# CONFIG_SERIAL_8250_CS is not set
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
# CONFIG_SERIAL_8250_FSL is not set
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
# CONFIG_SERIAL_8250_MOXA is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_HVC_DRIVER=y
CONFIG_HVC_IRQ=y
CONFIG_HVC_XEN=y
CONFIG_HVC_XEN_FRONTEND=y
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_INTEL is not set
# CONFIG_HW_RANDOM_AMD is not set
CONFIG_HW_RANDOM_VIA=y
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_NVRAM=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_SCR24X is not set
# CONFIG_IPWIRELESS is not set
# CONFIG_MWAVE is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_HPET=y
# CONFIG_HPET_MMAP is not set
# CONFIG_HANGCHECK_TIMER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set
#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
CONFIG_I2C_I801=y
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_ISMT is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PINCTRL is not set
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
# CONFIG_POWER_AVS is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_K8TEMP is not set
# CONFIG_SENSORS_K10TEMP is not set
# CONFIG_SENSORS_FAM15H_POWER is not set
# CONFIG_SENSORS_APPLESMC is not set
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_DELL_SMM is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FSCHMD is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_I5500 is not set
# CONFIG_SENSORS_CORETEMP is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VIA_CPUTEMP is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set
#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_INTEL_POWERCLAMP is not set
CONFIG_X86_PKG_TEMP_THERMAL=y
# CONFIG_INTEL_SOC_DTS_THERMAL is not set
#
# ACPI INT340X thermal drivers
#
# CONFIG_INT340X_THERMAL is not set
# CONFIG_INTEL_PCH_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_CORE is not set
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
# CONFIG_WATCHDOG_SYSFS is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ALIM1535_WDT is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_F71808E_WDT is not set
# CONFIG_SP5100_TCO is not set
# CONFIG_SBC_FITPC2_WATCHDOG is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_IBMASR is not set
# CONFIG_WAFER_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_IE6XX_WDT is not set
# CONFIG_ITCO_WDT is not set
# CONFIG_IT8712F_WDT is not set
# CONFIG_IT87_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_SC1200_WDT is not set
# CONFIG_PC87413_WDT is not set
# CONFIG_NV_TCO is not set
# CONFIG_60XX_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_SMSC_SCH311X_WDT is not set
# CONFIG_SMSC37B787_WDT is not set
# CONFIG_VIA_WDT is not set
# CONFIG_W83627HF_WDT is not set
# CONFIG_W83877F_WDT is not set
# CONFIG_W83977F_WDT is not set
# CONFIG_MACHZ_WDT is not set
# CONFIG_SBC_EPX_C3_WATCHDOG is not set
# CONFIG_NI903X_WDT is not set
# CONFIG_NIC7018_WDT is not set
# CONFIG_XEN_WDT is not set
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_INTEL_SOC_PMIC_CHTWC is not set
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
# CONFIG_MFD_INTEL_LPSS_PCI is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RTSX_PCI is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RTSX_USB is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS68470 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_REGULATOR is not set
# CONFIG_RC_CORE is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
CONFIG_AGP=y
CONFIG_AGP_AMD64=y
CONFIG_AGP_INTEL=y
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_VIA is not set
CONFIG_INTEL_GTT=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_MM_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_TTM=y
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_RADEON=y
CONFIG_DRM_RADEON_USERPTR=y
CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMDGPU_SI=y
CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
#
# ACP (Audio CoProcessor) Configuration
#
# CONFIG_DRM_AMD_ACP is not set
#
# Display Engine Configuration
#
CONFIG_DRM_AMD_DC=y
# CONFIG_DRM_AMD_DC_PRE_VEGA is not set
# CONFIG_DRM_AMD_DC_FBC is not set
# CONFIG_DRM_AMD_DC_DCN1_0 is not set
# CONFIG_DEBUG_KERNEL_DC is not set
#
# AMD Library routines
#
CONFIG_CHASH=y
# CONFIG_CHASH_STATS is not set
# CONFIG_CHASH_SELFTEST is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_ALPHA_SUPPORT=y
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
CONFIG_DRM_I915_USERPTR=y
CONFIG_DRM_I915_GVT=y
#
# drm/i915 Debugging
#
# CONFIG_DRM_I915_WERROR is not set
# CONFIG_DRM_I915_DEBUG is not set
# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
# CONFIG_DRM_I915_SELFTEST is not set
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_GMA500 is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_CIRRUS_QEMU=y
CONFIG_DRM_QXL=y
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_PANEL=y
#
# Display Panels
#
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_HISI_HIBMC is not set
CONFIG_DRM_TINYDRM=y
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIB_RANDOM is not set
#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ARC is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_VESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_N411 is not set
# CONFIG_FB_HGA is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_XEN_FBDEV_FRONTEND=y
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_AUO_K190X is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SM712 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_APPLE is not set
# CONFIG_BACKLIGHT_PM8941_WLED is not set
# CONFIG_BACKLIGHT_SAHARA is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_VGASTATE is not set
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
CONFIG_VGACON_SOFT_SCROLLBACK=y
CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_DEBUG=y
# CONFIG_SND_DEBUG_VERBOSE is not set
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_DMA_SGBUF=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=y
# CONFIG_SND_SEQ_MIDI is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
CONFIG_SND_DRIVERS=y
# CONFIG_SND_PCSP is not set
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_ALOOP is not set
# CONFIG_SND_VIRMIDI is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALS4000 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ASIHPI is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1_SEQ is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
#
# HD-Audio
#
CONFIG_SND_HDA=y
CONFIG_SND_HDA_INTEL=y
CONFIG_SND_HDA_HWDEP=y
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_HDMI is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_I915=y
CONFIG_SND_HDA_PREALLOC_SIZE=64
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_US122L is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_PCMCIA=y
# CONFIG_SND_VXPOCKET is not set
# CONFIG_SND_PDAUDIOCF is not set
# CONFIG_SND_SOC is not set
CONFIG_SND_X86=y
CONFIG_HDMI_LPE_AUDIO=y
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
CONFIG_HID_APPLE=y
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=y
# CONFIG_HID_BETOP_FF is not set
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
CONFIG_HID_CYPRESS=y
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
CONFIG_HID_EZKEY=y
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
CONFIG_HID_GYRATION=y
# CONFIG_HID_ICADE is not set
CONFIG_HID_ITE=y
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=y
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
CONFIG_HID_LOGITECH=y
# CONFIG_HID_LOGITECH_DJ is not set
# CONFIG_HID_LOGITECH_HIDPP is not set
CONFIG_LOGITECH_FF=y
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_LOGIWHEELS_FF=y
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MAYFLASH is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTI is not set
CONFIG_HID_NTRIG=y
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
# CONFIG_HID_PENMOUNT is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_SONY_FF is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEELSERIES is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
CONFIG_HID_TOPSEED=y
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
#
# I2C HID support
#
# CONFIG_I2C_HID is not set
#
# Intel ISH HID support
#
# CONFIG_INTEL_ISH_HID is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_MON=y
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
# CONFIG_USB_OHCI_HCD_PLATFORM is not set
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
CONFIG_USB_PRINTER=y
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
# CONFIG_USB_UAS is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_CHAOSKEY is not set
CONFIG_USB_ATM=y
# CONFIG_USB_SPEEDTOUCH is not set
# CONFIG_USB_CXACRU is not set
# CONFIG_USB_UEAGLEATM is not set
# CONFIG_USB_XUSBATM is not set
#
# USB Physical Layer drivers
#
# CONFIG_USB_PHY is not set
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_GADGET is not set
CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
# CONFIG_TYPEC_FUSB302 is not set
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_ACPI=y
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_UWB is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
#
# LED drivers
#
# CONFIG_LEDS_APU is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_CLEVO_MAIL is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_INTEL_SS4200 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_MLXCPLD is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_NIC78BX is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_DISK is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_DECODE_MCE=y
# CONFIG_EDAC_AMD64 is not set
# CONFIG_EDAC_E752X is not set
# CONFIG_EDAC_I82975X is not set
# CONFIG_EDAC_I3000 is not set
# CONFIG_EDAC_I3200 is not set
# CONFIG_EDAC_IE31200 is not set
# CONFIG_EDAC_X38 is not set
# CONFIG_EDAC_I5400 is not set
# CONFIG_EDAC_I7CORE is not set
# CONFIG_EDAC_I5000 is not set
# CONFIG_EDAC_I5100 is not set
# CONFIG_EDAC_I7300 is not set
# CONFIG_EDAC_SBRIDGE is not set
# CONFIG_EDAC_SKX is not set
# CONFIG_EDAC_PND2 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
# CONFIG_RTC_NVMEM is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV8803 is not set
#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_FTRTC010 is not set
#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_INTEL_IOATDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set
CONFIG_HSU_DMA=y
#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_IRQ_BYPASS_MANAGER=y
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=y
#
# Virtio drivers
#
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
# CONFIG_VIRTIO_BALLOON is not set
CONFIG_VIRTIO_INPUT=y
# CONFIG_VIRTIO_MMIO is not set
#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# CONFIG_HYPERV_TSCPAGE is not set
#
# Xen driver support
#
CONFIG_XEN_BALLOON=y
CONFIG_XEN_SCRUB_PAGES=y
CONFIG_XEN_DEV_EVTCHN=y
CONFIG_XEN_BACKEND=y
CONFIG_XENFS=y
CONFIG_XEN_COMPAT_XENFS=y
CONFIG_XEN_SYS_HYPERVISOR=y
CONFIG_XEN_XENBUS_FRONTEND=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_SWIOTLB_XEN=y
CONFIG_XEN_PCIDEV_BACKEND=y
CONFIG_XEN_PVCALLS_FRONTEND=y
CONFIG_XEN_PVCALLS_BACKEND=y
CONFIG_XEN_PRIVCMD=y
CONFIG_XEN_ACPI_PROCESSOR=y
CONFIG_XEN_MCE_LOG=y
CONFIG_XEN_HAVE_PVMMU=y
CONFIG_XEN_EFI=y
CONFIG_XEN_AUTO_XLATE=y
CONFIG_XEN_ACPI=y
CONFIG_XEN_SYMS=y
CONFIG_XEN_HAVE_VPMU=y
# CONFIG_STAGING is not set
CONFIG_X86_PLATFORM_DEVICES=y
# CONFIG_ACERHDF is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_DELL_LAPTOP is not set
# CONFIG_DELL_SMO8800 is not set
# CONFIG_DELL_RBTN is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_AMILO_RFKILL is not set
# CONFIG_HP_ACCEL is not set
# CONFIG_HP_WIRELESS is not set
# CONFIG_MSI_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_COMPAL_LAPTOP is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_IDEAPAD_LAPTOP is not set
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_INTEL_MENLOW is not set
CONFIG_EEEPC_LAPTOP=y
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ACPI_WMI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_IBM_RTL is not set
# CONFIG_SAMSUNG_LAPTOP is not set
# CONFIG_INTEL_OAKTRAIL is not set
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_PVPANIC is not set
# CONFIG_INTEL_PMC_IPC is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_INTEL_PUNIT_IPC is not set
# CONFIG_MLX_PLATFORM is not set
# CONFIG_MLX_CPLD_PLATFORM is not set
# CONFIG_INTEL_TURBO_MAX_3 is not set
CONFIG_PMC_ATOM=y
# CONFIG_CHROME_PLATFORMS is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Common Clock Framework
#
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_NXP is not set
# CONFIG_COMMON_CLK_PXA is not set
# CONFIG_COMMON_CLK_PIC32 is not set
# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# CONFIG_ATMEL_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
# CONFIG_SH_TIMER_MTU2 is not set
# CONFIG_SH_TIMER_TMU is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_MAILBOX=y
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IOVA=y
CONFIG_AMD_IOMMU=y
# CONFIG_AMD_IOMMU_V2 is not set
CONFIG_DMAR_TABLE=y
CONFIG_INTEL_IOMMU=y
# CONFIG_INTEL_IOMMU_SVM is not set
# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
CONFIG_INTEL_IOMMU_FLOPPY_WA=y
# CONFIG_IRQ_REMAP is not set
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
#
# Rpmsg drivers
#
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_VIRTIO is not set
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
#
# Broadcom SoC drivers
#
#
# i.MX SoC drivers
#
#
# Qualcomm SoC drivers
#
# CONFIG_SUNXI_SRAM is not set
# CONFIG_SOC_TI is not set
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
# CONFIG_PWM is not set
#
# IRQ chip support
#
CONFIG_ARM_GIC_MAX_NR=1
# CONFIG_ARM_GIC_V3_ITS is not set
# CONFIG_IPACK_BUS is not set
# CONFIG_RESET_CONTROLLER is not set
# CONFIG_FMC is not set
#
# PHY Subsystem
#
# CONFIG_GENERIC_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
#
# Performance monitor support
#
CONFIG_RAS=y
# CONFIG_THUNDERBOLT is not set
#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDER_DEVICES="binder0,binder1,binder2,binder3,binder4,binder5,binder6,binder7,binder8,binder9,binder10,binder11,binder12,binder13,binder14,binder15,binder16,binder17,binder18,binder19,binder20,binder21,binder22,binder23,binder24,binder25,binder26,binder27,binder28,binder29,binder30,binder31"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
# CONFIG_NVMEM is not set
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_FPGA is not set
#
# FSI support
#
# CONFIG_FSI is not set
#
# Firmware Drivers
#
# CONFIG_EDD is not set
CONFIG_FIRMWARE_MEMMAP=y
# CONFIG_DELL_RBU is not set
# CONFIG_DCDBAS is not set
CONFIG_DMIID=y
# CONFIG_DMI_SYSFS is not set
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
# CONFIG_ISCSI_IBFT_FIND is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_GOOGLE_FIRMWARE is not set
#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_VARS=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_RUNTIME_MAP=y
# CONFIG_EFI_FAKE_MEMMAP is not set
CONFIG_EFI_RUNTIME_WRAPPERS=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_EFI_DEV_PATH_PARSER is not set
#
# Tegra firmware driver
#
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_EXT4_FS_ENCRYPTION=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_QUOTACTL_COMPAT=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_INDEX=y
#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
# CONFIG_CACHEFILES is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
# CONFIG_NFS_V4_1 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_FSCACHE is not set
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=y
# CONFIG_9P_FSCACHE is not set
# CONFIG_9P_FS_POSIX_ACL is not set
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_GDB_SCRIPTS is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
# CONFIG_STACK_VALIDATION is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_PAGE_POISONING=y
CONFIG_PAGE_POISONING_NO_SANITY=y
# CONFIG_PAGE_POISONING_ZERO is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_VM_VMACACHE=y
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_KASAN=y
# CONFIG_KASAN_OUTLINE is not set
CONFIG_KASAN_INLINE=y
# CONFIG_TEST_KASAN is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_KCOV=y
CONFIG_KCOV_ENABLE_COMPARISONS=y
CONFIG_KCOV_INSTRUMENT_ALL=y
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Lockups and Hangs
#
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=1
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
CONFIG_WQ_WATCHDOG=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=86400
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_STACK_END_CHECK=y
# CONFIG_DEBUG_TIMEKEEPING is not set
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
CONFIG_LOCKDEP_CROSSRELEASE=y
CONFIG_LOCKDEP_COMPLETIONS=y
CONFIG_BOOTPARAM_LOCKDEP_CROSSRELEASE_FULLSTACK=y
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_DEBUG_SG is not set
CONFIG_DEBUG_NOTIFIERS=y
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_TORTURE_TEST is not set
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=120
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FAULT_INJECTION=y
CONFIG_FAILSLAB=y
CONFIG_FAIL_PAGE_ALLOC=y
CONFIG_FAIL_MAKE_REQUEST=y
CONFIG_FAIL_IO_TIMEOUT=y
CONFIG_FAIL_FUTEX=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
# CONFIG_LATENCYTOP is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_MMIOTRACE is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
# CONFIG_DMA_API_DEBUG is not set
#
# Runtime Testing
#
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_FIND_BIT is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_MEMTEST is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
# CONFIG_UBSAN is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
# CONFIG_EARLY_PRINTK_EFI is not set
# CONFIG_EARLY_PRINTK_USB_XDBC is not set
# CONFIG_X86_PTDUMP_CORE is not set
# CONFIG_X86_PTDUMP is not set
# CONFIG_EFI_PGT_DUMP is not set
# CONFIG_DEBUG_WX is not set
CONFIG_DOUBLEFAULT=y
# CONFIG_DEBUG_TLBFLUSH is not set
# CONFIG_IOMMU_STRESS is not set
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
CONFIG_IO_DELAY_TYPE_0X80=0
CONFIG_IO_DELAY_TYPE_0XED=1
CONFIG_IO_DELAY_TYPE_UDELAY=2
CONFIG_IO_DELAY_TYPE_NONE=3
CONFIG_IO_DELAY_0X80=y
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEFAULT_IO_DELAY_TYPE=0
CONFIG_DEBUG_BOOT_PARAMS=y
# CONFIG_CPA_DEBUG is not set
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
CONFIG_X86_DEBUG_FPU=y
# CONFIG_PUNIT_ATOM_DEBUG is not set
# CONFIG_UNWINDER_ORC is not set
CONFIG_UNWINDER_FRAME_POINTER=y
# CONFIG_UNWINDER_GUESS is not set
#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_COMPAT=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_BIG_KEYS=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEY_DH_OPERATIONS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITY_WRITABLE_HOOKS=y
# CONFIG_SECURITYFS is not set
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
# CONFIG_INTEL_TXT is not set
CONFIG_LSM_MMAP_MIN_ADDR=65536
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
CONFIG_FORTIFY_SOURCE=y
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_DEFAULT_SECURITY="selinux"
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_MCRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ABLK_HELPER=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_GLUE_HELPER_X86=y
CONFIG_CRYPTO_ENGINE=y
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32_PCLMUL=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_PCLMUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_POLY1305_X86_64=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_RMD256=y
CONFIG_CRYPTO_RMD320=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_SSSE3=y
CONFIG_CRYPTO_SHA256_SSSE3=y
CONFIG_CRYPTO_SHA512_SSSE3=y
CONFIG_CRYPTO_SHA1_MB=y
CONFIG_CRYPTO_SHA256_MB=y
CONFIG_CRYPTO_SHA512_MB=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=y
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_AES_X86_64=y
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_BLOWFISH_X86_64=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAMELLIA_X86_64=y
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=y
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST5_AVX_X86_64=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_CAST6_AVX_X86_64=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DES3_EDE_X86_64=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SALSA20=y
CONFIG_CRYPTO_SALSA20_X86_64=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CHACHA20_X86_64=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SERPENT_SSE2_X86_64=y
CONFIG_CRYPTO_SERPENT_AVX_X86_64=y
CONFIG_CRYPTO_SERPENT_AVX2_X86_64=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
CONFIG_CRYPTO_TWOFISH_X86_64=y
CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=y
CONFIG_CRYPTO_TWOFISH_AVX_X86_64=y
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_PADLOCK=y
CONFIG_CRYPTO_DEV_PADLOCK_AES=y
CONFIG_CRYPTO_DEV_PADLOCK_SHA=y
# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=y
# CONFIG_CRYPTO_DEV_SP_CCP is not set
CONFIG_CRYPTO_DEV_QAT=y
CONFIG_CRYPTO_DEV_QAT_DH895xCC=y
CONFIG_CRYPTO_DEV_QAT_C3XXX=y
CONFIG_CRYPTO_DEV_QAT_C62X=y
CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y
CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y
CONFIG_CRYPTO_DEV_QAT_C62XVF=y
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=y
CONFIG_SIGNED_PE_FILE_VERIFICATION=y
#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
CONFIG_SECONDARY_TRUSTED_KEYRING=y
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_KVM_COMPAT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_KVM_INTEL=y
CONFIG_KVM_AMD=y
# CONFIG_KVM_MMU_AUDIT is not set
CONFIG_VHOST_NET=y
# CONFIG_VHOST_VSOCK is not set
CONFIG_VHOST=y
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC4=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
# CONFIG_CRC8 is not set
# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_INTERVAL_TREE=y
CONFIG_RADIX_TREE_MULTIORDER=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
# CONFIG_DMA_NOOP_OPS is not set
# CONFIG_DMA_VIRT_OPS is not set
CONFIG_CHECK_SIGNATURE=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_SG_SPLIT is not set
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_PMEM_API=y
CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
[-- Attachment #3: raw.log --]
[-- Type: application/octet-stream, Size: 1048576 bytes --]
xffffffffffffffff, 0x0)
getsockopt$sock_cred(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000b1c000-0xc)={<r1=>0x0, 0x0, 0x0}, &(0x7f00002dc000)=0xc)
getpgid(r1)
getpgid(0x0)
r2 = socket$inet6_udp(0xa, 0x2, 0x0)
openat$selinux_policy(0xffffffffffffff9c, &(0x7f000012f000)="2f73656c696e75782f706f6c69637900", 0x0, 0x0)
r3 = open(&(0x7f0000666000-0x8)="2e2f66696c653000", 0x200000, 0x23)
accept$unix(r3, &(0x7f00007c0000)=@file={0x0, "0000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f00004fd000)=0x28)
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f00004dd000)=<r4=>0x0)
sched_setaffinity(r4, 0x8, &(0x7f00001c2000-0x8)=0x9)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xdcf000)=nil, 0xdcf000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r5 = socket$inet_tcp(0x2, 0x1, 0x0)
ioctl$sock_ifreq(r5, 0x89f0, &(0x7f0000853000)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_data=&(0x7f00000ed000-0x20)="0d00000000000000db0001ee000800000000000000ab0000df7fe6000d722a32"})
mmap(&(0x7f0000dcf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = socket$inet6(0xa, 0xa, 0x8000002)
connect$inet6(r6, &(0x7f000095e000)={0xa, 0x3, 0x1000000, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x6}, 0x1c)
r7 = open(&(0x7f0000dd9000-0x8)="2e2f66696c653000", 0x80, 0x2000000000000020)
ioctl$DRM_IOCTL_MODE_SETCRTC(r7, 0xc06864a2, &(0x7f0000ab7000)={&(0x7f000037f000)=[0x401], 0x1, 0x4, 0x1, 0x410, 0x1, 0x6, {0x4, 0x7f, 0x38e1, 0x10001, 0x28c, 0xfffffffffffffff9, 0x67d, 0x5, 0xffff, 0x57, 0x8, 0x7f, 0x9, 0x80, "6e2382f1fff7d5c5aed2a863ac7761c31b9a67701f263eebc44b6379a379aef7"}})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
semop(0x0, &(0x7f0000cc6000-0xc)=[{0x0, 0x1, 0x0}, {0x0, 0x0, 0x0}], 0x2)
timer_gettime(0x0, &(0x7f0000921000)={{0x0, 0x0}, {0x0, 0x0}})
r8 = semget(0x3, 0x2, 0x10)
r9 = semget$private(0x0, 0x0, 0x408)
semctl$GETZCNT(r9, 0x0, 0xf, &(0x7f000073e000)="")
semget$private(0x0, 0xfffffffffffffff9, 0x20000088100425)
semctl$SEM_INFO(r8, 0x3, 0x13, &(0x7f0000a8d000-0xd5)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
msync(&(0x7f0000952000/0x2000)=nil, 0x87abbe8d1cc6ad9, 0x4)
[ 48.884762] binder: 6952:6954 BC_REQUEST_DEATH_NOTIFICATION invalid ref 0
[ 48.895969] sctp: [Deprecated]: syz-executor4 (pid 6983) Use of int in max_burst socket option deprecated.
[ 48.895969] Use struct sctp_assoc_value instead
[ 48.953678] sctp: [Deprecated]: syz-executor4 (pid 6983) Use of int in max_burst socket option deprecated.
[ 48.953678] Use struct sctp_assoc_value instead
[ 48.999352] binder: undelivered TRANSACTION_ERROR: 29189
[ 49.009088] kvm: emulating exchange as write
2017/12/15 11:53:25 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = memfd_create(&(0x7f0000dc9000-0x3)="6c6f00", 0x1)
ioctl$sock_FIOGETOWN(r0, 0x8903, &(0x7f0000ff2000)=<r1=>0x0)
ioprio_set$pid(0x3, r1, 0x2000000000000007)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$sg(&(0x7f0000632000-0x9)="2f6465762f73672300", 0xffffffffffffffff, 0x40)
setsockopt$inet_sctp_SCTP_SOCKOPT_BINDX_REM(r2, 0x84, 0x65, &(0x7f00002b7000)=[@in={0x2, 0x2, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0xa2b1, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x1}, @in={0x2, 0x1, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x3, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x129}], 0x4)
r3 = openat$hwrng(0xffffffffffffff9c, &(0x7f0000890000)="2f6465762f6877726e6700", 0x40000, 0x0)
perf_event_open(&(0x7f00008a8000-0x78)={0x3ffffffffe, 0x78, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x1, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000e12000+0x925)={0x2, 0x78, 0xdb, 0x19, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x8000, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0x7, 0xffc, 0x0, 0x800041aeac57, 0x0}, r1, 0x9, 0xffffffffffffffff, 0xb)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdf, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x6)
shutdown(r0, 0xffffffffffffffff)
r4 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
setsockopt$inet_tcp_buf(r2, 0x6, 0x1d, &(0x7f000072b000)="70960c8c88b673ddf9e9f0f7f2f1b138038dd5a0f8b08c219bcfab164c935fce8ef0feb5b983bb1f2436e929831b9f02", 0x30)
r5 = syz_open_dev$sg(&(0x7f0000527000-0x9)="2f6465762f73672300", 0x0, 0x2)
write$sndseq(r5, &(0x7f0000647000)=[{0x6, 0x53ec, 0x8b4, 0x10a084b3, @tick=0x0, {0x6, 0x0}, {0x24, 0x9}, @queue={0x4, {0x2, 0x4}}}, {0x8, 0xff, 0xb7, 0x7fffffff, @tick=0x101, {0x1ff, 0x2}, {0xffffffff, 0x3}, @ext={0x47, &(0x7f0000624000)="34508e94ac83b7070ae31792d55ed27142ffc7cf1188e8f519e163df3306860992e5f539be8108b928d18820303c2f558185a781ba50be1e4f4410fff706c1caf8926bcfafc4e3"}}, {0x4, 0x100000000, 0x3, 0x376, @tick=0x6, {0x1, 0x4}, {0x5, 0xffff}, @addr={0x8000, 0xaf}}, {0x100000000, 0x100000000, 0x9, 0x6, @tick=0x9, {0x1f, 0x7}, {0x400000004, 0xffff}, @control={0xf7f, 0x3f, 0x6}}, {0x7, 0x80000001, 0xfffffffffffffffa, 0x3, @tick=0x3, {0x100000000, 0x80000000}, {0x4, 0xfffffffffffffff7}, @control={0x101, 0x7fff, 0x6}}], 0xf0)
fstat(r2, &(0x7f00009ed000-0x44)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
ioctl$int_in(r4, 0x5429, &(0x7f0000d07000-0x8)=0x5)
setsockopt$inet6_tcp_int(r3, 0x6, 0x12, &(0x7f0000c95000-0x4)=0x5, 0x4)
r6 = memfd_create(&(0x7f0000fd9000-0x2)="68f2", 0x0)
ioctl(r5, 0x227c, &(0x7f0000ac7000)="")
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_opts(r0, 0x0, 0x1, &(0x7f0000dea000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000001000-0x4)=0x6c)
ioctl$DRM_IOCTL_AGP_ALLOC(r6, 0xc0206434, &(0x7f00008ef000-0x20)={0x6, <r7=>0x0, 0x10010001, 0x5})
ioctl$DRM_IOCTL_SG_ALLOC(r0, 0xc0106438, &(0x7f0000f5b000-0x10)={0xffff, r7})
bpf$MAP_GET_NEXT_KEY(0x4, &(0x7f0000f43000)={r2, &(0x7f0000843000)="359b0d8bebfa2d9aca21e25d0ae30cf9dc8dc83cc8ff5fa75755679e3a1729fc45baaa403bddc0501d529a39b90d957b280935304f2200ce6efde0e20616674f5b09c401879d3972743337a2962a63b33c3942fd5dfe0f6d11bbc10c4a390e8a297a0c130a04546beb8ebcaf96c79e6e7c6361f9ba564bcedfb49544f555f0b5aaba690b0277424b1b2ec5f38e575186b3db757ec2673f14c27c6ff34ffa4e3388c00ea97da363aee91577737d2503b19299d3ec024b2301ec0a7b6e12399c89e2bc19bb3f31a56a5e49a1d6108fc46033fd19f92c185a6661d168674f12dd8fc1c36755", &(0x7f00006b7000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x18)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:25 executing program 1:
mmap(&(0x7f0000011000/0x3000)=nil, 0x3000, 0x1, 0x32, 0xffffffffffffffff, 0x0)
r0 = userfaultfd(0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$UFFDIO_API(r0, 0xc018aa3f, &(0x7f0000002000)={0xaa, 0x0, 0x0})
ioctl$UFFDIO_REGISTER(r0, 0xc020aa00, &(0x7f0000001000)={{&(0x7f0000011000/0x3000)=nil, 0x3000}, 0x1, 0x0})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000012000)={<r1=>0x0, <r2=>0x0})
r3 = fcntl$dupfd(r0, 0x0, r0)
ioctl$EVIOCGMTSLOTS(r1, 0x8040450a, &(0x7f0000014000-0x22)="00000000000000000000000000000000000000000000000000000000000000000000")
ioctl$KDENABIO(r2, 0x4b36)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
renameat2(r2, &(0x7f0000011000)="2e2f66696c653000", r3, &(0x7f0000003000)="2e2f66696c653000", 0x1)
timer_settime(0x0, 0x1, &(0x7f0000011000)={{0x77359400, 0x0}, {0x77359400, 0x0}}, &(0x7f0000000000)={{0x0, <r4=>0x0}, {0x0, 0x0}})
renameat(r2, &(0x7f0000011000)="2e2f66696c653000", r2, &(0x7f0000000000)="2e2f66696c653000")
clock_settime(0x1, &(0x7f0000013000-0x10)={0x0, r4})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x2, 0x32, 0xffffffffffffffff, 0x0)
ioctl$UFFDIO_ZEROPAGE(r0, 0xc020aa04, &(0x7f0000203000)={&(0x7f0000bb7000/0x3000)=nil, 0x3000})
clone(0x0, &(0x7f0000b26000)="", &(0x7f0000eaa000-0x4)=0x0, &(0x7f0000bf3000-0x4)=0x0, &(0x7f00003b9000-0xcd)="")
ioctl$UFFDIO_ZEROPAGE(r0, 0x8010aa02, &(0x7f00000c1000-0x10)={&(0x7f0000011000/0x3000)=nil, 0x3000})
2017/12/15 11:53:25 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet6_sctp(0xa, 0x3, 0x84, &(0x7f00000ff000)={<r0=>0x0, 0x0})
getsockopt$inet_sctp6_SCTP_NODELAY(r0, 0x84, 0x3, &(0x7f0000966000-0x4)=0x0, &(0x7f00008a9000)=0x4)
r1 = socket(0x17, 0x4, 0x6)
ioctl$sock_inet6_udp_SIOCOUTQ(r1, 0x5411, &(0x7f0000130000-0x4)=0x0)
r2 = bpf$PROG_LOAD(0x5, &(0x7f0000ee7000-0x30)={0x1, 0x1, &(0x7f0000ee7000-0x10)=[@generic={0x0, 0x0, 0xa7, 0x0}], &(0x7f000000a000)="87797374656d00", 0xffffff7ffffffff9, 0x80, &(0x7f0000646000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
mmap(&(0x7f0000000000/0xf73000)=nil, 0xf73000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$alg(0x26, 0x5, 0x0)
close(r2)
r3 = socket$alg(0x26, 0x5, 0x0)
setsockopt$ALG_SET_AEAD_AUTHSIZE(r3, 0x117, 0x5, 0x0, 0x0)
r4 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r1, &(0x7f0000f93000)={0x26, "726e670000000000000000000000", 0x0, 0x1, "647262675f6e6f70725f736861333834000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$ALG_SET_KEY(r4, 0x117, 0x1, &(0x7f0000797000-0x21)="0a0775b0d5ce83e5b3b60ced5c54dbb7295df0df8217ad4000000000000000e62a", 0x21)
r5 = accept$alg(r4, 0x0, 0x0)
recvmsg(r4, &(0x7f0000cd3000-0x38)={0x0, 0x0, &(0x7f0000ffe000-0x80)=[], 0x0, &(0x7f0000f71000-0x14)="0000000000000000000000000000000000000000", 0x14, 0x3}, 0x3d5a1db4cedf06e6)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmsg$alg(r5, &(0x7f0000f6d000)={0x0, 0x0, &(0x7f000031a000)=[{&(0x7f0000a8b000)="e07e0d0000000000003a84ee0abe8a", 0xf}, {&(0x7f0000eb4000)="d72f4d3d94a2625b227b0c25245f90858805bc6e00727514304e5834cfc94a1bbfadadb75dfcd122162231c47c23289f832d6c11063638ce3d6680b3e8be40a3b05d773c93a9762944320b9712183147e598eb8a4254e52e47593511e7fda6752e5b001d4832adc24750d83233ef180c33bffb94bdb1fba4064c9789ed6c5671b1c43602372d37b4de44cd9664c1c45db060bca47cd3151e90406b", 0x9b}, {&(0x7f0000e28000)="8992236fecb840000000000000009fc2f673910385e49e4f386a0ff64f41bcab7452eb07d6a353d5f6520e19ee61c78353334030519cd4b0003dbd464a29dc95b03b75f1429866350900003bbc52d66e0de5e758dd40599b70f58945196dc2a1022db60f4edcfa9899ed794143a72da8133f7bc07df868958c93ec69b3e3e8", 0x7f}, {&(0x7f000020c000-0xe2)="ef89da552dd330bcadfed9e746aa47bd70a9227eeb7210410a3f121e11683e61bb69c74cc9242bbda84ef11e1cfa9412c485b041877d4ee572105ed51bb1769f34d9fb498b24c8591e8aefdd08cbf41ede1f02e204f00e6f6ec04c21be760c72880da0ca6e01ea5dfe63786136cf3597eaa50389f5eabbb2f33eee7e2b96c1c92590cca3cfa2320d1e3643599fc8e45e824412f3a7432e4319e2abe0a370c274aba6c7d674f8ebb4416e523b8080042727795be956e4971ec0361cbd4813eba7d5617ce9d7d31caaf57214787ca945ef2f4c799bb9e76ae5847eaed2d17600124f", 0xe1}, {&(0x7f0000206000)="8561b7a0e627acd3a48d8b9f30c6d215c928bf2f5736097e1e283522044672aa4155d800000040cf28a2bd5ae7abd49744248b986fcef2d9e8ea1ef3b930ae82f03deffad4a4bc4ce29c3f57", 0x4c}, {&(0x7f0000f74000-0xe1)="99eac84d6a3828b426e0d2bd94a372440296e7dbd81f7612aaee2b98e359972268a6af8bb583511ab042180436c76c32970e44798ed07d43ab574b074b21e9a99da113d6d97363de0e14ea35948cfcd4e33b238769b5d816af54d725d9e0892fb493649e59bd10170b458b63ccda771d5c26156bdc372e736f4cad146efde6570ab31f177183b8325edb58a0b7ed4859e31ee77c7aed8fbebdf4f1bd54d38d684e74fba79cebae37a8d063fb487688b4422341a445637a86f7ed56f82dfd43d4a2744b5a7997da7a30de752718e12eb78a87b2aa694aaf6fc509d305842f108c80", 0xe1}, {&(0x7f0000f75000-0x1f)="c06b3a247fe5e051d3007662067db4d932c52b788f2a2137c80aaab29cd6d2", 0x1f}, {&(0x7f0000e3a000-0x39)="f06bf7cd469f89c692db8ce5f8a5ad8e755f50800c2528d688a580ba0f00edff1bfec8a00695fc50ed59d372f4fb3c2e2d8b1578d1ac44b620", 0x39}], 0x8, &(0x7f00009c7000-0x90)=[@op={0x18, 0x117, 0x3, 0x1}, @op={0x18, 0x117, 0x3, 0x0}, @op={0x18, 0x117, 0x3, 0x0}, @assoc={0x18, 0x117, 0x4, 0x9}, @op={0x18, 0x117, 0x3, 0x1}, @assoc={0x18, 0x117, 0x4, 0x14}], 0x90, 0x20004000}, 0x4)
close(r0)
recvmsg(r5, &(0x7f000022f000-0x38)={&(0x7f0000f6f000-0x10)=@ethernet={0x0, @random="000000000000", [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000893000-0x50)=[{&(0x7f0000e72000-0x84)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x84}, {&(0x7f0000f6f000-0x79)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x79}, {&(0x7f0000f73000-0xd5)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd5}, {&(0x7f0000e69000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0}, {&(0x7f0000f6e000)="000000000000000000000000", 0xc}], 0x5, &(0x7f00008ae000-0x46)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x46, 0x8}, 0x2)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$bt_hidp(0x1f, 0x3, 0x6)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockname(r5, &(0x7f0000004000-0x9)=@rc={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0}, &(0x7f0000002000)=0x9)
2017/12/15 11:53:25 executing program 2:
mmap(&(0x7f0000000000/0xfef000)=nil, 0xfef000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$inet_mreqsrc(r0, 0x0, 0x28, &(0x7f00008d3000-0xc)={@multicast2=0xe0000002, @rand_addr=0x80000000, @multicast2=0xe0000002}, 0xc)
r1 = socket$inet_tcp(0x2, 0x1, 0x0)
mmap(&(0x7f0000fef000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet_SIOCSARP(r0, 0x8955, &(0x7f0000ff0000-0x44)={{0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x6, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x15, {0x2, 0x2, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @syzn={0x73, 0x79, 0x7a, 0x0, 0x0}})
getsockopt$inet_IP_IPSEC_POLICY(r1, 0x0, 0x10, &(0x7f0000bfd000-0xe8)={{{@in=@empty=0x0, @in=@multicast1=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r2=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0}, 0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000fec000-0x4)=0xe8)
mmap(&(0x7f0000ff0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_mreqn(r0, 0x0, 0x0, &(0x7f0000ff1000-0xc)={@loopback=0x7f000001, @multicast1=0xe0000001, r2}, 0xc)
socketpair$inet6_tcp(0xa, 0x1, 0x0, &(0x7f000000f000+0xef)={<r3=>0xffffffffffffffff, <r4=>0xffffffffffffffff})
setsockopt$inet6_tcp_TCP_REPAIR_OPTIONS(r4, 0x6, 0x16, &(0x7f0000018000-0x18)=[{0x0, 0x5f7f}, {0x3, 0x5}, {0x3, 0x80000001}], 0x3)
mmap(&(0x7f0000ff0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ff0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet6_SIOCDIFADDR(r3, 0x8936, &(0x7f0000ff1000-0x18)={@loopback={0x0, 0x1}, 0xa, r2})
syz_extract_tcp_res(&(0x7f00003c9000)={<r5=>0x42424242, 0x42424242}, 0x100000001, 0x1ff)
syz_emit_ethernet(0xfa, &(0x7f0000fed000)={@random="b346d37206e1", @random="de895db1468d", [], {{0x86dd, @ipv6={0x8, 0x6, "a228af", 0xc4, 0x0, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, {[@routing={0x2f, 0xc, 0x1, 0x10003, 0x45c, [@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @loopback={0x0, 0x1}, @loopback={0x0, 0x1}, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @loopback={0x0, 0x1}]}, @routing={0x3f, 0x8, 0x0, 0x80000001, 0x9, [@local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @loopback={0x0, 0x1}, @loopback={0x0, 0x1}]}], @tcp={{0x0, 0x0, 0x42424242, r5, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, {[]}}, {""}}}}}}}, 0x0)
mmap(&(0x7f0000000000/0x926000)=nil, 0x926000, 0x2, 0x35, 0xffffffffffffffff, 0x0)
r6 = socket(0x10, 0x2, 0x0)
sendmsg$netlink(r6, &(0x7f000024b000-0x38)={0x0, 0x0, &(0x7f000061d000)=[{&(0x7f000061d000-0x24)=[{0x20, 0x1d, 0x305, 0x0, 0x0, "900000000000000004000301040001"}], 0x20}], 0x1, &(0x7f0000618000)=[], 0x0, 0x0}, 0x0)
poll(&(0x7f0000fec000-0x40)=[], 0x0, 0x100)
syz_emit_ethernet(0x98, &(0x7f0000012000)={@random="e7a5fd000000", @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [{[], {0x8100, 0x9, 0x1000000000000007, 0xffff}}], {{0x0, @x25={0x2, 0x2867, 0xb, "091757a90b7d55d0c490a0081a3706cffba30fec3337c305aca0c288c9e7a68350f25e27409f0dd597835d1810df8608e8d4aea9bfa1931273ac7704815910be8a0c6f14a217ca17930b3c660857af4a1fc387dc4d4b6209a56f77d4736cf2c4e7f7326434d4b4694abcf297b82b495e655d9b2451277949547690e70d1b50b388a04b"}}}}, 0x0)
mmap(&(0x7f0000ff1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet_SIOCSIFADDR(r0, 0x8916, &(0x7f000070a000-0x20)={@common="79616d30000000000000000000000000", @ifru_addrs={0x2, 0x1, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
syz_emit_ethernet(0x8a, &(0x7f0000aee000-0x8a)={@empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [{[], {0x8100, 0x2, 0xff, 0x1}}], {{0x88f5, @ipx={0xffff, 0x78, 0x101, 0x5, {@broadcast=0xffffffff, @random="2952b4cc3f96", 0x20}, {@broadcast=0xffffffff, @current=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x4}, "44b456d05ce34ae051d3b00fdf5769c6c6fbaa2efce3fed3a663c2195c60a246927fe949f4ff7a6ade39f1ebfd8ca31752e3c359ab518381603694afb106f615276d711dd8aa255d97d388ea3f6fe293da0ea5b6e17dda5e27b7"}}}}, 0x0)
ioctl$sock_inet_SIOCDARP(r1, 0x8953, &(0x7f0000fef000-0x44)={{0x2, 0x0, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x0, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0xfffffffffffffffd, {0x2, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @generic="007203fb04a922e804e7d5688bc88902"})
setsockopt$inet_msfilter(r6, 0x0, 0x29, &(0x7f000000e000-0x1c)={@multicast2=0xe0000002, @loopback=0x7f000001, 0x1, 0x3, [@broadcast=0xffffffff, @rand_addr=0x2, @empty=0x0]}, 0x1c)
setsockopt$inet_mreqsrc(r1, 0x0, 0x2c, &(0x7f0000008000-0xc)={@loopback=0x7f000001, @multicast1=0xe0000001, @empty=0x0}, 0xc)
socket$inet(0x2, 0x0, 0x1007ff)
mmap(&(0x7f0000000000/0xfef000)=nil, 0xfef000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r7 = socket$inet6(0xa, 0x800000000003, 0x2)
setsockopt$inet6_mreq(r7, 0x29, 0x1b, &(0x7f0000de3000+0xe11)={@remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x0}, 0x14)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:25 executing program 7:
mmap(&(0x7f0000000000/0xafc000)=nil, 0xafc000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6_udp(0xa, 0x2, 0x0)
r1 = syz_open_dev$vcsn(&(0x7f0000afc000)="2f6465762f7663732300", 0x7fffffff, 0x608080)
mmap(&(0x7f0000afc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_tcp_TCP_MD5SIG(r1, 0x6, 0xe, &(0x7f0000afc000)={{{{0x2, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0xa, 0x1, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x800}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x5a, 0xbe, 0xa, "928fd4f688b474770a8ab6e445d161c2368e3d1b5fed55ff15f410d2105e31ca21dea9560fe26aa70749280a7de7af4bee49268a6d5da7137ba5b36d8bfac73499d1b967a27255ac8d2c0b54050171bf"}, 0x160)
mmap(&(0x7f0000afd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_buf(r0, 0x29, 0x17, &(0x7f0000afd000)="0f57", 0x2)
mmap(&(0x7f0000afe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$kvm(0xffffffffffffff9c, &(0x7f0000afe000)="2f6465762f6b766d00", 0x23fffe, 0x0)
mmap(&(0x7f0000afc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$LOOP_CHANGE_FD(0xffffffffffffffff, 0x4c00, r0)
r3 = ioctl$KVM_CREATE_VM(r2, 0xae01, 0x0)
ioctl$KVM_CREATE_IRQCHIP(r1, 0xae60)
r4 = creat(&(0x7f0000afa000)="2e2f66696c653000", 0x22)
mmap(&(0x7f0000afd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000afe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000aff000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fsetxattr(r3, &(0x7f0000b00000-0x10)=@random={"757365722e00", "2f6465762f7663732300"}, &(0x7f0000a48000)="2f6465762f6b766d00", 0x9, 0x2)
mmap(&(0x7f0000afe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000afe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000afe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_FIOGETOWN(r0, 0x8903, &(0x7f0000aff000-0x4)=<r5=>0x0)
ioctl$sock_FIOSETOWN(r1, 0x8901, &(0x7f0000722000-0x4)=r5)
ioctl$KVM_SET_MSRS(r4, 0x4008ae89, &(0x7f00001f3000)={0x4, 0x0, [{0xffffffff7fffffff, 0x0, 0x6}, {0x200, 0x0, 0x6}, {0x9, 0x0, 0x9}, {0xfffffffffffffe01, 0x0, 0x6}]})
ioctl$KVM_CREATE_VCPU(r1, 0xae41, 0x2)
socket(0x16, 0x80000, 0x7)
setsockopt$netlink_NETLINK_ADD_MEMBERSHIP(r1, 0x10e, 0x1, &(0x7f00000f1000)=0x10001, 0x4)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = accept4$inet(0xffffffffffffffff, &(0x7f0000000000)={0x0, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f00002b7000-0x4)=0x10, 0x80800)
setsockopt$inet_mtu(r6, 0x0, 0xa, &(0x7f0000243000-0x4)=0x1, 0x4)
2017/12/15 11:53:25 executing program 3:
socket$netlink(0x10, 0x3, 0x0)
pipe(&(0x7f0000ad2000-0x8)={<r0=>0x0, <r1=>0x0})
getsockopt$inet6_IPV6_XFRM_POLICY(r0, 0x29, 0x23, &(0x7f0000e74000-0xe8)={{{@in=@multicast1=0x0, @in=@broadcast=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in=@remote={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f000021a000)=0xe8)
setsockopt$sock_int(r0, 0x1, 0x0, &(0x7f000052a000-0x4)=0x18b8, 0x4)
r2 = socket$inet_tcp(0x2, 0x1, 0x0)
getsockopt$inet_sctp6_SCTP_PEER_ADDR_THLDS(r1, 0x84, 0x1f, &(0x7f0000f69000-0x98)={<r3=>0x0, @in6={{0xa, 0x0, 0x80000000, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0xe9b}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1ff, 0x1}, &(0x7f00004a6000-0x4)=0x98)
setsockopt$inet_sctp_SCTP_AUTH_KEY(r1, 0x84, 0x17, &(0x7f00009f8000-0x43)={r3, 0x0, 0x3b, "49f458e5c2dc20e039639265f29707e72cc0e0298ee0370a80292332d2b8ae49dfe0f0b0a18af8330067620ce7baa5ba610983ea44108b009d2156"}, 0x43)
ioctl$DRM_IOCTL_AGP_FREE(0xffffffffffffffff, 0x40206435, &(0x7f0000000000)={0x6, 0x0, 0x0, 0xfffffffffffffffc})
fcntl$setsig(r2, 0xa, 0x9)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_RES_CTX(r0, 0xc0106426, &(0x7f0000c93000)={0x7, &(0x7f0000001000-0x38)=[{<r4=>0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}]})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_UNLOCK(r1, 0x4008642b, &(0x7f0000000000)={r4, 0x8})
r5 = dup2(r2, r2)
ioctl$LOOP_CTL_ADD(r5, 0x4c80, 0x0)
r6 = socket(0xa, 0x1, 0x0)
clock_nanosleep(0x6, 0x0, &(0x7f0000e10000)={0x0, 0x989680}, &(0x7f0000bce000)={0x0, 0x0})
getpeername$ipx(r6, &(0x7f0000014000-0x10)={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, &(0x7f000087b000-0x4)=0x10)
epoll_ctl$EPOLL_CTL_ADD(r5, 0x1, r0, &(0x7f0000ab3000)={0x8, 0x0})
ioctl$sock_inet6_udp_SIOCOUTQ(r6, 0x5411, &(0x7f0000e16000-0x4)=0x0)
ioctl(r6, 0x800000000008982, &(0x7f0000000000)="")
ioctl$TIOCSTI(r1, 0x5412, 0xffffffff)
r7 = socket$inet_udp(0x2, 0x2, 0x0)
ioctl$KDGKBMODE(r5, 0x4b44, &(0x7f0000a18000)=0x0)
ioctl$sock_SIOCBRDELBR(r2, 0x89a1, &(0x7f00000b2000-0x10)=@common="73697430000000000000000000000000")
sysfs$1(0x1, &(0x7f000072c000-0x15)="7d776c616e31657468302570726f63776c616e3000")
ioctl$sock_inet6_tcp_SIOCINQ(r0, 0x541b, &(0x7f0000499000)=0x0)
ioperm(0x8, 0x25, 0x10000)
creat(&(0x7f0000ed5000)="2e2f66696c653000", 0x20)
pread64(r7, &(0x7f0000505000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1000, 0x0)
setsockopt$inet_mreqsrc(r2, 0x0, 0x27, &(0x7f000071a000-0xc)={@multicast2=0xe0000002, @broadcast=0xffffffff, @rand_addr=0x1}, 0xc)
ioctl$sock_ifreq(r7, 0x8983, &(0x7f0000006000)={@generic="1b520310b564c42354e2d0b8a14e1ad7", @ifru_settings={0x0, 0x0, @fr_pvc_info=&(0x7f0000006000)={0x0, @common="6c6f0000000000000000000000000000"}}})
setsockopt$inet_buf(r2, 0x0, 0x10, &(0x7f0000ef1000-0xc0)="18000000020001000000be8c5ee18c883600003f0000000000000000988a3cdcc3f7b933c598055bf74852bb6a8807567f59dba67e1947b3550400000067a1e1e20067fc2163e000000000000003ff1f00000000000000c88ebbff060100000b00090000b121ec1474d733f542000700ec008bc5cfb7ebe7ec7ee87cccfffbba000000024f0298e9e9f55406aa0110ddfdff030100000000d791a2ffe3c5632c1adb8a335bd8b2d17fdea21b571068393d22b5affa00041ad0b4d2c23eef6795", 0xc0)
2017/12/15 11:53:25 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$vcs(0xffffffffffffff9c, &(0x7f00002c2000)="2f6465762f76637300", 0x400, 0x0)
fcntl$addseals(r0, 0x409, 0x3)
ioctl$KVM_GET_TSC_KHZ(r0, 0xaea3)
perf_event_open(&(0x7f0000cda000-0x78)={0x2, 0x78, 0xe13, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp6_SCTP_RECVRCVINFO(r0, 0x84, 0x20, &(0x7f0000126000-0x4)=0x100000001, 0x4)
nanosleep(&(0x7f000055f000)={0x0, 0x989680}, &(0x7f0000841000)={0x0, 0x0})
r1 = openat$autofs(0xffffffffffffff9c, &(0x7f000043e000-0xc)="2f6465762f6175746f667300", 0x100, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x2, 0x0, &(0x7f0000506000-0x8)={0xffffffffffffffff, <r2=>0xffffffffffffffff})
r3 = bpf$PROG_LOAD(0x5, &(0x7f0000b4d000-0x30)={0x1, 0x2, &(0x7f0000ef3000)=[@generic={0x8db7, 0x0, 0x0, 0x0}, @generic={0xd395, 0x0, 0x0, 0x0}], &(0x7f0000b4d000)="737973654f00", 0x1, 0x80, &(0x7f000000a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
r4 = socket$kcm(0x29, 0x2, 0x0)
getsockopt$inet6_buf(r1, 0x29, 0x0, &(0x7f0000098000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000365000)=0x90)
listen$netrom(r0, 0x4)
ioctl$sock_kcm_SIOCKCMATTACH(r4, 0x89e0, &(0x7f0000ef7000)={r2, r3})
socket$inet6(0xa, 0x0, 0x8010000000000084)
connect$unix(r2, &(0x7f00000d9000)=@abs={0x0, 0x0, 0x2}, 0x8)
setsockopt$inet_sctp6_SCTP_HMAC_IDENT(r1, 0x84, 0x16, &(0x7f000058a000-0x14)={0x0, []}, 0x4)
shutdown(r2, 0x0)
r5 = openat$sequencer2(0xffffffffffffff9c, &(0x7f0000e41000-0x10)="2f6465762f73657175656e6365723200", 0x100, 0x0)
ioctl$sock_inet_tcp_SIOCATMARK(r1, 0x8905, &(0x7f00005a7000-0x4)=0x0)
stat(&(0x7f0000c26000+0x2cf)="2e2f66696c653000", &(0x7f000003d000-0x44)={0x0, 0x0, 0x0, 0x0, <r6=>0x0, <r7=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
r8 = accept$inet6(r0, &(0x7f0000409000-0x1c)={0x0, 0x0, 0x0, @local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0}, &(0x7f00004e0000)=0x1c)
fchown(r1, r6, r7)
setfsuid(r6)
ioctl$EVIOCGABS3F(r5, 0x8018457f, &(0x7f0000374000-0x7b)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
bind(r8, &(0x7f00003d1000-0x10)=@llc={0x1a, 0x1f, 0x3, 0x6, 0x20, 0x7, @random="df033d942369", [0x0, 0x0]}, 0x10)
ioctl$LOOP_SET_STATUS64(r5, 0x4c04, &(0x7f00001c2000)={0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0xf, 0x17, 0x8, "49d186cd8690e6b125323323e8f048dbcb660b29c6bb890b2c7e046ca903312358c8a77d4620a1d6870e988fd0542acc9ee9a90489da4988512e64dbd6bb8608", "03ee20607259ea377267a0a01580c225ad4715d14b646b3dfab7435922f50c828227197a266db5d839f124fd257591431154d47974b861bc006aa98376563a88", "be429a2eca4e2d66aade595106d12f906aeffdff3e3b0209eda5ca2a7fd00445", [0xd, 0x8]})
ioprio_set$uid(0x3, r6, 0x1)
2017/12/15 11:53:25 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$autofs(0xffffffffffffff9c, &(0x7f0000001000-0xc)="2f6465762f6175746f667300", 0x0, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_IPV6_XFRM_POLICY(r0, 0x29, 0x23, &(0x7f0000001000)={{{@in=@rand_addr=0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@multicast1=0x0, 0x0, 0x0}, 0x0, @in=@broadcast=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000000000)=0xe8)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$EVIOCGID(r0, 0x80084502, &(0x7f0000000000)="000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000000000/0x1c000)=nil, 0x1c000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket$inet_tcp(0x2, 0x1, 0x0)
ioctl$KVM_SET_SIGNAL_MASK(r0, 0x4004ae8b, &(0x7f0000a77000-0x3f)={0x3b, "2ea08230675323bc362aa9378029a8068105c687cd8e66d9dd2ee6ef4657e8d67ebd70013d1b84a1f67c21442c94504d44cea040281fd63610b79b"})
prctl$void(0x27)
sendmmsg$unix(0xffffffffffffffff, &(0x7f0000008000)=[{&(0x7f0000000000)=@file={0x0, "2e2f66696c653000"}, 0xa, &(0x7f0000001000-0x70)=[], 0x0, &(0x7f0000000000)=[@rights={0x18, 0x1, 0x1, [r1, 0xffffffffffffffff]}], 0x1, 0x0}, {&(0x7f0000000000)=@file={0x0, "2e2f66696c653000"}, 0xa, &(0x7f0000001000-0x10)=[], 0x0, 0x0, 0x0, 0x0}], 0x2, 0x0)
ioctl$KVM_SET_CPUID2(r0, 0x4008ae90, &(0x7f0000011000-0xa8)={0x4, 0x0, [{0x40000000, 0x10000, 0x3, 0x7, 0x342b, 0x3, 0x9, [0x0, 0x0, 0x0]}, {0x40000000, 0x8, 0x3, 0x7, 0x33, 0x2, 0xeed0, [0x0, 0x0, 0x0]}, {0x80000001, 0x9, 0x1, 0x8, 0x4, 0x9, 0x1, [0x0, 0x0, 0x0]}, {0x40000006, 0x2, 0x7, 0x0, 0xe2880000000000, 0xffffffff80000000, 0x3ff, [0x0, 0x0, 0x0]}]})
syz_emit_ethernet(0x11, &(0x7f0000001000-0x11)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @random="f7e2dea5391b", [], {{0x800, @x25={0x5, 0xff, 0xb, ""}}}}, 0x0)
getgroups(0x1, &(0x7f000000a000-0x4)=[<r2=>0xffffffffffffffff])
inotify_init()
getsockopt$SO_PEERCRED(r1, 0x1, 0x11, &(0x7f00004e0000-0xc)={0x0, 0x0, 0x0}, 0xc)
setfsgid(r2)
mmap(&(0x7f000001c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair(0x15, 0x6, 0x4, &(0x7f000001c000)={0x0, <r3=>0x0})
r4 = socket(0xa, 0x3, 0x1)
getpeername$inet6(r4, &(0x7f000066b000-0x1c)={0x0, 0x0, 0x0, @loopback={0x0, 0x0}, 0x0}, &(0x7f0000e5d000-0x4)=0x1c)
ioctl$sock_SIOCETHTOOL(r4, 0x8946, &(0x7f000055d000)={@common="697036746e6c30000000000000000000", &(0x7f00000e3000-0xa4)=@ethtool_perm_addr={0x20, 0x9c, "8c3249262231fdd9ced47572f6d7b6aa7bea74f1ed3a3175953a1c72ad510c91a2a28289eda21361a6d0e9907781f8d56fd4578dd5ec6d53e8182dc2bf396538212ab748387556d6aa5db7209ea6e0699d382f21f8d4e1b55dfcddcc86d7fd7fd47de3e12fb8d0f90cb292c30e18a8a0d468061034335b00ec14de8306f802f99302eef8bd40732c553a2288b2bad13ea5fbb6afbc6f76a2dde09e4d"}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r5 = openat$selinux_policy(0xffffffffffffff9c, &(0x7f0000d85000-0x10)="2f73656c696e75782f706f6c69637900", 0x0, 0x0)
ioctl$TCSETAF(r5, 0x5404, &(0x7f00000ae000)={0x3f, 0x8, 0x3, 0x7ff, 0x1000000a40e, 0x40400000000, 0x1, 0x6, 0x9, 0x8})
ioctl$EVIOCGMASK(r3, 0x80104592, &(0x7f0000100000)={0x1, 0x5, &(0x7f00001a2000-0x5)="3aa2e388c0"})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x4, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$netrom_NETROM_T2(r4, 0x103, 0x2, &(0x7f000017b000)=0x9, 0x4)
ioctl$sock_SIOCGIFBR(r3, 0x8940, &(0x7f00005c6000-0x18)=@generic={0x401, 0x193ecf28, 0x5})
sendmsg$nfc_llcp(r4, &(0x7f000000e000-0x38)={&(0x7f0000000000)={0x27, 0x0, 0x0, 0x0, 0x0, 0x0, "4ea6f0e32638410f61c3845ad3e81292e2971a49c70755b5820c915be8e3a21e491762022736cd996146b6a2939efe01c9cbf2eb949c94c2855630ea2a71f9", 0x0}, 0x60, &(0x7f0000005000)=[], 0x0, &(0x7f0000007000)={0x18, 0x29, 0x37, "d6"}, 0x18, 0x0}, 0x0)
connect$ax25(r4, &(0x7f0000b33000)={0x3, {"13662e2f5ac7a3"}, 0x7}, 0x10)
2017/12/15 11:53:25 executing program 3:
mmap(&(0x7f0000000000/0x2eb000)=nil, 0x2eb000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r0, &(0x7f0000298000)={0x26, "6861736800000000000000000000", 0x0, 0x0, "736861332d3232342d67656e65726963000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
write(r0, &(0x7f0000145000-0xdc)="f76acc3a33f77e9e23c9cba442a10a483df474866909034685f874b089142ca4a35c2f837f63452daca2754ce30809eddb2b1181648e7e31e0b1974668d43863db9eb65ec69e95a06757a663667fcbb3966ca515351ab764d657559d62e30ba90ed6df5e333dc07e23ba506e7aa49a703bc718343570af877723799d7304f6be30311999ad42bd91d74b5a21a4702897b7ecd74c126e4582c684f826539bfe7eead0766f5d4da8bcba9bf461a8c21c64f949b70bf5c499f2b6d7d23add4ffeb38e30f48d6e6a0bdc02d9f8cfd696f396dcc1666b0bf9f57e707cbce9", 0xdc)
write(r0, &(0x7f000004d000-0xa9)="d25071d23caec1a1d372b5f3ef5315073570a3a66af08caca4df656346326ec816b7e7299f251a25da7956ae60675e77d572a8abf52b47fad81f4443dae17ee16c94db26ade494b26ca807119066cdc4165a9ecc57d983c727927e4ad4a4ba695996e320cbce544bac365a1d4b6cb2ac13a9a35382eab1a757b2c06904ebd0533f7ce793b63a8d0527f7738afbd400511f49d426ef35747dccdcb1f5383327b97f6218c92b38440a06", 0xa9)
write(r0, &(0x7f00002e9000-0x43)="2abdd2c71d95b69d768dfc1aece92d04346639fcf244b8f76ca2d29424b64b87761988937872bac0806064612f22cd5988aa08b10dcaa2731d06965b7d72888bd24a03", 0x43)
r1 = accept$alg(r0, 0x0, 0x0)
setsockopt$ALG_SET_KEY(r0, 0x117, 0x1, &(0x7f0000001000)="a23364fd5e580ef24d71a19dd93fc727", 0x10)
sendmsg$alg(r1, &(0x7f00002e9000)={0x0, 0x0, &(0x7f00002e9000)=[{&(0x7f00002e9000)="4f187fe633e40f292bd3eea91c8b314af2d147b2e74014e48394707a4bb28f", 0x1f}, {&(0x7f00001cc000)="0be333c593a3fe307d465f5c0262c48ef9ed1a706f460c91b812ddca271ea33200ff350636c10058d94f119eddbf40d29f36915baf45444f4e1cf58763475645e67e35a76496657d92d3bfdb2d2537029b3df06e758cc49348e5dfd2d182b2106b33027ceedb2b25cdefca4bbfc465468b46d3f7b0256f0fe55ef28b9581b2d325d01718496c781577db9dbe55b4f0a1872f0c5d853137a0cb63497e319074af6f0067f6fc6739a89c43579205c2dc7c30cb39b46e66542f64231aca7196025835c0df68c1d9ab61acbe23fb14bdf69dd6f043659e450634847d93a23dcca3ca65c2a06573062e36d547aa4f998f8bdf971b6955beb0a2f7", 0xf8}, {&(0x7f00002ea000-0x27)="082202604b9483d2765bdfca9bf023b8efae43cf58f6a10b16698229a49afa5b804d9404694b68", 0x27}, {&(0x7f00001a1000)="1abba0e68c17ecea0bf5f9a02877d82b132d619d914d70c72da5fb678c481d471df38c7afa2317ab528a2f9de306e13a7cb71b0960a1b29580daec77cd554caad73e7c057a5502813e70b13d8faf9edbc0de1e61c6f9d6ea31b1c4835cca4f7448a425fa5e9869ba4f703c326e47f26b263b041ccd8a624a332437a4800956e40f3e2bfc12", 0x85}, {&(0x7f000006e000-0xae)="4b8aaed3e2afaed4be5fcad9361bfd231238358de7adaef7bf84daf0993b568caebc0c85e2bbca098fadc1d19f4029722d16459cb8f4ee827f73900c20b1f978daf2782e26aa5f427f50eaafd5b4bd0b9ec93c7d7ea85d7fc3b6e087851b2977ccc7dc7cb69c45e4f982e92089511a3fd7d0e84549b4e8d6be8f4e07b1022d1bd37394b0dad83019dbeffe0bfe1fcf1b1e24731721f4b64578536fd800570742897ffcfcc269faad4a82d2f22ffb", 0xae}], 0x5, 0x0, 0x0, 0x4000}, 0x20008001)
mmap(&(0x7f00002eb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00002eb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00002eb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f00002eb000)={0x0, <r2=>0x0})
mmap(&(0x7f00002eb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$SO_PEERCRED(r2, 0x1, 0x11, &(0x7f00002eb000)={0x0, 0x0, 0x0}, 0xc)
write$eventfd(r2, &(0x7f00002ea000)=0x9, 0x8)
r3 = eventfd(0x200)
splice(r2, 0x1, r3, 0x0, 0x4000bf, 0x6)
2017/12/15 11:53:25 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket(0xa, 0x1, 0x0)
listen(r0, 0x0)
r1 = accept$inet(r0, &(0x7f0000a94000)={0x0, 0x0, @local={0x0, 0x0, 0x0, 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f000087b000)=0x10)
clock_gettime(0x0, &(0x7f0000d11000)={<r2=>0x0, <r3=>0x0})
getsockopt$inet_sctp_SCTP_SOCKOPT_PEELOFF(r1, 0x84, 0x66, &(0x7f000048a000-0x8)={<r4=>0x0, 0x20}, &(0x7f0000cc9000)=0x8)
getsockopt$inet_sctp6_SCTP_GET_LOCAL_ADDRS(r0, 0x84, 0x6d, &(0x7f00009f8000-0x39)={r4, 0x31, "d7319d71cd8e23c462cb4e9b3cea003108ec54bcfceba8555a60130af8c3c5b414c54c8c2a7b6983f1152c006ec7b70b73"}, &(0x7f00004a2000)=0x39)
r5 = dup(r0)
pselect6(0x40, &(0x7f0000131000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000154000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x7fff, 0xfffffffffffffffb, 0x3}, &(0x7f0000b91000-0x40)={0x0, 0x0, 0x3, 0x0, 0x72ca, 0x2, 0x7e, 0x0}, &(0x7f0000e1f000-0x10)={r2, r3+10000000}, &(0x7f0000a84000-0x10)={&(0x7f0000dcf000-0x8)={0x0}, 0x8})
clock_gettime(0x10800000000007, &(0x7f0000958000)={<r6=>0x0, <r7=>0x0})
setsockopt$sock_timeval(r0, 0x1, 0x14, &(0x7f0000455000-0x10)={r6, r7/1000+10000}, 0x10)
r8 = syz_open_dev$random(&(0x7f0000a84000-0xc)="2f6465762f72616e646f6d00", 0x0, 0x400020e000)
r9 = gettid()
socketpair$unix(0x1, 0x80010000000001, 0x0, &(0x7f0000f52000)={<r10=>0xffffffffffffffff, <r11=>0xffffffffffffffff})
ppoll(&(0x7f0000b79000-0x18)=[{r8, 0x1000, 0x0}, {r0, 0x8000, 0x0}, {r0, 0x20, 0x0}], 0x3, &(0x7f000071c000)={0x77359400, 0x0}, &(0x7f0000676000-0x8)={0x3ff}, 0x8)
ioctl$int_in(r10, 0x5452, &(0x7f0000009000-0x8)=0x3f)
getsockopt$inet_pktinfo(r0, 0x0, 0x8, &(0x7f0000c62000)={0x0, @local={0x0, 0x0, 0x0, 0x0}, @rand_addr=0x0}, &(0x7f0000933000)=0xc)
accept(r0, &(0x7f00007c6000-0xc)=@nl={0x0, 0x0, 0x0, 0x0}, &(0x7f0000f8d000-0x4)=0xc)
getsockopt$inet_sctp6_SCTP_FRAGMENT_INTERLEAVE(r5, 0x84, 0x12, &(0x7f000004a000)=0x0, &(0x7f0000405000)=0x4)
fcntl$setown(r10, 0x8, r9)
ioctl$SNDRV_SEQ_IOCTL_RUNNING_MODE(r1, 0xc0105303, &(0x7f0000fd9000-0x10)={0x6, 0x7, 0x4bc5, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$inet_sctp6_SCTP_AUTOCLOSE(r5, 0x84, 0x4, &(0x7f0000658000-0x4)=0x3e00000000000000, 0x4)
readv(r8, &(0x7f0000cf8000)=[{&(0x7f0000fb7000-0x64)="00", 0x1}], 0x1)
fcntl$setsig(r10, 0xa, 0x12)
getsockopt$inet_sctp6_SCTP_DISABLE_FRAGMENTS(r8, 0x84, 0x8, &(0x7f0000a10000)=0x0, &(0x7f0000649000-0x4)=0x4)
readv(r11, &(0x7f0000fa4000)=[{&(0x7f0000fa5000-0x8e)="00", 0x1}], 0x1)
dup2(r11, r11)
socketpair$inet6_sctp(0xa, 0x20000000005, 0x84, &(0x7f0000b28000-0x8)={0x0, 0x0})
tkill(r9, 0x16)
clock_gettime(0x0, &(0x7f0000230000)={0x0, 0x0})
2017/12/15 11:53:25 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$inet6(0xa, 0x5, 0x0)
socket$nfc_llcp(0x27, 0x0, 0x1)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
pipe2(&(0x7f0000466000-0x8)={<r0=>0xffffffffffffffff, 0xffffffffffffffff}, 0x0)
setsockopt$inet6_IPV6_FLOWLABEL_MGR(r0, 0x29, 0x20, &(0x7f00007f2000)={@remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x3, 0x0, 0x1, 0x8, 0x1f, 0x1f, 0xffff}, 0x20)
getsockopt$inet_sctp6_SCTP_GET_ASSOC_ID_LIST(0xffffffffffffffff, 0x84, 0x1d, &(0x7f0000339000-0x28)={0x5, [0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f000001d000)=0x18)
setsockopt$inet_sctp_SCTP_RECVRCVINFO(r0, 0x84, 0x20, &(0x7f00009b7000-0x4)=0x2, 0x4)
pkey_alloc(0x0, 0x3)
getsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(0xffffffffffffffff, 0x84, 0x13, &(0x7f0000bce000-0x8)={0x0, 0x0}, &(0x7f00001c5000)=0x8)
openat$rfkill(0xffffffffffffff9c, &(0x7f0000e21000)="2f6465762f72666b696c6c00", 0x200000, 0x0)
fchmod(0xffffffffffffffff, 0x102)
socketpair(0x8, 0x0, 0x0, &(0x7f00005da000)={0x0, 0x0})
mbind(&(0x7f0000e75000/0x4000)=nil, 0x4000, 0x0, &(0x7f00007d3000)=0x3, 0xd0c, 0x0)
r1 = syz_open_dev$loop(&(0x7f00003e4000-0x6)="2f6465762f6c6f6f702300", 0x40000000001, 0x4044042)
sendfile(r1, r1, &(0x7f00000de000-0x8)=0x0, 0xfffffffd)
fcntl$getownex(0xffffffffffffff9c, 0x10, &(0x7f00000a7000)={0x0, 0x0})
2017/12/15 11:53:25 executing program 1:
mmap(&(0x7f0000000000/0xfbf000)=nil, 0xfbf000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x5, 0x6)
recvfrom$inet6(r0, &(0x7f0000fbf000-0x93)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb9, 0x0, 0x0, 0x0)
bind$inet6(r0, &(0x7f00008a8000)={0xa, 0x3, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
r1 = socket$inet6(0xa, 0x8000000000000802, 0x88)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_kcm_SIOCKCMCLONE(0xffffffffffffffff, 0x89e2, &(0x7f0000fc1000-0x4)={<r2=>r1})
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_SOCKOPT_CONNECTX3(0xffffffffffffffff, 0x84, 0x6f, &(0x7f0000fbf000)={<r3=>0x0, 0x8, &(0x7f0000964000-0xc8)=[@in={0x2, 0x2, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x0, 0x100000000, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0xffffffffffff0000}, @in={0x2, 0x3, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x400, @loopback={0x0, 0x1}, 0x401}, @in6={0xa, 0x2, 0x8000, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0xe1}, @in={0x2, 0x2, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0x6, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7ffffffc}, @in6={0xa, 0x1, 0x7, @loopback={0x0, 0x1}, 0x1f}]}, &(0x7f0000fc0000-0x4)=0x10)
mmap(&(0x7f0000fc0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_ASSOCINFO(r2, 0x84, 0x1, &(0x7f0000540000)={<r4=>r3, 0xc26a, 0x1, 0x2, 0x20, 0x7}, &(0x7f0000fc1000-0x4)=0x14)
getsockopt$inet_sctp6_SCTP_ENABLE_STREAM_RESET(r0, 0x84, 0x76, &(0x7f0000b96000-0x8)={<r5=>0x0, 0x101}, &(0x7f0000bff000-0x4)=0x8)
mmap(&(0x7f0000fc1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_GET_ASSOC_ID_LIST(r2, 0x84, 0x1d, &(0x7f0000fc3000-0x18)={0x5, [<r6=>0x0, 0x0, 0x0, <r7=>0x0, 0x0]}, &(0x7f0000fc1000)=0x18)
getsockopt$inet_sctp6_SCTP_GET_LOCAL_ADDRS(r0, 0x84, 0x6d, &(0x7f00003dd000-0x36)={<r8=>0x0, 0x2e, "0c1a2be711b68274713c5a8578f689efce37ae2ff88b61fdc83afedef53e5d7e9c078c7ff44d983aaeaffbaf9175"}, &(0x7f00006a0000-0x4)=0x36)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_PR_SUPPORTED(r1, 0x84, 0x71, &(0x7f0000689000-0x8)={<r9=>r7, 0x3}, &(0x7f00009e1000-0x4)=0x8)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_MAX_BURST(0xffffffffffffffff, 0x84, 0x14, &(0x7f00007a4000+0xfd3)=@assoc_value={<r10=>0x0, 0x0}, &(0x7f0000fbf000)=0x8)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmmsg$inet_sctp(r2, &(0x7f0000fc0000-0x70)=[{&(0x7f0000945000-0x1c)=@in6={0xa, 0x0, 0x6, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x3f}, 0x1c, &(0x7f0000ae5000)=[{&(0x7f00000ae000)="b30d756731ccd5b7032679c8aafb552abf5406d9903c1f36e8b8", 0x1a}], 0x1, &(0x7f0000dfb000-0x180)=[@sndinfo={0x20, 0x84, 0x2, {0x3, 0xc, 0x7ff, 0x1, r3}}, @sndrcv={0x30, 0x84, 0x1, {0x3, 0x5, 0x202, 0x10000, 0xffffffffffff461b, 0x63, 0x600, 0x1, r4}}, @sndrcv={0x30, 0x84, 0x1, {0x6afd, 0x3f, 0x2, 0x6, 0x0, 0xffffffffffff2995, 0x1, 0x5, r5}}, @sndinfo={0x20, 0x84, 0x2, {0x8001, 0x3, 0x20080, 0x2, r6}}, @sndinfo={0x20, 0x84, 0x2, {0x0, 0x4, 0x200, 0x5, r8}}, @sndinfo={0x20, 0x84, 0x2, {0xd4, 0xa, 0x200, 0x7, r9}}, @sndrcv={0x30, 0x84, 0x1, {0x40, 0x5, 0x8004, 0x10000, 0x1, 0xacf, 0x100, 0x8, r10}}, @init={0x18, 0x84, 0x0, {0x0, 0xf036, 0xffffffffffffffff, 0x8000}}], 0x8, 0x40000}, {&(0x7f0000fc0000-0x1c)=@in6={0xa, 0x1, 0x1, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x400}, 0x1c, &(0x7f00002e1000)=[{&(0x7f0000fbf000)="ec92f89f22804e635c1c9079c7cf8cd14b407b1351949960c6ca787a0345c08304e423c3f38fa0d48f60c90f35705cdf0201e805c49b46727b984bf1515dc2a8425aaf2ae8c4373e87a1d7f3ad72411166c52d2fac4be139f46c8a6a48217c742be3e2c5870b6c5ac233148b2ed36299f70056c4d553d4a9024d31f7ece4fb257a39f700ff97cfa21173abd8c1428308e3192f31bcb83b62edd520888f35745ca6a878b131b0338957c8207b1d49e3d69a67642947692f43867db29b8a1d988f746287665ef94555193c3bf8ac31a69579ffffea55a5104ed802047ace1bcbf9372ee757bdfac7c5529c552f", 0xec}, {&(0x7f0000eb5000-0x1000)="56037fbf82d65b745c2711bf499b1b751909b742f143a66eb8a58c2400c44a9e6995bb3e453414ed6dd7ce691e854f76de3a6de60b36f8d086a19913afac0a6720f49cebb21a74e91f516180745994a739cef808ebd8797fadc0a3ab98fde1138b1df588f22cb4391af2f33f4eb1e8ca8a529dfa1e11bc82f21a69f69a90062ab0365895aead0e4059ed7df8354803afacd15ae3d7b750cab7cdbc60040610e23631bc6b713bf1541b08fd9aa7f9f1b3016e7b2cf9f6b71a572b329e2596c2f450f440b360e0ace31bcd67f06684fe859f4752708943768fe5ac576e91acb7adc8a2f3e130b92598bb5ccd71d5e9af0494630c86bfed08332a30d0e59d096667aa94d17ec803a0d6d02f735ed73592b00342974cfa2c02bd8d6e4a11ea44adde5ca427806085e18348a1c442030be875902de44e74a2b34fc0dc4963bd6d477cd6be622bd6fd83f44080bb3321e15e4a421a4a9a4e5127e2c6f35d7e2da74455f1def17f4682d8a9518a101e9463e9cea583bd1709408f1055aa6cba0eda83340b0666ee8fb771834d6b956c3c5b130b0fd3fa4c254f829ea022fdb368922706b194d71e7f1e29cb6202be0ebec6af523ce65ba42fa97979f5f2fbaa0ce90b57782f9e2777db2fab86e1967bc0a10aedd732b9c8becc3b6e16305995c3c91ef585f50c28c45eec79dd16a444528cd132e7bfa2f279ff5b370c66358fb459f2931ec394c83ffb4ff5084ab9601b11660c102346022ffc8df89ff0aa90a8bb0c2d18686bdfb62970893b3f0ad42f82d42240e40a8579a5dafabf839a7174aaa161758f183af385f08c51c457177e89677faabd1520259dc3d59196af2a122ff6b54dc2d9cd71a9c5840ad8b2a61a491d5d5ea820e2c2edf0904fdeae11e3de02536361c2034c1e2efde824148a3f5e50616f78ec71258888f825e67f451846c234ffacbeac679a38a1ef01a2710cfc3960d5a99cc2f7f89dd68c06ad560b9fda3a70326f4ed1e4e2946ce831495cf5b495aa1629bc39345d22c6efd8310bc7ccbb2430c86876cd0c945c94288eddc778cac6e0d9e3df1528a3469a77a94b636e0864a32a142e6b53763f0901dc88a50cf30299f08dbef715a7213be9def6dd06b60151d6a6e3dcdfa8c606e01115a640ab746ad9f5222cb9553693ad9b80e6309cc533c53b3e9e3e96578cf56f5a24ae35c48216d727fbb81bbc22aaf421e4f111147c3cde23c674930404f48760a5e0f9f7e50ed4fa746752f354ea9debc8277a0286298168a47038321421b21ccb54928148af37a5ff6deed93187d1f887da271fd2a4c36fa87dc879e01aa0267791054e4a460dfd8f7cff954d80cf1950522b3ec729e345cfa2ef619d2442baf56e80be2d4a788f61f5383fd8a23f24df2abf9c1005b974abb8ab8e5c5c148c1fd2dc8e1f7dedb8f86badb65947912005ce295e9dfe580208e18ba605a83570fab5aaeec0475abea8e449693ab30ec693fd8523a0c16768eea29c89b8b6aa8001cbdde9bb1995731e4bf6d91f9ca4da339cc6a180929d530ea5966cdbd700275119175b67263e3a9ad64afc8c1ba9c84db7cdf8584a56d277f1c1657582c60687f101345a7e6cdab0bf1483af959d426cd2f86263c4c4fd6bfda292fd291920bfea675e0c0ba226439f30bccc85955cbd2cca229982a2bc968cbfb33048065a5f0685e435f3c961337d0e5e290b2cd01c2cdfc72818b8b7c31387d748f49b1937aeb1d35faaecd03560f1cd0fae0721bc48d2e280319697bd5edd5c5363e29e75409a3788822a41fca3dd920da1755a4f54d2884dcce488f09a5baf58cb538e5a65a4d3fb60f650a0df6d91545cb4d54b3525dd5e0e193ea03d51319a8410047a29a79b4c5cfa9cc611698c61e9c2714cbcf00eb2238f6280b2a78a02ae796b53fd63a67a6472b37cb2eb31e384226496597dba867c54a98e101553fe69a44fd440b966e8e5094de81e13fc4f5479a40c3ef2520b016248ba59851a64c0aa43831847633b58e7f0b6c034354099aa00505caf9b24484a4165d9f6bcb13be0b90bf3f04c3970aa9e74b148e25e2569eb4c711a0121131690d5c6821353b06bd2b11624c4d6fd122c1e1506dbc1e5df6340b1b037fde01390416e9305eec1cbd3754fc91a91b7d69504ac380fe4255b6a789c606ddb4cf2d2bec51dbdacaec8ecec55a31dcf5ac97304f02fa82f28e5a4e085a46bfcdea6c6f28f400ab69616aa43ccf35327d79d7a33d97c29d4daa8ef2f39c5b8a006d1a654729fc5e87576e143294b108ba0db88ce2d6800d193cf7e3a7d5c01a5d2667a940758f1da19f41d1941483d02e03afc8ed77950070c2f384c5a635928504ef8f084a7cbb2f9d47b6fea27ae6ca0748093b032a5b7089bdee04ab9c7f6d9acf6964d2d0f0d40c1fc1967b817c16282e418afd682d85a042d71d8eb48978f43218f3517bd65242bf1dc4da675808deec750e94a32a9f1f3d8a4aa7987899bfa7e2ac1a70305db059f4ea810bd43a007562f712a5f8a841d89ff3f71639c34746c21c4606957ea80bb71fd819560a5ad2550cd2446c9d97fe419cb1dcc3688118c868bc7779ccb411c5392590415e8afdb27e45d50b9beb7d3f316ae7484bd6e5ad81036d08db7781e30c9714e3bcb47cd493204ac665dd0c63616b298dc6f28cc2329dcc1cb252229e4de5057619c23065a0199ac4d8fee40523f1ea64b1b1edb39df0914d41710a961f4f5b0b622ed14095a1009b5756a213760f8dad1fc02f4333b3a34533074efdb43f1332b688c28a8817e11932fa4575697213e94160c11f52d02d4eb7daad96e2b3fd42ea0dd2b3fa2326611dec8372fcfa0b176e2d6a821d504aff3533477f1eb0db4e0718cb03e5ef6e79dafdb55fbfe4334058de16c30252edb9b6b3e297cef8caad346d2e81e6aa6be8ec1d5cc2d8cfea2a9773683ecd3e078f734ab30fb3d90f4c949b430a28c67895d7c2f82ce03c956e52878f149bae94c1184912d22bc303f2c5b53730710201af6e822f1ba90374d9a2e9d059366f0b15b2e4abc1bd93381f3a6e22dbc52d10ceab1ca03af89494c36086216969b0c4f436439320c4592457de99652b5b608deef7d073fe327ad96b687c94287a81ff87f2c56ae4a8270837aad85d0219b3b0cc822afaf6c3844970692e320300172582a884dbe989ed5241fce129ae86e7d0ae01ab5f633d18467257d99ceafe76ee560e6593822577d0c52eb636a59547bbbb78f3214c1aab3038d8d6722fd6c6e04285eabf5bcb31505978872f91c06a70736a098af016838233a1768621e35280be3b9b3b21ad4027f30983f866c36058969ea0d50da74c51a8fc3c7dff149906c65621b7d2adfc10cf6ed7fa862731a74d02f0d916c941fcd74a0c875376779770476a493ef3b2697f34853edd2b8adb98ada13638739a66a0a053269b984ca6ed72bcd1d95098e5f34e6e389faf3ebc50efa372c48baba1702ec446e62eb879695689b37095475e861fe5512748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0x1000}, {&(0x7f0000260000+0x9d5)="a9574d2e3ffd8f8ecc28062016465edd787a0e9062a6fcfe6d574c2171054d7d16b152de7131fdfb65bd68ec6eeefbefc540626b554a14df7b45830dd4b87e790483c7b3cb4d635646ff6e609dcd2f64e32d5f2bec8167ec3fe0428510839386735e784065e63ce2609d00188ca056202cdb54b057b4a2fb3a38377a0ec2e0b77b0ba432564b14e7e62873e71b1ed60bbe1df6e3de12d952eead92642be1c0863c3da851a75233cb35205be451dec1743b1d248aff6c6e1b9b521510ce29bbcdce15914ef2547f33a41669ec64417903ded6c8813dcef4771cf772a5f6ce9678", 0xe0}, {&(0x7f0000cce000-0x86)="af1010e6a77898c54ccffd80c3a9f682fa915a3f542a76308c477c81170e3d02389c0f06378ee5e7a025e13c443474ed3efd6bf4c088e6e9cf3dc7588650d1800da180ff1b79e7859ae8358e8e7cd6cb45ec9df0e835ee9b70a17b93e1d14da169b49c801a85ad72ad9afab93379158dc9ded152dba24b6347887a6174338b7f894938544992", 0x86}, {&(0x7f0000fc0000-0xc1)="ada61201374bd9807b17f12bd1bc51cb5a8c88dfa8e854b14629e5a05dbd4055070911eb21d86a1fa2b895a96264901c3fec2009038d4bfb3c7c16a6d311a9f1703af74e030dee9c79fa9aae32f3cc32eca8ad9afbf4ba8b321548cab697ef884a87078aa47d1fe3bb2457baad0c5243a8f4664d9bdd7ce86d561f8af949f30dc9cf1cc16061d9947e9bc21a91ab31b2491b42efbaac8eb6f4cf4ee68e0821bbbb70f987f4376d1b9115f00b87a1e2e717e0f6049a4e80f46f58c8160d79a90507", 0xc1}, {&(0x7f0000fc0000-0xc2)="e178c40f4660f6586e483466dd4a4d4cfee8c382ba3bf049b9341c5092e23331653530496657c9fac83ab6c308e2b5cfffe8983a80c3dd5618dc077031f8d7d56ba959961004b5ba448af2aaa177bea038486e7606b66c3327a6156e6c04252cf52969c4a3ea2324700ba36b5f58eb903807edd21c78d6c2907d9da6d95fe945125c7ecf028a044b520fd7ac1c58ec04267a3dd01bc78a87a424e78ea4e7d2326ec94d13cdc3d55ac945d35e6fedb218653b02913015d8a4f03155814654fb2d42a8", 0xc2}, {&(0x7f0000fc0000-0x1000)="a29b9b60fc9a51e2bc462b73400ffd38b535301eb737de42d0bc5cdfb09d1dfc205613103aa39e9d5e24d25d0b19cfe150231fb50b5812fc0cf377c305d1a612080b25daf1aa0f7855a989f15cd49230f3d832f22ae8d7dca88c531239b347836dcbd1425a52ca7f42389dc41630067cab370d6e2bb146df21c3bf717e234f00a5ae9f2cd8f13f9a57d48723411baaedea49d206c875e6645c91217e5d117757e7c609786310d5b9c2ac0faf173751841edea484b9f82936bde214aa38366301502304b0282662a821995cee6dd36aef1d0cffb5e9ae53a4c684a1912efbec83db53feb1706e4dd027e3b5f233b32a8016b0d04ee44a91c51d3807f3973a937a68c02f1d758a49e246287e24e0d4af6d71930bd5574b9d5fd058c0250eef42f105e821d9cc5232d3fc5bef71277b53b4eca8a19b17c4481cbd42dff7b4c5c6dc3493cb141c59f3f078f461cde290cbf00616d5f4f7b30a7052ea2724b377663e61a5214e351aa3846a5e81236120414fa42986413ce14702ed5ec9b3b421b8a85f924fed65304b9560153218399531c9a9aab6c28c4036017cd0999769a111025c337e39e313c333624454a4389802c1111ce3590a4643071ff8dd58156e004c4d5894678c9badf836a57a4e2afb13b9192d2b75e221fd3814cbf3f2ff71892534a7feaa57616df4dc0ef21898e56820ab82696d1d759479c5514c79951dd74ff121533cae3c3521fe2425da0f1011550be55ed5f6d4748ff5a2a74e276ad9fac0816bb8f1b037a1854a969040d679c99529d0b07eb4246442c6a8033feb51ae7e327b000a05776081f9457027ca9d6bcc65e84d5b7054213321be8faa3e586d8ba176d28f4995c6b77d5d6834b1af1c7392c4d986145c7340c63e31c07e1c61a6b839c0e4db7fa626bfbcd4cc840308cc7e485a46782c5788d8d838e9e0a739d4cf84a76d9cb98baa05c1f66bfcd205db8e26a921baef6cbfb6578d577f1c6f8ce25f3dacd5c5863fbcbcf3891cebac835ac7bf18d37bcebcf616f9727afbb868b85a036621bb550d9bef340ea95f746f07adc7203dc5c985fe8c4f2a0f3d4fe7b5fbcc7df32e5625d40063b0e6a2f52d96a50c34d773f20412cf5d10731162790f9687fc587d962951911422925af607bf3754674554fd2627dcc58c2d5a551d94da401fcb844c48f7b8dcb66a6c675e4e815f4a9bca949989ecdcabbb45052bfb825ed7a5529b4ab2469e6359acc9009776cd1d2ca8651f77a26c5776a2b404956b902bb8e759ce303866ac14320909485350842df73de905b670999360379c989264b43968a54ce9a5bac8b4d0ae4faac37c5a780c0b75d22a756ed13a33aafcdc5bc3c53e5aca40d9b8ae98cfc19813239c1ff4d7b2e5096f711542c44a3fd3482cf06468dbe4ee0e4f8ea343a4631e7be7449c233726a73259d520acbba8ed4090dae370280dd9a2c5e82cd14e6cca0f0512c1fb4d4f022d16d2b133f04ec2fd32a8e1d0a9987f61f959242c2b8fa48578a8fa9192611c449086acb88e9e056a8eb6d439310c193f74aaf44d05d78601f7b5b3444a9d94704efa8db95e88b28b2f9c80bdc9b9be63fcedbc1050eb89d179334b34473ef1016d093d546c4b6c50677d55ce2dafb607e342d04037ddd446e945501d291f77337751fdc2b03b84485e55fc8e78362e76de3b37fe2c9d85e5edd5095b9cc70b794ff920225c4fc67c52c5f03fc488d33a5e261deeaec56fd6627020397f2009729a36cbfa7579d1d308779e9afd71a1de3cf6184a91c8882e8ea41cbcf1b3bc27f83036dd1873e7c6e883fd28ce3de89e9e56a7258749ce96624bca4f30de6567f944059c5d31cc08bbdbd7483a0a0bf6b732bd5eb64b1581160623b08c9fae78d47354dc94e3eaa7eb9a644f9e2e5150523ae52127954bcd8acb7b9dbe2f99696a84e74434bbd2537febe40a6a1e9df821359c83e7f42ebfbf070f73c1dc881c746ffe1e89608111cdd1b1e25d99d006230063345c2c82c1b7acd253f4558b7b94109c255dcbb71566b5c99c6620d853eae2be6421ffbde493f920902701230b219a803c2a2820e3bd9228a4a54e0daadca9a5ea23f4c5949a7f6d555e3b2b3f91d5c8d1f34431ff021b577908b0596f1fae69d404bdcd2258356fdb8403281278cf5650e6295bece2c80dc208db5977efad01e42dc23764216190089ea0685d0c7091dbd084262a5a278a241a71b81d159214c63470546827b0b28a2e44797d0cf9f7079d8a9342727a6fff957aaefe0778b6f940b35fd1ec88be9c764661ab2673e6a1c915d6dca76e3ca4ab97d15e51965536b0fecad86540e631596d4cb4cad2688dd1a9f26067a1d7b90b403e8175989b29ae2ee5fabac76343447add608dd0b8f2d2619611778ce503600d940025885ea2fde4cdafcb19fa133afa91274d779b1dedd48aec8014b7ea49e5651ff8deabd128b4fa991709c770e3974f7bb31afe11368f442d11f04e9b0514430e82621600afc78a1b44523981997fe4d1c11d711a1089062b7854c3e812b27a074eafce83ee6b0f49c2ec23a9891454a97110cf5d33f33e8a2911a0549071dbc784295e3fa13f5a889a7a60094523e45254e08d893f06445de0c54bb0fbcf22b573254488d025b822e78e3660b352a1a62e3e55cf6d287a4854e9b18cd95ee4ff01ce996dea98ab382872be6d8310fecba35633b3677d0786b43d89203b656403e687301fd8e62b09668b516359bab912f5ca75300d98d6d1941e17027195cb309b72f1df881e2e20ddf329a432f976fe840dcd925dd0374c9aaf236432d7f3b25ceafa82111b934af4908778c6d202da8ef7fc3531a9c5c86bc8eb2509b39e737b174e5a3db850fcdae44343f0918fd71f1e8874cc67ddf0d00eee9fa271d3ceb37f82921acd6d992599e5eaea35bd9ba2ceecf8ac0e4fccdcea91c9f796be315216fbf252f987d90a9767fe8fbcb16d9c4dfb5184d23f5ca4f2f368ba9f920301bdb591470d299d9250a1cfb424e29a84ca752ab22c129beaf4513f3c0cc991542f228391a58c9ba9e4f24f2d41bcf07092aa6af111c30660b297d8df3b2e145db71c6724bce62e3666c7b765b5e270fcdd8fcea96c299d83d58be7de08b8c18aabc3b5e46c6ac25a52ba8e48d341f1a38114bbf45efbd68f1997d53c0457c895d9447e9128a99d8d81e17dd27e8cbd85c577cc2b047cfbebcc4992b9045477732a21ab6317a37f90ce0c2f9fe6142b43330a20bcd4c9c789c0e7a4518591b5607dc186589a16a80aca22299a339821464e9d6f66a5baeeaddc832ed04f54b6794da014aca6a766d5a35a74614712724b51283182972799c959326c13d3cb33d0b34dab190eed84afde738de89e70532072d8c51a4d39a2f15638b3812e2c304a534d6496c175d5870e9eda5490b63ba2238d5677d030b5ad493983c00809401acfd24baa4c995d80c1bcddfcc38e82f5ea415c6e6819c6f48117c387876a569540665ff3618e102bba363e3980afe7ffe07a31dd5eb5beac0bdf94ec2cd242c03deffe53a09623494d871ae63bcffb1fc88dacfb98ae5dda16a11de237827244b5e450b2560de3873d30a34c73164941e85b2e4439e9389ea8d07ec46a16af9e3512923eebf5a6bbb3641a9dc78416c32d0f1e5790e6b1572e2f55008de6f50b41d1ae8afaefae7e35554901d22ae3ad7682d2bd726f122fc0c96327ffba8d8a99ac66ead294017d0c9c23fda3aaea5258271a12f7ffbd939e7d15febc6d23d3a205f29288e75e3bd64022e83fc9ceff364bfa72e68d52bf18d8967113c209519d16df50ffa93a4d1448c83f7275a58e1520561de9a93e50742a767c8fc78f40aa7b88699806ac179551cbe86a22ef200b6b198b06fc79047dfa724b0212031722640cd66af95ea39e5a0cd6a91c43d56ba7e10f16a6f6d6e1266756144f2db23c30b168e1c6e4c4a1ce07d2c4a77e50d4838ebcdcf391b812240eab0534a1f5059e3f9baefc438b59361951065cba31b2f007f03ac284c05388a01ef5901aef08aca147002d743239ab01d48d4b6bba830dfdb206f5da7bc8c70f4e55499d0dce22e6e961f1ffe13bef684a3b2bfec094ba683ab49a1dc165b1eda98f580b6813df80b4299f0988b6c7184997ddb37270126b974c76953bbe0511723df5431b9f4af7a01a4d63f51a8c3add83850d5a79cf98777799739380805b9c0aa54659dbc13a650b6e581cc3011215ede3e801186f96d6a23af7024f49d2f9149a6d426d6f02da01db8488a2574e03013db426a479dbdd061fa7a7dd211b15dfea3712a8b6512da97427b892be222be4974417f4989f1a82a8bb66dc65568e3d1b3dbfb63377f04aec1f4cef515d8f5aec348270367c9d506da84f6aed234524481df820b144a7875e0bd1486d6edceef0afe37cb4a739f55e078bd4568e3956ff8f209fd3c053c0e97c17ab6c1482659e8b8668fd661fd39a90a7b2b9b4d361eac933d326f9542f5b55d0267f4eb52da51c39783236109bdbf738b70bc8a62f8ce9f4441f9c6687fbf5ca910807e39c20a2ba9e710869102d7c23be7eb33a97110fa706e0ba6b0b7917802fa37efe46f5f79e80f6d33165c901f69ad900ce8210b78a060b021ebe0175ce43723212c3e39aa38e68e2e968539b9c6139c961c60a8f523d84cadb87416cbbefa5608d8b85784c33ffd43bd6e8c59ce2093bb1f273d7ee937c0237202fbf51b7a74dc0b12d3b492bcfbf7eedc4f19c46629c60a15d0356e67c0de697ae1146a977c4cc62671e889f01c15b4e7e34ecf7afc4832b1ba3ec142e1d8800da23a959db2853e0d54f64a42d909c4751a28f3cba1719b606939124a798151b1725e9decb0aba2f1c1b7b23db163316b41ca858c79e4445489524e51979363d0f0e30e3b9df55f19b476c0241d2a35b6176be92a0565c2d3a2d71dc845b6a5b0f0eb81327c8ef6595d2a3616f1a6e05283b7c311d4d0d57525d0a7d01abfdd16f51b7bdb32398ac3583289c72a24f95533d33d454e56f0707ff39ee8608fc36cb49b5299b164de7d4650922d6fb4274fad5ed3b4a416b33d1de540d6d65e0aa2e05889ef41f2895da75f05e2a53a47217310f9a8aa1625a1e6fa9b82daac059714c94f495669e9e5684a8d0c25a14063e56ee67c58ca4b79979c63ff12f6bcf7636c7ab1adba81a70339784b448a030bb40ff0eaf6a656e1e9406971c1edb88679d92e099497206ea8904c7a145e982c46690d601112e034d143c2d68839e9121866416c7a38c35f52b11d98c536e95459be28672f2365481bce640c295938dd879222aa622bcfbb9c0966e43a42f04ebb7c172c8fa2ada2fc8a5ca5ac34aca5af862fb7fd27bb2748bd53db41146d8c9a708c385595224952ac74839d8294a8b1dcf3cdb378290aac19dabf6f01929b3ef0833dcd5ad5ef77b6ce9dc4106bb8b7a0590b94988602b6f5f4ae19fcaa9ac259f629fc3a1394c657bfb604911a6e7e67481cd9d6445f5c2fe119a171314f50dadcdbef72ca92da9c22d9a9de15573f94694c852172a2fe6acc6132d0553941218d1e6cccd1cf25ec71486eb68cff00df8a65c6f1c92a967c0d6579a0b9f7a04e4f47df9ebd009416f80d587dc98930a0f079bce739621d5b33eeec3d11cc50e7d14da4acfa8d9e14040f7155348b8eef4beafc5d30ba4e56014d05fdce43068b6dc42c0d9c38f4ae53e0659c0462ad4968c7d822a46f6abec81e18edaffe60351299ac418c3479871efb6eb4f56e6f98bc1a3da4aed6c012d081add34", 0x1000}, {&(0x7f0000fbf000)="923865bcbe1b9e2207604b29376c032ffccc3b43309bdddc044b462ff707ab22dec7a0dbbe35ed61f6de7139fa63e25285376fd7bc7402ee9eafde64e41bbbc9663da46b442eb0841a974ddf5dab3649e30bdf000f37cb9828dd11dc2a603591d63486e80983f41a2bf3d734581db0", 0x6f}, {&(0x7f0000127000)="a891e3bdf1672b5d8000ffa78347beca3b02531fee8118f47cec0ef87a5a1c984254b21231dbe98d1bef8272d4933f850d0fe814a56d599348528db997f082653fdc7066f48897460f89b7fda4291533f1a0ab7c7c32abe74482c2484f26b4c6c3", 0x61}], 0x9, 0x0, 0x0, 0x40}], 0x2, 0x880)
sendmsg$inet_sctp(r1, &(0x7f0000558000-0x38)={&(0x7f0000686000-0x10)=@in={0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000793000-0x10)=[], 0x0, 0x0, 0x0, 0x20008090}, 0x8000)
sendto$inet6(r1, &(0x7f0000fbd000)="2748b301b01bc4f59374b6d6c2fb929b131b639b3e410afff7ecce84167f37127d7dd028d28140d091cd641247cbb749498900000000000012347c7d630654cfecd5d1e3190e895d008974a599751d55b83c63fd07303d299bec7b2c16a04275b366ec1588fe054413ee55bd07005b67d14b9237ea42a18cb7daaa9aa9a83371cf00720a00000000000000005175c79e0e4a3f2568cbfac6afde2463b6c4a1cfc7187f8af8b73c47d352a4b9aa415d17b0e63b91367d7a8b72", 0xb9, 0x80, &(0x7f0000fbb000)={0xa, 0x3, 0xfffffffffffffffe, @loopback={0x0, 0x1}, 0x6}, 0x1c)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r11 = accept4(0xffffffffffffffff, &(0x7f0000df2000)=@l2={0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, &(0x7f0000fc3000)=0xe, 0x80800)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r12 = accept4$inet(0xffffffffffffff9c, &(0x7f0000001000-0x10)={0x0, 0x0, @multicast1=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000000000)=0x10, 0x80800)
ioctl$sock_bt_bnep_BNEPCONNADD(r11, 0x400442c8, &(0x7f00007ac000)={r12, 0x7, 0x3, "7ddcc72b99ada1d7657557d2e3a27107b06d9497b8f4219241105bdac93e39da6f580f0d5b3d33af8b504ef987fb40223002cf333d6a1375470ce6ece806960bffee69fe8ec13ec6c05b0dea8d03b8ee841956a991bfcb38ed2274dd39285623b26496f75b1580fd4ec343"})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r13 = socket(0x10, 0x3, 0x0)
getsockopt$inet_mreq(r13, 0x0, 0x24, &(0x7f000052a000)={@loopback=0x0, @loopback=0x0}, &(0x7f00006ac000)=0x8)
ioctl$DRM_IOCTL_PRIME_HANDLE_TO_FD(0xffffffffffffffff, 0xc00c642d, &(0x7f0000a30000-0xc)={0x0, 0x80000, 0xffffffffffffff9c})
socketpair(0x0, 0x4, 0x6, &(0x7f0000b28000-0x8)={0x0, 0x0})
pipe(&(0x7f0000275000)={0x0, <r14=>0x0})
ioctl$DRM_IOCTL_IRQ_BUSID(r14, 0xc0106403, &(0x7f0000e9d000-0x10)={0xdae, 0x6, 0x4, 0x5})
ioctl$sock_SIOCDELDLCI(r13, 0x8981, &(0x7f0000e98000-0x12)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, 0x535e})
getsockopt$ax25_int(r13, 0x101, 0x3, &(0x7f000034b000-0x4)=0x0, &(0x7f000090c000)=0x4)
write(r13, &(0x7f0000f95000-0x26)="260000001e0047f10714c1f83a0022fb07000300030000000000020000002232040027006e35", 0x26)
recvmsg(r13, &(0x7f0000a9b000)={&(0x7f00002fe000)=@alg={0x0, "0000000000000000000000000000", 0x0, 0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58, &(0x7f0000751000-0x10)=[{&(0x7f0000d77000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf}], 0x1, &(0x7f00007bf000)="0000000000000000000000000000000000000000000000000000000000000000", 0x20, 0x7}, 0xff)
getsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX3(r11, 0x84, 0x6f, &(0x7f0000ffd000-0x10)={<r15=>0x0, 0x0, &(0x7f0000937000)=[]}, &(0x7f000007f000)=0x10)
getsockopt$inet_sctp6_SCTP_DELAYED_SACK(r13, 0x84, 0x10, &(0x7f0000bf3000)=@sack_info={r15, 0x1, 0x7ff}, &(0x7f00001e4000-0x4)=0xc)
getsockopt$inet_sctp6_SCTP_SOCKOPT_PEELOFF(r13, 0x84, 0x66, &(0x7f0000f4e000-0x8)={<r16=>0x0, 0x3}, &(0x7f000020a000)=0x8)
getsockopt$inet_sctp_SCTP_DEFAULT_SNDINFO(r13, 0x84, 0x22, &(0x7f0000445000)={0x100000000, 0x4, 0xfffffffffffeffff, 0x3d60, r16}, &(0x7f0000f68000)=0x10)
mmap(&(0x7f0000000000/0x9e4000)=nil, 0x9e4000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009e4000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$PROG_LOAD(0x5, &(0x7f00009da000)={0x1, 0x3, &(0x7f0000862000)=[@generic={0xd885, 0x0, 0x0, 0x8}, @generic={0x25, 0x0, 0x0, 0xfffffffffffffffd}, @generic={0xd39d, 0x0, 0x0, 0x0}], &(0x7f0000981000-0x4)="47504c00", 0x8000000000005, 0x80, &(0x7f00009e5000-0x80)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
mmap(&(0x7f00009e5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:25 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_procfs(0x0, &(0x7f0000125000)="6e65742f7463703600")
readv(r0, &(0x7f0000266000-0x8)=[{&(0x7f0000c3e000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x92}], 0x1)
prctl$intptr(0x17, 0x7)
setsockopt$inet_icmp_ICMP_FILTER(r0, 0x1, 0x1, &(0x7f0000ad2000)={0x0}, 0x4)
inotify_add_watch(r0, &(0x7f0000160000)="2e2f66696c653000", 0x0)
ioctl$DRM_IOCTL_ADD_CTX(r0, 0xc0086420, &(0x7f00001f0000-0x8)={<r1=>0x0, 0x0})
ioctl$DRM_IOCTL_UNLOCK(r0, 0x4008642b, &(0x7f00000b3000)={r1, 0xc})
setsockopt$netlink_NETLINK_BROADCAST_ERROR(r0, 0x10e, 0x4, &(0x7f0000357000-0x4)=0x4, 0x4)
2017/12/15 11:53:25 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000bdf000-0x78)={0x2, 0x78, 0xe2, 0x0, 0x20, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffc, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x968, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x400, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$vcsn(&(0x7f0000b6b000-0xa)="2f6465762f7663732300", 0x2, 0x404)
bpf$OBJ_PIN_PROG(0x6, &(0x7f00000c0000-0xc)={&(0x7f0000909000)="2e2f66696c653000", r0}, 0xc)
socketpair$inet_icmp_raw(0x2, 0x3, 0x1, &(0x7f00009bc000-0x8)={<r1=>0x0, 0x0})
ioctl$sock_SIOCBRDELBR(r1, 0x89a1, &(0x7f0000a90000)=@generic="d04ff3ea79000080007204742104ac1e")
syz_open_dev$sndtimer(&(0x7f000002a000)="2f6465762f736e642f74696d657200", 0x0, 0x4000)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$sndseq(&(0x7f00003d2000)="2f6465762f736e642f73657100", 0x0, 0x20000)
r3 = socket$inet6_sctp(0xa, 0x5, 0x84)
r4 = dup2(r3, r3)
ioctl$KVM_SET_XSAVE(r4, 0x5000aea5, &(0x7f0000856000)={"63a68202d5ca88af8ee14bdd1d30d0edf592ac09bcd6383f6774f8c15d123a6c730ca316d9a4449f004829f29b8a08538309b92aefca45b7baf19d061ffbfebde77daa6e3cc5d4f5929d013e19e0078486721d01f52c26270014791b35c2e7b323c17b17409456cfa73d8b2edac3683cf1f652f2a7c6790a88000234afdd92d3387e5f910c86ee389de41a433fcaeedbd76d0b2956db97856685c4ae289ac56aa1404f5c8753b0ad85b83fdf3e83a168d57e1e5a572bb8dba6c6cc69e9fcabde07ed0c538dc074e70cd73da838855348a36bd210c75d5e35f90d89cd6ad56e7f8b30d70e9b4c0fab7c061399696d77fa62f80eb1bf67b66406a2f899ef8fca18a0c4d93bc800701c609bec5bdaea3637c2c99ea707dc71731fa0f72d06f2d15c706622ed12b9a780ccffb9c3e602b1a455ebe65f00598bd3ed72a3f2a5e89d4a1170730f51f374b8e054773e5b9d6ae1da9382eb6ff39594033e5a55edf0fd3d301367d37aa4aef32640cda0c8ce2b9f85b9ac0bb286a8171a2eb356f97d7152d1947c67c086ca820468348b0add9895ab89d8aeb9b026cec7fe2df0151abb680a4c55622e2f08b806e35b93c444607ca85ab5abef9539858c35d7bfc53fc0f740384550c801a05c0f3240cb086bedc798445d8054a315937905f46d1634f56f757d481ee6db08d82b5cb4e6e0191aef5fe53d4f773a611f6fa54bd3a7f754f5977db46408cb0d5cc3e3bd455eead9aab4d0fd35e6e07f87d70b8e4ec6ed9d6b8108b4279096f58ab85ee9e4cc6315c57d1d557411259e29d83f000000728162ab62dcefe9ecb54f305022f8fcc5d88c407a74f11b8e7d98116ff41bbca13bce875d9557b5f8a124764f1c78a3bdddf2d0dd1c23a9b3e316661e022bb3033a9fac28cf85b0f626a96043214ee102d1f45c8abe6c3205468573a16e5386089a801256f714748da6b96cc93c47d11d9e42da284e4b8e545708cd7ffe9056abf8843e2371f6404665e1c21764b1822e7bb2ed932aec17424e28ceae66f0a99b3f2545f7d5690743dbb27793493338040fccdd80a79ef97e616f5eef0adc81a583bc2faf41c5a228e8e7d7af858a56485f0b73b6d80c90c0a7b3238f4da64209c93998c1238af65ac78b5f15b3c7d31a3640d653187b8400000cc8422c53ba3be3a0f5552cf0c121d01b30eb428a71456de35aba149c569f50bcf129e91188c6de785019b63c0b8caadd33fecbcf05f3d9fd9726059d33276cc3c56d7d226b751a4e59f2ca2fdc5003001520e2e82e64a7908a9388d0df3cca131b0336c6377e4de265cf990f5fa6be27d9ebe0caf0f0ea7513944267080a22aaf7c71f2938ce5acf5541fbc8ef3c477d499b20c65f814b7e3eeb2e247de95d7f0f766e5e2ff4814c476afbea7ce1c45390023a2dce424debae1da58f1a2d11a3b0a5845f4df36c1a"})
setsockopt$inet_sctp_SCTP_SOCKOPT_BINDX_ADD(r0, 0x84, 0x64, &(0x7f00001cf000)=[], 0x0)
setsockopt$inet_sctp6_SCTP_INITMSG(r4, 0x84, 0x2, &(0x7f0000ab8000)={0x8000000001c, 0x4, 0x9, 0x2}, 0x8)
ioctl$PERF_EVENT_IOC_SET_OUTPUT(r4, 0x2405, r0)
getsockopt$inet_sctp_SCTP_INITMSG(r0, 0x84, 0x2, &(0x7f0000e3b000)={0x0, 0x0, 0x0, 0x0}, &(0x7f00003a0000-0x4)=0x8)
accept4$unix(r4, &(0x7f0000802000)=@file={0x0, "00000000000000000000000000"}, &(0x7f0000297000-0x4)=0xf, 0x80800)
ioctl$sock_inet_SIOCSIFADDR(r3, 0x8916, &(0x7f0000106000-0x20)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_flags=0x2000})
getsockopt$inet_sctp6_SCTP_RTOINFO(r3, 0x84, 0x0, &(0x7f0000727000-0x10)={<r5=>0x0, 0x7ff, 0x7, 0x7}, &(0x7f0000cfb000)=0x10)
setsockopt$inet_sctp6_SCTP_SET_PEER_PRIMARY_ADDR(r3, 0x84, 0x5, &(0x7f00001e0000-0x8c)={r5, @in6={{0xa, 0x0, 0x6, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x9}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x8c)
getsockopt$netrom_NETROM_IDLE(r4, 0x103, 0x7, &(0x7f0000074000-0x4)=0xff, &(0x7f0000ebb000-0x4)=0x4)
getsockopt$inet_sctp_SCTP_GET_LOCAL_ADDRS(r4, 0x84, 0x6d, &(0x7f0000aba000+0x6d8)={<r6=>0x0, 0xf7, "27167a9ddd74ace1a62949c7b07b55296fb78814ae7c1bff9be82b68944f6f0c39290cbefb346f3482daf4b46234d10befc86cb16b1e3a57f57e40d2a9c125d58056bd23ada3b730579f6d9147c7144ca3c7474a6d72302db6e4bc6c9ac62ef809a98a01c53e03b59c6dcecbe92b36abaf43e49187c01b84851447aef4b41f1ef5f821637e51b3101fd47cbb2296f6a0d226d0da91c79fd1871f3ba105426b05ffe93830d27b631ddd2ccaa9b2fe7132c6afd053a1b5f0f953fde14b220db9774d51dc7a531f41dbcc4c706e386aa13745be2ee9944fd70f6d9f18f5bb20cce05facebcc4fe5214303256ca6667accbf46816d55cf1737"}, &(0x7f00009f7000-0x4)=0xff)
getsockopt$inet_sctp_SCTP_ADAPTATION_LAYER(r4, 0x84, 0x7, &(0x7f00002b9000-0x4)={0x0}, &(0x7f0000858000+0x27b)=0x4)
getsockopt$inet_sctp6_SCTP_PR_ASSOC_STATUS(r0, 0x84, 0x73, &(0x7f00003cd000-0x18)={r6, 0x0, 0x0, 0x10, 0x6}, &(0x7f0000d35000-0x4)=0x18)
r7 = socket(0xa, 0x802, 0x0)
connect$inet6(r7, &(0x7f0000ce8000-0x1c)={0xa, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
sendmsg$alg(r7, &(0x7f00007fb000-0x38)={0x0, 0x0, &(0x7f0000960000)=[], 0x0, &(0x7f0000d6a000)=[], 0x0, 0x0}, 0x0)
setsockopt$inet_sctp6_SCTP_SOCKOPT_BINDX_ADD(r3, 0x84, 0x64, &(0x7f0000e6e000-0xbc)=[@in6={0xa, 0x0, 0x8515, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x2}, @in={0x2, 0x0, @rand_addr=0x8, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x0, 0x7fff, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x9}, @in={0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x0}, @in={0x2, 0x2, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0x9, @loopback={0x0, 0x1}, 0xd283}, @in6={0xa, 0x1, 0x6, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x1}], 0xbc)
setsockopt$inet6_MRT6_ADD_MFC_PROXY(r2, 0x29, 0xd2, &(0x7f000055b000)={{0xa, 0x3, 0x2, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x8392}, {0xa, 0x3, 0x6, @loopback={0x0, 0x1}, 0x9}, 0x6000, [0xc6c6, 0x0, 0x800, 0x8, 0x2000000000000000, 0x4, 0x6, 0x8000]}, 0x5c)
sendto$inet6(r4, &(0x7f00003f3000-0x3)="026bd2", 0x3, 0x1, &(0x7f0000ab9000)={0xa, 0x3, 0x5, @loopback={0x0, 0x1}, 0x0}, 0x1c)
2017/12/15 11:53:25 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20000, 0x3, 0xf72, 0x0, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0xa5, 0x0, 0x0, 0x1, 0x40000, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x8)
r0 = syz_open_procfs(0x0, &(0x7f0000d2d000)="7569645f6d617000")
r1 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0xc1, 0x0, 0x0, 0x6, 0x0, 0x8000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, r1, 0x1)
io_submit(0x0, 0x0, &(0x7f00001b2000)=[])
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r3 = socket(0x9, 0x1002, 0x3ff)
r4 = socket$inet_tcp(0x2, 0x1, 0x0)
r5 = bpf$PROG_LOAD(0x5, &(0x7f0000105000)={0x1, 0x2, &(0x7f0000415000-0x10)=[@generic={0x8db7, 0x3, 0x0, 0x0}, @map={0x2, 0x0, 0x1, r2}], &(0x7f0000652000)="7569645f6d617000", 0x1, 0x80, &(0x7f0000d9a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
r6 = socket$kcm(0x29, 0x2, 0x0)
ioctl$sock_kcm_SIOCKCMATTACH(r6, 0x89e0, &(0x7f00004e4000)={r3, r5})
getsockopt$inet6_IPV6_XFRM_POLICY(r0, 0x29, 0x23, &(0x7f0000ee6000)={{{@in=@empty=0x0, @in=@broadcast=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r7=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@empty=0x0, 0x0, 0x0}, 0x0, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000fc0000)=0xe8)
getsockopt$sock_cred(0xffffffffffffff9c, 0x1, 0x11, &(0x7f0000e9f000)={0x0, 0x0, <r8=>0x0}, &(0x7f0000b40000)=0xc)
fchown(r0, r7, r8)
r9 = getpid()
ioctl$VT_SETMODE(r0, 0x5602, &(0x7f00002a4000-0x8)={0x1a4, 0x0, 0x0, 0x100000001, 0x7})
setsockopt$inet_tcp_TCP_CONGESTION(r4, 0x6, 0xd, &(0x7f0000062000-0x9)="77657374776f6f6400", 0x9)
add_key(&(0x7f0000cd8000-0x5)="7573657200", &(0x7f0000b74000-0x5)={0x73, 0x79, 0x7a, 0x2, 0x0}, &(0x7f0000cf5000-0x2d)="93cdd1ef3d2ee5e9c2c827371a60209ec8cb2a980b934959fc015da16748446744c33be32b81a8b98695d53c7b", 0x2d, 0xfffffffffffffffc)
r10 = syz_open_procfs(r9, &(0x7f0000a14000-0xe)="6f6f6d5f73636f72655f61646a00")
sendfile(r10, r10, &(0x7f0000014000)=0x0, 0xffff)
2017/12/15 11:53:25 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x553, 0x100000001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1124, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = accept4(0xffffffffffffffff, &(0x7f0000358000)=@l2={0x0, 0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, &(0x7f0000542000)=0xe, 0x80000)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
clock_gettime(0x0, &(0x7f0000fec000)={0x0, 0x0})
futex(&(0x7f0000004000)=0x0, 0x400000085, 0x20000000, &(0x7f0000726000)={0x0, 0x0}, &(0x7f0000004000)=0x9, 0x401ffffffc)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e2, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x6, 0x0, 0x0, 0xf72, 0x7f, 0x0, 0x0, 0x0, 0x81, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xa7, 0xffffffffffffffff, 0x9)
pipe(&(0x7f0000738000-0x8)={<r1=>0x0, <r2=>0x0})
bind$inet6(r1, &(0x7f0000bea000)={0xa, 0x3, 0x800, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x100}, 0x1c)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x0, 0x0, 0x8004, 0x0, 0x0, 0xf72, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
openat$kvm(0xffffffffffffff9c, &(0x7f0000255000)="2f6465762f6b766d00", 0x80, 0x0)
ioctl$KDDELIO(r2, 0x4b35, 0x81)
ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
ioctl$sock_inet6_udp_SIOCINQ(r2, 0x541b, &(0x7f000074a000)=0x0)
r3 = socket$inet6(0xa, 0x8000000020000007, 0x4)
setsockopt$sock_int(r0, 0x1, 0x2a, &(0x7f0000faf000)=0x3ff, 0x4)
setsockopt$inet_tcp_int(r1, 0x6, 0xe, &(0x7f0000709000-0x4)=0x7, 0x4)
bind$inet6(r3, &(0x7f0000b8f000)={0xa, 0x0, 0x7fff, @loopback={0x0, 0x1}, 0x0}, 0x1c)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f00009af000)=<r4=>0x0)
ioctl$KVM_CREATE_DEVICE(0xffffffffffffffff, 0xc00caee0, &(0x7f00008ae000)={0x3, <r5=>0xffffffffffffffff, 0x0})
sched_getaffinity(r4, 0x8, &(0x7f0000a5b000)=0x0)
mkdir(&(0x7f0000f4f000-0x8)="2e2f66696c653000", 0x0)
mount(&(0x7f000071e000)="2e2f66696c653000", &(0x7f000000b000-0x8)="2e2f66696c653000", &(0x7f000000c000)="72616d667300", 0x0, &(0x7f000001c000)="")
mkdir(&(0x7f0000025000-0x10)="2e2f66696c65302f636f6e74726f6c00", 0x0)
mkdir(&(0x7f0000156000-0xe)="2e2f66696c65302f66696c653000", 0x0)
symlink(&(0x7f0000747000)="2e2f66696c65302f636f6e74726f6c00", &(0x7f0000ab9000)="2e2f66696c65302f636f6e74726f6c2f66696c653000")
sendmsg(r5, &(0x7f0000256000-0x38)={0x0, 0x0, &(0x7f0000d42000-0x60)=[{&(0x7f0000f8d000-0x6b)="a78a11b700e80a7ffd7f2cf0a3ea78e2016eb0b4339a059196d8988665e4d721ad08e697db52f2122d99f88430b9a718392303bf98c399c266ae9400930de8a90a1cb2fd1f5eb22ecb88ea21b15ba3e85d0f216011e7f859e238a8e7242375c36ded438ee42b02803bf3c9", 0x6b}, {&(0x7f0000fcb000-0x2a)="150a2f0202d2c5a015bda5d1ee7731b694f5312e3c63a7eef122977ae43f91911f92f82124d4c88ac7ee", 0x2a}, {&(0x7f00007b6000-0x78)="d2123f9f96b0f8c112a70d623e92dcb52c123b0d073efb17a6e863b4da01729041dfb58d459c12a255f53c6a20af1f477e938361faf687cec106a45b76e6455bd34fd183dde9c95af97b7066b5683483cf51b229ded67c6b41665554cf85dbf97a8f779284a626b834bf91a87510c1f512873035ea53bdbd", 0x78}, {&(0x7f0000d53000-0xfd)="dbb5a902489d6f1bcbf0f32c6d7fce8a0873f073d3562e0400366b5952098b0cb7e1857c6cbd1e292ebe3f298f1769c28398844bd96ce0a7dbbe2bc91d116829eef9fce5ead80e0d2e6a9d6c824383e4f2156de422138fcffbad7ca0996f8f0abda947bebde143aa458b92efb03c4fa615b03b6092f9f86b99eab9b808c8546c524dea4553a62f8468a28474f22f0a8527802bcf13e979132a9192ae8a4f1c9afa63ebaccb9dfbe8f040271308a54fcf607a8d2c63646f8ffa016a4149c2a300b5773f5ec68d4cd244f97d95be6d114a870f3c949232102460d935c008f018c74642c77c97f5b753cb272253eb1a32639389d1f7dc7a6a3e6c6b1cac40", 0xfd}, {&(0x7f00000dd000)="308542a48945e5e96a739ce177c9e625f5f296b2e0b84bdf248223809f7343af4531429f8c4e00a35803c3665a1afafc28aeae088c371c688674a857d4690ea93b4cc1775fa55aeb1b6d07894a2a5ca9b01984de9fa4070223d2661aa491fbfc05c07506a1fc95a501d05216a843e1ad0657807a0611f4209283be24f8b132623880f0ab273621d5da69636c3cc9626e4b563b9f8967a14a6b9916a5cdf214c4b9b33eecfa4e", 0xa6}, {&(0x7f0000822000-0x84)="6844c4106d1baecd6fc18906fecce5f61c8085f46fbf5ba0c8177eeb2302bc2d023492d50a377feb62155c0ce8d99d31eab1c25a227c3328e308e6738043234682f57d725403899f33b26a720f8608c61ba5f4d468878521167de0c16159176160b4e93de92a917f382b5806ec8ec5e98227d29d35f778cf7f7c3bb2c6508b378cb42242", 0x84}], 0x6, &(0x7f0000816000-0x588)=[{0xd0, 0x101, 0x6, "33542e456bdbfa2feab818ca7c95da713615341d7a29af7148056400d45ef24e889fa990973370a2a1f12318826fcf5bee7a06d868eef80b5b5ece8ac95e19c475aaa8c4511dafaaec81a891367e3ca4609886e562ebf2ecd28c5a36c64758246548cef3040dcdaf1dfa98e360f9e7cd430de7a7cbbef38d948e26ee0bce2bfcf278b44d1bf6ae09349d3230c05502b8540b610137a32cca109954817c1b5eddaf70cbb8e180db08a8b61132ee293566ad3b0d9a78220b923fe07d"}, {0x108, 0x118, 0x9, "9185182b58957c1f8201cbebf4b1107f4b03aa1bba61162b289cb0b7de527d25d69baafcd7330a370f31c72989f4e0557073ce40a3fed2f7e9bf2c572562e4431be45213df37dccb248c66ed2671c09a62181cabc48c776e70ad1b1c15c05a1a06e49c4b53c0cf4b26c95188006957f470bcb59323406566c8c8a012fb7bc9067bc1f2bc71b679c886f20dc7cc02e1c52dd7925802c1ebb63a71cafd1cbf3de0d07e58fa751cb7b6df7661dd0205ecd5f528df34c9c28c93df65b95dd3e40a7c4dcc8f45a43dd2079b1225ac77f88aa86dad796c2d2c4f6493f8d5f2647b4283d6120d8f374d63b7f0c872997d38d76c034c"}, {0x68, 0x10e, 0x88, "a78a2cf496278ffb84a48ec684cded0f47112bf05e6a0f48d91b708f425d6bb30c30fca34dbfd71eeff4ec365f1c9b1af3ae890eaf39dce689f665598b65f00d92da53d6b49614c3987b444bed49cc8bd7cd57"}, {0x48, 0x109, 0x5, "ab118804a45281fbbb307e0c7875b5579b3e9a554119610695aa86ce7a926c801d4220087ca40abac047ed20d762a7fb2a36b02b"}, {0x20, 0x0, 0xfff, "53faae401cfa474da127067c101a"}, {0xf0, 0x3a, 0x4, "b80a80efa1ffda1d8b15d2c4ea7cab95840866ca8025edda0e03afc0a8d7d9bd726b46d7eaa472c79b66b5d69b5620bddbc61d5865eed6be85e3cf9d368aea61a46ec9fedf1b918329ff48ecd7e24b2cdc79d0fc37eb46580920de7520813a4f55eae824bc1e2272b05df180bf65c4942c219e679eac7a09dbc691fbb177150d68a0cf18cf7173707108943dcb0be5ac8f0ae9b8e192f8bce48f8ef2132b1a2c5275e147d5f541f1e4626a8dcf54afca5fdc6bcc45aeaba4aeb30097063915239d84a5d7eadf23a49d5107521decd367f0fdb19182b9d8b2a19e4747cc"}, {0x28, 0x1ff, 0xc2, "0f5a8f3dc0884efce17f2e9ab9e7d4b2dc94a9"}, {0x110, 0x116, 0x267, "c16e6be49da7cb4361ce254355665ac453d4a00541bdf9edc18a53a3d7a3c1bb24a1e039345e0249a11e3b4d8d737da39d38e5eab258755a27d98df8f7adcdb9f6c8cb3222c7c474fcd24863a06026eeddce2022045904c6f978d9386fd93b49058bb79d21792ec8f9f02a0ec3839ef8b7ef6d02da9a0b95cbfbdf9dd49c845f2cb998e47aad5e4f1cd42a61397a2dba04e351afdc25da66573c1eb38c6c0245bbb64721e99c71425999d0b76830589d1666dbbabd477a141ec91c34f1106c4a126a12c6eb447df5dad410dafd6da26d119b5c75a0378e770cb03e0b2d0437545eef3ca7c9139ec58368361a39b0f40c34e067ad302ad9b7d4"}, {0xa0, 0x10f, 0x9, "64963cdf437e3de0975302873adbd07279482d99bef43ba66098876241f7df5bc688ab1ac523324fcd0d54ecd298fa4daea32307fdaa2c8e473cb3999ee4858611b9d58575b340d90ddaafe10ad380d6b21269c34e195e5d35644aa39a72532888ceda2ab3d487dde72f821323c2fe23e3f964d33bc08b90c39a1ff41874cb341f3300f96b8a81c26d71d20e4a8d5e07"}, {0x18, 0x11b, 0x10000, "30bfcb7fd8"}], 0xa, 0x4000000}, 0x1)
rename(&(0x7f0000b95000)="2e2f66696c65302f66696c653000", &(0x7f000044c000)="2e2f66696c65302f636f6e74726f6c00")
2017/12/15 11:53:25 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = accept4(0xffffffffffffff9c, &(0x7f0000001000-0x10)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f000046f000)=0x10, 0x80000)
getsockopt$inet_sctp_SCTP_PEER_ADDR_PARAMS(r0, 0x84, 0x9, &(0x7f0000f56000)={<r1=>0x0, @in={{0x2, 0x2, @rand_addr=0x20, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x8001, 0x6, 0x5, 0x5, 0x2}, &(0x7f0000822000)=0xa0)
getsockopt$inet_sctp6_SCTP_DEFAULT_SNDINFO(r0, 0x84, 0x22, &(0x7f00004dd000-0x10)={0x7f, 0x200, 0x7, 0x0, r1}, &(0x7f0000767000)=0x10)
setsockopt$bt_l2cap_L2CAP_LM(r0, 0x6, 0x3, &(0x7f0000000000)=0xd, 0x4)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
writev(r0, &(0x7f00001f1000)=[{&(0x7f0000f39000)="29000000180031fbffff0000006500070a000066036dff06b102ffe10c000800040000000007070b37", 0x29}], 0x1)
socket$bt_bnep(0x1f, 0x3, 0x4)
r2 = socket(0x1e, 0x2, 0x0)
socket$unix(0x1, 0x2, 0x0)
getsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(r2, 0x84, 0x13, &(0x7f0000d34000)={<r3=>0x0, 0x9}, &(0x7f000039e000-0x4)=0x8)
getsockopt$inet_sctp6_SCTP_LOCAL_AUTH_CHUNKS(r2, 0x84, 0x1b, &(0x7f000048b000)={r3, 0x1000, "3bfff3e8b2dcf78235b321387925595324d5662856bba66fdad084c0106a749e6056d1dbb31c7bde883f9896416d8a076a434c2b42472b72b5e3465c4583fb60e7203a82bb5cc8d95cf1ee3d76ce070681a793dc04dd6ad85a2cf1db9aaf96caab43be7ea437f83b9f7bd19958fdbf5776ec268e5e67d38edeab47c4cd6c68998112474553897dcfcae5b58a92bd163f3b64ffaa35687c985fd74deb73b0a115daf160043d0dffcd5ab2f2d9f3a562b6c02b6d8f31e4c9f2557a42a6469796500b692ddbd91a5f06ea19652f9cde05979a140125a9a47ea1c20f71b0efe3039f70918e1bc05f254665e3a024cffc132bc9cbb2272b49c624d278f8b73a14d8ea0ab87ed6d8dc5211c78a77d2df165a1dd8fc1a56be30cf8c932b6bc05a2c5f25ae601d9376f5164b0109e78b264133c7bc048bc25fdb9036128389a016fa7b72080f9af915d7254934555bd5e23ca175eefe4fa54d41287752e01c81850652933c3be5656851784cdfa259c37e3dd1643abb2a6bbf31ebb1f1d28c61a6a89ae3b37b410f4693204cc7242eed846cae42f92b90f59571f7bea5952f9dbf018f50272f195ccbabdde894c11f68c4c15a776aeb6c6e44cfa7f8c37f330731ec7352dca737f99e8caaa082bd2ab731fc311e327a905fbdc6024f2562e7b405ccb1e3eeb60bc298b653076575e6be3922f8b33a46aad88b74444d16e2f2d8a91d8a6af7fd181f962efc101ef0683a260e44971a982c82290b2bd64ca702400bdf6ec9eac940cae207ff6740d9e2f51771da0a468c1eac9c7dcfa18bccedb0870324dbb1dcd8298a929d8955e03cf725f2cef2502f02a3d9196844d481fa0c4ee7f3dd75e1e7018244c45d2b731995a7de5a7669a3633b200ec0521d63636a2df3dc31ba0c97dd883a1074f18969cece31b00426ffa684567105d52f0e8173717fcd956233ae4b525d4a53af94d3a56bc70811f8ba0c1d3a35843814869dba175b8b05bb296910a63c0b467495198b05f143ea3f03359560721a894cca81f8239996b33079bfe3e93a96cc35daed79711c0ced48ed60402b154fb3dfb3605a6eda38d2a49a4ae7e58a419e0009bce57d0bd34a95658d4a046021528a6097aed1bc5f4f014873069d891215f0b1d69e1f117608ddeceeea6e61a8c276b289d1d91b114a9cd4a8de0cc2c434852bf1bdac9a2feda66404047351b770014e97770cfedcd9aace06db802c2a30cf4b54da23a904ccda8f38a53251d15889963373c2070408d78636d9313759c25c05ee89ac60ba983645cff6b9197122f77b2980c849a3b814c0f8bc5b7bbb3a2b8be363b012f4bb93b1d9fb8d7ad49c34cc1658acbe5b454cdd20746eb28263da6e491cf7e8bfc5c1e595284292eefc1901f6c0349fd4f76680127c2981bee2ad7ab70565d1db8fdec06f5455e0f93c626578ad7b016c331c61492cec09fee474fe1b241bc852a3be10098eb78d83051e3310eed1f15eb0f1cd5e2bd7af00a30fb518c8ab03da91c992a730cc9fd93778d765db6bd0f464bee8ae87a0c2680d375d70c3f3d1ce4b9046ac3352500fda1777049ada360526ebbf849a336f61d5606a88bd855096f672d75030e7ab0276d7d18c60b99172ef951a591bac31b812316b8c4be59c114a94f533d35700d9e48e49b5758dd03c6c750f6f5a8956a2c70234734f72973cf4e81764d2d5c4c08fbb2597324ba3f06a9d7ab35b4051d8ff0f4d62bd370635c4e8b01840822f04a0c73dd9770fd31a7ad258c31d635206df8683cfc5f2e4a4fbf70d0469ee2e57eef12eee298432673dc38d0cc1b19f34a8d0350be374831265ee297e83627141136a12b93280a6ce0dcc2721b0cac2d4f79a38bf15df15dc9db42763bf9df2384c6e91ad3b6141b60b0b8876906b636c0e126550d7f777be3d511f29da9def7547c097b7df9e2ca472e5db2e92bd94ef10e3d35c81a5ae819b8b780988fb54c2ec36f718597ae49f983fe5ddeeb9f9c1f228ae70ab71309a50db8404c87d55f42fc4bb3c6566f6e7ae1e3cd33f951b355e107f066210bcbee2d07913e2ab41c7a4159aab7f4e4f70e7c2eef2e4fe00f590db1000bbdb506fcaf9d520e5ad12aa619643c124c43b0f0c4b1e894a78dbf160a5b5c785d8ca6c50c0a14f7c36d475fe5bb003970e959db8bcefc960e5aa688379d5929f3c79edfaef9c88993b863b6875e68db8a2d0c95e420e9dec35e4d41b81b42eb01b406c8ff362506342b9bfeef890f9f3b5b40c421dc7a48c415cd4e5c72696130c3cd195cb7adccb71649fce748a12ccd864abdb9f9b4c16e39bd3ea46dcbcd2a7f0d06283ef6ae61f40990d43f4c12e73035f7368eaa4e038fbf8d1a14ec0c35d5576682ae616aa8d923139c98d8adb7c669459398a0ba58be5632c8c357e3037344178f5cb6f268fa5f64cd6141ae19915e2a9a2541446520c16270e9d5831cfe546e3be131ed98f0177cd616770b94c4e4005e553f1cd176624dbcd228ea6c1d685a3017ff1e14a51c080aa5b2b54551436e15f2ffcd8d3d99b7832ce00762e4b8a85cf20c29f24a63a24a81107de432ce38a75a3f8c9eb13854bb6d7a3c5bed795b10e5b4f1f1c3a849c595b2b3d8335bb3ee7b67fb4b649984571c755ebd859b00350213092bb994ac614b64f1b45747a9422d83b8e6aa50d6f047f6e8750eac999041d1eae8724af3efcff0e3d7876fe9c8aa4a034a9f3373345030aa1434fa1139bccaa41d2704866624f8a2105136081f1a077810dfaa1449f1a6581523aa3e6786264a994002d23c443141c5ddba72753245d2dba7fb5da203296c0901ab06e21abdd109a14f84d1f26f7d2166f7d85c89c01d8d351f49f7bd212e1e9e79e1c89ea1c6e220b95e9960a88f59da884a4e0d5be87fd80b0d000b1bd3b1013f7065b7212a7199a7db112de4e4ec59f324c74c204c19f1a361535a9cce32fb3f7dd609688a5db95751b8f77fc6800cde3e1cf98a5c7fb0d9b2a5120e00407f0857be03633b6892b47f4f6755e648176116cf31a82163d241cc49ba7568b94326e6a31aa727614a60e82559237105719490ba8a10a54925c4031f22aaf2a7de406f2ffdb07e3ee68e12fc43ff7c0555092beda3f58eb9ea756108cf962965ed6a82cfbce6ce8e5adc915cfb2e73de6fd154282c579474468ea73008016bc0d2d3e2a17bd0a7d6e538cf9cfe26009c4ef8d1959c58c150b93e69a9cdfea54278cd8a86bdf478f6b058abe2d05ad8e477e40d7a6958fa7548537221e143abf29de207a7050fb4e2cf4cd86e51a935651f3bd995b70b964b330c28b4f6b101d330b82f060939c94c217e7987ca56218316fb8dc315264a00cff71423e1e1ebd3e8671e460c179ef19bb8d46857d7536183dd2e4abdc0f068f25a47ac3f6eb8db00bfbe18db6b9a6bc7749c5d5a28599b778bde40d2a735d8a99f2c459f957f6e8ecca5866f8c0268f17f8998c1e67335f3823eea97e8fbd2c87ae53f71a2acf190654e2e00bd21385e96d6bc6db14a70bd86bca04375cd68ef31ccd953e3a3728af971960a073006cf3a6e6730fbe8f320ccac8ceb7f2b370a587d2fcd983a459650229e503075f8554f948e92601f067880ec949e360558a0c492ad8928700c8eb65b93a0b3f24a881a9fb653331979bd106749ece7db5cee2ceedb87bda23710262de4538805479ac7ee1b2463e278db1904b8d616c6fe5b7b7626a8e874cffd08b42c74dc087aba1e9074cc613bb65c32b52ba1f487770c98c8df742b9854a0f442d57bd8329a10cd6b7591145b12de25770a3927859c0f38c7e6ea186b54cae561d7b96d04ef3ffb5813c566157c4cbce9af10cbfbc342b414aba6c226e24e4b40325dc3519e9747ba4c8567fab452b7348fd62210f38a1ad08121c67a9da79439d7577ad707d9c757260cd4f915071bb40bb6bf5055cac24991023393c7339fec9a3d59ae01b52d54c11f499d9f5eb23dd683eeea507dc6485424cbd5fc710b40a97b5cc4602532218dcbfd06dfede2ee77eb352838d92f5aa7c7cef3ec4d9fb1d32a94beb095adb9dcf19859e12fe1bbba4d24d8ce75f461ac19d9b66b36559fc2ad4f1d7747075e468181dcecb40a832d857f5150de3c3081c87863d9a863d9ba2b56e756b3d4f72a88b990b7907a99f9e1022375963982522692f79bcafd2b8043f263a71a88b0823d1bab724058b876fdf37dc4e6442f49f5a13a0de36b02e5c6afcd877c171c7c72fa33bacf6c95fe034e3c43e8def3e9bb4e32fb6410c00feb609de87816782ab98b61e22975e51c7e9d4380a6f61cf6cb7c4377e1bca22387c92851d5446b1b8785798759727a7483393c767caa5cd663bc4b3df49ce04e83b51738e74472b6156f4c83733dab941f48c5a3a1f21b85616f7f81c95f88f88f1b4bf77347969b93b0b224a8fa2c9d5255cbc91912dd87753bede03152700beac31d3e1e0a83040c28d03eec22ea3df8b297be4bd9a4d77ef18e6ba30f9e33d177c9d97b7df293b4d1f220ea0fbdc69206b3c573a2b08ed82ae0a0ddbe6eed71f649ce3d8454a6c6090bc2a4dfb601a70af0cf2280af697aa1dba88b04853d53066e27e376c8fbab315796309886a4da4e26ca1044f690a81b5ed4af024201d635e84d01545484fe06610110eb2b0927610cad113ffd523314d03cd78b5d9e89738c837c0f09d25cd0f88024cb6bb2ef738c7b05f9f001edbe77b7d299a4c847d4c7c3ce36f6e23e6e60adf5291cb67094a8a153c7d5a48c800ce427bd04f30ee6409f6af918186a5a8486ad8d6b3fb7ef7106b9cce8a8df2777f5b4958469f6f06780e67dd3fcc112cb3ca27f2903ead5138b04566ea7dfd215513a3ccc658abd22ccf06d6770d485d16c4e8177796909b092f8c615ca52a8ce4fb09bd2e85b40c759733d8fb227321c10928968ac025ab4cfb2af206e708c64421844925340b47237c670d730eb479e8fa30e221aaca4573c6413f881741f0afffa0a52b1fbc1a4daaf176f7f4a38c2ef5f38fc231409bb7e7693b68b27e5922c0e4c6b7efb9b181725d1c23a7dee97208590024b91f74862d7ab490f7386dedbeb27b12262ad0b08922266730c116937146897b8167418b0a2b210a2307159d4bec53908270e8d10b7cbe29f3fee72366a0cc983905266f78577ffd394adc276335fa0e2f8d031465b14d8602e48aec1683f0a07a32376e42b434447a90c50cfd982bdacb9021e0adf771c84171c55988ee5c0dbae4050c4bf0bf2c8e04417aacbc789f694b4f133da9f61a97b14dd7739ed39253e1709d06c40b4f4ee05224d631295537f2f98c2ca45b32c9750cb507502729b15e872be117b48563279a3319f4131f392667dc2aa66b7bd63663fe4ffb7d0e4b8bf87288d5f9647aa3ae990adce267e196dd7f8f2db3a7c8433b8470bb44e0279ec5a3a97d54b3cec598712251acd5551f02f2be990a6f430db1d1f7471dc9b7089672b4d88c30e8e6af60849567a7dedfec12a04f7471ea891727abfe9ce607923bbae50b52e25b4101b59b1b7ab42f71ce5e2f69f5a4cb49d2df7419f028066755b47305b26c61e95f0716b1d0751dc7af7351b122582a619aa45f8f6392e4161a371c2b52b990424007d5583e8cfc1fedfcbcdc7245d2364cac52826f731d605cbab00b33830c0f30a820cbe5730259597f05e303d8617b941c4cc9c26802882ba9d2938ed830ebcb2058d31780d4838b5632b88ec2cdc03d5f1c306baaafd42f97698b0211a5631a5f080d2902c357008fa560d01cd79b64b8c1a067a3"}, &(0x7f0000542000)=0x1008)
bind(r2, &(0x7f0000fb8000)=@generic={0x20000000001e, "0103000000000001000000003a00000009bf79f321b30c7bc8790405c7bad62e0a53a632ed4938d30006fb8f8401a3ff59829a2b0afe7ce43a4b2470a0c5216669ca021f6f65dcf160e7e58f358c0002f0000158d19bcb3151314a8ef1f1622ca5bdb9c8ead2000077aeb81c90001d6d7c980ee590c8b9f70dc136cb184a"}, 0x80)
bind(r2, &(0x7f00009b4000-0x80)=@generic={0xa, "0103000000000000000000000000000009a979f321b30c7bc8790405c7bad62e0a53a632ed4938000001018f8401a3ff59829a2b0a707ce43a4b2470a0c5216669ca021f6f65dcf160e7e58f358c0002f2000158d19bcb3151314a8ef1f1622ca5bdb9c8ead2000077aeb81c90001d6d7c980ee590c8b9f70dc136cb184a"}, 0x80)
socketpair(0x11, 0x80006, 0xa76d, &(0x7f0000ebe000)={0x0, 0x0})
bind(0xffffffffffffffff, &(0x7f0000a63000)=@llc={0x1a, 0x1d, 0xa0a, 0x0, 0x0, 0x296, @random="fffaff3e073c", [0x0, 0x0]}, 0x10)
r4 = socket(0x9, 0x7, 0x7)
bind(r2, &(0x7f000054a000)=@nfc_llcp={0x27, 0x7, 0xb971, 0x1, 0x4, 0x1, "d6e048df75d3d09af7fd50ffdbf9384aff1aa0bbcb0e0b38d41e33f426d791d97052a4cfdf7a80fd9b766fab8f42c42ce2171557bcbcf449550626a1ddee59", 0xb4}, 0x60)
r5 = socket(0x800000000001e, 0x5, 0x0)
recvfrom$unix(r4, &(0x7f0000036000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1000, 0x4, &(0x7f0000521000-0x8)=@abs={0x0, 0x0, 0x0}, 0x8)
sendto(r5, &(0x7f000014e000)="b89da767aa9e5c493bab5382dc3aee52997d3bcfe7394b544c0684df0c92219553d7a553649f3852937feee70dac2ccae585549d7d5d0a37482f7f273224", 0x3e, 0x0, &(0x7f0000bc1000)=@generic={0x1e, "ffff0000899acae7d5fd6f09790802ceab75d656f5fbfd00000009f56b72dfb6fb3e90484cd725f3fe9e0d8e1fb142c69c0c68a59e3413cd11d80253e5f9c0719e9cfe7eb58dc5c7f256b3ecaa00319dcf247b42bdc33f03030000000000000041fc480fbb1bf13a83131b401c20f3df8461acbb410bcd1c3e37db70b1a8"}, 0x80)
setsockopt$inet_dccp_int(r5, 0x21, 0xf, &(0x7f0000f29000)=0x5, 0x4)
prctl$intptr(0x18, 0x1)
getsockopt$inet_sctp_SCTP_SOCKOPT_CONNECTX3(0xffffffffffffffff, 0x84, 0x6f, &(0x7f00000e8000-0x10)={0x0, 0x1, &(0x7f0000c04000-0x10)=[@in={0x2, 0x2, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}]}, &(0x7f00009c5000-0x4)=0x10)
getsockopt$inet_sctp6_SCTP_DEFAULT_PRINFO(r4, 0x84, 0x72, &(0x7f0000f8a000-0xc)={r3, 0x8004, 0x2f}, &(0x7f0000ef3000-0x4)=0xc)
socket(0x1e, 0x80000, 0xf68e)
pipe(&(0x7f0000012000)={0x0, 0x0})
r6 = socket(0x10, 0x2, 0x10)
write(r6, &(0x7f0000109000)="1c0000001e000720279822081d0000000100000000e7ffff0600f70000020019", 0x20)
2017/12/15 11:53:25 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
add_key(&(0x7f0000309000)="7567656c00", &(0x7f00005d6000-0x5)={0x73, 0x79, 0x7a, 0x2, 0x0}, 0x0, 0x0, 0xfffffffffffffffe)
r1 = openat$selinux_status(0xffffffffffffff9c, &(0x7f00003af000-0x10)="2f73656c696e75782f73746174757300", 0x0, 0x0)
getsockopt$SO_PEERCRED(r1, 0x1, 0x11, &(0x7f0000767000+0xd90)={0x0, 0x0, 0x0}, 0xc)
mmap(&(0x7f0000000000/0xda6000)=nil, 0xda6000, 0x0, 0x64031, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$sg(&(0x7f0000643000)="2f6465762f73672300", 0x8, 0x0)
mmap(&(0x7f000030a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0xe)
mmap(&(0x7f0000da7000/0x1000)=nil, 0x1000, 0x3, 0x33, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000004f000-0x78)={0x200000002, 0x78, 0x7f, 0x2, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x9bb0af8aaa049dec, 0x0, 0x2, 0x10000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
sync()
lstat(&(0x7f0000cf6000-0x8)="2e2f66696c653000", &(0x7f0000453000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
r3 = socket(0x10, 0x20000000000003, 0x0)
write(r3, &(0x7f0000566000-0x22)="2200000014000721004f10f7e2ff0500020003000100000008000200e700ff02f155", 0x22)
connect$nfc_raw(r3, &(0x7f0000557000)={0x27, 0xffffffffffff8000, 0x800, 0x0}, 0x10)
getsockopt$ax25_buf(r3, 0x101, 0x19, &(0x7f000087c000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000f30000-0x4)=0x64)
r4 = bpf$PROG_LOAD(0x5, &(0x7f0000a1a000)={0xfffffffffffffffc, 0x0, &(0x7f0000693000)=[], &(0x7f0000c62000-0x1)="00", 0x120000010, 0x86, &(0x7f000029a000-0x86)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x200000006, 0x0}, 0x30)
ioctl$sock_proto_private(r0, 0x89e4, &(0x7f00008eb000-0x26)="8415ee06974c9fe1960542bbd8132823dd3a38f2bb497c08dd26833fe6bcb223c3a5e037720d")
mmap(&(0x7f0000da6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000da8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$OBJ_PIN_PROG(0x6, &(0x7f0000da8000)={&(0x7f00007f1000-0x8)="2e2f66696c653000", r4}, 0x10)
recvmsg(r2, &(0x7f0000253000)={&(0x7f000075e000)=@ll={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @random="000000000000", [0x0, 0x0]}, 0x14, &(0x7f0000a9f000-0x50)=[{&(0x7f0000a58000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x46}, {&(0x7f0000f5c000-0x4a)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x4a}, {&(0x7f0000910000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9c}, {&(0x7f00002a4000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9d}, {&(0x7f0000660000)="000000", 0x3}], 0x5, &(0x7f000048e000-0xae)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xae, 0x154}, 0x40000000)
getsockopt$inet_opts(0xffffffffffffffff, 0x0, 0x1, &(0x7f0000936000)="00000000000000000000000000000000000000", &(0x7f00000ff000)=0x13)
fcntl$getflags(r0, 0x401)
socket$inet_tcp(0x2, 0x1, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x0, 0x40032, 0xffffffffffffffff, 0x0)
listen(0xffffffffffffffff, 0x1)
2017/12/15 11:53:25 executing program 3:
mmap(&(0x7f0000000000/0x11000)=nil, 0x11000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$binder(&(0x7f0000001000-0xd)="2f6465762f62696e6465722300", 0x0, 0x0)
mmap(&(0x7f0000011000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$sequencer2(0xffffffffffffff9c, &(0x7f0000012000-0x10)="2f6465762f73657175656e6365723200", 0x0, 0x0)
mmap(&(0x7f0000011000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_dccp_buf(r1, 0x21, 0xf, &(0x7f0000009000-0x54)="5ca74013a47ee67c1495cb1de5447ee92c5584bffe09fb6c207d2e3ba11130742a75e5e00a2a22f8d108b91baab8a67bab966b1092769a5994a9738f0e4ce8d45173d09e99965d771479b55b77b75febd332a01e", 0x54)
mmap(&(0x7f0000011000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000012000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000013000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000013000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000013000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$EVIOCGVERSION(r1, 0x80044501, &(0x7f0000013000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
sendmsg$netlink(r1, &(0x7f0000006000)={&(0x7f0000011000)={0x10, 0x0, 0x7fffffff, 0x2}, 0xc, &(0x7f0000011000)=[{&(0x7f000000d000)=[{0xd6, 0x4, 0x10, 0x3, 0x305c, "1d392b7e4f86e2b340cc8ff0a0b763c6fb51e7a2245a2c3355912cf304a1b264db7132daa64ca34f9fed6bb5cf68303112bd846fd08ee4bf871f0372fed45fa0919494a2dc4a3a176e84c9d50a55440a6face577c22ae6e6476d9049c36c226a1f41e54de6955f6303979274ac6d6be867132a43638b025a77ab81b3ff016cb752a109ff5664f0228d858d8d72daf90ffa7efdd1f9a583a224e61c0fd0317baf99c8c4748e8edec8f39fbe0f911fda733108439a67608eb8a4bfea891ee49964adc140b29ce1"}, {0xad, 0x8, 0x0, 0x4, 0x2, "aab4ca7e5d43eb8423228df17328212927633e564036fe4c80bc48b3ce37569228b2c252bf983e5940e44173259c9d087bff17630f1e74ea9ecb8373205f007bc09eb2b1aab97d834fc0a52c6598ead60c714623f5f090f980b3d3d75528c9cc4ae5ff6fb5ce82ae33a36c35564db7867822b16c467e0e3439a520490f7ac3d3ac256ad7fffb24d8e0b97bce1d1eba4d305f884dc14a6d2aab2770ea13"}, {0x5b, 0x9, 0x400, 0x40, 0x20, "753b8e42e890c13ad25a48395bd93701fd3fe827323fa7ba6350e7b928e04587bd91c826b1d4dd00c174df8976886e3ed1e096b574d7ba7b1bb96a6291afd063e4912800876a42aa14a3d5"}], 0x1de}], 0x1, 0x0, 0x0, 0x4000800}, 0x1)
r2 = syz_open_dev$sndseq(&(0x7f000000b000-0xd)="2f6465762f736e642f73657100", 0x0, 0xa000)
ioctl$SNDRV_SEQ_IOCTL_SET_QUEUE_CLIENT(r2, 0x404c534a, &(0x7f000000e000-0x4c)={0xac40, 0xc3, 0x3ff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r3 = mmap$binder(&(0x7f000023d000/0xc00000)=nil, 0xc00000, 0x0, 0x8011, r0, 0x0)
mmap(&(0x7f0000011000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$BINDER_GET_NODE_DEBUG_INFO(r0, 0xc018620b, &(0x7f0000012000-0x18)={r3, 0x0, 0x0, 0x0})
fcntl$setstatus(r1, 0x4, 0x40c00)
mmap$binder(&(0x7f000000c000/0x3000)=nil, 0x3000, 0x2000000, 0x10, r1, 0x0)
mmap(&(0x7f0000014000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_FIOGETOWN(r1, 0x8903, &(0x7f0000014000)=<r4=>0x0)
ioctl$TIOCSPGRP(r1, 0x540f, &(0x7f000000c000-0x4)=r4)
setsockopt$sock_int(r1, 0x1, 0x20, &(0x7f000000b000)=0x8, 0x4)
mmap(&(0x7f0000012000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$ax25(r1, &(0x7f000000a000-0x10)={0x3, {"154fe83963a188"}, 0x7}, 0x10)
openat(r1, &(0x7f0000012000)="2e2f66696c653000", 0x8000, 0x1)
2017/12/15 11:53:25 executing program 0:
mmap(&(0x7f0000000000/0x5cc000)=nil, 0x5cc000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005ce000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005d0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005d1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005cd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f00005ce000-0x8)={0xffffffffffffffff, <r0=>0xffffffffffffffff})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
r1 = socket$inet6(0xa, 0x1, 0x8)
setsockopt$inet6_buf(r1, 0x29, 0x38, &(0x7f0000854000)="ff8d57a9a22d7355032fc98689b53a6e97c97677010964b6497540f22dbd387a8295139bd52e79ba1dbe169bc3895e77a104c2a6ba6e7d959796cd9a52c656e35012d8c4644605a7", 0x48)
sendto$inet6(r1, &(0x7f00000b2000-0x6b)="", 0x0, 0x0, &(0x7f0000439000-0x20)={0xa, 0x0, 0x0, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x100000cb}, 0x1c)
mmap(&(0x7f0000f53000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f54000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_int(r1, 0x29, 0x38, &(0x7f0000f54000)=0x4, 0x4)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
read(r0, &(0x7f000063b000-0x63)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x63)
mmap(&(0x7f0000f55000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f55000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f56000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f57000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f57000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
recvmsg(r1, &(0x7f0000f52000)={&(0x7f0000f57000)=@un=@abs={0x0, 0x0, 0x0}, 0x8, &(0x7f0000f57000)=[{&(0x7f00003f8000-0x1000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}], 0x1, &(0x7f0000f52000)="", 0x0, 0x400000000000001b}, 0x0)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005d1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005d2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f54000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
vmsplice(r0, &(0x7f0000f54000)=[{&(0x7f0000f53000-0xb7)="603063453c13518ea27ca5ab75ba03fc72be3cad3407d97291a9b847e78153b1a5454db263b009d0b169aaa4838c00dd90bfefe2d48f5af9b6216e4a887f4398210b4a9c670333f2e319d708d40c59a242f17aca01c1298e5e6e2c0a20eb0b5089e9660bbc31ff4d01bb6c1c0b0ac31141953b04237575049cc8e92875310a8eed7cbac5ea964e9933a4bf855856c7b84f25efc72ae934222c1af19111058229797706b2464924aa6579d87a21b8d4fa2e3ad858044734", 0xb7}, {&(0x7f00005cf000)="f3f2f1bf34ab705359d820ef9c4835492e0698a44e6ccd14f38595c6bb6cfedd10ac09ef3416783d441f60f1d0475b7c41d6557ea64c25b7e2458df3492a76618ec555b84da8313bc1fee0d3e5582bd675dde083384cbef5ac0544abecc9813a520a6c34c3c6a95dac0a", 0x6a}, {&(0x7f000048b000-0x6e)="349259b2f79f2fad94e9057534868fbebe24f4b5487586167e869d8bdbf8aa2eb397e8f76543fc16e318266d1454835c31bb329dd346689dd529f71de8e1e6a02f4a48e58922f4db0333cf59d7d03243e63811ebebb83915a446803e6f96db49b36f0bcf74313d8403d72b18db60", 0x6e}, {&(0x7f0000935000)="e6edb08a68d4381ad048942bf77c4fd8fbfcb53413dbd9d396ad94d19b40a3e4fd34a558822ef0c59b2c43", 0x2b}, {&(0x7f0000cd1000)="cf06a3824d", 0x5}, {&(0x7f0000226000-0x63)="14e06fef2c14e8633ad4ec2ef4752f50cc6aa2f6a09010ce1596948af455cde21e7b68d284cc8f6235feefcd7701272a2353bc836f1fd82dabf712d94440ae359739f08e9a45382f09f4ebc8feab3192cd2951b0eb986f7e290c7cbbc2308292420ce5", 0x63}], 0x6, 0x5)
mmap(&(0x7f00005ce000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$int_in(r0, 0x800005421, &(0x7f0000ea1000)=0x2000803)
socket$inet_icmp(0x2, 0x2, 0x1)
[ 49.373878] netlink: 'syz-executor1': attribute type 39 has an invalid length.
[ 49.413486] nla_parse: 2 callbacks suppressed
2017/12/15 11:53:25 executing program 4:
socketpair$inet(0x2, 0xf, 0x20000000, &(0x7f0000bf6000)={0x0, 0x0})
socketpair$unix(0x1, 0x1, 0x0, &(0x7f0000000000)={0xffffffffffffffff, 0xffffffffffffffff})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf6e, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x401, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x4)
r0 = memfd_create(&(0x7f0000ecc000-0x24)="706f7369785f61636c5f61636365737373797374656d406b657972696e67776c616e3100", 0x2)
mmap(&(0x7f0000000000/0x30000)=nil, 0x30000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp_SCTP_PARTIAL_DELIVERY_POINT(r0, 0x84, 0x13, &(0x7f0000eea000-0x4)=0x7f, 0x4)
ioctl$TUNSETIFF(r0, 0x400454ca, &(0x7f0000500000-0x28)={@common="7465716c300000000000000000000000", @ifru_settings={0x3, 0x4, @fr=&(0x7f0000296000)={0x100000001, 0x9, 0x8, 0xfff, 0x400, 0xffff, 0xfffffffffffffffb}}})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000011000/0x3000)=nil, 0x3000, 0x4, 0x32, 0xffffffffffffffff, 0x0)
ioctl$VT_DISALLOCATE(0xffffffffffffffff, 0x5608)
r1 = userfaultfd(0x0)
ioctl$UFFDIO_API(r1, 0xc018aa3f, &(0x7f0000d28000)={0xaa, 0x0, 0x0})
r2 = epoll_create1(0x0)
ioctl$UFFDIO_REGISTER(r1, 0xc020aa00, &(0x7f0000e4d000-0x20)={{&(0x7f0000012000/0x2000)=nil, 0x2000}, 0x1, 0x0})
epoll_ctl$EPOLL_CTL_ADD(r2, 0x1, r1, &(0x7f0000ca3000)={0x0, 0x0})
r3 = syz_open_dev$sndtimer(&(0x7f0000b0d000)="2f6465762f736e642f74696d657200", 0x0, 0x0)
r4 = openat$rfkill(0xffffffffffffff9c, &(0x7f000059a000)="2f6465762f72666b696c6c00", 0x0, 0x0)
ioctl$TIOCSSOFTCAR(r4, 0x541a, &(0x7f0000b2d000-0x4)=0x6)
ioctl$SNDRV_TIMER_IOCTL_NEXT_DEVICE(r3, 0xc0145401, &(0x7f0000013000)={0x0, 0x0, 0x0, 0x0, 0x0})
readv(0xffffffffffffffff, &(0x7f0000c84000-0x10)=[], 0x0)
ioctl$SNDRV_TIMER_IOCTL_TREAD(r3, 0x40045402, &(0x7f0000383000-0x4)=0x1)
dup3(r2, r1, 0x0)
syz_open_dev$evdev(&(0x7f0000326000)="2f6465762f696e7075742f6576656e742300", 0xfffffffffffffffa, 0x843d)
mq_open(&(0x7f000001b000)="47504c24656d3100", 0xc2, 0x100, &(0x7f0000027000-0x40)={0x9, 0x1, 0x7ff, 0x8000, 0x0, 0x0, 0x0, 0x3})
mmap(&(0x7f0000030000/0x1000)=nil, 0x1000, 0x3, 0x4000032, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000271000)={0x2, 0x78, 0x49, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0xfffffffffffffffd, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:25 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$hwrng(0xffffffffffffff9c, &(0x7f0000b23000)="2f6465762f6877726e6700", 0x200, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r1 = perf_event_open(&(0x7f000002f000-0x78)={0x1, 0x78, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x20000, 0x0, 0x6, 0x8, 0x0, 0x0, 0x0, 0x7, 0x0, 0xfffffffffffffffc, 0x8, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0xa)
r2 = socket$inet_tcp(0x2, 0x1, 0x0)
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f0000e4b000)=0x0)
r3 = memfd_create(&(0x7f0000e66000)="00", 0x2)
ioctl$TIOCGSID(r3, 0x540f, &(0x7f0000ece000-0x4)=<r4=>0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x400000000000009, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r4, 0x0, 0xffffffffffffffff, 0x0)
r5 = syz_open_dev$vcsa(&(0x7f0000202000)="2f6465762f766373612300", 0x3ffff, 0x400000002)
bpf$PROG_LOAD(0x5, &(0x7f0000b4d000-0x30)={0xffffffffffffffff, 0x0, &(0x7f0000ef3000)=[], &(0x7f0000446000)="2f6465762f766373612300", 0x1, 0x80, &(0x7f000000a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x8000000000100, 0x0}, 0x30)
ioctl$EVIOCGKEY(r5, 0x80404518, &(0x7f0000866000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
inotify_add_watch(r5, &(0x7f00007bf000-0x8)="2e2f66696c653000", 0x80000001)
r6 = inotify_add_watch(0xffffffffffffffff, &(0x7f0000218000-0x8)="2e2f66696c653000", 0x1000000)
inotify_rm_watch(r1, r6)
ioctl$KVM_SET_GUEST_DEBUG(0xffffffffffffffff, 0x4048ae9b, &(0x7f000047d000)={0xa0001, 0x0, [0x7, 0xe2cb, 0x64, 0xbea7, 0x9, 0x81, 0x1ff, 0x100000002000005]})
ioctl$PERF_EVENT_IOC_SET_OUTPUT(r0, 0x40042409, r0)
2017/12/15 11:53:25 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x968, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x5, 0x1, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = socket(0x10, 0x3, 0x0)
ioctl$DRM_IOCTL_VERSION(0xffffffffffffffff, 0xc0406400, &(0x7f000033a000-0x40)={0x4, 0x81, 0x2000000000008, 0xe2, &(0x7f0000cf5000-0xe2)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1000, &(0x7f0000810000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1, &(0x7f0000cf4000-0x1)="00"})
setsockopt$SO_ATTACH_FILTER(r0, 0x1, 0x1a, &(0x7f0000fa4000)={0x1, &(0x7f0000f96000-0x10)=[{0x100000000000006, 0xfffffffffffffffd, 0x0, 0x0}]}, 0x10)
socket$inet_icmp_raw(0x2, 0x3, 0x1)
r1 = syz_open_dev$mouse(&(0x7f0000d17000-0x12)="2f6465762f696e7075742f6d6f7573652300", 0x0, 0x400400)
ioctl$SNDRV_TIMER_IOCTL_INFO(r1, 0x80e85411, &(0x7f0000c0c000-0xae)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
getsockopt$inet_sctp_SCTP_PEER_ADDR_THLDS(r0, 0x84, 0x1f, &(0x7f0000239000-0x98)={<r2=>0x0, @in6={{0xa, 0x1, 0x3, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x96, 0x0}, &(0x7f00006f8000-0x4)=0x98)
setsockopt$inet_sctp6_SCTP_ASSOCINFO(r0, 0x84, 0x1, &(0x7f000004e000-0x14)={r2, 0x5, 0x7, 0x7f, 0x1, 0x8}, 0x14)
write(r0, &(0x7f0000936000-0x26)="26000000130047f10701c1b00e000000000000000100000009ef18fcff00f132040014006e35", 0x26)
pipe(&(0x7f0000cdb000-0x8)={<r3=>0x0, <r4=>0x0})
r5 = openat(0xffffffffffffffff, &(0x7f0000e82000-0x8)="2e2f66696c653000", 0x2000, 0xa3)
getsockname$unix(r5, &(0x7f0000c18000-0x8)=@abs={0x0, 0x0, 0x0}, &(0x7f0000728000-0x4)=0x8)
ioctl$PERF_EVENT_IOC_SET_OUTPUT(r1, 0x2405, r5)
openat$sequencer(0xffffffffffffff9c, &(0x7f0000c18000)="2f6465762f73657175656e63657200", 0x20000000, 0x0)
ioctl$SNDRV_SEQ_IOCTL_GET_CLIENT_POOL(r3, 0xc058534b, &(0x7f0000736000-0x58)={0x100000000, 0x6, 0x9, 0x4003, 0x101, 0x423, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$nfc_llcp_NFC_LLCP_RW(r5, 0x118, 0x0, &(0x7f00004fa000-0x4)=0x3, 0x4)
r6 = socket$inet_tcp(0x2, 0x1, 0x0)
r7 = socket$inet6_tcp(0xa, 0x1, 0x0)
ioctl$sock_SIOCGPGRP(r7, 0x8904, &(0x7f0000b24000)=0x0)
connect$inet6(r4, &(0x7f0000ebb000)={0xa, 0x0, 0x3, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x81}, 0x1c)
fcntl$notify(r4, 0x402, 0x8)
bind$inet6(r7, &(0x7f0000c9c000)={0xa, 0x2, 0xffffffffffffffff, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
getsockopt$sock_linger(r5, 0x1, 0xd, &(0x7f0000099000-0x8)={0x0, 0x0}, &(0x7f00008a3000)=0x8)
listen(r7, 0xfffffffffffffffd)
add_key$user(&(0x7f0000f6e000)="7573657200", &(0x7f00009c2000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, &(0x7f0000d5a000-0x57)="5153e7ae21fe00e43ab48a6394b4fa881ec234e9d8455e65fa98e84969d734dfac2ef3f27af8c728758614bd4f0c70653ebe67e00783a66993a8a4b5b1f0a1b326d5ed9d5387b5b236201c11f29ba137baad46d762b4d6", 0x57, 0xfffffffffffffffe)
sendto$inet(r6, &(0x7f0000d44000)="", 0x0, 0x20008045, &(0x7f00000f6000)={0x2, 0x0, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
socketpair$inet6_dccp(0xa, 0x6, 0x0, &(0x7f00000c5000)={0x0, 0x0})
close(r6)
2017/12/15 11:53:25 executing program 6:
r0 = socket$inet6(0xa, 0x1000000000003, 0xb)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x2, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = creat(&(0x7f0000001000)="2e2f66696c653000", 0x100)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TIOCLINUX5(r1, 0x541c, &(0x7f0000003000-0x28)={0x5, 0xa0, 0x1ff, 0x8, 0x30000})
getsockopt$inet6_buf(r0, 0x29, 0x30, &(0x7f0000001000)="", &(0x7f0000001000-0x4)=0x0)
setsockopt$inet6_int(r0, 0x29, 0x4a, &(0x7f0000001000-0x4)=0x1, 0x4)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$bt_rfcomm_RFCOMM_CONNINFO(r1, 0x12, 0x2, &(0x7f0000004000-0x93)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000004000-0x4)=0x93)
mmap(&(0x7f0000000000/0xf50000)=nil, 0xf50000, 0x4, 0x32, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$sg(&(0x7f0000f51000-0x9)="2f6465762f73672300", 0x9, 0x501800)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_PRIME_HANDLE_TO_FD(r2, 0xc00c642d, &(0x7f0000f51000-0xc)={0x0, 0x80000, r1})
r3 = fcntl$getown(r2, 0x9)
fcntl$lock(r1, 0x7, &(0x7f000073c000)={0x2, 0x4, 0x4, 0x80000001, r3})
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_SET_GSI_ROUTING(r2, 0x4008ae6a, &(0x7f0000f50000)={0x7, 0x0, [{0x4, 0x3, 0x0, 0x0, @msi={0x100000001, 0x4c482061, 0x5}}, {0x8000, 0x2, 0x0, 0x0, @adapter={0x4, 0x100000000, 0xce, 0x2, 0x2}}, {0x0, 0x4, 0x0, 0x0, @irqchip={0xffffffffffffff00, 0x7}}, {0x6, 0x4, 0x0, 0x0, @sint={0x9, 0x6}}, {0x8000, 0x3, 0x0, 0x0, @irqchip={0x5, 0x9}}, {0xab2, 0x3, 0x0, 0x0, @irqchip={0x7, 0x6}}, {0x0, 0x3, 0x0, 0x0, @sint={0x3, 0x1d}}]})
r4 = ioctl$LOOP_CTL_GET_FREE(0xffffffffffffffff, 0x4c82)
ioctl$LOOP_CTL_ADD(r2, 0x4c80, r4)
r5 = dup(r0)
mmap(&(0x7f0000f51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fsetxattr(r0, &(0x7f0000f52000-0x1a)=@known="636f6d2e6170706c652e73797374656d2e536563757269747900", &(0x7f0000255000)="00", 0x1, 0x1)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TUNGETIFF(r5, 0x800454d2, &(0x7f0000f51000-0x4)=0x6)
sendto$inet6(r0, &(0x7f0000f53000)="", 0x0, 0x0, &(0x7f0000b55000)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x0}, 0x1c)
ioctl$sock_inet6_udp_SIOCINQ(0xffffffffffffffff, 0x541b, &(0x7f00002a8000)=0x0)
recvfrom$inet6(r0, &(0x7f0000f57000-0xf2)="", 0x0, 0x48010122, 0x0, 0x0)
[ 49.413491] netlink: 2 bytes leftover after parsing attributes in process `syz-executor5'.
[ 49.454598] netlink: 2 bytes leftover after parsing attributes in process `syz-executor5'.
2017/12/15 11:53:25 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = open$dir(&(0x7f00000b9000)="2e2f66696c653000", 0x180, 0x1)
r1 = creat(&(0x7f0000a83000)="2e2f66696c653000", 0x48)
ioctl$KVM_REGISTER_COALESCED_MMIO(r1, 0x4010ae67, &(0x7f000036b000)={0x107000, 0x11000, 0x0})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = syz_open_procfs(0x0, &(0x7f0000ab5000)="6e65742f6669625f747269657374617400")
ioctl$TIOCGPGRP(r2, 0x540f, &(0x7f0000257000)=<r3=>0x0)
sendfile(r2, r2, &(0x7f0000858000-0x8)=0x3, 0x65a3fd1d)
nanosleep(&(0x7f000056d000)={0x77359400, 0x0}, 0x0)
perf_event_open(&(0x7f000002f000-0x78)={0x0, 0x78, 0x0, 0x1000, 0x1fb, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x0, 0x4f2d1588af716cea, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r4 = memfd_create(&(0x7f0000201000)="2d76626f786e657430626465762c00", 0x2)
setgid(0x0)
ioctl$DRM_IOCTL_RES_CTX(r4, 0xc0106426, &(0x7f00009da000)={0x6, &(0x7f0000d23000)=[{<r5=>0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}]})
ioctl$DRM_IOCTL_GET_CTX(r2, 0xc0086423, &(0x7f0000028000-0x8)={r5, 0x2})
ioctl$KVM_SET_USER_MEMORY_REGION(r2, 0x4020ae46, &(0x7f0000af9000)={0x10002, 0x3, 0x11000, 0x2000, &(0x7f0000fad000/0x2000)=nil})
sched_setaffinity(r3, 0x8, &(0x7f0000b8a000)=0x75)
ioctl$KVM_ASSIGN_DEV_IRQ(r2, 0x4040ae70, &(0x7f0000087000-0x10)={0x400005, 0x200000000006, 0xfff, 0xfffffffffffffffd})
r6 = openat$kvm(0xffffffffffffff9c, &(0x7f0000eb7000)="2f6465762f6b766d00", 0xfffffffffffffffe, 0x0)
r7 = ioctl$KVM_CREATE_VM(r6, 0xae01, 0x0)
ioctl$KVM_SET_CPUID(r2, 0x4008ae8a, &(0x7f00005b2000)={0x5, 0x0, [{0xb, 0x67, 0x7, 0xfffffffffffffffc, 0x6, 0x0}, {0x0, 0x1, 0xffff, 0x40, 0x4, 0x0}, {0x7, 0x10000, 0x10001, 0x6, 0xfffffffffffffa6e, 0x0}, {0xb, 0x2, 0xff, 0x4, 0x2c636efe, 0x0}, {0x6, 0xff, 0x5cc6809d, 0x8, 0xbfb, 0x0}]})
ioctl$TIOCTTYGSTRUCT(r1, 0x541a, &(0x7f0000d8d000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
getsockopt$inet_pktinfo(r0, 0x0, 0x8, &(0x7f00004c5000-0xc)={<r8=>0x0, @multicast2=0x0, @remote={0x0, 0x0, 0x0, 0x0}}, &(0x7f0000244000-0x4)=0xc)
ioctl$sock_SIOCGIFINDEX(r4, 0x8933, &(0x7f00007d4000-0x28)={@common="6c6f0000000000000000000000000000", r8, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_CREATE_VM(r2, 0xae01, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000d9d000-0xc)={<r9=>0x0, 0x0, 0x0}, &(0x7f000044c000)=0xc)
r10 = syz_open_procfs(r9, &(0x7f0000ad9000)="617474722f63757272656e7400")
memfd_create(&(0x7f0000e0c000-0xd)="617474722f63757272656e7400", 0x1)
delete_module(&(0x7f0000e8f000)="76626f786e6574312b736563757269747970726f632c00", 0xa00)
sendfile(r10, r10, &(0x7f0000359000)=0x0, 0x21)
ioctl$KVM_CREATE_VCPU(r7, 0xae41, 0x1)
[ 49.484100] netlink: 'syz-executor1': attribute type 39 has an invalid length.
[ 49.499332] netlink: 2 bytes leftover after parsing attributes in process `syz-executor3'.
[ 49.525958] netlink: 2 bytes leftover after parsing attributes in process `syz-executor3'.
2017/12/15 11:53:26 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6_tcp(0xa, 0x1, 0x0)
close(r0)
r1 = socket$inet6(0xa, 0x8000000000000802, 0x0)
bind$inet6(r0, &(0x7f0000fbf000-0x1c)={0xa, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
setsockopt$inet6_int(r0, 0x29, 0xcf, &(0x7f0000c03000)=0x9, 0x4)
sendto$inet6(r1, &(0x7f0000fbd000)="", 0x0, 0x0, &(0x7f0000fbb000)={0xa, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
r2 = socket$inet(0x2, 0x1, 0x0)
r3 = syz_open_dev$tun(&(0x7f0000e6e000-0xd)="2f6465762f6e65742f74756e00", 0x0, 0x101101)
ioctl$TUNSETIFF(r3, 0x400454ca, &(0x7f0000a5b000-0x28)={@common="67726530000000000000000000000000", @ifru_names=@generic="4f54000cc0a1ed4f3a0a1fdc222073b5"})
ioctl$sock_inet_SIOCSIFFLAGS(r2, 0x8914, &(0x7f0000630000-0x20)={@common="67726530000000000000000000000000", @ifru_flags=0x301})
ioctl$TIOCGPGRP(0xffffffffffffffff, 0x540f, &(0x7f0000b4a000)=0x0)
ioctl$TIOCGSID(0xffffffffffffffff, 0x540f, &(0x7f00002de000)=0x0)
sendmsg(r2, &(0x7f000005e000)={&(0x7f0000ad2000+0x7b3)=@l2={0x1f, 0x1000, {0x633, 0x4, 0x9, 0x1, 0xb43, 0x2}, 0x7fffffff, 0x1ff}, 0xe, &(0x7f0000667000-0x90)=[{&(0x7f00005e6000)="a679fd7dc16a7b4a64fab93ea221656ac842bd993f5a05d998de557b7b36826ddbbfe2a77e2ea829ac8eaf0e96f7325d7182b7a9466c76cf3f369207fdac8de0bc527af17009af030669aa4aed83d0079ca5e913d56f361c1bf05753f436f20390d8750364c6c24b14c6446669fa08f44e91fc60d1895c5ef6cf132bd273", 0x7e}, {&(0x7f00005db000-0x6c)="74c1c5acc3c9d351174aa4279304b815a8b156ba46cea8897acffc3254ebae6b3719a254f3a7df541c50ef13c9ae86f1127ec57b6d605723493ea439dd8b5954a8f990081e191e24f7a69cc1f976fd34890bedb827445ee4f159dfe5e642758976c8bc51b169c5f9f8a0f8c4", 0x6c}, {&(0x7f00008bc000-0x5c)="c5184ddc59a4b6c9d8d102a4707100273636682c84c50369cc312167b68e10039dd2d6f052f3722f339490c92eb297c1e66ffafa62ae8972122e81f686312564834339e9fc5013535d0ee42aa43da1075580abb5e80608c20018b8d0", 0x5c}, {&(0x7f0000e42000-0x52)="cb50683fc500831ca56405237d89cc7fbab7d694788cf34767b8c13fe5892279d51aa8a4912d3f52352f90d32e0fc3e6e3180841eaad8c36fd456cef5d9d5f6973e781ba0572a00637a84e3f67a0507dcc59", 0x52}, {&(0x7f0000107000)="35f7806ba9febb6525b8b2df28f88bfbb7375f307a6a86208faa3f35cd402f7a2e782510959c80d5c948e2367ac41c077953428af7fb1853e9ddb6e949e37799bcef21266bf7e61dd5f03e1a04057342b4ac4baa0f64a52f5c48fa6ad95331b3619f7222700c0ff34319a645ad0ea08a4540fab2df4555b7ebabe70c94098aeb485f7cfc4865f1c5c2f9eb0cc1874b9e29c51adf43b6ee833133eaa929", 0x9d}, {&(0x7f0000f62000)="628252dfe9562209c48f1bbc837ebe32cd177daff20bb7c50aa7e2e766", 0x1d}, {&(0x7f0000be7000)="63d88ea518990c520faf0e6123269b69be13324b2564c9b63a88609cc4b8e639199a8592251aab103e963a6cf24fbf5e5f664d626fdc92cca78942a8a3dc926214d6d76c98bcb02d5949dc2e2e0e6d84cf70c10779ecfc1848220180494934c00104c7e4175fbd6a0841b3620923e599d25b48449f9d99f9801febb00b3169ea3b4eb55e22926631b84615cc856a5a593f0e4bdac5b4445b6bf4193cf13a", 0x9e}, {&(0x7f0000e93000)="1390b36b44a87e8c0f3ebaf31a1b01142d0d613d9eec49cf9a00427484becdfd7dfc4990d86574ee712ebde9f2c405b6a32f88f2e3acba4c5789a86bc73c08ce3b5f8ad8a17302401c02d28e62aa88165182a7cec8f8e7eda5e674c0dd1b1b82c8fb0ab87cd7167bf7b8139ab960494789a07b4796c422dd9057aa58c0cd41576c3521b5dc0a989744c768f587416e1b30480e21b3d23faff33c8c0b04d520b918b2d81c58cd2ba5e80da80010ebe15691246f5029ba4d9144e7ef4d520df1e9972122918e46887537afd91c63cfc5eaabfc20a0a8189477b0a87513423731", 0xdf}, {&(0x7f0000c7f000-0x57)="9e6b212623595970d08b8ccb81b7fdf6791ae3e44bc305d50457fb73719378936d53f6efd074516a18c8aef56fbdcfe83885d8f8bb8864cb89b79cd7de76ef98b863085148ed42cd6c7fd621e75ab233d9bcdd0eaa604f", 0x57}], 0x9, &(0x7f0000035000)=[{0x90, 0x6, 0x3, "2be1382b835af5b2f5a5b5a1bb74f5ff6eb97c596a29ed7bd6997132e5e127a02370d26d74e3164d856101c457340fe31e520f0a828b87091d0fc0075572899b76bbc4889f20cbdf4b24f6f96129eb47672ac53e3a0c9d3c6f55be6d250aa389b4c72c71debc7fff3f33198ad02f4763e87a876f2b31c160d8c9"}, {0x50, 0x3a, 0x0, "0efbead8cc17a62439ef961336fe545710c5a730df3e52016aff68d472a984933499bfedfe28aecac9ffebbc85a762f9643e682a4fc3f71212593089a5"}, {0x80, 0x195, 0xffffffffffffb424, "1c8f930dce7a3af179383a02df6dfd9de500e1767b0fe819d74eb95c7a562d08ba35354479c1e3eb20d1a99315bba824633586e840d8c90eec025def3aa1327b500bf4c8deef9f9e3082b4f45caf8f100083e789baa8c8d9c5a63371755965e66d21edcfb704bc7bc174d22f"}, {0x80, 0x0, 0x800, "34c469674aafc039c6a445f7241378c13ee18b40f8cbef8b95d07d7c48e508d496235cfaa5e2e5e8bfa43690287b97395715bb2bd29d6be8a7ac300327eb72c88683b659065fc343264cbdab7330b1c7e364aeebeca2e41e54a419859f1ee65b021eee453ef60b6da993629d460db5"}, {0x1010, 0x84, 0x100000001, "fdf41dd38f91e59c543bfa02a68397965db0250ff01ed764058c2512350ce131073a902d6f235386f1e8e277f2af35cfaabc0e97d2ae543bfd7112b6eb26b89586b7ed41703bfecf041d6d98ebbf001fd7a71961d4461d04dcd2d140a5bafa2a457bb198c7272476283d3d58273846add8615d7853612ce216ee20b442c5e5bd8e084881eade7859cf1f337e669611800b618aad366d5855c26a6b1f023b65a7dc707b7f092ab6e3972dfb6cc0effa4e4cd6e771d284ab2f958fdf860a850b2f77a4040b92e4beb816808207ad4e07fabb3a85b3737be59643bdae78e95fbae211464b93fb9012075ba74c158d2c857f6958bfacbb23ca57dc5c6a489a942170bfd37c028db456ee44576606b863e422ed6d1f4e95f06aae4b09a67d5ab2e9d7d46cab10e8bc357e893f7cbb266c0b368917ff385d4e62a5875be84a4b6458ba63df55cd84d1d60205c771fe7270cd1b8eeaf6556cbffef6e216769e2290331923c406a9f2b0d6727b15ec7b5211d689bd534a2cd3b8a15db02a1cab56c41e478e4edc6d616c387a9b736976e24b801af2d3820965d6fe4a026234ee278afa4706f4a2627644595ab2b1a40d517d8b719ba54f6a1ea75a39988b89aafcd1f07d35d6918f3aac4a5163060439ebf0f32d1d465c08c70da5338b4502c32e8236ddf0facdfb22a8404ffd8e6d6fb1af03ffda365ac3543a719d4753733ca123fd03fbb13ec88152472752813f503159395700e84f133be4c9121a16f5d1ef60101425155892171b73200851696ac181ffa783479d5dd7cc21e36975e261da7b1024bc2935e6935f6c50eac652f3b7f5f8bb57a9ec0be43ffca499dc3872f91ad7cb0facbe85e7515c5331dd181d21ba2791c948d4f6c7ca15dbffa12722873443ddc44d80b94f263e924593a20f5a8b94c8049ce5af1cb6a736ecae29549d9ae006d2e014f24464a6026770fb1fae27aad1ef1f5576a99349352d84f24ac74ca7d1ec4d3e1792431d8376d5e4b0e3437ec8de934ee5f0668f614083bb46fed1ae823565c846e640667452bfc4695a3f02423f7aa803687afd02b968ad6fab1757e07055b563ee0b1d09ca42c0342b9c7149dae223114d2c81dcb7310849d63c89b1fb05f3e1f7fa9de0929c1da320f75acc4eabc8cc0efcb1b7deb6ca53ca7b6310eeceda99ede9d37c8bb68b708d5ffa7a7d7cd5f1095eb749ac550fec88d965b78fd4ac79bf3b2e40fb00e2f1d5dd3cc5392ffb54765200a75cd85a73cf0b91fbfd7559bdb2fc489e1b7b5d4e8e936bccf5c385de07b1ccc6ee2edeee73b345f7a75a6a6a80f3b9acfe5eac9cc46bb66ff1c83680b1425a8819dd0e1db0e140ce96f5c847277f06c44a19ff455c9ed56524367911d034a0ceae93803a75018a0d16ba01b05129e12ad4a9fa9d927eeca155b86e2e1de58a69d786aeecf454860936e1dd1e48c2d4b0b35e75feed3688f386c0c0d30a4844b69454edbc051c19a71f6c725ebd987ee5e3bb6bf33ac969a6f7570dbbef9d2d282695604c2557d44ac71ca6ea744e4caf454c267c03ce7b3e4748922fd35f871acffff32d938a63f52cbb455743508609caeba54046c23066a0dee7e85e894d4856f1d2d251e5f162da92c11270e97208f9c6431cf5cfb314429ad23089d4e0b214fddc37c99fb827f62baa193e7301b68d402296e36b6f9da094654eaa7c97528937d0a6b79b37c51bb04e1dd10e958c6532fb30d8d7720a176aec90113c5b0566723b87799f7c9ab2a5efc9380fc7e66250a2dbc609ca8eaafc6a1d66f960ced9fdfd98387385be8169aab392c3e7f2d9d2a65c139f2675298b5786b291f70134a6a93d4a95087440c4d7531728cbbb8c7804d1ff84e4f83b6e5163c54cf9be689e0269c5e84b9f0cc09ef4fc56127fe8eaffba8b289914c46f1f0f6471500618f2bcd1935aaeec93fcac803bf168525d8f331fc905d43dd850cc9384c52d3d3bd3347b7dcf732c6b93bfdfe2fb6adfe47495f2c9abb2400da35ecf0f22a051bfc3190d9759dfa1e31d33bf1a5c506b68a06e6a96c31a35a4cb1cb477f5bcae0c9c2daa6f4923fe724d0e258ad8bd93536c28a683f46171f41604c46fd1b5f265c0a5ca3c69d3707f70289f8c5adb7680c3c1ca1ae56c715e3883f67a04d5b514413f168f0c0172e81467eb101fa65e2d859ac203eee27687b7e95cf6ed4c01cfe8f0563e546ebc6bf2d27f05b856421b34eb05db20fa2cabbad5a888b7f67a4f0db37ad28991fab33c1ea28da677cd67633c95e7b189a1577beebcda86bfe90696d6f30e1231cff5a28d67d1392104658df1aa081b4e34ac54d0b7c980a7fda64b4c393be3acf4a94aaf892b02aa10f9a6c76f45e7766a84794fae7d1023907445c0ba4a9ef6795cb48ed21d5cd1e69ee5401ddc139727ea764c071ea177206b5bcd01f5fab947f0ea236005fdff8799b1dd736ca0afc3dc59356cafd7201484253e7a8c75563c03b52875aee2d9afb9a9dc9b99ef7e150b51a1b1736c0cf0745cfa8a69d20c629c0851c16a7cbb63f636d72282ffa9a2064e631168a8722f96fe2b515e3bb4fd27d5d5bb6a8c7ab233cb18c82eb15f85275782e4bb61bdbcb557bb64a457baacd29a840eb74f9d59caf2e97a839d183cf61d59859ced7550cb65fc75086c700b0b022e817fc17899bbacf2ea9334885b5b4c2840f9c93b56aa0eca3b3f10908ff984a8e7df953c3476ab1c4bbd1fdce863faad74d625c113aefc108c589187822b226e4b048f900b7a73ff4ce3e3b2bbe87cc3f3446e62e9d85bb7d3788aff2b2397f788f887f4d5af9e7a9706c9379197bc7da726323b3b5ace2d5a42e0cc1b579c39186719b70588191807263eb664df628538974f349873d3b774f4799162333f11bb0ec3d87490e3c7914e8307b12eb9bcc9b7272ac7ff23e0476ca6fd1bef1473ede9253bc59bbea4af45bfaca9142b9a448c1f7fdf72d99654320121def54ff60e3e97d73e807621d64910c918e55591ff128d05b19a09097886840f01505d086aa4424ca2d666270063eae3f7c2f45e256eccc24882ab02303f01f1f44d2dcc2ef8500b568a9514a65c393d3b49ce2c309ed50f8b412925efd54f198f24819d3a1a4ef32877eb91f83de132defe19df48d2c47896a251670d5e15b3a75d76e4952c6672c877c905bfefc6bfab80f44ec008a0849a20fbd8b57bb3bee1dc4646a9a9d14234e2213d7241b94a5095a74bb6288ba92b4a49d462a51cb713196e34a2946835d27eb3f093878ca17cd88046305d85e343cf5ee4bc8b07caf89b511ac2c7b6afc479dd974de71c69da75248122c40a39c0ebd93930259cfbb05f3da0482766ce38894f743044b0172d3097016a7a4a874c9b7a018ba8567266213617fc7bcdf0fbe7712c8b783027164fb36f70121671e2a002b8853b18e80acd97b0c8b1e97ef6139b7330e19e87184bcf12878fb60dc1ad45fab8fd17e60fd6cedce47f3c2fda7e2aa3a98cee8c10ad7e0739288f9fbf8e73609965aded3de02d9a5e0a4b5e3442943cfb42e7700ef486b6de5e67bc1dd7420544d08055b83028dc2d5644d4fa463d4796d4579b21dc89ba1dce6ae5f131f2ae9604c83b767303f25045b997239f4996b84657d8a090dd617910f6520d2e3587681e86b7c513d0083fb7515b93e24af6eb85c39962b519f841f402f10a92a637d92db437c177af3ce83c7b0fc2d903e15f6fdc01db12e47538985cff420c40c468aad5134a6c42520f2d53be182f620c4f0eb008a020de00ce23a694f01fc8b99931754c162bc3a058964ddc0da144b2fe44e8c2fc3667dc3de830c8f1cfaaefa532037c7c6842dd501f67f58d38cf1b43c9c730cb6568cdef7185edc9e487a3292e9cefdc6eb6e9ab7c75327525b573c48348a5af323f52092bcd93e0df45c57bfd33dbbd3cc0b4af2e6abe46b2ebe8627e0dbb9f875c587b0365d016236b2c1ce5eee7c0a27ac4d56bc1935dddc2eaeb7836a73a8f524cc515be4f39750757f5cdfaff361674728ddf83bfcad733f5762fdd3237b9619110e03cec7c8fbaff719f43a575a9fcc2a2133737d32cd01979937805cd68c2656574e5a75a0cae66877c27ef1a49478609a0cd2f7ef5fdd34bf44b52eccab372b09511978e77141e9857d9a8a3f23aa0c785d36a0ecdb616a1b59b50c13bace66562cf0dc7e7db75d89a4098213ad7b004a3b769514143da34564931ad1369ac589ba6b39008395ac49a3b2d52027d6448bc6281d53b11121b5a55b23f90dd26fbc2ee58d278dd3bafdd6c537247e20703f2a9c3a77c5376a719844c278c4f4843653b2b6c8caca4e67a641d926d6441d8b732404e41c714b90b71fe953eaab3ec650a8022d13d5b4f99657488672ab1571073f292ceb1039adc3d08f3bccc52d0f59ba0960cdd78c5f784966260958fe754b53632b9d651d4c93b6481ff6419910df82868c6da661e41cfef79d15b12ab1e0b0947a4a266addf54c77ff7aac09700f3db5db37c66f1d2ac1065bcd2f32a01f0a579d86d00a45cf03c5ebdea7c95c977ddfcb505904455ed5cc771779522e17292e7cbc93ae5b49b1baa05af0f4860a3f9759105ac840a69939def6678daab5abfe3f214886975a2dc4d30024b88ee5153a09ef4aa4491a66bdd033036bd499efbf9172bdb80979f6989da231fef34bb9b92516cf9a8ab9601b4696a9f67aa5bc8643ba8f06daeaa3083fa3a53b25ea4fb24d5e4f14256fb4e6d4b285530619780a6d84502df983e14a7c7b934dc24a454d2d8932c00ceb8fb45b4707b813bb4e25382f53ff6d3b2231ebfb811924d25cb5a9de6f336c2b1fb07fcc33a8452a155062ab0c6de55e9097ecc1e20276a6e457e4ffc9734a7de8bddf469389f1abfbdb290a9f395cf04e3cac74de2d366ee6c3434d8df9fe80165e55a7f8d8fcc014a09cdcf7e23bd5bbac589d7dd090889cc9e963250b70ca3b564f18cb9b0168f21ee736550a1cf5c565d5162160deb42e836f811ade0431e46ce88d0cad05b59602157b4955fdfe168a68aea96988c5766e3d58d0376c02fc0a3618b28c3a69e0ddcd52ca04ff1dc44151d16c23b0e5eebd19d966c8ba9dbfc33005e831015df7a3635e8004b97083ade4a7223181eba69f98313f4df4cebb15b8acfbd2686e74bd0254e3b46841adf8794fcb4e1bc67206e0026dcb95bf14591830091c8c48d730c21b2a0ffa8c1463ab2afaf9f8fd3c3274386005f43c97170a97d75319b5d00133052967372b0d147aa473a2e3bbb56ca8f086fea1966664460563537889d20260b85aca9da4d83654a73109b87f56911e434edbff2acd48c209c83fc1511d07040fde02f0cd423ad0fb224b9a4f1ecd56bd956224de0c21230448d18fe91bcc1a4f8b609d07f7c03b90466934739561526e8f9eb4c3ca8d91e1f0c770b1f3f31ac0f72b711dcdac65371d38867a0149fe182b0aab98579347b96f06e95cd42dee526ffe12e86292d364ce772626880182bdf2d91f203e63e0f802f6db71ab481245f938c7eb5758b7faabef2e2217a9d3c1ff7e6dc86ce49f134635f3c85cb5c16f0948a648c753fcbd7b3ef6cc0b149f113f4f6faf72e926207df1136107a9c6c4566989e5871392add5a99d5f02fd8a65c53642c6df686b726c875e21d0ed9bfcfff439d3d8425fc71e9825d54f7be0cffbc6f5ad6557f2884f8633cddfb94c1aa1242a9fc2ba0aa41c4ed6a5a8f206cd831870d97b2171647523f7961a47d7e5e6e252631aa8a601317f4076ac5f19983989e0b3665d6"}, {0x20, 0xff, 0x800, "b646070132b0fc291400d7"}], 0x1210, 0x8040}, 0x4000)
write$tun(r3, &(0x7f0000d0b000-0x41f)=@hdr={0x0, 0x0, 0x0, 0x0, 0x1ff, 0x0, @ipv4={{0x5, 0x4, 0x0, 0x0, 0x415, 0x0, 0x0, 0x0, 0x11, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, @broadcast=0xffffffff, {[]}}, @dccp={{0x0, 0x0, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, "b31d90", 0x0, "91b903"}, "500e4156bafc36f82a4b504b036ac54c641b052b4bd37bbd64c835a43ff64c517d4be4bd09fd51dba95d4fe44d8faa82b23a5cc4658c9fedeef7256b40604ee4f878d9d3c3999e0312f06d8aedcd5039894a18126498dcc964dd5a402c417a1cc798189d285118d98e9f7ae8fc0ec9b74efbd90cd7d544765d2df18be50c1323476820af79bad0e65d1c48e0ca8685ab6e775d350961652c7a7c9f2918c9444a307a6b8fbc093f56829fa579723c6ecef716d5085439b3a070b638ce690c66144c8e0314250fa36a5a9113de159c9195db60cb56dc158ea825a7c56dcf9ab155f076e53afec5a4155269dd56fb99aaf6044ec72e8745f18929fd1bce7c52bfa1e099f237de1f32f43bd6ee103b9341a3eb484170637324bacee722c7625288463e69dc1cfb1162ece3f1b48eb95125e52cbf498aa2ae4f949a4f21bff523f3e29cb058647b17895e3901ba4d7750b0544537e77dc19f18b4d2ce1800e06596f84c4de7aaf4338810d040ed19ce89619e475824c0ecbce568fad0c59374a709ae626a706904f394a7874cbedb022d8397bbe406318dd5f5e81eb4fd15d7f49cbd4f9a871b56db62211dd7bb416e976aa57d7d5fd34f25e9f881dbab0466e9ec68c15b642b0057050564c6950b2ad79fcd5c81748252cf80f1403313664b1e54a333c90937f55c002e89304be9236ba919e36b677a2f4f7a495cc51bac62462d2c0f71328f7975f9ebb64f14094c1098343cc26e30e6a1e9b46b5df39a89ff2a44950e202bbddf866c8dbd834dee240dd2b10b3b0e0a47c8f1a810a8be5a71f7e68621fe0928ae2c23b2f3d01b01a94184217f467adee09c9e6a22ba53c634620162868da27af8974300231a1c6ba6b1fb145278327d6ff0edd905e52d0f1adbdfe92c152ebe3e988ec64ab512231e2abce8bf2ed6f6a4e1829fadb8ff3c51117b1094b8c9cb2cd807d88b3eeae3272d250868acebb332a5c6fe7717e782e9b3323d961b872568fe7798fbc4a81230a13b639a673c0044ce623355527a183efbe6367c30ee3d22b5de0e8913deedd0cac21a90fe13995a887baa295a64b367b6da934ffb23836fa6fce9023e8ee9d0152542e57a86c92d1569a1ef1e7d15b325e5c340d6933f890c43467f3b09371a9505a46064fc404c87ac13522b52e89f7afd49974539d3af5d1a5b8567a3570568fc344d4f854e1a385620cec24c6ec14a221d14b7259a11d5d7745933f6e608d74e49a4f7f1159eb2662a22ea7c6ef3ecf064f06e7443df5bd4de8e949e7e3500079e33b6b7dd0dd333dde809ab361601c66c4023aaee80021a8459fa2f4feca656b2f7117969e3e0abd5f18c1f507a207972ef12a11e3c437507ec91e571e487fa8a625608430bd0f9485d8e384f1cde04a6d4046c2f95ec56aff13155a79bd5b6cb"}}}, 0x41f)
socket$inet(0x2, 0x4, 0x101)
2017/12/15 11:53:26 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80040040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
sync_file_range(r0, 0x0, 0x8329, 0x0)
openat$kvm(0xffffffffffffff9c, &(0x7f0000f1f000-0x9)="2f6465762f6b766d00", 0x0, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xf5a000)=nil, 0xf5a000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$inet6(0xa, 0x6, 0x0)
mmap(&(0x7f0000f5a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = perf_event_open(&(0x7f0000e0e000-0x78)={0x20, 0x78, 0xe3, 0x8b8d, 0x0, 0x0, 0x0, 0x2, 0x0, 0xfffffffffffffffc, 0x65d7, 0x5, 0x0, 0x6, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x40000000000, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = openat$sequencer2(0xffffffffffffff9c, &(0x7f000046c000-0x10)="2f6465762f73657175656e6365723200", 0x2, 0x0)
ioctl$KVM_REINJECT_CONTROL(r2, 0xae71, &(0x7f00008df000)={0x1f, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r3 = syz_open_dev$tun(&(0x7f00005ab000)="2f6465762f6e65742f74756e00", 0x0, 0x40200)
getresuid(&(0x7f000097c000)=0x0, &(0x7f000070a000)=<r4=>0x0, &(0x7f0000b56000-0x4)=0x0)
stat(&(0x7f0000030000-0x8)="2e2f66696c653000", &(0x7f0000374000)={0x0, 0x0, 0x0, 0x0, <r5=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
setresuid(r4, r5, 0x0)
socketpair$unix(0x1, 0x2, 0x0, &(0x7f000007d000-0x8)={<r6=>0xffffffffffffffff, <r7=>0xffffffffffffffff})
ioctl$int_in(r6, 0x5452, &(0x7f0000009000-0x8)=0x3f)
shutdown(r7, 0x1)
ioctl$PERF_EVENT_IOC_REFRESH(r1, 0x2402, 0x7fff)
ioctl$SIOCSIFHWADDR(r3, 0x8924, &(0x7f0000951000-0x28)={@common="726f7365300000000000000000000000", @ifru_addrs=@llc={0x1a, 0x19, 0x287, 0x3, 0x7, 0x80, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [0x0, 0x0]}})
ioctl$sock_ifreq(r7, 0x8921, &(0x7f00008bf000-0x28)={@common="626f6e64300000000000000000000000", @ifru_addrs=@llc={0x1a, 0x0, 0x2a67, 0x1, 0x4, 0x9, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [0x0, 0x0]}})
r8 = getpgrp(0xffffffffffffffff)
r9 = syz_open_procfs(r8, &(0x7f0000000000)="636d646c696e6500")
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_bt_cmtp_CMTPGETCONNINFO(r9, 0x800443d3, &(0x7f0000002000)={{0x6, 0x1200000000000000, 0x100000001, 0xe171, 0x200, 0xc74}, 0xff, 0x400, 0x7ff})
openat$ptmx(0xffffffffffffff9c, &(0x7f0000eb4000-0xa)="2f6465762f70746d7800", 0x2800, 0x0)
read$eventfd(r9, &(0x7f0000001000-0x8)=0x0, 0x8)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x0, 0xfffffffffffffffc)
setsockopt$sock_int(r0, 0x1, 0xf, &(0x7f0000e87000-0x4)=0x40000000000003fe, 0x4)
bind$inet6(r0, &(0x7f0000895000-0x1c)={0xa, 0x0, 0x6, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x400}, 0x1c)
sendto$inet6(r0, &(0x7f00008c8000)="be4b", 0x2, 0xfffffefffffffffe, &(0x7f0000ac6000)={0xa, 0x0, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x0}, 0x1c)
setsockopt$SO_BINDTODEVICE(r0, 0x1, 0x19, &(0x7f0000d9f000-0x10)=@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, 0x10)
sendmsg(r0, &(0x7f0000a45000)={&(0x7f0000a86000)=@hci={0x1f, 0x0, 0x0}, 0x6, &(0x7f00004fb000-0x10)=[{&(0x7f0000e2c000)="cb1be040c3d5dbda34d730af6977e2d78b65c332a4d6c95760c6ec15062d317091e0cde8723ac9448b33eaed01bc1e0c938f8969211bf49568d9bd5016a7beae5b366febd105711a1a8d28050bd85e4b1dcb640842c7d9601415747ed075ab7d24dc2c2162700afb3f4a5e191331742ed06ce9e4947d42efb71d55c55b4110350aa0fce360f7be9761e12bd6119ab5d2531bbf66f50b58857821c6d4f91a7d1dc4b6bddba3daf7f7f7db523b480bec245d1aec6bd76903133237759b43f1eaacb67c0505e71dc8a6cd833c20f581502c21109a6662e7f40ac4f6c1a1b948c6983ab4e48780f71c62deeca6bc174c042bb87efbcafead1beaec9f19aef5e7227457e64947748d98e0cae2cd8cacaa7e8dace890df8117dd8918ea8edbb769e7bcaefa51a743636f7907ea395cc184cb391bb37d4916e550e166956025a41172f3bc3b23a3ad0fbecc75b501051615e44d3e2b7d02f5b13cd99c0ebb3d1e6d8c2c2fae041c10be62875b5f6e8c31f8a850bf21aa0a4c1d29ce7201bedeb4840ee35210ae23c3c08d9d31dfcf8b080eab60579f92fdf733e47ecf96691cc9e9db14ecb06a063a3717636e19c1853a4b1eeb1ca44a685efbff7ec45ee6fe2742cf00ee6e32658575020035f605c7952b9d0b992f8ebca3d84c1fcd019b76b2c2ca13155e8aa902e6c1670287a01d68850947a16d1e4ff853dda96910b8886497a51f3db16251f8ea6555f03df4a25b85ef1d53e192762f078211e80989322c56f06e8e35046c4424d1538e054b3281bc8fdf9d22f7082d49964ca1904b7bd4e532b122a584e6c3cedd553b90311ee28fe9fd21455bf793f587081b740e7b504409b0691f6c40d8d08c71b0cdbd25b500441892f3e1a8f2d915c34e477574b963693a318d0a1d441562b4025ceebf9bd391a273db7ad03eb756f576ee30e532c7bd0697c68a6302694dff0bf79c74f42834f8df50b8adce13972b79e39892fbe6c843c748c5add868f73ec92378f9309b71a06cd852c6e2c864b91e8bbb6009a560a7ab9513efb4626fae00f8d7ad1168941d2ed5c47fb55b6b3989c85b9938e6a3cdfd5e49c129f04ad585bb4c009350bc023a291c39bafcfd978d65d838934631a69a59e67993f8ad4f94242a7fb47d83127f289c6753382e954950a6047a4855c99381a9780049ac7438474c62c8d810ea301e6f8294dfb9caf4553f2606050440e36a8dd0852cd652ebe801bb26ced1b698f9ffee57b559a45b3fa8758e9cbdf213e39a240c62531dad87a336f8849c85eeaed6210395f7c849628293d10dc74edd967f27e0fc84cbab77f446fa1615fc3214c980143f42ea0dc735bae1815464a7e36dc96b309bf28be770c98ba4378864725211cb01376a4087022c7e3e7fc3b01bfb158670659599ed16c46fb406b7463d920a2299e03f456a14a197ec7c81ce99dbffb7ccbeda534b4e96e556d1bf7148c7a7bd296e0f336bba73426351aa716c8fa1afbdfc338d932d6e633151cad629168952e0177a50309bdc417e90987109d29f4d159f301dea6e0f8a8490f637b2d0a1ccdef31585f0cfb1fa6df84e9c926f686cf934aa07e9f79bacf623572175e0bcd7073dbf5b741a2d12173d5fec9d6643122909e8aaa7712a311e7b5a140becc76da2aef4aef803781c2b36be2a72959af0e0ea32597b816422ba0be893388e121d67059f3fbaf3458a04c67e1b9e55a150a1b0f2b8caeceabb2699e757888c60a381f3e939005b292df5df68166f8f97272db639c62f479d000fe0f29f2aeb39cddc66dc84cad2488c2cba9e7ed1a195747098ec37e1df09c9cce45cd28646a9124ff837beebdd497cad99980837f59f10b5673732ac64ea0fb403bd83c332726a13771abe49f43614c4d8fd60e919caebc18e187328ddac44d69cbf6d368987fab84f28f97884a7f52e518d558073fa9117b378d0d1f06302b6703378b8cc2a646a91c20fe0218be1de9cbdb008ef73b58556d2e485f3cfaa9529bd888804ba7b40bf53", 0x598}], 0x1, &(0x7f00008f9000)=[], 0x0, 0x4040010}, 0x200007fd)
r1 = syz_open_dev$tun(&(0x7f0000495000)="2f6465762f6e65742f74756e00", 0x0, 0x0)
ioctl$TUNSETIFF(r1, 0x400454ca, &(0x7f0000fbc000)={@common="7465716c300000000000000000000000", @ifru_data=&(0x7f00002a4000-0x20)="8ba4739100e341972a31cc2b9215437f60675fac8b3a7701d2cbdf094dd5781e"})
mmap(&(0x7f0000fbd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x5, 0x0, &(0x7f0000fbe000-0x8)={<r2=>0xffffffffffffffff, <r3=>0xffffffffffffffff})
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x50, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x8000000)
setsockopt$SO_ATTACH_FILTER(r3, 0x1, 0x1a, &(0x7f0000aba000-0x10)={0x2, &(0x7f0000fbd000-0x10)=[{0x20, 0x0, 0x800, 0xffffffffffffe00c}, {0x6, 0xffffffff, 0x400, 0xfff}]}, 0x10)
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = dup2(r3, r1)
fcntl$setown(r2, 0x8, 0x0)
mmap(&(0x7f0000f52000/0x3000)=nil, 0x3000, 0x2000001, 0x20150, r3, 0x0)
mmap(&(0x7f0000c9b000/0x13000)=nil, 0x13000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendto$unix(r2, &(0x7f000014a000-0x4a)="f55351cee2a9788585a49148aa321f2af577b2d4e9cd4311dcd90f1ae714c1b22824aa4f789790800bae56692652e3311efee5715e1627431b29bfb5d7ec0b2b7b00885fac050c08c700", 0x4a, 0x4000000, &(0x7f0000001000-0x8)=@abs={0x1, 0x0, 0x0}, 0x8)
openat$cuse(0xffffffffffffff9c, &(0x7f0000098000-0xa)="2f6465762f6375736500", 0x4200, 0x0)
sendmsg$nfc_llcp(r4, &(0x7f0000014000)={&(0x7f0000003000-0x60)={0x27, 0x5, 0x3, 0x7, 0x3, 0xfffffffffffffffe, "55689d844febc2dfd6ff1acb5afea2fdb39b64fa44c153ab9feda9d25e0c25e5b4b8778bd7d08f3b257f2203bf654c9f21f54f59de892028d8622c00630748", 0xd346}, 0x60, &(0x7f0000026000)=[{&(0x7f000000f000-0x94)="12dc3adb5cdf55fb546620c25857683ee59494c3be37cf739e979dc8d1d042625d3f5c86f6c54fcd08cfd165e44c358168e3fcc6d6ac47392b84c3627efb17191d49ff2e485333bec578af109863a03eb7e1949dd721b76d4d3a002fb6c2a724742d9fac70ebc1113fc62e3736cdecec3eccb1c3f8a1ab3c19ba6fca697fc33f0a50fdb474300128bb62c840f9a2532349f5883b", 0x94}, {&(0x7f000002e000)="b35f0001000000000000ecda740f544f2d4f6107000000000000005dbeb777547e33311723a3736d0e60f783a28ad036020000005e9132d00d3c7fa23076c176a4d88554f674010012b79f11a77b74e512b75e80effc7a8ae0670eaf76d376dcb7f211154bd47b8aa983d27080fcec6c", 0x70}], 0x2, &(0x7f000002e000)={0x1010, 0x1, 0x1, "14caa741c7cbda8c74c2fc1fceb1cec5d7e047d63d2d690c409580e09b2f0c34160ab645518dd8f46b3427bf2553234739177321d0c85c1ef232c50af6a0cae3914a99ccecfcacf6038cb31c9e6dca270a282671f1ee8c807cab80414e571901f57c194a4b6a1af5a175557223ad50d50e871e041bb75c824184e87fb670e0f0ca766056309114bf1687d9991487a0e94e320b9559868fdec67e7cecb5f9dfa7c23694e084f14fcc8b26f342d472ebfe38723fee6d5fddb60cbff8d1f1d499aaafdee1c137f20422ec803af838fa5333f60744f2f60b554da5b9e5ae2e3d0d4b5429cb52747f2f023798f0bc73a86b0278e0ad0eb83f3c842f432ae3272ebfbe335fd3ef1baaed3718917b4d9925956ea9c06a94ea992ae6b15977b59659899f551205c7f941eccf58e0b7762ff40e96543ee3187251f1e03d9608b0ed5d81e6aa8add11473b5c6ffb2c0e21ea4b9b1f4ab10df124543b928a975072546ee069bea8f0f7413451eabfd83277069d2522d1c7e2fd9781eb83d99e3c2c1e6be77b59d1e99cff32d179cb41b331d2ea2fa6687987f9b9d0cfcba0aa24b1bbccf4ed234e62c15700aa030b652becd8760a1f6ef16dcbad70dd8e993deaece37fae04b8a83da86d309fe80709736d01f2fc550c771eda648b154e1774bca92ca5e29ea383baa30c0974e7fd9276959a08b21d9fa4cd1bb36862d2bc2a93eefbd167227acd5ee03fd065dff79d525ddbabd04a8e699c4006380c7f97e89eb7cc3c560b2f1fed42193e909f87ba6b2e54a80105133a24bd267931e93fe3c01e8460a48469cb1b9b2a83673db4b820b220c0cd02e29a8cbca37fb0f037ad61397297a1b0e9f1f2d4bdfee1af5487b71e242233b749067e2e24aa41927f40b9cda713d23b2c870d338b6f7657b7005d627f42b32193ccf3ba645c50c4ac914ca9d29dcec0f0014674f565c6d35854c7c31e85f3ff1549c053b0e48026af8ca77943f177009b873bb835c8667f03eeaf0e9a3454bc8cd6ac5860cab2e06def882adee2e2c7cc6ccd4e6b794a2cd5f00ed030cc8f31d0ae18132a9ce83a66797f2b8e79b074533484520c0334eef8b06c6760e6cf9f95b9bbcc401d86719eef6e443175557f28702bd4320a5bf9ffd2e1d7b21f6f4d127312e44e6f8c35586d68996c62f3552edf8c993c557c68822f9f34c6ef621d6417d9d4da67079680df9c48e0e07e0161b589a86691b7c881b2fafb5e07054b715385dd6ee8e59309cb3c4e77adc288ca4fcd77701079997236b6e9c2b5a9267a0fa07f857d4fb3edc0b04bbf00285eac70dd3af5c1cb4cf1bab336f56dbc1872fef36bc930f8506ba8c61b31ffeeb2a70640018802ce40ffe103ae17681348c87e85d339214b3f1e3f1ace7a81b0ad8e7673ac8a31447e2220215b150d884b415466871e3b44ead7faa1c99c25b9b28033706f13d49ff39f916557a299981e65c1ff32c3ea91ce2be39c50e60feb8847d26128fce0068d7b125d70362eca61f7464a905f4858726ebb7b0d7d95bd12d0cc171eeec25689c8cf0302a21e7f93fafbfa40019f273893151e9b052e12ddeac3f819a44046fe34d33c78f3b12a0d6bfef68fe073104fb1206ac737b413356a5e969f1cfe876d4d74fa90f679b2d5c3ef0cf4f1a1fab97d33553b49673a13f296abca02ecba046c0e72d10b8d020bf9382c81baa6b202f953f425cd961ea60965d3b16aaae04dd823c7ea3e65b638b8253465abc9944e80b8afabc1e9a440cfd5b21043b07803407ca19a102da2437a8230d808dbf6f00f6ecaf3f9e3ce794d88c85bede50f9d3e9ebdc04f9025cffc4087215394fb4e80470ba948199a34a5a17934fa296a95bcdaf136853bcc775ef42bc1f3afc1737d043d3b5319f596cec594b609a9752e637c8cabd90cc68ec1e8df41bbd6fcbc0247fa927c5392d3c77f4e0744368d20e8ff7c7f82d5cda896a58f39362ab1e5eea2176eed4830537e96d3299a3b6d102192f81de6a70225a97d43e40ea834dfdab50e66f3eacee1b4508849496d0a7ce81c671c2aac849f2acc6a85320a833be4095752b18a8e64c083e09313726f34b5f34e522dd3e28ffa8f424199503ee91914713f9800ee8187869da4762563078437a171606b101f4f7055378d936365c3f1c7619b398c4fb358bd2599d327e8abc3a5bf61b5fb407741f3928ce5357a4605b9eebf3e42cdd53d410f2322d4fa3084f522125b6263b32a75b355466988d5d7a96bb735e85bedd2a0b5f3372ee3949f605249db6537eb344cb3f24e944c28044629d193bf46c13158f3165aca9c4e689e9d2b1571f894c6b111f2d604b8038550628f6e5d157bf7ce8c193cb82df84c134e9cb7a92899c9273371f3aedbcc9c9f75b2a4bad2f1c09c31a66532fcaedeb8b185737dc9dcaf908ae871a59d9107b86c4a3d896e6323e50ec57909b70e21814a04db98f963b612c10724c120541fba860740084dee912e5f4020bd8b5e13a568b84bd6b170947a8e4670dee03ad972ebd99b7e02b5fa3b58244897d07435c2d3ee9d448588e0da78cc4cd6203b9fe972567f5c05a64af25e3d6d320e9e0df0f7547676fbf30aa2edd8b87055b3df2fb60bb79b3239653bb863cd4aaa047772ba995a7863dd1eaaa991e9273e515e9259351755b3bfb490399801ebd2ebe6c595b9f762bb874853ac8811a94be35912e6b7c64a16990efaac3b5c6bc193f5bbd59e5be5bc09a6b9c13cdab0363135876668924e78ed2e7f30dce72111585848798279327bbbd1025708a3223543a9703504174644482bb6d4c076928e9d0d873a4117e52014f25c1c39775ef85a258f6f93342e169036dfadfd7434e2b34c3da12e0966b1ca31753d0774ff98416d7a9953872c8a01f9dec4fb50ecc7fda1f69d985d3aa9ce20806d62a8837cdacb88735e7d0205086973edea3b808b148af21646380f5795e88c8bae7b564b230f4d88f842f7fe8290af19123bbff58d555190221bd6eba28e9dc84bc7330d9bccd80df426aa2cbb9b43447cb9d2d201f61df30f3158cdf4b3461c1ece7c31d8a5d584d3fcc438f9c85876ce5c0cd9cfd87b25421929fd410fc150f3a5e540993d61730b86b7d38eaa5cacf86abd44d59188d042cdc939ac39e1717e71344a169e811a0c41bff4ad13c419b2d23f709ee1469c4a7510db0bfa3ca8abc42f9613ee7016a89f2d6117e27f7659f2a457446d742b263d5dc8dfb76951a0ac4f017f53c2ef45e8dc577266631ca23a70ae76f91fff0cd05009399283c636a1ee7eceb50e40db22cc9dcdb32e46e66c5f919d5b168c4ff67765bc1b2a7a11ab5bd4abcf11fa574f85fde8c347ccab6c07b55fc97805d4cef36892fd1ff58af11bf9cfff402a2ba01d8ce6dde6c210e397a8435d9fc7ab38ab320c9513109052d90e72ea6974736b37fe18e612838950dc1a3ec89c29fa49f7b7429bb6302f3fb2bfb9fe8f87dcde4c62627cc7251e3d4feab80bf7face83ea95f13953ee9620a80fa367eabee7988189ed3c727a7369441f30db343b116ffd463d01c04c2a5b1e23cab0c8fd62948caae906a778051685c28bcfc40e728e5b3707d0a3bb510928d58ccbd4dcbe75b54af65fe84639c1bda75ac7cc44687864972875be6bbfc56fb458e72e231752159934f067433dc8308b8c56f05058c142e09029cf68bd4564b9b72ccba9c17e0d089b9cc928ef468e0f21e8704004bd01502e5d014f40ab054822d962cb8d0058f56170c11b4677b8189bc59dd988664aecac674b496a935f7173ccd0fe44ad3eb49b8082fd4b10deee986400afac82c2cce7a472c0ffe09c00298b51956bf2487947f2b5c86cee343f140a8fb1a2b3caeff1004512ec524aebb79018eb2178afa530357ed0a768f2a905c05bf9ef4065753c34599148ef9b1cc4055f0837d5a8f60f95788ea93735edfc45d50a178c92cdb9ab569a1deb571e00ec43cf952a62eae1647d9c250e4efd67149c17aa87af6283d8d166b76d0bd346dce1d986286d12abed8f703eff350d959f837999272e2093709912076c5f4479fc6d98ef852259c3109f295a619ca9272b58f2e71f46edbf04ee69d43e470d62e4d7b629e01574b79179a38ab15a7b4141d96e9cdd099288e437f8bc35f587cea90578fb5403179fdbad31b6c925fccd8a5920f5bc12fbd0c6fb94a9a7e589bdaa5e58ff327fab902f711e2d0695fbc9a29125635f5ada7666e83fba87e8033f5535ba52c040b1cdd8c255f684fa8e485658c324ccabbb3b43450f23807664936e34cf65273f7d5c4fb8e3e22509d9e5612e5a522e8cea92c5c6a7cd5cf6eeec8ccdb2e964eef54a80d075d76dd50f2af7e711527fbf5424345213bccd1ef16552d284af2b109d9ef65244d0fb8c3caf7a17f249846fab136b3abacb5c2300be5d9de50e26d218263be99e298d2fea133e0be0274bbc292a67cbf03283372975fc0716679c693d4ca74b272b92e6a1d52f28402f8d773eea75fd3968f965b2627065f0c1b2773d83ef2875c0edc181ddbef95d393d3594416f446a771b83dc2998341b9e02c4ae9799efeada37b607712eea62160082ae08917fb2ca324eb8d52b6e1e26bc55bc4b38812fb772a083c8dd2ebd209dacec1818212ce955f56e5a19559d716381463cbe409020016f0fc8941ee15128f32622cf10b7c37e25336537f69a4c9aa8d4dd478e3296029c0bf97b3d6f66b353e0f58f93bdc722588ca043e2088a0125ef8aa205f97baf7723b2c04cc2c415a14dd2f8879a336b1851410e824ec7f17a7f408bfae3f1014a1f469468b471a0f48bc37dd5068a80ac2fd7570da10a8a369e8ea703f1ff81809f3e1114b29e17feec151d0e029436662d7eb609af699da0232c79e53c399e07fb51e5eaff18efd20bae1c0230e120313a7e4a57e9e25b97f8a4e1989ecc14c4ab07818a1b3ae5ef84b38502c429224518eb49e413422b7439408235096325ae90faae9a0bfc2f4fdda183303e64acfa6f2ccd55291224b44cc8c54ad8f50f52c3f8b3394a59845e510c3752e938068a2cb927ed1d14d1d3845693ed3dbe597aeed5f75d59faa6741f3bc58748ba7e05db612f36902fa66420b8b7e58941c2b1a0e3f80607d535bd6032cfb2287af2130a92e790b2ea0393fd9c8adb69c03c45fdb27069d57d54dc0d440733c83fe8ef36ab1346521960953e0c94f2ad746090d626be685f20c9de5ad2e0bac0bf1e72e5f11195c4ddafb59de26861dffe207215a895a95233d848b48e6633b1985c9ec559eecbf826ea08f94698bb2bbd110a45798a2b7e349f85c15f70d2cb22033d39a70f98f2b7a3223c2cfeac2d5610c31a48148914a1ba6a5eaf3dbc9e03c9d71101609f5bbd746dd2cdc9f8f12c252ed72d262b8f6747b9f6bb0c2fc1f379eb7b5b2cced84d1e32f5eafb222c21ee0dfc5aa489031e967fdc15d546b86f0d114f1a441583164f62c058bdf43ebb5b02cdb990ed562edc937c39dae4cedf37310bba3995786a567bfa1e7260d229e902dc9fb1c9e2dadd2ab6ccac429ee8e56fab34a90ab56f2628b954d339c9cadcf3e9b1e982ac066c408ace9f52bad0cced301909c7f36145b868fdd7d9366f364225a63ed45ad97efc87956a03954a1672b4242be47043ae578940894924b2e27be459c2a33d981a76cb771c9f45ac6a40e19c862b35086a3d13696362d24ca2a27c4bbbc13609b69038593b014064bc3d42d051c4f2b142de96d7947af53c0ac529f7eb5fb74b907f1ceed0f9da115e60ad22840f0eebfe3f5d"}, 0x1010, 0x1}, 0x1)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$ax25(r4, &(0x7f000042f000)={0x3, {"bf9425cb00000c"}, 0x200fffffff9}, 0x10)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendto(r3, &(0x7f000002b000-0xd8)="080400", 0x3, 0x800000, 0x0, 0x0)
2017/12/15 11:53:26 executing program 0:
mmap(&(0x7f0000000000/0xf73000)=nil, 0xf73000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x2, 0x0)
setsockopt$inet6_mtu(r0, 0x29, 0x17, &(0x7f0000f63000)=0x5, 0x4)
pipe(&(0x7f0000ca4000)={<r1=>0x0, <r2=>0x0})
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
accept4$inet(r2, &(0x7f0000f68000)={0x0, 0x0, @remote={0x0, 0x0, 0x0, 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000f73000)=0x10, 0x80006)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TCSETA(r1, 0x5402, &(0x7f0000f73000)={0x401, 0x5, 0x0, 0x629, 0x38, 0x0, 0x2, 0x61, 0x6, 0x4})
setsockopt$inet6_int(r0, 0x29, 0x19, &(0x7f0000516000-0x4)=0xb94, 0x4)
sendto$inet6(r0, &(0x7f0000f64000)="922501ea331b8a35776f5e1d91c11710fcd9c124f896e5442bd7880e33c98699fdbdda67a3173d16f6421c45fcd1c09fac71ec575beacd95ba63d3da66", 0x3d, 0x4004, &(0x7f0000f5b000-0x1c)={0xa, 0x2, 0x7, @loopback={0x0, 0x1}, 0xa}, 0x1c)
getsockopt$sock_buf(r0, 0x1, 0x1e, &(0x7f0000f69000-0x9e)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000f1a000)=0x9e)
connect$inet6(r0, &(0x7f0000b7d000-0x1c)={0xa, 0x1, 0x30, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10000000011b}, 0x1c)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$inet6(r1, &(0x7f0000f73000+0x84e)={0xa, 0x1, 0x20b4000000000000, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x3f}, 0x1c)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet_sctp(0x2, 0x5, 0x84, &(0x7f0000e4c000-0x8)={0xffffffffffffffff, <r3=>0xffffffffffffffff})
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_icmp_ICMP_FILTER(r0, 0x1, 0x1, &(0x7f0000f74000)={0x2}, 0x4)
getsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(r3, 0x84, 0xa, &(0x7f0000f66000)={0x20004, 0x2, 0x4, 0x6, 0x100000001, 0x100000000, 0xdabb, 0x1, <r4=>0x9}, &(0x7f000023b000)=0x20)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$EVIOCSABS3F(r2, 0x401845ff, &(0x7f0000f73000)={0x3ff, 0x6, 0x8, 0x100, 0x3, 0x6})
setsockopt$inet6_mtu(r0, 0x29, 0x17, &(0x7f00009ab000)=0x2, 0x4)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f76000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000f76000)={<r5=>0x0, 0x0})
mlock2(&(0x7f0000e3e000/0x2000)=nil, 0x2000, 0x1)
sendto$inet6(r0, &(0x7f0000426000)="d6cdddf6785b2010c70c0e53a7b8dc46fb08eb86a063c48af64531b6d0b5e54fc637a8ce449a0b9e9bc58337badcb8b3287366371ab8840cc0f3d5af77d601c926a964d38709a0155dc77d7f1db3dec18d2d3622d251666f5ee4723301548b798edf884d4ec51c76d0cc08d1a40051c9123b925e030e86296d2f292c596ebcd8548189ed3217ad11850252b4bf8d3586df05325e80ef836926eb2206588aa95d0374723daf2a574b8cbc080db80b5bb82cfda253f60f52303155726f41ed8eb9e8926f5e2471eefa9f3dbb87c97f8ca5d5ab2fe8e7b33258064b19f1fce68e2bd76173823280dde3ff0bdd43965a3224c4888751d958dbda5412d855c3104a56fc2dd2756cec6488513f1c72fc760e90cbbaeb031ce7e3969a1d7d941520e47963083f6804564c1be136ac8e10b64ebee48f6d9a719988633f001b611ed60a71b1a7a1b595be3ab1a5d876cf9a0d86e26c5dfc4ceb2963937ecbd0a7873500b85d115d88af3838ed2b9b4c1a5aaf8d546786b2172bed07527d72f5b5bb15c5cd7339089fec4154bbc0dc37b92c7c91af56880a3699f728d121082be998c8000a9f282b3c80cbb815a723dec3ef1c7db995e326b31f1cfdf714f46e31464d32d54539720910680b1034ee6af9cc574be349fa1d1cf7666b5715d392558f16cadbcc2cd0b67e5e80005959d3445de0be4798f7a1e3bce43abce01a36ec36e41c90028bec1fac8227c6665e82b821c50bf2dd1725bfd257ff9d0fcd9da635b4fcd3d12933401cc03fe108ac5b719ef6f2d6adc79eeb8dbfaf89487ba4e13fab495977668b9ee4b261627abe77094ba1411274b69e644482e3e4a9463a32146f0c5cb0495475a80c392a9f8c1f785f647bfcc14897fdeb74c32e335d511dd03ffe548b1055f7b2378ba31701a9b09273c8ee41d9702358714d15ae958cae8f2e46b858ba5c9240390d86989e88489c77898e37d54bfd8de73b17fa1a57e0177a950c981e3174783c93cdc31dc5133298164511d89875179792783f5d1bc36789309f65d3e85034a578f159688751e2c49daae0ff8b50a501c7a7eb7c5f2cce063ec1bc0b35500d132fc679e827eef7919d488da4dee22fffb3581bd8cdc3a6af7ef4844c754a31c1519fdaca546726c259d27e01111bf44e18462c229d57582d22ca38214ad06c6aa3af9425be3b3b72d00ee1feb764f7bf8cb57452133b1a96f73d40462b0b51a80b3523c5b936a92200d7179b4c705c8ca2d3481c21349844ddde0400b19c54388fa465dfeb61d41ffde3e3f9abc6913b9acba43362c8869ce47995e38f06e29222f3ee256526bc1511b215550747bba3cc8b516946107e9d2fe79f955efa36c5d567b24735b18fa5cffd924b355c61808f103fb8d28128f8658a7e197785b66c52525576174740f93886286f0981475c7699fa8552201ae3ce3cd20b3b0b1c5e166ecbca3f4f484bbfd4a5e2be556d0b0a44bae81a6e3c2a67e381ffaeef4b3b0fe74785d1991bf193c8eea1686db19c1867726d1fe37df19d26fe4eb78f79754e72a0ff66fa381675bac1d90406b5a62784caca11f51f5802d29ace1e64e71e86f213f70b35002688d4556605fe6351451a03c06ceeeaa5f6d1014adc68309c6dab7fa38ebf2b8a1b8ba6a3ec3e5c04c1d81f0ac02b0d1e7874496e978f78f29d15891b3dae69c8af582f3448d489c576cc3a28577a96c872c1fc69cbb053f4ce6b1770e1a674fa99f13037934a6ef9f408c4036506f08ef95a0de742e894ed23a611e96864f4f1e6a764ef3dd0f6048201e8e225a67587b19141850249ba55e30f3883ceee97a37205121d09c9f35776108922ab57cadd5758f2d656379100d9ce6280fb4d06527078bb1a75c686ddb44f45634939224c91f89bd7f29d12298e72cffabe02a81a9b7d26899f5d90401c3aefff2b340076d831c5f62a121ae56ca16df1b90987bca1907778b04e639a77a1cbe1bbb1e57f1a0c21cab036c0b4f020e4572792b0447874d31266d0b649e29acd1dfbe6ec4d5453acf17358a9ffb355fdde45fc9ddd2c5a7300d38e4f05a712689d5657446105ef9e5b409a7c94fb9a91f35e019a96a0895d48d9273cf6c7168839a57aeb51d99ef1e1d4e782fe9d5ae8af653925ee71dc53b9aed3232fb9c7d974b1ef01d96a7c8af4f61f6318f870264d09e1bc863ac6e748cdbded86e035797e934c8cc78b119b70183f8fc8be2857bed43afc99dbe9a32833b8b720111987340124456cddef92339f2c32d8300ac65caa89335bd2b968a5583af989c388f7211ad9e576576d896295bbbba7afe7042e4f747fc04a7d13844b981e252a27898760f534ef9f238f2668fc897382bf279d7ad7a2784709ae893761d3d81c638d043ba5834d6b76c38aa2df4604bc8299341733fc6208162db1f829fed0847e200fd36455a0b0c6289164bbadd5f7bb0973d3577ecc365b55a45aa4ebc2aefe5afee149a69368a1d43ab10ac4a9a247ba16f8d10506dc7f41de2030eb43d6bd64a8db72579d62ba4beb4827c6c04443e316221bb7b0319ab1d3c87fe5d9e432987ec79faa2e483630b2f821b1bbf2f8a65a25074626b8bb492eba863984d1832cbdc4c5c8f5f4e9d1e610c7a6dac72302f099f5152b1342ded0039530b5da18eceb032011e4ec143e6aee138fdc98fb0cc610b27d577c698a932b891331b7380aaf851952d7183c546abbdd99f7f48ca785d46748a4685b3d04eceed93ec2c72270d69d233371e3e6a0274a8b624aeb5d4c07e3c01ecb910062e73320623eab82c56818aad493ce0d57c4120e6b72f16fda195b21f630273fd9e0c8552477c29dc525b8d799d9572506db1a59dce392568290928e1e083bb43a0b6753a7447064b5fce51f5a598971b536ca309f99d49ba9a5795084f8d5bb1f79982c6ed2ade13a6e667cbd9fd0f5f26d4513e0737625f77f64354ab8a57f0ada351779d27a314bd510591fc4aa9d1d153d85d7deb93292f6e9b33ad248a27fba34f75fa2a198b4e09acf80a89e36d4ef66ae29250066f5cdbfa74babd35d0b27dc996f12127a9f129c79086917d9a3d3bb51d15a0ff6dfea82b32dc1bb64872372feab107cc1a9aa19d32693fb8edc301fc70a488923cdfa0af8f6edd98839da20d34eeb420c7826ec59178c55f3961ea3dacf4a43dad239e8d8f452a75259f0e2383992fc78d0d04d4ac119c04da7d5693bd8e49e5f179cc7301fa288e15d68aff3753f7197912814dff995ccc5571a516c102adea47ce9f9472870873a69de359bb41dbae36f0dfa19004b21671fdb266d2429dc20b492ed33b318f57550965907c2dfce74074126f89dec8cdf30149edfbac18c902a1dda16359f0688be4d01805c9442620e054e8716f41d33eaa680f43ca285b8bacf974b001a5972ff54d540935cbe7f2e9477eef081dc86562cd9978b67b86ca0a759c332c4b345942a0c3f235486cdbba5b377a81692a17544c94cc6cf126d5b9fbf45e76872cb917261d4a122347426ee0befe40b2c44774c6afd6c4af7081c2aa344d68017e81f1f31d5920855f360ec8bbff031a6110d3689d92cc63a814d3719f2b21c56c43996afa8fe9f060f36b4c0fba202832908a7f3113d609dbe9e75e832ab8a962ead8a3ab3abbbada40c9493cddbf67ddffe7beda10da58d95fdcb2ff049288bfa47e7314be5e6c6a1456c69860c0a3efc516aef35ea5435510599cf4500d8a1c7ea986846232a25428d103d3470be10bbbf887ea01a3030eb078755d380ebaf3dad82d3eec7e983bf27214c54ead1104bdf4468b6b40a81b6ff93c9c2a69501e6608b44536a06990342b0007988dd61d05bd1afe31ddc8719c3a558ed49f0b8115ca94628ee6867c74df66e3fed869f47bbf8218bf9a2892941e696569bb868376c53e6d90f7ec5971bb9a4abaeed5ababcda71032fa2ff35dee29fb980ac962e34803535e9a887e32c670b3f85adaa33f5595db9f087c3d40941adb6e87b8abd03297b42fc806c15e48bcf00bf007e2d4d51650afeef957fddf56d88208249d6cfe0b32733091e5d654a15f00a097533d0b123092f8446de3e0d9d882994ec9b64005e64755cecc77a1979c9dbcc9ef8e13c04787001cea12c865865a5f7f9799af52332bed514a0f801a0561ea153cf18d4f0f718a40a38511454006de04760e1384c2a95837f89f8258b67af337531faff6aff14f796c4211cc736198e66201e5d520b785f3e961e122c6fe16723a3b8dc9e82cb74202297e4416f5a46f99f9b9038b4e7b821b7beb9d486d8773fbe8045eb7241c7eb653f757cd66f6133eee4c8199458b66fbada915947cf134e0b7dfdcdfc04fc15e282ebacf3a8f8793ca5572dffdc24fceac2153092c114bf020a6e26e78df488894087d0a581d6e99d4c7e26f81254e2f56b69b55eb9c694570d59bae0ed6e8a6c957e3dc80d60ceafc97f5922a836937d93fe093f8badbdf44358129bc4131a8a3d624c245471fb4b821cf0b0331da5db36c054335c23d6f7f5889630d84b6a116b28f2ea7eaa9c9ab6491fd5dedf464fa4ba9a610aabdc98cbd16e367fcbd48423c76a8b3f50fa60c962468e29393a24d45e5138f5294a25a89cfe6d3ba84a461d74e6ad5b91a5d0258bca666c4e334843e3392c406a92d8e30346edbe696f214a877c7b1cd95d9f4aa9985578dbcb2d163fee04b3d1328ec094ac3671e0d03360337ea3378825aab4c426bc646bc362d9f12b9a79473f3435c6e227a1654e3ed1596bcb4a2a4c2c55f1473666538ba442e4327e93db91a577be81569b1289c1d80a23350b50f4c9d7438ea4887452b7d3a1bec376b894c409273849aa6c0a9dbe40b5f2bb166ac11dbe9b0f1c3128fe160c630c24d29e489ce826ee9fc99d83d1a44974b6a5faa6d8a9afca3af7a9d05c8118fcf4f4dd6c4bda524f5924bd845d4243c4f6f64741992935e4936b924f9e9c914658dd48dc9ccedbb790f8db66aa2cc4f730eea3e41bcccfbc4250494348beca054eae60bda41682cd0a7686845c98e3a70d87cb74112f2ddb703df26746d6ef2bae920b589fb5a8ad4d0f9fed4ade76079319f150eb129f2595b076ee468ca2600a5b2bdd875347f130848d5a471a6086e172e7dbc46d7bcae0c31d0cf8a5df444289e9b171416489fe51b8ca19bfbba2e0c6ca756e9053d90d0acd63523152f249595b72c7a43f92a09e57d5a2809466bbf0f4391c3626156ea657cdb2eed277067b18752f44a62803a4ba6885e6b2e4e20d70ebc7c3e0394282bf08ed8602033b4afc08ff92899c39c5633f4f9949265dc3a4a6eba5fcfb86eda251826682cf71b3eb8a99acc5faf7adf6d0b1eac0e5b75429cbf88c7f0fd436d41227ff60201a07e6996cb1fda708ad61b46b3aa848afea481707c4ec61c250c62b3ff7faee52e92097458066aca645c2152eb1612e7ba9f3d5bbe543d2e78734734b9c176c31dd3f9aecea7fdbcedff693632c3afdf2af2c516951b9b34063ccd13e8147a0f1734bcade0b5a3a334fe467947421fc1da029335b0a96dc64ca7fcf0a07c36f7312548b091bc7c4badd3e2d96d1d48a7a6e041036ed60a3fd640131c6ce1a0eaefa242a00ff5ec87bbde528261eba1da153a76d67777b0c7b8f49fd4db86545c074b3e7a948197b4bcb43971310bc0d533013d44b8d3712118b7c37e00d5cc0def187adcd24efa768908b609138583de5dc75084834bbe12b1fab0cdc15f6e4b8569cc6b31e7b1fd871b9a5b7707416c514adbf421c7c379eb17ebe3584379d3d8c57", 0x1000, 0x48000, &(0x7f0000aed000)={0xa, 0x1, 0xffffffffffff8000, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x0}, 0x1c)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f76000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f77000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f77000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f77000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_bt(r5, 0xdd1f, &(0x7f0000f77000)="221df8d6720a88b33ded8256b251388d8e18207eb0ad6226cecd2ae2e9c5393e605ae7b6a144005b058ff43225161fda1354c7b4edfeaf7af72b2245e4625604dd1e2dd82e837699dcef8eb6d1c8f2b155207fd4c96fd9bd1897ff745c733d3e2c9e00e76207f031075fb85396e93ebc89365a0119946b58ff4956e7a1ea0320eb1c5fc189dc00c48043cd2b1ca528b8ef3c8d1e6c5381d750c7962f8ff75f1b62d1ef7f61c0146c")
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp6_SCTP_PEER_ADDR_PARAMS(r1, 0x84, 0x9, &(0x7f0000455000)={r4, @in={{0x2, 0x1, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1000, 0x843, 0x8, 0x1, 0xc}, 0xa0)
write(0xffffffffffffffff, &(0x7f0000f74000)="260000002400430500000000000000060000000401c7000000000279ffffffff010007006e352a", 0x27)
recvfrom$inet6(r0, &(0x7f0000f6a000-0xf6)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xf6, 0x2000, 0x0, 0x0)
2017/12/15 11:53:26 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
gettid()
r0 = gettid()
r1 = perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0xfffffffffffffffb, 0x0, 0x0, 0x1, 0x0, 0x0, 0x8000, 0x8, 0x80, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1000000000000000, 0x0, 0x0, 0x0, 0x0}, r0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x71, 0x7, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0xfffffffffffffffe, 0x0, 0xfe, 0x0, 0x81, 0x4, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x800000000, 0x0, 0x0, 0x0, 0x0, 0x8, 0x0, 0xfffffffffffffffc, 0x0}, r0, 0xdd55, r1, 0x0)
r3 = socket$inet_tcp(0x2, 0x1, 0x0)
bind$inet(r3, &(0x7f00001a3000)={0x2, 0x0, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
listen(r3, 0x3)
setsockopt$SO_BINDTODEVICE(r3, 0x1, 0x19, &(0x7f000073e000-0x10)=@generic="76ac2d525822e09456361fdee2a055a7", 0x10)
r4 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$sock_int(r4, 0x1, 0x200000000000000f, &(0x7f0000433000-0x4)=0xfffff7ffffff7ffd, 0x4)
syz_emit_ethernet(0x57, &(0x7f0000004000)={@local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [], {{0x800, @ipv4={{0xd, 0x4, 0x0, 0x0, 0x49, 0x0, 0x0, 0x0, 0x6, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, @local={0xac, 0x14, 0x0, 0xaa}, {[@generic={0x7, 0x11, "0dd233593018524982f90e1c8154e2"}, @lsrr={0x83, 0xf, 0x1, [@loopback=0x7f000001, @broadcast=0xffffffff, @multicast2=0xe0000002]}]}}, @tcp={{0x1, 0x0, 0x42424242, 0x42424242, 0x0, 0x0, 0x5, 0x10, 0x0, 0x0, 0x0, {[]}}, {"0c"}}}}}}, 0x0)
setsockopt$sock_int(r3, 0x1, 0xf, &(0x7f000000c000)=0x8a54, 0x4)
r5 = dup2(r3, r2)
ioctl$DRM_IOCTL_ADD_MAP(r5, 0xc0286415, &(0x7f00005ca000-0x28)={&(0x7f000095b000/0x3000)=nil, 0x400000, 0x5, 0x80, &(0x7f0000033000/0x3000)=nil, 0x9702})
bind$inet(r4, &(0x7f00009de000-0x10)={0x2, 0x0, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
accept$unix(0xffffffffffffffff, &(0x7f0000d61000-0x53)=@file={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f0000ce6000-0x4)=0x53)
socket$inet6_sctp(0xa, 0x1, 0x84)
socketpair$inet6_sctp(0xa, 0x1, 0x84, &(0x7f00008b7000)={0x0, 0x0})
r6 = socket(0x3, 0x4, 0x100000000)
getsockopt$inet6_mreq(r6, 0x29, 0x15, &(0x7f000045e000-0x14)={@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, <r7=>0x0}, &(0x7f0000747000)=0x14)
setsockopt$inet6_IPV6_PKTINFO(0xffffffffffffffff, 0x29, 0x32, &(0x7f00008bd000)={@remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, r7}, 0x14)
listen(r4, 0x4b)
syz_extract_tcp_res$synack(&(0x7f0000e2e000)={<r8=>0x0, 0x0}, 0x1, 0x0)
syz_emit_ethernet(0x3c, &(0x7f00009d1000-0x3c)={@local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, @random="4c610fcc15d8", [{[], {0x8100, 0x1, 0x9, 0x6}}], {{0x800, @ipv4={{0x5, 0x4, 0x0, 0x9, 0x2a, 0x3, 0x0, 0x0, 0x6, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, @local={0xac, 0x14, 0x0, 0xaa}, {[]}}, @tcp={{0x1, 0x0, r8, 0x42424242, 0x10005, 0x0, 0x5, 0x4, 0xfffffffffffffffe, 0x0, 0x0, {[]}}, {"0995"}}}}}}, 0x0)
ioctl$sock_inet_SIOCSIFADDR(0xffffffffffffffff, 0x8916, &(0x7f000062e000)={@generic="6169efa77e518aba800d2b06409081cd", @ifru_addrs={0x2, 0x2, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
socketpair$inet6(0xa, 0x5, 0x2800008007, &(0x7f00001bd000-0x8)={0xffffffffffffffff, 0xffffffffffffffff})
futex(&(0x7f000000d000-0x4)=0x4, 0x9, 0x4, &(0x7f0000ee0000-0x10)={0x77359400, 0x0}, &(0x7f0000048000)=0x0, 0x4)
timer_settime(0x0, 0x1, &(0x7f000093e000-0x20)={{0x0, 0x1c9c380}, {0x0, 0x0}}, &(0x7f0000fce000)={{0x0, 0x0}, {0x0, <r9=>0x0}})
futex(&(0x7f000000d000-0x4)=0x2, 0x0, 0x4, &(0x7f000000b000)={0x0, r9}, &(0x7f0000048000)=0xfffffffffffffffc, 0x0)
futex(&(0x7f000000d000-0x4)=0x0, 0xa, 0x1, &(0x7f00006f7000)={0xfffffffffffffffc, 0x100000000000000}, &(0x7f000099e000)=0x3, 0x20)
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet6_sctp(0xa, 0x0, 0x84, &(0x7f00000ff000)={<r0=>0x0, 0x0})
getsockopt$inet_sctp6_SCTP_NODELAY(r0, 0x84, 0x3, &(0x7f0000ceb000)=0x0, &(0x7f0000404000)=0x4)
r1 = socket(0x17, 0x80803, 0x6)
ioctl$sock_inet6_udp_SIOCOUTQ(r1, 0x5411, &(0x7f000055e000)=0x0)
bpf$PROG_LOAD(0x5, &(0x7f0000ee7000-0x30)={0x1, 0x1, &(0x7f0000ee7000-0x10)=[@generic={0x0, 0x0, 0xa7, 0x0}], &(0x7f000000a000)="87797374656d00", 0xffffff7ffffffff9, 0x80, &(0x7f000000a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
mmap(&(0x7f0000000000/0xf73000)=nil, 0xf73000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$alg(0x26, 0x5, 0x0)
close(r1)
r2 = socket$alg(0x26, 0x5, 0x0)
setsockopt$ALG_SET_AEAD_AUTHSIZE(r2, 0x117, 0x5, 0x0, 0x0)
recvmsg(r1, &(0x7f0000f3f000)={&(0x7f0000f6e000)=@hci={0x0, 0x0, 0x0}, 0x6, &(0x7f0000f6e000)=[{&(0x7f0000afa000-0x92)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x92}, {&(0x7f0000f6e000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6c}, {&(0x7f00005c2000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x93}, {&(0x7f0000f6f000-0x1b)="000000000000000000000000000000000000000000000000000000", 0x1b}, {&(0x7f0000865000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x38}], 0x5, &(0x7f0000a26000-0xc8)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xc8, 0x1ff}, 0x10000)
r3 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r3, &(0x7f000080e000)={0x26, "736b636970686572000000000000", 0x0, 0x0, "65636228636173743629000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$ALG_SET_KEY(r3, 0x117, 0x1, &(0x7f00001ec000)="0a0775b0d5e383e5b3b60ced5c54dbb7295df0df8217ad4000000000000000e6", 0x20)
r4 = accept$alg(r3, 0x0, 0x0)
close(r2)
recvmsg(r3, &(0x7f0000f70000)={0x0, 0x0, &(0x7f0000f70000)=[{&(0x7f0000f70000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xbd}, {&(0x7f0000dcc000-0xe8)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe8}, {&(0x7f0000f71000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f00009ac000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf}, {&(0x7f000081f000-0x7e)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7e}, {&(0x7f0000f70000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6d}, {&(0x7f00009cf000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe1}, {&(0x7f00004f7000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xfe}], 0x8, &(0x7f0000f71000-0x14)="0000000000000000000000000000000000000000", 0x14, 0x1}, 0x3f5a1db4cedf06e6)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmsg$alg(r4, &(0x7f0000f6d000)={0x0, 0x0, &(0x7f000031a000)=[{&(0x7f0000a8b000)="e0fbe5e4007faabaa43a84ee0abe8a", 0xf}, {&(0x7f00005d5000)="d72f4d3d94a2625b227b0c25245f90858805bc6e00727514304e5834cfc94a1bbfadadb75dfcd122162231c47c23289f832d6c11063638ce3d6680b3e8be40a3b05d773c93a9762944320b9712183147e598eb8a4254e52e47593511e7fda6752e5b001d4832adc24750d83233ef180c33bffb94bdb1fba4064c9789ed6c5671b1c43602372d37b4de44cd9664c1c45db060bca47cd3151e90406b", 0x9b}, {&(0x7f0000523000)="8992236f04f2b8a01782acbca1495c9fc2f673910385e49e4f386a0ff64f41bcab7452eb07d6a353d5f6520e19ee61c78353334030519cd4b0003dbd464a2adc95b03b75f142986624fe347c3bbc52d66e0de5e758dd40599b70f18945196dc2a1022db60f4edcfa9899ed794143a72da8133f7bc07df868958c93ec69b3e3", 0x7f}, {&(0x7f000020c000-0xe2)="ef89da552dd330bcadfed9e746aa47bd70a9227eeb7210410a3f121e11683e61bb69c74cc9242bbda84ef11e1cfa9412c485b041877d4ee572105ed51bb1769f34d9fb498b24c8591e8aefdd08cbf41ede1f02e20402f00e6f6ec04c21be760c72880da0ca6e01ea5dfe63786136cf3597eaa50389f5eabbb2f33eee7e2b96c1c92590cca3cfa2320d1e3643599fc8e45e824412f3a7432e4319e2abe0a370c274aba6c7d674f8ebb4416e523b8080042727795be956e4971ec0361cbd4813eba7d5617ce9d7d31caaf57214787ca945ef2f4c799bb9e76ae5847eaed2d17600124f", 0xe2}, {&(0x7f0000cdf000)="8561b7a0e627acd3a48d8b9f30c6d215c928bf2f5736097e1e283522044672aa4155d800000040cf28a2bd5ae7abd49744248b986fcef2d9e8ea1ef3b930ae82f03deffad4a4bc4ce29c3f57", 0x4c}, {&(0x7f0000f74000-0xe1)="99eac84d6a3828b426e0d2bd94a372440296e7dbd81f7612aaee2b98e359972268a6af8bb583511ab042180436c76c32970e44798ed07d43ab574b074b21e9a99da113d6d97363de0e14ea35948cfcd4e33b238769b5d816af54d725d9e0892fb493649e59bd10170b458b63ccda771d5c26156bdc372e736f4cad146efde6570ab31f177183b8325edb58a0b7ed4859e31ee77c7aed8fbebdf4f1bd54d38d684e74fba79cebae37a8d063fb487688b4422341a445637a86f7ed56f82dfd43d4a2744b5a7997da7a30de752718e12eb78a87b2aa694aaf6fc509d305842f108c80", 0xe1}, {&(0x7f0000f75000-0x1f)="c06b3a247fe5e051d3007662067db4d932c52b788f2a2137c80aaab29cd6d2", 0x1f}, {&(0x7f0000e3a000-0x39)="f06bf7cd469f89c692db8ce5f8a5ad8e755f50800c2528d688a580ba0f00edff1bfec8a00695fc50ed59d372f4fb3c2e2d8b1578d1ac44b620", 0x39}], 0x8, &(0x7f0000933000-0x18)=[], 0x0, 0xfffffffffffffffe}, 0x4)
close(r2)
recvmsg(r4, &(0x7f000022f000-0x38)={&(0x7f0000f6f000-0x10)=@ethernet={0x0, @random="000000000000", [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000893000-0x50)=[{&(0x7f0000e72000-0x84)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x84}, {&(0x7f0000f6f000-0x79)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x79}, {&(0x7f0000f73000-0xd5)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd5}, {&(0x7f0000e69000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0}, {&(0x7f0000f6e000)="000000000000000000000000", 0xc}], 0x5, &(0x7f00008ae000-0x46)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x46, 0x8}, 0x2)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$bt_hidp(0x1f, 0x3, 0x6)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
syz_open_dev$sndseq(&(0x7f00000bd000)="2f6465762f736e642f73657100", 0x0, 0x3ffffc)
r0 = socket$inet6_sctp(0xa, 0x7, 0x84)
r1 = dup2(r0, r0)
setsockopt$inet_sctp_SCTP_AUTH_CHUNK(r1, 0x84, 0x15, &(0x7f0000897000)={0x400000000006a}, 0x1)
setsockopt$inet_sctp_SCTP_SOCKOPT_BINDX_ADD(r0, 0x84, 0x64, &(0x7f0000224000-0x2c)=[@in6={0xa, 0x3, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}], 0x1c)
setsockopt$inet_sctp6_SCTP_INITMSG(r1, 0x84, 0x2, &(0x7f000037c000-0x8)={0x8000000001f, 0x5, 0x81, 0x400}, 0x8)
r2 = socket$inet6_dccp(0xa, 0x6, 0x0)
perf_event_open(&(0x7f000092b000-0x78)={0x2, 0x78, 0xd4e8, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x4000000000000000, 0xfffffffffffffffd, 0x2001000000000fa, 0x7, 0x6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x3, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
munmap(&(0x7f0000949000/0x3000)=nil, 0x3000)
perf_event_open(&(0x7f0000001000-0x78)={0x1, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0xd8, 0x0, 0x0, 0xac, 0x85, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000949000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$kcm_KCM_RECV_DISABLE(r1, 0x119, 0x1, &(0x7f000094a000-0x4)=0x0, 0x4)
r3 = bpf$MAP_CREATE(0x0, &(0x7f0000000000)={0x4, 0x4, 0x4, 0x9, 0x0, 0x0, 0x0}, 0x14)
bpf$MAP_UPDATE_ELEM(0x2, &(0x7f0000028000)={r3, &(0x7f000000b000-0xb5)="", &(0x7f0000571000-0x1)="16", 0x0}, 0x20)
bind$bt_sco(r3, &(0x7f000033c000-0x8)={0x1f, {0x100000001, 0x9, 0x7fff, 0xfff, 0xa21, 0x100}}, 0x8)
dup2(r2, r3)
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000000000/0x9d9000)=nil, 0x9d9000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000022a000/0x4000)=nil, 0x4000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009d9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009da000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009db000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009d9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket(0x4, 0x3, 0x2)
r1 = accept$nfc_llcp(r0, 0x0, &(0x7f00009a6000-0x4)=0x0)
r2 = accept(r1, &(0x7f00002d0000)=@in={0x0, 0x0, @multicast1=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f00009dc000)=0x10)
mmap(&(0x7f00009d9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00009dc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = bpf$BPF_MAP_GET_FD_BY_ID(0xe, &(0x7f00009dd000-0x4)=0xffffffff, 0x4)
r4 = bpf$MAP_CREATE(0x0, &(0x7f00009d9000)={0xd, 0x6d03, 0x100000000d4, 0x5, 0x2, r3, 0x10}, 0x1c)
mmap(&(0x7f00002dc000/0x2000)=nil, 0x2000, 0x0, 0xcca73760b7d47896, r4, 0x0)
mmap(&(0x7f00009dd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$PROG_LOAD(0x5, &(0x7f00009da000)={0x1, 0x3, &(0x7f00009de000-0x18)=[@map={0xfffffffffffffffd, 0xfffffffffffffff9, 0x10001, r2}, @map={0x595, 0x100000001, 0x7ff, r4}, @generic={0xd39d, 0x104, 0x80000005, 0x4}], &(0x7f000088b000)="0542fffe", 0x8000000000005, 0x80, &(0x7f00009d9000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
r5 = socket$inet(0x2, 0x80003, 0xf5)
mmap(&(0x7f000019f000/0x4000)=nil, 0x4000, 0x2000001, 0x1111, r5, 0x0)
sendto$inet(r5, &(0x7f0000cd4000-0x51)="467f711645f5de2e7e546b01205a77d43e904debfa348eb30deb8a63fe4cc5da2ccb567c01083d40d233d206fea8b8dcb2bf3e8819165cc17646a6c3427daeb0f25b7d3ba9bca51a83b4687ef4e882f769", 0x51, 0x40008001, &(0x7f0000301000-0x10)={0x2, 0x1, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f00009da000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet_SIOCSIFFLAGS(r5, 0x8914, &(0x7f0000b7f000-0x20)={@generic="c0fabc0bd7aa3cecbe75dd4f76c63180", @ifru_addrs={0x2, 0x3, @rand_addr=0x80000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
socketpair$inet(0x2, 0x2, 0xf8d4, &(0x7f0000a44000-0x8)={<r6=>0xffffffffffffffff, <r7=>0xffffffffffffffff})
r8 = socket$inet6(0xa, 0x800000000000005, 0x0)
ioctl$sock_inet_SIOCSIFFLAGS(r8, 0x8914, &(0x7f0000334000)={@common="73697430000000000000000000000000", @ifru_flags=0x1})
getsockopt$sock_int(r7, 0x1, 0x2f, &(0x7f0000890000)=0x0, &(0x7f0000606000-0x4)=0x4)
r9 = socket$inet6(0xa, 0x0, 0x4fd)
getsockopt$inet_IP_XFRM_POLICY(r6, 0x0, 0x11, &(0x7f0000211000)={{{@in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, @in=@multicast1=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r10=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@local={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000df8000-0x4)=0xe8)
ioctl$sock_SIOCGIFINDEX(r6, 0x8933, &(0x7f0000343000)={@generic="8ef4f47eb3c950bbe8ef79176beae9c8", r10, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
sendto$inet6(r9, &(0x7f0000efc000)="00000000000000000000090000814d01b2d322633b001b2d8fab3bf6921f1a7326a222e24732de4a7a5bdb3d27d69c07ca0e672b2d153e54f91335e50191247164d81b6e2964218376481096789fd63b072fb20fbb1b5788442cf24e030000000f518a97f8070000000685a7e5c8d68a91e2b940131d08bbd929ef8eef35994c8c0c3d40a775", 0x86, 0x80, &(0x7f00004ab000-0x1c)={0xa, 0x1, 0x3736, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x402}, 0x1c)
sendto$inet(r6, &(0x7f000028a000)="518a8e34fe6b60be9692be6369261214333f9f6837b937abc351f66a112c5d05eae30992ba6f36218184e888bf4bae37be9ce7f119ed1303baf780cefd06ef37fb3be68b4ee65b7b65dbd00caf2862af7055d9ba615a6622a3e9e31d23e2148bc2d060758813ef43f03b18ec0bf7639090372c7392263d47a1eca34f9b5fcf04b5756094bd282e6ca268a9366f7433fe2ea978fd9c69bc6958274d8a9c4d1c404a315adc757677920d17acb362bdedefd90c626be5563b9accfbe476fefdb03e2936df5ebc413d30a10ada8a64bc83f8872922dcc9c472db616b1ba283befe29b4488b91708c5e691dab3a2e56099719e6b27297d773f20c38567e497dd15e75358af13752ef5803c88af974caf4d7ac7e80fc48a30292f7e850d56dd88063542f5905c1e58cbb5ca86249bd7edca8e7a4df8c3e83d355d3156a45fb4e23f8cd670bb9b172ecfb59a05ee143b4b2f644140a58f2f405cca8f8666882081f7ccd15f9661c47903ac74bb42ea71b3002a29f901787be7409f923edbe2ceab1e019896e4ac62bb1ba21375fe0a31869619609e2b6629da216c7c2443c05000000f73fbf068612af92e8a73080700b9ddf3806edfac5b1446c7c3d39a1831b09955b685c2e0262cacc728f7e01f1fc86a9813f3bcf4ed79be874366b9ce9548a8785be377d097316cd28ecf2b3337c5079e0a1b074ee2523dede048d2215fe655de73110bb243acf243c3bbf8d26e1de7cfdd159b7804edcf014f3b5150c0848d7cdeba4d48a93cf4da08c80d02721638fefaf69f6b91afbf5d838356a744785b67f1df362802e118be3560dbcfefea2b05e47211f6aa12b2db5c11b9c95d7425e47cea23e575e54c4633ab7c9d1a81b33b00db4619ed67f3bfd18411f3fd37936ec86a922d2f7f4968a7d0b757e7799e99eb5706064b43fb47519b82ddda908a15dd2f06d0449f81d7ca39250eb2038e69a4c187a68e078d135d28b4ea4521f29a208666282d8a1885cb85526ad7a7e99259294d0c1299f126d5e33ce9d50cb8b5ef79fcf8c7706088adce0a10c5d8789b62e37351973308025503a7c50819890c412fc8ce9659cb5ebf5b04085d3ec5537f3947ca17a7669f0381f358c23911da534b1b773c18b0d921ecd3f7ac88c415ef70d819e4f05aaaf0ca82353e51f8d43383afb6746796512847364c07dde9f9d32908a39f3201dc43ad5573ad05d17e6e93858725af92ff63fba906789aeefddc7cbebe259f14cacb31024a2520b7063091275462a91dbe46061ff9d1c7c60dacc13e7a5a64cc8abf5c307c3a16f6650a96f22d250b09855d4fbfbe1909f4cb5672be3610915a116e20b15590a9c05fb94b335c1f81b401dea00326ad455c2c83220ee20f7e19aab4a7781105f5a982394dd5bfb73e4c049cc3fd6e706b1629540ad026c2e8dcdcace18d97743887fc97635bd47c805192856d0aa87ed60d196b10cc23e2ed119f32597335c8f6847bd932296de6c46e8f96f3a103213cd135ce103ff8f0ea90043febbb69304501100967417f5b41c2d96a1bfdb9fa35f002ff4ad29208b245769a0a7896225dbc6d0aeedb4c408175d5983c8fb38184c5ae940a0b9a74f4b0e22ab55c699af607cdb819c557eb1a691d82d83374506e1fb1fcd00cb90421f6a1419cad64723d3fb7ece2e9315b731301fb9b2c2056552cead72c9dac3fd7e6559717090d224eee71b58a58242b6ce78dbcdacddbd743e4c13aff5510b403418595f094006e30a42487154f3e5158d6c17b6bff6f9a948f84d93f4420f3a2859da02f91d80efa80e3585aeb24b654c09715c1e04fab02923cce1f09d9ec09a3bebb3a474fda71602d9fd138f9adfb62ed2484b45addb288dda5263e3c07d7eb4472d3dd760fd9e2b0bfcb19077951633dd249fc7141b8e074037cc8d8a2535417dd01e105c383423122c80978ebd410f4d19e02c5c4f7b12b9642a8f2f3b72079578b8541fca35f28e9bf7137a325cdd2cf0eacf8f25f1bf73e9033aa5845b569e8050d71d649424335ac867110aa732ee877e8b5425c2702e0e58688736d5f56af410ec92627d38b7e6cb3b34bd2d74a51401d71a8114ccafe64388dc33037a2becf24e2fc9e5a15625243c7b9d1c1879bb5ea75d8243e50e5c58fa9932de3962dabe8397691098a2bcb6c692bfd27d2dd5fddbad203c5d7560690fbc600762ec7c71770f96b625b77f17b295b900b725ece60e485269df35faeb34867c79617849c95ca407734c21b8ad5e56a43dc880860425de1260336cb9fe1ebe0463e102f6fd170b9c9a577e75f41356903e5d984e7ba6fdbd09cbd51feebfc55fd63434e54d3dbbc59738a6dbfb08fb76236c77cf88eb67edde92d4929b872224339fdce7a77ed4df37f155e701f8efc1b2f2f75e5cf07b7d64c318e183e9f2356211d29511e1b12feb931e1cc21d719e932e7832f04905debd6679589f728a7fcb501ffbda9b877bfdef4e4b3cc23982c4dba7af24375510c4046e56f0b57f9b0731324391a5ca307ec1b33def6eb1ca62fdf2149dc3e9e938be0b6c9679c410252cee9d65d0ff9c0757b61be3abc68ad9e33098592fec4de3c9d4add022f3cad259162f2dedf15394b25089edd14913e99118383fc306ed00c0df16fabd987efd17cb79a38414862095b91a6b49840b0ed43d20faf7c834bf66396e1392d4f1cb2a103cc3784d14c0e3c8e8ae899e7c8da87c802bfa18e452718a09bfbc857a2a6a99b4a6e9e80518e98e8522121d395710c47bafbc9962e7772821758b1e240301000000b828afa177f0997812a63445b02ab3c26d442c42a5f848abf159e3a628a6318710133bd14c01706c1aa5e75df7410acb69c0793a70d95185e14794d9635cf886429ce935f85e37be02bf26cef5b8b0cee5cb8ca0accf0ca577a486c0cdf203012f266622efa4d6a8ca36f285ca40f07580511368b63df9a3bfdec90505cf22e689f8d1ef39eef9e94cbf0fe24b1475d68a703538a30ea9848603284c4b6cd6bbd72c1685a37d96dc8d7d6bfc2aedc85451a450e396f6222a2700000000000010008e7e5a77e65021a94cd4a8f116f74b0bcab6f3f5ddb41d340518dd06f246dccf028b30742a38681660c343aaf19dd985fb493985a28ca3e117801a5a06c193ba5834b965ed1d35cc1c5c819c7e3ebc6b76317a7696de593e717c68799578f07d33c764e880f350a7687c501df82f1ceefdf1cda5de9df88e3ed88739dfe8889f49f76a8f58da4974a3f987d0c1b8e801bf01ad4ed9e220b1372137a08bca918015b71fbfc9922a161538b43800e34c070ee4cd9b484448334a0242a4c61b8cfdfb4f03b6017abcdd42a3a5adb4f35a3c9abdd65e90dfae68e8c740148ea61ba0bbeef6ece0fe18355165253f60090400c164d4900f140fa09ea297ebc8529954edaba89ab2d9cef0b2836e9e92aadf845772472e24b77314731e2ebf2043e43d5f5f68447fca856648efa9f63e0109e2bd034c108b25f501955ddb0e249522ee0b1cdff29f0ed627ec2555587a01b95bef189af2d400b009bde88692d841b609803614435f4567f7baff25e5fac07209628639eff240afd62192e7e9d29f1805f316db5c2a01af15c896e84bb58fa52102316f93b1cd666798a72949e72f7110b161789de852f4c6e57dd162544d37c2ac575c1708748483fabc615b6a87f35f42df30cf0cb45eed1aa7fa84ae91854c7636c0dd07875b03721b0602a53a36f625cfb535954ee16e8fb6bdf9c45d8be72d5c9bc6f88575bdbc113318426238c10ae3547967b7df4692236dd8dc3ed3eb685562e5935698acbab7883dc17933d85646ab36270e04332455694335f6ce5472970277ee0351888e953a16ccf90936f943a6caa667b2736c9188c8d778e6c63fefb3d514c93680b25a20a608120a48da49908043f5a9fcde66d99d89234d81bf732bf1f77c7a6d0f9805172bd690759492fa64275a561099653cd987ac24134e2d9b7de8cee2c695e3f0ef0d4849fd55bc965cb0e69a82c41a43a887a39ae7422bd80f7c419066434df767db45cb6b891040dd0b581bec004ad9598a8775f15110850f6c04439dc5a1e0d96d3730ce44e0c618b751fcfffcf9ecc7bb8e3cf6f7d21e8f17b6ff1990c75748c456dda09e4c1b6459239c8bf5714a33fb8e6946a5d87f9cbeafea2948d5c833f3683bcf3a6c0c64605033da505f643d311bb5cd952da53c16d677ecfa6569f8e9519789436984e2750639a2eeb4d49b1f679dca9aced4b6dfb6085115047d511b70cdd372e78965afe3b9e80421f9b251e79762ba2178b437b60a1d1b0c26fae06e60ace028b7aabc7ce3c25cb98e434935b94d78e1a386891d5cec6e7473606ea99a30302d1f3b8bbef5cfebea3c6bf0c6a33916f0af6a5d61f0576a4bac1be93eac1a1d566f3754e4394a656832f1284d4e2df1c300331dbb2f3d7fe834acf9a28c69082c6caf101b1a0b33aeec9568125832ffb47377e61eb995a62643d3f72c9fed57707007e10c7ce596622aac96fc1889f8fb6423d9dda6964756ccb4baefeeac26d6a78c501c9d04d0435977c478b5b105fa4914ebbb53a6f657620a776811db9d4b623b8af74506a3b75f2e557538c4e5df2f7d68ebc3f6b421cc16fd5828a8aeef483b6dbefd9a7483dc598fee5b3529d5cd1dbb478f74a08d5fba2c85c0eea96658a0c23be92e7284505bf1aec2d344e3a0a5ae0d05725797d05a3c526bb2911fab4aed3b90c97ef63c4ad95470da1fe3033404c13fa82a0c91447efa0e7d82a671f260075ecebd44e8353f37bf6c8e494866b4ce5149e26a7f5ec7b9c3e2c0ec27278e74cbc8a2bbc1bb581db6db96a4aa557ef3e2afef249df9ddb210aeef9611245e80a07eafe9cecb769114e1192f7fec497272bf338ec905f16167a29a39d86f7cf4caa6e120b0563b2fe13fbcabe5139193b963a6b11cc6aef547fa91cb130166e8ba509fe21f1d98b35e09aebcdb7af18a11d5cefb0023843316d611014389a00576b967fe54c8a4679fcd802e8b06eb58e845703db7d0c1cabd96a136392d6def22e0d404ca90d5e253561b4ea26e763928e493dc7d3aac8838053cc9c616ace8b0f3262c32efc1da1d068165d58a00f68da6cdfb4857bba628e3c1a948b217beaa43ca24bfe22c155dc89ffa5ba9a96a2479dbe33ec8a3a0e4a09546f404e39791ae0371aec99381073bc36472b044ea60393c161c2f65f34de609b5df361474c3cd9a2b8f8dc081eb279e9e006e864ed80bc95b05b80922ac32378867d4d082bdd828657ff2533f8f58659a6cf62bab32498e15cdaaf9c899e96c295bf62fab9fed11924685d9072847ae0543f9201f7d6176e2b5164a37a1b5791ec4bc866d70a837f8a7961f9dbd0fd175241d66469bbd1033b30fb89313c5a328badc22885db989cab47b48777bc290eb4a25e8c1951837360f42f9e7bef1a17e892d66bb40cc9bf20ad2afe44d1ee46c462e0170de6415f3423048ea83ccf5c9a04349fd910129aa54d74616dc52b88ec604faa7324ad129deeb67ec04062ff89a1ee5929896fe2c3f2f776673298335eca312e80ae945d3cbeb1cff34985a6fae5fecd4b3de307960f684d6cd6dc90ceae3f7531deeda2c6f0d88ceff6ecd10916075e41d954fb19145f0c98f3b7c7fef1ba222cba043a8c447ab162250448dc2fa6bf773d40550d126c7afa42f8d167ed9ea115b8e11af8c2438e9b517ddbf2aa27ac09d2d4b45ae2ba85f19bae5f90b0d2ff92da33601fe98f8863f5748aae5a1127e74", 0x1002, 0x1, &(0x7f0000f6c000-0x10)={0x2, 0x2, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
ioctl$sock_inet_SIOCSIFFLAGS(r8, 0x8914, &(0x7f0000a71000-0x20)={@common="73697430000000000000000000000000", @ifru_addrs={0x2, 0x1, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
socket$inet6(0xa, 0xa, 0x6a04)
2017/12/15 11:53:26 executing program 3:
r0 = socket$alg(0x26, 0x5, 0x0)
close(r0)
r1 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r0, &(0x7f0000b17000)={0x26, "6861736800000000000000000000", 0x40, 0x0, "73686132353600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
bind$alg(r1, &(0x7f0000fcc000-0x58)={0x26, "6165616400000000000000000000", 0x0, 0xffffffffffffffff, "67636d28616573290000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$ALG_SET_KEY(r1, 0x117, 0x1, &(0x7f0000002000-0xc6)="ad56b6c5820faeb995298992ea54c7beef9f5d56534c90c2", 0x18)
r2 = accept$alg(r0, 0x0, 0x0)
sendmsg$alg(r2, &(0x7f00002ff000-0x38)={0x0, 0x0, &(0x7f0000985000)=[{&(0x7f00006fe000-0x63)="9576fb5678f4d8bb1b8c63a229d9ca03842c53286f77e16d6684d4bfd43e32c65df5593002", 0x25}], 0x1, &(0x7f0000633000-0x90)=[@op={0x18, 0x117, 0x3, 0x0}, @op={0x18, 0x117, 0x3, 0x1}, @assoc={0x18, 0x117, 0x4, 0x3}], 0x48, 0x1}, 0x0)
r3 = creat(&(0x7f00000c0000)="2e2f66696c653000", 0x101)
ioctl$SNDRV_SEQ_IOCTL_SET_CLIENT_POOL(r3, 0x4058534c, &(0x7f000097b000-0x58)={0x87, 0xffffffffffff9923, 0x9, 0x118, 0x17d, 0x69, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
bind$alg(0xffffffffffffffff, &(0x7f0000a0f000-0x58)={0x26, "6165616400000000000000000000", 0x0, 0x0, "726663343330392861757468656e6365736e2867686173682c6374722873657270656e7429292900000000000000000000000000000000000000000000000000"}, 0x58)
recvmsg(r2, &(0x7f0000b2f000)={&(0x7f00008e8000)=@nfc={0x0, 0x0, 0x0, 0x0}, 0x10, &(0x7f0000031000-0x60)=[{&(0x7f0000513000)="", 0x0}, {&(0x7f00000cd000)="", 0x0}], 0x2, &(0x7f0000590000)="", 0x0, 0x5b4f}, 0x40)
bind$alg(0xffffffffffffffff, &(0x7f0000df3000)={0x26, "6861736800000000000000000000", 0x13, 0x181b35782676de3a, "73686135313200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
epoll_wait(r3, &(0x7f0000ee3000)=[{0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}], 0x8, 0x0)
r4 = dup3(r2, r0, 0x80000)
ioctl$TCFLSH(r4, 0x540b, 0x800)
eventfd(0x200000004)
pipe(&(0x7f0000eeb000-0x8)={0x0, 0x0})
recvmsg(r0, &(0x7f00001e7000-0x38)={&(0x7f0000ebe000-0x10)=@ipx={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, 0x10, &(0x7f0000f88000)=[], 0x0, &(0x7f0000503000-0x6b)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6b, 0x2}, 0x40002000)
[ 50.003838] device gre0 entered promiscuous mode
2017/12/15 11:53:26 executing program 1:
mmap(&(0x7f0000000000/0xaec000)=nil, 0xaec000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000aec000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
recvmsg$netrom(0xffffffffffffffff, &(0x7f00000f9000-0x38)={&(0x7f0000de8000)=@ax25={0x3, {"c3c5d50d155ee5"}, 0x0}, 0x10, &(0x7f000016f000)=[], 0x0, &(0x7f000007f000)=[], 0x0, 0x0}, 0x0)
r0 = syz_open_dev$usbmon(&(0x7f000062a000)="2f6465762f7573626d6f6e2300", 0x1ff, 0x200000)
fcntl$getflags(r0, 0x0)
dup(0xffffffffffffff9c)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat(0xffffffffffffff9c, &(0x7f0000db6000)="2e2f66696c653000", 0x0, 0x8)
ioctl$TIOCGPGRP(r1, 0x540f, &(0x7f000016d000)=<r2=>0x0)
ioctl$EVIOCGSND(r1, 0x8040451a, &(0x7f0000c35000-0x1000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r2, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f0000dea000)="2e2f66696c653000", 0x0)
open(&(0x7f0000033000-0x8)="2e2f66696c653000", 0x0, 0x0)
getgid()
perf_event_open(&(0x7f000001d000)={0x0, 0x78, 0xe8af, 0x0, 0x0, 0x0, 0x0, 0x8000000000000000, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
clone(0x0, &(0x7f00004f5000-0x1)="0d", &(0x7f0000f13000)=0x0, &(0x7f0000df6000-0x4)=0x0, &(0x7f0000ef2000-0x2)="")
connect$inet(r0, &(0x7f0000d0b000-0x10)={0x2, 0x2, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f0000f50000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x0, 0x32, 0xffffffffffffffff, 0x0)
madvise(&(0x7f0000c55000/0x4000)=nil, 0x4000, 0xc)
clone(0xa060000, &(0x7f0000e21000)="80", &(0x7f0000001000)=0x0, &(0x7f0000f29000-0x4)=0x0, &(0x7f0000493000-0x2)="4026")
ioctl$SNDRV_SEQ_IOCTL_QUERY_SUBS(0xffffffffffffffff, 0xc058534f, &(0x7f0000281000)={{0x100000001, 0x8}, 0x400001, 0x3f, 0xe05, {0x5dfc, 0x40000000000000}, 0x6, 0x8bdb, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000000000/0xef3000)=nil, 0xef3000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mkdirat(r1, &(0x7f00007b2000-0x8)="2e2f66696c653000", 0x109)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$LOOP_CHANGE_FD(0xffffffffffffffff, 0x4c00, 0xffffffffffffffff)
perf_event_open(&(0x7f000055c000)={0x2, 0x78, 0x6f, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r2, 0x1, 0xffffffffffffffff, 0x0)
pipe(&(0x7f00008ad000)={0xffffffffffffffff, 0xffffffffffffffff})
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x5df000)=nil, 0x5df000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005df000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00005df000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
seccomp(0x200000001, 0x3, &(0x7f00005df000)={0x2, &(0x7f00005df000)=[{0x5c, 0x0, 0x1, 0x0}, {0x6, 0x0, 0x0, 0x7ffff7ff00000}]})
fstat(0xffffffffffffffff, &(0x7f00004e9000-0x44)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
2017/12/15 11:53:26 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
close(r0)
r1 = socket$inet(0x2, 0xfffffffffffffffe, 0x6)
setsockopt$SO_TIMESTAMPING(0xffffffffffffffff, 0x1, 0x25, &(0x7f0000693000)=0x0, 0x4)
sendto$inet(r1, &(0x7f0000f3e000)="", 0x0, 0x0, &(0x7f0000eea000)={0x2, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$binder(&(0x7f0000005000)="2f6465762f62696e6465722300", 0x0, 0x0)
r3 = syz_open_dev$binder(&(0x7f000099b000-0xd)="2f6465762f62696e6465722300", 0x0, 0xffffffffffffffff)
mmap(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x0, 0x20011, r3, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = syz_open_dev$binder(&(0x7f0000005000)="2f6465762f62696e6465722300", 0x0, 0x0)
close(r4)
r5 = syz_open_dev$binder(&(0x7f0000009000-0xd)="2f6465762f62696e6465722300", 0x0, 0x0)
r6 = mmap$binder(&(0x7f0000001000/0x3000)=nil, 0x3000, 0x0, 0x3853, r4, 0x0)
ioctl$BINDER_SET_CONTEXT_MGR(r5, 0x40046207, 0x0)
r7 = openat$selinux_policy(0xffffffffffffff9c, &(0x7f0000259000)="2f73656c696e75782f706f6c69637900", 0x0, 0x0)
bind$llc(r7, &(0x7f0000671000)={0x1a, 0x19, 0x1, 0x2, 0x8, 0x2, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [0x0, 0x0]}, 0x10)
ioctl$BINDER_GET_NODE_DEBUG_INFO(r4, 0xc018620b, &(0x7f0000971000)={r6, 0x0, 0x0, 0x0})
ioctl$BINDER_WRITE_READ(r4, 0xc0306201, &(0x7f0000009000-0x30)={0x4, 0x0, &(0x7f000000b000-0x4)=[@register_looper={0x630b}], 0x24, 0x0, &(0x7f0000009000)="d8fc00016de37101d99e3b4d488546c2bbb067efde7b55e9d1008602c19fe0b0078ade69"})
ioctl$BINDER_WRITE_READ(r4, 0xc0306201, &(0x7f0000007000)={0x4, 0x0, &(0x7f0000006000-0x2c)=[@acquire_done={0x40486311, 0x0, 0x0}], 0x0, 0x0, &(0x7f0000002000)=""})
ioctl$BINDER_WRITE_READ(r4, 0xc0306201, &(0x7f0000ffd000-0x30)={0x0, 0x0, &(0x7f000000b000-0x4c)=[], 0x0, 0x0, &(0x7f0000c12000)=""})
ioctl$BINDER_WRITE_READ(r4, 0xc0306201, &(0x7f000000b000-0x30)={0x44, 0x0, &(0x7f000000a000-0x7c)=[@reply={0x40406301, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x18, 0x8, &(0x7f0000005000-0x68)=[@fd={0x73622a85, 0x0, 0xffffffffffffffff, 0x0, 0x0}], &(0x7f000000a000)=[0x0]}}], 0x0, 0x0, &(0x7f0000004000-0x4d)=""})
perf_event_open(&(0x7f0000837000)={0x5, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x666, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20000000, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
ioctl$BINDER_WRITE_READ(r5, 0xc0306201, &(0x7f0000006000-0x30)={0x108, 0x0, &(0x7f000000b000-0x108)=[@free_buffer={0x40086303, 0x0}, @increfs={0x40046304, 0x0}, @increfs={0x40046304, 0x1}, @transaction={0x40406300, {0x1, 0x0, 0x2, 0x0, 0x1, 0x0, 0x0, 0x48, 0x8, &(0x7f000000b000)=[@fd={0x66642a85, 0x0, 0xffffffffffffffff, 0x0, 0x2}, @flat={0x73682a85, 0x100, 0x0, 0x4}, @flat={0x77622a85, 0x10a, 0x0, 0x4}], &(0x7f000000e000-0x8)=[0x30]}}, @clear_death={0x400c630f, 0x0, 0x1}, @request_death={0x400c630e, 0x3, 0x2}, @reply={0x40406301, {0x2, 0x0, 0x1, 0x0, 0x11, 0x0, 0x0, 0x20, 0x10, &(0x7f0000008000)=[@fda={0x66646185, 0x7, 0x0, 0x2e}], &(0x7f0000002000-0x10)=[0x78, 0x28]}}, @transaction={0x40406300, {0x2, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x20, 0x18, &(0x7f000000f000-0x20)=[@fda={0x66646185, 0x1, 0x3, 0x2d}], &(0x7f000000b000-0x18)=[0x78, 0x28, 0x78]}}], 0xeb, 0x0, &(0x7f0000000000)="ef7e012f6dedee7f24f0f1408ca3662d07dd3b564a5f775291eb7cfd3c7303c239d60396a2b0d00c7ba73cdf425373ba6c0ed9c15ace0e07973b0a7a4e896178660036ead3c45e3db404d38c7f0abf8a7e1e2e710447f0ec93e717de20a81366c5f0b3c57795367a4fbafbdf474a87cbf7a4c1c1d785883bb7da6c67f03f21703efd5cd3de10a906355794d2fd44028a3501650048ae53bbccc20a6f9f2a05992946058324d71b64a7e7c389302d34fff8983fc8cf5f39af11cf4f5e9d6a75b820e0767c839fefc0220df5f72da23f52d4c73aa7df4388f5c736869601b251a8289e93bb8bbd7512d626a9"})
r8 = syz_open_procfs(0x0, &(0x7f0000003000-0x9)="6e65742f7374617400")
ioctl$BINDER_SET_CONTEXT_MGR(r3, 0x40046207, 0x0)
ioctl$KVM_REGISTER_COALESCED_MMIO(r8, 0x4010ae67, &(0x7f0000674000-0x10)={0x6000, 0x0, 0x0})
ioctl$BINDER_WRITE_READ(r2, 0xc0306201, &(0x7f0000007000)={0x4, 0x0, &(0x7f0000006000-0x2c)=[@acquire_done={0x40486311, 0x0, 0x0}], 0x0, 0x0, &(0x7f0000002000)=""})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = open(&(0x7f0000001000-0x8)="2e2f66696c653000", 0x4000, 0x4)
ioctl$sock_ipx_SIOCAIPXITFCRT(r0, 0x89e0, &(0x7f0000072000)=0xff)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_AGP_ALLOC(r0, 0xc0206434, &(0x7f0000001000)={0x7, <r1=>0x0, 0x10001, 0x5ad})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_AGP_BIND(r0, 0x40106436, &(0x7f0000002000-0x10)={r1, 0xffffffff})
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$nfc_llcp(r0, 0x118, 0x2, &(0x7f0000002000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x45)
ioctl$TIOCGSOFTCAR(r0, 0x5419, &(0x7f0000001000-0x4)=0x0)
ioctl$KIOCSOUND(r0, 0x4b2f, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$selinux_status(0xffffffffffffff9c, &(0x7f0000003000)="2f73656c696e75782f73746174757300", 0x0, 0x0)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_PROG_ATTACH(0x8, &(0x7f0000004000)={r2, r0, 0x1, 0x1, r0}, 0x14)
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KDGKBDIACR(r0, 0x4b4a, &(0x7f0000006000-0x7b)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fcntl$F_GET_RW_HINT(r0, 0x40d, &(0x7f0000006000+0x954)=0x0)
ioctl$KDSKBSENT(r0, 0x4b49, &(0x7f0000002000)="")
socket$bt_cmtp(0x1f, 0x3, 0x5)
ioctl$KDGKBMODE(r0, 0x4b44, &(0x7f0000007000-0x8)=0x0)
ioctl$sock_bt_cmtp_CMTPCONNDEL(r2, 0x400443c9, &(0x7f0000006000)={{0x4, 0x0, 0x4, 0x1, 0xfb8, 0x29b3}, 0x4})
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_DEFAULT_SNDINFO(r0, 0x84, 0x22, &(0x7f0000008000-0x10)={0xffffffff7fffffff, 0x201, 0x7f, 0x2, <r3=>0x0}, &(0x7f0000008000-0x4)=0x10)
getsockopt$inet_sctp_SCTP_PEER_AUTH_CHUNKS(r2, 0x84, 0x1a, &(0x7f0000006000-0x86)={r3, 0x7e, "4403809dfde86c1facf32ae47223fc187ce1881be0e870e632eeed95b975cb606b2151689d8aaf55caa495371934d8174d56f5d9cdad5c279882d6dd593a98d37de37c02d7155321b297de1958f43750edb47d367950435ea5b9f13355702ab64554c3008aa819d89feaa1922901409682adaa5bf2c54722faed3f947ea4"}, &(0x7f0000004000-0x4)=0x86)
mmap(&(0x7f0000008000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$MAP_DELETE_ELEM(0x3, &(0x7f0000002000)={r2, &(0x7f0000009000-0xa8)="d9f274481cc7d9aee2780fcf3430acafe6431ceac5f18ccf22cb4b75536605374d751121494d43eaeaff43d732d63be27c25ae01ee0dc87bfaa493d48b91ab4f9b11e989e88375a69d4712eb7290eb11b842ffcbb6d31f8a9b1f1f6007b5533b773e7fa124b37ca5b066a99272567417ddcea13a9c2e31cb980d88bcaecb7874b235e1b6e6a9041cc86a064c2c765c25de16c4b754c9d7a63aec331fcc6111bcab98c00144e26d8c"}, 0x10)
ioctl$KVM_GET_CPUID2(r0, 0xc008ae91, &(0x7f0000007000-0xf8)={0x6, 0x0, [{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0]}]})
2017/12/15 11:53:26 executing program 3:
mmap(&(0x7f0000000000/0x6e000)=nil, 0x6e000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x1, 0x0, &(0x7f0000011000-0x8)={<r0=>0xffffffffffffffff, <r1=>0xffffffffffffffff})
getsockopt$sock_cred(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000069000)={0x0, 0x0, 0x0}, &(0x7f0000067000-0x4)=0xc)
socket$inet6_tcp(0xa, 0x1, 0x0)
pipe(&(0x7f000006a000)={<r2=>0xffffffffffffffff, <r3=>0xffffffffffffffff})
splice(r1, 0x0, r3, 0x0, 0x58, 0x0)
r4 = dup2(r0, r1)
fcntl$setpipe(r3, 0x407, 0x0)
writev(r3, &(0x7f000000b000)=[{&(0x7f000006a000)="6c", 0x1}], 0x1)
pwrite64(r2, &(0x7f000006c000-0x3e)="02e112f50ec7a40ba62779b1bb33b89c8b5d9d3ea5ac5664669360fc97e01a350ff003bff50cd3a7298c6e435f276b88e82a602445957d17672a42ef8094", 0x3e, 0x0)
getsockopt$inet6_IPV6_XFRM_POLICY(r3, 0x29, 0x23, &(0x7f0000042000)={{{@in=@empty=0x0, @in=@broadcast=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@multicast1=0x0, 0x0, 0x0}, 0x0, @in=@local={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000059000-0x4)=0xe8)
mmap(&(0x7f000006e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_mreq(r3, 0x0, 0x24, &(0x7f000006f000-0x8)={@loopback=0x7f000001, @rand_addr=0x100000001}, 0x8)
read(r2, &(0x7f0000043000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf)
r5 = dup3(r4, 0xffffffffffffffff, 0x87ffe)
read(r0, &(0x7f0000032000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xf80)
writev(r4, &(0x7f0000051000)=[{&(0x7f0000058000-0xe9d)="ad", 0x1}], 0x1)
mmap(&(0x7f000006e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
write(r5, &(0x7f000006f000-0x89)="3c891d352d160bb93f972be7b62f95850cfbff0300b4a1d997057db1c953d0569be4c4f3ff48b7cf0731ef602e63c4f227e654016b98c6a736a00a81d4ffa49ede110884630d5377d005d226526545a912047b3e167ac8c1d0b000c7702df65a3753b4f884c1de74feed10810b20545f7b144ec193c4774b1c45191506993b96ba65679df31d16f40c", 0x89)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$kvm(0xffffffffffffff9c, &(0x7f0000031000)="2f6465762f6b766d00", 0x0, 0x0)
r1 = ioctl$KVM_CREATE_VM(r0, 0xae01, 0x0)
ioctl$KVM_SET_BOOT_CPU_ID(r1, 0xae78, &(0x7f0000235000-0x8)=0x1)
eventfd2(0x0, 0x0)
r2 = creat(&(0x7f0000d61000)="2e2f66696c653000", 0x88)
ioctl$KVM_X86_SETUP_MCE(r2, 0x4008ae9c, &(0x7f0000f5a000-0x4)={0x16, 0x2, 0x3, 0x0})
r3 = syz_open_dev$sg(&(0x7f000093d000-0x9)="2f6465762f73672300", 0x100000000, 0x20000)
recvmsg$netrom(r3, &(0x7f00008b1000)={&(0x7f000011b000-0x48)=@full={{0x3, {"245d77ee4a001f"}, 0xf0}, [{"bb17bfdfaf375b"}, {"e0f474f145b7f8"}, {"a8d411cbd14b44"}, {"677ae9b95c6c4c"}, {"fbf74588bb5fc5"}, {"e8e5ba1bfdcfc1"}, {"18bb90fe206b10"}, {"156845fa5cdf79"}]}, 0x48, &(0x7f0000569000-0x30)=[{&(0x7f0000f60000)="a12ee1437be116d89213363982f0a46cc0a5d2c0ac79530718caad5603c02e98939557ce1403de175c1e01fe2a8801b13ec633d1057b3be6b901685eb0d2d58786028a64d2e96cb023c12743b6b7a83acf837b3d604c73e2b5390af5d81247970ece2265e4d7cc7f3481c3fa9374b7144ea1ccd4659a5ec695490bcc6378939f52ca015fdb6763118379f3ccd6d93a486ee215c171fa1a0f989306cd0473ed866daaf74e42235c8a1f133998862c495fdbfac6a3a9", 0xb5}, {&(0x7f0000124000-0x5e)="332fc3b3f09f4b4b958d934e07c3005d9e1b1d00b767a425d258b46a9b9212c1429d42c390ef6c5802ed253ee8d844a40cabec834f70662c0fdcf5d298c9df6579c3e4a108ebd9d9c94f8f8134c89d566be818c3a6a3e840240ee95517414164a339250037b33de64729296cc7bb53352222bf9a50c43a8bde3cb79342c3873bb53093be9f39fe75745839fb52ee47b2584a25d23aba67e2f9ae14ccfb94541a772c75d1dea7c186b149c46db32e28", 0xaf}, {&(0x7f0000e41000-0xa4)="e3d68cda6f6d54db2956bb89e7fb329114a15b09a83cabcea43ab02e6a8cb86ab6ef697714189213e41c2891ac2615a7ef096cc8decb31c3806cd7210993761ab0f9a1b2f62afeb4d6264a23c9fa76ffd72041f8579faf401ad0506c7c29a239c3a31935047916784e8a9c37173bf55fd4d5864699668fb2e922cf9ddfbf713c19e1219dbf477c888226300864729a718548fbfe703aab1b1e122a7efc61e89a10350884", 0xa4}], 0x3, 0x0, 0x0, 0x8080}, 0x40)
ioctl$KVM_IOEVENTFD(r1, 0x4040ae79, &(0x7f0000020000)={0x0, &(0x7f000002d000)=0x0, 0x0, r3, 0x4})
socket$bt_hidp(0x1f, 0x3, 0x6)
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$netlink(0x10, 0x3, 0x0)
sendmsg$netlink(r0, &(0x7f00008dc000)={0x0, 0x0, &(0x7f0000e85000)=[{&(0x7f0000f73000-0x3b4)=[{0x9a, 0x75b3, 0x2, 0x5, 0x80000001, "b73b8d6b563c2ce20e9ac238728298709bbf2288573f98325bb34141186ede7e5854b010403ac82a618b652756dac75fe795881f1abca2e295e256c567a40b31c4da43b9731491f02fd3adb3cdc66acb1efc9914920a7c6c613e2abe53015287bf93742c7c5d18bd6f265c2c1c38c01a1946bdf55e02a8846981d7a226e7fc74a674eb82b41e914ee078"}, {0x9b, 0xfffffffffffffffa, 0x308, 0xd78, 0x100000001, "73ce7c30dc50dcb5b4717b7c509b975ab6e49991e32f6852e2ea79737da8496a9f04526d6b1efa4f5c7c547bfd134b5cb91a1fc32acfc4b9cdcfb8b0e436c20c44f11b0b320919263f6d945f955d89bc02ce641975e75caef201e6f00219f7091c4d053e16e9b2a78ee8295840cf5a435c19bf9d6034533abd6a589bd21f64b1fdedc9c7a5bd279c588bf6"}, {0xab, 0x9, 0x418, 0x8, 0x2, "89033782e533c4ce6779f5aa29e8b7a2e1b2f0b4b2ed8dedd9b75e2aba3f03e64c59a7851ca3403049cd42eb476f053824ddb29f0b9114c46fbe571da15a7188bb93aa61eb53672638c7d2d167f359eabf405041853fc38b2bddcd9432f14a137b0c49679bcdffb6f296c11bf08799452193ea9d9564de371988d405095b7330f0e8acb2b86ec0ba3ed00cb610c29df7b99c01d72e747347a10d9c"}, {0x72, 0x200, 0x0, 0x4, 0x7, "19071409d351e702c64dd1e63e910343beab9e6cfe637d1b40b34da703b537eaa0d194639e11343817ebb9c286d557f5dc47f4ef27d2ab6049bc2e4e0c6756873a8594a0cf3b0a27b5c0017e482b01f35c5f6fd68ed9a1e4d7b2e075a3ec0601bd5b"}, {0x5c, 0x0, 0x4, 0x6, 0xeb, "b2ed2470255e757680b3127e9c18a70ce8c734111eaea222f3fb87a9ce63866917c7616bdb235654e03cbc16136a5175002652f87257fda2168ada07eadbee13fef453062e574ad967a9c4fc"}, {0x56, 0x1, 0x1, 0x2, 0xf2, "c9b29d9f5133ce92fb685d1bb45a698354de55bc2ee544f738c4e02e459914dec6b65326e8594507fcc7508d52df817bacdcd278269e8a129a46ee8dd6903aafa2c3b87abf4d"}, {0x6e, 0x6, 0x20, 0x0, 0x400, "81543fd5e7d00a302e8774670d3d84e9a351956214b351a27019178be7fef19e18947e77afac0144234df42d95dedd888baf5e2ed4ef04c1fd93c9b4c666a606fe0bdaa86b0f005f0bab5eb48177f55370c381fd448dade6405f2e90b711"}, {0x42, 0xba1, 0x425, 0x100000000, 0x1, "89d6796cc10d82589f16a1d35b34eb205feb4da7cbff417de99ccba3c5eb8240e0e5b57494a6acaa482127626716651f1820"}], 0x3b4}, {&(0x7f00003d7000)=[{0xcb, 0x4, 0x14, 0x2, 0xffffffff00000001, "54d7bc048e8401b6abea91af9f6f96db9a1e89427e04b6ee77f847dbcc9a9b461c48ab92c40fe8ba7a9a338c0f20c02dcf1481fad10294536be9a0cb8e5d3de9b65053a0acf3aa7c2b43fb780edbd7bfff7ea4762981035e87865c13d125e5c97e04fd261ca7e16b8f54b71fa9884a0093040b711fda6b27e12147374dcb2d386d1f02b1e071b77c9d91a6cfa03d477d443877f664203b57cfeb2fb8b7712416390d2ffd8e7c9d1e67d1da9d581d581d79da5baed3e8f1d096cc45"}, {0xee, 0x2, 0x200, 0x2, 0x2, "be7000182c5f05b7797ea0d1bc4b242502d9e97d91ea5ca89e555b3627a72549c3ef2d0f299c2884ceba427498f94f1c0990f7ccf72744ba9962b28a8d2d027f5b6a255fe2a7cf2e5c8b26184086f27c8a8e8394d0ed24b899c9dd1d973cf50f5ba8e50f6c0c17fed176391f02e77fe48fa0da07f782b1204b04d1264ed447bc80e8c7c03e95a610ce9138a1b5f0242abea7f0b585b5d1ca5e82c60b5b4fd7e965b1a660765ad6764dbb31f405d54345f539c2faa356bc85316c3df9547dbfbcc784ca0fcb538d244fa68c38da1fe5e6a5870e51ad73c0ec5e725ec04172"}, {0xd6, 0x6, 0xa03, 0x1, 0x2ec890c4, "cf58217ba44a66afca94031da973da64206c71cea48629800077380a636bfbf595242d0ea62246679663d24a8a385566a5d63e6ba1d2a65ee0b4186e922d734f1b5d541c395402f39cd40559cd9013cf73970f85a296fc3e8094cdc82e1aaa33f1178204dc1956314980522e049d4f3d72c444e73d30820b4d26d22b2f1e5113abc54f8c897344d1a0e0d5f8be7df5554213bbc4616bdfa41b97fa9a3594cf47e48c479fc49a54828bd40ff850ce14703e04a32aa38401f8c3a921ed9b853575ac8f39615366"}, {0x28, 0x0, 0x920, 0xfffffffffffffffb, 0xfff, "f923b77cd697f3c27c460dd051e9e96d62d0e6469d850eeb"}, {0x56, 0xfffffffffffff1fc, 0x8, 0x1, 0x8, "2a478fa8f0a058c870779e1cea96b4fd1a2a5602b113416ee2cea6c439ef2e6f84a752c58053e5c617465da0a493cfd807d674ce76b0dcc3bf2bc3d8ba10c7417b1f43e5e7a3"}, {0x94, 0x64132f82, 0x200, 0xb1, 0x401, "41adba7bf03d3ca706b502d3c334dcfacc5af9856419e98dab2d5e9135ea4e56faea60c6aca5146c96196b10c9c724909221307fe36f163a1fcb913f86c36729f7c0bae8886a7fc42a521de85278f9c79219ac31087af9b2854c6a1065cfc020be11bf5477930e1df1f441be5f14bf449d925aec0e7d2bb1c937e0c5ad160730c1cc509b"}, {0x45, 0x3, 0x200, 0xfffffffffffffffe, 0x6, "1e87ebc091600cfe512c1dfe1f5fe7e026b99548a359abb31bf33fb36741e425b05c1f4d3a866a6f78bb04a4a763312297f9e7f5f0"}], 0x3e6}, {&(0x7f0000ca5000)=[{0xec, 0x81, 0x700, 0x3, 0xdf, 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"4f4b391b91bed6c7fc32136268fd96efa6c753c74df1acdd55eb3a255e646b59c0bea909c0fa73adc1af284a48edfa886d7ca83a064087463d5e7a8cda5af9499c03ccb2d8ca65e0544850d75cbcae8117e9071781805cfd7f10f79673f00bdb3deb1eaf7c16285bfa754fd935311ae16bf265002866ed8754d79ed5765bb5479ed0837f05328dd4f756494a3d13d2eec6ddc88c2edfa9c9f9a1b21d398b895c48861ea548fe1d3d38c5cce59a70ca8203f4b245877c4582c98dc22d1ac537031e60c5cdabf2654978e33a99026fba436efcf820b2196ef66e0a27c4de61b55dca779596d1415781a9f991bbd7fc8aaad7a7e46a6883881f6b0000ae74e11efc99d34cd200d420fc49cc3336cfe8aa1d4ea51fc5be5e033e8882c888d6f3242684e7ac1b0290d659e7c3e5ab918f39147d9afddbf0c2efdc79dfccb325ac2472b3b2c94f39ec1bd1a9112a6a12872e2115f668bc4ba15b038a2928fe40a7c3912533f16a8ac3044684150ed7cc946e853ddfce3186177df042715bef1497bfe7daa990935053bbc0d38dc75b721404840a78615fa2f4ada7b8f4b862f40950c02434e26608bd1b57a47ad8208cac225327d57bcca6365977051ad108c002d761ee45bd7e0d61d791f4e75be1cecbc4d415a1d4be8f7b9463f282f50466c91f3004697e4ae74beefd4c3b3bbb049c7c97f07b5c445dea7356f8d5fc25698267ae7add09881c5d4def95ad15bb38b15fe5d4452acaf79fcb1f789c3b2fd71d555f8356c22f14cabb6897497c1dbeb20ec3457937e36e37832da6f16ca5057e41f90b043e0f33fe4bdc96eb22d9278b4061ff44375070cd3ffe9632a82a0398487d6d4e11fa7a226958369e8c90fcd797695978fa3f5c36a15a32bf3b6d3b38ed2e43e7e98f2cfac43f9f6abba4dd0e202d6382e397d4d799f91e4e1aa2b56b5da187d72b392a07d502ef08cc151fa38b67aa2b4b64e664bb9a679c104c119788603f4684f7e2cf9253ed55f3073adae342535446e5e4fae82c6893bcd13d841362a59920daf01d4f8bba3ccd321839b8e60dcdf5ac2a9014e89eff5975468ef9c51d0e21a5427a27ab1bc5ba979534056ba22c23910562df177c57da2f816fb57d459a12d6bd5de94403b2353d9e9161c35c7b77744883c12a73be0d5a7f740fd83ada0f0825c6b82d2637ac44a18f2918a0ef6ea792bc1eb6dc969996bb4688d9354b16382490c989cac9687813aeb597238d14d0587e61f1dbfe26638320fd1b510594fcd03290891d176bccfd754d6bc941c3d9511bd63e1f6c1de1510181d4df2dd11d83efa8430a49b92c2ae48d7298f09376db860b5f2b17070dbce335b19a9c95d628ebab3fb07674dce1801cc53f0d770a0f60bfd4c54844089ef9c2bdece4e796389fbbbcba30ee2fe542081ddb06f9c3ce9dc40780729fc13b69fadc1af033fe6a45e8b962771fe52168e1209a98dbc8db9cf22dc5ecce7a996c95f4b15faa30f3ddf4d4fed839a9fb4644cb1f1a58a25152c0dcc6f8b79c07bec2652cdac65ec037810d66ae7912f7fc0b0054971f6df2981cb102235c16c6093ea3f6aa778b04e0abb364f252d1471a2b5c1e60150ed7f0b0412505f83f95680e38ede6bc299b14e6f83a581ce51592e4429489e90334535f367b8abc704b3e6e586f0750f6d89cf76c294146456c91638018167d42eac3ed3f75b373bdc57262fac1a9ea0d9944de41feb8a803e4534d8e2994dbf10cca45ddffebe4b015cfae60ad299ca404d3a05f3f81ec2216bf272640d07bbc6dd298da0ad4d3a49b43e490f4064024cba39fb3104d88bf65c6d0a40766551a6226e04f5672c4307da9c821661f90bd976eefdf83b9f408557dafe948f7458f2bdb095c67bbaa762d0ea9e96440f549bfa0de7b18932ad0d6bfa4d0332187f0efd41f200dbf24c0a0f0c1290e753d62e81a443777bcbbf24bcc74e0d0193c7dede4f7270a3e21d341fd9871f73136d36bc034b3f45b4397d1f72b6ab4645a04ad5c3e59b748b29c59256b1f1da4910ec9ec80856e27ce5e0074560f47ddafe3b3f653d403c3d7018bf46b99cb2f4fa2d2b44cb809de2b876b7a0a8588d67a428cfb36ba40241b2c24e26e9e94be91ac249c5363f46ab8e126623a78a17003edbfdb12c0cc5d623e249893065312edffac1615a323c301fd8828b67c80887d1baad703cbcb175a44a29b776b409d3c7d050e6590c6ca4fa5b0996f082ede299f1e5742b427c7c19202183b9bcd308d7e2fe798c38d56eb8fb9362c85f05e03c3e784a85eeeb8556639d09bbfc0661ff235d78e81972ca4462982115cc2e93e18feda480a244637545fe1c025407b4a2f5ae1b9f6ff43e81d1a85c8b78c4fd387252c9cfaacacf84a56945d58457ac31a3c2e6aa508315aaa986525bfb63c1184a7e69e83a9cb3e95673e184cbabf69b3c45ea9b7c655941f1bb7518af9e13d269283f671be021ec1ef7ab3f76b44ff165672f470125d0930be082503287dc2c50083d3ceedb1db041f94bbaa7ff267db8ab7483b0112a2cfd08818ac1dd154d7c29a558a569781c670ea2378266b96176089190183731b3e97ef29a1001c8f48474beb657caa7b64745ffa1d31cb822e73bfb7823514ead851293f7b6c49ecfa50c7c1a39861fa86d39dc6218b3082ce678737b8ab7677ba2d0a74a325168082181627e4f35c5d22eff2a3787b52a7d587eeb9cbc4184e8dd20eca081d860a760b643e21b2aaba152cc36e2df78199932804a7b58ed77cce0afb64907acd6bb2ef5b4e77642cf1fb9b5a8f3435f49ff99feb1e163f64bd8a61dc1fe866f63c5698bc86b4f6e829d51cb42848bb2fb4a9e7c736eacd0299f0b81be5675cc649ac7295ccabb8c5f96355292742a8ba8c8cb2800941f6bb0fdb7876a402882fd61bd2dd8b4bfed9132ec43b21e4db6c74268c0f525e69821eed417a70ab4ea0ad2212964359269e9f4020068ebe6091c8b3e59baedfcf348ca1c7afd79c8e35b9410a857f83df98530e70e530938d59489810656be4679a5e82af891947aa094c2da56b5203d006ba1a55a475b540629386907ea6edaf43010ebc5ffad256a5f2c62dc9a3e19385ab51a60daa9839aa04395da428cc779e3a734c59485f8bfb448017d163956ee33db69fa5bb25f79abfa1897ddde6a409721b7dacb6511d740c9dd4e7f5425c77b81c6b22026063b026963851b286f7de06435be46bb4988fb7dad583c1e397c54cf08415732ae21fe185dbdd3ad4dd136f91c87be9de7fba3e33725103b20c3550771a91c25ec2f1e29a797c9552a193f92fe516c61ac5199207aa8280106087430d67f472dbf04eb70494060756b730cf5d48450ab63c2257c836b86a9c91aa38ab368259578ef61143f952c180958268239689914d64e1310b3266f0c27be860cf6cd3013fb34020adb6be6cd676ec44520a7f4675d1d0abdbd17ce322982ba7756eb67d2c9dd9d36585e44bd9f67d5efd7ae58816e125a555011e47c02d71250d10137bd48f0ec9a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{0x28, 0x5385, 0x401, 0x4, 0x15a67670, "0133156432a8936daba5d704a259e55cbb05da7121aed83b"}, {0xbe, 0x2, 0x8, 0xfffffffffffffffd, 0x2, "8f95bdb1ecd5a3d7f487a3cd33dffd4ab92995b702754b5be7651af4ff18a2050224b4d7d43ce9462d178a2e79a000e6a27755c46c18a88eaf1a6ed69ca59857e339d24ab43fe07d1fed7731c66e1a54fcf5d0cffc873f4f5e5ac4902315989bf37347ee2d92e2139bdff58b12638abca7b61ef150e204ec74ef33a56dfe0ac31e2f0bb82641783689ed812e157b92e3b8759edc81cb95ce1e376f0c6f364f69756a4715271aa36d656111c75054"}, {0xe8, 0x76a61017, 0xe, 0x1, 0xfffffffffffffffa, "16cdc6b06c517a15c70198659f5c0e710d61473bebe18988a374c5777a10ca68fba5d09d68b00692f668b2c5314a4db5b95d3e181d0924c2c9736d4a76c10e74daa85b3d8af826636112ac3a4f2b6e8e6ebd2f54947925481f6c4ed53894a831463aa63c98d430fd2aacbbe62a220b8733df86c8a6bd330a2a837a816f8c033e4c3632ce38d9c41f5561a4b3a49a896db9ed89a48f251c3e03b6359e26f8780ee171841ec510dba675e0f59a6d9dcdcdd7b9c1fdc5f5998ec803f52a7c822f4c0d400953843245811315c8dad248457f80bba5b706c13160"}, {0x51, 0x2, 0x400, 0x649, 0x7, "bf7349d63837b291d4ed77504fe5e9240400a2098eb5fef37d181357a596725f6120519f6c9333a41bac72452e08e92e0b67f0d68bdf35e694838fab63d5c271f7"}, {0x1f, 0x2, 0x1, 0x2, 0x8, "0c122bdcb785696e94f6cea23f40f9"}, {0x10e, 0xf6, 0x110, 0xfffffffffffffff7, 0x1731, "c345f1287e685196db46ab6c4ed00580d5d42e4e15cb87dd1161a40035a1e2fcb25d47812532a08205923c4d8fcc528853b41313918847727ef55dbbbd848c70d567986d371472535f74fb6584366816ddcb2ab7c9d756e4fae461e83a9ec5db3b061ec862432511de667c17a6f91c8929bae55f7c1ab2c6656cf7ec6c2521152e55225d18fbb578be8ec63d60c277e4d6921a91c6d3a187e5b62ec2c5f45eaa1e066dd63a0708ed17f8c25a6cf188db3187b04e98a1da57da8deec24920ad8f2bbbcce46af9a0360e0dfbeca41ce4ec0416abebea8b9a5ad55420d08e586f776a76d7b8c03941197283500187f77b891e7dce883bdd89f7b1b11955c790"}], 0x2425}], 0x4, &(0x7f000093c000-0x18)=[], 0x0, 0x0}, 0xfffffffffffffffd)
mmap(&(0x7f0000000000/0xfbf000)=nil, 0xfbf000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$ptmx(0xffffffffffffff9c, &(0x7f00001b5000-0xa)="2f6465762f70746d7800", 0x106, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = accept4(0xffffffffffffffff, &(0x7f0000666000)=@in={0x0, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000fbf000)=0x10, 0x80800)
connect$ipx(r2, &(0x7f00009e6000-0x10)={0x4, 0x101, 0x40, "be19b36c8576", 0x8001, 0x0}, 0x10)
ioctl$TCXONC(r1, 0x540a, 0xff)
ioctl$TIOCNOTTY(r1, 0x5422)
r3 = semget$private(0x0, 0x4, 0x8)
getsockopt$bt_BT_POWER(r2, 0x112, 0x9, &(0x7f0000f3d000-0x1)=0x9, &(0x7f00004da000)=0x1)
semctl$SETVAL(r3, 0x2, 0x10, &(0x7f00006ae000)=0x0)
rt_sigqueueinfo(0x0, 0x3c, &(0x7f0000987000)={0xf, 0x80, 0x7, 0x95})
ioctl$VT_GETSTATE(r1, 0x5603, &(0x7f0000b16000-0x6)={0x4, 0x2, 0x2})
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair(0x4, 0x3, 0x8, &(0x7f0000412000-0x8)={<r4=>0xffffffffffffffff, 0xffffffffffffffff})
mmap(&(0x7f0000fc1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
writev(r1, &(0x7f0000fc1000)=[{&(0x7f0000fbf000)="8b62c5c21aa2f300000004e9141ba6080000003099267b935e003b", 0x1b}, {&(0x7f0000fc0000)="d8ae59935f54ff72e8f472e17c1e116f8a5ae56313bfe81215b5cfaf7866305ad53810bb8c9e1fc5e17c32787399265be73acf9ed9bba48fbb097368795102c5cb950c82329a4e8530fd2845e9338da40a8e2ff94d1bc0bdac6f82ad9e252d539567d106670633789d", 0x69}], 0x2)
ioctl$DRM_IOCTL_AGP_ALLOC(0xffffffffffffffff, 0xc0206434, &(0x7f0000c1f000-0x20)={0xffffffff, <r5=>0x0, 0x1, 0xfffffffffffffffd})
ioctl$DRM_IOCTL_SG_ALLOC(0xffffffffffffffff, 0xc0106438, &(0x7f0000fc1000-0x10)={0xffffffff00000001, r5})
ioctl$TCSETA(r1, 0x5402, &(0x7f0000f36000)={0x200000004a79, 0xffff, 0x100000f7, 0x68e45f24, 0x7, 0x1c, 0x400000006, 0x0, 0x8, 0x10000000200000})
ioctl$TCSBRKP(r1, 0x5425, 0x1)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fcntl$setpipe(0xffffffffffffffff, 0x407, 0x8020000000080402)
ioctl$SNDRV_SEQ_IOCTL_GET_NAMED_QUEUE(r4, 0xc08c5336, &(0x7f0000d76000-0x8c)={0xf3, 0x7, 0x10001, "71756575653100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x5, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
fcntl$setpipe(0xffffffffffffffff, 0x407, 0x0)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat(0xffffffffffffff9c, &(0x7f0000000000)="2e2f66696c653000", 0x410000, 0x40)
mmap(&(0x7f0000000000/0xb2c000)=nil, 0xb2c000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000b2c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f0000a09000)="2e2f66696c653000", 0x160)
capset(&(0x7f0000000000)={0x19980330, 0x0}, &(0x7f0000002000-0x18)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
mmap(&(0x7f0000000000/0xff6000)=nil, 0xff6000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$inet6(0xa, 0x100000003, 0x1)
mmap(&(0x7f0000ff6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet6_udp_SIOCOUTQ(0xffffffffffffffff, 0x5411, &(0x7f0000ff6000)=0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000123000/0x2000)=nil, 0x2000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x5, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x100000d, 0x32, 0xffffffffffffffff, 0x0)
sendto$inet6(0xffffffffffffffff, &(0x7f0000002000-0x51)="54f914a0d2c0692f424ebda9d0d59e51d8cfebca9650098bd2998b536de5ae4385432d1895ebc413d9889751d60264d2901cb0d1569dfac9249b61cd52e5f12a1c928c4bb573d18be7f79dfbfdff18b401", 0x51, 0x0, &(0x7f0000000000)={0xa, 0x0, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x0}, 0x1c)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bind$inet6(r0, &(0x7f0000001000-0x1c)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x3}, 0x1c)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_MAX_BURST(r0, 0x84, 0x14, &(0x7f0000002000)=@assoc_value={0x0, 0x0}, &(0x7f0000000000)=0x8)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000002f000-0x78)={0x0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x400000000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x4)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfbc000)=nil, 0xfbc000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket$netlink(0x10, 0x3, 0xa)
mmap(&(0x7f0000ff7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ff8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ff9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
writev(r1, &(0x7f0000ff9000)=[{&(0x7f00007a2000)="8b0a751cf64142d7f558ea081c550455f3659cab6747192d2e963e1385b02f4d1b9b26020e383c8815d69a47b195149564f270f52c36cd7e871d163ac9cc88c866a09025e262a9a012737c685bdd29a02991279de2665f02c0b6bf2798ca9b00f6cddb3e0c79d3af832ccb584698972131144a3851bdead7dc6fe3168c56390ccad5dc718697d31a08a06c7bd11d368722649dfa98c0aa20458468c315ab0468de7dc0cb48efdab27bb27f07a9", 0xad}, {&(0x7f0000d0a000)="adadc06927bf27d4ddb0c074a3bcf2f1a3621c73ed763ffe8fa4ad5dea5685b4c3b4b950ce0be9171ddff9c96f70fa153186449c4fa1644e35928d63df252073baabc4a5eebd5a73ba55cc95d57581e55b1cebe3bda1c2e3e078c7f86669cf97ae671df5f4adbc3fb12682f454d8fbebf57b9f09eacd5da2761dac5a88a2935745ebaf72d85fff466e69730a79d4b74c51ce9ce44f45a7322933e40e1354e0dd91e48212cd72d4a8b21ff4e7313455a4c224db30a9bc7ddb91f4c0f2ebec76fa47d2802d7e58a876e435510c2d2e565e4646d60c91acd4d55d1933a72c51799eaf912aa1", 0xe4}, {&(0x7f0000ff8000-0xa5)="ca94c70cf8d280c4156896de070f2034d610f8f557e1c660ca8b473ab858010ccac39c3664a7ccf2d781183b28fef492c67b59c2b23dc8937b6d821b06b1310df2dba8928db0ef4a333c1f92fc1cea87a248c1980e0150f7a218b2026cdb8c3deda7d5081ab0460068b454567901558af1664b1bdaeb670955e8c3d041f5d4e30085d1a1bc081be4caaaa2a600f19322a0f86022945ff6b70f8130b8dad7894cadc4a1ca06", 0xa5}, {&(0x7f0000b12000-0x9b)="6d4169c91f5620b832e84e2268e3174d9892ac20df004923f9bb9f5f55f98826c5e9c2cabfb0ce74f83c259af2502a6bf45dd852bcef17a5ef3f06879cfc560abcb6932e43be95cb65a19221c654737da38b19c9eb1026e6bc6f92f10ac492f3d34280d5da8e01a7bd683589f91da77bc8999fbdce48cda0acf9eb25bc046c435ef7bee5245953635bbd6878f10443956cef1797e10a1e1cb5668d", 0x9b}, {&(0x7f0000ff8000)="9c23a61dacde0f1230b4f14de9e2f3e640d88184ae9c4d4c29778cc21b4092f2657e1f5a93e622c0c32bfe5df3c0d1dc147e4dde054b650a070ecc8fca26c9d539", 0x41}, {&(0x7f0000f59000)="905d70272671ccd09e1a78ae90180f731c6a68d01daa907cfcabd0d11c280d1cda10a3c7eb7a811e3178892b9cdc837522b58da769337d84cffa0a3a548f0058c7418a628a360dbc177d1b72a5027ce632c3c9d138108f6eef3456c2bb7ac9d99c712e91d35ecd88acc9e31cb5da9dac319f443a59de7295", 0x78}], 0x6)
r2 = socket$netlink(0x10, 0x3, 0x100000000000000c)
dup3(r2, r1, 0x80000)
bind$netlink(r1, &(0x7f0000fb5000-0xc)={0x10, 0x0, 0xff, 0xa9cc}, 0xc)
creat(&(0x7f000041c000-0x8)="2e2f66696c653000", 0x100)
[ 50.074875] binder: 7168:7171 ERROR: BC_REGISTER_LOOPER called without request
[ 50.082329] binder: 7171 RLIMIT_NICE not set
[ 50.106563] binder: 7168:7171 got reply transaction with no transaction stack
[ 50.115474] binder: 7168:7171 transaction failed 29201/-71, size 24-8 line 2747
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x80000e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
syz_emit_ethernet(0x2605, &(0x7f00002ba000)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [], {{0x86dd, @ipv6={0x0, 0x6, "43f0ca", 0x25cf, 0x3a, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, {[], @icmpv6=@pkt_toobig={0x2, 0x0, 0x0, 0x4, {0xbc, 0x6, "c4b8fe", 0x2, 0x32, 0x5, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, [@dstopts={0x3a, 0x23, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [{0x7, 0xfe, "bb2a9c28e52c888afd53e373895bb4e7ac2e3d998a48d9a0347f66926c79c7ce7717fe5f229e50aca747037ae9be27fd495bd7c3cd2e8dc15fb6462c59ff8286811234ae5047c8f2dfb3f7df7718db6c44b6ab4e160afd9759700064cc0c8aa16e45724f2ade63cf28cc43987f1da06e0ac88b9f51f4068c7a5388699fb706bc969031856eba28cfff05cdf1f7b9b5d5f8868df16c8fe3a7feadaf455ea4c0b3910291e62a019a64e422f1ff6c7f2f6e4aa54aa6c14e51b7519609495b670304607a5f04a7c1ce5f16c5f19e058671db2f8acba93b3eef70454c4308473268201c1b35611a0735498c31f980d0aa33245ea6f02c9b6ebbe082e3546eeda9"}, {0x7, 0x16, "620d63c049cdeeba4cfbf2ecbb23a38b93e92e9bc943"}]}, @hopopts={0x2f, 0x480, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [{0xcf, 0x1e, "fed02d8ca24ae742a28cf062a1ddbf4ed034e17f163a570d9715b1ad729c"}, {0xc9, 0xfd, "51505b8815b3661db18a27f05ebbd29e76f25a50c09f5678beecf26ebf9c754ed8490b185fc0b59de6094120318b760a56ccc53d38a15134f481e52083175c757de5eaf8651f5a94c8d827a2889f263d25166edea65f3e975330665c4d8575c7ada04da11a4e45b2364cf40e712840bd7ce155ce5c883493a7408526cee557cfef99d745c55f6e02540af883ddcf0d268e6faf08c324cfc92ae13d2aecf7f1f6b015a094ec38525a8e22758ab55eae5aa1a839d7636fa27af9f1e83bf51efb75b9e5ba971fd5fe45a592cf87eb6f7f51c26d7b507ce61feca877cc579d2dd6ce4b2d655777961d3d271327f830c5fdb1cd26afb3fca9ce72b51ba0f305"}, {0xff, 0x76, "1dd3a037d08e9d23009cf8886fa4f79586d1dd024597b7b07b5c0eb511ff4d0e386cce93124935cc0ff41bdce144c2d3e7d7d7b4fd08a791cdd9d379843f8bec3b81fd28f8c2b073e2e2cda3a1d7e56c7fe7318f42191fef9468531e1c9d2f4a4bea16eae66a3a64f3a7f6752b7aacd7438893b70160"}, {0x5, 0x1000, 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{0xc7, 0xe3, "e56c2b1bbcce7f112db276397ce8b8c54206fa317bbd92fde87e6490cb6f1f4fcc344989f3e24be91ff9f52d6871effd51eda707120d914982df76612e24b7893a6ecfea0b2edd7be931b5876a215386fe0991adae4aa34a3f7613423d70d9b1508b778f14cef251c81e14ee0715bae3b53f5109ec0c98106dbf7b3b01c68c82c8b7e71005283b0b82339d85727a4a3922c43a6d37bdfe592db42d7aba2f4248402ea4c5bf1a645e9edc86a7ee33f4ddf313ed639195ddba52921d3a1ee179ae57bc66b081310f6c638ad6d38328c004f38606f79ae88b8b4b57420acf6cd9481fa92c"}, {0xcf, 0x30, "c16043e4c25b577d4642c157ace3baf1ddaf20ee284682e37b64ad2a4e0a5edac9129b0a0bd1682868344981c0ac6b4b"}]}], "06eac2ad2f972ecba266efb34c1010e53d04fee9059a0b45c3fae797586d664b8414e9d0d788efbb5986393aa04e6294db4095029cceafdc4fbc8c2982e7493de8bddead9613db25c27614254f72e148cca5c04d2dd7b539e4b1a589d1dfda7a0201f1937f13bb97679de696a3d9c8"}}}}}}}, 0x0)
r0 = gettid()
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TIOCGSID(0xffffffffffffff9c, 0x540f, &(0x7f0000279000)=<r1=>0x0)
r2 = syz_open_procfs(r1, &(0x7f00003cd000-0x8)="6e65742f6c6c6300")
getsockopt$inet_sctp_SCTP_INITMSG(r2, 0x84, 0x2, &(0x7f0000ec2000)={0x0, 0x0, 0x0, 0x0}, &(0x7f000062c000-0x4)=0x8)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000, 0x0, 0xf74, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r1, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
unshare(0x800000)
r3 = open(&(0x7f0000107000-0x8)="2e2f66696c653000", 0x20000, 0x148)
ioctl$KVM_SET_LAPIC(r2, 0x4400ae8f, &(0x7f0000cb0000)={"4c6b6bb3902c066d03de26db900bc653a080b38a268861d9414a4d7a9dc12a3e646cd2f2579735ab15da0e18bafd8abdcc3a5e6ee2e401da858eca77bef5da823207703a175b4f91878584bfbbfa4a6e14819e83bec6af962432c1cc74f4ce02b2c0991765086dbc20011dd41000322c0b2426a858e1b3b893e15913f3fd7f1c3660d0b46c24e63fc5998bf75e1688275bb0c96ad01e12efdd14eb243375a396c5c880b206b82776099bfd34be6011c2e00e7ab80d466e00e62996edf1c73b0709c53ad377cdf87fadcc4b662841df157b5ce54b300921e1253b5f56db5a1e8e7fa71f15ea8166d4d6a1710cc14af2866de740411d947c47bab031763799dc5b98a40a2399f221f7d9a51264573d7bc7cd91fc683a4cf4a578e07e4a27c0860835e98b2844c1570f1199db191005188bdf0a417d6744236a7291c4de730fb37f4c7e4eea7a31cf50d49695b63a20e5a2a596ce16741264607f3a87e9fc835a5bd4c211349b02cbd19fd9be695fe6d7d87aa1ae1d8cc41508463dfade51649799b86343d6a95c990bd79fb7047a10682c0db43fbbfe5bb39c22597148223f999ac8a61a25c69c7f793ffec9f50a730ddee67416fea31671444df7da6dded80c61cf301180e0cece82937fa7491f0694b268bcdb32d6bdc8e59abbfd8943efb75bae061b9961056219f5c0f0dc4f24b55d2d9b23272e6feb99e708e6e4bb75ef8a6a0555052c4eb9a7386bbf4f9e40cffc72447afe109db3dbe90c48e6ad94ccd548d8a973673eb61610021661dc9011d4ca9312c041bbec3b94f3ef7f736dd70df8106c86325e4da368f53467995085a62225c6660f7ae5358508d04d19ddbd310e10495f427a80683ea51517f4c2d7fadc874d37bcfddc0c1cec545c2b89243b444c9305b4c26f2ae25555b5dcdc2263d417d226baab361e9aa21776f954939a347eef56164dec3a22a7192c426cadae1b6729d8eb7633a3ac01ca3dead876c09e7f8c7b0710d292466bccea6e11051886f6d96a6294876164ed929a469f23ca1239704857bcfd8d7e26b35b9fcc17120b7870ecb773f4402ee1e52451f3bb7a25ad4e2ae056e6f535e53da444cc38cf98e5be624c9b4fa0d0cf59b117da48d9c2ac18f1cc081c60a8347270278daa47312e23d97c8820db526f59f2bbfa1f917be9a9fd42a88fc2dd05ffb0ca65f444f53852891bafa60853996c6c0176ab1e4b2d495f583172beda986c278b95a48ac30a7883ac3720f849bdf03cd87acb0ce468af91f9140deea6f80665624415044685cafa4ad82ce2bba733c8c4905c6ee122024d588afc0bb42f585197dff73831039463697bae6c74a99015b09dc882712d9cc5dbb748d27d6b6b2923c1b1f0614c9d18401c1918d041491d4f05aabe7bcacc83c6fba05f011bf10cabaecb307f52f46fa30a581fe7f06ed59a3967e0"})
ioctl$EVIOCGMASK(r3, 0x80104592, &(0x7f0000a32000-0x10)={0x11, 0xb7, &(0x7f0000ad0000-0xb7)="9025eda6a20d259784d112ed72cfacd5d87ab024b83f3207b517301642b1f3b7dba9d780485dec96cda8d3aeffa8a00cf89437eaf959c9e12a82bddd7aad89efd9f9d9d6b2f48f45ef6cfdde61c8b3ea318fc5cf46888e360ffad94a224c30b489fb6190dee72c0693738395b0e524792e7fab3e14d7ba398b8b57490e49f055611f28fd9abb6ef1cb86457d52c25cc805784170f0781ba2bcde1a93812d0b0cff3da03d7913d36ce4a1162a66ace5b803e0eb3c6b2af6"})
socket$unix(0x1, 0x1, 0x0)
getsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX3(r2, 0x84, 0x6f, &(0x7f0000d7b000-0x10)={<r4=>0x0, 0x94, &(0x7f000086f000-0x94)=[@in={0x2, 0x3, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x0, 0x8, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0xfffffffffffffffc}, @in={0x2, 0x1, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x10000, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x81}, @in6={0xa, 0x1, 0x200, @loopback={0x0, 0x1}, 0x2}]}, &(0x7f0000bbc000-0x4)=0x10)
getsockopt$inet_sctp6_SCTP_PEER_ADDR_THLDS(r2, 0x84, 0x1f, &(0x7f00007c5000)={r4, @in6={{0xa, 0x0, 0x1, @loopback={0x0, 0x1}, 0x800}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7, 0xfffffffffffff801}, &(0x7f0000e9f000-0x4)=0x98)
socketpair$unix(0x1, 0x5, 0x0, &(0x7f000000b000-0x8)={0xffffffffffffffff, 0xffffffffffffffff})
semget$private(0x0, 0x3, 0x0)
semop(0x0, &(0x7f0000000000)=[{0x0, 0x100000000, 0x1000}], 0x1)
unshare(0x8000000)
perf_event_open(&(0x7f0000934000-0x78)={0x2, 0x78, 0x7, 0x0, 0x40, 0x0, 0x0, 0x0, 0x0, 0x3, 0x18000000000, 0x7, 0x3, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x5, 0x0, 0xfffffffffffffffe, 0x0, 0x0}, r0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x200000002, 0x78, 0xc56b, 0x100000001, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e7, 0x0, 0x0, 0x0, 0x0, 0x100000000000000, 0x0, 0x2, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
syz_emit_ethernet(0x34, &(0x7f0000c94000-0x70)={@random="6c014764b69b", @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [{[{0x9100, 0x2, 0x6, 0x1f0}], {0x8100, 0x2, 0x3940, 0x200000007}}], {{0x8809, @llc={0x1c, @llc={0xfe, 0xdc, "d62e", "70c2236e67542df2416448ac2b830d8391d2d4054116a7a9"}}}}}, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000e2d000-0x78)={0x2, 0x78, 0xd4e7, 0x0, 0x4, 0x0, 0x0, 0xfffffffffffffffd, 0x200000000, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x10000000, 0x0, 0xffffffffffffffff, 0x0, 0x0, 0x3, 0x0}, r0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
syz_open_dev$sg(&(0x7f000006c000-0x9)="2f6465762f73672300", 0x4, 0x101380)
syz_emit_ethernet(0x42, &(0x7f000097b000)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [{[], {0x8100, 0x78, 0x7000000000000000, 0x8}}], {{0x20086dd, @ipv6={0x0, 0x6, "a228af", 0x8, 0x2c, 0x6, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, {[], @udp={0x0, 0x0, 0x8, 0x0, ""}}}}}}, 0x0)
2017/12/15 11:53:26 executing program 1:
r0 = socket$inet_sctp(0x2, 0xffffffffffffffff, 0x84)
perf_event_open(&(0x7f0000d21000-0x78)={0x2, 0x78, 0x44, 0x2, 0x0, 0x100000000, 0x0, 0x0, 0x40, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x6, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0xafb000)=nil, 0xafb000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$kvm(0xffffffffffffff9c, &(0x7f0000002000)="2f6465762f6b766d00", 0x4000, 0x0)
r2 = ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
r3 = ioctl$KVM_CREATE_VCPU(r2, 0xae41, 0x0)
ioctl$KVM_SET_MP_STATE(r3, 0x4004ae99, &(0x7f0000932000-0x4)=0x0)
ioctl$KVM_SET_SREGS(r3, 0x4138ae84, &(0x7f0000af3000-0x138)={{0x0, 0x0, 0xd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0xf001, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0xd000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, [0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_SET_VCPU_EVENTS(r3, 0x4040aea0, &(0x7f000096b000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0xffffffffffffffff})
getsockopt$inet_sctp_SCTP_RECVRCVINFO(r0, 0x84, 0x20, &(0x7f00006b5000-0x4)=0x0, &(0x7f0000342000-0x4)=0x4)
ioctl$KVM_DEASSIGN_DEV_IRQ(r2, 0x4040ae75, &(0x7f0000f77000-0x10)={0x100000000, 0x800004, 0x1000, 0x1})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$ipx_IPX_TYPE(r1, 0x100, 0x1, &(0x7f0000001000)=0x8, 0x4)
ioctl$KVM_CREATE_IRQCHIP(r2, 0xae60)
flock(0xffffffffffffffff, 0xa)
ioctl$KVM_RUN(r3, 0xae80, 0x0)
ioctl$KVM_GET_XSAVE(r3, 0x9000aea4, &(0x7f0000928000-0x400)={"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"})
ioctl$KVM_GET_IRQCHIP(r2, 0xc208ae62, &(0x7f0000d14000)=@ioapic={0x0, 0x0, 0x0, 0x0, 0x0, [{0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}]})
ioctl$sock_inet_SIOCGIFDSTADDR(r0, 0x8917, &(0x7f0000a10000-0x20)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_flags=0x4000})
ioperm(0x800000005, 0x800004, 0x0)
ioctl$KVM_TPR_ACCESS_REPORTING(0xffffffffffffffff, 0xc028ae92, &(0x7f0000c7e000-0x28)={0x0, 0x4, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
exit(0x3)
ioctl$KVM_GET_REGS(r3, 0x8090ae81, &(0x7f00007e1000)={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0})
ioctl$KVM_RUN(r3, 0xae80, 0x0)
ioctl$KVM_GET_SREGS(r3, 0x8138ae83, &(0x7f0000679000-0x138)={{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, [0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_SET_CPUID(r3, 0x4008ae8a, &(0x7f0000a53000-0x3f)={0x4, 0x0, [{0x7, 0x800, 0x1, 0x100000000, 0x5, 0x0}, {0x6, 0x7, 0x0, 0x1ff, 0x200000008, 0x0}, {0x4, 0xfffffffffffffff7, 0xfd, 0x40, 0x5, 0x0}, {0x80000019, 0x521, 0x0, 0xfffffffffffffffe, 0x5, 0x0}]})
r4 = socket(0x10, 0x802, 0x0)
getsockopt$inet_IP_XFRM_POLICY(r0, 0x0, 0x11, &(0x7f0000a44000-0xe8)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r5=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0}, 0x0, @in=@broadcast=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f000045e000)=0xe8)
recvfrom$packet(r4, &(0x7f000089f000-0x95)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x95, 0x10020, &(0x7f0000130000-0x14)={0x11, 0xfb, r5, 0x1, 0xf87, 0x6, @random="5dd10f232178", [0x0, 0x0]}, 0x14)
2017/12/15 11:53:26 executing program 4:
mmap(&(0x7f0000000000/0x4000)=nil, 0x4000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket(0x40200000026, 0x1, 0xfffffffffffffffe)
getsockopt$sock_int(r0, 0x1, 0x26, &(0x7f0000001000-0x4)=0x0, &(0x7f0000000000)=0x4)
getsockopt$inet_sctp_SCTP_DEFAULT_PRINFO(r0, 0x84, 0x72, &(0x7f0000003000)={<r1=>0x0, 0x7fff, 0x30}, &(0x7f0000004000-0x4)=0xc)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp6_SCTP_ADD_STREAMS(r0, 0x84, 0x79, &(0x7f0000005000)=0x4, 0x4)
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_SIOCINQ(r0, 0x541b, &(0x7f0000007000-0x4)=0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_AUTO_ASCONF(r0, 0x84, 0x1e, &(0x7f0000004000-0x4)=0x0, &(0x7f0000008000-0x4)=0x4)
r2 = openat$vcs(0xffffffffffffff9c, &(0x7f0000006000-0x9)="2f6465762f76637300", 0x400, 0x0)
ioctl$KVM_PPC_GET_SMMU_INFO(r2, 0x8250aea6, &(0x7f0000004000-0x2a)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
ioctl$KVM_SET_SIGNAL_MASK(r2, 0x4004ae8b, &(0x7f0000002000)={0x88, "fb65c06edd713bd7b1ccffe578efb5f18b082f5213ab15830d0cd1140c2788f002a5725efba37aac3fd639cac9e70fba7fc3ad67fa93729903f93701c9c64955312adcda60089984fc7943cb3bf5ee851841936596b32cb224ed4e25745ea14881c08315b68a4f8120f425dc9d84e62e11c01ea77c641fb9b9125112abb346e6e1190cfb8aa63983"})
r3 = add_key$keyring(&(0x7f0000001000)="6b657972696e6700", &(0x7f0000002000-0x5)={0x73, 0x79, 0x7a, 0x2, 0x0}, 0x0, 0x0, 0xfffffffffffffffe)
request_key(&(0x7f0000000000)="6173796d6d657472696300", &(0x7f0000005000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, &(0x7f0000005000-0x18)="766d6e6574312f73656375726974792673656c696e757800", r3)
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$vga_arbiter(0xffffffffffffff9c, &(0x7f0000006000)="2f6465762f7667615f6172626974657200", 0x200b40, 0x0)
bind$unix(r2, &(0x7f0000004000)=@file={0x1, "2e2f66696c653000"}, 0xa)
setsockopt$inet_sctp6_SCTP_PEER_ADDR_PARAMS(r0, 0x84, 0x9, &(0x7f0000002000-0xa0)={r1, @in6={{0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x80000001}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x8, 0x1, 0xffff, 0x10001, 0x46}, 0xa0)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$sg(&(0x7f0000000000)="2f6465762f73672300", 0x98, 0x40000)
ioctl$KVM_GET_DEBUGREGS(r0, 0x8080aea1, &(0x7f0000bbc000)={[0x0, 0x0, 0x0, 0x0], 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$llc(r0, &(0x7f0000001000)={0x1a, 0x7, 0xfffffffffffffffc, 0x18, 0x1, 0x5, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, 0x10)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$selinux_avc_hash_stats(0xffffffffffffff9c, &(0x7f0000002000)="2f73656c696e75782f6176632f686173685f737461747300", 0x0, 0x0)
mknod(&(0x7f0000002000-0x8)="2e2f66696c653000", 0x7, 0x1)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = msgget$private(0x0, 0x80)
ioctl$PIO_UNISCRNMAP(r1, 0x4b6a, &(0x7f00009b3000)="809562bd8cf415b8f70b3adf195f9a61a93abc98719d0d0577ffaccb566da34fd6ce1dd08d7c754caa0ab7932b16facf41aaee66b4834c0c2da8c44c22fcd6ab85690f8d4972136ecf2d2a34419e612194c8")
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f0000294000)={0x0, <r3=>0x0, 0x0}, &(0x7f0000a3b000)=0xc)
r4 = getegid()
chown(&(0x7f0000862000-0xe)="2e2f66696c65302f66696c653000", r3, r4)
msgrcv(r2, &(0x7f000030f000)={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0xe9, 0x3, 0x1000)
ioctl$TUNSETIFF(0xffffffffffffffff, 0x400454ca, &(0x7f0000a5b000-0x28)={@generic="41a2d2c80c8303e6c85bfc7eca0be519", @ifru_names=@generic="5101c313d25cbe75d715aefe0e29175b"})
ioctl$TIOCMGET(r0, 0x5415, &(0x7f0000c3e000-0x4)=0x0)
msgsnd(r2, &(0x7f0000c97000-0x3a)={0x0, "521b5ddb46b59ebf77320474b0990743342498b80a1b2178e10b87cfebb973de8ae2e8eb542b1fe973925c2047c2bb5f0c9b"}, 0x3a, 0x800)
[ 50.130852] binder: 7168:7182 BC_FREE_BUFFER u0000000000000000 no match
[ 50.130868] binder: 7168:7182 IncRefs 0 refcount change on invalid ref 1 ret -22
[ 50.130874] binder: 7168:7182 got transaction to invalid handle
[ 50.130881] binder: 7168:7182 transaction failed 29201/-22, size 72-8 line 2832
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet_icmp_raw(0x2, 0x3, 0x1, &(0x7f0000001000-0x8)={<r0=>0x0, 0x0})
fchmod(r0, 0x8)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_PROG_GET_NEXT_ID(0xb, &(0x7f0000b32000-0x4)=0x1f, 0x4)
writev(0xffffffffffffffff, &(0x7f00005ce000)=[], 0x0)
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
seccomp(0x1, 0x0, &(0x7f00007f8000-0x10)={0x1, &(0x7f0000ed2000)=[{0x6, 0x0, 0x0, 0x407ffc0003}]})
socketpair$inet(0x2, 0x800005, 0x800000006, &(0x7f0000223000-0x8)={0x0, <r0=>0x0})
r1 = semget$private(0x0, 0x1, 0x81)
madvise(&(0x7f0000ce1000/0x1000)=nil, 0x1000, 0x4)
semctl$GETZCNT(r1, 0x0, 0xf, &(0x7f0000466000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$inet_tcp(0x2, 0x1, 0x0)
rt_sigaction(0x1f, &(0x7f0000743000)={0x1, {0x3}, 0x4, 0x94}, &(0x7f00003f8000)={0x0, {0x0}, 0x0, 0x0}, 0x8, &(0x7f0000707000)={0x0})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f0000025000-0xa)="2e2f636f6e74726f6c00", 0x0)
r2 = open(&(0x7f0000963000-0xa)="2e2f636f6e74726f6c00", 0x100, 0x0)
mkdirat(r2, &(0x7f000000b000)="2e2f636f6e74726f6c00", 0x0)
removexattr(&(0x7f00000ba000-0xa)="2e2f636f6e74726f6c00", &(0x7f0000dff000-0x15)=@known="73797374656d2e736f636b70726f746f6e616d6500")
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
memfd_create(&(0x7f0000f4b000)="202a", 0x1)
ioctl$sock_SIOCGIFINDEX(0xffffffffffffff9c, 0x8933, &(0x7f0000000000)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
perf_event_open(&(0x7f0000271000)={0x6, 0x78, 0x7f, 0x2, 0x8000, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x40, 0x0, 0x0, 0xffff, 0xfffffffffffffffc, 0x9, 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x40, 0x9, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0xfffffffffffffffc)
r3 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r4 = socket$inet6(0xa, 0x2, 0x0)
bind$inet6(r4, &(0x7f0000c97000)={0xa, 0x0, 0x4, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x3}, 0x1c)
setsockopt$sock_int(r0, 0x1, 0xf, &(0x7f0000f5a000-0x4)=0x100000000003, 0x4)
r5 = socket$inet6(0xa, 0x6, 0x0)
setsockopt$sock_int(r5, 0x1, 0xf, &(0x7f0000d1c000)=0x8, 0x4)
bind$inet6(r5, &(0x7f0000f5e000-0x1c)={0xa, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
connect$inet6(r5, &(0x7f0000f67000)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x0}, 0x1c)
connect$inet6(r4, &(0x7f000047d000)={0xa, 0x2, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, 0x1c)
dup3(r3, r4, 0x200080000)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x215000)=nil, 0x215000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000215000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = accept$inet6(0xffffffffffffff9c, &(0x7f000020f000)={0x0, 0x0, 0x0, @remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0}, &(0x7f0000215000)=0x1c)
ioctl$sock_inet6_tcp_SIOCINQ(r0, 0x541b, &(0x7f0000152000)=0x0)
r1 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r1, &(0x7f000007e000)={0x26, "726e670000000000000000000000", 0x0, 0x0, "647262675f70725f7368613531320000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$ALG_SET_KEY(r1, 0x117, 0x1, &(0x7f0000080000-0x91)="9fa0291e41797c3d71854a9fe2cd858674c82988348b5ca3a6103d5ca1cb9eef", 0x20)
r2 = accept$alg(r1, 0x0, 0x0)
setsockopt$SO_TIMESTAMPING(r1, 0x1, 0x25, &(0x7f000014c000+0x34a)=0x2, 0x4)
mmap(&(0x7f0000216000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000219000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000021a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000021b000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000021c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000021d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000021e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmsg$alg(r2, &(0x7f00001b1000)={0x0, 0x0, &(0x7f000021e000)=[{&(0x7f0000216000)="3c14fbbec62ca02b3a4952db57337b8b1d3ae67b043b003c", 0x18}, {&(0x7f0000217000)="952fa5b47c097b2e8fbd028b55073b08c5a80cc308cb6f6c14c669836e60139812dc0894aef3b20c6bd24f49ba2e015f2a69ffd5e4", 0x35}, {&(0x7f00000d5000)="4f50757930f032a8ba41ae6fa20a00843ecce9cfd3db103ab0343f095777c9ef20459cddf58915554f07e6e4e3036566e46f57d72d8ed6df37f9a7e82be3742139aa52e1", 0x44}, {&(0x7f0000218000)="b352f97a0439f3c4595815e3228f24556b850000b7127c5f81a2abccdb305a81a64206d6bfeef6e23626171a9ecea84ad7ff4e9c42d93690e8ac56069654657be8e88c91ccc6bbd2f73651414e06f4dd09e9b02dfb481bef392cef795b59a5e520c4d613c3f2bf0d0645b2b3f2b2d297d23422cc2ee9897261b276c552375b47f54160ec0daeb26e2bf611399002573de58f4c681c00c0c072e5e3b5577a0f122a06d9e886a926a6fb840c1fa4eaff4c9e5f64c808453d76d86ad7cc5bae66be91fb7fc4d0bb2302d9c613052bc04a0d5192c5dfe847ee08d03d913085ddf05c6290738143a51158fa4fc91d15110962d60b2e1c", 0xf4}, {&(0x7f00001af000)="c6d2e767b7aa34bee2992d3825b3f1bec029e9f7b2bcb5bbabedb0a8006e0d10ac4d165bdb178bd71b738394988802fea0986ca3fd5c58b72522b1a07a22977aeac16e35d5cea3ccb0eea0808f50e1be9563fb44d49b67fbae03502919bf56624c4978c68862e1458971537edf0a", 0x6e}, {&(0x7f000021a000-0xd8)="a5411fb20fc52e48f8f93c2e17869d5c1c7ea832f7741482ce7492b0c2bbbf75ef8712e9101ccc5268faaa69eb03d69f06b6a7ed95b29b637279c53a4262531fd67f53b09db0dbd571b3e8b5ec280ef3025b36b01965db735f87ce72dea212b32aa8b3e2e14aaf356640d5f6233fc757e13ac1eff0c2cd9c410d7704f0932545cd394a85fc1f6b5ce2ed576c7bdb69afdcb527ed11f685ffe1282d59b3b88101e9c6e2133393c7f9e7586a0242333a59da2a5b77f7691a90baa884add9f97c20f16b16c7bf1724cbfb5d87a8489a7e8ef5b953ac609d0a05", 0xd8}, {&(0x7f000021b000-0x7)="d1c8effc0cb406", 0x7}, {&(0x7f000021b000)="f5b1898b107754802f2f8f1b4da87d55620d84afbb622c9b55adb74cca8a710b905c6a0d3e448fb3d69ca05851cb0407e6f01f653d9eb7fbeb27f20af6c2b1c5a8aa22996e11c60b43ed8dd1f9a95d1e2eb57d4c215518ee0daa85f67e62c95fbb95b4736e52cd7b302439d06287ee986373f6bc32dbc1e5b52dcd834e87a7a2491141", 0x83}, {&(0x7f000021d000-0xd8)="056204fbd822aa9c4314f243221a5100e8e491fed57f0e36b842ce3776d677db9c47485daf02f854e28c14fd67ffe88954c7b5748b715b4e082766a4321d904e5c972ca0a52f138bc9a27c6ddb09463f859a7469c8892efa7801968c7d178baca6ce5b722a508aa60ea16fdfa397649ba306c3b6826ccc27c73d6a4fcddab829a6a64172e837a1d13f36e66f4ab5fa6e063de4ea3b09fd507dc3701d30fcd1be08b3e085d3c04e1e0a93935b0ba6aae88d102f54c67a036c7e2a7e6a0a27abd38dca8ef3a2f9964241168968b7fd69569aa7abe83cd549d3", 0xd8}, {&(0x7f000021d000)="aa9a1ca151eeef0e68d1e0a96a47304d3747f70e9ae234fffeab7fe8d5928a7c598ef8408ee7244198d1561b34f9d3fc9205085f174b1417a4751396ed7edd46f9ba57b68fd226b071e381b07d7c109acaf54e5bf0f8e60d8bd86a07cb41002676f2eae48a77ceda67e5bbd6d799444645d0baf610790dea556579cc9e98a0aca260287a468a652b96257007f0058720a35c59e5f154579296ad6d93660debbb0d464051cbf4d4ac076bae4ff4971d084fdba1ef88ba7506af308829aa3929a2840fd49861b4db5355", 0xc9}], 0xa, 0x0, 0x0, 0x8000}, 0x0)
mmap(&(0x7f0000216000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000216000)={<r3=>0x0, <r4=>0x0})
mmap(&(0x7f0000216000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000216000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_PRIMARY_ADDR(0xffffffffffffffff, 0x84, 0x6, &(0x7f0000217000-0x8c)={<r5=>0x0, @in6={{0xa, 0x2, 0x6, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x2}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, &(0x7f0000217000-0x4)=0x8c)
mmap(&(0x7f000021f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(r4, 0x84, 0xa, &(0x7f000021f000)={0x2, 0x1, 0x4, 0x6, 0x401, 0x8, 0x7, 0x818, r5}, 0x20)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f000001c000)={<r6=>0x0, 0x0, 0x0}, &(0x7f0000073000)=0xc)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_IP_IPSEC_POLICY(r3, 0x0, 0x10, &(0x7f0000040000-0xe8)={{{@in6=@loopback={0x0, 0x0}, @in=@empty=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r7=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0}, 0x0, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000218000-0x4)=0xe8)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r4, 0x1, 0x11, &(0x7f0000218000-0xc)={0x0, 0x0, <r8=>0x0}, &(0x7f0000218000-0x4)=0xc)
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f00001f4000)=<r9=>0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000220000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r3, 0x1, 0x11, &(0x7f00000f8000-0xc)={0x0, <r10=>0x0, 0x0}, &(0x7f000015b000)=0xc)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$SO_PEERCRED(r4, 0x1, 0x11, &(0x7f0000217000)={0x0, 0x0, <r11=>0x0}, 0xc)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000221000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_FIOGETOWN(r3, 0x8903, &(0x7f0000221000)=<r12=>0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_IP_IPSEC_POLICY(0xffffffffffffffff, 0x0, 0x10, &(0x7f0000218000-0xe8)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in=@local={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r13=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000053000-0x4)=0xe8)
getsockopt$SO_PEERCRED(r4, 0x1, 0x11, &(0x7f00001f8000)={0x0, 0x0, <r14=>0x0}, 0xc)
r15 = getpid()
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_IP_XFRM_POLICY(r4, 0x0, 0x11, &(0x7f0000218000-0xe8)={{{@in=@multicast2=0x0, @in=@empty=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r16=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@loopback={0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000217000)=0xe8)
r17 = getgid()
r18 = getpid()
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000218000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_IPV6_XFRM_POLICY(r4, 0x29, 0x23, &(0x7f0000219000-0xe8)={{{@in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r19=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000217000+0x2cb)=0xe8)
mmap(&(0x7f0000220000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000220000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r2, 0x1, 0x11, &(0x7f000002a000)={0x0, 0x0, <r20=>0x0}, &(0x7f0000220000)=0xc)
mmap(&(0x7f0000217000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmsg$unix(r3, &(0x7f0000218000-0x38)={&(0x7f0000217000)=@abs={0x0, 0x0, 0x1}, 0x8, &(0x7f0000218000-0x20)=[{&(0x7f00000a9000-0x37)="04fff0ee9200e73ee542efd57c4862ba683e70c480acd6f6ac86081f2216d240dcea9b0cfe99a625fe2b203893fcf25f4d23a05bae77dfcb3e42a2381d56cbc73464609e8f56b9a9760bc58b616ccac65b4f1aaba4644e9719efc57f9ec53c4d4210ad5bec33fc3fa70220c65cc4d38b08394805474b057b54f55d2ac4c29d4f94a3909c2027d6fc4bcdf2b089fe55de3a27ebe329e747328d37a31e3bb1e1b01a589fc326b422f5e9210bb583d983508561", 0xb2}, {&(0x7f0000217000)="ecb4e11c903934a02b", 0x9}], 0x2, &(0x7f0000002000-0xd8)=[@cred={0x20, 0x1, 0x2, r6, r7, r8}, @rights={0x18, 0x1, 0x1, [r1]}, @cred={0x20, 0x1, 0x2, r9, r10, r11}, @rights={0x20, 0x1, 0x1, [r4, r0, r4]}, @cred={0x20, 0x1, 0x2, r12, r13, r14}, @cred={0x20, 0x1, 0x2, r15, r16, r17}, @cred={0x20, 0x1, 0x2, r18, r19, r20}], 0x7, 0x40}, 0x80)
mmap(&(0x7f0000220000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000221000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000222000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
recvmsg(r2, &(0x7f0000215000-0x38)={&(0x7f0000215000-0x14)=@ll={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0]}, 0x14, &(0x7f0000089000-0xa0)=[{&(0x7f0000075000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xea}, {&(0x7f0000204000-0x6a)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6a}, {&(0x7f0000054000-0xe2)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe2}, {&(0x7f0000220000+0x29d)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xa8}, {&(0x7f00001f2000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe6}, {&(0x7f0000199000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x3d}, {&(0x7f0000222000-0x35)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x35}, {&(0x7f000020f000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f0000223000-0xd3)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd3}, {&(0x7f0000140000-0xe6)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe6}], 0xa, &(0x7f0000214000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9b, 0x9}, 0x400000000000040)
[ 50.140206] binder_alloc: 7168: binder_alloc_buf size 536870912 failed, no address space
[ 50.140212] binder_alloc: allocated: 8 (num: 1 largest: 8), free: 12280 (num: 1 largest: 12280)
[ 50.140222] binder: 7168:7182 transaction failed 29201/-28, size 536870912-0 line 2947
[ 50.190666] binder: BINDER_SET_CONTEXT_MGR already set
[ 50.190675] binder: 7168:7182 ioctl 40046207 0 returned -16
[ 50.195621] binder: 7168:7182 ERROR: BC_REGISTER_LOOPER called without request
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0xfbe000)=nil, 0xfbe000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = gettid()
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = perf_event_open(&(0x7f0000b30000)={0x7, 0x78, 0xdd, 0x8, 0x0, 0x1, 0x0, 0x0, 0xc2, 0x0, 0xfe, 0xfffffffffffffffe, 0xfffffffd, 0xfffffffffffffffe, 0x0, 0xb76, 0xfffffffffffffffe, 0xfffffffffffffffd, 0x200, 0x404, 0x0, 0x100000, 0x0, 0x1, 0x40, 0x0, 0x0}, r0, 0xffffffff, 0xffffffffffffffff, 0x104)
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000e59000/0x1000)=nil, 0x1000, 0x20003, 0x3f, r1, 0x800000000000000)
r2 = syz_open_dev$evdev(&(0x7f0000626000)="2f6465762f696e7075742f6576656e742300", 0x7, 0x501000)
write$evdev(r2, &(0x7f0000733000)=[], 0x0)
inotify_init1(0x1)
r3 = open(&(0x7f0000001000-0x8)="2e2f66696c653000", 0x50a00, 0x0)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
process_vm_writev(0x0, &(0x7f0000000000)=[{&(0x7f0000fbb000)="", 0x0}], 0x1, &(0x7f0000fc0000)=[{&(0x7f000077d000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x3d}, {&(0x7f0000fc0000-0x1b)="000000000000000000000000000000000000000000000000000000", 0x1b}, {&(0x7f0000227000-0xca)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xca}, {&(0x7f0000f46000)="00000000000000000000000000000000000000", 0x13}, {&(0x7f00008e2000-0xae)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xae}], 0x5, 0x0)
socket(0x400000000000010, 0xa000000a, 0x5)
mmap(&(0x7f0000fc1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = openat$kvm(0xffffffffffffff9c, &(0x7f00009f1000)="2f6465762f6b766d00", 0x4, 0x0)
r5 = ioctl$KVM_CREATE_VM(r4, 0xae01, 0x0)
r6 = ioctl$KVM_CREATE_VCPU(r5, 0xae41, 0xfffffffffffffffd)
mmap(&(0x7f0000fbf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_kvm_setup_cpu$x86(r3, r6, &(0x7f0000884000/0x18000)=nil, &(0x7f0000fc0000-0x18)=[@text32={0x20, &(0x7f0000e59000-0x53)="70c50fdd75e666ba4200b880110000ef66baf80cb8583ec189ef66bafc0cb0feb9800000c00f3235000800000f30660f3880a62a691fe3660f38f6ddc4e24dba950000010026650f01d1660fdb2f660f388227", 0x53}], 0x1, 0x6, &(0x7f0000fbd000-0x20)=[@cr4={0x1, 0x20000}, @flags={0x4, 0x1001}], 0x2)
r7 = ioctl$KVM_CREATE_VCPU(r5, 0xae41, 0x5)
mmap(&(0x7f0000fc2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_X86_SETUP_MCE(r7, 0x4008ae9c, &(0x7f0000265000)={0x11, 0x0, 0x0, 0x0})
ioctl$KVM_SET_SREGS(r7, 0x4138ae84, &(0x7f0000012000-0x138)={{0x0, 0x0, 0x0, 0x0, 0x9, 0x0, 0x1, 0x2, 0x0, 0xfffffffffffffffe, 0x0, 0x3, 0x0}, {0xfffffffffffffffc, 0x2, 0x0, 0x4, 0x0, 0x0, 0x0, 0x7, 0x80000000, 0x9, 0x0, 0x0, 0x0}, {0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x40000000000, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x7fff, 0x81, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0}, {0x0, 0x1, 0x0, 0x80, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x101004, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x6, 0x0, 0xfffffffffffffbff, 0x3e, 0x0, 0x0}, {0xf000, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, [0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fbe000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_MODE_GETRESOURCES(0xffffffffffffffff, 0xc04064a0, &(0x7f0000e0d000-0x40)={&(0x7f0000417000-0x1c)=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], &(0x7f00004d3000-0x4)=[0x0], &(0x7f0000fbf000-0x4)=[0x0], &(0x7f0000fbf000-0x14)=[0x0, 0x0, 0x0, 0x0, 0x0], 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, 0x0, 0x0})
ioctl$KVM_SET_VCPU_EVENTS(r7, 0x4040aea0, &(0x7f000017a000-0x1c)={0x101, 0x8, 0x4000000000006b7c, 0x0, 0x4, 0x3, 0xff, 0xffffffffffff8000, 0xffffffffffffffff, 0x10009, 0xfffffffffffffffc, 0x4, 0x0, 0x4, 0x100000001, 0x79, 0x3, 0xfffffffffffffff9, 0x40000000000002})
ioctl$KVM_X86_SET_MCE(r7, 0x4040ae9e, &(0x7f0000019000)={0xaac75d3986ff5ebf, 0x1, 0x7fffffff, 0x1, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0, 0x0]})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r8 = timerfd_create(0x7, 0x80000)
sched_rr_get_interval(r0, &(0x7f0000825000)={0x0, <r9=>0x0})
timerfd_gettime(r8, &(0x7f00007b9000-0x10)={{0x0, 0x0}, {0x0, 0x0}})
getrusage(0x0, &(0x7f00002d0000-0x90)={{<r10=>0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
timer_settime(0x0, 0x1, &(0x7f0000274000)={{0x0, 0x989680}, {0x0, 0x989680}}, &(0x7f0000aeb000-0x20)={{0x0, 0x0}, {<r11=>0x0, 0x0}})
timerfd_settime(r8, 0x3, &(0x7f0000005000)={{r10, r9}, {r11, 0x0}}, &(0x7f000000f000)={{0x0, 0x0}, {0x0, 0x0}})
timerfd_settime(r8, 0x0, &(0x7f000000b000)={{0x0, 0x0}, {0x800010000, 0x0}}, &(0x7f000000c000-0x20)={{0x0, 0x0}, {0x0, 0x0}})
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$kvm(0xffffffffffffff9c, &(0x7f0000aeb000-0x9)="2f6465762f6b766d00", 0x0, 0x0)
r1 = ioctl$KVM_CREATE_VM(r0, 0xae01, 0x0)
r2 = eventfd2(0x0, 0x0)
r3 = syz_open_dev$vcsa(&(0x7f0000626000-0xb)="2f6465762f766373612300", 0x80, 0x8000)
setsockopt$bt_hci_HCI_TIME_STAMP(r3, 0x0, 0x3, &(0x7f000058e000-0x4)=0xdaa5, 0x4)
r4 = eventfd2(0x0, 0x0)
ioctl$KVM_IRQFD(r1, 0x4020ae76, &(0x7f0000081000-0x20)={r2, 0x0, 0x2, r4, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r5 = eventfd2(0x0, 0x0)
sendmsg(0xffffffffffffffff, &(0x7f0000fbe000-0x1c)={&(0x7f0000353000-0x80)=@generic={0x0, "32e7057c439b7416e63747300fb4e0a9d7c9f8e94c4f7f4d9b642988ebb7639d2fde327a99dd3b221e168c56571335b66b84ba46589657791d60817c68d8e2a15cf6c542968e3ec68bed67affa767812cf9360a9248914013e3413437a116359e519dc19bf743824ff9999f60d31c39444b395c694dc595ad8bc5e927e2f"}, 0x80, &(0x7f00001c8000-0x8)=[], 0x0, &(0x7f0000fbe000-0x5a0)=[], 0x0, 0x0}, 0x20000000)
r6 = open(&(0x7f0000d2e000-0x8)="2e2f66696c653000", 0x2000, 0x0)
getsockopt$packet_int(r6, 0x107, 0x1f, &(0x7f0000e6d000-0x4)=0x0, &(0x7f00006bf000)=0x4)
setsockopt$nfc_llcp_NFC_LLCP_RW(r6, 0x118, 0x0, &(0x7f0000d9c000)=0x6, 0x4)
ioctl$KVM_IRQFD(r1, 0x4020ae76, &(0x7f000034c000-0x20)={r5, 0x5, 0x2, r4, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_IRQFD(r1, 0x4020ae76, &(0x7f0000fc2000-0x20)={r4, 0x0, 0x100000100000002, r2, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
fcntl$getflags(r2, 0xb)
openat$selinux_avc_cache_threshold(0xffffffffffffff9c, &(0x7f0000792000)="2f73656c696e75782f6176632f63616368655f7468726573686f6c6400", 0x2, 0x0)
[ 50.195629] binder: 7182 RLIMIT_NICE not set
[ 50.195663] binder_alloc: 7168: binder_alloc_buf, no vma
[ 50.195678] binder: 7168:7208 transaction failed 29189/-3, size 0-0 line 2947
[ 50.198075] binder: 7168:7208 BC_FREE_BUFFER u0000000000000000 no match
[ 50.198093] binder: 7168:7208 IncRefs 0 refcount change on invalid ref 1 ret -22
[ 50.198099] binder: 7168:7208 got transaction to invalid handle
[ 50.198106] binder: 7168:7208 transaction failed 29201/-22, size 72-8 line 2832
2017/12/15 11:53:26 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f00008a8000-0x78)={0x4000000002, 0x78, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x200000000, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = socket(0x40000000015, 0x5, 0x0)
setsockopt$sock_int(r0, 0x1, 0x27, &(0x7f0000bf9000)=0x4000000000000, 0x4)
bind$inet(r0, &(0x7f00008a6000-0x10)={0x2, 0x0, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
sendto$inet(r0, &(0x7f000056a000)="00", 0x1, 0x0, &(0x7f0000dfd000-0x10)={0x2, 0x0, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
sendto$inet(r0, &(0x7f0000fc3000-0x1000)="ba671368d1434e64c449605bdbbfca6d2b9f8be49e9301442865319997d0efdb2f54b6a10c7327757482bfce945c2a91fb8dfafc1d3f56bc543ab87321e12cca08a744a2d128b00634bc882151d36809229a96bc3437ef159489384ade077ba295eac2882dbfd3781dd4d4e609c42628dbb709b3eb1fa030009045dd98b9e6d77b6cec9ceb685595d43995e0f04c32260943add79831e661c6a351dedc8b9d220fbf9fb6e44fb6a629ce9a82025124fec9f3ee751f7da0cd7e799be88ddbdac20b48e890ff81d7fa28c2d017d7932f2569038740461accd4582f576e4fdbd150a3399f8266bc19eb943648ad1ad81420ed6c382436e474390c8995e829e4f9df43eed85a60b9ee254e31eb62900857fa134e76cc64880334adbff069a2e5e647d2ed36a96b23834b6f6ca6b8113baf4cf30347fbb7ffc30aea99872cc0dba03b07d3347b2d257edbe2733c26b7337a79962d8ce85469e3bcbe0e4a48a6ae69613f2d4b5155b390ef67aa714b82b6313ee277cb8986eca5db2e97cb1ae2243bba80274f614ece521baef443394b4c161cb9ae926e21892578b49cfd6efe1cb1572148c10d92218ed73ec116a18de80ac42d2726a4523a764fc6dc356c5fbbf9d2c947ae3bc9a3dc76099f3257c8d5952876151b0326d8cb1d5683ee4ad5ded9a34c00ac1b03f34627ec18a7c2e92c87b7896549cfab5eb55fa85a970994bd4b22b5f0d045e241256d06f485a47b4a55ed389bc1734541232cd41908b5cfa4b8fcfcafce500a0c7ae99767713a98e7927aa69f6ccd7daea62f19ceb82559f41899c9a9aee99113e7e64b5f8b9824be9fdbfa4dd4995673d882bb4daeb64413b334e114965d2ba3cea8051e692508701b9400cb12eae457f8b8549944091b729160939918d8fcae611a5ded665f770db637487a236da1a58ba7566668651a77171fc4fe506496d19059343dbe4f426625d3f2b705f54581372361770bf5a9098a9fafefaf546426b294239ac33e3186e4d58ad2fa995a6ad4dc074e7cca11aead109563b2076c7c6e9f57ec63df960804e2e7f9d8444de9550cca3df7834d864e9777291c2e1f6205de2e43dc995ab8bb1515a365efc2830fa3e7a1dd137f550d6035212bc1f51c3b4ceea430df49ffc9210084ef156ad7e0d219efd6c116693735b44521d389969a3a65617cd2fd6e14060601cee4cd054cf36fe048b57d1d9ee3cad2a73552449926b4a6b03fbe9c0ec68357e1fbe52ed77b67f5870c0aefb7ee8236747e0d67a26725fb515544cbbe8464da94cfd8c0b94bb4e51a263b1749bd0a7cf651931f806d1b928d1f9994f1ad4d50e6a5cd7a8e4e687f8564fdacc864013d095ba9d5709eced3c28eabda476d177a7836400a01e02beeb5a6636d4064fdda344967ad8682d14b87c71727cb66be27d1d39191f4223c545b62fb4860262ba8076a65dbc194cee1df846c584b7bbe9dce6e6895b2cbbb64b03b55548b845cc3de2f939ef918421af9a5e9157e837651245299c03992d0ddee06bd22a31522aca0f309b1feccebc0b1c0ed9d21c19bfd15cd313ff64394fd6a10904890c9f6d646b026f27253e8f584c3ffd20ad67e8b62ed7676706d40bc5c80e376980b75", 0x481, 0x40804, &(0x7f000069b000-0x5)={0x2, 0x3, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
recvfrom$inet6(r0, &(0x7f00008d9000-0x7c)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7c, 0x0, &(0x7f00008e9000-0x1c)={0xa, 0x0, 0x5, @loopback={0x0, 0x1}, 0x1}, 0x1c)
setsockopt$inet_sctp6_SCTP_RECVNXTINFO(r0, 0x84, 0x21, &(0x7f0000756000)=0x10, 0x4)
recvfrom(r0, &(0x7f0000235000)="", 0x0, 0x0, 0x0, 0x0)
sendto$inet(r0, &(0x7f000020a000)="", 0x0, 0x0, &(0x7f00002b4000)={0x2, 0x0, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
sendmsg$inet_sctp(r0, &(0x7f0000f3c000+0x6ed)={&(0x7f00006e5000-0x10)=@in={0x2, 0x0, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000f9e000)=[{&(0x7f0000309000)="b14cfab6432b87d653e0db592294df04e846ee1fe229ab4965d29014037f964d065b73c0cce2ac118ea3dab62a84c903e158b066c5f0312d6fd81a49cb5c01f155338c987deb9bf52cac2dd0914f0f4b5e30d3001518687f348632f59d6022b6bfa042ba0cf5c5ef4dec0f9c408bbd50ddb8e97bcc08ead93fea99abe5b6cc5b4044d60af5a2eb35e5e960c7da145f0e1d4cf9a1480dd5d25c7ec5ee7e1c41757f5187724332e83d40cb6062d5e3cfb5c75b1a4e1366da3a54ab86e6c393171a8906237a32f194e99ec581c33f17dcfeb210bc499c6959a63ba3776e96", 0xdd}], 0x1, 0x0, 0x0, 0x48015}, 0x800)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$vcs(0xffffffffffffff9c, &(0x7f000033b000-0x9)="2f6465762f76637300", 0x0, 0x0)
r1 = socket(0x1e, 0xfffffffffffffffd, 0x0)
recvfrom$inet(r1, &(0x7f0000895000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x8b, 0x122, &(0x7f0000eba000-0x10)={0x2, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
ioctl$KVM_SET_DEBUGREGS(0xffffffffffffffff, 0x4080aea2, &(0x7f000034b000-0x80)={[0x4, 0x4000, 0x3000, 0xf51d2086b01615df], 0xfffffffffffff800, 0x2, 0x8, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$sock_timeval(r1, 0x1, 0x14, &(0x7f0000455000-0x10)={0x0, 0x2712}, 0x10)
r2 = gettid()
socketpair$unix(0x1, 0x1, 0x0, &(0x7f0000e19000-0x8)={<r3=>0xffffffffffffffff, <r4=>0xffffffffffffffff})
ioctl$int_in(r3, 0x5452, &(0x7f0000540000-0x8)=0x5)
fcntl$setown(r3, 0x8, r2)
readv(r3, &(0x7f0000cf8000)=[{&(0x7f00005ea000-0x1)="00", 0x1}], 0x1)
listen(r1, 0x5)
accept(r1, &(0x7f0000f16000)=@ipx={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, &(0x7f0000982000)=0x10)
fcntl$setsig(r3, 0xa, 0x12)
readv(r4, &(0x7f0000fa4000)=[{&(0x7f0000fa5000-0x8e)="00", 0x1}], 0x1)
fcntl$setstatus(r4, 0x4, 0x0)
dup2(r1, r4)
tkill(r2, 0x12)
2017/12/15 11:53:26 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$selinux_enforce(0xffffffffffffff9c, &(0x7f0000c9d000-0x11)="2f73656c696e75782f656e666f72636500", 0x400200, 0x0)
creat(&(0x7f0000b55000-0x8)="2e2f66696c653000", 0x42)
modify_ldt$write(0x1, &(0x7f0000b9a000)={0x2, 0x20001000, 0x400, 0x5, 0x5, 0x3, 0x1, 0x2, 0xa91b, 0x1}, 0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = dup(0xffffffffffffffff)
ioctl$TIOCSWINSZ(r0, 0x5414, &(0x7f00001d4000)={0x8, 0x3, 0x5, 0x1006})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10000000000000, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
ioctl$sock_inet_SIOCSIFPFLAGS(r0, 0x8934, &(0x7f000002e000-0x20)={@common="64756d6d793000000000000000000000", @ifru_flags=0xba01})
r1 = syz_open_dev$vcsa(&(0x7f000077d000-0xb)="2f6465762f766373612300", 0x2, 0x3fffff)
r2 = socket$netlink(0x10, 0x3, 0xfffffffffffffffe)
sendmsg$netlink(r2, &(0x7f0000011000-0x38)={&(0x7f00008e0000)={0x10, 0x0, 0x0, 0x0}, 0xc, &(0x7f0000014000)=[{&(0x7f0000a42000)=[{0xe6, 0x0, 0x500, 0x2, 0x803, "9399ee68c33afb35294ad2daf5319c3fcd06352e6a49973111aa9c9a653f83216565d61bf7929ed3a46604c5895059f8c066ff3b88ed8412c34bc9db0bc813043bebf0bffc093bbbd6c799c8287e37b9c118f5a605ee9dec69325a6b912bf91f7ac3af45c0efbce1e2dc7b926cec9c3cf89f73c63d5a715f73c2758f3dbb1c371c3cf4f923c159b4460dce0e79b55b81ae55c6046dba7089b07f88b00b3b7cb4cf929eb879e966e1fff04b8790fc869dcb4b8a58af90600f5015e19d7c61406346e630c6e4b30ce87853b78d84deff2c0d33839492a7"}, {0x1a, 0x9, 0x400, 0xfffffffffffffffb, 0x3, "ce7464228f580d4c32ae"}, {0xb8, 0x9c, 0x2, 0x8, 0xfffffffffffff801, "e357dc44ea16b1bbb1c3fe95900d5b31390fad71e2c892c07ed7ed16d2d47c0bd4fd93d1516f11b9113e46a704f3c150313a9c186736bf47d0e5ade1656fee7bed03ddd010a1fedfe756d3095a26732ea3fceacf108e875b38e545db87ed225d17d74952ba2c7fd6b7a7fd230d06b89bf270cce1ccf69933060e0f3e33fcb3372144dd5a77b11d4fff323f5d2a36030f42185f42c6711ac3a0d369512402a1c953c56263fcf7a8c2"}, {0xcc, 0x1, 0x200, 0x2, 0x0, "d6efc86e68eeeaa66fb76f1f838c2c55fd920540813a40dc222f5f3ca675ede55b265ac80e62fc142c974c921f779ebf8f6acaf946e420d05a16eef918f63fc628b0e11114b6b3184966c69ad86422a8c6a77c7c8bfc6a177f3ca218ec45c9ebe88195b8a8c9e1a4a71b2e3b03a04635e4ce4609db4634bb27820276a7a3945b5fde172017bdb6f34d3cca129f8f47295c62e00d6479350edf782d789178d5be9744555c9d7976d6df00acce54616d14b0251e1e3407b372ae913d4e"}, {0xc7, 0x800, 0x2, 0x0, 0x800, "0e7683eb1fe8238ab6593bf0f23b6666f1d9d7dbe188c0fe2bdbdb95796f40c2ef0afcae31f48ff517228565978c5d6788c29c4159876e7c2906e50347fa306127e12b637ae42ad3a63cbf812678beecb9868e084e56d88be0ebfb3bf2531596e3798deaac1f68130162b216573978d1abf83630a760579c8bc563809776b811f06129975095aba72ae0be94e88d7ab364f4dfb3f79b5d3bce251fc95d7d8f1ce98458202acce6d9729a710be029b25251d84fab564b7f"}, {0x2e, 0x2, 0x10, 0xfff, 0xe310, "eeb389f1bc5679f8f529e82955776a4ea49f8795ad27e8b8a8926c4c2c4e"}, {0x46, 0x4, 0x4, 0x4, 0x0, "c7e977fc0a979f109d8cf16cbf3f47e8b0071b33fc7a61bb3089216a9daf0efa4c62da9595d6c1aaf117475963c12170015c632006e2"}], 0x3bf}], 0x1, &(0x7f000001b000-0x98)=[], 0x0, 0x0}, 0x0)
setsockopt$inet_sctp_SCTP_AUTH_CHUNK(r0, 0x84, 0x15, &(0x7f0000de6000)={0x869}, 0x1)
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r0, 0x84, 0x18, &(0x7f0000417000)={<r3=>0x0, 0x2}, &(0x7f000047e000-0x4)=0x6)
setsockopt$inet_sctp6_SCTP_RESET_ASSOC(r0, 0x84, 0x78, &(0x7f0000e73000)=r3, 0x4)
r4 = accept$netrom(0xffffffffffffffff, &(0x7f0000d72000)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f0000a0e000-0x4)=0x10)
fcntl$setstatus(r4, 0x4, 0x6000)
accept$inet6(r1, 0x0, &(0x7f000092f000-0x4)=0x0)
r5 = socket$netlink(0x10, 0x3, 0xc)
r6 = request_key(&(0x7f00002df000)="69645f7265736f6c76657200", &(0x7f00005c3000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, &(0x7f0000107000-0xb)="2f6465762f766373612300", 0xffffffffffffffff)
r7 = add_key(&(0x7f0000913000-0xb)="256b01001d0007ffffe47a", &(0x7f0000b42000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, 0x0, 0x0, r6)
r8 = add_key$keyring(&(0x7f0000ea8000-0x8)="6b657972696e6700", &(0x7f00003d9000)={0x73, 0x79, 0x7a, 0x2, 0x0}, 0x0, 0x0, r6)
keyctl$link(0x8, r7, r8)
r9 = socket$inet6_tcp(0xa, 0x1, 0x0)
setsockopt$inet6_buf(r9, 0x29, 0x400000000000003c, &(0x7f000078f000)="bc", 0x1)
writev(r5, &(0x7f0000c9d000)=[{&(0x7f0000804000)="290000001800ffffffff6800000a00080308ef0c060000000000000000000000000310ec010019ff00", 0x29}], 0x1)
r10 = socket$inet(0x2, 0x8000000000000003, 0x5)
getsockopt(r10, 0xff, 0x2, &(0x7f0000a58000-0xdd)="", &(0x7f0000c1c000-0x4)=0x0)
getsockopt$inet_sctp6_SCTP_INITMSG(r1, 0x84, 0x2, &(0x7f0000a44000-0x8)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000689000-0x4)=0x8)
2017/12/15 11:53:26 executing program 4:
perf_event_open(&(0x7f00008a8000-0x78)={0x4000000002, 0x78, 0xdc, 0x2, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, 0x2, 0x0, 0x0, 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x10000000000, 0x4, 0x0, 0x40000000000000, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x4)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xf000)=nil, 0xf000, 0x0, 0x1b071, 0xffffffffffffffff, 0x0)
mremap(&(0x7f0000000000/0x3000)=nil, 0x3000, 0x2000, 0x6, &(0x7f0000007000/0x2000)=nil)
msync(&(0x7f0000002000/0xd000)=nil, 0xd000, 0x4)
mmap(&(0x7f000000f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000010000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000011000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bind$netlink(0xffffffffffffffff, &(0x7f0000011000)={0x7, 0x0, 0x0, 0x1246f80f}, 0xc)
ioctl$PIO_FONTRESET(0xffffffffffffffff, 0x4b6d, 0x0)
remap_file_pages(&(0x7f0000003000/0x9000)=nil, 0x9000, 0x0, 0xfffffffffffffffe, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_SIOCGPGRP(0xffffffffffffffff, 0x8904, &(0x7f0000e19000-0x4)=0x0)
getsockopt$SO_PEERCRED(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000048000)={<r0=>0x0, 0x0, 0x0}, 0xc)
getpgid(r0)
perf_event_open(&(0x7f000071f000-0x78)={0x0, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffff8000, 0x0, 0x0, 0x0, 0x278d, 0x0, 0x0, 0x0, 0x100, 0x0, 0x80000000000000, 0x0, 0x0, 0x0, 0x0, 0x0}, 0xffffffffffffffff, 0x1ff, 0xffffffffffffff9c, 0x8)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f00008a8000-0x78)={0x4000000002, 0x78, 0xdc, 0x0, 0x10001, 0x0, 0x0, 0x6830, 0x0, 0x0, 0xfc, 0x0, 0x800, 0x40, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r1 = socket$inet6_sctp(0xa, 0x1, 0x84)
setsockopt$inet_IP_XFRM_POLICY(0xffffffffffffffff, 0x0, 0x11, &(0x7f0000001000)={{{@in=@rand_addr=0x0, @in=@broadcast=0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0}, {0x0, 0x2000000000000, 0x0, 0x469e}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@loopback={0x0, 0x1}, 0x0, 0x0}, 0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 0xe8)
getsockopt$inet6_buf(r1, 0x29, 0x2e, &(0x7f0000001000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000a12000)=0x90)
r2 = getpgid(r0)
perf_event_open(&(0x7f00004e7000)={0x2, 0x78, 0xdf, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0, 0x0}, r2, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfbd000)=nil, 0xfbd000, 0x3, 0x31, 0xffffffffffffffff, 0x0)
waitid(0x1, r2, &(0x7f00000fd000-0xc)={0x0, 0x0, 0x0, 0x0}, 0x1, &(0x7f0000134000)={{0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
clock_gettime(0x0, &(0x7f00009e5000)={<r3=>0x0, <r4=>0x0})
futex(&(0x7f0000670000)=0x0, 0x5, 0x7, &(0x7f0000318000+0x832)={r3, r4+30000000}, &(0x7f000046a000)=0x0, 0x8001)
mmap(&(0x7f0000000000/0xfee000)=nil, 0xfee000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
unshare(0x20000400)
timerfd_create(0x7, 0x800)
2017/12/15 11:53:26 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x7, 0x32, 0xffffffffffffffff, 0x10004000000)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1f, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
creat(&(0x7f0000e3d000)="2e2f66696c653000", 0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = getpgrp(0x0)
setpriority(0x0, r0, 0x1000000000085)
ioctl$TIOCPKT(0xffffffffffffffff, 0x5420, &(0x7f0000b23000)=0x5)
r1 = openat$kvm(0xffffffffffffff9c, &(0x7f0000fb1000)="2f6465762f6b766d00", 0x0, 0x0)
r2 = syz_open_dev$usbmon(&(0x7f0000d24000-0xd)="2f6465762f7573626d6f6e2300", 0x6, 0xc000)
ioctl$KVM_GET_XCRS(r2, 0x8188aea6, &(0x7f00006aa000)={0x2, 0x4, [{0x7fffffff, 0x0, 0x5}, {0x3, 0x0, 0x7}]})
getsockopt$inet_sctp_SCTP_MAX_BURST(r2, 0x84, 0x14, &(0x7f0000796000)=@assoc_value={<r3=>0x0, 0x0}, &(0x7f000095e000)=0x8)
setsockopt$inet_sctp_SCTP_DEFAULT_PRINFO(r2, 0x84, 0x72, &(0x7f00000a3000)={r3, 0x0, 0x20}, 0xc)
ioctl$TIOCGWINSZ(r2, 0x5413, &(0x7f0000418000)={0x0, 0x0, 0x0, 0x0})
ioctl$RNDCLEARPOOL(r2, 0x5206, &(0x7f0000df7000)=0xfffffffffffffff8)
shutdown(r1, 0xffffffffffffffff)
r4 = ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
getrlimit(0x9, &(0x7f0000b93000)={0x0, 0x0})
r5 = ioctl$KVM_CREATE_VCPU(r4, 0xae41, 0x3)
syz_kvm_setup_cpu$x86(r4, r5, &(0x7f0000669000/0x18000)=nil, &(0x7f0000574000)=[@text64={0x40, &(0x7f00005f6000-0x62)="8f49d09a1366ba6100b800800000c461a5ed81024d000048b800780000000000000f23d80f21f835000000003923f8c2b9d4b8010000000f01d9c7442400d7000000c7442402ca000000ff1c2466ba6100ec4b0fc75a004c0f01c9b9c60200000f32", 0x62}], 0x1, 0x55, &(0x7f0000dfd000)=[], 0x0)
clone(0x4002000, &(0x7f00000a4000-0xaa)="aef2e3faff131dc7935428807c1b2cd063a899103b1a7f4a319e2b97fb48b0514b4280537cbfc9e8f6e32d1c6a2c3be4ebe1814d640de66cc6986abc535e856463e5c72548a5daf612d73889d0049026571c5f61ed30a1731ce815f7ec78622d8514dc59cadf26fa248afc371623655af21a8631e0d13b2cfeb028f6ebd2adecbf518ad9dec5f0348c337ac142f99721b3f64516fd0f6474e00aa1b9a3dc200123fe71eec06037d1f040", &(0x7f000079f000)=0x0, &(0x7f00008be000)=0x0, &(0x7f0000828000)="cff7fc299295e24f08b24c642e817fc2174f76568bb0b1ed84b3afb41947b14d124c64f939be705f671687afe8a5f6b774caaffc90530cc612462afd24311537aed043dde4fa51dfa03cddbced706c6d5d1c599ba1063073a4d3f2593412f7121b46f10dd07c8034ffdb3a7981e7e8567e562a6120652114404b4ae26f8495a9606718c4ded642c6bbb85b9a5038d1ad087f775d437acbb38e54f88713d3f0db67ec5d247c30ced2cf619598be04f76bf2a9c0c10f564459195f267e421d47adb2eb2cdc5fd27325a4ed2f2d")
getrusage(0x0, &(0x7f00001da000)={{<r6=>0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
futimesat(r2, &(0x7f0000db0000-0x8)="2e2f66696c653000", &(0x7f0000e11000)={{r6, 0x7530}, {0x0, 0x0}})
ioctl$KVM_SET_GUEST_DEBUG(r5, 0x4048ae9b, &(0x7f0000e53000-0x48)={0x1, 0x0, [0x1f, 0x10000, 0x4, 0x1, 0x10001, 0x80000001, 0x6, 0x8]})
ioctl$KVM_SET_CPUID2(r5, 0x4008ae90, &(0x7f00008e5000)={0x0, 0x0, []})
ioctl$KVM_RUN(r5, 0xae80, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfe9000)=nil, 0xfe9000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
msgget$private(0x0, 0x10)
r7 = gettid()
getpriority(0x7239692a7ef9e3d6, r7)
mmap(&(0x7f0000000000/0xcd4000)=nil, 0xcd4000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0x1a000)=nil, 0x1a000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfc9000)=nil, 0xfc9000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = inotify_init1(0x80800)
r1 = openat(0xffffffffffffff9c, &(0x7f0000fc4000-0x8)="2e2f66696c653000", 0x80, 0x102)
ioctl$EVIOCGREP(r1, 0x80084503, &(0x7f0000a29000-0xb3)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
getsockopt$sock_cred(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000c87000)={<r2=>0x0, 0x0, 0x0}, &(0x7f0000fc4000)=0xc)
fcntl$setown(r0, 0x8, r2)
fcntl$getownex(r0, 0x10, &(0x7f0000fb4000)={0x0, <r3=>0x0})
getpgid(r3)
ioctl$KVM_GET_VCPU_MMAP_SIZE(r1, 0xae04)
ioctl$sock_FIOGETOWN(r1, 0x8903, &(0x7f0000fc4000)=<r4=>0x0)
ptrace$setopts(0x4206, r3, 0x0, 0x0)
ptrace(0x4208, r4)
ioctl$PIO_UNIMAPCLR(r1, 0x4b68, &(0x7f0000fc4000)={0x0, 0x9, 0x3})
ioctl$EVIOCGREP(r1, 0x80084503, &(0x7f0000f13000-0x75)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
ptrace$setsig(0x4203, r3, 0x0, &(0x7f0000fc2000+0x2de)={0xb, 0x0, 0x4, 0x0})
ioctl$SNDRV_SEQ_IOCTL_CLIENT_ID(r1, 0x80045301, &(0x7f00000ce000)=0x0)
ioctl$DRM_IOCTL_PRIME_FD_TO_HANDLE(r1, 0xc00c642e, &(0x7f0000fc5000-0xc)={<r5=>0x0, 0x80000, r1})
mmap(&(0x7f0000fc9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fc9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$ax25(r1, &(0x7f0000fc9000)={0x3, {"78000000013760"}, 0x2}, 0x10)
ioctl$DRM_IOCTL_GEM_CLOSE(r1, 0x40086409, &(0x7f0000fc4000)={r5, 0x0})
recvfrom$inet6(r1, &(0x7f0000ce1000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x44, 0x40, &(0x7f0000fc7000-0x1c)={0xa, 0x2, 0x4, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x3}, 0x1c)
mmap(&(0x7f0000fc9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ptrace$getsig(0x4202, r3, 0x80000001, &(0x7f0000fca000-0x10)={0x0, 0x0, 0x0, 0x0})
keyctl$revoke(0x3, 0x0)
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f0000fc7000)={0x0, 0x0, 0x0}, &(0x7f0000fc8000)=0xc)
bind$inet6(0xffffffffffffffff, &(0x7f0000017000-0x1c)={0xa, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x8001}, 0x1c)
mmap(&(0x7f000001a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_emit_ethernet(0x3f, &(0x7f000001b000-0x3f)={@local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [], {{0x86dd, @ipv6={0x0, 0x6, "000000", 0x9, 0x21, 0x0, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, {[], @udp={0x3, 0x0, 0x9, 0x0, "88"}}}}}}, 0x0)
mmap(&(0x7f0000fca000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
creat(&(0x7f0000fca000)="2e2f66696c653000", 0x10)
[ 50.200767] binder_alloc: 7168: binder_alloc_buf, no vma
[ 50.200787] binder: 7168:7208 transaction failed 29189/-3, size 536870912-0 line 2947
[ 50.330436] binder: send failed reply for transaction 25 to 7168:7182
[ 50.337062] binder: undelivered TRANSACTION_ERROR: 29201
[ 50.343072] binder: undelivered TRANSACTION_ERROR: 29189
[ 50.357407] binder: undelivered TRANSACTION_ERROR: 29201
2017/12/15 11:53:26 executing program 2:
r0 = creat(&(0x7f0000ed7000)="2e2f66696c653000", 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_CREATE_DEVICE(0xffffffffffffffff, 0xc00caee0, &(0x7f0000001000-0xc)={0x2, <r1=>0xffffffffffffff9c, 0x0})
r2 = openat(r1, &(0x7f000018a000-0x8)="2e2f66696c653000", 0x2000000000020000, 0x1)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f00008a8000-0x78)={0x4000000002, 0x78, 0x1e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000000a000)={0x5, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x668, 0x0, 0x0, 0x0, 0x0, 0x3, 0x3, 0x20001000, 0x8, 0x84, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
ioctl$KVM_PPC_GET_PVINFO(r2, 0x4080aea1, &(0x7f00008c5000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000000000/0x8b000)=nil, 0x8b000, 0x1000004, 0x10000032, 0xffffffffffffffff, 0x0)
ioctl$KVM_DEASSIGN_PCI_DEVICE(r0, 0x4040ae72, &(0x7f00006c1000)={0x0, 0x7, 0x40, 0x2, 0x1ff})
ioctl$VT_DISALLOCATE(r2, 0x5608)
futex(&(0x7f0000001000)=0x0, 0x87, 0x1, &(0x7f0000191000)={0x0, 0x989680}, &(0x7f0000000000)=0x0, 0xfffffffffffffffe)
setsockopt$inet_sctp_SCTP_SOCKOPT_BINDX_REM(r2, 0x84, 0x65, &(0x7f0000728000-0xb0)=[@in={0x2, 0x0, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x2}, @in={0x2, 0x3, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x3, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x0, @rand_addr=0x40, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x0, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0x403, @loopback={0x0, 0x1}, 0x3}], 0x98)
socket$llc(0x1a, 0x1, 0x0)
fcntl$getown(0xffffffffffffffff, 0x9)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xa81000)=nil, 0xa81000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000a81000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f00002da000)={0x0, 0x78, 0x0, 0x6, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfffffffffffffffd, 0x0, 0xffffffffffffffff, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000a82000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = syz_open_dev$sg(&(0x7f0000a83000-0x9)="2f6465762f73672300", 0x8001, 0x80000)
sendmsg$kcm(0xffffffffffffffff, &(0x7f0000a80000-0x38)={&(0x7f0000000000)=@llc={0x1a, 0x0, 0x0, 0x0, 0x0, 0x0, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, 0x10, &(0x7f0000000000)=[{&(0x7f0000000000)="25850e28b8e79998", 0x8}], 0x1, &(0x7f0000a7f000)=[], 0x0, 0x0}, 0x0)
r4 = syz_open_dev$sg(&(0x7f0000bbe000-0x9)="2f6465762f73672300", 0x0, 0x0)
ioctl(r4, 0x227b, &(0x7f0000002000-0x1)="06")
fcntl$setstatus(r4, 0x4, 0x2800)
read(r4, &(0x7f0000000000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x58)
ioctl$PIO_UNISCRNMAP(r3, 0x4b6a, &(0x7f0000a4c000-0xdd)="d4b36fd19662305fc8c9e0af3c3bdf3c7be29663d343f66b3ea3535e763654c163962751b5972c3232175432387f6cb1d04ec8ef56c54ddb58358fd316d22d93ad1ba937551dd41e0b3dd69d1fbf84d9c1fbcb031aad555d85c5ebee3fa7565c89e02bf6342b0bdd4fd415949629a82a959518b8a6cd1f260d6baacbc982294ac96ee9c5b309a8cacf80ca61738dc6704fb4c17f4af826e45f8bc9aa0a438f1a4c8dfb844073753d4abfd0760b9d037462fe0cde15283b4acb2dbc4d16cb3bb71804d91daf688e14459e5c0d1f012b4d05d9651f2f4fc8a9da30e12084")
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
futex(&(0x7f0000004000-0x4)=0x1, 0xb, 0x10000, &(0x7f0000003000)={0x0, 0x0}, &(0x7f0000003000)=0x0, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000940000)={0x1, 0x78, 0xffffffffffffffff, 0x15, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0xfffffffffffffffe, 0x3, 0x0, 0x0, 0x35, 0x2, 0x1, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet_udp(0x2, 0x2, 0x0)
getsockopt$SO_PEERCRED(r0, 0x1, 0x11, &(0x7f0000a61000)={0x0, 0x0, 0x0}, 0xc)
fcntl$getown(r0, 0x9)
r1 = getpgid(0x0)
r2 = getpgrp(r1)
fcntl$lock(r0, 0x6, &(0x7f0000627000-0x20)={0x2, 0x2, 0x49d, 0x3ff, r2})
bind$inet(r0, &(0x7f0000d6a000-0x10)={0x2, 0x0, @rand_addr=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
r3 = socket$inet(0x2, 0x1, 0x0)
r4 = semget$private(0x0, 0x2, 0x40)
semctl$GETVAL(r4, 0x2, 0xc, &(0x7f0000c2a000-0x47)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
r5 = syz_open_dev$tun(&(0x7f0000520000-0xd)="2f6465762f6e65742f74756e00", 0x0, 0xa)
stat(&(0x7f0000c43000-0x8)="2e2f66696c653000", &(0x7f00001d7000)={0x0, 0x0, 0x0, 0x0, <r6=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
r7 = getgid()
syz_fuseblk_mount(&(0x7f00006e8000)="2e2f66696c653000", &(0x7f00000f6000)="2e2f66696c653000", 0x8000, r6, r7, 0x100000000, 0x4, 0x1040)
r8 = fcntl$dupfd(r5, 0x0, r5)
ioctl$TUNSETIFF(r5, 0x400454ca, &(0x7f0000a5b000-0x28)={@common="67726530000000000000000000000000", @ifru_names=@generic="4f54000cc0a1ed4f3a0a1fdc222073b5"})
setsockopt$SO_ATTACH_FILTER(r0, 0x1, 0x1a, &(0x7f000055c000)={0x0, &(0x7f0000516000-0x8)=[]}, 0x10)
ioctl$sock_inet_SIOCSIFFLAGS(r3, 0x8914, &(0x7f0000630000-0x20)={@common="67726530000000000000000000000000", @ifru_flags=0x301})
write$tun(r8, &(0x7f00003f1000)=@hdr={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @ipv4={{0x5, 0x4, 0x0, 0x0, 0x415, 0x0, 0x0, 0x0, 0x11, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, @multicast1=0xe0000001, {[]}}, @dccp={{0x0, 0x0, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, "b31d90", 0x0, "b99878"}, "500e4156bafc36f82a4b504b036ac54c641b052b4bd37bbd64c835a43ff64c517d4be4bd09fd51dba95d4fe44d8faa82b23a5cc4658c9fedeef7256b40604ee4f878d9d3c3999e0312f06d8aedcd5039894a18126498dcc964dd5a402c417a1cc798189d285118d98e9f7ae8fc0ec9b74efbd90cd7d544765d2df18be50c1323476820af79bad0e65d1c48e0ca8685ab6e775d350961652c7a7c9f2918c9444a307a6b8fbc093f56829fa579723c6ecef716d5085439b3a070b638ce690c66144c8e0314250fa36a5a9113de159c9195db60cb56dc158ea825a7c56dcf9ab155f076e53afec5a4155269dd56fb99aaf6044ec72e8745f18929fd1bce7c52bfa1e099f237de1f32f43bd6ee103b9341a3eb484170637324bacee722c7625288463e69dc1cfb1162ece3f1b48eb95125e52cbf498aa2ae4f949a4f21bff523f3e29cb058647b17895e3901ba4d7750b0544537e77dc19f18b4d2ce1800e06596f84c4de7aaf4338810d040ed19ce89619e475824c0ecbce568fad0c59374a709ae626a706904f394a7874cbedb022d8397bbe406318dd5f5e81eb4fd15d7f49cbd4f9a871b56db62211dd7bb416e976aa57d7d5fd34f25e9f881dbab0466e9ec68c15b642b0057050564c6950b2ad79fcd5c81748252cf80f1403313664b1e54a333c90937f55c002e89304be9236ba919e36b677a2f4f7a495cc51bac62462d2c0f71328f7975f9ebb64f14094c1098343cc26e30e6a1e9b46b5df39a89ff2a44950e202bbddf866c8dbd834dee240dd2b10b3b0e0a47c8f1a810a8be5a71f7e68621fe0928ae2c23b2f3d01b01a94184217f467adee09c9e6a22ba53c634620162868da27af8974300231a1c6ba6b1fb145278327d6ff0edd905e52d0f1adbdfe92c152ebe3e988ec64ab512231e2abce8bf2ed6f6a4e1829fadb8ff3c51117b1094b8c9cb2cd807d88b3eeae3272d250868acebb332a5c6fe7717e782e9b3323d961b872568fe7798fbc4a81230a13b639a673c0044ce623355527a183efbe6367c30ee3d22b5de0e8913deedd0cac21a90fe13995a887baa295a64b367b6da934ffb23836fa6fce9023e8ee9d0152542e57a86c92d1569a1ef1e7d15b325e5c340d6933f890c43467f3b09371a9505a46064fc404c87ac13522b52e89f7afd49974539d3af5d1a5b8567a3570568fc344d4f854e1a385620cec24c6ec14a221d14b7259a11d5d7745933f6e608d74e49a4f7f1159eb2662a22ea7c6ef3ecf064f06e7443df5bd4de8e949e7e3500079e33b6b7dd0dd333dde809ab361601c66c4023aaee80021a8459fa2f4feca656b2f7117969e3e0abd5f18c1f507a207972ef12a11e3c437507ec91e571e487fa8a625608430bd0f9485d8e384f1cde04a6d4046c2f95ec56aff13155a79bd5b6cb"}}}, 0x41f)
recvmmsg(r0, &(0x7f0000842000)=[{{&(0x7f000008e000-0x6)=@hci={0x0, 0x0, 0x0}, 0x6, &(0x7f000072e000-0x60)=[{&(0x7f0000a94000-0x12)="000000000000000000000000000000000000", 0x12}, {&(0x7f0000223000)="0000000000000000000000000000000000000000000000000000000000000000000000", 0x23}, {&(0x7f0000d38000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f0000808000-0xb)="0000000000000000000000", 0xb}, {&(0x7f00001a8000-0x24)="000000000000000000000000000000000000000000000000000000000000000000000000", 0x24}, {&(0x7f0000603000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd0}], 0x6, &(0x7f0000cea000-0xa1)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xa1, 0x3}, 0x263}, {{&(0x7f000090a000+0xc24)=@generic={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x80, &(0x7f0000dc8000-0x10)=[{&(0x7f0000a4c000+0x9cb)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x46}], 0x1, &(0x7f000095d000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000, 0xffff}, 0x3}, {{&(0x7f0000a65000-0x10)=@in={0x0, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000d8e000)=[{&(0x7f00003ee000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x5d}], 0x1, &(0x7f00008fd000-0x7c)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7c, 0x0}, 0x20}, {{&(0x7f0000ae4000-0x9)=@rc={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0}, 0x9, &(0x7f00008f2000-0x90)=[{&(0x7f00005d0000-0xcf)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xcf}, {&(0x7f00008bc000-0x1d)="0000000000000000000000000000000000000000000000000000000000", 0x1d}, {&(0x7f00009e2000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x33}, {&(0x7f00004c1000-0x7b)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7b}, {&(0x7f0000b3e000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xeb}, {&(0x7f0000843000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xcd}, {&(0x7f0000e8b000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd2}, {&(0x7f0000db5000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe7}, {&(0x7f000025c000-0x3b)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x3b}], 0x9, &(0x7f000019f000)="00000000", 0x4, 0x7fff}, 0x0}, {{&(0x7f0000410000-0x6)=@hci={0x0, 0x0, 0x0}, 0x6, &(0x7f0000e37000)=[{&(0x7f000085f000-0x57)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x57}, {&(0x7f00004f1000)="00000000000000000000000000000000000000000000000000", 0x19}, {&(0x7f0000e27000)="0000000000000000000000000000000000000000000000000000000000000000000000000000", 0x26}, {&(0x7f0000d60000-0xee)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xee}, {&(0x7f0000ad7000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x50}, {&(0x7f00003b1000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xc3}, {&(0x7f0000c8c000-0xc1)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xc1}], 0x7, &(0x7f0000f2d000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x88, 0xb0f}, 0x8}, {{&(0x7f0000617000-0x9)=@rc={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0}, 0x9, &(0x7f0000344000-0x60)=[{&(0x7f0000909000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x8e}, {&(0x7f0000b1c000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f000013f000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb4}, {&(0x7f000056d000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6a}, {&(0x7f000069b000-0xe8)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe8}, {&(0x7f00004b5000-0x99)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x99}], 0x6, &(0x7f000094f000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x36, 0x2c29}, 0x1}, {{&(0x7f000071d000)=@rc={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0}, 0x9, &(0x7f0000544000-0x40)=[{&(0x7f000016b000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xce}, {&(0x7f0000e55000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x39}, {&(0x7f0000e5c000-0x60)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x60}, {&(0x7f0000140000-0xb1)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb1}], 0x4, &(0x7f0000e7d000)="0000000000000000000000000000000000000000000000000000000000000000000000", 0x23, 0x3f}, 0x80000000}, {{&(0x7f0000cdd000-0x8)=@sco={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 0x8, &(0x7f0000a41000-0x80)=[{&(0x7f00006d6000-0xeb)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xeb}, {&(0x7f0000669000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xc9}, {&(0x7f0000cf6000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0}, {&(0x7f00009f9000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9d}, {&(0x7f00000aa000-0xb)="0000000000000000000000", 0xb}, {&(0x7f000010a000-0xf6)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xf6}, {&(0x7f0000ff2000-0xb9)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb9}, {&(0x7f00005be000-0xf1)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xf1}], 0x8, &(0x7f0000ec8000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x81, 0x200}, 0x7}], 0x8, 0x40000040, &(0x7f0000131000-0x10)={0x0, 0x1c9c380})
write(r5, &(0x7f0000944000-0x1f)="07219a8d9d2c89167c103cc3166199681d0b0ff551e05eba8e0e434c947932", 0x1f)
poll(&(0x7f0000adc000-0x10)=[{r3, 0x2, 0x0}, {r3, 0x1124, 0x0}], 0x2, 0x0)
ioctl$KVM_GET_XCRS(r8, 0x8188aea6, &(0x7f000068f000)={0x0, 0x3, []})
r9 = socket$inet_tcp(0x2, 0x1, 0x0)
ioctl$sock_netrom_SIOCADDRT(r8, 0x890b, &(0x7f0000cf1000-0x4)=0x0)
readahead(r0, 0x4, 0x81)
setsockopt$inet_buf(r9, 0x0, 0x31, &(0x7f00009b1000)="", 0x0)
r10 = socket$inet_tcp(0x2, 0x1, 0x0)
accept(r0, &(0x7f0000271000-0x14)=@ll={0x0, 0x0, <r11=>0x0, 0x0, 0x0, 0x0, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, &(0x7f0000541000-0x4)=0x14)
setsockopt$inet_mreqn(r10, 0x0, 0x23, &(0x7f0000b12000-0xc)={@empty=0x0, @loopback=0x7f000001, r11}, 0xc)
pipe2(&(0x7f0000f63000)={0x0, 0x0}, 0x800)
getrandom(&(0x7f0000432000-0xf6)="00", 0x1, 0x3)
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
dup3(0xffffffffffffffff, 0xffffffffffffffff, 0x80000)
r0 = openat$qat_adf_ctl(0xffffffffffffff9c, &(0x7f0000412000-0x11)="2f6465762f7161745f6164665f63746c00", 0x10800, 0x0)
setsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(r0, 0x84, 0x13, &(0x7f0000001000-0x4)=0x1f, 0x4)
r1 = socket$inet6(0xa, 0x5, 0x80000006)
ioctl$sock_SIOCGIFINDEX(r1, 0x8933, &(0x7f0000466000-0x28)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000000000/0xf08000)=nil, 0xf08000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfb7000)=nil, 0xfb7000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$sequencer2(0xffffffffffffff9c, &(0x7f0000a88000-0x10)="2f6465762f73657175656e6365723200", 0x104, 0x0)
getsockopt$inet_sctp6_SCTP_SOCKOPT_PEELOFF(r1, 0x84, 0x66, &(0x7f0000035000-0x8)={<r3=>0x0, 0x5}, &(0x7f00007c8000-0x4)=0x8)
getsockopt$inet_sctp_SCTP_ASSOCINFO(r2, 0x84, 0x1, &(0x7f0000076000-0x14)={r3, 0x7f, 0x9, 0x9, 0xfc, 0x90e1}, &(0x7f0000935000)=0x14)
r4 = openat$autofs(0xffffffffffffff9c, &(0x7f00003ab000)="2f6465762f6175746f667300", 0x0, 0x0)
mmap(&(0x7f0000fb8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r5 = fcntl$getown(r4, 0x9)
r6 = perf_event_open(&(0x7f0000fb8000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0xfffffffffffffffe, 0x0, 0x0, 0x0}, r5, 0x0, 0xffffffffffffffff, 0x0)
r7 = open(&(0x7f0000716000-0x8)="2e2f66696c653000", 0x101000, 0x4)
r8 = gettid()
r9 = perf_event_open(&(0x7f0000001000-0x78)={0x5, 0x78, 0xfffffffffffffffa, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x663, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x8, 0x0, 0x0, 0x573, 0x0, 0x0, 0x0, 0x0, 0x0}, r5, 0x0, r6, 0x0)
get_thread_area(&(0x7f0000eff000)={0x0, 0x0, 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x6, 0x32, r6, 0x0)
r10 = gettid()
ioctl$PIO_UNIMAPCLR(r7, 0x4b68, &(0x7f0000d09000-0x6)={0x796, 0x1, 0x100000001})
perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r10, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r11 = socket$inet6_tcp(0xa, 0x1, 0x0)
getsockopt$inet6_buf(r11, 0x29, 0x20, &(0x7f0000fe6000-0x74)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f00005ce000-0x4)=0x74)
bind$unix(0xffffffffffffffff, &(0x7f0000003000)=@abs={0x1, 0x0, 0x2}, 0x8)
prctl$intptr(0x1f, 0x0)
r12 = semget$private(0x0, 0x3, 0x1)
exit(0xd800000000)
waitid(0x1, r8, 0x0, 0x2, &(0x7f0000ea6000-0x90)={{0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
tgkill(r8, r8, 0x8)
semctl$SEM_INFO(r12, 0x1, 0x13, &(0x7f0000aa3000-0x1000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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dup3(r9, r6, 0x80000)
dup2(r7, r4)
[ 50.363238] binder: undelivered TRANSACTION_ERROR: 29189
[ 50.366825] dccp_invalid_packet: pskb_may_pull failed
[ 50.374376] binder: undelivered TRANSACTION_ERROR: 29189
[ 50.400335] dccp_invalid_packet: pskb_may_pull failed
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000011000/0x3000)=nil, 0x3000, 0x1, 0x32, 0xffffffffffffffff, 0x0)
r0 = userfaultfd(0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$UFFDIO_API(r0, 0xc018aa3f, &(0x7f0000002000)={0xaa, 0x0, 0x0})
ioctl$UFFDIO_REGISTER(r0, 0xc020aa00, &(0x7f0000001000)={{&(0x7f0000011000/0x3000)=nil, 0x3000}, 0x1, 0x0})
read(r0, &(0x7f0000013000-0x3b)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x3b)
r1 = memfd_create(&(0x7f0000013000)="00", 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x2, 0x32, 0xffffffffffffffff, 0x0)
clone(0x0, &(0x7f0000b26000)="", &(0x7f0000eaa000-0x4)=0x0, &(0x7f000039b000)=0x0, &(0x7f0000bda000)="")
fcntl$getownex(r0, 0x10, &(0x7f000058b000-0x8)={0x0, <r2=>0x0})
getsockopt$inet_IP_XFRM_POLICY(r1, 0x0, 0x11, &(0x7f000066f000-0xe8)={{{@in=@rand_addr=0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r3=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@rand_addr=0x0, 0x0, 0x0}, 0x0, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f00000f7000)=0xe8)
r4 = getegid()
ioctl$DRM_IOCTL_AGP_INFO(r1, 0x80386433, &(0x7f000021b000-0xb4)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
r5 = fcntl$getown(r0, 0x9)
r6 = getuid()
r7 = getegid()
ioctl$sock_SIOCGPGRP(r1, 0x8904, &(0x7f0000271000-0x4)=<r8=>0x0)
prctl$setmm(0x23, 0x3, &(0x7f0000114000/0x1000)=nil)
setsockopt$inet_icmp_ICMP_FILTER(r1, 0x1, 0x1, &(0x7f0000467000-0x4)={0x7fff}, 0x4)
getsockopt$inet_IP_XFRM_POLICY(r1, 0x0, 0x11, &(0x7f0000858000)={{{@in=@local={0x0, 0x0, 0x0, 0x0}, @in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r9=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in=@local={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000666000-0x4)=0xe8)
getresgid(&(0x7f000055a000-0x4)=0x0, &(0x7f0000c41000)=0x0, &(0x7f0000bfc000)=<r10=>0x0)
ioctl$sock_FIOGETOWN(r1, 0x8903, &(0x7f0000104000-0x4)=<r11=>0x0)
lstat(&(0x7f00003c4000)="2e2f66696c653000", &(0x7f0000098000)={0x0, 0x0, 0x0, 0x0, <r12=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
getresgid(&(0x7f0000aef000)=0x0, &(0x7f00003a7000)=0x0, &(0x7f0000e8b000-0x4)=<r13=>0x0)
sendmsg$netlink(r1, &(0x7f0000757000)={&(0x7f0000001000-0xc)={0x0, 0x0, 0xaac, 0x8}, 0xc, &(0x7f00003eb000-0x50)=[{&(0x7f00000ac000-0x1cf)=[{0xf4, 0x1, 0x400, 0x0, 0x5, "9613b144bd4a4cf75dc3bce04c1e900a5fdb5bb8033f793d827013b6d3a5792e45692c9f7b2b3a0c51761138d26e14e40621f06944d00dee3a942f6d1b71c3a954e9c980103d9090748db7e8ac440042f6b360705f7d817d4c3becb6c5048b8ceaed97808a73108a82f7e3db2c895bf655758bc5ff70072fad617d7d160d76a7089ba22ec5808ab1fa665aea13489dbcbbe61056f070d030b45bc41f23183acf9f441f51b8c694c3e1395e7a3a5d6b8bed715e69ba33a6fc4b2788cb802892116088399e30aa467bcbf4eabb93a21f154880fb7c922bcfa39270d1164e3cf857fecea426"}, {0x89, 0x2, 0xb00, 0x3f, 0x5ff0f512, "adc748c6f5562167a2a6daa8b6f583fba513d20253db9bf30d14445cc50b694fe5e0e6a16c9c2da1ccf64b674b6f7f59ece4bb75858b3b4b2d63112a615f275008ce7d3fbab641a8bebac4ec58bb1542e6cec88448809247ee471e8d606695598e59c4cba0a5c5cd1b5520916c81f15be7f00f6f1e27c238f5"}, {0x52, 0x101, 0x21, 0x4, 0x4, "f3ab8c51ff0fbf9ff5ed6214a79b606bb41a9da08695262edb4ab4a75343fa097566f936543785d9869ac12e48b3b2f57acb371295a8636a9db4911da35f7f7d70dc"}], 0x1cf}, {&(0x7f00005e7000)=[{0x1010, 0xffffffffffffff1f, 0x0, 0x8001, 0xe748, "3f40a4e26d294baa354f8ab758dd5be1282857b9be1046a5e80b8047ce03c00192e73841d430cc4134bf3ff1d32539058b8a6bea28c9955d1b2ef6326b8a4fe230dc2c7bb589786e97979e540bb22aaf23d5659d5c0ed3104a6b86587ab9a3fbc44fc392a33ffd130db5a033fd2bc626f9d8f97f0c4192cd89a5b104ffd97ff6a0b96ab47ccfdf1f02508c69d66511fb20a0501caeea4a62cf8a6b01a300ae1b6cae1c628160e5cdf1719fa278e01d069dff751b7f20fd308562f0cc9048a46cf6115000f6f5a3b05896f0930a08fe950250e7cdd4c1f8e9101db81124df3c517120ac9e5ba8d371cc62f29a21758df418e5fe7e17d84f8174d3b01ee370e2360cd409c86811f7bba4dbf1a3f9a0ea959cde85c43426f0e06d1788e932933ac76d169ab5227944eca1333309124f2c5212f37072df05da12bc00b329ad67c7581bd30a6666baf56501ae9ec849b9c7483a2eabd0a230ad376f0af20c72ebaead8ec7c89944b4e0f3e6fbc78d3b558a1da98c978987fa6165b6b49048e9f3aec1cb0caafbd3e8dd85da9dea0eca0a43cfdb809f0c2119fc80ebf99cf3b546e46be7045bc6a23925968f329b96620327ff233b2c5c1d38a28d8cac368cfb34f55fec6bc8f96300b2441ecd807d2cf7defdfa50d61ca09cba71ccadb782008bfa597cf35f56ecfc8431df0088e6512b67e44be338c9b31bab0b7d406db7466369388069e40e3eb6ce3ce4897b4c7f4f24fdd4ac5b9eef97ec42704b2e349e0216518fd233bc490dac8ba19c5f3b9c280e05fe80ac42198c16f97ebed692898fc009b5eedc8341d5c8b35d81fa0fc346b6e07bd3e62bed522e1bfbe0881b9aa4850689de1118faeddbe386fac24beacdcdd6d5e68087aa8b59c9ff67429691fc561d04e2cd6cb9533c9624f5a5646d23f83a4c36f7d2c46846f8b4d1d0559919ec73ab07fb54959a8894188a4ea8a6dff507404ca2b8d5754a6f02168a164f06ffec4ee6cdd09c1b4baf432ddf33b7c15aee37e5ead43bf6cd3cead0d27f57aced7eb7650553ec80bbbdc258178ee712861afacd100e41375e54bb4a022ce70046d4936846ba2a98e99d7d1ce3e59764690638f584642e3be7549ed4550b9423bb1b0f25ad5194934745d960df393d9d9718a2779f087e42f7bda85aad841bd97a7f26ab1f07ebedfee35b7159f7071683d8eeb46cf35c90563c870da0de7fa67cc2b5859c4e3de50ed2f6ec8481bb853922e50ea3453feacd48fa0ee3f5de24953aed709ca300ee78fbfc327154e5be4e68107555ac729466f997d71e53cb357c140e579d5e8dbacd48a6539a190f606227a256d89d8543d1f79e0b97c193548c84cf09e6e66cb569316ac9a4c66bda23a878e66f55cafd800163d376c926668326fbe2e1bebd187ba8dad4de9c899a7bc9fe5671276ce801a7b65f4cccd4cb7d6e1e5693b24867cdee8657e1652f0fff6910bfc463f2cc267649b3a8de198cc3567100efe864e18005221f5182027221b66be5414eee4e0413f390e2dfc437f7140c02cd8c040373d6be3140feb083bdc5635f74d22396f97b24c928a05b704f0441d3c2abaa2acd3bc602591f2da4a3516f11248be529277e1e25212383d1d6c9f418caed53eb756ee55a4a7f1eec2a93bb99b2b63017e7f6b9d3c4fae4a5c70456ecf996823a48c47a91e6e2998216f8e7f4838bb1bbd5c9282e6e35bd9566eb05b46fd38a602658f26156818e602b626a4f909071c67e6898ad5f35c3c1f7288b465329a90694a4f60938e4ed1fa1cf5cf3b5a62704103079aa2a77b6760e27d1faab07c1f47c19310507f2abcad3bebac10f682892d6d004116d316b2efc4d4fdd8f607e3d7c6aa329e7609f747bfb3c5cd52ade321d6ad5f49ea82ff0f0d81b70382ecea90bc76c0a1ecaf14b52f2e11c100fc363572e21c05d28fff658502eaa199e6b0d33769807aec004c57688f9c637f1e6917e6c0f1b0eee42e9bfb2761c62b81e2c6f00dffd5e5fc01bea79409420492f4aa91ec892df6658986c503fdaa09ea32efb436713cacb11687db5b8c3df5527d977cfd11a6f66891644cc7d8443c070bf8eccb6adaf2abaf7b74bfaa9f9aebd58a92067d55735a6249b18d207f2917feac17b9a0a0145f3112a079de0f2c5bd0f002b7b155d03196933af27fa514260f54cb68313c339d7199db07eaa98314a93ec1b24c9c69b46384ea2c7a1a77b1e91c34199a8d8d90c8fd77534bf325a5efe3fe03e19f20ec6239a76dd1d1a93425adaf83fb3912843abbaef2f8d98a516d050c226b8d6f3956fb9704875cf59769151de8603268d37fe5f6810f20d0b6b92837d2a40e5c84dc81be788e9af9cd26696a18b609e106163a02b98b86a500623406291c2dd2397b82ff67b0e20254ca220674f09918fe9165ed0afb4adc4349caa1f0c90b3263b616cbf897b6e8980f4143dd12b399d0a2c67b3dda10f28e9983eacf2d8d033fc91c1ab64c5964c9a33c68e7bb1557522d0b757b185bd22a867e07a4e5e05e6ebba1680f4967775ff05d37abd62f8f6852f621ba4aa8603fe36be75e5f24881ce3e05a364ed7d239171ebde7d7b4b55fc719bb9f1573219419dfa5ceff9dd9b9a04b763bb87e8db61f2a335e976fddf2d67f3f76a92c44197538a53a2692b489e51d28ceada94599a93ea82c72dab82bd682d743258ddf8eb4d6155f0f33491bc344caf46a0538c48e7fc27a611a1853dc8c358435e138dcef0d16c952a09cd01523cbc9cd1e639fa12eaac6daf8ccf6ee9aa11138b1de488a3d14228ad32908542678c7ac85318d168134226bb50b8ebb2e96686c16c541bff612358df1a7c86c9dfddd040592e5559991daa5037914ee60a013f840ec59743528f215a18ae0d8f20f73151236051a4ab488e192a174e6870ce44d3ec9e4f76d5a5952cc9810dcafcdf9fe86af6c28c037423951c03798689ff4c5e9c3b7b3b9253b4d4b1f17998896dc0e4e8b10302189467f03fd1adc50c5543ae4da6eb611d1e4b4779174961171af1bcd52537e30a0e6766a203613b015036820cdfed87af0f4c8dc8f1ba0c0bf415d9d3fc89af8ffbfdc8cc412194a9806e79fab18b88c73a40991f67a8d73fa1765ef156e8a8e8101f27524c78bc416b493476fd0a4bd4106443a2223e285af386e2e59375d98258454e3a698fe5aa777e88d4beaa54e53d830c849d80079a724f355d3fbbb1a0ec84f7f07be027f477953b90605195bb2adf8774ce497edd851060aa5b68b7aba298b3e901c46b5fd0abde1558fdfcc4b7d8413f6678bb28fa4ab25d6d9363b4a6d1cfcad3ae747ed981af11548f0039f54df4c818953a32eec5e2ab366f41c90d040949d4c130ef3bf37e069119e47d67f36cd72a8cc34600ecbb234cacbfdcda81433dff47ab7cbcc577bfd45bf559ef00b0e8714166df663eb4a59d50d9652d8b97e2c56356c6fc4b47f31599830b7ef5db646745d9f7640857555ba32ebdb1b03e794dcf9bcea9333aa088a973fc8b794b6ff09e4b482b46de8d1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{0x59, 0x1, 0x206, 0x0, 0x6, "6c3f5fba70d81a0bd8b98bf6c69b0627a627e06e73c287902f518a5e6531942e4476b7e0a45cfc56345724554422a089031f9f3e520e19cacff22ee2aeac18b4a7745c942486f5d53b"}], 0x1069}, {&(0x7f0000280000)=[{0x10d, 0xff, 0x0, 0x200, 0x80000000, "831a0842710b037f84a5092d5ff1ba4e66ae26cafd3141b1de12dfebc7346aeef34ddfd428b12da7d4302cb4ed70dcf62e6e725404d0001db4695613ebf0739e29ddfc5d1fdc2e821434780aadcf6155af85c6a915df8957f9cdbd14da44b50fd86ce5b286761097442694d09f37d55fe11662ee711116c86cb8b48facafc5e134782778525ac54d2ddde2274bc3be1ac8517a0a75d1125ebd16ddf7b0a1523cba0b9b2ab6e3ad1728e7d48a29f477ec5253faf9f853793d2552da3db15f7836493e77e05dbd8ab66dcc135a6d717faefa2864ae14370dd627446503028ec3fb3933d961edfdbfae48437b786ebed31f399d20384215030f15d1f38e42"}, {0x57, 0x69f, 0x320, 0x7ff, 0x9, "d86ffe88f7861b437cf0a92de549321d5898adacf57c9b380e519f1366fa57aff7d03617418571b5dd998fbbc147cc87eb50e746189d1f4da9e2aba704cf8b7c0e7d0ab04c21ac"}, {0x1010, 0x3ff, 0x0, 0x2, 0x7, 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"b23f50614d7af7261d719eabb61aee25dc0015c04ed75f3d4b286ab385fb356e6e5dd7e0e3fc157377cc0c2d149374f88d5be9432af9c77b32621dfd9465ac8551d543acf2a40728c81282be957c02ac2ea9bf10b937e848604fbd537177885f1f8df07894733f434331cac244e85c152569c31bb2cbddf547848ee2dfc5426008a484cfa4636c43f560114f6ad6739542e7223b714dfe98e1ce596ee89de644497fd83d860065ce82dc463583d48722d369abb69245ec58ab2ab700c53eb7faeaae8171999425b4e1ff4f4c7adec4da687c9b825fd79e8c813dcc5cad4515e90a8794ba259366115423c4c8513270c585862bcad43b6cc34a168166092a8bbd72a43e161a60db8db34126d84c82d9bc24c2b0b84771726acbfd0c6eaa9bdda763fdd64a5fda9e2af8e7fe674d836682c7ddd470f146b0ee01eb7be839027e1bca4f235eaf970ef2b3554e410322f0318a0604351429711a2a559c5098560aa18387384ea846ee98a01ec9fbcabe59ebf55d40d108a34f39a8fac14f30a67c421b521d6ede0afab73cfaf0f104da0a93c59c2e61028b037cd5deeebc984c0c7bf5935bedd2bbb0a4fa97a23e40802315123e0959a88cab902fc34627a411fdffce4d278b340a8c367c1e75fe666d38217601913a7b78adaad6ed52b817dacfb4135e2d854f0751c025198618a6eddc6bf88e72ac6012c33967618eeebd4a75d46a7cf4ea55817bff7ece170825ff8ffd990a294a01ee2393e7c7490fc8cac030907c5897d0abafd50b3fda13151531e6633e76129d9dd7b1c33df2dc2ead26d44e1dc81a7ecf89b97c5c5d43c096daeaea565a8888bca64e380a454bf01813a271db6751af0c508e8bc800526a867ce6a19948872608843ac10ad24ef7ff2dc848cd3e24cd1e17c606b528d6e2a49f099e05954767a6862c1a5af88556b0605c68084920050ab4cc8e579c84389af93b24b5a31424bb0310f3b7eb14b5c9e043a202b79dcce7d0eec2f9858b10012722699169d95612ffd3ba0b0154c3a8cd41c5fbd0369de7bca20be83dbc8e8b70129c36999fd34da0338e7e886eb68c3125ebd1cbf8acc5e04515ad9612c3456d493e1532863042da262936cfdc47dcfa7aac1a7bc3de27a304923614c3ee8ca428ad2cffb86f6e383113d79b88582aff3c6df7f89ca604ae2bd48705430f9f72ac5b7ae89d55eb93d4d0fdc2676e4c544d8f296c74e964495a905fe391cdc9d438642293afc322761c8c9837abed472edfe478e3a761c4337d21bf7220d25d82f5a51c3d306a7d0c18b2819d61d961c06959c16344df75983982689bfca846e2eb626c3d5d4a7624de212aa735db433c7dc25d034c5b1354a42fbcb3b5d30fb4d5a0e3d3c0401c2178e98349b6318c43427486ff47e451c93cceaafc052fce3b93def35cd3c1a1649181f9a5d5099a0665a5f7236c5a83f19aca31bdc8efdaa14464f42a7485575610085cd43b24c0443b9765a16790bc7856459e34354a80fd707c3d54f73c8cd27af2e5ef2b9ebe41b886dbb14ec0c12e5d4a9af041753595f8cae0a459ae693d158d6276c38e8574dd284f653e1ed1ea11a3e705e766fe49ed57b8736e620cf73121d96eab5c8dfa65b5bdb9645b72f7815b66ab4cc01f2d921e5a8a81443975f6ba139ca1cdf932d1136d37bcfff437897410c55ef8b34babbfb34aeb0186c4d144c8b48c14bbe953c6cabeed6a9b04b0a7227d12bb5729de160ae52954df4d15ae020baab501d7fda3df07a1de58e2272d115a2b5ad096e2470ace67ee6b7de396c73052b68f2aa49c271461dd756df2e91d7ede7003d52b1a490c48275e93e452b6457392cf1d44461c92f75b5546180a8ee7e43c4be2aecd003ff8799090326146f3f8dd17c1c36c4c73f2dff82edd622fa27eb70ed1deee207a849b61f4bddcd209a7cea75a81c996d9501f8fae53c324743908fbcfb2f35bd69580f8f7144772c44cc46078f608d37c529506118a68359d5d3800b6a791b47629d294a30b59f7ee0477c05b9b8916f63085f3654a7ec056ac4040a58e4cfb0b8da892c90786377733aa4c00dad42c27334f4ae0553027598156e8f34e755a7a810fe0b79048dfcd6b59ea370e56fab146ee885d6ed42122dd0837f67d19e10f721feb7094a9cb73338c1b3af0a3aa4faddc86a4004c32c3d899987b8c10da845fd802548f1d91525921ad8097881e95675b7b02c2a1056c188246a5be271adcd3137dce2f9c53441871808d5734cc47234943cc5fdd5e4c22c619ab9fb7c8203593438ab0d70705ac18be7477d6118cd4088dfcbeee999bf88170ebbf75f40a5ea876a0b7af975f98fa4d36661794c26652f84f3db37ca70eccc2d1f4335ccab8de6781047057613c1c7ab83d83430237ea01f1eea64a3864390cb9267b2d70a599c309f2adf583e431b41dceddb13a295e93a46cef8b1fdd32f43a5893489a8a40477c022e9fd2b60f504da80b2fbfd6f3076213f7f32c8e8a867c5568e07bf67f647f178271c2efd73a0909eb519d0e675674e5a56e296ce7d8c6faa3ee955033a157e9c800bed79382ec4257cfc7effaddb2fcb19aa30eb14a8b97a26d48ea46a990b1c5acb022195a43489d2ebcbb2bf6a5fc41f77f9fe90862d4610234358fc72762260db002b2f0bd47c6cb2afdab013674cd55e576afeee98fc0e259b4339b714e75340c2dc79eb432dc07ec65b4ee8eaa46977c9be4dcfb0366568c3cf6e32ab183a67485268d853d41a74fa9b10d45e43413d5194aed58a75dfdc89e98debecdc0aff1070b948e83bc547e8f344816cc16222f8be001661029b346ba2256a7ecdfb4d8e33eaaea422b0f9b309151d2e438ccfc0bb7c6f8df5c8259926a9713bb0ae6f8a34fe522066c5e1101eae4aefdd7d81d02307cc85505f6de45a1305efa1d1ca2d3b9e8b39b26cb21e59b14f68810228214c086d0629dd250d6cfb16efbdb7e05fcf9e959e19154b43773a41765d2e78ab85a0fd75d29aca1dba79b8b4ec7b42a0cbb23f8067eb0b010bc33c77395e9e54a9b2d7dcd214b2a0300ff90530620af0723308672ae5649b530365e1354e14c8f746d5ddb4db9da00e3821e2bfe8bb0ee1b71342fd0ae7ad680c342080fd0c83a9ed12c3c0661dce2ed3bbd1dec3ac0eed7bf642eb8ead2d02b959dad665ca77277f6530377c6b22605d4ffc66476bb29d817677ea5ec1a99b272935a6886c3a5a6109f1d9ff5c87a981256423c990819856f037b225fb943935c85b906434a31b0080c9d34dc03abc5f3d75bf25abd4fb74e4aa6063f203cd9459d4e863cf9d4c7f34047e3c155612d17172527e3d892650d2fdc925ca844dd32c566ee070d8f83753fc1c20d4a349bf2bb9ad695d761f36319c3afc7bb08321b8130bdf12011e4821d9cf41401e4b2141d907454c179cc8870d59de83a24e0b2fb41eea92f6151aec728e0f641905ec1e723c0050366e9b8b5fa0a097406f6887e5f227e2a99f67e45953205e4099da7266915c0d27b2b5b18f308305f8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{0xc6, 0x8020, 0x100, 0x819, 0x6, "220d6835792f06b963c7ab644709b2b17da6fc53148a498035e5f12cb22705e5d84c07a6e7c8568b02659722aaec14d3206fc479e55a83e23cc3da727d1c13db97884b853862c00590944ef34634c797c7b5033ad14574a7b55b529419b4bcbb0fea2b4ad24379d8344aba6194d5f5386486345790264ccec58217a1f0efd357d2d127e128e47c866cf1fe4853f64a7078d0e3e9368972175943f82cb64065696b2584ec100603007c51c23a03dc0bb21383ab598687"}, {0x10e, 0x0, 0x100, 0x0, 0xfffffffffffffff9, "3d80d3ed5c24ebf2e6a47c2c5ba0e0fde21f84cedf40c2d90e33056cb080d0330794856e239e2eb0676eff5ce3279dd1768df7b2ba618bd6632110ea857d564560808f81308e625cbe8cd29a34d0b798174e79177c92148d36f7237b1a5db9fb8d50dfffe08ba54c699ff1fcf5730dbac17b65ce3a12d4ae98fd39a3b10364a2366de622a37a1aac298dfcede4012cabde84a339285f1589049fb7c3c7a0d410740d5600274a58d1830303bc934429450d936ebad722cdda224b8505b6c35c141067c21e1b9875137db31b2910b88e90159620d5d6a7dfced05b5fc2370cc9e452ddb0f9ba94e7a37e1bc5344c75cad2092b56944760b39c9b2cd429b2f6"}], 0x22a4}, {&(0x7f000016c000)=[{0x19, 0x6a84, 0x100, 0x6, 0xff, "420d704daa9554ac5d"}, {0x10e, 0xfffffffffffffff8, 0x400, 0x0, 0xffffffff80000001, "170c829abb6cb562cd898a05f7689e2600f822ef20329d598ada9b43e1e4543fde6728a6f6b23dc4f83fc74a01acde007687f4687bf0b97e231305d32c1ad7c0732672b29faa41314523ca76a874a921be0b24ae135bf075e84428d472521c313cba92c2751ceabb907289e9ea43da10932f00f3cb4e11200af6653a09282d2f301e8aa9ea84e9cf2baaa4b619a6ebf6ed49e6c56a603aa699d8eada3f3b2e740d9cc939548bd1be1e25648a66099e3ea783d4953008acb37f3fa471c9ad7650f78daa659878c54efe1cc48dea693c991823cf84644fffc433f3aaa4f41c4ae0a482f16c2eb4c4bab8cde698483206e300d3ec2b43f9bfc1ee97a48aaa1b"}], 0x127}], 0x5, &(0x7f0000096000)=[@cred={0x20, 0x1, 0x2, r2, r3, r4}, @rights={0x28, 0x1, 0x1, [r1, r1, r0, r1, r1]}, @cred={0x20, 0x1, 0x2, r5, r6, r7}, @cred={0x20, 0x1, 0x2, r8, r9, r10}, @rights={0x30, 0x1, 0x1, [r0, r1, r1, r1, r1, r0, r1, r0]}, @cred={0x20, 0x1, 0x2, r11, r12, r13}], 0xd8, 0x890}, 0x80)
ioctl$UFFDIO_ZEROPAGE(r0, 0x8010aa02, &(0x7f00000c1000-0x10)={&(0x7f0000011000/0x3000)=nil, 0x3000})
flistxattr(r1, &(0x7f0000148000-0xd5)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd5)
mq_unlink(&(0x7f0000587000-0x2)="5d00")
2017/12/15 11:53:26 executing program 4:
mmap(&(0x7f0000000000/0x7b5000)=nil, 0x7b5000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = inotify_init1(0x800)
mmap(&(0x7f00007b5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
signalfd(r0, &(0x7f00007b6000-0x8)={0x0}, 0x8)
mkdir(&(0x7f000002a000-0xa)="2e2f636f6e74726f6c00", 0x0)
r1 = inotify_init1(0x80800)
mmap(&(0x7f0000000000/0xb28000)=nil, 0xb28000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
nanosleep(&(0x7f00004e8000)={0x773593fc, 0xffffffff}, &(0x7f0000001000-0x10)={0x0, 0x0})
mmap(&(0x7f0000b28000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = open(&(0x7f0000b29000-0xa)="2e2f636f6e74726f6c00", 0x40000, 0x11)
mmap(&(0x7f0000b28000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
write(r1, &(0x7f00005de000-0x1)="96", 0x1)
ioctl$KDDELIO(r2, 0x4b35, 0xfffffffffffffff6)
r3 = open(&(0x7f0000b26000)="2e2f636f6e74726f6c00", 0x80000, 0x0)
r4 = msgget$private(0x0, 0x1)
msgctl$IPC_INFO(r4, 0x3, &(0x7f0000b26000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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r5 = creat(&(0x7f0000015000-0xa)="2e2f62757300", 0x0)
mount(&(0x7f000001b000-0x6)="2e2f62757300", &(0x7f000080b000-0x6)="2e2f62757300", &(0x7f000001a000)="6578743400", 0x1408, &(0x7f000001a000)="")
mmap(&(0x7f0000b29000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mount(&(0x7f0000028000)="2e2f62757300", &(0x7f0000b2a000-0xa)="2e2f62757300", &(0x7f00008fd000)="6d73646f7300", 0x2008, &(0x7f0000004000-0xa2)="")
ioctl$DRM_IOCTL_SET_VERSION(r3, 0xc0106407, &(0x7f0000b27000-0x10)={0x2, 0x2, 0x5, 0x6})
clock_gettime(0x5, &(0x7f00000ab000)={0x0, 0x0})
epoll_create1(0x8080100)
ioctl$sock_inet_SIOCGARP(r5, 0x8954, &(0x7f0000b28000)={{0x2, 0x3, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x0, @random="741a3dca7844", [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, {0x2, 0x3, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @generic="bda377a3ec44ea2bc3baf3b1915b032d"})
r6 = fcntl$getown(r2, 0x9)
ptrace$setregs(0xf, r6, 0x7, &(0x7f000089b000-0x7c)="455fc2733b55987b9c9e25e39883f7f4df738fef1774f3d55b1a2a9322f7fd3c0a27c56d4fb45eb5d4e3aa5ee50f15c2e4e75e08936ea8b130b13253f9513d659a1fd1d026adca357fd7a90ffe997bd2a178e30d0e1201edecfba4c915a64ff031351f2e2f88735adc655e29d08e59f6f44369cd918a32001ebbe472")
clock_gettime(0xfffffffffffffff1, &(0x7f0000b28000-0x10)={0x0, 0x0})
rename(&(0x7f0000b29000-0xa)="2e2f636f6e74726f6c00", &(0x7f00000e0000-0x6)="2e2f62757300")
ftruncate(r3, 0xffd)
r7 = gettid()
fcntl$setown(r3, 0x8, r7)
mmap(&(0x7f0000b29000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
rt_sigprocmask(0x0, &(0x7f000003b000)={0xfffffffffffffffe}, 0x0, 0x8)
[ 50.411261] device gre0 entered promiscuous mode
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = creat(&(0x7f00008b5000)="2e2f66696c653000", 0x40)
r1 = msgget$private(0x0, 0x308)
msgctl$IPC_STAT(r1, 0x2, &(0x7f0000cc8000-0xdf)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
ioctl$KVM_IRQ_LINE(r0, 0x4008ae61, &(0x7f00009c6000)={0xffffffff, 0xd7})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x96c, 0x1, 0x0, 0x0, 0x0, 0x10000, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = bpf$PROG_LOAD(0x5, &(0x7f0000f9c000)={0x1, 0x1, &(0x7f0000ad5000)=[@generic={0xd39d, 0x0, 0x0, 0x0}], &(0x7f0000bba000-0x7)="8b797374f7006d", 0xffffffff, 0x80, &(0x7f0000da8000-0x80)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
signalfd4(r2, &(0x7f000022f000)={0x5}, 0x8, 0x0)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = open$dir(&(0x7f0000bf7000)="2e2f66696c653000", 0x10000fff6, 0x4373cafdc23a051a)
r1 = openat$kvm(0xffffffffffffff9c, &(0x7f000034b000-0x9)="2f6465762f6b766d00", 0x0, 0x0)
r2 = ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
r3 = perf_event_open(&(0x7f000002f000-0x78)={0x2, 0x78, 0x43, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
sched_setaffinity(0x0, 0x8, &(0x7f0000976000)=0x75)
gettid()
r4 = syz_open_dev$mice(&(0x7f0000001000-0x10)="2f6465762f696e7075742f6d69636500", 0x0, 0x2)
pipe2(&(0x7f0000c62000)={<r5=>0xffffffffffffffff, <r6=>0xffffffffffffffff}, 0x0)
sendto$packet(r4, &(0x7f0000edf000-0xc2)="3fa399f8c76eda975d2ae5c319b18498eef5c18e5e0a52171ae1901dc6a17a9a5becb649a7234b0747c0a01db33a5b7eb08d5ae55b5bda1f361692b52824081b75c6589872d3d6d6f55ee6a6d080285d79b6f3556f7ba6b8e0039d712cbd3e1d0f2fec57c42a145d614cd00077fd8dfd8b2cb609bbd7fa1cacc047354e5464c3572a2df34376a3d574cd66efdd20c3432a74969913ba153fd53479f9c6fabebd573df7e79f3dc57f8386214818fa321cd85ac5398f1e435690c09660db6c2c259a15", 0xc2, 0x80, &(0x7f000028b000-0x14)={0x11, 0x4, 0x0, 0x1, 0xffffffff, 0x6, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, 0x14)
vmsplice(r6, &(0x7f0000d87000-0x30)=[{&(0x7f0000e36000-0xb9)="ab", 0x1}], 0x1, 0x0)
timer_create(0x3, &(0x7f00003f7000-0x60)={0x0, 0x8, 0x2, @thr={&(0x7f0000b35000-0xc9)="ceceee3244684b53e5774c78abb31c6fe2f34fe3343665afb4f80bd30244c1042f22a6891533d7942e1ce282fb5ca942cf49ddedadaadfff5fd4a66c5adcb2ba8f550a1b6b95db2d22dd2e9c5a9be924158166f08efbbcee76ef09542265b3c55ca13b05726962dee954f2b9a9689fa22676104fed33d1b4a1910bb106fc0343a8809f021008e306e48f6c5eb8e33ac8d22b9023f42dfab19cb7e9f0b74a26ef8bc80a5e4de0029a1cf26716c41a4f8e403360ca318edc10205f9d0002a1bdf3cddf96863d233e0cd3", &(0x7f0000efc000)="ef44616570614d37549c5c536bc3e014ee690d9fdace652ec55dbbbe3170b0b117c5c2b00aae0dde8efc2932273fd42532ba0d3e87d184696c3c367b08af2bd30a47b94d6159e34fa2951cc4cb1b4b9db161a6f5192d3fe8c748b61a0bf685295dcf5ee44e7e905a189ff3"}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f000035e000-0x4)=<r7=>0x0)
timer_settime(r7, 0x1, &(0x7f0000793000-0x20)={{0x0, 0x0}, {0x77359400, 0x0}}, &(0x7f0000d72000)={{0x0, 0x0}, {0x0, 0x0}})
bpf$BPF_PROG_TEST_RUN(0xa, &(0x7f00003cd000)={r4, 0x0, 0xef, 0x5, &(0x7f0000243000)="22e2805a4b5f8a6168524bdb2cc8d4bc61e5bb6d4d8cd7672c5ae53302d86d7b7e9be0362da586242af353bdaf36b19703e3080157b0d83413adb1be3fc3594efc5ef822a9058342a8e7ceac4c62d02c8c6729b80da7fa5777d0d32dee1031a3c2a8748ccadef5e2e64b8d990756e4284d5f289400c9b65cf68e179a38945a740600c07582d37f805a591715447d12519da484ec9635eb183249a8d547021d54f608dcc19cee024547e9b9bd0a8ec7ce910848c0e1e68f3daf8c01b6c585b3b95524680867a0b3c8a78da22e2262f2a41b92229a2e95da847af50ea0e098524408689f6f61fc24304d6472011c77a7", &(0x7f00008c3000-0x5)="0000000000", 0x8, 0x401}, 0x28)
fcntl$getown(r0, 0x9)
writev(r4, &(0x7f0000fb9000)=[{&(0x7f0000549000-0x4c)="57767aac639d6d174e6797da36cfdadb909495aae79b336f4e0f0a10825e546dec6957037a783467a53fc2900af2b51108e8af568df04a6d676be2d2140a0a7abb05e3554d0ccd6eba0fe229", 0x4c}, {&(0x7f0000e03000)="3b77c19b268558c2524d8e8af218b401925e88f2a9ebb91ec99a3af720a4ffdfb3b37ec7f925be767d081998e473943f99e73f2880aa4e5ad851c605cb8b85d3b75d8a719b14bd56c92c", 0x4a}, {&(0x7f0000639000)="6bde43731fe8ab9e7d1fac0428d03971aed1a4a9bbba1902ed720f53caf646", 0x1f}, {&(0x7f0000cec000-0x50)="14952c3e516d5aaa7d7f64a91e0dcea7fcf9be5bc7ba4d95e066cf6854af38068ee81031e405e9c672e6674dc1d68eed9782d24eb98c4c31c3b5282378f6f9ffcb0cce8fb9ce257a4b0502582b78be6e", 0x50}, {&(0x7f0000bf2000)="cab1cbfef7bd1290f253296b7c4d3cbdb4f082bd281459c434b534088972c1aa576b3815933fa5434a40b105cbd458f9dd8e0281f9830f28490813686ea9c0824c8b025005d32af3a31764c19d95a7b0861e432c842466088e61cb9b298bbb2fd17e41dcaf115e9896ee469a24b5e16aaa03cb349b5d84f6e30d2fb349", 0x7d}], 0x5)
r8 = ioctl$KVM_CREATE_VCPU(r5, 0xae41, 0x2)
ioctl$KVM_SET_USER_MEMORY_REGION(r2, 0x4020ae46, &(0x7f0000e38000-0x20)={0x0, 0x2, 0x0, 0x1000, &(0x7f0000005000/0x1000)=nil})
open$dir(&(0x7f00006d9000)="2e2f66696c653000", 0x40280, 0x80)
r9 = dup(r3)
ioctl$DRM_IOCTL_MODE_GETCRTC(0xffffffffffffffff, 0xc06864a1, &(0x7f0000011000)={&(0x7f0000005000)=[0x1, 0x800f7], 0x2, 0x0, 0x0, 0x80, 0x2, 0x6, {0x8, 0x208, 0x0, 0x0, 0x3, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x7, 0x4, 0x6d57, 0x0, "5c3981e33f5e3048688f9251519e632912a33d00000000000080019e44e8d117"}})
ioctl$KDDISABIO(r5, 0x4b37)
ioctl$KVM_SET_SREGS(r8, 0x4138ae84, &(0x7f0000002000)={{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x53, 0x0, 0x0, 0x0}, {0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, [0x0, 0x0, 0x0]}, 0x80000016, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_CREATE_VM(0xffffffffffffffff, 0xae01, 0x0)
ioctl$KVM_TRANSLATE(r8, 0xc018ae85, &(0x7f000001e000)={0x1001, 0x4, 0x0, 0x40000000000000, 0x40000002})
ioctl$KVM_XEN_HVM_CONFIG(r9, 0x4038ae7a, &(0x7f0000a68000-0x38)={0x6, 0xbbf, &(0x7f0000db2000)="c2dd65bc38d83672d46a25f33ebe3f792ef41361bb881d3881c9e73530f1d8c98fb5bb2a4b2e8f41dc0664d3e9574baf6c5128cf4aefa76eca009c2cab3df5849d6802d476aee665e217343abe386fcd253db2ccb9dbaa743fd7d70d85c7161ce970445d15d691b50c65529892", &(0x7f000013a000-0x47)="fd94ddbba6e815bb7b9f4f29d13bf6510ce634de0af00a955682184d330ab5df64a51bbcb71face7ae8a12bb7dde5af5a0a57c85c07bb08b807176ad625ff007de78482b14c377", 0x6d, 0x47, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
recvfrom$ipx(r5, &(0x7f00002ec000-0xe4)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe4, 0x2, &(0x7f0000bcb000-0x10)={0x4, 0x401, 0x2, "045d5ff6b614", 0x8, 0x0}, 0x10)
syz_open_dev$loop(&(0x7f0000cb5000-0xb)="2f6465762f6c6f6f702300", 0x0, 0x800)
ioctl$KVM_GET_DEBUGREGS(r6, 0x8080aea1, &(0x7f0000214000)={[0x0, 0x0, 0x0, 0x0], 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$SO_ATTACH_FILTER(r5, 0x1, 0x1a, &(0x7f0000e2f000)={0x1, &(0x7f000028b000-0x8)=[{0x3, 0x2, 0xfb, 0xfffffffffffffc00}]}, 0x10)
2017/12/15 11:53:26 executing program 1:
mmap(&(0x7f0000000000/0x16000)=nil, 0x16000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = userfaultfd(0x0)
ioctl$UFFDIO_API(r0, 0xc018aa3f, &(0x7f0000002000)={0xaa, 0x0, 0x0})
mmap(&(0x7f0000016000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket$inet_sctp(0x2, 0x1, 0x84)
mmap(&(0x7f0000017000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_CONTEXT(0xffffffffffffff9c, 0x84, 0x11, &(0x7f0000017000+0x117)={<r2=>0x0, 0x2}, &(0x7f0000003000)=0x8)
getsockopt$inet_sctp_SCTP_DEFAULT_SNDINFO(r1, 0x84, 0x22, &(0x7f0000004000)={0x0, 0xb, 0x6, 0x81, r2}, &(0x7f000000a000-0x4)=0x10)
r3 = openat$selinux_avc_cache_threshold(0xffffffffffffff9c, &(0x7f0000018000-0x1d)="2f73656c696e75782f6176632f63616368655f7468726573686f6c6400", 0x2, 0x0)
mmap(&(0x7f0000018000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendmmsg$nfc_llcp(r3, &(0x7f0000019000-0x38)=[{&(0x7f0000015000-0x60)={0x27, 0x1, 0x2, 0x5, 0x3, 0x624f, "452cf42c0f17cd967d9056018eb5dcdb997d69ae22a5c611f7dcfb270b569365d9b499a6820823299b08d9020ec5cbfa2f540c25a02c51ae712349c8df4be4", 0x0}, 0x60, &(0x7f0000007000)=[{&(0x7f000000b000-0x1000)="48621e8dba8b7d43ee444f9df3a4ba1e196a09d05979c7c68b1b45d282adbe5c4884d23a290cf12039d337f4cd22e74f8e382574bd8e7eb9935c72b950e232e86cb8674b4d160fea87d6bf46bc12afc72e44b26c5acdac231e0cd190debed0228b638b63ab835d960be391599a14a316b39e7face672f7ecc6ce64c3551c6fa1a75b8849d73be15212e336e3fc30c8c7c8e3070f1c3c18e6d6b4c09747a37c68b75dd7fe42b81dac1c3685911b8055b87e499ff0206a8dbe5709d0047f8df8080e3ce184ca4afe2a993338cfaa5fc6ebe82ff570c8a38d7bf36e6f2f5ad9634021407044fe12794dbca647310dd83c9160eadf475704f36b3a71933a40e3c6df3b7fa880fc4ead4f4c68cf492f2d10032fdb40305b0b853964660652f00560f11f02cf431cee56f97cc5bfa83c15e7c56748e147a674687d501b5b34b8e1edf8d2cfbdcf12296dcee397b8c9225dc0ddff36fa6e951d59ffe288bc2ee2ac1b74c0f0848c44eef10e3374ef25a3b2c28ea260cc2c5ca4cf96f05f47fef3c0feb558680b1dfeb375cd2c4b7fc5ac44075c33161b60e3453bf9ad8d1cfda09e6fd12354120cba3f5b728256f7ad775e3a1a215a19c2ffb5a8f199321a96a6e48236c6487cc8437953f91c09fe0b151755f7930fc9cc051e4c9bf1fe0b5002b14cddd33f588ca653513e1905009e7aa456b23b883f8289b2a4f3e58c4e3d8bdde9a2d044dc82ed684423d3d9aba15d21f7d36bf08a8d700694da447977e716c6aaa05a3169f50c37a502a31289ab1901fc3dec470d26d782c70a922247c7cc65b0f09f6956a612a0a3bc8a75bb8786675311429aaf08b4f6396ac99dcb91ae465d083f1dc3b5fa126147443125afd39dcb34dec9c0de060cb47d2a784772d2610f0a12749bf5394dc4086928541420da0f8ced7edcc9ac7c6d09299e05d0a8df2d74149a626876f32fc3d06dd3d80f50669d15d5c16dd967627a7f54e7d66b4881c67dadbec5465c4bb4d42b8cb5aa4afa36d546f4623b3a6519c781cd542784b8fd531b59a108e7715f7e27e20881cb7914c1db4f74c9be3a28f2da9c4842f70d0e0f1387823aa75ec12a6a1e6abde09668ec7034fcec7b279c2ca3dd2a2f552a05104d7555d76e302e0e7d482147dcb193d04fa132989ab298701242e3847d411e7d5d8b0c3850d083b0d954559f09f711da7eb1aeab060cde2d1db0fc6a4d478e90ea1aac57624686d299e7fabfbf4a8de4804e1fc17f4cc6ae4a8416b4338fea37ae0dddcc5c053142e9218487ba277652f4bb416aa1cb1523c55d0df50dd3e25baa4eeff2194b50a0e268272d68bc2caa0f09f785d0f3124c8c9cb6852bc4268d9a62065bcb7595ee6e798a882dd723264ada1a6915f23c141b297f75a8ff539ee164f315b107926547467a992fe1eb136f7c3ce644e11eed9b2482a6f09c9c69d3e70ab42431bc7fe98714a67c112e6929d68637e399f7f44501c44e40175db0683977763f7543a52baef341854dbd15d91a7a732409222c1ace4ad393ba84d328dc4885ead8cc9d71b0bd88db2f7da7bddf15bedd44b510ff16e03389acc756b7009e17ef29dfb8d8bf0d1d6221b37e1a778ab2eb3c8aff4a80fec06a60a4bf4e755a566681efd837f59e17b1717b3144d4e45f9367985489b0eeea38aac6dfa99bcee10d5d558adf4ce474491f157c0ab302e52b8315ee6c74176d8b71fc4a6dc40309e7183744713b6f54505fa3f04d78681210489f0e36e04cec9738ea98c24013682e1d5c656830495a8435edd27baa107083ba31316a18ee59c7a3f68675d7f3301607b18cc07434d20d8db2722b41c171179fb01066c0f35d27438fdc27ee1ce282976e2280faac0e4976eda3a5cb74b2dc593cc57380d677fa82a1d86e7a2262e58388490f224f154ca87b60229ca607bf12caa63ab9f2b495e93f912e3f1abc1c9e6f202e6ad4c0c9f198388ab3ed1a3e8b56839503ee6248683100f36f4ff9e3194a08476bc8db72fe30f461800ef508fef2011b1b7a1b59d0efd9bd510d352f171772a8df50f7e1498545905746d5edec8b723bdbb731bcd7afff96b60a642bb156aed66734d6b819567c988c858256adc782c887f0a3e33a9751fd2a44c518418a8830ba6806130e8ade5403aab433434121c37526572d669097206a9c29bbd35b149a91465716f44e05906d5dc32329533e2877f95f97331b4cd4329d8ce7ad8d1f8af14921344b6adab6415831d5bfab8a4cff6f550e9d15ce0798e126b96ebe840bed1a0659e6961055ab6166430471236e92c93fb2e8124f482d50cb387c91b42e4e5f6fc6c4536867b477fd561492b422f3b914d727a20171022a2d8f82318131884473af057e0a1b6ee37303054664d6923e5b95f7d158d1a906f8cdd59c64b2d8a4564bd777acb8d20fea7ae52717898812d9a3a9a03c462f6e36fecda4643148f919537056c9772169f6a0b6b1a02fd4289f365cd8a4f2f3e3ec044586fe78679fa2145e6cdb26e28ad82cb19514391ea4a0b1daee337a23e4b81288ce216da7ea6f7642e39b4b2250c8add0c2c889b1ffd1c9133ebcca937744dc5b6dc57a98cb49bf3a2469c43c44add486bcc400d6dde1591ee42c1acaa9864e312513ba9659f48afb6f9078180864e0eba0289cf947e1aa4f6d0ce748dc786ef4903297a265d6cd655a3d91099f676ae98df87421ab87b256a07a578497fa95c43713afce02028bc5ca47cce6b40786cc47a50108003ff551deed853dd0c8f78b4e558725a88b031157f4f577b0c60b987cd61da58d3a408a69a6ecd38f2c88e90556815e49dccb3ce12af0334aadc155503a6720ab418184714a39c61b4c0febbef80cf7af9a9d6751392500e8eceaf747a11af282f8720437292c3317b9ef44243ef38a1686ea371f7f8bc0f8d2a49efb09fc25d9a7472542795255877c7a047f982fbd88b7ea1f90d7485016cdf1a3dd364d6a3bae83568b229309025def5f0fec7e68dcf1efe4fd382fc47edcca9053e889e0ed865b1b9390fb1541c4383c003abae3505ed5f855fd79440cffa1c133b8a99002fc0ae8b22f6f2e968614f80818e9be43dfd31c3057bcafb56db9404e84121e2410a0a093d2e0ae0c6e75455052921c0e59258b613398e6a413cd68afbde750655b7415609f224543e9439c4caa257d1454fe93f2d05b63d0e5411b9e27493a7221036d3d522d1b61d92ff3d682c3ac935b47ff8f8cb81c3a1e515550958b4b5344926ebf22e22cf9b6c1865bfa7abf49cdd0eab0f0fb3c1e919f175badc70663b92f8a7465affaf7f79f48022d52f63e2d179defb99bbc4c28322ba5af6c585cbf14c3c382ca2c3c1b1277a2559dec0c500def32b2041ee12e0e8573490b23088ecbdd17775c147c916598b1c190735064c93eb7deb34bdeef95fa0489ebbab4197114b41f91f088e85a0e87ad5175dac1362e52776cb4dc6b0dd0bc08eec79f9cfeb7494a216536049fdf54091a6c12ae0b10310beae912ed5a156eed4cdafdb8a99297487b745e12085d9a475f4c2633c0cf53f1a9c1adaed2d195c1ccd005c7ab9f0d4a54f25d65aa792e4df64b3dfee6ceb50a38e122e7a57798d88ac3eb89ac25ec14c989e532aaa0abd7bb33d75656e962b49a93f2054e3e5d789f07f9895839909dc38a68a67ba46ddc0c10e22ff510b56499f9a7b84cf0826a4dfd38c0b188e72880b6085b14f124b1a61cf3fa2665fce883b31827125a18bd481fe57f5445185fe61cd8d17232c367d321a9f3c5ea5da33854e7203060a2ade66a1a978a0bb809343ac759f31493344774729f3901ebfd70a7bd7a8b3744d4178c245d17c250e6806e11cbcb1dbd3a71cbb98e80fbf0780fa0420094f2c7ddea08f36eca9fa02c212cae4b295a5029d09d38d3b1fe8f118d8774ffd43b1644d86148301c73fec3204048c2a6dbe97f7f0fb0d8e4dbf6c9f90a6017a6f8fd416b1a5bdd9e79a096b8454f982df5ca2bf4991d11150d5885fa6d9db29b595e9227208e4b6cb68984fade7c36a19be882f6b35cf81c4b0aeb019470a9c219ccb6177e31e59d3363e280fad2d7ac23724517e0587fc04014a045bbd55ab16486affdfa618568e688df147d6adaae6e54937c91edb5690536149b04ad77e8cee08a6d37dbd87d39500c9d2f4c8669338df4a4259732357ac554c58063fa8498c3008ca4348662fc84b629adc3d0f12d8ce1c124dd324d49745504629c20503f66c95d795a846c98724d8d8b32a89945b358513a6cbdac817d5377ff1b43452ee43ce385b7aae7651e20011670ce0e5be867b9b2237e5f6eea6a77fcac559362e4d8461eabae902d26182f300efff6fa0217ae7ec967edcf858b80cb32aaae9be31605f252c6a3ac56d4fa5980a51035a1bede4e544f1ac0a83346a88c4f08375db453fb7b07972a955fde5ffa1a22f167c202547d17b3533d9cc3a2e1774e44fbfd09036a04a4ad55de292bee7ffb5c3b41e3d450b76fcb9b23720782b8180be7f39b751a45eff9a3fa9f04ab281b56abec9a4f66d1e8329ee90544e89877eb9ddaf1dce648ba1da2460acedc77eca94a6a1c809e5bec5fe5086a42d4d52b0aebd401a7a3327866a95a71dc330f5314a63aeb076d1f6fc93baaa174ac62083bf39ac26cd2f7c9658bb28e3f580f57d8632cb05525f0abd3638ec8bf90fc06533000f4dd0f3a40b0546bd889c87773519d55a400ad2ca980a635b87230a3f2bed8ec1fa2ec93068efba6b82e165b04fec4b4b33dc603c533bee35c6f5954e127797920277e70c21983c8748e6a322af2b6dcc303d360e28ef48f693e76a0132032d3dd5d321b9154e9f5e1133a0f6d1870f09626147f11fd334f4cc6de89d959ef6362711fbd6df8509601ef3e2454008edda7f76e3790f9e4a48f0fae6d42e80cc26bcc3504044c141ee3d71c94bbe931b4bb4a5ca689cfbde802df298ddb725948647d050742753ff985d41c83447f9e6766ef5d0c38ae7a445f1e531cdd339e1471c6dfea59bfd5d8d9eefb1595952f98bf5a9e08718eb95033f13adda81bd8f0d0e4dc87ec30898d3c8b90822a9334f125d2105d84b50558cd75aa19b6d91afbcffe841ac41cce33c1ea1ac9e9a5162a278b5f991484e173a6d3715b8ae93aa7396be7ad69e354bff9cc3e67afca8f332b43a5dedeac83fbc420e4fe950ecafdfb6fb1638d09a724bf783d6d9b1537e151a6c51feb16e06ac013bde8aa502f75e3e9edb72c68d12ea9cc6ceebe7a17cdb1b6c03a7d162c963e8d3e465bb1b5e1d823fe05612658c203892ad15ea9ab0e17e8e4e95741e8d8c1c54f6bd9b7e73bb7264e0054deade713f05f24ea17b43c1cb53474d2dd98b101088d348f2b7339dd80344c05dba91a490a476f72891f3964d898c81df8a9db1dc186720133702174a6a3592513d5c31f0f682687f385f5706f40c9e7d139f3cf1161bc8d15683698c80488c32e1076350185fd2d5d1306023c1ef4e400c66fa76d4d2304dc40d996f98328fea03670b3ffe3c934ed15eafd5e5b9381cc721c7f8ac944badfca84113b7ee68e33175c848d98574f32646efda99b5be4343e5f97ef1b2f2b740156833e39cbaee7bd9898d66fc2e76e04e3b2a9edb2ebea4b2e9d02204d1638f337f43026825301dea025a9bf6938128e79e5ac83e19456b5c2017a2a3df1917c886c4904753d4037caecfbd4bc8449a87e61cca560fe882ef9adf179387ed97a17ae3c73a26d237499a13f2ce1351d081b304bb7c545ea7f3829f7778a587f4c8a0699dc9c143216", 0x1000}, {&(0x7f0000014000)="33e82c6bd04d2c28e2fcd8a3489d4398e03bea727576823e26cbbfc8eb94a53c2b7cce25f5d53c363e726f95891e6330cc7185cde22677b4b9d9a05da283e2b9347400333501f4b7b8f06a61eddd8be40ddde5cfdae647c40a59aea7", 0x5c}], 0x2, 0x0, 0x0, 0x0}], 0x1, 0x4)
getsockopt$inet6_IPV6_IPSEC_POLICY(0xffffffffffffffff, 0x29, 0x22, &(0x7f0000006000)={{{@in=@empty=0x0, @in=@empty=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r4=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0}, 0x0, @in=@loopback=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000017000-0x4)=0xe8)
setuid(r4)
socketpair$inet6(0xa, 0x0, 0x9, &(0x7f0000006000)={0x0, 0x0})
r5 = openat$selinux_policy(0xffffffffffffff9c, &(0x7f0000011000-0x10)="2f73656c696e75782f706f6c69637900", 0x0, 0x0)
ioctl$sock_netrom_SIOCGSTAMPNS(r5, 0x8907, &(0x7f000000c000+0x49c)=0x0)
getitimer(0x1, &(0x7f000000b000-0x20)={{0x0, 0x0}, {0x0, 0x0}})
ioctl$UFFDIO_REGISTER(r0, 0xc020aa00, &(0x7f0000004000-0x20)={{&(0x7f0000012000/0x1000)=nil, 0x1000}, 0x3, 0x0})
mlock(&(0x7f0000012000/0x1000)=nil, 0x1000)
r6 = openat$pfkey(0xffffffffffffff9c, &(0x7f0000012000-0x15)="2f70726f632f73656c662f6e65742f70666b657900", 0x0, 0x0)
ioctl$sock_netrom_SIOCGSTAMPNS(r6, 0x8907, &(0x7f0000003000)=0x0)
mmap(&(0x7f0000017000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$bt_BT_VOICE(r6, 0x112, 0xb, &(0x7f0000018000-0x2)=0x1000, 0x2)
ioctl$UFFDIO_ZEROPAGE(r0, 0xc020aa04, &(0x7f000000e000)={&(0x7f0000012000/0x1000)=nil, 0x1000})
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x96c, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r1 = socket$key(0xf, 0x3, 0x2)
r2 = accept4$inet(0xffffffffffffffff, &(0x7f0000dd5000)={0x0, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000d59000-0x4)=0x10, 0x10080000)
r3 = dup(r1)
epoll_wait(r3, &(0x7f0000014000-0x30)=[{0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}], 0x4, 0x89)
r4 = socket(0x3, 0x8080f, 0x6)
getsockopt$inet_sctp_SCTP_GET_LOCAL_ADDRS(r2, 0x84, 0x6d, &(0x7f000016b000)={<r5=>0x0, 0xd8, "cb657f3a5f54bb3471497cd268521788ed316400455e8ca6720643773a86c244ca32e15c1d169ee7f0c019d287f5f7c690c486ea9e34b49816acc6c3468a69307410d70c1aae3bae49b5d8818b0a75d47d47610fb8a6de66e7b9dcef0c537f94d6b7292d2ce3b507fce4bf22f384ef65a83495c58bbd6a1b0f6ca9e771e74d63c118838e375d4c2e7d131eedcdd42b95d73e97ed9c666966900acd5f105e0988a97f13f4d43382a540fcea7eb54c86a6c44b3a2b5fe54e6baa051062d638c7b462847e73f4d257c9df4612e1c02eb4628bc7f1d930ece767"}, &(0x7f000020c000)=0xe0)
getsockopt$inet_sctp6_SCTP_LOCAL_AUTH_CHUNKS(r4, 0x84, 0x1b, &(0x7f0000c37000)={r5, 0xbf, "8ecc6239722bfb2a6c0b7fe93d759ea3f7fd896a344dcd0b331b913886fea93ef6953f52b3afb3b756b8658c50d5df0a09aeb174bc8d00d3cb6afaf27d67aeac6cd13aa9d2e42d7a505c8d47051e72e82dce7d864d3a623277459e3a836d1393b70b5d8fd34f64cae4c430d28f8bab08998a921c9ce8f4a2b3e782932f7adaa2cd4e4d112ea0299760bca4c2e9116af4435cad067e2a6cb2d1942072aba28ef689cb75788b38d70e0f70b4de4d614a2dedfcffc151382344ce850c1de854e3"}, &(0x7f0000cbb000)=0xc7)
setsockopt$inet_dccp_int(r2, 0x21, 0x0, &(0x7f0000669000)=0x5, 0x4)
sendmsg$key(r1, &(0x7f0000f56000)={0x0, 0x0, &(0x7f00008ff000-0x10)={&(0x7f00009d6000)={0x2, 0x10, 0x800000, 0x7, 0x24, 0x0, 0x0, 0x2, [@sadb_x_sa2={0x2, 0x13, 0x8, 0x0, 0x0, 0x40, 0x2}, @sadb_x_kmaddress={0x5, 0x19, 0x0, @in={0x2, 0x2, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x3, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, @sadb_x_sec_ctx={0x19, 0x18, 0x10000, 0xdfa2, 0xbd, "53b39843737db1b33bbf19c4a01a92e953962ff07b5447d0b3ed827f8f852a9bedaca381262bab9163d08622ccd23a5e3dac81859c55a2d676a47eeb19baedb7745f9e04cbd0f0a137b888a77e52f3ec088f89089be066b4a5d55d11ed67f2592fbf987dee49643246481c9ba3140755eeb478484391088f6e3dd43aa373daffbe79f055eac88c1063013abc9d799f5298dd662b062ac6a72f148b248182cfb60764a5a461756d7fcf292d8745bbae6a0e541435e84e87313d48323a5c"}, @sadb_spirange={0x2, 0x10, 0x0, 0x80, 0x0}]}, 0x120}, 0x1, 0x0, 0x0, 0x0}, 0x0)
io_setup(0x3, &(0x7f0000566000)=<r6=>0x0)
r7 = openat$selinux_access(0xffffffffffffff9c, &(0x7f00002ca000+0xf5d)="2f73656c696e75782f61636365737300", 0x2, 0x0)
setsockopt$inet6_udp_encap(r7, 0x11, 0x64, &(0x7f00006d6000)=0x5, 0x4)
io_submit(r6, 0x1, &(0x7f0000afb000-0x8)=[&(0x7f0000f5a000)={0x0, 0x0, 0x0, 0xf, 0x8, r0, &(0x7f000016a000)="ce4f07eb0275fa4a307802c8d3dcbeea5f6da483d85247b6aad5b0604fb81d9e91e197dfb3007b6cf300040bf6dc79fdc92be37b331adad7155072ee301a80b7d9b9ed14143829652856c8e001e3227b6a1467429b75139028f302089b1dd780a8420c2e", 0x64, 0x8, 0x0, 0x1, r7}])
2017/12/15 11:53:26 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$sg(&(0x7f0000d0e000)="2f6465762f73672300", 0x0, 0x85)
syz_kvm_setup_cpu$x86(0xffffffffffffffff, 0xffffffffffffffff, &(0x7f0000595000/0x18000)=nil, &(0x7f00000e0000)=[@text16={0x10, &(0x7f0000506000)="baf80c66b81105a48a66efbafc0cecbaf80c66b87241568c66efbafc0ced0f380abf290066b80500000066b9000000000f01d932320f20e06635010000000f22e00f07f2ab0fb69e0018f3ab", 0x4c}], 0x1, 0x0, &(0x7f0000b59000)=[], 0x0)
ioctl$sock_bt(r0, 0xdd1f, &(0x7f00006e0000-0x9c)="fc3f6a88e2885f8aafd3646a9871d3bfdad81c2e1cb025f70cb66c1f09a5502e76b458dc34328414c8517267085ab6fd776feb3ada8dc9361a6f83d1f21f5c0f8c98e7a09875ab462783334cb855b969e66fb31cd7d8585199f1febe55931363eddd88965ef2f2d1b030e8899110dd85b02e2e37e4a53bbb88f87fa16d224d2d0b0c8c357b11a0f63835de060502067f27f6feac539a5c650fad4848")
getsockopt$inet_dccp_int(r0, 0x21, 0x11, &(0x7f00007f5000-0x4)=0x0, &(0x7f00003a4000)=0x4)
ioctl$KVM_SET_LAPIC(0xffffffffffffffff, 0x4400ae8f, &(0x7f0000001000-0x400)={"daab9192927a652ad29ba2a079776a0f7183bc3f8bc51c80c2a6ccbfd055538e9f4e913b69de641eb118488a5a950f699540b1d9e91443ad26d190ee6645150e8455ead15163d0ebb2f1ab5af6a0a2cab6dd67bbb8f3eafac2fd3808bf2c04dbed9cbe625260cedfb26e2bc86be8a8ed0b9d6e82a706d2b3cd8ade1bba248fe108050395496d0d4f85a3ed31929260e5e1999fe5d41b6927e83779b7c773a6245bcf9204d3e22db4bfe0398b11359f31b94d654ecfb7c0540b4f713a2b070da35b01ae3dce86b87000214ace36585fc10dc23d40dcee3ad558ec018f85c431467d7191327154ab8c4631b652846868886196102a1b9f74c43612e80fa02137f6a7a3dda4638a40cc2cf6ecce37731174745223d1d2d44aac53cb8afa377ebd37401fd80d26d6d248a7e37a56d882b0583d9810920687e4c03e4c3603cf8fc20aff84174db937079b306f6a73e251c3124def2bf47645202d8c2dfa505450b5d69fc4fb23dc474c926829b72eed949510486344e7210eb82d07c9245597886756ff727b2a1189dbc9b225ceb73762c5e245dc30ecb7bf6d9a2ba7f8cf3a4cbe305d4fb4922d64b71e58e9886ef10b4c5a2c20ceb8fc08eb4f80389cf520b1106a1e239a0f588e60ab1a39cd4015e3ec1c3f8e561413178e2c1ed72a633dd44a7ef9e121793799872b0e49595c3b14e8cd65cab14f9b8337e1b1f722d676e75499abfef2b995d2f5b238866f78b9ec75c2dec1b9a6a7609422ed2de7eba7506be10e3a4905757eb78c08f4fe239a6181371d0e6b8e60f32ffde4c00661659dd5ffc3681c8f56166d49f4f7b3b7c16e1e56062113a7705e0f828484ba69298a9e9dbede82bd6edb70f3c92fce73c7be60265a5b0387e9f8c80e3834e988844122345fda9fadc5852c6a4550547feaa6f1fd97b14b653f5437019b421334fd4c704a3730ae824f87ab208cd602ee6fdc17740dc40a6d86175e791c90f1479af5e739f6ea832019cae79ebeab0008ddc99f1c078da541152b412e35f9548864a5c4f52243239f81206714d00b08bcf69db92c1798c6f595a0c17063870020d0e238439cf7cf8431c937f7c2ea83340b16180de6114dc17156260002a9c09b80c790d1c38cff882c5fd0944437fc1d43071278a34b7b25f4b05410790a8383e8cca8fea8af41dde20c7f762e9a138bc9cd263795d492382fcbdba35bdd0653d9f964c6fae4c57731b12b3c797053f1dc3afe13f0e1af5592b888c4bf542a05f184f5a14532682a5ebc4170f2b28ac10b349960cd6f6ca534aa466ab67b53230eadb1f081aeff049d46f0677106b5f685c05fbd3a622424c870b5374d8726563f24b3b63909e8e7b5d2a9c7a3d3bfdfdc2f062f9c3ad2a42fd2f7ef67e2019790441f9e8e83b7b6cbf1f5f45303b18cea2a870ad1532fdb5fefbb92bcc8db4209b4cd17"})
syz_open_dev$usbmon(&(0x7f0000845000-0xd)="2f6465762f7573626d6f6e2300", 0x0, 0x0)
r1 = add_key(&(0x7f0000646000-0x6)="6269675f0679", &(0x7f0000337000-0x5)={0x73, 0x79, 0x7a, 0x1, 0x0}, &(0x7f0000de3000)="4be3609e8280c70082d388edb77ae7358518cbf1636d8d92c46b", 0x1a, 0xfffffffffffffff8)
r2 = request_key(&(0x7f00006ab000)="6c6f676f6e00", &(0x7f0000220000)={0x73, 0x79, 0x7a, 0x2, 0x0}, &(0x7f0000f8a000-0xd)="6269675f0679", 0xfffffffffffffffa)
r3 = request_key(&(0x7f0000c15000-0xc)="635b667364692e6d617000c1", &(0x7f000002e000-0x5)={0x73, 0x79, 0x7a, 0x1, 0x0}, &(0x7f0000833000)="706f7369785f61636c5f61636365737300", r2)
keyctl$dh_compute(0x17, &(0x7f0000827000)={r1, r2, r3}, &(0x7f0000ddf000-0x11)="0000000000000000000000000000000000", 0x11, 0x0)
unshare(0x2c000200)
ioctl$KVM_PPC_GET_SMMU_INFO(r0, 0x8250aea6, &(0x7f0000eb7000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
r4 = memfd_create(&(0x7f00007a2000-0x3)="fb008d", 0x2)
ioctl$KVM_SET_TSC_KHZ(r4, 0xaea2, 0x4100004)
setsockopt$inet_buf(r4, 0x0, 0x2f, &(0x7f00006ac000-0x77)="24666ffca0685b84962cf0db6a62cdc2026fffba530fd279b5fbcab71885ace4669b02e31e25e73e0d13284b8af8f3547b4559583d26f2c33bb94eb809db530d3fb18dce2927b41075b0bd1763161c9b8d3f745fe75befa799a55763276a005471a2aba468c6ba2d85fee65e2cc569306cea4c7e09589a", 0x77)
write(r4, &(0x7f00001fb000)="75", 0x1)
sendfile(r4, r4, &(0x7f0000001000)=0x0, 0x2)
execveat(r4, &(0x7f0000006000)="2e2f66696c653000", &(0x7f0000006000-0x28)=[&(0x7f00005a5000)="74e6745c745064626465766d643573756d776c616e3076726e657430707070307300", &(0x7f0000006000)="2400", &(0x7f0000004000)="6b657972696e676b657972696e67766d6e65743173656c662a296574683000"], &(0x7f0000006000)=[&(0x7f0000001000)="2d406370757365745b6d643573756d5b00", &(0x7f0000005000)="2400", &(0x7f0000007000-0x6)="626465765e00", &(0x7f0000003000-0x2)="2400"], 0x1000)
ioctl$sock_FIOGETOWN(r0, 0x8903, &(0x7f000031b000-0x4)=0x0)
timer_create(0x0, &(0x7f00006ba000)={0x0, 0x41, 0x1, @thr={&(0x7f0000e12000-0xab)="e0db076b9f4ddbc6440c6325a85d980e384c88a0873e762728eb687d222b1e056a5af9dddb2be571c183177e8023e3d75830a7295d4e7b0a56faa836a62f1ebb6ece3f76ef7c4aa44959a01096ff7353000776cafc078acaea9f45d30f96fafd792fa54132fd0759befdd7472070c80fe4383c4f4a3811340ef490fcebe18e144b2563c391b522e1627f27d42883372b38841c032d181704d149e7cd914d04b7673b65596d1080e136c252", &(0x7f0000483000-0x5e)="055d564ef3f0aa9b05b9cdcb57cef957dc42c3892798820a3bfeb04dbd6c27e0f62f8cb795d051d18b40e348286c39d2c6531e7e509e6ae2b2bb4909826d4375cf8938b00e9b322642ae41caba518ee3b5ac820d55466b1d25645580ac2b"}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f000046f000-0x4)=<r5=>0x0)
timer_delete(r5)
preadv(r0, &(0x7f0000052000)=[], 0x0, 0x0)
r6 = dup3(r4, r4, 0x80000)
r7 = syz_open_dev$sg(&(0x7f0000572000-0x9)="2f6465762f73672300", 0x0, 0x0)
close(r7)
ioctl$TIOCMSET(r6, 0x5418, &(0x7f000005a000-0x4)=0x5)
ioctl$KDDELIO(0xffffffffffffffff, 0x4b35, 0x4)
r8 = openat$qat_adf_ctl(0xffffffffffffff9c, &(0x7f0000ced000)="2f6465762f7161745f6164665f63746c00", 0x20400, 0x0)
getsockopt$inet_IP_XFRM_POLICY(r6, 0x0, 0x11, &(0x7f0000b80000)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in=@loopback=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r9=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@local={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f000023c000)=0xe8)
recvfrom$packet(r8, &(0x7f0000e16000)="0000", 0x2, 0x2040, &(0x7f0000c6c000)={0x11, 0x9, r9, 0x1, 0x400000000000007, 0x6, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, 0x14)
2017/12/15 11:53:26 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$OBJ_GET_PROG(0x7, &(0x7f0000001000-0x10)={&(0x7f0000029000-0x8)="2e2f66696c653000", 0x0}, 0xc)
r0 = socket(0x10, 0x2, 0x0)
write(r0, &(0x7f000081c000-0x25)="2600001300470020000083140022e3041000ff010000000100000100000001067f10000480", 0x25)
r1 = socket(0x2, 0x1, 0x0)
getsockopt$inet_sctp_SCTP_AUTO_ASCONF(r0, 0x84, 0x1e, &(0x7f0000d5a000-0x4)=0x0, &(0x7f00003b0000)=0x4)
listen(r1, 0x0)
r2 = epoll_create1(0x0)
syz_open_dev$usbmon(&(0x7f0000044000)="2f6465762f7573626d6f6e2300", 0x6, 0x4c2)
setsockopt$netrom_NETROM_N2(r0, 0x103, 0x3, &(0x7f000040c000-0x4)=0x1fffe020000, 0x4)
getsockname$netrom(r1, &(0x7f00009ec000)=@full={{0x0, {"00000000000000"}, 0x0}, [{"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}]}, &(0x7f000012d000)=0x48)
r3 = accept(r1, &(0x7f0000dd9000-0x10)=@ethernet={0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000f98000)=0x10)
ioctl$DRM_IOCTL_PRIME_HANDLE_TO_FD(0xffffffffffffffff, 0xc00c642d, &(0x7f0000010000)={0x0, 0x80000, <r4=>0xffffffffffffff9c})
ioctl$DRM_IOCTL_FREE_BUFS(r4, 0x4010641a, &(0x7f0000f4a000)={0x1, &(0x7f0000f7e000-0x4)=[0xff8c]})
ioctl$DRM_IOCTL_FREE_BUFS(r4, 0x4010641a, &(0x7f0000017000-0x10)={0x0, &(0x7f0000016000)=[]})
setsockopt$inet6_dccp_int(r1, 0x21, 0x4, &(0x7f0000da6000)=0x1, 0x4)
sendmsg(r1, &(0x7f0000a5a000-0x38)={&(0x7f0000000000)=@sco={0x1f, {0x36, 0x6, 0x5, 0x9, 0x8, 0x9}}, 0x8, &(0x7f0000496000)=[{&(0x7f0000014000-0x59)="7dc541445378653b2cccb5f04146e312a71a63e74d6a2382aaf30ad49656cda4c4fc49415d19202db568e4fda07c7260ca595b3d893263978f0d559be9abb43c0677701114ad325c8c48ba60b62da4ef940e6073f698661e0f", 0x59}, {&(0x7f000000b000-0x3f)="af998a8cee14274f766ae1dffa7e56b43be7230d013a0ff41cc9bf592f868492d583fa022b4c4053ab9a3d859caa476a16e50c05b6a9238400a6c83f7c274b", 0x3f}], 0x2, &(0x7f0000009000)=[], 0x0, 0x10}, 0x20000080)
setsockopt$inet6_MRT6_ADD_MFC(r3, 0x29, 0xcc, &(0x7f000000b000-0x5c)={{0xa, 0x3, 0x200, @loopback={0x0, 0x1}, 0x9}, {0xa, 0x3, 0x5770, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x1}, 0x7, [0x7781, 0x3, 0x8, 0x0, 0x5, 0x5, 0xe97, 0x6]}, 0x5c)
getsockopt$inet_sctp6_SCTP_DEFAULT_SNDINFO(r1, 0x84, 0x22, &(0x7f00000bf000)={0xfffffffffffffff7, 0x8, 0x3, 0x3f, 0x0}, &(0x7f0000543000-0x4)=0x10)
socketpair$inet6_dccp(0xa, 0x6, 0x0, &(0x7f000068f000)={0x0, 0x0})
getsockopt$llc_int(r0, 0x10c, 0x1, &(0x7f0000415000-0x4)=0x0, &(0x7f000049f000-0x4)=0x4)
epoll_ctl$EPOLL_CTL_ADD(r2, 0x1, r1, &(0x7f000044d000)={0x10000000, 0x0})
epoll_wait(r2, &(0x7f000062b000)=[{0x0, 0x0}], 0x1, 0xfffffffffffffff7)
setsockopt$sock_int(r1, 0x1, 0x7, &(0x7f0000008000-0x4)=0x0, 0x4)
ioctl$DRM_IOCTL_MAP_BUFS(r4, 0xc0186419, &(0x7f00001d2000)={0x5, &(0x7f0000f71000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000533000)=[{0x2, 0xf8, 0x2, &(0x7f000036b000-0xf8)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, {0x1, 0x1f, 0x5, &(0x7f000005b000-0x1f)="00000000000000000000000000000000000000000000000000000000000000"}, {0x2, 0x93, 0x3, &(0x7f000045e000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, {0x4, 0xe1, 0x4, &(0x7f00009f8000-0xe1)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, {0xffffffffffff9a97, 0x1000, 0x4, &(0x7f0000bec000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}]})
shutdown(r1, 0x0)
2017/12/15 11:53:26 executing program 0:
mmap(&(0x7f0000000000/0x270000)=nil, 0x270000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x800000000000000, 0x0, 0x1, 0xf72, 0x0, 0x0, 0x0, 0x0, 0x7f, 0x0, 0x8, 0x0, 0x0, 0x0, 0x80000000, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
memfd_create(&(0x7f0000047000-0x6)="2747504c3a00", 0x0)
pipe(&(0x7f0000646000)={<r0=>0xffffffffffffffff, <r1=>0xffffffffffffffff})
r2 = syz_open_dev$urandom(&(0x7f0000fa6000)="2f6465762f7572616e646f6d00", 0x0, 0x80080000)
splice(r2, 0x0, r1, 0x0, 0x100000000, 0x0)
sync_file_range(r0, 0x20, 0x0, 0x4)
syz_emit_ethernet(0x6e, &(0x7f0000519000)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [], {{0x0, @ipv6={0x0, 0x6, "a228af", 0x38, 0x0, 0x1, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, {[@dstopts={0xaf, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0], []}, @routing={0x0, 0x4, 0x0, 0x0, 0xbbb, [@remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}]}], @udp={0x0, 0x1, 0x8, 0x0, ""}}}}}}, 0x0)
sched_setaffinity(0x0, 0x8, &(0x7f0000bd4000)=0x75)
perf_event_open(&(0x7f000002f000-0x78)={0x2, 0x78, 0x43, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x100, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f0000632000)="2e2f66696c653000", 0x0)
mount(&(0x7f000000a000)="2e2f66696c653000", &(0x7f0000015000-0x8)="2e2f66696c653000", &(0x7f0000014000)="70726f6300", 0x2000021, &(0x7f0000fc9000)="")
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x10004, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = openat$kvm(0xffffffffffffff9c, &(0x7f0000df3000-0x9)="2f6465762f6b766d00", 0x8000, 0x0)
r4 = ioctl$KVM_CREATE_VM(r3, 0xae01, 0x0)
r5 = ioctl$KVM_CREATE_VCPU(r4, 0xae41, 0x2)
ioctl$KVM_SMI(r5, 0xaeb7)
mmap(&(0x7f0000000000/0xda6000)=nil, 0xda6000, 0x0, 0x64032, 0xffffffffffffffff, 0x0)
ioctl$KVM_SET_IDENTITY_MAP_ADDR(r4, 0x4008ae48, &(0x7f0000ea4000)=0x15ffd)
ioctl$KVM_TPR_ACCESS_REPORTING(r5, 0xc028ae92, &(0x7f00007c2000)={0x0, 0x6, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_GET_CLOCK(r4, 0x8030ae7c, &(0x7f000022c000)={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_SET_CLOCK(r4, 0x4030ae7b, &(0x7f00006f1000-0x30)={0x100000000000003, 0xa, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f000092d000/0x400000)=nil, 0x400000, 0x7fffffff, 0x2000000008972, 0xffffffffffffffff, 0x0)
clone(0x0, &(0x7f0000b08000)="", &(0x7f0000001000-0x4)=0x0, &(0x7f0000001000-0x4)=0x0, &(0x7f0000a53000-0xd5)="")
openat$cuse(0xffffffffffffff9c, &(0x7f0000b85000)="2f6465762f6375736500", 0x10000, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x35, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfa1000)=nil, 0xfa1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = inotify_init1(0x80800)
mmap(&(0x7f0000fa1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$hwrng(0xffffffffffffff9c, &(0x7f00001fc000)="2f6465762f6877726e6700", 0x1, 0x0)
mmap(&(0x7f0000fa1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f0000fa3000-0xc)={<r2=>0x0, 0x0, 0x0}, &(0x7f00001be000-0x4)=0xc)
fcntl$setown(r0, 0x8, r2)
syz_open_dev$vcsa(&(0x7f0000f06000)="2f6465762f766373612300", 0x40000000000077, 0x180)
mmap(&(0x7f0000fa3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fcntl$getownex(r0, 0x10, &(0x7f0000fa4000-0x8)={0x0, <r3=>0x0})
ptrace$setopts(0x4206, r3, 0x0, 0x0)
ptrace(0x4207, r3)
mmap(&(0x7f0000fa2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa2000/0x1000)=nil, 0x1000, 0x8, 0x50, 0xffffffffffffffff, 0xffffffffffffffff)
mmap(&(0x7f0000917000/0x1000)=nil, 0x1000, 0x8, 0x20010, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa4000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa4000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = socket$inet6_sctp(0xa, 0x200010000000a, 0x84)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet6_tcp(0xa, 0x1, 0x0, &(0x7f0000935000-0x8)={<r1=>0x0, 0x0})
mmap(&(0x7f0000000000/0xfa0000)=nil, 0xfa0000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
accept(r0, &(0x7f0000ed2000)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f000062b000-0x4)=0x10)
mmap(&(0x7f0000fa0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fa0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
accept(r1, &(0x7f0000762000)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f0000fa0000)=0x10)
r2 = accept4$inet(0xffffffffffffffff, &(0x7f0000c21000-0x10)={0x0, 0x0, @broadcast=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000dff000-0x4)=0x10, 0x807ff)
bind$inet(r2, &(0x7f0000905000-0x10)={0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
r3 = bpf$PROG_LOAD(0x5, &(0x7f0000f9c000)={0x1, 0x3, &(0x7f0000ad5000)=[@generic={0x2015b4, 0x0, 0x0, 0x0}, @generic={0xec3, 0x40000000000001, 0x40, 0x0}, @generic={0xd39d, 0x0, 0x3, 0xfffffffffffffffe}], &(0x7f0000bba000-0x7)="8b797374f7006d", 0xffffffff, 0x80, &(0x7f0000da8000-0x80)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1, 0x0}, 0x30)
socketpair(0x11, 0x80800, 0xfff, &(0x7f0000192000-0x8)={<r4=>0x0, 0x0})
epoll_ctl$EPOLL_CTL_DEL(r4, 0x2, r3)
r5 = socket$inet6(0xa, 0x1, 0x20000000000)
setsockopt$inet6_int(r5, 0x29, 0x8, &(0x7f000054a000)=0xa, 0x4)
getsockname$ipx(r4, &(0x7f0000b13000-0x10)={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, &(0x7f000050b000)=0x10)
setsockopt$sock_int(r5, 0x1, 0x4000000000000002, &(0x7f0000d11000)=0x3fb, 0x4)
bind$inet6(r5, &(0x7f0000bcf000-0x1c)={0xa, 0x0, 0xfffffffffffffffd, @loopback={0x0, 0x1}, 0xc}, 0x1c)
setsockopt$inet6_mtu(r0, 0x29, 0x17, &(0x7f00004e3000-0x4)=0x2, 0x4)
sendto$inet6(r5, &(0x7f0000554000)="", 0x0, 0xfffffefffffffffe, &(0x7f0000f63000-0x1c)={0xa, 0x0, 0x8, @loopback={0x0, 0x1}, 0x0}, 0x1c)
getsockopt$inet6_tcp_buf(r5, 0x6, 0x18, &(0x7f00006e3000-0xa2)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000135000-0x4)=0xa2)
setsockopt(r5, 0x3, 0x5, &(0x7f00007a5000)="fd0300000000000000006c4b0e544c0a28f7c13b7218a58832362bfb59092e9209a3f3a5ea2c3eba4743c2b100f6587a34887f83f48840c70cd3ddb384eb4501010000d12ca2a55b5b6a7b6b11a435", 0x4f)
geteuid()
mmap(&(0x7f0000fa1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
llistxattr(&(0x7f0000747000-0x8)="2e2f66696c653000", &(0x7f00008a2000-0x4f)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x4f)
getsockopt$inet6_buf(r5, 0x29, 0x6, &(0x7f0000fa2000-0x2)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000fa2000-0x4)=0x48)
setsockopt$inet6_tcp_TCP_MD5SIG(r1, 0x6, 0xe, &(0x7f0000f64000)={{{{0x2, 0x2, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0xa, 0x3, 0x8, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x19e}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x80000000000002, 0x6, 0x4, "7f56b22a2237ff2392e04121b7d9ec8a85d84f9a5f2d63b223796e1327f1ef0154558d0317016c820c10e7d8ee5cf31170f5ce05edb807975b0c30270323ec391a87de9a6f0395cbdf748e05655572b9"}, 0x160)
2017/12/15 11:53:26 executing program 1:
r0 = dup3(0xffffffffffffffff, 0xffffffffffffffff, 0x80000)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TIOCLINUX3(r0, 0x541c, &(0x7f0000000000)=0x3)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TIOCGSID(0xffffffffffffff9c, 0x540f, &(0x7f0000c8b000)=<r1=>0x0)
mmap(&(0x7f0000000000/0xaf6000)=nil, 0xaf6000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$kvm(0xffffffffffffff9c, &(0x7f0000a06000)="2f6465762f6b766d00", 0x0, 0x0)
r3 = ioctl$KVM_CREATE_VM(r2, 0xae01, 0x0)
r4 = ioctl$KVM_CREATE_VCPU(r3, 0xae41, 0x0)
syz_kvm_setup_cpu$x86(r3, r4, &(0x7f00002ea000/0x18000)=nil, &(0x7f0000af2000-0x18)=[@text64={0x40, &(0x7f0000000000)="e0c422fd23a00000000000010000000f6ad9b805000000b91b9600000f01d94f0f0090000000000f060f01f035004000003422954f30b805000000650f001f3e660f3881ab00600000b805000000b9006000000f01d93e664d0f3880bb00000000", 0x61}], 0x1, 0x58, &(0x7f00003c3000)=[], 0x0)
ioctl$KVM_RUN(r4, 0xae80, 0x0)
ioctl$KVM_SET_SREGS(r4, 0x4138ae84, &(0x7f00005b2000)={{0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0xfffffffffffffffc, 0xffffffffffffffff, 0x10000, 0x0, 0x40000, 0x0, 0x1000000000000000, 0x0, 0x0, 0x0}, {0xd002, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x4, 0x3c, 0x0, 0x0, 0x0, 0x3, 0x0, 0x4000000000000, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x4, 0x0, 0x1, 0xd0e4, 0x0, 0x0, 0x0, 0x9, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0}, {0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x3003, [0x0, 0x0, 0x0]}, 0x20000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
ioctl$KVM_RUN(r4, 0xae80, 0x0)
r5 = syz_open_procfs(r1, &(0x7f00003cd000-0x8)="6e732f75747300")
getsockopt$inet_sctp_SCTP_INITMSG(r5, 0x84, 0x2, &(0x7f00002df000)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000307000)=0x8)
perf_event_open(&(0x7f0000549000-0x78)={0x2, 0x78, 0x3e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000, 0x0, 0xf74, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0}, r1, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
unshare(0x8000000)
r6 = open(&(0x7f0000107000-0x8)="2e2f66696c653000", 0x20000, 0x148)
ioctl$KVM_SET_LAPIC(r5, 0x4400ae8f, &(0x7f0000084000)={"4c6b6bb3902c066d03de26db900bc653a080b38a268861d9414a4d7a9dc12a3e646cd2f2579735ab15da0e18bafd8abdcc3a5e6ee2e401da858eca77bef5da823207703a17fb4f91878584bfbbfa4a6e14819e83bec6af962432c1cc74f4ce02b2c0991765086dbc20011dd41000322c0b2426a858e1b3b893e15913f3fd7f1c3660d0b46c24e63fc5998bf75e1688275bb0c96ad01e12efdd14eb0000000000000408b206b82776099bfd34be6011c2e00e7ab80d466e00e62996edf1c73b0709c53ad377cdf87fadcc4b662841df157b5ce54b300921e1253b5f56db5a1e8e7fa71f15ea8166d4d6a1710cc14af2866de740411d947c47bab031763799dc5b98a40a2399f221f7d9a51264573d7bc7cd91fc683a4cf4a578e07e4a27c0860835e98b2844c1570f1199db191005188bdf0a417d6744236a7291c4de730fb37f4c7e4eea7a31cf50d49695b63a20e5a2a596ce16741264607f3a87e9fc835a5bd4c211349b02cbd19fd9be695fe6d7d87aa1ae1d8cc41508463dfade51649799b86343d6a95c990bd79fb7047a10682c0db43fbbfe5bb39c22597148223f999ac8a61a25c69c7f793ffec9f50a730ddee67416fea31671444df7da6dded80c61cf301180e0cece82937fa7491f0694b268bcdb32d6bdc8e59abbfd8943efb75bae061b9961056219f5c0f0dc4f24b55d2d9b23272e6feb99e708e6e4bb75ef8a6a05550509000000386bbf4f9e40cffc72447afe109db3dbe90c48e6ad94ccd548d8a973673eb61610021661dc9011d4ca9312c041bbec3b94f3ef7f736dd70df8106c86325e4da368f53467995085a62225c6660f7ae5358508d04d19ddbd310e10495f427a80683ea51517f4c20000000000000100dc0c1cec545c2b89243b444c9305b4c26f2ae25555b5dcdc2263d417d226baab361e9aa21776f954939a347eef56164dec3a22a7192c426cadae1b6729d8eb7633a3ac01ca3dead876c09e7f8c7b0710d292466bccea6e11051818f6d96a6294876164ed929a469f23ca1239704857bcfd8d7e26b35b9fcc17120b7870ecb773f4402ee1e52451f3bb7a25ad4e2ae056e6f535e53da444cc38cf98efbe624c9b4fa0d0cf59b117fc48d9c2ac18f1cc081c60a8347270278daa47312e23d97c8820db526f59f2bbfa1f917be9a9fd42a88fc2dd05ffb0ca65f444f53852891bafa60853996c6c0176ab1e4b0000000000000400986c278b95a48ac30a7883ac3720f849bdf03cd87acb0ce468af91f9140deea6f80665624415044685cafa4ad82ce2bba733c8c4905c6ee122024d588afc0bb42f585197dff73831039463697bae6c74a99015b09dc882712d9cc5dbb748d27d6b6b2923c1b1f0614c9d18401c1918d041491d4f05aabe7bcacc83c6fba05f011bf10cabaecb307f52f46fa30a581fe7f06ed59a3967e0"})
ioctl$EVIOCGMASK(r6, 0x80104592, &(0x7f0000a32000-0x10)={0x15, 0xb7, &(0x7f0000ad0000-0xb7)="9025eda6a20d259784d112ed72cfacd5d87ab024b83f3207b517301642b1f3b7dba9d780485dec96cda8d3aeffa8a00cf89437eaf959c9e12a82bddd7aad89efd9f9d9d6b2f48f45ef6cfdde61c8b3ea318fc5cf46888e360ffad94a224c30b489fb6190dee72c0693738395b0e524792e7fab3e14d7ba398b8b57490e49f055611f28fd9abb6ef1cb86457d52c25cc805784170f0781ba2bcde1a93812d0b0cff3da03d7913d36ce4a1162a66ace5b803e0eb3c6b2af6"})
r7 = socket$unix(0x1, 0x1, 0x0)
getsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX3(r5, 0x84, 0x6f, &(0x7f0000d7b000-0x10)={<r8=>0x0, 0x94, &(0x7f000086f000-0x94)=[@in={0x2, 0x3, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x0, 0x8, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0xfffffffffffffffc}, @in={0x2, 0x1, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x10000, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x81}, @in6={0xa, 0x1, 0x200, @loopback={0x0, 0x1}, 0x2}]}, &(0x7f0000bbc000-0x4)=0x10)
openat$selinux_avc_cache_stats(0xffffffffffffff9c, &(0x7f000020b000)="2f73656c696e75782f6176632f63616368655f737461747300", 0x0, 0x0)
getsockopt$inet_sctp6_SCTP_PEER_ADDR_THLDS(r5, 0x84, 0x1f, &(0x7f00007c5000)={r8, @in6={{0xa, 0x0, 0x1, @loopback={0x0, 0x1}, 0x800}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7, 0xfffffffffffff801}, &(0x7f0000e9f000-0x4)=0x98)
socketpair$unix(0x1, 0x5, 0x0, &(0x7f000000b000-0x8)={<r9=>0xffffffffffffffff, 0xffffffffffffffff})
shmget$private(0x0, 0x1000, 0x7c0000a2, &(0x7f0000831000/0x1000)=nil)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x0, 0x0, 0x4000000000, 0x0, 0x0, 0xf72, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r7, 0x1, 0x11, &(0x7f00003df000)={0x0, 0x0, 0x0}, &(0x7f0000ca8000-0x4)=0xc)
getsockopt$inet_sctp6_SCTP_DISABLE_FRAGMENTS(r6, 0x84, 0x8, &(0x7f00004d5000)=0x0, &(0x7f00009bf000-0x4)=0x4)
getsockopt$sock_cred(r9, 0x1, 0x11, &(0x7f0000d81000-0xc)={0x0, 0x0, 0x0}, &(0x7f0000ae2000)=0xc)
2017/12/15 11:53:26 executing program 2:
mmap(&(0x7f0000008000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$urandom(&(0x7f0000009000-0xd)="2f6465762f7572616e646f6d00", 0x0, 0x5)
r1 = socket$inet_tcp(0x2, 0x1, 0x0)
r2 = openat$vcs(0xffffffffffffff9c, &(0x7f0000008000)="2f6465762f76637300", 0x800, 0x0)
perf_event_open(&(0x7f0000b8d000-0x78)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, r2, 0x0)
setsockopt$inet_mtu(r1, 0x0, 0xa, &(0x7f0000a72000-0x4)=0x7, 0x4)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x812, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
sendto$inet(r1, &(0x7f0000008000)="", 0x0, 0x20000000, &(0x7f0000035000)={0x2, 0x0, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
get_thread_area(&(0x7f0000e2c000)={0x0, 0x0, 0x0, 0x0, 0x200000000000000, 0x0, 0x200000000000000, 0x0, 0x0, 0x0})
r3 = accept4$inet(r1, &(0x7f000068c000)={0x0, 0x0, @multicast1=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000ec3000-0x4)=0x10, 0x800)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$inet(r3, &(0x7f0000000000)={0x2, 0x3, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f0000000000/0x8f2000)=nil, 0x8f2000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$inet_tcp_int(r3, 0x6, 0x1, &(0x7f00001c0000-0x4)=0x2, 0x4)
connect$inet(r1, &(0x7f000077e000-0x10)={0x2, 0x1, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f00008f2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f00008f2000)={<r5=>0x0, 0x0, 0x0}, &(0x7f000068c000-0x4)=0xc)
getpgid(r5)
mmap(&(0x7f00008f2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f00005e2000-0x78)={0x2, 0x78, 0xdb, 0x0, 0x2, 0x0, 0x0, 0x4, 0x0, 0xb, 0xfe, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20040, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000000a000)={0x5, 0x78, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x4, 0x0, 0x668, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20000000, 0x8, 0x0, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x26d000)=nil, 0x26d000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$LOOP_CHANGE_FD(r0, 0x4c06, r4)
r6 = perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf72, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x100, 0x0, 0x4dabeff5, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000026d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_tcp_TCP_REPAIR_OPTIONS(r6, 0x6, 0x16, &(0x7f00006c3000-0x38)=[{0x3, 0x887d}, {0x8, 0x20}, {0x8, 0x9}, {0x0, 0x80}, {0x800000000003, 0x4}, {0x4, 0x7b71}, {0xc, 0x0}], 0x7)
mmap(&(0x7f0000000000/0x6000)=nil, 0x6000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mbind(&(0x7f0000003000/0x2000)=nil, 0x2000, 0x1, &(0x7f00008aa000-0x8)=0x3, 0x8, 0x0)
r7 = openat$rfkill(0xffffffffffffff9c, &(0x7f0000c38000-0xc)="2f6465762f72666b696c6c00", 0x200000, 0x0)
ioctl$DRM_IOCTL_AGP_ACQUIRE(r7, 0x6430)
get_mempolicy(&(0x7f0000000000)=0x0, &(0x7f0000005000-0x8)=0x0, 0x10001, &(0x7f0000003000/0x2000)=nil, 0x2)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
readlink(&(0x7f0000000000)="2e2f66696c653000", &(0x7f0000398000)="000000000000000000000000000000", 0xf)
r0 = socket(0x11, 0x80000, 0x40)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_tcp_buf(r0, 0x6, 0x1e, &(0x7f0000001000)="cd3b116ef0d8bea7a61936b12e3a82acbbce660a45ffa4611f3d9fb0c3e95ae28292e4c61e438f7dd17d315bdf37c4d1e9e838f97f73707472e3c7c3ef3083ffda", 0x41)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_GET_MAP_INFO(0xf, &(0x7f0000000000)={0xffffffffffffffff, 0x18, &(0x7f0000002000)={0x0, <r1=>0x0, 0x0, 0x0, 0x0, 0x0}}, 0x10)
bpf$BPF_MAP_GET_FD_BY_ID(0xe, &(0x7f0000000000)=r1, 0x4)
timer_create(0x0, &(0x7f0000002000-0x60)={0x0, 0x17, 0x2, @tid=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000001000)=<r2=>0x0)
timer_getoverrun(r2)
r3 = openat$sequencer2(0xffffffffffffff9c, &(0x7f0000002000)="2f6465762f73657175656e6365723200", 0x400400, 0x0)
ioctl$KVM_GET_SREGS(r3, 0x8138ae83, &(0x7f0000000000)={{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, [0x0, 0x0, 0x0]}, {0x0, 0x0, [0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_RESET_STREAMS(r0, 0x84, 0x77, &(0x7f0000003000)={<r4=>0x0, 0xb3}, &(0x7f0000001000-0x4)=0x8)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp6_SCTP_CONTEXT(r0, 0x84, 0x11, &(0x7f0000003000)={r4, 0x5080000000}, 0x8)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_ENABLE_CAP(r3, 0x4068aea3, &(0x7f0000004000)={0x0, 0x0, [0x1, 0x1, 0x7f, 0x0], [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r5 = gettid()
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$int_out(r3, 0x2, &(0x7f0000005000)=0x0)
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = openat$selinux_commit_pending_bools(0xffffffffffffff9c, &(0x7f0000006000)="2f73656c696e75782f636f6d6d69745f70656e64696e675f626f6f6c7300", 0x1, 0x0)
sigaltstack(&(0x7f0000004000/0x3000)=nil, 0x0)
getsockopt$inet_sctp6_SCTP_I_WANT_MAPPED_V4_ADDR(r6, 0x84, 0xc, &(0x7f0000006000-0x4)=0x0, &(0x7f0000001000-0x4)=0x4)
r7 = fcntl$getown(r6, 0x9)
fcntl$dupfd(r6, 0x406, r3)
ioctl$TIOCMGET(r0, 0x5415, &(0x7f0000000000)=0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
rt_tgsigqueueinfo(r7, r5, 0x33, &(0x7f0000007000)={0x16, 0x81, 0xffff, 0x1})
[ 50.533930] SELinux: unrecognized netlink message: protocol=0 nlmsg_type=18176 sclass=netlink_route_socket pig=7312 comm=syz-executor3
2017/12/15 11:53:26 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket(0x11, 0x80003, 0x8)
setsockopt$packet_int(r0, 0x107, 0xf, &(0x7f0000fe8000-0x4)=0x20, 0x4)
setsockopt$inet_sctp6_SCTP_AUTH_CHUNK(r0, 0x84, 0x15, &(0x7f000012f000)={0x400}, 0x1)
read(r0, &(0x7f00007e7000-0x58)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x58)
mmap(&(0x7f0000000000/0x89f000)=nil, 0x89f000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet_udp(0x2, 0x2, 0x0, &(0x7f0000650000)={0xffffffffffffffff, <r1=>0xffffffffffffffff})
socket$inet6_sctp(0xa, 0x80002000000005, 0x84)
r2 = socket$inet(0x2, 0x3, 0x6)
setsockopt$inet_mreqn(r2, 0x0, 0x20, &(0x7f0000282000)={@empty=0x0, @multicast1=0xe0000001, 0x2}, 0xc)
setsockopt$inet_buf(r2, 0x0, 0x23, &(0x7f000089a000-0x58)="e4a445eb7fff050000000000000058639a2c9505f049bd0986c5780100000007ea95000000b50000e6ff82fd9fd0be8306a5add26c010a05b2bb00b260e7da9feb5dbc445838dfae358aa6fdd11ff1096e00000068b5feff", 0x58)
getsockopt$inet_pktinfo(r2, 0x0, 0x8, &(0x7f0000662000-0xc)={<r3=>0x0, @multicast1=0x0, @empty=0x0}, &(0x7f0000283000)=0xc)
setsockopt$inet_pktinfo(r1, 0x0, 0x8, &(0x7f0000519000)={r3, @loopback=0x7f000001, @rand_addr=0x2}, 0xc)
getpeername$inet(r2, &(0x7f0000390000)={0x0, 0x0, @broadcast=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000e3d000)=0x10)
r4 = accept$inet6(0xffffffffffffffff, &(0x7f000062b000-0x1c)={0x0, 0x0, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}, &(0x7f000089d000)=0x1c)
sendmsg(0xffffffffffffffff, &(0x7f0000c75000)={0x0, 0x0, &(0x7f00005f0000)=[{&(0x7f000089a000-0xc6)="110cc19085bd95b152e80254e4f9330afc8863e8d395613fa20977b031862cc96ae2ae0cef644ef4d090b20ee2effcfe5a1efa00eaff6d3b4dabe17dbbf22f967bf6a0f79f3c2a1ab6cb205e31fa9a83fa6c43cdf0ce5c818524bae1cb5f625162757a4e3dba81cb1714f830252d0eb5165ca227b084f41b9473aedd784fdab62f094b5a29b85ac9e2321acd705f723e2ba6880e4a585e588e101e685037c1504ad82d63cc7646fb1113cfb7c8eba6a82ad90fc7eb2da0211f829d6d9f36810250d083ae0b5d", 0xc6}, {&(0x7f00002f1000)="145d95d93ee358851881b0aeb656882199955378ecd4e56777592ffb474675fa9ae4a3546bd658a01a72bf35f3c9fbc517c5d007e36149926e4d1da588dbe3f29e8199bb4d03b30082f66d068f7c3f0fa9fba9bc959795753ea3fc947ea76d9f50616ad1a37bf62415b9064c46fda7c3d639904f36430f3537f17a8ee566bef4f34677c169132a85167575ec248fcf70f158e288a616fd7cbb508ee8c9763a8b22f2f4c99d0e9104ed32f2e687e9b11487c35ef60ad81ef0386906cd940aa8c5b38257462481fbd2ecf25b321784f81b8712651d33f8f9183962e5b6fee12d7f1b1bf4b22bbe0cd5cdcea1f606e7526a311fe87237be408cd124cea3b2b75d7f44c13e1117e7645febcfad44e68b3df162bc14e6f07d3f2b60a1ea0bbd9705e1fbf7c79a15d182dfcc465fef3fd1e771f9df5e69cb30eafee45e4b0b523330754b8c53438066932abaf5edd116a5a26a0b1e063635c64e57c7fbf27fd573f0c07fa398d763894b3b19918df167b039b66f1b2a900d235532eb12795f00a739d203e6045322570440b9c29be76666a4df180e0d88cd2aa3b043ac27c7d527e3b3692463de100affd0111d8f30f241266b124ebb5fac4b1a81693b27c37739f8940483c1b81405d909f0a6a45378758764b7e218d23dc5789b0e160c11fd37e22a1522965f8a76c6e9e695e36bdbb8c2f8df7e6c5628a50c4a8f4f9ab90bfe17789740d4ffcfd9e5f010c53f63176194d5ce1f786e1a63428d1745998f770158ad51d4fb408d788c8a83bffa781cdcff5619bd47117343354f55134171020e88b05d9f888943daf7d62b847f6b8eefa0cfaccc8fa31403159e87bddc37193979b6c7a0f7441a8d4c67d977aaa9d65e948a56d31c85ab48f1c295488dd438ddaad49a1270956666c470a4aa486c28fb6d5198d3ede7b46be9728ed66724c24a594360b2c95b8c812b26a7b0b3b64314368daf13e1f876a6803d730eb10ed85fe077cc7d205fdba270303a6f886dc01ffdcece94d3f7fc233a11fa6a348ab9366a7aab2fa482e6684b8f10830331a1cda7d482f8aa3d7687f38139757dade21544e5ebd4480a65baaaf97c823521a3bd139e3bf636dfd8eeca1e591792d46dbf26485726669cef16362e807378b0146f1ce0c0b6f22e388690c5ed6976f85a495c1b710e7072d07f18021ef70948585479bacf4612bf478466c9fafa283222eb6ee591eadea78b7863016e3402c2c2572adc73dc87e7c15ab9ad08c3836840db4090811d6e31572e27bd08f537cca5204fa3b3f97c3bc55164a8cff0b59aa05971b8ddec166d4e4896a4687ba87ec965b5646167e8ff22dad8f3219930882934d5b53048ea4482c1e299cf000019be12155093f70e2d8231d55b43b3ce8815f9f200b4d2e7f54f0064f3d396519bf05e168389b8b872ad89188e3b374bd858858011f8e6d6bb477558059ec9a66fee08815733a733f456803b1335a345ad5a9b511722fdae4be4b1f7bac4fe6a0a4af524de2b70f9a36167b144458c8576e8f799320256167da5ff70775bd1d551b11c423c9ade649818dccaa851b8b0144670cd11faa445e2992d74778f3a5d3f93b6c03d040a58f80acd057a4607c479c31b047bb06e1c14604ee53c6c033c9f443f315a4ec82fe1758c7e7dd04a663adb2ed0ac433b82c015bd288f2d4e5b438a41291d856d8f2b7163e61d6144b2c2b7431b7d0558ab038c6e42b16acc4306e6bebe2b894ccd968c738378e25dd538f668e6b062038c749347a27a068b20f783824a8ad3a1ba9c613873f3ca3bba14e54aa17735531444f3d8afc03fefee8fed8e123024d9de4c62c7b2cb1350d77ecfcf804ed454060e97c6b07582bd1105cc57691facf5f4ab6f1ec2f124f9882441b46fcf0dcff2df0cacf6c2c848bd264390cb1c2aad948c049880a9ecd87eb767f5012d10e2e8c952c2d6462a87d953d15a0f080731831ed0634bcd8e210ecaffb9fe18636aa6470e40fc85eebfb8d8e8e0fbc531a39d559bf113d2a6e2fb96e9a15ba268be3aff618e8e9c75da92bf8e54e8a0f256fbca447c86228a55807d2ff826ba0863141aa3d464545264077519e11f8f598d406c5d461b4b74ee3483e2274f3f49f77e24c5b4318b6d1a297b58450c99a9df3f52c6f7f0716abc26c151f43b2876ea0e08e4f7dddb6e73b983799baf02de1e52361fcbcbd159707718c3c34442780f1d610e446182cc14699690e51f1345e281893f6d22f429514526ffbe581df294eb43acd3129587759579835838f988c6429f68243b32f9142115abc4a1c3020069db015c9d1f7392486dbfe94d35d443d73e4a8ed50bea703434ee23723105b67c67cfc81d10ccf92c59c0239829885d0e08afc08541127336a1d08212fe1c472042540b686ea37b34adb32bddf580cc5652dc2b37e05425eed92f5c65e345383894f8b8f3155de7951433ef362bc5615c1fe8a94fab5c17ddca901e5ccffe76a1a0ba4282874eb18d79c314819d0779d8f3b0433202d6d45404a929f14fd52c9f5410ee871dbfc600b0027a12c19606157f6bcb143e20213570c69518b55b8921dfa5627d369d9d775ed782eecd8f45a5aad491bc43dfa14c60ff77958217d25715d0e1e729804a49c9a94a482bbfac314c7c1fc6ddd0428a7bc424d06e4c9c0b357818e47b21e8a30fa3bef4c59de14dcba3b428b1704a10173c3f372289da526f05fb0458c9fc75008b58421f27fa61eb8692b94209541e6e0d2ff3a5f97b3c1ab5a5824e8acf997a319b9e3cacb0d325dbd5b5544721329ca3b559edd86996a915b37262672e79c0333e646c14c85609f7438682376cb295ce32089a966ba96b5fe42f3d6a15f0c6ab8ce38e739bcc3c91ce14286a4a47761a1eb7e95b42793a813fdfa7dc6893e35891c9e4a5d0f7e4d19711117340432fa928351b25aa21b954d02067a227974e51e52471429cf67f25c0adf225d2205a8527c238c40d6a6a5f051d2a5d081ca5a50b103f6156251e0dc05352e5a60b9abee572bf16ceb4164359fa35508ac503167327ae8c9fd32b0144e93eeb980167d2e8016dd5bb425b100536f4c5dae1a1fd5b537d050b6491dd28ef2daa0f2274bee37634b3123e0dbf982841b89ecea1c746297b6c3c1ba53ff0d77c62ace5453ed35fa03d158cd58278f528e7908ff285f0ea2d30afa8e038ebbe5cd29c6268e4a66f6a23913026d11554537b64c572b8665c90f7a474582be42641b0a1b6c048bd8affd693dd2147f93db8a49ff7fba1f71438b5b2955666b81f34cdcb41c23fbe740e1cde64ef9dc5ad6ff90954771fe054fa7c82c90962a37b7c7e80f2276caeb522e7e43cb1c1a848fba3b24ce46e06c4cab19d011bae9108f3feb10dc6ce975be56c01ab350d94de1218e6570d15d0a709c52c4e20e158981b5785fa8c982e288338ae7f788d7e7b87db63f7d8e9c1b590b37a6516edcd481695123ae01892dd6a505d203473c4526f77f4d8ccbe070f35e1e45eba2d8675f984421a92c597b47618777193bd236bf96505bb89033399fc818be13089aa2a6573f7a8cb32bd127408821faddb3c438859479ceec026c59664857cb7b88b585da799d3d3a2ab0c560b34bf29fead33b0114a1be75be6fa36afaab8b8f6fc4e84dad63b9ab0fbe5eca14c5caa09d81a8763468c7500a32b89d772e85c332347e5dbac9e22aa277aea6625ed29ee91e1e6916e469db3503d29beb421ce7fd6d1b345eb29660325f0200c2bd8835b8e39e45b92956658987b01b663e67ccd1ea652535c1500364aeccdb3e7e5a2f101bf3b42eed44c72bd9f6b1f2e2ea4393a71a059fcbd7dffabf97a9e1de5c41c0af7a61fb2b8dfec29d23fc0757b2df5c6173715838e97b231c7260396fba11428bcc6834a463005ed464115eca273d8a7625791666d8e7104a06eb7c3e7f135c09ff03f5499a527853b177f6c14fcd6cb69ee977bbc5bd2365b78a8a3933c50e0cd11fc763a9a19cb27789226d9fe19d62a955cf7905abbba87374b3c7f3b31ec25351469c9c18a9b28159c492d9495c735ed23c5ae701b700e4e1a0899ba728776c34aa11f568907b7718fda7e190e14d39287472f8e5b3e4f13bc9bd569c8bd8e75523ce6cb5e175da6d3a2813e3c7bc306b09d54d425cda798e01a5283427a8da05ba7d434e08a45684f7df048466c7e3dbb341641fa28e0874f5be0ef4c81361453a5e12b84c476ab189f39945624fdf6582c798777470f3e416caa88c2d3d92f1e6c91a4685a3a8d5252b6dcf9ac43134b7dd6df5e2e707ef0946530f2542e3eba893f574f279553e91ddad4be7ed635037a35b23705f08b74a0a188c1283ae1e270487b63e26c3d5d075dc0c3c6d9515416080032ce4240f004ba972285cf8f9b1880938d54b709c22c6c08e55c52982dbd34fb7f9d0f3198bcf709d0d9508e34c0b46f97e00673d497bf5146cae51e5d1d74c102955dc3a64e037cc641c5e5dca32f8a755574ffbe7554cc651741684c8ed796c64404fff22f4c8a175702264d3c12557750567e0bc87685a68960694cf9ca7e5c5b75ab8e3ca6deda275310ac02d2ca9138519e3b702a60c51e357bff7c0ce55174e582d6f02394228f095988ed93d11ff348c5a127e878a769252c8c336dc7ef5427ee7438f4a7deb9e885021fc9499dfe998fad1e399e6a63f4883a78063f0349a13371cee2f6deb625f5e7bb5a21dc0a44b100f0cd974fd86050657107fbac2a086fd358a972e87f8c5c9b9a470eee780f572c9377923e85dd61f508a6f1982ec26fcda91ea1c9844d92edc7625b81bab48e9eadb8cdd43ac7e80af11c86a5f359af1667d30f3213dbe29598b88e8d2a0eefea7f4d1d53f1d622dc6cfdea45fd8cc03b3db086b88b4c56d1154f6232ef5aa04820c4e2524d4426ecfbad2dc5869f7187a483e80d1d4daa0b6b50538514cd04850d55b4f3adb9db58db912d08e14c0d3a11d9f21d539387b8e6476bfdae1ab824582f5f0fe595b9f6ddc1b89ec68b28e0f4aa2af2350981d460684e5234bd766c64803b145df7a4ba1860c4717d86e9eb8d0e8620a178482d1ca38b0379f4bad3aa62381bdcad7d226043d168eb48861dab79906a28087ebdf6157055e7b75bc28935a31f2b93d7da727aa53d5ef6ffec91c36ae76dc398ea345ff5192d81ab8ca87edd209fb9500c22799a607145292f40367af60e1ca959536c7f681130b7b7742797d50b642ff99d99ea5cd06afef3a41770a22280713a5c008b3efd074feda84696e30b237a130611ceff4120f25d402995bba2db79e7a06b440eccf9730847f5c9b3f23caac7802d53e9e2d7735389891cf6b892967e876607827ce10a838fdd3f095fbcdf15907d0daf01ad0ce771e246b6120ce2f608323909f54596f1567a51b4529e567a9edfc4a9c7e04cb312435a63686da3a68ce2f2fcc31cc15916eed3a4551c78c43a01f5ffe9fbcbabf63f85c82435366bb53262c4b1b0eaad062320f9905595b12abd05c47cd62c93b631145c07b195f7a4bb17a3d7eea41e262f2ecedbf5fe10f174623ebb60f27a6f9f5d944595a10c664355a4a523451afcd78553565f811b614e19aa7181030f60e61017626800ca40ac87636c2896916b3756f68083757ae04e98b9016cd5f90b490f1b309e104176629289b4d0bfa0150dfdd0838ae66a03271137677b10dadc5627dc8fd4d143800ebb7df7d2c2f3a1a6dd0dccda6f037c72ac040e3d1d47341696ca56b58df565f2affc09a2f62dac533493fa39f8dea336f7bfa866cd", 0x1000}, {&(0x7f0000cc3000)="02fdaac2cbf264d876cc665909c737081d43c57f37b9ead348d057d333080b2737ddd55e0ba6fea319a12024da554f6b5ede2b132c6ed12950da90df58311655021229f51a79103981f3429114f2467153ab6bad58682d9529c0da322cac50cf4623231bb47c78db3375339ddda8ba", 0x6f}, {&(0x7f0000b45000+0x6f1)="4f38", 0x2}, {&(0x7f0000d40000)="42ae5cd41c7830d1a30161cc438d4503053baa39437244e5e9e65a6c142855d61fc3b9186eaadad667c63aadf87d77e969afd581aa33bb10c304ceddff00d790040cec2ce339d7828f23671e328402732c3341becd6fdc6b6b8be8f6c6670a1249ff8e3e15cb0307b1a90c5d2ac58dcaf9a1eed1c9930634f1f01dfcff3656410fd76f73209949e844c3b91c6e", 0x8d}, {&(0x7f0000dfe000-0x7a)="abadc42af01fdb47b0e91fefe326bef09bb4c24de63e3b67b45354e6b072126ae317f365db1955005126899206210b627741d534466677c66fe6cce759a9e669f4588dc8d4de22d81acea654d56f56aedef751f8904a65f0b1eb1af0200051a5ecbee85d1ca97c61d7ff2029dc6270df6f782d6d34b2fc5ef2d7", 0x7a}, {&(0x7f0000b73000)="03f1864736359520d78e5ffabe59600ded3f30e72e5b89c0d4fe8a3b5884a4fab8b829601f3d1422272d27681dd47daf44768d117711b4682714f7fcd75ce35a6b6e474488f12c01a46b2e936a128a8e9b42890d1b64ced7b37f87329f6008c98303b9f51a9cc0b216e156360f9de5293fff133ff698bea5c1dd9d15445311926256de23c05b1fab3fc9f74b6b571b824f7df04538ab9cd21a72dcc196c0348acb0ab73ebf92434aa5d19a88fc463d6920710c59578a155fa2475335e53bb5059b6f20796a3d26202d3c214127e118e8669e1b", 0xd3}, {&(0x7f0000730000-0x98)="a48027af1c0c7873f1a47689b27b1eaec109be4df92b278983c21cf3031b4d9502f823fb7f2ccdcfbe9b8b5adb06dc4d3883b631782b0889e52de6a0c0466f1713191f74ed05cab3b859ed88505bf1b280ae30b6e8a853ea1edcd3dddd971948985bcb0410d80ebe71fc79dd492353a19468068a891a0b3f2e88e778162cf28ecde8f87496704e34c8deb4cdf3044a2843c8a7dd08be24c2", 0x98}, {&(0x7f00007fa000)="62fb5f0f5fce1f794cbaaaea32cf50b99d8d83c0dd74a54860febf4690b5a6507e87ca724df9be988b5d411deccdb0a43785c8e0d9e7d3dfbfc2c9e0d6ba45703c50a8cf972852f5e82c3ae905128d497a335ca27ea976f5122579bc096a61ae01df3c9c5051801b5bc4962bc80b7796816782c46f0ad5dafd1327b3f15cc8eee2", 0x81}, {&(0x7f00005e5000)="c00b960ba07627f70d591b9ebc8c8a2a1d8a8e451094d0d1c053cc4b33056a10da5f94fce272f5bb7fe31e89e5b96ef4e343b3a9ab0a517dd3b64ba29e9b9f51b6394e40a80639f08759f8f048b984a86780b77e379f69ae90468245786db01b3e10ed0f31b5cf1daeab4cc91c2de3", 0x6f}], 0xa, &(0x7f0000f78000)=[], 0x0, 0x100000000040004}, 0x40011)
setsockopt$inet_mreqsrc(r2, 0x0, 0x27, &(0x7f0000001000-0xc)={@multicast2=0xe0000002, @loopback=0x7f000001, @multicast2=0xe0000002}, 0xc)
r5 = socket$inet_sctp(0x2, 0x5, 0x84)
setsockopt$inet_sctp_SCTP_DISABLE_FRAGMENTS(r2, 0x84, 0x8, &(0x7f0000550000-0x4)=0x4976, 0x4)
ioctl$sock_inet_sctp_SIOCINQ(r5, 0x541b, &(0x7f0000734000)=0x0)
socket$netlink(0x10, 0x3, 0x11)
setsockopt$netlink_NETLINK_ADD_MEMBERSHIP(r0, 0x10e, 0x1, &(0x7f0000cb1000-0x4)=0x7, 0x4)
getsockopt$inet_sctp6_SCTP_CONTEXT(r4, 0x84, 0x11, &(0x7f000000c000-0x8)={<r6=>0x0, 0x3}, &(0x7f0000610000)=0x8)
getsockopt$inet_sctp6_SCTP_ASSOCINFO(r0, 0x84, 0x1, &(0x7f000037c000)={<r7=>r6, 0x23d, 0x0, 0xffffffffffffffff, 0xb63, 0xffffffff7ffffff7}, &(0x7f0000830000-0x4)=0x14)
getsockopt$inet_sctp_SCTP_GET_PEER_ADDR_INFO(r2, 0x84, 0xf, &(0x7f00008ca000)={r7, @in={{0x2, 0x0, @rand_addr=0x8, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x400000000000101, 0x9, 0x20, 0x2, 0xfffffffffffffffd}, &(0x7f0000f63000)=0xa0)
r8 = socket$inet_udp(0x2, 0x2, 0x0)
setsockopt$inet_udp_encap(r2, 0x11, 0x64, &(0x7f0000c42000)=0x3, 0x4)
setsockopt$inet_MCAST_JOIN_GROUP(r8, 0x0, 0x2a, &(0x7f000089d000-0x90)={0x1, {{0x2, 0x1, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x90)
close(r8)
socket$inet_tcp(0x2, 0x1, 0x0)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet_icmp(0x2, 0x2, 0x1)
recvmsg(r0, &(0x7f00003d8000)={&(0x7f0000cdf000-0x10)=@ipx={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, 0x10, &(0x7f00003cc000-0x80)=[{&(0x7f000084d000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x33}, {&(0x7f00006fb000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6b}, {&(0x7f0000b1a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x68}, {&(0x7f0000ace000-0x96)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x96}, {&(0x7f000000c000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f0000677000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f000051c000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0}, {&(0x7f0000664000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xa8}], 0x8, &(0x7f00009de000-0xe0)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe0, 0xd7}, 0x141)
r1 = openat$selinux_validatetrans(0xffffffffffffff9c, &(0x7f00002a8000)="2f73656c696e75782f76616c69646174657472616e7300", 0x1, 0x0)
ioctl$sock_bt_bnep_BNEPGETSUPPFEAT(r1, 0x800442d4, &(0x7f0000ba5000)=0x5)
r2 = add_key$keyring(&(0x7f0000eac000)="6b657972696e6700", &(0x7f0000001000-0x5)={0x73, 0x79, 0x7a, 0x0, 0x0}, 0x0, 0x0, 0x0)
r3 = add_key$user(&(0x7f0000176000)="7573657200", &(0x7f00009d6000-0x5)={0x73, 0x79, 0x7a, 0x0, 0x0}, &(0x7f000003e000)="fa", 0x1, r2)
r4 = add_key$user(&(0x7f0000893000)="7573657200", &(0x7f0000753000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, &(0x7f0000632000-0xc1)="b33ab70079ebe0d94f729cd653e520c19ad7d97fe21769e7c4db44c249b544230ba287fb8bd6ed266ccf59ef70995bf2e8e0ecd3fff32853747eda22d2818d08ca27e0ec821620e365a0e6b9485f2d925493f60c01e33e5f8c7eba67fc19a9497f5b07e5849d2e875b066cd640b336616fe0f3c3002813b4627ee7597689525e8e81f750a86eb580fb4690ea52246bd3d32b1a91f944edb74b1f50ae08c5387ed8fd0598b600579f3af3f864e1c324f6928f6672f98f7e149be31bd78b506e8b0a", 0xc1, r2)
r5 = syz_open_dev$mice(&(0x7f00007b4000-0x10)="2f6465762f696e7075742f6d69636500", 0x0, 0x400000)
ioctl$TUNATTACHFILTER(r5, 0x401054d5, &(0x7f0000e1b000)={0x2, &(0x7f0000b61000)=[{0x9, 0x8001, 0x9, 0x6}, {0x4, 0x1, 0xfffffffffffffffb, 0x8000}]})
keyctl$dh_compute(0x17, &(0x7f00004c9000-0xc)={r3, r4, r3}, &(0x7f00005cd000)="00", 0x1, &(0x7f00008bd000)={&(0x7f0000334000-0xc)={"7368613235362d7373736533"}, &(0x7f0000836000)="da", 0x1, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$sock_SIOCGIFCONF(r0, 0x8910, &(0x7f0000f16000)=@buf={0x7, &(0x7f0000daf000)="520d6760af86ec"})
2017/12/15 11:53:26 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000500000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20000, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x4, 0x78, 0xd4e7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e7, 0x0, 0x0, 0x0, 0x0, 0x100, 0x2, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
signalfd4(0xffffffffffffffff, &(0x7f0000006000)={0x7fffffff}, 0x8, 0x0)
epoll_create1(0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x5, 0x0, &(0x7f0000845000)={0x0, <r0=>0x0})
r1 = accept(r0, &(0x7f00009c7000-0x6)=@hci={0x0, 0x0, 0x0}, &(0x7f0000de4000-0x4)=0x6)
getsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(0xffffffffffffffff, 0x84, 0x13, &(0x7f0000564000)={<r2=>0x0, 0x5}, &(0x7f0000dfe000)=0x8)
getsockopt$inet_sctp6_SCTP_SOCKOPT_PEELOFF(r1, 0x84, 0x66, &(0x7f0000165000-0x8)={r2, 0x89d}, &(0x7f0000326000)=0x8)
mkdir(&(0x7f0000032000)="2e2f636f6e74726f6c00", 0x0)
r3 = open(&(0x7f0000028000)="2e2f636f6e74726f6c00", 0x0, 0x0)
symlinkat(&(0x7f0000444000-0xa)="2e2f636f6e74726f6c00", r3, &(0x7f000034b000-0x8)="2e2f66696c653000")
fchmodat(r3, &(0x7f0000e35000-0xa)="2e2f636f6e74726f6c00", 0x84)
iopl(0x0)
mkdirat(0xffffffffffffffff, &(0x7f00009ec000)="2e2f636f6e74726f6c00", 0x104)
name_to_handle_at(r3, &(0x7f000000a000)="2e2f66696c653000", &(0x7f0000036000)={0xc, 0x0, "58"}, &(0x7f0000040000)=0x0, 0x1000)
renameat(r3, &(0x7f000001b000)="2e2f66696c653000", r3, &(0x7f0000009000)="2e2f636f6e74726f6c00")
lsetxattr(&(0x7f0000592000)="2e2f636f6e74726f6c00", &(0x7f0000aff000)=@known="73797374656d2e706f7369785f61636c5f64656661756c7400", &(0x7f0000242000-0x12)="63707573657476626f786e657430242d2a00", 0x12, 0x2)
getsockopt$inet_sctp6_SCTP_PEER_ADDR_THLDS(r3, 0x84, 0x1f, &(0x7f00004fa000)={r2, @in={{0x2, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0xb1, 0x0}, &(0x7f0000e94000-0x4)=0x98)
prctl$seccomp(0x16, 0x2, &(0x7f00005d2000+0x95e)={0x0, &(0x7f0000ab9000)=[]})
readlinkat(r3, &(0x7f0000edc000)="2e2f636f6e74726f6c00", &(0x7f00005df000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xea)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = socket$inet6(0xa, 0xa, 0x9)
setsockopt$inet6_IPV6_FLOWLABEL_MGR(r4, 0x29, 0x20, &(0x7f0000f60000-0x20)={@loopback={0x0, 0x1}, 0x800, 0x0, 0xff, 0x1, 0x0, 0x0, 0x0}, 0x20)
2017/12/15 11:53:26 executing program 2:
r0 = creat(&(0x7f00002b2000+0xcd4)="2e2f66696c653000", 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$VT_GETMODE(r0, 0x5601, &(0x7f0000001000-0x8)={0x0, 0x0, 0x0, 0x0, 0x0})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x966, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000e6d000-0x8)={<r1=>0xffffffffffffffff, <r2=>0xffffffffffffffff})
write(r2, &(0x7f0000e8e000-0x25)="2700000014005702007fffffff00000032000000f6582a00000000000787001f05", 0x21)
close(r2)
r3 = socket(0x100000000011, 0x2, 0x8)
setsockopt$packet_fanout(r3, 0x107, 0x12, &(0x7f00007e4000-0x4)={0x0, 0x0, 0xfdd}, 0x4)
r4 = socket$inet(0x2, 0x1, 0x0)
r5 = syz_open_dev$tun(&(0x7f0000520000-0xd)="2f6465762f6e65742f74756e00", 0x0, 0xa)
r6 = fcntl$dupfd(r5, 0x0, r5)
ioctl$TUNSETIFF(r5, 0x400454ca, &(0x7f0000a5b000-0x28)={@common="67726530000000000000000000000000", @ifru_names=@generic="4f54000cc0a1ed4f3a0a1fdc222073b5"})
r7 = openat$cuse(0xffffffffffffff9c, &(0x7f0000583000-0xa)="2f6465762f6375736500", 0x80000, 0x0)
ioctl$sock_SIOCGPGRP(r7, 0x8904, &(0x7f0000527000-0x4)=0x0)
getsockopt$inet_sctp6_SCTP_GET_PEER_ADDRS(r1, 0x84, 0x6c, &(0x7f000025c000-0x4e)={<r8=>0x0, 0x46, "bf90f292d3670f0011f47ed70cdfb59bef877125c9e20b4279202cfe7489cb4f96c9279f3a56e8978624c4296aa665367be24e0c5c684c4a03ff591bce5628dfc7b138e49f22"}, &(0x7f0000a45000)=0x4e)
getsockopt$inet_sctp6_SCTP_LOCAL_AUTH_CHUNKS(r6, 0x84, 0x1b, &(0x7f000047b000-0x8)={r8, 0x0, ""}, &(0x7f00001ea000)=0x8)
lstat(&(0x7f0000eb2000)="2e2f66696c653000", &(0x7f0000f66000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
fcntl$getownex(r3, 0x10, &(0x7f00002d1000-0x8)={0x0, 0x0})
setsockopt$bt_l2cap_L2CAP_CONNINFO(r7, 0x6, 0x2, &(0x7f0000baa000-0x5)={0x12d, 0x3, 0xcfe, 0x800}, 0x5)
gettid()
getsockopt$inet_IP_XFRM_POLICY(r3, 0x0, 0x11, &(0x7f00006c6000)={{{@in=@empty=0x0, @in=@loopback=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@remote={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000861000)=0xe8)
ioctl$sock_inet_SIOCSIFFLAGS(r4, 0x8914, &(0x7f0000630000-0x20)={@common="67726530000000000000000000000000", @ifru_flags=0x301})
write$tun(r6, &(0x7f000020e000)=@hdr={0x0, 0x0, 0x0, 0x5f78caba, 0x0, 0x9, @ipv4={{0xd, 0x4, 0x0, 0x0, 0x1039, 0x0, 0x3076, 0x0, 0x0, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, @remote={0xac, 0x14, 0x0, 0xbb}, {[@noop={0x1}, @lsrr={0x83, 0x1f, 0x4, [@empty=0x0, @empty=0x0, @empty=0x0, @loopback=0x7f000001, @local={0xac, 0x14, 0x0, 0xaa}, @local={0xac, 0x14, 0x0, 0xaa}, @multicast2=0xe0000002]}]}}, @udp={0x1, 0x0, 0x1005, 0x0, "0330936fee7091ab920712397a82a7c3e58af8e7421d7c483319effcd884c775e8d9ebf2567793bb218f45ee9688ab7226d0ca0fe318d2c4482e1f59afb01dd78daf0dc5fab7de78761280b8fc6f119a71ad362df22cdd51820fc3f6d65e549ce79c99f1f3ef9c1e6af5cb7b4d4db8b2464fbbd91aca0d4855800984d815794646c03c357d260fe5f45bccd76cff1167bf1f91f6332a727bf7ca61f480e0714ae3216c05d4ec83624c72ee20b1849146abb701ce661509c999f950a88a62f5a67b52f565cfbf898a84e2d1b989ee00fd5abd4170b1aed8ae4408e8441f78115768554c35d82e03308c245d796fea9521d51c162410ab8e6e83cccd39384e19a4c1eb3e18ff97338f0b8b33361bc9771509a246258e298620a8755cbcb3914fcee92158987ab5aa4e4c923282c35bbf1f4385af113ae00b8da6d6ca8f2b3ed073aff908446ad44b83c814e686c9010521e7828682d9431305a16f731c77cac2cc4ed5e4e4d3db0b6237306eb0909091394e15da2946f69471c5c404cb0343529d84941f4f927eb73c6c83bf5300f1e972f3d5b71ef4e0ef493fa43aff2382316dd457beb80aa076d40e457a2d602356fc9f71bccaa9ef23e431a1913ae59c1baff9000065a6c37d1bdfc08520535d4fe40d431ef9a06eea0da4cc9b0611b97470b89641f0f1156ef5ab538c620bd75217aba079b5154088160ada45097c6a13d613c51461d3a3fa5bd250c5b4a271ec6284fa99ca31fe8c0a7bf1c6d32d459745e7dd1256066af8e65e65a242615bc30d9e85395de5ec57f1b6636dec5febae83db6a993a59b317161ff94ac788e73ff819122944acb8a1a00a819bd61ac4f609527bf174f26beea60cb3a9ee9e1e8ea85647bd260250243f7b262d463457067a12390731a0d9b20000000000000000796e4ea302676543ff6b8cdc6e041dc87722019ab1d5d358665bc05d376f351da21a0b84b0e5e8f1f8e4d23c518cb4bf3e993963b0b9460d8ed9fd1ddf879e4e62ffb545bc30b30cd29be8445e36cda495a54a789b20b053df6970a407052221338f4a8c751a649065c00c470c437c21363817a54da198a2d488f8faf68d0eb0be8d15937a77dc6d935522f84f17971768b57a5f6989ba8911ed4caa50c12e43f102294ec405df183cee46a9c1bb72b22b62eada128ce91ce31613dddcd7f40d83a0f18eaae6e8229be2ec328215a28c00e4572b28dcdf48ac2b3eb7b79f92d9ffac98a0809e798b971c69705d7feeed78caaedf37dcad9e71d1ada9f0a2f37749ffc14b4212ac66588ccb99ded92422657277920ed7b3e80b145212a66f0a3fb0faa88374f4e9d8fad6cfdcd40131016b78feef588cf04a29295282cce21eee0e537362a9a64eb7d352dec82023da3cd2f61e04d83be7f078565a3c444f1f3f976b5c686d7c0ffa9384a470c78a368ff5320000001591389faa3b3aa8309979c1a7f5e24f3dc57cd3761a33e093a9bdaa2a307b393df5f84c54db424cad667c25abd37300d774c72dde8852bb09359efb88441940d973d4c48f7ba8b4980d8a5eccdc9fcf5214ff27bd5b1d5a47eacb2048b452624de044f4eba7a1d4f4020510fb7e215c2769e9c39df211e5fc36d7c1ddbfefa7ea9660e9fcbeacd2b943fb8cfd030cc523349e55d53e9a08dc507752b399fca5f529c28551d69222c5191d3c789cbc3fc77854f28caf282d6a6614912ceb1d76e0e38fe5ae80bd7bf38fd957b23625f2a8b130c64f5799b624e89800475ba503835804b8de05791dcfd953aa219a216c3d7fe75b0433c9416218976199060e3d40d4755553e1dbdffda7d8a9000ffee87f078a1d71e68cc75df0d812fa0ba59b964b5356d193f9ba7ee10bbc6070edabed4ac794359839781951fb2170236f93b12b54309e829057de2a692d4514b934a46ad895d1d787ec31ba43c37672294167f5e9871fb851aa68f7a85836dc2eca3fbb749917e3f7b86c0b6aba8b5be7ab16b07ad70f4842d2143f28daea2c83f48603d34f30a68067456c6e5e76b71698ae4018b469b21b71fcead317444243e38d18c4a5728459a8c551190193a3c4981f0f2580314466c8bf4466c029cd6cbbef6b7aac4e1fdd3d69e007a406926e029f47220274f8483baa9c3298c2939db7afe9b1908378e45341f13fc521b4a9f820258afbad16d9394ba1c991091c7a022719cf4c2430b6dd11fe1351a8f0678bd8ca30b470f3b36fe54bfe2b865cb54bea4e1ea63499b31d95bab401da65482993ddc21eef72dd889858e9677dd890eba3acbed8d40e4a1a8e6d20f47b48abcfc6dc0a82d10b80b885aa7bebb858c26706e4c95fa25398e55425a2d389b1156cbf3708c8745a30a41ee831158dff5cbf1fdede595f62044c08b23bb01f046c5d675bc762cad95a1875cfca3b3a168769adad67d60f860c625bc80b1ccc97a591c4d10db04d13584dabca62157fb5ffec0109d2c372422a63ff9705447f187456524f55776afbf19780656c04a7125791363d9cf7400e01258b22efe631be3893e0726f0366169aa96c5f2db761ddf37071741817abd644449f6032f57d27925ae5b6fe7dcce2aba96ceb56c687cee2103c0991800b09aad7577d4c46872b5f38a4ee06fdacadb783f6e865d59cfbd285a87b39c751b8b340a030b9826d8b16d1c0190112bab0ee48c2671720037a302ad650fa7b695dd2dda85ebc75f75df458b2593a9af29c0d17c75fe20244765c03b687cb3e61aed349f51a0aa139fd920eeb730f7cdcefbae27771e080c5d93910c83ff0983a51c58cd3b99240ad6458ef5e9635878e6131755a042141f8fb61e44d386b249444ccc5591584ee706760169c7be0e20cb5153ea32872f070030cfa59259e851dea623603efc3e3bcbeab06d24ef105aa5c80fe0f5f3a332974a2c5aca517e287c0be60fb8660c15a2675137f96f4495b119f038906205cc2e9e382c660624d9daa1f158a748f5c58f5d082575e0b05795345557489150ed925e20f22567f89759001f97435ae868a45f4f2ab3276e6de2bf2ffe169c2c39ee78e3dea90652642718dff46d5b8c0116b0509f507056a6f1cccb729a68a42d2aca9dea6d1006f34a6b9a2d27b61bc678c9ff0e079a5bab03f366ba1df81887acae936baa94ce48b2709485097665cc971a8ffedd2c2c1a4bb0a4b364ea54b996fcb5ed328f6d8da2746859afcd7aaf20e67201c5501e07ec4e9ebae8b2b12edcd2780f47bd53f4511011df0ded991f4dd6074552088685e7803d706cd2afefa432759b43924018bb7bfdbc61a7b06cace066697b95565f6e00d692a5e9be0765a12771c525a678c85759e9a8f4aa075364036d11bd7cd488e41a07bf679376fb08707bff3564c147a78d077636f46cd11b8c3819159e69f103a6d58a2ec10647db66566c44a22bd2270915f145e3feb314274f4e90e3109ed1bfaeb9d9b3f8ef47b42128688107319f4243475ec116e32e54ecdacceac1deb29af8b3751fdb83912486b1941f673647fd79c5b61ee14909baa4fbcbc0794796fcbaf67b86ad6f99c7f50e84d2c1f7799b2a9f3c49ca98dc87db80ec3e974e83e0de57cff1b204f111ea7e794638e520ddf06b82c650f80db13f403f7b12efff3788fd15f9e6a2dee28b346b9c3ba2304d691980ed862523386f0eac0b362bd2c19dfe75c73012cb3539f02ddeaaac2a5677fae4d0b48d770aff2fc35661ca1c318c70c7fbaa38130995b70a0f4b8abc4448f3fda35f51bb75955b1f900a894788830b19698bb6fd764009973e1a65e7036f4b8644737da9035fc5b0ea6345c25f99780702029ceb309d55736abdb2803a56e7afaf4345f76d3a11e8b0164b96e68ae4a84c536504107a54c36433d1ee49ee439bedb43ad2bbe7ae2001f21656460405e1e00d6a2ce853ab5e3fe782279b6a16727c9d5dc0391875552bc48ec2fc25833369649536c6e4eb87ef78f2d8b1189463966a8c03ff2984da244a2c4beafbe8740a72ff9b695bc41e783d838484410f52d280f132ddbfa76075d7ec56f3b2536e4a7482eb106afe6c29adba942c616b7914f82694ccfa9a1e25cae93ad53f2aac13ad87058642bc83c7a781ebeb4f6a09e739803f686bae4d9ff6cbb83ca12b93dd4791d746b927ab285b768703ea3abb76167c1d56e1ebffe69c1b4c79a948f99daa14a51ad8857c29a2ba9fbc088e120e5566a048524ac247f391dc87e9ce8b269a5bb6635c7f76aa07cdd89e5cb1e9051d7ef14c299ff32d653778c3c40d14a2359f9139282c504be4292f7c3749f9e09321917c26e48e7ecec931c64533da7b6bd511e15170f66c6d63c1064384545a4c92fa23a1b1d659be3b9dc1649db44f2a0bb08aa0cd94315a9219b5a0a20765438caa3065279487cfc4704f8abc8600322ac927dc448a227d41777182eead38d3510ac691572cf368319b7274315d3b29e9387f4b73d0470aebb73b30c1f0fd1bab4834d6823796b7a6b974e85553f09a1862caacc73a79423719214632092a027ada46555532e1542e3825025ff1fb98d1a157571fba9a92c671b4649e19be2b211f944aabdbedf3befc1c2cd079cc367870360f5c5a1dc2afe6158bd761ea8855c15bce7c0f71334f465ba9762b74cc1ae547e5c0de0d934c3ad80f5a41881fdea2f10ee906b381b688b8f43e5bfc8d8e522ec1aa5f3c315ef398bdf4d31dc163324bf33a310ca7f44a5bfaebd0b7cf50a3647865260a2bac757c15007b7889fcc79838c0cf8657b0d82dcb828204df70650debb3577c19e76fea560d39135e0253d1ad31604eb1303dad04c65811ce0a17ffb22936a5f630e2b406e7c7c7c73de8520415982a6356c6a313b4dc63fca714a408e50a651a4c2b0a744b27e4f1ccf622620d4d1265992acb74b48c8daced8b3544b18ee09be85aa9808b74ea222dae9be165458573cdabb0df10b1c74530b76250ce63736fdfaa4b8636b7b35c75d0ebd44cec50e98aec97412fa4b98c6fac8a7369a46af7ba53309664fc31e0e971d723d5a77a18dfc5e420f8f7fb9cb4e97b767b02a97e11728147164ca1632dd6a47993f242de0dd6dd57391b7d7977c69ecb79e438ca7092a71dd3e0fe26b0acdd046b928b319460498929a2b1181b25efb4991cb3bf772d1f67b563252660fc9bf27a2226355badb51e2078a4f87ff3a542939dddb282467121692094a4b82db9a18872f4d184025741cb26e1c377b8892f9856f2cc8d1c77451b2a2fe096e779cb9d7cca399a8bb5b70a4b6a04caf4d266ec3fba53dd0abdba21ed5fdeb7b41c9c61b4e712375adedaedb69ed35aacea1fc1ac50713b08dc72c01dcd728d658de488551b2a295482a0ea2741dbbf307da31ec62e87f2ac22d95a49b72456a5f1efb64af8893fef5590985085139230c8f6ee704a308a843a824ab7132cbc593417526906587a3daf51c0d27319e353e600d3a1b4f2c42352b4b91393d34ad3850acafb178810dc3c2d3948bd091c08829dd26935d77c7c7f93dab1b28fbb1c24d8cb4c9e6a3830114db3b1e0b3889fbe4641a6537538e46ba9f14e3a082acbe6ef73a045c20cde316d0210eff5482ca62ec7829e9146f02757bd33a0ee9b0ff159ff2eaea394aad7f9d72ff99055afb33d230986a19974e1b2f01da97c538c9203d73ae0fa918a1f740233ab69f6a76635d307bb2804eb61b6a2b58dccbbbca0ffa7ec1fa747ee1c914f240a7487217e62eeed7f575523d8ddd8cf190ec1d1a28af0212bb7b2ce20d755d7f694af9beab36e96d6e0e3d96fd10"}}}, 0x1043)
open$dir(&(0x7f0000d5c000-0x8)="2e2f66696c653000", 0x200, 0x124)
ioctl$KDGETKEYCODE(r6, 0x4b4c, &(0x7f00008a1000)={0x0, 0x1000})
close(r1)
getsockopt$inet6_IPV6_XFRM_POLICY(r3, 0x29, 0x23, &(0x7f0000125000)={{{@in=@loopback=0x0, @in=@remote={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000b93000+0xfea)=0xe8)
ioctl$LOOP_SET_BLOCK_SIZE(r0, 0x4c09, 0x7ff)
2017/12/15 11:53:26 executing program 5:
mmap(&(0x7f0000000000/0x755000)=nil, 0x755000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$usbmon(&(0x7f00002e6000)="2f6465762f7573626d6f6e2300", 0x15a, 0x304)
setsockopt$inet_sctp_SCTP_RESET_STREAMS(r0, 0x84, 0x77, &(0x7f00006cf000-0x8)={0x0, 0x3}, 0x8)
r1 = openat(r0, &(0x7f000074e000)="2e2f66696c653000", 0x101010, 0x800000000000063)
ioctl$DRM_IOCTL_PRIME_FD_TO_HANDLE(r1, 0xc00c642e, &(0x7f00002b3000-0xc)={<r2=>0x0, 0x80000, <r3=>r0})
r4 = openat$selinux_status(0xffffffffffffff9c, &(0x7f0000571000-0x10)="2f73656c696e75782f73746174757300", 0x0, 0x0)
ioctl$DRM_IOCTL_GEM_OPEN(r3, 0xc010640b, &(0x7f0000053000)={<r5=>0x0, r2, 0x7})
ioctl$DRM_IOCTL_GEM_OPEN(r4, 0xc010640b, &(0x7f00001ef000)={<r6=>r5, r2, 0x2000000000000008})
ioctl$DRM_IOCTL_GEM_OPEN(r3, 0xc010640b, &(0x7f000074f000)={<r7=>r6, <r8=>0x0, 0x3f})
ioctl$DRM_IOCTL_GEM_OPEN(r1, 0xc010640b, &(0x7f000074e000-0x1)={r7, r8, 0x7})
signalfd4(r0, &(0x7f0000719000)={0x0}, 0x8, 0x80000)
mmap(&(0x7f0000755000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
r9 = openat$vga_arbiter(0xffffffffffffff9c, &(0x7f0000118000)="2f6465762f7667615f6172626974657200", 0x2105, 0x0)
ioctl$KVM_SET_DEVICE_ATTR(r9, 0x4018aee1, &(0x7f00003ac000)={0x0, 0xfffffffffffffff6, 0x40000, &(0x7f00004a4000)=0x0})
ioctl$sock_bt_cmtp_CMTPCONNDEL(r1, 0x400443c9, &(0x7f0000754000)={{0x8d23, 0x2, 0x8, 0x2, 0x7, 0x6}, 0x7ff})
r10 = memfd_create(&(0x7f0000753000)="75736572aa736563757269747900", 0x4000000000200003)
mmap(&(0x7f0000755000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r11 = openat$kvm(0xffffffffffffff9c, &(0x7f000074f000-0x9)="2f6465762f6b766d00", 0x0, 0x0)
r12 = ioctl$KVM_CREATE_VM(r11, 0xae01, 0x0)
mmap(&(0x7f0000756000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pwrite64(r3, &(0x7f0000756000)="a9e2ff5f0a36000096c0d7087c6a358c20b6477c7c5c9cbf84bc34fcb44cc1f6b07b04c3ca9aea99d505", 0x2a, 0x0)
mmap(&(0x7f0000755000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000755000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r13 = request_key(&(0x7f0000755000)="646e735f7265736f6c76657200", &(0x7f0000110000)={0x73, 0x79, 0x7a, 0x2, 0x0}, &(0x7f00006df000)="2f6465762f7573626d6f6e2300", 0xfffffffffffffffa)
mmap(&(0x7f0000755000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_IPV6_IPSEC_POLICY(r9, 0x29, 0x22, &(0x7f00001fa000)={{{@in=@empty=0x0, @in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r14=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in=@rand_addr=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000755000)=0xe8)
fstat(r3, &(0x7f00002a1000)={0x0, 0x0, 0x0, 0x0, 0x0, <r15=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
keyctl$chown(0x4, r13, r14, r15)
ioctl$KVM_SET_GSI_ROUTING(r10, 0x4008ae6a, &(0x7f00005a6000-0x158)={0x7, 0x0, [{0x7, 0x1, 0x0, 0x0, @adapter={0x8, 0x4, 0xfffffffffffffffc, 0x4, 0x400}}, {0x7fff, 0x1, 0x0, 0x0, @adapter={0x40, 0x1ff, 0x7fff, 0x800, 0x13b}}, {0xfffffffffffffff8, 0x7, 0x0, 0x0, @adapter={0x2, 0x3, 0xffffffffffffffc0, 0x767f, 0x3f}}, {0x400, 0x3, 0x0, 0x0, @irqchip={0x2, 0x7e2}}, {0x9, 0x4, 0x0, 0x0, @adapter={0x8, 0x2, 0x91a, 0x0, 0x5}}, {0x68, 0x1, 0x0, 0x0, @sint={0x1ff, 0x5}}, {0x0, 0x3, 0x0, 0x0, @msi={0xfffffffffffffffe, 0x7fff, 0x6}}]})
r16 = ioctl$KVM_CREATE_VCPU(r12, 0xae41, 0x0)
syz_kvm_setup_cpu$x86(r12, r16, &(0x7f0000120000/0x18000)=nil, &(0x7f00005bb000-0x18)=[@textreal={0x8, &(0x7f0000755000-0x39)="0f234c0f2343660f382899040064660f3804d0f26726f6699bb8b3088ed8baf80c66b89c318e8766efbafc0c66ed652e6536d6f30f350f18d2", 0x39}], 0x1, 0x2, &(0x7f0000754000)=[], 0x0)
ioctl$KVM_SET_MSRS(r16, 0x4008ae89, &(0x7f0000750000)={0x4, 0x0, [{0x40000000, 0x0, 0x8}, {0x40000001, 0x0, 0x1ff}, {0x1000000000, 0x0, 0x400000080002}, {0x266, 0x0, 0x4}]})
[ 50.643091] SELinux: unrecognized netlink message: protocol=0 nlmsg_type=18176 sclass=netlink_route_socket pig=7312 comm=syz-executor3
2017/12/15 11:53:26 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x400, 0x0, 0x0, 0x0, 0x0, 0x400000000000, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = syz_open_procfs(0x0, &(0x7f0000003000-0xa)="6d6f756e74696e666f00")
mmap(&(0x7f0000000000/0x8000)=nil, 0x8000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = syz_open_dev$binder(&(0x7f0000005000)="2f6465762f62696e6465722300", 0x0, 0x0)
close(r1)
r2 = syz_open_dev$binder(&(0x7f0000009000-0xd)="2f6465762f62696e6465722300", 0x0, 0x0)
mmap(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x0, 0x20011, r2, 0x0)
r3 = getpgid(0xffffffffffffffff)
fcntl$lock(r1, 0x7, &(0x7f0000f70000-0x20)={0x0, 0x0, 0x4, 0x4, r3})
mmap(&(0x7f0000009000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000008000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$BINDER_SET_CONTEXT_MGR(r2, 0x40046207, 0x0)
ioctl$BINDER_GET_NODE_DEBUG_INFO(r2, 0xc018620b, &(0x7f0000140000-0x18)={<r4=>0x0, 0x0, 0x0, 0x0})
ioctl$BINDER_WRITE_READ(r0, 0xc0306201, &(0x7f0000009000-0x30)={0x74, 0x0, &(0x7f0000023000)=[@transaction_sg={0x40486311, {{0x4, 0x0, 0x0, 0x0, 0x10, 0x0, 0x0, 0x0, 0x0, &(0x7f0000886000)=[], &(0x7f000016d000-0x18)=[]}, 0x9}}, @acquire={0x40046305, 0x1}, @increfs={0x40046304, 0x1000000000000}, @acquire_done={0x40106309, r4, 0x3}, @exit_looper={0x630d}], 0x48, 0x0, &(0x7f0000009000)="d8fc1dd16de371f1d99e3b4d488546c2bbb067efde9e55e9d1048602c19fe0b0078ade697201170fdbcc34816df860d3f87023a9d8567fa3297aac9d65b25106fc55ed85da8cb6f3"})
ioctl$BINDER_WRITE_READ(r1, 0xc0306201, &(0x7f0000007000)={0x4, 0x0, &(0x7f0000006000-0x2c)=[@acquire_done={0x40486311, 0x0, 0x0}], 0x0, 0x0, &(0x7f0000002000)=""})
mmap(&(0x7f000000a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$BINDER_WRITE_READ(r1, 0xc0306201, &(0x7f0000004000)={0x4c, 0x0, &(0x7f000000c000-0x80)=[@reply_sg={0x40486312, {{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20, 0x8, &(0x7f000000a000)=[@fda={0x77622a85, 0xfffffffffffffffe, 0x0, 0x0}], &(0x7f000000b000)=[0x0]}, 0x0}}], 0x0, 0x0, &(0x7f000000b000)=""})
mmap(&(0x7f000000c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r5 = mmap$binder(&(0x7f0000009000/0x2000)=nil, 0x2000, 0x9, 0x4010, r1, 0x0)
r6 = mmap$binder(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x0, 0x10010, r2, 0x0)
ioctl$SNDRV_SEQ_IOCTL_GET_CLIENT_POOL(r0, 0xc058534b, &(0x7f0000633000-0x58)={0x2, 0x8, 0x8, 0x40, 0x200, 0x400, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
recvmsg$kcm(r0, &(0x7f00008e2000)={&(0x7f0000396000)=@ll={0x0, 0x0, <r7=>0x0, 0x0, 0x0, 0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0]}, 0x14, &(0x7f00003be000)=[{&(0x7f000023b000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x38}, {&(0x7f0000d59000-0xff)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xff}, {&(0x7f0000f9c000-0xe3)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe3}, {&(0x7f0000523000-0x94)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x94}], 0x4, &(0x7f000024a000-0x3f)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x3f, 0x9}, 0x20)
ioctl$sock_inet6_SIOCDIFADDR(r0, 0x8936, &(0x7f0000c14000-0x18)={@local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x3, r7})
mmap(&(0x7f000000d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000000d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000000d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$BINDER_WRITE_READ(r2, 0xc0306201, &(0x7f000000e000-0x30)={0x54, 0x0, &(0x7f000000e000-0x54)=[@request_death={0x400c630e, 0x3, 0x4}, @increfs_done={0x40106308, r5, 0x3}, @request_death={0x400c630e, 0x4, 0x0}, @release={0x40046306, 0x1}, @free_buffer={0x40086303, r6}, @dead_binder_done={0x40086310, 0x4}], 0xca, 0x0, &(0x7f000000e000-0xca)="1225bd0ce6ffb6fa93cf990803ad59007904cf4b9e3e9f751ec47ac3d78c463c71d1cc332cbe58ac10d8f7d804b3a71fe6a42646114256e38e1a447e77ee7b5b5f1c97e00b8c8825dc1c49e0ddb38c1c4debf80fe13a47beb301fbc48a73ff1659ef4250e4f31cfd1b0c21e1a87daac317e82f472d4505fc504658004b7993de11233f60a90e1ce034b8a8ca176854e93fc8ab9d3a176b3176ceaa6264440169da3e1c391b9592da7da35c2da55de5e768150f513572bd99103a2c99afc207d122e62911a1c890d14aa9"})
ioctl$BINDER_GET_NODE_DEBUG_INFO(r1, 0xc018620b, &(0x7f000000c000)={0x0, 0x0, 0x0, 0x0})
preadv(r0, &(0x7f00009d3000-0x80)=[{&(0x7f0000f5b000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x68}, {&(0x7f0000b58000)="", 0x0}, {&(0x7f00009d2000-0xe7)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x2e}], 0x3, 0x54)
ioctl$sock_bt_hidp_HIDPGETCONNINFO(r0, 0x800448d3, &(0x7f0000cd5000)={{0x8314, 0x0, 0x7, 0x771, 0x6, 0xeb}, 0x100000001, 0x2, 0x4, 0x7ff, 0x7, "c2655e6663b861a87f4bef50ba77fb42e5bdd62693b49a3916886d4cacb5673418223d1971d85b78d47733f88a8e8cca0c323195ed301ad587d60a74e3658d674d0f392431d83c7a8cea5cf04cd7acc49ca78c6d299505cd297ec68da97b1e698011dea7f77675cdf79dc75e1e0e1304f86e4a72a2334eb16c0c308c53f21439"})
[ 50.681989] device gre0 entered promiscuous mode
2017/12/15 11:53:26 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
fcntl$getown(0xffffffffffffff9c, 0x9)
getsockopt$SO_PEERCRED(0xffffffffffffffff, 0x1, 0x11, &(0x7f0000af6000-0xc)={0x0, 0x0, 0x0}, 0xc)
getsockopt$sock_cred(0xffffffffffffffff, 0x1, 0x11, &(0x7f000085e000-0xc)={0x0, 0x0, 0x0}, &(0x7f0000269000)=0xc)
ioctl$sock_SIOCGPGRP(0xffffffffffffffff, 0x8904, &(0x7f00002e5000-0x4)=0x0)
r0 = getpgrp(0xffffffffffffffff)
r1 = dup2(0xffffffffffffffff, 0xffffffffffffff9c)
ioctl$KVM_GET_REG_LIST(r1, 0xc008aeb0, &(0x7f00000be000)={0x3, [0x1, 0x8, 0x7]})
r2 = getpgrp(r0)
perf_event_open(&(0x7f000001d000)={0x3, 0x78, 0xe3, 0x7, 0x0, 0x0, 0x0, 0x200, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3e31146b, 0x0, 0x20000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r2, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000011000/0x3000)=nil, 0x3000, 0x1, 0x32, 0xffffffffffffffff, 0x0)
r3 = userfaultfd(0x0)
ioctl$UFFDIO_API(r3, 0xc018aa3f, &(0x7f000040c000)={0xaa, 0x0, 0x0})
ioctl$UFFDIO_REGISTER(r3, 0xc020aa00, &(0x7f0000001000)={{&(0x7f0000011000/0x3000)=nil, 0x3000}, 0x1, 0x0})
r4 = creat(&(0x7f0000a1d000)="2e2f66696c653000", 0x110)
write$sndseq(r4, &(0x7f0000012000-0x2e)=[{0x0, 0x0, 0x0, 0x0, @tick=0x0, {0x0, 0x0}, {0x0, 0x0}, @time=@time={0x77359400, 0x0}}], 0x30)
mount(&(0x7f0000e76000)="2e2f66696c653000", &(0x7f0000015000-0x8)="2e2f66696c653000", &(0x7f0000014000)="70726f6300", 0x1000, &(0x7f0000eee000-0x3)="eb35db")
unlink(&(0x7f0000e88000)="2e2f66696c653000")
mount(&(0x7f000055d000)="2e2f66696c653000", &(0x7f0000ca5000)="2e2f66696c653000", &(0x7f00007a0000-0xd)="616e6f6e5f69736f6465666e00", 0x11088, &(0x7f00008df000)="8ec536c00883070e73aee2252a0be8b06cf4626b1e3d966f1fdd91c3949949adadd20c64924b3ff51c3c9e56f6a152a75759a404375079b92cd35ed3c472fd8ddd90d1b5b45bce0d212ca56752350367783a8e940b275190714e025dcf5d5e9ec6a81a3c427c7c2b724de5d8c9f12f8605d128c1d6754c86c294b531342e64ffd02dfbca")
getsockopt$sock_linger(r1, 0x1, 0xd, &(0x7f00002e7000-0x8)={0x0, 0x0}, &(0x7f00007d8000-0x4)=0x8)
ioctl$UFFDIO_ZEROPAGE(r3, 0x8010aa02, &(0x7f0000002000-0x10)={&(0x7f0000011000/0x3000)=nil, 0x3000})
socket$inet6(0xa, 0x200000000400002, 0xc0000000000000)
2017/12/15 11:53:26 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0xfffffffffffffffb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0x72e, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
lremovexattr(&(0x7f00008eb000-0x8)="2e2f66696c653000", &(0x7f0000171000)=@known="636f6d2e2e000002650046696e646572496e666f00")
r1 = openat$rtc(0xffffffffffffff9c, &(0x7f0000ed0000-0x9)="2f6465762f72746300", 0x200c00, 0x0)
dup3(r0, r0, 0x90004)
mremap(&(0x7f00009a9000/0x4000)=nil, 0x4000, 0x4000, 0x3, &(0x7f000046b000/0x4000)=nil)
ioctl$RNDADDENTROPY(r1, 0x40085203, &(0x7f00003e4000)={0x0, 0x46, "8600ed84ab6a687b737b6ed70db9653d409ace227c05e4bc356542a34cf29d79af2ad8203222711b3e1ade9bd23b893ba36f4b7c81ea773b0a55e9581b2c674b392d75961913"})
ioctl$sock_inet_tcp_SIOCOUTQ(r1, 0x5411, &(0x7f000075b000-0x4)=0x0)
getsockname$unix(r1, &(0x7f0000514000)=@file={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f0000fa2000-0x4)=0x6e)
mkdir(&(0x7f0000635000+0x43e)="2e2f66696c653000", 0x9)
mount(&(0x7f0000018000)="2e2f66696c653000", &(0x7f0000a9f000-0x8)="2e2f66696c653000", &(0x7f00000db000)="72616d667300", 0x0, &(0x7f000000a000)="")
chroot(&(0x7f0000739000-0x4)="2e2f66696c653000")
mount(&(0x7f000055e000)="2e2f66696c653000", &(0x7f0000a52000-0x8)="2e2f66696c653000", &(0x7f0000a2e000)="726f6d667300", 0x2000, 0x0)
pivot_root(&(0x7f0000a3e000-0x8)="2e2f66696c653000", &(0x7f0000432000)="2e2f66696c653000")
clone(0x0, &(0x7f0000085000-0x1)="ea", &(0x7f0000d09000-0x4)=0x0, &(0x7f0000362000)=0x0, &(0x7f0000f2b000)="")
chdir(&(0x7f00002d6000-0x8)="2e2f66696c653000")
remap_file_pages(&(0x7f0000825000/0x3000)=nil, 0x3000, 0x200000c, 0x0, 0x8002)
mknod(&(0x7f00000ac000)="2e2f66696c653000", 0x1000, 0x3)
ioctl$TIOCGPGRP(0xffffffffffffffff, 0x540f, &(0x7f0000d21000)=<r2=>0x0)
linkat(0xffffffffffffffff, &(0x7f0000f09000)="2e2f66696c653000", r1, &(0x7f00006bb000)="2e2f66696c653000", 0x400)
rt_sigqueueinfo(r2, 0x7f, &(0x7f0000d20000)={0x0, 0x10000, 0x40, 0x3})
socket$inet_tcp(0x2, 0x1, 0x0)
write(0xffffffffffffffff, &(0x7f00009c7000)="0c43dfe9037c3be496c5478bafd27b62fba94783a922e0ff5be24e9f27a92fd31052f883822ab2c20d0317c59c357d8c0259aceaee1bc9d9623526a4d5e48f6d9ef2d3f0d510b5830d47284d9d08f4ad8af3136a", 0x54)
getcwd(&(0x7f00007a5000+0xef4)="", 0x0)
mkdir(&(0x7f0000063000-0x8)="2e2f66696c653000", 0x85)
perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
dup(0xffffffffffffffff)
eventfd2(0x0, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:26 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$sndseq(&(0x7f00000bd000)="2f6465762f736e642f73657100", 0x0, 0x3ffffc)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x299aecbd, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x208, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r1 = inotify_init1(0x80800)
r2 = socket$alg(0x26, 0x5, 0x0)
getsockopt$sock_cred(r2, 0x1, 0x11, &(0x7f00006cb000-0xc)={<r3=>0x0, 0x0, 0x0}, &(0x7f000052b000)=0xc)
fcntl$setown(r1, 0x8, r3)
ptrace(0xd, r3)
getsockopt$inet_sctp6_SCTP_GET_PEER_ADDRS(r0, 0x84, 0x6c, &(0x7f0000203000)={0x0, 0xb0, "b930ca8232b4eddcead76d4b94d0830bd17395f7598e44cc4808ab5e64bbc59282aab922e75b800b09cefd481830eb10f6f1eabe4996dbd1811b5c830d3608fe0d7dc6fbd9617fa3593e99c48260e524cdbb9b8e1709006d6a3d9650e8b0f06611e5d8841ff789804de7b037ce91ccf968d8bc87cd414fb0dc05aa78ac364618bcbeec44a9db4f26c97ca8454210664b5bb94d9a8933addcb9eda1c46669ec1fa0457e9e817f432988de8a12a6664613"}, &(0x7f0000450000-0x4)=0xb8)
ioctl$EVIOCSABS20(0xffffffffffffffff, 0x401845e0, &(0x7f0000725000)={0x101, 0x84, 0x3, 0xffff, 0x100000000, 0x6})
ioctl$KVM_GET_PIT(r2, 0xc048ae65, &(0x7f0000730000-0x70)={[{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}], 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x960, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0x2000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r4 = openat$loop_ctrl(0xffffffffffffff9c, &(0x7f000030f000-0x12)="2f6465762f6c6f6f702d636f6e74726f6c00", 0x0, 0x0)
ioctl$LOOP_CTL_ADD(r4, 0x4c81, 0x0)
ioctl$LOOP_CTL_ADD(r4, 0x4c80, 0x0)
2017/12/15 11:53:27 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00007d0000/0x4000)=nil, 0x4000, 0x1000009, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00007d2000/0x1000)=nil, 0x1000, 0x7, 0x32, 0xffffffffffffffff, 0x5)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffdfffffffff, 0xffffffffffffffff, 0x0)
r0 = openat$ptmx(0xffffffffffffff9c, &(0x7f0000f43000-0xa)="2f6465762f70746d7800", 0x8, 0x0)
ioctl$TIOCTTYGSTRUCT(r0, 0x541a, &(0x7f0000550000)="")
r1 = syz_open_dev$vcsa(&(0x7f0000045000-0xb)="2f6465762f766373612300", 0x3f, 0x3ffa)
ioctl$KDSETMODE(r1, 0x4b3a, 0x90400000080)
r2 = ioctl$LOOP_CTL_GET_FREE(r1, 0x4c82)
ioctl$LOOP_CTL_REMOVE(r1, 0x4c81, r2)
mlock(&(0x7f00001bb000/0x1000)=nil, 0x1000)
openat$hwrng(0xffffffffffffff9c, &(0x7f0000d8b000)="2f6465762f6877726e6700", 0x3, 0x0)
mmap(&(0x7f0000000000/0x1c000)=nil, 0x1c000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = syz_open_dev$loop(&(0x7f0000c8f000)="2f6465762f6c6f6f702300", 0x0, 0x42001)
mmap(&(0x7f000001c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = gettid()
sched_getparam(r4, &(0x7f00007c0000)=0x0)
rt_sigaction(0x28, &(0x7f0000bd5000-0x20)={0x9, {0x6}, 0x8000002, 0x1ff}, &(0x7f0000af3000-0x20)={0x0, {0x0}, 0x0, 0x0}, 0x8, &(0x7f0000ae7000)={0x0})
getsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(0xffffffffffffff9c, 0x84, 0xa, &(0x7f0000014000)={0x23, 0x100, 0x4, 0x20, 0x9a6, 0x9912, 0x4, 0x5, <r5=>0x0}, &(0x7f000001d000-0x4)=0x20)
setsockopt$inet_sctp_SCTP_AUTH_DELETE_KEY(0xffffffffffffffff, 0x84, 0x19, &(0x7f0000005000)={r5, 0x81}, 0x6)
mmap(&(0x7f000001c000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$SNDRV_SEQ_IOCTL_CREATE_QUEUE(0xffffffffffffffff, 0xc08c5332, &(0x7f0000cdb000)={0x6, 0x0, 0x7fb, "71756575653100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xffffffffffffff0e, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$inet_sctp6_SCTP_AUTH_ACTIVE_KEY(0xffffffffffffffff, 0x84, 0x18, &(0x7f0000798000-0x6)={r5, 0x4}, 0x6)
mmap(&(0x7f000001d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl(r3, 0x125f, &(0x7f0000005000-0x4)="")
2017/12/15 11:53:27 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$TIOCGPGRP(0xffffffffffffff9c, 0x540f, &(0x7f0000f3a000-0x4)=<r0=>0x0)
r1 = openat$selinux_policy(0xffffffffffffff9c, &(0x7f0000eca000-0x10)="2f73656c696e75782f706f6c69637900", 0x0, 0x0)
perf_event_open(&(0x7f0000b3a000-0x78)={0x0, 0x78, 0x7, 0x2bd69fa0, 0x8, 0xaf5c, 0x0, 0xfffffffffffffffb, 0x10000, 0x1, 0x10001, 0x2086, 0x9af4, 0x8, 0x0, 0x0, 0x2, 0xffffffff, 0x7, 0x289c4, 0x1, 0x2, 0x1, 0x4, 0x2, 0x918, 0x0}, r0, 0x5, r1, 0x1)
pipe2(&(0x7f00006a3000)={<r2=>0x0, <r3=>0x0}, 0x0)
syslog(0x9, &(0x7f0000822000-0xb0)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0)
syz_emit_ethernet(0x12ad, &(0x7f0000a54000)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [{[], {0x8100, 0xfff, 0x1, 0x80}}], {{0x8af7, @ipv6={0x1, 0x6, "335b3b", 0x1273, 0x2d, 0x7ff, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, {[@fragment={0x0, 0x2, 0x4, 0x8, 0x1ff, 0x40, 0x1}, @fragment={0x5e, 0x7, 0x7, 0x9, 0x20, 0x100000001, 0x1}, @fragment={0x6, 0x100000000, 0x2, 0x0, 0x837e, 0x10000000000000, 0x2}, @hopopts={0x32, 0x232, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [{0x5, 0x4a, "06614617bd80a28313b91154d322b0d93801658c16410b21ac9157777281533bde56a9c1b2aa32e858407443c05e7bde7af971225df94daf6af8a6fcd09764d55bddec0f8f06a40e79f2"}, {0x0, 0x9f, "1a6f8c08d31d0f765d1ac9ce54ec5a8763fc53f6116e8804910263baaec27e1058452ab447b252d717889b79fbaba94e2894eed8c741efa3c82a929eb933a46e4ba1d737a9ee57f7a2d32dc58dbd103c530b429cd27c2a2384af30f1229149d006520cff143d9fc81dde9454f3bc433014a9bc2bc35a7e0e46f3ffaf957fdcf131a53b678ea2762b3191af7a1dff3c7469234b8e975f7b77029c1b1331ff33"}, {0x0, 0x0, ""}, {0xff, 0x11, "4fc514d0fd17b8284f05e5969b82a75255"}, {0xff, 0x1000, "957c595c834733911be98c24a8aa72a95db627092e8ff7ec9cd4055cde1cbe12789f60512f89800ce18e3c6130922c83ed12aa867e469a017c094b278442ed8597f871248393a31bd20cf5f47c0a10c97808797644583769a82c0ca36f68568ab15b0e7bba422ba572c5ff6731bd48b6b231cb195330da601286a835f98b777676870e7f2f15ae4398e11709cc85c120cd33739134396e72da6e77407518f5be4e9417f070b4cd805f7be25ea9436e0a7fbf1a06ec302ba2723695a5f62907610a026a9f07163ef0a28b069ae9de2affaddeda0e3013f9bb7f3ab8746ec7bb42e63fa503dcfcd0829994b48ba8cd2675c65b685461d1bd8986d4b09b85022e9252a3fd346d8edb41b5d1027b3c88c016104715a45ad9251757c99f7c13a0bb808fde36a08086947e43dafd3002d6113fc6613cfe380c3e9296d59760ac394c0fdac866057e0b91a062c22009a726c6003ea84d4547336ddc1d37990c36872cbc5acf7febf7989315c052eebe4ea251aeca259fcfda3521a59ee3e85d607f6db2af592d9cb1b805353dfe95373b9e99f0685b355eb1ce301dd0a0b5351942e2dbea9c8860ecbc9d6bc5d180e5c97aaaf8210843d96f810c12ab13c295b0805af7a6f9bbc5b03b58bf914afdd7949af232f3a9bc9e447662dfc8da34f4f2e180fd2c726b971f6c6605fe1c0c359f924b6a72d762374dac02228f99a9f22a70ea05091a4f259892e56646b2980a199449229201397c115fc0807d1c60a4f168b952c68a6414e0ce434862e661fff88ba3579ca31035d3bf4e219bac0219499fbd80326426c10f88d1526294ec4f89fb3f32a5764a0d58d4c0ee1e114afb275a3d5b7c9805d18c7bc588c5a95b41b6a8318a7382d9ae7bef852feac5aeccdb0db4c94e2b77ce585a410333db4519ef8d035ac55adfabe34bb9823e89251a7a292330e9da80b9f254ea022ac595313f290c5be46412ccb823264698d175ef4e1f055b542f83fd1c9a267fd8ab7bf452f8370d2872130ff68b9b6a453980f7620c1168b90228ebb3f2bafac1e0e4007ab3024e31a004a0d18edf4174755c824e945099ff89c7d3ec1b2d619d71f75235997a6ac424213b56c335579cdc578e3421f55325fca141934f50630c83b749831b676631a0999528da8ac2821b5ad0c6b4cd899741a6ec31a442e8b65037aae7701483dc9bb88892cd125827132f7252b88e91d5a3aab89c331575bf208c8783e8704da2923c5fabb2921d5265266fe27129c068a9235a34106dc809e7f5b1a3ec4c7a2b8b29b0da96ecd8d9ca3cf2523c9cdd222c5f5eb774ec1c455f92cd40402a62d9361fc8ed6031083ac3d1cbb86be6672b63500a654b39e6988790c3919fcecf81f3ff5d323e3fc562c108db73c0abe667550ec4c7fcc0d968db71bb95fcfd79c4ef60d9bae4108a9b7615fd435d8feceab900f05d6ff9a512f45b25fcf88d71a243633654f92ed9756007a8d29090206380ead277ae83c7a29ab3ec292654e9fde19ae5b7f52e193e4078a92b031994d99d38b8028ee088df8f50f962121f3f60f979f49934c7d2815f42611ad2751e9e2bc1511a7733580abf1e49069bdb21930e20bc185db492921fc57ef03d3b36d807a71d2deefaf503b4651efb85c9c56478def719833109740c013f50606c7fde514c3938ace94f6cc61ac5ed916e42536d3ab83277620b2d905aba277d9ba7fade07ac43b3e9f7b196058874eaf659ea0412cbf9ea7b23ac46546bd045691cfaf8c158b8744273a0a7daf868761a71404600f110817eff628ef5ebe5b92ce75444a9532ea5e63b5030a7552750b87351fc86b91483b5927787e4a9450154e2a1254080d17b780684f0545aa10a9eb8927690e05d1218c900229215f93a8f0eeb25cc4ed772eff0f92241f25d2d514b34dd3d0946e2d054fd3b119f8eb3ac1fc928cd650fc696654379b178fb953c3a42c067171450cfd035624e526bfbef001e344fb30b69c0c0154969489a58a46cd7719dcff8b8b17d115e842bd3c80e60070b65109c5c6ce759abb7e8af65e4491b96dade064b0410639c396c7e7c2343e6fe26d6ec47ed222bba17dda398cb3e39373db35ed6d03b5cd705e7f99daa5e020d5e46dc67b2850ba2f7f7571dc095a824a99cefa54c1c3ddc992c3405543d9ea0a5b866fc9ec45ef45c362c0f1c051d730d96b35fad20ff21fc60c10db7e3d6a107eb054d6a4d19074b764913d1d5d5a18373be1040dbc78dccc81a4df0050da13b58dd1eeb81a572de2711f6b453fe4cfe8733e8fc8b660f208450ec1a3c0535ce9b784087e34858610e971c244e622c5f215f3d9f0cc54a2184088bb6a0bb2c92dec69817726ae84f7778bfe5ece1b91907a83a82fe018ef3954cb4ec7d090f2aa05ed840900d6258e63ef2086e5a80fffe45632eed469b0dd2bb25838375dde8f5563aa40fcf81e63f085a9db65206bb3e33a0da8042f139081bdecea346e1556ba159ccd3f0c2f6006cc2630ed7e10578ca0e7026920ce14858c49c9ee7f45de148d8f4b9e257a287bea247a8aad858d730c907cc54b8af83b4c7b617e4252050499d565eb604a9704ab767a2e7e86d01d5807116946e721bbcb330ccce97f93ce80184e082a285353f34be314c0e924bd95c1d4e109b5ec3e13edd0898a79f2d2c19234cbc0e6447d5085f6b388ceee31e2ed3fe6a2d02a710ebfec674a3ac309dd74424fd1aa5c28ea74349174b0df0f1df611894fdfe48b107ced012ae08f179982a7c21428151c29eff215b471871832e2c3ecc1f01e69aea11d19627e60ec5dbc87267f8140867f85fc644ddf5fd45250ad9711dd4513bf75abbeaa1b9c6a8f461f0c9ac3ad460bf4ba614e4b04d2352d7dd3174edc9c97a236a193df2a1d436f6c9d149f591ad3d0eb835c1d3632c4de858561bc42004e2e62da7d1af441f1eeb33876c96521b7f06f04f22d87f2719d8b336bceba30ef5166ab0462f496888067cb88c65ca387c48d8f07734e8e1351dc1bc1ccfba3a93715cd1f1c6f84877207c426cd18ad3fd44fb7ca53d538cd93a236eb86f25558cec360d4077f330887bed05b5a34bbae1c1d468f7166b41ddb20cb1c9e3bf0f7fac51ea52a3ea0edd61078b7324103f665bcc1c10353bd97623918b42c7d13ddcda05562ae291b20a1175972d2d9903be3873fdf549454c65e78ebd887c1d931e981af3d7bcbb955d9775c1c0944d1120e43c7503a961012af3627ebd4186884c3d55b53e850f2664e2e43f895b2bbbd1e97deb193b370503243c65de1bb0b630c183961db6299ed15cb8da3c5bcc7aa29838346210e3e5fa9e2e24c074b131ea224dd1a48d7ad8f3ecc9752cbc58667104ed4bb5befa58d9ae988999d4be8fd51a2fcc4d597cc1d6ee00195ea48d5d823c1c352ac8f7c14f447434f1f085528a1529219df686f0e338f0271829badcbc2fd31f7a424d74a19e105b78d15ffeebad8f6b6133fe6cc5be35ae37fe22f3ceb0f85f7c9e7d472c2b71a2e936064f1d6ff373bc3e6154fdc2df9fef899cd99d471391440d00bf85097ca399d43d840285ad16aa26e61c9089e5a9624b0bc4d767b06500c7ad9af7762c72c0094655dff1f6eb7df423fa2ca614a4000e0325886d999cceb0083d53a3ae034170f516cca280a4d1270112cd758b3579e783a815f705608b1afc4fa9aaced5ae8d97c3d55e82daed29b8d746ea67da5e94d4707c90363282f1b1ccb0d11e3d63f586d389dc1e2b3e5793304ea27fe27e2a81fc9d8d50f1a0b186c9a92e441bdd7fa97043b0e4ede46ee815ad83cbe0cb440b04597a644bfa1c1e9fc9976ead12bc37aff226df1a4fc4aad57a1d579cc14309dc47c39e06a04a15338a877a527df139b6652b81e92675e6f567a86ede73730a049318ec99b00fca3b8e2031980e15de29c6d3545409373e893b720f3246e58f1f45d6eda42d1567c3cf9c3aae8c215b8a7028510209ebd68bfbfe019f97d048adb0ab0d0720b8ce991dbd32566bd14ce0ff8dc4c47e6062134fc83adc31da73b44e40a076ee167366fa5c3213b1967aa14130eadc1d46b059e71e6c8f6afb9fb7a712d386834f2ae2caa869251be51d21aed14675b7911716af9511a7998fb057bc06c73767755c96548b085efe2fe1b2bd21246da7c94f572661088077aafa4b087be446fec754e2b3dba88b547c75f627a64b08d974f5118c920d9a6a6b22a9b4e07295d8491c838412a7f0717fd2dff67790eb601c0beb228aa0d9f70b4ebbf38160acb21e363539dcdd60cef9c69419bc3989903700ae737f474ac1c8f19b5899f3cf9657abe0284bcd8703a6e47acdd5424fd82c812c81054a71adaf152a3a6888cea0863202b66da0ebd69d1f651ca41eca45820dcc5cfd5d22e008abe928131f08d17f1fe71ccc6cd4b16f5f763afc564a9cd43304efdf06945fbc5b5209f196eba4cae1a7d013912c98b1517ea99efd507ba6495689df4d69331f0aa58f476d1426c0cf6ab95e9852188ea57dfa3dab995f68882a0bdfc0824582d8f7aac382af88a319f801f437b70e0e6dd0a98b55d26fb69e9acd1bb5072029edf1875ed9cefa8a40a5e3aad0708ff03eab86d20bb0ed6c7a6b2603f5261bf37b6f6d4668309de6e6b51967a67e59a07b916cd76f441b9a33e4b904bca8a4dafe1f0e7e0733a5aed6c945e12d5a06f878e4c138b44294402d26fe7fe88ecb0d822c3e6bdce29aee600cb4fc57c862e7657a55bc52af43877b9aaa254b145fe0a2b37e083ecfd90fbd9cec8d966c37bf3171bd7d67294010095b5a2bfeb2ba408ea54c28a1845f049803a1298e93b6bb47cb7b5bf49fd67a56dda6d1b329fde15e022ab6a51d084a3f6714bb36b93b7fff0a33530bec7488d31f33f43aca2d8c43f4bd9bb399b0d3ce83873df37218c0241a27949f9ff638fd00176d84a2b3adc615e27c12d9219a9969433640d1ec3d4b9bc2cdd4915f12a1ef3af45269004048fab24d0973254902cef62e62f355fda6399091b410faed3d0d1722e71d2853ec830d501d6e0b6f7de6bf618f112419d025c65a86e1a89bc0635c537b97c528a22cc533cd8d8cb0c4b139a570590e9ded79a3cf573cffa5d9829654d64fd3b1a258fcb56805cd7abdb47687851a0e2575bb70b891ce06d9be301b34d75734295a8a0bb04cfd80ebf031a727b202599ebb5c7a8f7779b0e1311a08ec9b3c42cbe5813403299525097c0c4a46bd8ac71c467aa64980ea9f15169b6571dd17c1e669271d535bdd6c9470efeb9fc8eb3a8c027df014e5506ee3d7bd638dd2532f74132d0cbd7f436ad7dfcd14a99a1c53042c6fb3dfcd8e7f6bf1234991a074f0f6e3dae330e1fa512e7d5a4dd3476af8a5bd42385ee768dbae740daeb6b1a8752ef450fc12403cb314e63f024ed9f62c9623950f62238d24aa0a4a017568b03b120b58839f28816be840a30d2cc40a8703d428ffd1e3baf9061bebb52ecb8c4d890d5ac00cfff522e65af3e93cd32fef4e420f2f6bfa84a0015e76b833302af40c44833a77ec377cdda30411488fdd50ad0d1cc2bff3e03ead12eeb18fb67d10dbcbfac75671116810eee51760b4fe23a8453a3e87b36d1ca1a32732965b1c6b69d0c483e4185afa5db20329fbdd15d7f35826a4847c9cee75f0ca1aea52822cc8324ea59198455506e778e7f120880e76408e88005c56bdc0b4859fc8d297feb206562658fdd6d8bfd305df804adbf4f000172eef1d5682244db14f889e74f63b9a7bddebf8973baa31fb4ba228c96999491be49bb2"}, {0xcb, 0x8c, "a4f2ab0612213c4427be144d81424754ee86aece25573088930dd87b976095c44acffe877609440904fbd5121a18212189f3c39eeb741cfae260f37115d15afc83dbd2505f4dd905f31de71ed748445543c5320bdec05894d23c40ff578ce05506f2dad350904c8091035e4b9422e9c41bfd546ec91f9270b74193843aedaf87afc60041efa78c81e7d9561a"}]}], @dccp={{0x3, 0x0, 0x4, 0x1, 0x1ff, 0x0, 0x0, 0xe, 0x7, "327d63", 0x7, "97f2cd"}, "21e825acde1d0b49278621ef64822e6353f3f87492b296825f3acdffcc5c529ab4442dac9fa7429decee5b3877bd970cc25d171e6a8acc89eaf31439511774d801f8b98b8fc33c677b136894891ef5573e7cc755d964df1c0e547e29a747a34490d0615fe6e0afbbb018e15dde22b6374bd16091ff075181b71168264fdeca8e6a081237e65d721fb7780983c8cbc0974f7d43bfb12cb1d00ec89ff5c0eec78692a771e2b282dafeb0fd68"}}}}}}, &(0x7f0000779000)={0x0, 0x3, [0x91f, 0xa63, 0xb42]})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f00001f8000-0x8)="2e2f66696c653000", 0x0)
mount(&(0x7f000000a000)="2e2f66696c653000", &(0x7f0000027000-0x8)="2e2f66696c653000", &(0x7f000000c000)="72616d667300", 0x0, &(0x7f000000a000)="")
mount(&(0x7f0000037000)="2e2f66696c653000", &(0x7f0000c50000-0x8)="2e2f66696c653000", &(0x7f000002f000-0x6)="72616d667300", 0x148000, &(0x7f00009e5000)="")
lstat(&(0x7f0000f40000)="2e2f66696c653000", &(0x7f0000508000-0x44)={0x0, 0x0, 0x0, 0x0, <r4=>0x0, <r5=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
pivot_root(&(0x7f000005c000)="2e2f66696c653000", &(0x7f00007ad000-0x8)="2e2f66696c653000")
setsockopt$inet_mreqsrc(r3, 0x0, 0x25, &(0x7f000017b000-0xc)={@local={0xac, 0x14, 0x0, 0xaa}, @rand_addr=0x20, @multicast2=0xe0000002}, 0xc)
r6 = creat(&(0x7f000016d000-0x8)="2e2f66696c65302f66696c653000", 0x2)
getsockopt$SO_PEERCRED(r6, 0x1, 0x11, &(0x7f0000271000)={<r7=>0x0, 0x0, 0x0}, 0xc)
chown(&(0x7f00003af000)="2e2f66696c65302f66696c653000", r4, r5)
mount(&(0x7f0000bbd000-0xe)="2e2f66696c65302f66696c653000", &(0x7f0000917000)="2e2f66696c65302f66696c653000", &(0x7f0000467000)="78667300", 0x1000, 0x0)
mount(&(0x7f00002ba000-0x8)="2e2f66696c653000", &(0x7f0000cbf000-0x8)="2e2f66696c653000", &(0x7f0000dcd000)="72616d667300", 0x80000, &(0x7f000002f000)="")
mount(&(0x7f0000f28000-0xe)="2e2f66696c65302f66696c653000", &(0x7f00002fb000-0x8)="2e2f66696c65302f66696c653000", &(0x7f0000239000)="007609", 0x1004, &(0x7f0000a06000)="")
accept$unix(0xffffffffffffffff, 0x0, &(0x7f00003ec000)=0x0)
getsockopt$inet_sctp6_SCTP_GET_LOCAL_ADDRS(r6, 0x84, 0x6d, &(0x7f00000ed000-0xaf)={<r8=>0x0, 0xa7, "3d358f186e2f0c0c068dd65d4cb8e5aa9799372dc1745c90777be28e95561f34c39d3957a41998a19c2d9e17cee9bc909fd8540f4488e479df65957d7883162e3658d63aa187fdeb0a4cbe2d3397ada932ed688bd93d68f762a03ef1a00c2070ede433a0cc2b84e3efa0aba8354ee3918f90db73e2991d7ac50461943af7fff262311b952b4f53dd08c44413f5a372c00b33f7fff2c4603afcaba8461543416bee24a85166e490"}, &(0x7f00000e0000)=0xaf)
setsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(r2, 0x84, 0xa, &(0x7f000051c000)={0x5, 0x9, 0x200, 0x1, 0x1, 0x4, 0x9, 0x5, r8}, 0x20)
tgkill(r7, r7, 0x5)
setsockopt$inet_msfilter(r3, 0x0, 0x29, &(0x7f0000c3e000-0x30)={@local={0xac, 0x14, 0x0, 0xaa}, @broadcast=0xffffffff, 0x0, 0x8, [@rand_addr=0x80000000, @multicast1=0xe0000001, @multicast2=0xe0000002, @broadcast=0xffffffff, @empty=0x0, @local={0xac, 0x14, 0x0, 0xaa}, @loopback=0x7f000001, @multicast1=0xe0000001]}, 0x30)
[ 50.711501] binder: 7369:7371 got reply transaction with bad transaction stack, transaction 35 has target 7369:0
[ 50.721983] binder: 7369:7371 transaction failed 29201/-71, size 32-8 line 2762
[ 50.748717] binder: 7369:7371 ioctl c0306201 2000dfd0 returned -14
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
futex(&(0x7f0000004000)=0x0, 0x0, 0x20000000, &(0x7f0000726000)={0x0, 0x1c9c380}, &(0x7f0000001000-0x4)=0x29, 0x401ffffffc)
r0 = semget(0x3, 0x2, 0x400)
semctl$SETVAL(r0, 0x1, 0x10, &(0x7f00000de000)=0x1)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e2, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x6, 0x0, 0x0, 0xf72, 0x7f, 0x0, 0x0, 0x0, 0x81, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xa7, 0xffffffffffffffff, 0x9)
pipe(&(0x7f0000738000-0x8)={<r1=>0x0, <r2=>0x0})
bind$inet6(r1, &(0x7f0000bea000)={0xa, 0x3, 0x800, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x100}, 0x1c)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x0, 0x0, 0x8004, 0x0, 0x0, 0xf72, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
openat$kvm(0xffffffffffffff9c, &(0x7f00001ff000-0x9)="2f6465762f6b766d00", 0x80, 0x0)
ioctl$KDDELIO(r2, 0x4b35, 0x81)
ioctl$KVM_CREATE_VM(r1, 0xae01, 0x0)
ioctl$sock_inet6_udp_SIOCINQ(r2, 0x541b, &(0x7f000074a000)=0x0)
r3 = socket$inet6(0xa, 0x2000000000001, 0x0)
setsockopt$sock_int(r3, 0x1, 0x26, &(0x7f0000faf000)=0x3fe, 0x4)
setsockopt$inet_tcp_int(r3, 0x6, 0xe, &(0x7f0000709000-0x4)=0x7, 0x4)
bind$inet6(r3, &(0x7f0000b8f000)={0xa, 0x0, 0x7fff, @loopback={0x0, 0x1}, 0x0}, 0x1c)
clock_gettime(0x0, &(0x7f00001b6000)={<r4=>0x0, <r5=>0x0})
ioctl$SNDRV_SEQ_IOCTL_SET_QUEUE_TEMPO(r1, 0x402c5342, &(0x7f000030d000-0x68)={0x0, 0x3, 0x7, {r4, r5+30000000}, 0xfffffffffffffffa, 0x6, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f0000000000)=<r6=>0x0)
personality(0x8000000)
ioctl$KVM_CREATE_DEVICE(0xffffffffffffffff, 0xc00caee0, &(0x7f0000001000-0xb)={0x3, <r7=>0xffffffffffffffff, 0x0})
sched_getaffinity(r6, 0x8, &(0x7f0000a5b000-0x3)=0x0)
mkdir(&(0x7f0000f48000)="2e2f66696c653000", 0x100)
mount(&(0x7f000000a000)="2e2f66696c653000", &(0x7f000000b000-0x8)="2e2f66696c653000", &(0x7f000000c000)="72616d667300", 0x0, &(0x7f000001c000)="")
mkdir(&(0x7f0000025000-0x10)="2e2f66696c65302f636f6e74726f6c00", 0x0)
mkdir(&(0x7f0000915000-0x10)="2e2f66696c65302f636f6e74726f6c00", 0x20000)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
symlink(&(0x7f0000747000)="2e2f66696c653000", &(0x7f0000001000-0x16)="2e2f66696c65302f636f6e74726f6c00")
sendmsg(r7, &(0x7f0000256000-0x38)={0x0, 0x0, &(0x7f0000d42000-0x60)=[{&(0x7f0000f8d000-0x6b)="a78a11b700e80a7ffd7f2cf0a3ea78e2016eb0b4339a059196d8988665e4d721ad08e697db52f2122d99f88430b9a718392303bf98c399c266ae9400930de8a90a1cb2fd1f5eb22ecb88ea21b15ba3e85d0f216011e7f859e238a8e7242375c36ded438ee42b02803bf3c9", 0x6b}, {&(0x7f0000fcb000-0x2a)="150a2f0202d2c5a015bda5d1ee7731b694f5312e3c63a7eef122977ae43f91911f92f82124d4c88ac7ee", 0x2a}, {&(0x7f00007b6000-0x78)="d2123f9f96b0f8c112a70d623e92dcb52c123b0d073efb17a6e863b4da01729041dfb58d459c12a255f53c6a20af1f477e938361faf687cec106a45b76e6455bd34fd183dde9c95af97b7066b5683483cf51b229ded67c6b41665554cf85dbf97a8f779284a626b834bf91a87510c1f512873035ea53bdbd", 0x78}, {&(0x7f0000d53000-0xfd)="dbb5a902489d6f1bcbf0f32c6d7fce8a0873f073d3562e0400366b5952098b0cb7e1857c6cbd1e292ebe3f298f1769c28398844bd96ce0a7dbbe2bc91d116829eef9fce5ead80e0d2e6a9d6c824383e4f2156de422138fcffbad7ca0996f8f0abda947bebde143aa458b92efb03c4fa615b03b6092f9f86b99eab9b808c8546c524dea4553a62f8468a28474f22f0a8527802bcf13e979132a9192ae8a4f1c9afa63ebaccb9dfbe8f040271308a54fcf607a8d2c63646f8ffa016a4149c2a300b5773f5ec68d4cd244f97d95be6d114a870f3c949232102460d935c008f018c74642c77c97f5b753cb272253eb1a32639389d1f7dc7a6a3e6c6b1cac40", 0xfd}, {&(0x7f00000dd000)="308542a48945e5e96a739ce177c9e625f5f296b2e0b84bdf248223809f7343af4531429f8c4e00a35803c3665a1afafc28aeae088c371c688674a857d4690ea93b4cc1775fa55aeb1b6d07894a2a5ca9b01984de9fa4070223d2661aa491fbfc05c07506a1fc95a501d05216a843e1ad0657807a0611f4209283be24f8b132623880f0ab273621d5da69636c3cc9626e4b563b9f8967a14a6b9916a5cdf214c4b9b33eecfa4e", 0xa6}, {&(0x7f0000822000-0x84)="6844c4106d1baecd6fc18906fecce5f61c8085f46fbf5ba0c8177eeb2302bc2d023492d50a377feb62155c0ce8d99d31eab1c25a227c3328e308e6738043234682f57d725403899f33b26a720f8608c61ba5f4d468878521167de0c16159176160b4e93de92a917f382b5806ec8ec5e98227d29d35f778cf7f7c3bb2c6508b378cb42242", 0x84}], 0x6, &(0x7f0000816000-0x588)=[{0xd0, 0x101, 0x6, "33542e456bdbfa2feab818ca7c95da713615341d7a29af7148056400d45ef24e889fa990973370a2a1f12318826fcf5bee7a06d868eef80b5b5ece8ac95e19c475aaa8c4511dafaaec81a891367e3ca4609886e562ebf2ecd28c5a36c64758246548cef3040dcdaf1dfa98e360f9e7cd430de7a7cbbef38d948e26ee0bce2bfcf278b44d1bf6ae09349d3230c05502b8540b610137a32cca109954817c1b5eddaf70cbb8e180db08a8b61132ee293566ad3b0d9a78220b923fe07d"}, {0x108, 0x118, 0x9, "9185182b58957c1f8201cbebf4b1107f4b03aa1bba61162b289cb0b7de527d25d69baafcd7330a370f31c72989f4e0557073ce40a3fed2f7e9bf2c572562e4431be45213df37dccb248c66ed2671c09a62181cabc48c776e70ad1b1c15c05a1a06e49c4b53c0cf4b26c95188006957f470bcb59323406566c8c8a012fb7bc9067bc1f2bc71b679c886f20dc7cc02e1c52dd7925802c1ebb63a71cafd1cbf3de0d07e58fa751cb7b6df7661dd0205ecd5f528df34c9c28c93df65b95dd3e40a7c4dcc8f45a43dd2079b1225ac77f88aa86dad796c2d2c4f6493f8d5f2647b4283d6120d8f374d63b7f0c872997d38d76c034c"}, {0x68, 0x10e, 0x88, "a78a2cf496278ffb84a48ec684cded0f47112bf05e6a0f48d91b708f425d6bb30c30fca34dbfd71eeff4ec365f1c9b1af3ae890eaf39dce689f665598b65f00d92da53d6b49614c3987b444bed49cc8bd7cd57"}, {0x48, 0x109, 0x5, "ab118804a45281fbbb307e0c7875b5579b3e9a554119610695aa86ce7a926c801d4220087ca40abac047ed20d762a7fb2a36b02b"}, {0x20, 0x0, 0xfff, "53faae401cfa474da127067c101a"}, {0xf0, 0x3a, 0x4, "b80a80efa1ffda1d8b15d2c4ea7cab95840866ca8025edda0e03afc0a8d7d9bd726b46d7eaa472c79b66b5d69b5620bddbc61d5865eed6be85e3cf9d368aea61a46ec9fedf1b918329ff48ecd7e24b2cdc79d0fc37eb46580920de7520813a4f55eae824bc1e2272b05df180bf65c4942c219e679eac7a09dbc691fbb177150d68a0cf18cf7173707108943dcb0be5ac8f0ae9b8e192f8bce48f8ef2132b1a2c5275e147d5f541f1e4626a8dcf54afca5fdc6bcc45aeaba4aeb30097063915239d84a5d7eadf23a49d5107521decd367f0fdb19182b9d8b2a19e4747cc"}, {0x28, 0x1ff, 0xc2, "0f5a8f3dc0884efce17f2e9ab9e7d4b2dc94a9"}, {0x110, 0x116, 0x267, "c16e6be49da7cb4361ce254355665ac453d4a00541bdf9edc18a53a3d7a3c1bb24a1e039345e0249a11e3b4d8d737da39d38e5eab258755a27d98df8f7adcdb9f6c8cb3222c7c474fcd24863a06026eeddce2022045904c6f978d9386fd93b49058bb79d21792ec8f9f02a0ec3839ef8b7ef6d02da9a0b95cbfbdf9dd49c845f2cb998e47aad5e4f1cd42a61397a2dba04e351afdc25da66573c1eb38c6c0245bbb64721e99c71425999d0b76830589d1666dbbabd477a141ec91c34f1106c4a126a12c6eb447df5dad410dafd6da26d119b5c75a0378e770cb03e0b2d0437545eef3ca7c9139ec58368361a39b0f40c34e067ad302ad9b7d4"}, {0xa0, 0x10f, 0x9, "64963cdf437e3de0975302873adbd07279482d99bef43ba66098876241f7df5bc688ab1ac523324fcd0d54ecd298fa4daea32307fdaa2c8e473cb3999ee4858611b9d58575b340d90ddaafe10ad380d6b21269c34e195e5d35644aa39a72532888ceda2ab3d487dde72f821323c2fe23e3f964d33bc08b90c39a1ff41874cb341f3300f96b8a81c26d71d20e4a8d5e07"}, {0x18, 0x11b, 0x10000, "30bfcb7fd8"}], 0xa, 0x4000000}, 0x1)
umount2(&(0x7f0000117000)="2e2f66696c653000", 0x8)
rename(&(0x7f0000b95000)="2e2f66696c65302f66696c653000", &(0x7f000044c000)="2e2f66696c65302f636f6e74726f6c00")
unlink(&(0x7f0000159000-0x16)="2e2f66696c65302f636f6e74726f6c00")
ioctl$sock_SIOCGIFCONF(r3, 0x8910, &(0x7f0000090000-0x10)=@req={0x28, &(0x7f0000a08000-0x28)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_ivalue=0x3ff}})
2017/12/15 11:53:27 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket(0x10, 0x2, 0x10)
r1 = accept4(0xffffffffffffff9c, &(0x7f0000001000)=@alg={0x0, "0000000000000000000000000000", 0x0, 0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f0000001000-0x4)=0x58, 0x800)
r2 = syz_open_dev$vcsa(&(0x7f0000689000)="2f6465762f766373612300", 0x100002, 0x8000)
getsockopt$inet_sctp6_SCTP_DEFAULT_SEND_PARAM(0xffffffffffffff9c, 0x84, 0xa, &(0x7f00002ad000)={0x1, 0x80007, 0x1, 0x400009, 0xffffffffffff2711, 0x40006, 0x6, 0xffffffffffffff80, 0x0}, &(0x7f000078d000)=0x20)
setsockopt$inet_sctp6_SCTP_RTOINFO(r1, 0x84, 0x0, &(0x7f0000001000-0x10)={0x0, 0x0, 0xbc9f, 0x3}, 0x10)
setsockopt$inet6_tcp_buf(0xffffffffffffffff, 0x6, 0x1f, &(0x7f00003fb000)="44bb8dbf5b1e4e304af95444648df60bbe986c563619a0296d0be9d7395f00203521f2ef9c7af390c338d6f09e4bbe9fa52abc8e248fcc469fa026d24bc08eb62fb5e1765c63a2174a0000004099b20000000074de097f66d69388729d509a1d5067a68cd058da3f69fc619f335462517a1a3af2ad05e1d71ba4ef58e846451bd67beceb24f4f087e4f1a3456947f7fb45fa3c00f60cbe64054f94febafadef92027ff1021027e8a314621b4c15e3b52e2cc63e4fb5021638ee3346efd2fbd6882579834dca7da4a1636055f93de5fb4a9296109", 0xd4)
ioctl$sock_SIOCBRADDBR(0xffffffffffffffff, 0x89a0, &(0x7f000097d000-0x10)=@syzn={0x73, 0x79, 0x7a, 0x0, 0x0})
setsockopt$inet_sctp_SCTP_RTOINFO(r2, 0x84, 0x0, &(0x7f0000982000)={0x10000, 0xc000800000000001, 0x3ff, 0x1}, 0x10)
read$eventfd(r2, &(0x7f0000f47000-0x8)=0x0, 0x8)
r3 = socket(0x11, 0x802, 0x8)
setsockopt$packet_int(r3, 0x107, 0xa, &(0x7f00003bc000)=0x2, 0x4)
clock_gettime(0x1, &(0x7f00003c1000-0x10)={0x0, 0x0})
write$evdev(r2, &(0x7f0000306000)=[], 0x0)
getsockopt$inet_sctp_SCTP_DEFAULT_SNDINFO(r0, 0x84, 0x22, &(0x7f0000d00000)={0x3f, 0x209, 0x7, 0xfde, <r4=>0x0}, &(0x7f0000552000)=0x10)
getsockopt$inet_sctp_SCTP_DEFAULT_PRINFO(r3, 0x84, 0x72, &(0x7f0000cab000)={r4, 0x5, 0x30}, &(0x7f0000b34000-0x4)=0xc)
ioctl$fiemap(r1, 0xc020660b, &(0x7f0000fe8000-0x20)={0xa, 0x1ff, 0x5, 0x405, 0x0, []})
getsockopt$sock_timeval(r3, 0x1, 0x0, &(0x7f0000219000)={0x0, 0x0}, &(0x7f0000913000-0x4)=0x10)
preadv(r3, &(0x7f000006d000)=[{&(0x7f000021f000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x32}, {&(0x7f00009f1000-0x83)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x83}, {&(0x7f0000496000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x8c}], 0x3, 0x0)
setsockopt(r3, 0x107, 0x5, &(0x7f0000001000)="", 0x47e)
getsockopt$inet_sctp6_SCTP_DEFAULT_PRINFO(r0, 0x84, 0x72, &(0x7f0000c74000)={0x0, 0xe262, 0x0}, &(0x7f0000baf000-0x4)=0xc)
syz_emit_ethernet(0x36, &(0x7f0000926000-0x3e)={@local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, @random="4c6112cc15d8", [], {{0x800, @ipv4={{0x5, 0x4, 0x0, 0x0, 0x28, 0x0, 0x0, 0x0, 0x0, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, @local={0xac, 0x14, 0x0, 0xaa}, {[]}}, @tcp={{0x0, 0x0, 0x42424242, 0x42424242, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, {[]}}, {""}}}}}}, 0x0)
r5 = socket(0x10, 0x2, 0x10)
write(r5, &(0x7f0000a86000)="1c0000001e000720271622081d000000010000140000e4ff0400f70000020011", 0x20)
close(r5)
write(r0, &(0x7f0000b72000)="240000001d0001000000000800000004020000fa8c00000000000000f7727f0001fffffecf", 0x25)
r6 = socket$inet6_tcp(0xa, 0x1, 0x0)
setsockopt$inet6_buf(r6, 0x29, 0x3b, &(0x7f0000470000)="0600", 0x2)
socket(0x7, 0x6, 0x7fffffff)
[ 50.780261] binder: release 7369:7371 transaction 35 out, still active
[ 50.787033] binder: undelivered TRANSACTION_ERROR: 29201
[ 50.796169] binder: send failed reply for transaction 35, target dead
[ 50.807370] binder: 7369:7371 got reply transaction with bad transaction stack, transaction 38 has target 7369:0
[ 50.818230] binder: 7369:7371 transaction failed 29201/-71, size 32-8 line 2762
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r0 = userfaultfd(0x0)
ioctl$UFFDIO_API(r0, 0xc018aa3f, &(0x7f000000a000-0x18)={0xaa, 0x20, 0x0})
ioctl$UFFDIO_ZEROPAGE(r0, 0xc020aa04, &(0x7f0000ff3000)={&(0x7f000090a000/0x3000)=nil, 0x3000})
ioctl$UFFDIO_WAKE(r0, 0x8010aa02, &(0x7f0000799000)={&(0x7f0000b0c000/0x3000)=nil, 0x3000})
r1 = openat$rtc(0xffffffffffffff9c, &(0x7f00002db000)="2f6465762f72746300", 0x0, 0x0)
ioctl$KVM_HAS_DEVICE_ATTR(r1, 0x4018aee3, &(0x7f0000a49000)={0x0, 0xb28, 0x2, &(0x7f0000c30000)=0x0})
ioctl$KVM_GET_MP_STATE(0xffffffffffffffff, 0x8004ae98, &(0x7f0000ec4000)=0x0)
r2 = openat$selinux_load(0xffffffffffffff9c, &(0x7f0000919000-0xe)="2f73656c696e75782f6c6f616400", 0x2, 0x0)
getsockopt$inet_sctp6_SCTP_AUTH_ACTIVE_KEY(0xffffffffffffffff, 0x84, 0x18, &(0x7f0000d7b000-0x6)={<r3=>0x0, 0x6}, &(0x7f0000cae000-0x4)=0x6)
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r2, 0x84, 0x18, &(0x7f0000222000)={r3, 0xfffffffffffffff8}, &(0x7f0000641000)=0x6)
2017/12/15 11:53:27 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
socket$alg(0x26, 0x5, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x400000041, 0x2000000000000032, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f0000001000-0x78)={0x5, 0x78, 0x0, 0x800000000000000, 0x0, 0x0, 0x0, 0x0, 0x10220, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x3000)=nil, 0x3000, 0x6, 0x4011, r0, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x5, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7fff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
socket$kcm(0x29, 0x2, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_SET_SIGNAL_MASK(0xffffffffffffffff, 0x4004ae8b, &(0x7f0000672000)={0xce, "b745f78320132f2af7c7128474fffdf1d92bfb0c91069c3e0d6237575da2b90e0b79e83921b44a5b642bc4f1ee731bfaf4d752eb9ae7ab58026b0b602758ce2fc50df9b43fe96a0a159fd140068a298ed506434567ca83ceb77da023e85a953e5dabc9caff871958f03d0c0b7b560213c9aeb5cb18a061352cbb209161b1a9b64c704c83bc2aa47bccb10c9364d71831bfb06cd8157ca0e6f4548002fbb6c4ada5ffe274b93f31ac513497268913fd98171a4d06a7ec2aa306c353c50ccc75e38d80db25a0d769b0f76c7090b2b4"})
gettid()
perf_event_open(&(0x7f0000001000)={0x5, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x666, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20000000, 0x8, 0x8, 0x0, 0x0, 0x7, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x8)
r1 = syz_open_dev$mice(&(0x7f0000561000)="2f6465762f696e7075742f6d69636500", 0x0, 0x200000000402084)
ioctl$VT_RESIZE(r1, 0x5609, &(0x7f000074f000-0x6)={0x7, 0x3, 0x10001})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getuid()
perf_event_open(&(0x7f000000a000)={0x5, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x668, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3, 0x20001000, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = openat$sequencer2(0xffffffffffffff9c, &(0x7f0000f93000-0x10)="2f6465762f73657175656e6365723200", 0x100, 0x0)
mmap(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
migrate_pages(0x0, 0x832, &(0x7f0000001000-0x8)=0x0, &(0x7f0000002000-0x8)=0x210)
ioctl$KDGKBLED(r2, 0xc0045405, &(0x7f0000001000-0x1)=0x0)
getrandom(&(0x7f0000a6d000-0x19)="00000000000000000000000000000000000000000000000000", 0x19, 0x3)
openat$qat_adf_ctl(0xffffffffffffff9c, &(0x7f0000b39000)="2f6465762f7161745f6164665f63746c00", 0x101000, 0x0)
epoll_create(0x100000c)
mmap(&(0x7f0000bf5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_fuse_mount(&(0x7f0000f49000-0x8)="2e2f66696c653000", 0x0, 0x0, 0xffffffffffffffff, 0x0, 0x0)
2017/12/15 11:53:27 executing program 1:
r0 = getpgid(0x0)
getpriority(0x1, r0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x237000)=nil, 0x237000, 0x1, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket(0x2, 0x3, 0x40000000040)
sendmmsg$nfc_llcp(r1, &(0x7f0000888000)=[{&(0x7f0000104000)={0x27, 0x3f, 0x9, 0x7, 0xffffffffffffffae, 0x8, "9152b137ee8bdfd87af998d4f8120f9caf258f2633e1b02dba820c16cd041c7bd6891bfde97fec04fa1a235b2a17c220fa66dac1cb1b53aab7deb1a12a3f75", 0x0}, 0x60, &(0x7f0000790000-0x40)=[{&(0x7f000037b000)="332c995a2cfc8b77885890971546d5914114930b7428b4913fe5f8e637fe0e4904addfd754b59df711dde922b71931566f62ff0e5633246eef938baafcb2380a46b7fd723d768b43432e9e25ad3376daaf9c4a8203afd3f2a5c235e1b2276b74b7dabd314351416eb78ceef30251fdc29c158457912fc22e4839f56a6f4f9871d742642ca6c1677775e8f50f7a30a126fadc6755c9f7dc748b76a52321edee776a886b746a07fbe564c54328f0f39b72fbe92e3a6a0ece40bcf26085e30f5b71a5e2d16799f5dd0f5e688c6b6a9540e3cb", 0xd1}, {&(0x7f0000b81000)="42ee5f48105247cb7ba09b7c2dad3ad06adbc6a2079dc4ce3d022be3c5a1e8de5564a5c5a4bc8c2672e05ba955663db5493966cd492af8aaf1c0f1e2875b4e98cf856fa7f997c368f2e00bde4c513ec96d6ac89da356ebff0aa903d5c3b487030494c9879dc6fc7871216e5e6d2742ba850f503065d7eb6d3545fe9317e19f08ea0ac590f854d2338442074e9165dc61ad5d1475505f2bd119a12f1d3a6fb35457186e7d0c8de095f727b058e68ab4f80a3f6ace7cba7f74260fd82c877bba42c9f70669336c7c2300d85626a666afe5979027700b1ea2fc7144f0e82db54b1a37be515c87026dfa1c630c7a25e9b14afa3e7802a98d19b8ddc0a4b4fe0ec89ae69ec14a609b0869d8849ee86fc56a1ccf17e39fb456abdf4193881a47505e176b8fd0707369e22174f0f1a90a5f6600550ae3f73162e58fedc2351f0b9e26e52eda8c180437b5d7826bb98ab6806d5d347eaafece2c787396ac6317f419565b4543f3e49b8dd6d80404c32730eecb4923fefba44869e24f23290020009866b7ebcce496616ab2763f697197ed44de2b80726256270e9aa7c5c6569a59058d90f2ec420c5b875d391b1d4e0ef48f25504c69f558a0c3a712eb668aaf663cbdd966fad3f579796cb87f6cc7d59fc5f245860d25a58fe1a0f3feaf75a0a9aa1583d73d535c51be450d70281fad1a70078c88ef4a3f4f89546abcb87991d2b719737943786e6d19dcb22ab50208e0a5cf30125b87b75adbcbaa90d360053e38bd46905b8e88c3d6439a56ac1bf38fb15859fcd0551498645d7e9370da20e3746e354012fd447c1472400192a40787a59403f48d4319836ecdf6bb4e1a13f81dd5b04b94c6ba5016f8f414312990c42ee9c0360be6fb815f5b13db2fe788c919cc20aec9c4a060d59055307ed255873d4eaff152992dc05a14a436304bf8f23cdcadb0ef1a5beeeb768d88d0a4a2ec98cffafbbb8ae562478768e21ef211c27b9229e516f0931f9c3c19335ac5f8d6a8f743e8b72a39cd64e7a1fd7dffdeb73fcedc504c9d1ef96114243505fe0606850cc3e0ebb2a3bc7d905faea0455a1ccdc55fa4f76d57cc301e4c926c105f1c87af24b3e311f528ec8d03c203e189849ae7982818c5bb23d6fecc82e7f9076bed1e54d6b7cb9aa765d2b4de479548a9dacc90184d2cdc17065e79e2a0ea000a95bf6974b914a6d196cd4f00a547a315503f7ba2b6d7a4b48cd8a57a59368ad96239a5c82f347a10fbf539879c4b70e123465550067c59646380cf04cdd8f1e82f1a212b91c0f50345657d17669edef4ad227c8a7e6a9e6576319710f0ba01796099112c5aede888675e0c39ebe898bb42f3153eee9f257239208b6ca64623ff8dc5b628e0ba39fd01ec5f42337ac5903c5fe210cd4d8ca380da260a6f14ed22966a4e4eb2a2c52c9309d9eb8ba0570c9315ffaf22f80e2b19b6ab7cfdae3ae9411d11c89a500e1a73420ab31d1b779cd960161e87d98a6e95a40c6f89d8814e76e06da54ebe549cc4cafd7cf788a3b28170f5912a141d58ec7342ddfef5afb8b167557f638d7c656b711b315b32bdb7230939acec2881bfae48f80403ad2848e48152d62a6d317f80366978db5e74c296a9ca0056b8f75054954ce6a290da223a7d4325a51b14bdc1e2143fdeedbc6657645b3428d53d0a75866610bc6d258389b11709ce97ee0c326cece52b04b31f4e11e5a5f2153efe805b733e637cadc7a403292024e92084ce4cfbba542f0f3dccae737fec811a0e8d561ddd15890103dfec5134aafa0de6b824115756670729ff431a3d680e90b0a32091a98f2d8cefdc8e11ba3a085a56b38299ca6f0f71b67c6b0327b82e6fab578c76647815f21f931d49cd49c0a6ef5537a28a6f6890c01d5230b9436cb7b6b0e8ff027afe8e28be4450e144cdd09ae94b22e22358117c7e100c4cedba59ac83b8038742bb4e446748bd1cbee2506e4cb10afbe68d31c32f7da96b9ce591087e4db95072e3ca62e0eb8081cbf05f5d230874937beb39b5eeca95915281321a1c3ac4b42adef75226c1d91548cea6d4d7c5860b575f8276c30554cee0734c7ae5d7e7461cb5de1559f3d914da6d263af3bae3108ad35ed00efa54309c7e4e84059e51c89346183f57eeda0440e28460730a6e837cf37eaf255b77cf9f485f84184f35011257e068c3106f742b5096f70fb05a7d9228e9cfe2f1cdff5a607b93763eef3f11930fff7b3293e3e2f12c7197b6ceaadf3ea62e7f752d161bd66427ca7c42119e5c8b262a6ba1e35c08994bbf8ad48ba3d10b223ebdf473d953f9ea5194c81f915e41539a8fd8a79dfbd5ccef8e6b21a3b95727a47e6744f54950e613592194d467dba8a39d22f729f18155d27cc9b0d915954bd2d67daa96e9494cd065e672882aa4ea1c434af91ecee79e8b376c20e6e8961b5b5f6ec53dca8d541dcfca89b87fa866f715db7e3b12f3cdb14e4fc3a5917775be23f430cdd1be7ad03fa086a065f6984d511ff94cb13c0f6719de30b550ad6fa4b22202da7eecfae6d91a2bf0a27608613d6445678d5592f005346006c5772f79a8b6628a6a4f175383eebdfa3fef8ed20c12f1e97be54ae071f9436e21d0dbaeefb28064fd00bac8b594e433e141851bd0a9d71128bd1c4cdcd49879a6868a6a45a909f1edb93d6c513363b82fc1e8b14f782f7c34a9ac6cea5f382e0314bdbf9db791d60ca62c5966f2e33695d9ea45ee4cb1059c39a61eb5e391fc6428f8fad4576664e0a7323ed27e44af673d549023b7c27867843298f3480aca9aa722fa299037b3787b6b568fbfafdb342cfe63187b2da88e39da0628cab016ea42d8e3a1807864cd1b711b6a9fc1a66ff358603ea5bf212c2fe18344d31b71da1ae463e3e3717b7ecc584a2bce090eada2d3317dc76bd08052c4bf6ce5728a7318390db50b45b8b3083a69d84b5015e4dbd02353bd90d0b0a542d136937891580ffd88263dae6f38ffeae832398d8a866028c988f4f262e95d74c4373810d8b29167e192a0491f71acd66b81dee6f05a0e499bd9bad55a88e5c8edc6cec58ba1fea4d97e4fd28ff8c820eb5c2a70cb3d0290f052819a83027e3ee32810d222ddc4585f720467876ac4042260c782ee878a52649bb7b36ffe2b67bc125d2216ba8a7b12859791167151d5c76012da680cee41b2d3d02d3288446af9c1b06269325cd17cca5d7176f8744c3427bc9f18f292e6760699a969e522edede41b78d73bbbc62fdee93ca96a78004769b75b4615c43728addc0140621d5890b74bb5f1a5c8fd329f4305355ed56f9389f69ef233d9104fe9344658ac81ba88b99bf1e28d599af417838a628f2a758271bc34de88f15d4fa8208a60ac476604c762efdd37f604daec8ace704fe3444edf6229b34ebbf2a446d807d774039ddba0e1e4ac678988f2513c443fa99f384cdc84c8057b2fd0b0ec6f384d7442a991e59f98919c19b17fa2d2e69783bc46f3770c44b36463df29094a1690458610e0f7f940287412f5970da5a9a0283b98b8f0761551d7a33bcb8ab414c5bf1ebec0269941dd7ccaaddf6a64a63ad9b59dd0eba5e7f8421ca2bfc87b620eb09f920218b8b90340eb8dbacd6dfe89111861c06c29cbdf14904ceae7a061a32d9d10f3907382f5ee38bf60b8e49079bbce74e74f6627ea1da32c16aecceb936f39db985e3a0d88340bbdb2cf619813731d9c25277b4260d5e6bad99ad7a4b79270adba568d2e0ef86c5441321a9c092c059292d2d0719d7f0a2782a2575b4fc313a2b13352ed9ccb88c8a7af8c91bbdfaf6c7627f0f7c98838addbafe20df4e4ec706edf5416211579b8f7ee9bdf704d5e2bdbcb722a1ff1c4e239739535cff4f8817e2c88e4f644cb4471c95269873c1bf291bedde99a37bdadcf52e2ff3185f1285f87b602b74f7b7cb91a5d430c8de00a1aea96657ee00dbaff6004e7a8b81898c6e1bec8c5bc9b7c14c42f03ccd2b4c2f3c99aa6408e934f287180dcfcb579d4731d8e3f866990a2d18178b6d3f4036471066adc8ee42feb9330e61719be26c73598b2d05946ef1ff7732043e308bb6d0354fd52ff1a1a81c44b78cb7e36610b81419f527d1c9c1599c2d6800f3092b81772b1d343d33095021d345aff26849549de87c116667d3dc7c5a78db92433a72ca7d1442076dcd7b2dbf6e43d3c9a37251118d38523222dc45e3a459c1e5a6fe22b13329e1273c8601878fb8bb8b462f33dbb4f6116f69fcfc3410684b3394660e0563b33b136708b4ad029de8adaf79273a28a5124bfafff0b9622a9d1be3d04e350bb7de7202c692953abb74f3672efba83270197918c5dd2469c6b65ff0b10d225712c289cc5855edabf4953e294b9ec0ac31a52832b5dcd1a2104374e32c4ea33e01629a55b2d85953d76f1b3c48a0a47485958910e55f7d720f1ce5cf7b3db80aa1375e9aee873d62ef3839bbe85bc0d0193eba7d54f324902dc96972278aa0c7f660e6986fc392379aeac4086498bf4a7c27c92914de7adae15cd9a6ce4b00571dfb99293eb93b03afcf200cb0666b55a782c348ea613740a585bd8c05fa15479a96bddfcc79b03f2d70dcc14c56f59212b0b67b4fb7ab58127904b4635c3ae59ce6c3d7942261f90c99756ea7ab2cdf307bc7ade1f17db8b098df6501e836b6c128ad19a5fe2188a0796412d1c59fa71d0f69f181a0408c4f8167b123e61e4a319c67aca00f307159164e67e3898b71bb6f86d0e8ed8c861fc6445745297d6a4fbd800527d40cd4ca7f560adb97aeceb2f91a65e768ac9a2cb57fbcdae216fc5286613916f5adf80d9096722d871a44566aef2fd721877a301a7458e8720624e8f263bd046cf0e45b8556b0b3f07e992e9f7b03a0774f0f66eb210b28cb467828bf16726c233ffc76c3c94d00496805eb8ced98a070cd79442b860032003b9b57493aef9d91fdef241ba665a01fff3d296458177be9d1c12226ac5e38777439df45ca06ad22fd4b4a8ac269525bc85c5bf4ba9053ee9b4d8b5fd3f82924bf7ee6ae4932cba16fc18c8a4c51c623756f08f35b795f99927b4a961052358308c998443bf003093ff947cad796e50f9b046b910654a8e42f98bc9caaa475e8fd4eacded68f8585f02a7ebd75bd7e8f52128c8ba87005e1363761d65336591093669d24fbd0f87c93581f202c9ea883249715db9f27164b5f64be5d91577f5fde3d06e0273775c4dd7c0f7e43bfe7b91e37da11351999e61f1127d06882ff573e700bb8e53dec09db267e821769bbcd3fcc0db1d00bd1d9954f095c93348ab854093d4a17dc1fddd3bca17de76e5bf2e054ca01c69fd2b2322bb89d8dcdf040d7f5ae0ffcb7db0e216cbbe62f00f6e7b1f051a87edee517fddea8242180a452a2e647f52df9598ef24b1cbb5c845e947a56f1b9f723a402e205473a16425bdb6b1ff5b6d317f31fd8cfec27576cb93b251b8a4ecf8ba7ae6152725c8f4ae32ff527fb2f689a871add2c3231fb424fa2c83dba647cc880f33ea0c35e2287a5a536134b39a55e6e2769e6a0c5f934fbe8b7b07607267d813908d2e976d14074c6dd56337d884f2646bca87afcc574e10ac199ac9dc11025025aed4243c588e965236de56a266ced96bad9908ddb441aae15e179262edc96889407ebee4ef25bc2c992526efaf6f17fd192df9fcec0bb950cba742c69ff0d974813c725d6cfe05227c9472dcedafcd3968da11f4e41ce7eea06851913ad3f2a1d9847dcf147cc3d5feaaf781adaf2250474a2617131da1c689e63358dce6a16f83", 0x1000}, {&(0x7f0000bfd000)="49a2fc1a03c9984c5a1e21610fdafb6524b1884844dde4f01c4d0fae698758fd43d64f46144556cae94f9abdd44b5d196bb7c412cb5cfbc892258688c062a14670f11aedbf3a74869e0c4bb2b1faff8ab2b143f06a6b2f4f80092b47cc1283eb7f4b24004a1f72986c13240adb11dc6501fcb38e749d2213355df794525a13b5dde496e68731d5696153cc9aab80144183b87aff99dea2c4e23ce2cbff3b42454be04b3066507174939e0b328087cf7758069df6df196013250e49ff060f74e1099d2039aab63efb3db1357821ae5ce890e9a01ea8c4758b10bf4ce6e19924d98fceee5cf7a56ffa70", 0xe9}, {&(0x7f00008ea000)="6ad14fc096dac8f83fcb487640dc14595fbfa2e25a5e88b01adac4dc3a9b45e01179174eee9c376cc7c46f7cdaab3aebb9ff73a30b6947105b95d23318ce115997c67962dc69ce0134a74ac7391d00ec56a244991c4364aaf194b7b6d7513e89a88a8d1661358d3275b4b4be60be53151fbd4164b09f5e9cea614c0c08edbc43de169dd103c9ec42d9ed7f813b49d2cfbf0e64537c6685fd4594c007201bb3067e0ee160c03d2e53b9e59c4b60017cd3fb6e94e5ed2d99eec5843b80a7ef2a928b01d1c7e7aba3ce28850421cda2a0958e1be52d69d4cf630cc47ff096f9cb5e5d848d2237ea16bbb88f20eb855ab57a3cf23a", 0xf3}], 0x4, &(0x7f0000651000-0xf8)={0xf8, 0x11d, 0x7, "6ed784b023c7a6951927fde9e5bcc9776857c962a43ad90065190f6d8a9c2527a0f44f4619acf8b2df179c94e36178251c95fdd857eb9f1e08a0ee140c5dfa81e34d36acb7969d25d65a9c770cd3eb7bb056f891125f341309f769cd804f9c419193043b1e417df772f12c893065ff257ecfd2d62070984f7b446ecaacf57d428c07ae5bbb7175154121eded18180e420dc33c1a3f0f9530e92ac6286647c281c6d7b94790e17e544def00fc4e8077a2da58f1e7fe11fc7b5eae1fd8d55798c93e458e67c77401ad7d0b4cf5c732ca16679598292ba9b47cfa901898bcdd72f276412176"}, 0xf8, 0x854}, {&(0x7f0000418000)={0x27, 0x1000, 0x40, 0x6, 0x6, 0x400, "4cd0305802768fe3a44f750d712d9be0c4d5298a8d651361ab494ee16eb62fa735536323dda584be3a5a549a6f013db28b25eeb02d544abe3985c4f8976fdd", 0x40a554d8}, 0x60, &(0x7f0000d8a000)=[{&(0x7f0000fd7000)="261a3251d5cc2a47f9cd386d26b993d2abdac32b0800b61c55703ed664228f718a3f1b2668d2c6e9ee4cad815b5c524eefe77a33f305d8d75f3ac729cccb0cdbba83c957e61942ea578a76373ffcebd22dc4e26ccbf2b3167d8e9198ce6b26dfda056132dbb2ec568f1752a652261c39a012d07833f4832a8a52965584b7e0c41bdc50bfb375a403e616d473fe79738b5fe394ff41dbb7863749429237eed2edf59b29623812d5d1c16542ee0205d63750a597e35f509ae70ef633c8b4e91c07abee97b2c11bf9b55d234432833ade90f29e9670af28e2ed097dfc0c2c09a6d36f90ed1abdf00bf343c92bdf73b59647d535c934739ab8", 0xf7}, {&(0x7f0000ef4000)="82ce6193b484555e2fe771410105170714f3a22ef50fffef1b4c3481115b717347261eace1186560502fa1ab6c9b89ebcf1701a60d1e227c9f8def5be7c7a399217a64f33d03f3d72e75e8260e0bf25dc6f2a1677832909d4362ca99e2e89dd56b5205e33cfa4432080d83461ab8add216c5dd180c6436c7310131bc296537c23ea1a260a76abec5f576808ad9e60d08ca99f801b109f568cef68267400056", 0x9f}, {&(0x7f0000764000-0x9e)="51884adbc1c3a18e407ed924108c3bc1edf2eaa9d9daec2dc2a86454eb7e638457297aef7b288ee07575bea7ca61672754a1b5ca7dd8838e4e874fede6ff356ea88b5b73e2a29e230f8002e45f0b1de13c939aac35a91525d5304f5dba3d7056f18afb2b0ad66d2ec88175043089a98842bba3a22f5f4073b890e8bb578900145b90efc4c544d6c2e724bc1dbc95088d6311c09ab3b4527f51f05ac44524", 0x9e}, {&(0x7f00005b4000-0xae)="a28d3e1cb03285dc1ee572fb631a74f7da97f23d194e7a4fe7cee9c781ab8465696ea9c3661b56c38fff25b1beff264c32bf29d9b6598f11f4a5366857278b9e99f8eb2008d7e6931e91f09148229eb2cace4de0c4a110d9d3d775b3847b61db8110e0d9f2b63795e0f4028f6234f415ce74d91e1dd117a78f376c16c74f24c65cc6317b45144fb67a07b7039727a2aee3fe5319330ccb435eaa268304a460683f21dc69a522fa4e665a8a94523c", 0xae}], 0x4, &(0x7f0000391000)={0x108, 0x104, 0x6, "d2bf0b7ad78a181f51629074c1fc886d5a7ba4bd7c25fc4a29ee4d905576da6e65be28149e97fcc36bf53519f2b3f2009feca732e03fe330e9266368771d512b7d8bbea796487ccfce79dc6b87a6717f45485bcae6085dd208ab80782780b978a3de4cd9f34230568e428afdded6819a9fb19defba1fd88e9deaadac06ca235f777cd46a957540445f28f54b44877aa42a2c8854d3e7ab70070d82842d953cf9cd28b3f45cecb6fed7cb753fede51418a43d4caac3c28f8ca3e8e5d73e8aa766fd2251bbf3d7caa42d6d6d4f787bfd1755c88d825be17dd68d581d685f6e55ed972464892c00401496dc57acd78cfa0c2e5fc2891c"}, 0x108, 0x800}, {&(0x7f0000108000-0x60)={0x27, 0x6, 0x1, 0x1, 0x80, 0x2, "80ee6c0acfc515ccea7777e9830a8432f2e3a3158b5575e5f72ba4eb3d41b76225e6e9a96b2ba3c27e0e66e2418bcb416041c890f54445a50bb8fd6126a1e3", 0x8000}, 0x60, &(0x7f00006f6000-0x80)=[{&(0x7f0000e05000-0x9c)="891bb68993687e6203915508bbe2235ca7031fbf91842aecad18439e596ec6455fe4885fd7dfdcf54b33f33a0f178abd132bce53bb86cf058983da66f38f592846b86aa504066d888fed807de7480933d4641af00dab6606e6a5b53cc099697a8112e70f11de18531ba20d97953db0f399bc4c2b724d67db99d2a4d5a7a0069cb14db3ad8b33c810f41f48afb1810d07b76672444dcd101ae86d520a", 0x9c}, {&(0x7f0000559000-0x3f)="3f9c7bd2a291e6f77f585b1111b2e6c0390f453b6bed065a3225bb36292f6c96df287e50cfa5e71286c9acf48c255ae8d624b73fbd2602bfb1d97a895794e4", 0x3f}, {&(0x7f0000400000-0x20)="344f03f5bff6fe08abb57c6a613794737b9bc2ee57c30b018abd6ca1786e96e6", 0x20}, {&(0x7f000040b000-0x2f)="e57ffc182ed932af8fb2a8505022aa7e9550881ad017bd568d4795e1e33136514b6f65320716689fbb0fc51cae9b6b", 0x2f}, {&(0x7f00009a7000-0xd2)="d3649b38569e7f66ef620c650e9e71a18251ae62d875340f65a7fda0c1ad12203d0e323d01f54970a293134233092b1f02a12fea6cb53ec94f1461b99d286f6d27e2a0b391c6048e1ee85c214531c83aa1879437a3d01d77a37644ed7ada306a5acf3104cce7e65dad40f0466b9212daea035e0b5f4679cccfbde202770ed5387c2de70fe0995a73aaaaa0b84e7ff7f9193b0afb275dfd057ae53802e1244abf710324f85353035a6c8966749686f4a6963616598c23b218fcd2dc9317540ba6a4d4b67d0b9641aab6d65c2c1bd1386aa5dd", 0xd2}, {&(0x7f00009ca000-0x2)="304c", 0x2}, {&(0x7f0000ddf000-0x23)="b30c249233c733a6c607a1aa3a3cc55c887ae23d76f1000c87f4b460b151a7bdd258c9", 0x23}, {&(0x7f0000228000)="4176115ea42feab6502b3312e0a969994c74ae0198ba272b16b92cc4db078917218a21fc69b031e0ce935d29af0d8c0ffc02da8893edb47fd9800bdfb7e831045e2beb76b1533ec0e2686fb81b49dff51277b54a8be933dfa68d01bf33bd9df48bbf4e214f3f4b5b677a970ab38d9b9a6ed959c0eda4f9eafbe1765f7ae8876364fb93f611cb2163ef7a4eeb796bfe49514ba754ffcdaba7a46ed20b1c7c46b42b66460a988abd03bfd135133bc156659ddc534924c634421208b9ea731a317058e3ee45fe1545b5ea10226b11f073d0710c865b87681793242ec703ea023eccdd4122ccb85156476a4be1b93687e57f4091f93f", 0xf4}], 0x8, &(0x7f0000ea1000-0x78)={0x78, 0x88, 0x9, "cd121f0aec3c5d1e62a9b7b84c789c1c10d06224e7121c4ffb2915c832f3ab19c6935adaa56bd4152c293396b7dba91739c8ef375cdaf30b923fc26147713fba9a031c1f9590d1fc66849c5dbf6ff3bf8327a35c1abf0d3781394102778654bc2d6b848d086577"}, 0x78, 0x0}], 0x3, 0x10)
ioctl$sock_inet_SIOCSIFADDR(r1, 0x8916, &(0x7f0000154000)={@generic="fc1d30c52d07b0d7a99161b610de90f7", @ifru_flags=0x1000})
getsockopt$bt_l2cap_L2CAP_LM(r1, 0x6, 0x3, &(0x7f0000d87000-0x4)=0x0, &(0x7f0000075000-0x4)=0x4)
setns(r1, 0x0)
sendmmsg$nfc_llcp(r1, &(0x7f0000239000-0x38)=[{&(0x7f00000a2000-0x60)={0x27, 0x10, 0x0, 0x0, 0x0, 0x0, "a627cfd86399dfac2063b4a66021e531678e893e12003ab58c3204d87637cb25d67298ca57fad84a7a71bdfb674dcd27daed2fc91b715303fffc878eb6b571", 0x0}, 0x60, &(0x7f00006bb000)=[], 0x0, &(0x7f0000303000)={0x10, 0x0, 0x1000002, ""}, 0x10, 0x0}], 0x1, 0x0)
getsockopt$sock_cred(r1, 0x1, 0x11, &(0x7f000068a000-0xc)={0x0, 0x0, 0x0}, &(0x7f00007b6000-0x4)=0xc)
2017/12/15 11:53:27 executing program 7:
r0 = openat$sequencer(0xffffffffffffff9c, &(0x7f000082a000)="2f6465762f73657175656e63657200", 0x10000, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
readlinkat(r0, &(0x7f0000b07000)="2e2f66696c653000", &(0x7f0000000000+0xb39)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x52)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
tee(r0, r0, 0x9, 0x9)
llistxattr(&(0x7f0000801000)="2e2f66696c653000", &(0x7f0000388000-0x26)="0000000000000000000000000000000000000000000000000000000000000000000000000000", 0x26)
getsockopt$sock_cred(r0, 0x1, 0x11, &(0x7f0000a3c000)={0x0, 0x0, 0x0}, &(0x7f00005bf000)=0xc)
fcntl$getownex(r0, 0x10, &(0x7f00008d3000-0x8)={0x0, <r1=>0x0})
r2 = syz_open_procfs(r1, &(0x7f000018d000-0xa)="6e657400")
socket$kcm(0x29, 0x2, 0x0)
sendfile(r2, r2, &(0x7f00004db000)=0x0, 0xffffffff)
[ 50.828724] binder: 7369:7371 ioctl c0306201 2000dfd0 returned -14
[ 50.845332] netlink: 16 bytes leftover after parsing attributes in process `syz-executor4'.
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$kvm(0xffffffffffffff9c, &(0x7f0000000000)="2f6465762f6b766d00", 0x0, 0x0)
r1 = ioctl$KVM_CREATE_VM(r0, 0xae01, 0x0)
getsockopt$sock_cred(0xffffffffffffff9c, 0x1, 0x11, &(0x7f00004e5000-0xc)={0x0, 0x0, 0x0}, &(0x7f0000e6f000-0x4)=0xc)
r2 = syz_open_dev$vcsn(&(0x7f00008f0000)="2f6465762f7663732300", 0x1, 0x101000)
ioctl$DRM_IOCTL_FREE_BUFS(r2, 0x4010641a, &(0x7f0000d09000-0x10)={0x6, &(0x7f0000c61000)=[0x3f, 0x6, 0x23, 0x4, 0x49, 0x8001]})
ioctl$KVM_CREATE_IRQCHIP(r1, 0xae60)
ioctl$KVM_GET_IRQCHIP(r2, 0xc208ae62, &(0x7f0000df3000-0xd8)=@pic={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_buf(0xffffffffffffffff, 0x29, 0x44, &(0x7f0000109000-0x1e)="000000000000000000000000000000000000000000000000000000000000", &(0x7f0000218000-0x4)=0x1e)
socket$inet6_icmp_raw(0xa, 0x3, 0x3a)
r3 = socket$inet6_icmp_raw(0xa, 0x3, 0x3a)
setsockopt$inet6_MRT6_DEL_MFC_PROXY(r3, 0x29, 0xd3, &(0x7f0000ee6000)={{0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x80000000000}, {0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x0}, 0x0, [0x4, 0x0, 0x0, 0x6, 0x0, 0x8001, 0x0, 0x0]}, 0x5c)
socket$inet6_sctp(0xa, 0x1, 0x84)
socketpair$inet6_udp(0xa, 0x2, 0x0, &(0x7f0000ee6000)={<r4=>0xffffffffffffffff, 0xffffffffffffffff})
ioctl$sock_inet6_udp_SIOCOUTQ(r4, 0x5411, &(0x7f0000002000-0x4)=0x0)
setsockopt$inet6_MRT6_ADD_MFC_PROXY(r3, 0x29, 0xd2, &(0x7f0000002000-0x5c)={{0xa, 0x3, 0xce66, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x7d}, {0xa, 0x1, 0x9, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7fff}, 0x3, [0x7, 0x6, 0x2000004, 0x7, 0x2, 0x200000000000054, 0x0, 0x100000d8]}, 0x5c)
socketpair(0xb, 0x8, 0x5, &(0x7f0000737000-0x8)={0x0, <r5=>0x0})
socket$inet_sctp(0x2, 0x5, 0x84)
accept$inet(r5, &(0x7f00005bf000)={0x0, 0x0, @multicast1=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f000087f000-0x4)=0x10)
setsockopt$inet6_udp_encap(r4, 0x11, 0x64, &(0x7f0000ff5000-0x4)=0x7, 0x4)
syz_emit_ethernet(0xff, &(0x7f0000d95000-0xff)={@empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], @random="73aef2cf2a86", [{[], {0x8100, 0x5, 0x3, 0x53c}}], {{0x0, @ipx={0xffff, 0xed, 0x3fe, 0x1, {@current=0x0, @random="340522162599", 0x25}, {@current=0x0, @current=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x7fff}, "8b3946b3c7000af5c1982150a06d3e7bd936df1a409cf40b5f60b997a558857168518ada76698d6abe8eed8bd44e3ebf383996ef200175b57288af7f40902fff7864defe000bf6bc9e1acfa1112c05f95a4fd983441fdf271e8dff350f678714ab06b75d3e9f182e70366287ee3632334cbd6aade90a49bbd6c72ffac1b5e6ebc69a551a08160abe2fd2ffffffff8cf364cdc28f7ca575191ecf32871a802237ff7f00006caf1e09555128f5048210cbf6311673606444c06d3896aaec7533efcb0cf11fb647dd65afeb055214d7fd"}}}}, 0x0)
r6 = socket$inet6(0xa, 0x80005, 0x0)
setsockopt(r6, 0x84, 0xa, &(0x7f00006ae000-0x6a)="d7fdaf95070179890fddd5a45d3f32eb840000f6d5733a0000a26a0400465f2626dcbf4299eaca32daa3871536529c2509beefa9f9ac1ba8376b48d7fca4caf9127ccf56401167e4c30034e0e1069276b2a9fff37a000114b57d9ecd06c70998d4ff7f409f4f45b222ff", 0x6a)
ioctl$KVM_SET_IRQCHIP(r1, 0x8208ae63, &(0x7f00002e5000)=@ioapic={0x1, 0x1ff, 0x0, 0x100000, 0x0, [{0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0xf08}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x3, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x8, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x12c9}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0xffffffffffffffff}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x7}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}, {0x0, 0x0, 0x0, [0x0, 0x0, 0x0, 0x0], 0x0}]})
ioctl$EVIOCSREP(r5, 0x40084503, &(0x7f000011e000-0x8)=[0x80800000000000, 0x2cfa])
r7 = ioctl$KVM_CREATE_VCPU(r1, 0xae41, 0x80000000000)
ioctl$KVM_RUN(r7, 0xae80, 0x0)
ioctl$KVM_SET_XSAVE(r5, 0x5000aea5, &(0x7f000079f000)={"2e2e6887ef24b550c8cca88d5bb6bd9499b81cd4d3dd2e7573e234a1965c07034e22677eafeb9a82f276f8fc471d701a947e9344105c80bbe93d38b5c83191e301e9bccfdf4d4004fa1994e4ec5e66e55c66b0608b864c0013e206060cbdff827ec3df95c6701fb6a9b3f4bac8407ef74587491a2a7782c37be062d4afb8ee3e2204dc79fbf6e729e8db64a52a81b99b8a80d763e73ea5848c227c2a63d7a1055000837f97de50711014529930bb93a7b2475dd53b090344f8d769bb2851327148bfc5547d901e4fc65cd3ef4aace795ea0dd8728d25d193decbc3bdb8f6e60549e3888cf807653b69795ae5189d94a56cd0e749230907a18b6b666c915643276a68bd0504e2feb86b8bda436b0e9c64e4ab6148ce01edb0192f9db79d4e42db7d8649fe77b7ad52105662551a708373f9e0dd74661634292ac3021b62df742bd3e3e6bf422ec9794abd71ba74f3731ec482e22075e34f1e755851ad817ec7418902d107a48f6466ade2d0fd43e3695842ebcb7b64b1bb4286b1c20bb90311d49d0638950504a5eb173800d34fbd8253ee23ad285119bc056d64f6cc87571cb31739ed6fab4c9e70cdc9fb47e2f74077d5ddab957486d15fd6f5727e7556bfb04fd2c9b31d64a96a1cc64aee2c1788c0277648ed9d8a86118076d14d6d081e9b452c4a739563815b940e2fe7534be599ed8ff0371a673da89f5246924d31c8889fda31710673e209f0412c798531bf0f6d66b033832f04aea1262c5445ed6b4946f5276028c85e105f4aed086e4573f6dd981243e4ea6addceacd1206a255ff1542efa651b36dad08d436748bcb8148c2348237050ecef1e18d13107130bbba24d2c09d1452b3417eb1de6ac643f1261faa6d7a5e5d205d748e18366594ae6b87aaa6a7a66ff34adb87fae0a292a1da653304b49f286bf8f2950eec904e0a1833dabf28d75921db61f0248e22bee3c7919c79a79f5f74cb153d4cf0804e179be3ab4737206933c7a12cbaf3abff44e053798edf32ba028244b7e9afaa71a56aac403f044e384b46fede51bfbce27a3a91c1c8f32b13ae80d7d103893bef5513599700e88166ad94ebcf1ec764ee1d97bcffdb06c7a0ab8dbe159fd54cab8a208cf32bb2ec3a27eca0b741577002c8355571f67b486f95b3cdc2308a5ff554bbcda65250a4a4926d3572892e9befecaccc13c781d6f23d7653bf4aff89fffe07ff5e04e27534ea45aaaf2149c15b0709f4dae75d8d333db4e4689d583fba61a90e743a54e5d9225162eaa379dd7ddbde098581fd0919b285e71bb9a10e99e55f18939f08e77bbff094c9a0a62bc78ff650620cb6870c4b1920f70afca61f230c67bebcf3e095a5dfa9423d113ec6e3abcaa052fd824c1d5c32cd5d6693dd0c9eb0c6f2ef3f7d08b405d4c51eab7296e45ce712c415da08a22d3e4b2a353eadbba"})
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x96c, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r1 = shmget$private(0x0, 0x4000, 0x181e, &(0x7f000066a000/0x4000)=nil)
lstat(&(0x7f0000f22000-0x8)="2e2f66696c653000", &(0x7f0000fd2000)={0x0, 0x0, 0x0, 0x0, <r2=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
getresgid(&(0x7f0000b50000)=<r3=>0x0, &(0x7f00004ce000-0x4)=0x0, &(0x7f00000d5000-0x4)=0x0)
lstat(&(0x7f0000fa0000-0x8)="2e2f66696c653000", &(0x7f00001d5000-0x44)={0x0, 0x0, 0x0, 0x0, <r4=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
stat(&(0x7f0000e61000)="2e2f66696c653000", &(0x7f00007a8000-0x44)={0x0, 0x0, 0x0, 0x0, 0x0, <r5=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
r6 = accept4(0xffffffffffffffff, &(0x7f0000197000)=@generic={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f00006c8000-0x1)=0x80, 0x800)
setsockopt$inet6_MRT6_ADD_MFC(r6, 0x29, 0xcc, &(0x7f00005b4000)={{0xa, 0x0, 0x587, @loopback={0x0, 0x1}, 0x7}, {0xa, 0x1, 0x6, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x40}, 0x188, [0x2, 0x5f9a4858, 0x40, 0x4, 0xff, 0xd755, 0x7, 0x5]}, 0x5c)
r7 = gettid()
memfd_create(&(0x7f0000120000)="2a00", 0x2)
ioctl$TIOCGPGRP(r0, 0x540f, &(0x7f0000174000)=<r8=>0x0)
shmctl$IPC_SET(r1, 0x1, &(0x7f00004c1000)={{0x5, r2, r3, r4, r5, 0x0, 0x4, 0x0, 0x0, 0x0}, 0x10000, 0x2, 0xfffffffffffffbff, 0x51ec7e41, r7, r8, 0x2800000000000, 0x0, 0x0, 0x0})
r9 = openat(0xffffffffffffffff, &(0x7f0000e25000)="2e2f66696c653000", 0xc0040, 0x12)
setsockopt$inet_sctp_SCTP_HMAC_IDENT(r9, 0x84, 0x16, &(0x7f00005d2000-0x12)={0x7, [0x20, 0x1638, 0x1ff, 0x1f, 0x5, 0xffffffff, 0x8]}, 0x12)
setsockopt$inet6_MRT6_DEL_MFC(r9, 0x29, 0xcd, &(0x7f0000df1000)={{0xa, 0x2, 0xdd59, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x4}, {0xa, 0x0, 0x6, @loopback={0x0, 0x1}, 0x3}, 0x9, [0x7f, 0x1, 0x1ff, 0x84d, 0x100, 0x1, 0x2, 0x7ad52d21]}, 0x5c)
setsockopt$SO_ATTACH_FILTER(0xffffffffffffffff, 0x1, 0x1a, &(0x7f000002f000-0x10)={0x1, &(0x7f0000001000-0x10)=[{0x80000009, 0x0, 0x0, 0x0}]}, 0x10)
socket$inet6_tcp(0xa, 0x1, 0x0)
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$rfkill(0xffffffffffffff9c, &(0x7f0000097000)="2f6465762f72666b696c6c00", 0x109000, 0x0)
getsockopt$inet_sctp6_SCTP_RESET_STREAMS(0xffffffffffffffff, 0x84, 0x77, &(0x7f0000e2a000)={<r1=>0x0, 0x4}, &(0x7f00002ef000)=0x8)
getsockopt$inet_sctp6_SCTP_DELAYED_SACK(r0, 0x84, 0x10, &(0x7f000092d000-0xc)=@sack_info={r1, 0x2, 0x0}, &(0x7f0000725000)=0xc)
clone(0x200, &(0x7f0000fbf000)="", &(0x7f00000f5000)=0x0, &(0x7f0000f8b000)=0x0, &(0x7f0000e03000)="69ac15d3ee90163a4a6462b3d518adc1ec1f4e9751215efcfa94b668cccbcef897ed634cac3d98437817dfa590f984119d51c33b1673984ed19240ac81b533446b13e391c478ed8466780b35b9e3c7c290838bb5f2ef1a59999d9ed345c6f858d74927f02d80383949031940194c066452aaa36bb5f98f245a9b6c238f09204653a9f25d634a2abcc495a6fae2f2c316c0")
getegid()
rename(&(0x7f000098d000)="2e2f66696c653000", &(0x7f0000d5b000)="2e2f66696c653000")
mknod(&(0x7f0000ebd000-0x8)="2e2f66696c653000", 0x1040, 0x4)
execve(&(0x7f0000f8b000-0x8)="2e2f66696c653000", &(0x7f0000a7c000-0x38)=[], &(0x7f00006fd000-0x10)=[])
ioctl$sock_SIOCGPGRP(0xffffffffffffffff, 0x8904, &(0x7f0000ba1000)=0x0)
read$eventfd(r0, &(0x7f0000de2000)=0x0, 0x8)
r2 = shmget$private(0x0, 0x4000, 0x0, &(0x7f0000594000/0x4000)=nil)
r3 = openat$selinux_member(0xffffffffffffff9c, &(0x7f0000afc000-0x10)="2f73656c696e75782f6d656d62657200", 0x2, 0x0)
ioctl$sock_kcm_SIOCKCMCLONE(0xffffffffffffff9c, 0x89e2, &(0x7f0000cdf000)={<r4=>0xffffffffffffffff})
mq_open(&(0x7f0000276000-0x10)="2f73656c696e75782f6d656d62657200", 0x842, 0x8, &(0x7f000043c000-0x40)={0x0, 0x3f, 0x1, 0x9, 0x90, 0x100000001, 0x2, 0xffffffffffffff3e})
recvfrom$unix(r4, &(0x7f0000cc5000)="", 0x0, 0x3, &(0x7f00007b3000-0x10)=@file={0x1, "2e2f66696c65302f66696c653000"}, 0x10)
shmctl$IPC_INFO(r2, 0x3, &(0x7f0000c42000-0x6b)="")
execve(&(0x7f00003f0000-0x8)="2e2f66696c653000", &(0x7f000045f000)=[], &(0x7f0000cd5000-0x8)=[])
open$dir(&(0x7f00003e9000-0x8)="2e2f66696c653000", 0x26102, 0x0)
ioctl$DRM_IOCTL_ADD_CTX(r3, 0xc0086420, &(0x7f0000f36000-0x8)={<r5=>0x0, 0x0})
ioctl$DRM_IOCTL_DMA(r0, 0xc0406429, &(0x7f0000474000)={r5, 0x7, &(0x7f0000c00000)=[0x8, 0xfffffffffffffffa, 0xffffffffffffff7f, 0x5, 0x0, 0x3, 0x5], &(0x7f0000d30000)=[0xffff, 0x78e], 0x23, 0x5, 0x800, &(0x7f0000e8e000-0x14)=[0x7, 0xf7, 0x1f, 0xffffffffffffffdc, 0x20], &(0x7f0000ba5000+0x344)=[0x6, 0xdaff], 0x0})
mmap(&(0x7f0000000000/0xf69000)=nil, 0xf69000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = syz_open_dev$mice(&(0x7f00004cf000)="2f6465762f696e7075742f6d69636500", 0x0, 0x101000)
syz_open_dev$vcsn(&(0x7f0000ed8000-0xa)="2f6465762f7663732300", 0xfffffffffffffffe, 0x6401)
setsockopt$inet6_udp_int(r6, 0x11, 0x67, &(0x7f0000362000-0x4)=0x1, 0x4)
2017/12/15 11:53:27 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet6_sctp(0xa, 0x0, 0x84, &(0x7f00000ff000)={<r0=>0x0, <r1=>0x0})
r2 = socket(0x17, 0x80803, 0x6)
ioctl$sock_inet6_udp_SIOCOUTQ(r2, 0x5411, &(0x7f000055e000)=0x0)
bpf$PROG_LOAD(0x5, &(0x7f0000ee7000-0x30)={0x1, 0x1, &(0x7f0000ee7000-0x10)=[@generic={0x0, 0x0, 0xa7, 0x0}], &(0x7f000000a000)="87797374656d00", 0xffffff7ffffffff9, 0x80, &(0x7f000000a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x80000040fe, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0}, 0x0, 0xfffffffffffffffb, 0xffffffffffffffff, 0x0)
r3 = syz_open_dev$sg(&(0x7f0000deb000)="2f6465762f73672300", 0x7, 0x240)
r4 = syz_open_procfs(0xffffffffffffffff, &(0x7f0000c7f000-0xa)="6e732f6367726f757000")
getsockopt$sock_cred(r3, 0x1, 0x11, &(0x7f00002cd000)={0x0, 0x0, 0x0}, &(0x7f00004ab000-0x4)=0xc)
setsockopt$kcm_KCM_RECV_DISABLE(0xffffffffffffffff, 0x119, 0x1, &(0x7f0000425000-0x4)=0x0, 0x4)
r5 = socket$netlink(0x10, 0x3, 0xc)
writev(r5, &(0x7f0000b5a000)=[{&(0x7f0000ec0000-0x3a)="390000001000e0036906ffff7f0002000000000006000000000001070000001419001a0012000200b600000000000008000300ff00001ee405", 0x39}], 0x1)
inotify_add_watch(0xffffffffffffffff, &(0x7f000002a000-0xa)="2e2f636f6e74726f6c00", 0x0)
mmap(&(0x7f0000000000/0xf73000)=nil, 0xf73000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$alg(0x26, 0x5, 0x0)
close(r0)
r6 = socket$alg(0x26, 0x5, 0x0)
setsockopt$ALG_SET_AEAD_AUTHSIZE(r6, 0x117, 0x5, 0x0, 0x0)
r7 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r7, &(0x7f000080e000)={0x26, "6165616400000000000000000000", 0xe, 0x8e, "726663343330392863636d2873657270656e74292900000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$inet_tcp_TCP_REPAIR_OPTIONS(0xffffffffffffffff, 0x6, 0x16, &(0x7f000033f000-0x48)=[{0x2, 0x2a88}, {0x2, 0xa75}, {0xa, 0x71}, {0x0, 0x8}, {0x8, 0x8000}, {0x7, 0x3}, {0xb, 0x1ff}, {0x3, 0x7}, {0xb, 0xfff}], 0x9)
setsockopt$ALG_SET_KEY(r7, 0x117, 0x1, &(0x7f0000647000-0x20)="0a0775b0d5e383e5b3b60ced5c54dbb7295df0df8217ad4000000000000000e6", 0x20)
setsockopt$inet_sctp6_SCTP_SOCKOPT_BINDX_ADD(r4, 0x84, 0x64, &(0x7f0000775000)=[@in={0x2, 0x0, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x5, @loopback={0x0, 0x1}, 0x8}, @in={0x2, 0x3, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7}], 0x58)
r8 = accept$alg(r2, 0x0, 0x0)
close(r8)
recvmsg(r7, &(0x7f0000f11000-0x38)={0x0, 0x0, &(0x7f00001db000-0x80)=[{&(0x7f0000f70000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xbd}, {&(0x7f0000dc0000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe8}, {&(0x7f0000f71000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x1000}, {&(0x7f0000a33000-0xaf)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf}, {&(0x7f000081f000-0x7e)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7e}, {&(0x7f0000f70000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6d}, {&(0x7f000020d000-0xe1)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe1}, {&(0x7f0000030000-0xfe)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xfe}], 0x8, &(0x7f00001d3000)="0000000000000000000000000000000000000000", 0x14, 0x3}, 0x3d5a1db4cedf06e6)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_MCAST_JOIN_GROUP(r1, 0x29, 0x2a, &(0x7f0000aff000-0x88)={0x8001, {{0xa, 0x1, 0x80, @loopback={0x0, 0x1}, 0x3}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x88)
2017/12/15 11:53:27 executing program 2:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000002000-0x8)={0xffffffffffffffff, <r0=>0xffffffffffffffff})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe2(&(0x7f0000002000-0x8)={0xffffffffffffffff, <r1=>0xffffffffffffffff}, 0x804)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
renameat(r0, &(0x7f0000002000)="2e2f66696c653000", r1, &(0x7f0000003000)="2e2f66696c653000")
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
gettid()
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
gettid()
r2 = gettid()
r3 = perf_event_open(&(0x7f000002f000-0x78)={0x4000000002, 0x78, 0x40, 0x2, 0x0, 0x7, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x100000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4000000000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r2, 0x1, 0xffffffffffffffff, 0x0)
sched_setaffinity(r2, 0x8, &(0x7f00000c2000-0x8)=0x2000000000400075)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = accept$netrom(r0, &(0x7f00002e0000)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f0000a75000)=0x10)
ioctl$sock_SIOCGSKNS(r0, 0x894c, &(0x7f00002b8000)=0x328)
r5 = dup3(r4, r3, 0x80000)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfc7000)=nil, 0xfc7000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = dup(r4)
mmap(&(0x7f0000fc7000/0x1000)=nil, 0x1000, 0x0, 0x32, 0xffffffffffffffff, 0x0)
r7 = signalfd4(r6, &(0x7f00002e7000-0x8)={0x5}, 0x8, 0x0)
rt_sigprocmask(0x0, &(0x7f0000eab000)={0xfff}, &(0x7f0000460000-0x8)={0x0}, 0x8)
r8 = getpid()
getpeername$llc(r5, &(0x7f0000162000-0x10)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0]}, &(0x7f0000199000-0x4)=0x10)
r9 = gettid()
tkill(r9, 0xa)
readv(r7, &(0x7f0000939000)=[{&(0x7f0000fc7000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x80}], 0x1)
prlimit64(r9, 0xb, 0x0, 0x0)
tgkill(r8, r9, 0x1)
mq_timedreceive(r6, &(0x7f0000fc9000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x4e, 0xd977, &(0x7f000080e000-0x10)={0x44, 0x1})
socketpair$inet6_dccp(0xa, 0x6, 0x0, &(0x7f000021e000)={0x0, 0x0})
2017/12/15 11:53:27 executing program 0:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
stat(&(0x7f0000000000)="2e2f66696c653000", &(0x7f0000001000-0x44)={0x0, 0x0, 0x0, 0x0, <r0=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
getsockopt$inet6_IPV6_IPSEC_POLICY(0xffffffffffffffff, 0x29, 0x22, &(0x7f0000b68000-0xe8)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in=@multicast2=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r1=>0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@multicast2=0x0, 0x0, 0x0}, 0x0, @in=@loopback=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000e6c000-0x4)=0xe8)
setreuid(r0, r1)
socket$inet6_tcp(0xa, 0x1, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$autofs(0xffffffffffffff9c, &(0x7f0000001000)="2f6465762f6175746f667300", 0x602080, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_IP_IPSEC_POLICY(r2, 0x0, 0x10, &(0x7f0000001000-0xe8)={{{@in=@remote={0x0, 0x0, 0x0, 0x0}, @in=@loopback=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@rand_addr=0x0, 0x0, 0x0}, 0x0, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000001000)=0xe8)
ioctl$SNDRV_SEQ_IOCTL_GET_SUBSCRIPTION(r2, 0xc0505350, &(0x7f0000002000-0x50)={{0x80, 0x7f}, {0x4, 0x738c}, 0x401, 0x3, 0x3, [0x0, 0x0, 0x0], [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
futex(&(0x7f0000003000-0x4)=0x3f, 0x4, 0x80000000, &(0x7f0000003000-0x10)={0x0, 0x0}, &(0x7f0000000000)=0x10001, 0x6)
ioctl$sock_inet_SIOCSIFADDR(r2, 0x8916, &(0x7f0000001000-0x20)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_flags=0x2000})
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
rt_sigtimedwait(&(0x7f0000004000-0x8)={0x7}, &(0x7f0000003000-0x10)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000002000)={0x0, 0x0}, 0x8)
r3 = openat$selinux_validatetrans(0xffffffffffffff9c, &(0x7f0000003000)="2f73656c696e75782f76616c69646174657472616e7300", 0x1, 0x0)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_X86_SETUP_MCE(r3, 0x4008ae9c, &(0x7f0000005000-0x4)={0x4, 0x2, 0x31, 0x0})
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp_SCTP_AUTH_CHUNK(r3, 0x84, 0x15, &(0x7f0000005000)={0x1c4}, 0x1)
connect$inet6(r2, &(0x7f0000003000)={0xa, 0x3, 0x516, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x834}, 0x1c)
ustat(0x0, &(0x7f0000002000-0x20)={0x0, 0x0, 0x0, 0x0, 0x0})
setsockopt$bt_l2cap_L2CAP_OPTIONS(r2, 0x6, 0x1, &(0x7f0000004000)={0x9, 0x87d, 0x10000, 0x7ff, 0x1, 0x5, 0x7}, 0xc)
fcntl$getflags(r3, 0x1)
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$selinux_checkreqprot(0xffffffffffffff9c, &(0x7f0000006000)="2f73656c696e75782f636865636b72657170726f7400", 0x10000, 0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000007000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
clone(0x40000000, &(0x7f0000007000)="093a62be755b716dafe92905f61abd6f8a4a7071c005d50727b334fbffa6226cf4ac162d28c16c30440309ea7417e1d571743f400392721299344dea909845ccd141dff5bfaee1f5498f1c4027e12e0120c1339adc7e721f579aa894ed51ee219df920ac549b65026af440a3142d89de65c9e337bb1802a40240b3f9c070808c1b18c1b107e8884af32a7ebcb3273164770a9ea3af500fe4725a8f75a9bf7ea2d44c67a3bc142361b20b7ee3", &(0x7f0000003000-0x4)=0x0, &(0x7f0000007000)=0x0, &(0x7f0000007000)="df0c1e1438956ccd3283a5b306a2a22cd7fee72ad59d13ec46e329a00a68d9612ab61f220b9ab68f784e8d61c39c78d149221f54ee715bbfcb3d68f6fbe041194a1168fe001cbdae9e18a1b845d9bac5751fe699236e0c")
[ 50.870859] binder: release 7369:7371 transaction 38 out, still active
[ 50.877606] binder: undelivered TRANSACTION_ERROR: 29201
[ 50.891197] binder: send failed reply for transaction 38, target dead
2017/12/15 11:53:27 executing program 5:
r0 = perf_event_open(&(0x7f000001d000)={0x0, 0x78, 0xdd, 0x0, 0x0, 0x0, 0x0, 0x7, 0x0, 0x0, 0xfa, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket$inet6_tcp(0xa, 0x1, 0x0)
r2 = open(&(0x7f0000c02000-0x8)="2e2f66696c653000", 0x80000, 0x20)
getsockopt$inet_sctp_SCTP_PR_ASSOC_STATUS(0xffffffffffffff9c, 0x84, 0x73, &(0x7f0000934000)={<r3=>0x0, 0x9, 0x20, 0x101, 0x9}, &(0x7f000087a000-0x4)=0x18)
setsockopt$inet_sctp6_SCTP_AUTH_KEY(r2, 0x84, 0x17, &(0x7f00007ac000)={r3, 0x0, 0x95, "0903deabcda278371ffb9dd893c0a0bb84d9183089f96bc5444be111b6649cd964dc06ec2f91b040aff73004b8dc59718d2545471dcda232002ed00a8f7971e96c032a37a134d11b3b71f91b4244a77f6521c1891a0928fb1ba4e98d56a6584272fe4f0a0c577486f12b2c90fbddd37e7ff38c3a1da37b3b77a7f9f6b216f8b856fe6f1a9a7caea38e2ca8299b15da6d56b9ab445d"}, 0x9d)
ioctl$DRM_IOCTL_MARK_BUFS(r1, 0x40206417, &(0x7f00005cb000)={0x8, 0x4, 0x3, 0x3ff, 0x7, 0x4})
fcntl$getownex(r1, 0x10, &(0x7f00008df000-0x8)={0x0, 0x0})
getsockopt$inet6_tcp_int(r1, 0x6, 0xa, &(0x7f00007ad000)=0x0, &(0x7f0000b16000)=0x4)
socketpair$inet_icmp_raw(0x2, 0x3, 0x1, &(0x7f0000f72000)={<r4=>0x0, 0x0})
r5 = socket$netlink(0x10, 0x3, 0x0)
ioctl$DRM_IOCTL_INFO_BUFS(r4, 0xc0106418, &(0x7f0000ef3000-0x20)={0x9, 0x1, 0x8, 0x42b, 0x6, 0xffffffff})
writev(r5, &(0x7f000010b000)=[{&(0x7f0000e24000-0x39)="390000001300090469000000000860fd180000400100000045000107000000140d001a000400020004002a00000000000000010c00001ee400", 0x39}], 0x1)
openat$cuse(0xffffffffffffff9c, &(0x7f0000001000-0xa)="2f6465762f6375736500", 0x8001, 0x0)
openat$cuse(0xffffffffffffff9c, &(0x7f0000001000-0xa)="2f6465762f6375736500", 0x20500, 0x0)
r6 = dup2(r0, r0)
r7 = ioctl$KVM_CREATE_VM(r6, 0xae01, 0x0)
ioctl$KVM_SET_TSS_ADDR(r7, 0xae47, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x0, 0x10, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x6e000)=nil, 0x6e000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000006e000/0x1000)=nil, 0x1000, 0x3, 0x10, 0xffffffffffffffff, 0x0)
ioctl$KVM_SET_GUEST_DEBUG(0xffffffffffffffff, 0x4048ae9b, &(0x7f0000055000)={0x80000, 0x0, [0x3, 0x2, 0xa07f, 0x470, 0x100, 0x80, 0x9, 0xff]})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
set_mempolicy(0x1, &(0x7f0000000000)=0x0, 0x0)
mmap(&(0x7f0000000000/0x3000)=nil, 0x3000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket(0x10, 0x2, 0x10)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000006e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = memfd_create(&(0x7f000072d000)="6c6f00d799b374b742d119623f0d81a2040e4f6852909800030d4f65fc586a30fcb7d44626e8de2ad2e607ceb5b024a776e45e0840c409e026d018d44c647dd7c19af1f22d2ab7b1d4e1c276065dc5c3a769aa038eeb6ffa39004ca2083816b8dc3a8193b24d8dce9ab0d84d6670d073150eebfc12bbe66980f842a01b98863944eb18e5ca321f256a308dc29f485d858954928c7a7fbac95a9cd70aad235459d9fe58", 0x2)
ioctl$sock_FIOGETOWN(r0, 0x8903, &(0x7f0000ff2000)=<r1=>0x0)
ioprio_set$pid(0x3, r1, 0x2000000000000007)
perf_event_open(&(0x7f000025c000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf72, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = socket(0xfffffffffffffffd, 0xb, 0x3)
socket$inet6(0xa, 0x8000007f8, 0xa7bf)
ioctl$KVM_CREATE_DEVICE(r0, 0xc00caee0, &(0x7f0000b13000-0xc)={0x8, <r3=>r2, 0x20000000})
ioctl$TUNSETOFFLOAD(r3, 0x400454d0, &(0x7f00004ee000)=0x88)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x9, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r4 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r4, &(0x7f0000436000-0x58)={0x26, "736b636970686572000000000000", 0x0, 0x106f, "63747228626c6f776669736829000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
r5 = accept$alg(r4, 0x0, 0x0)
sched_setaffinity(r1, 0x8, &(0x7f000023d000-0x8)=0xf968)
setsockopt$ALG_SET_KEY(r4, 0x117, 0x1, &(0x7f0000dfb000-0x4)="a23364fd", 0x4)
r6 = getpgrp(0xffffffffffffffff)
sendmsg$alg(r3, &(0x7f0000055000-0x38)={0x0, 0x0, &(0x7f000028c000-0x10)=[], 0x0, &(0x7f0000ff2000)=[], 0x0, 0x4}, 0x0)
ioctl$int_in(r5, 0x5452, &(0x7f00007fc000-0x8)=0xffffffff80000000)
recvmsg(r5, &(0x7f000027e000)={&(0x7f0000284000)=@llc={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0]}, 0x10, &(0x7f0000a0c000)=[{&(0x7f0000f31000-0x84)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x84}, {&(0x7f0000fdd000-0x9e)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9e}, {&(0x7f0000947000-0xeb)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xeb}], 0x3, &(0x7f0000af4000)="", 0x0, 0x800000008006}, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd9, 0x80000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x101, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10000, 0x0, 0x0, 0x0, 0x0, 0x4000, 0x3, 0x0, 0x0}, r6, 0x7f, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f0000940000)={0x2, 0x78, 0xfffffffffffffffb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffff, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x3)
r7 = socket(0x10, 0x3, 0x0)
write(r7, &(0x7f0000723000-0x1f)="1f0000001a001bf200001321fdf3167600041d0100008d3d93391a0001454a", 0x1f)
fsetxattr(r7, &(0x7f0000793000-0x89)=@random={"6f73782e00", "736b000000000000000600000000"}, &(0x7f0000e24000)="00109879b2923fbf3bde6b06ecd03c8e937cbde652ceabf84c99d98760e033ce24f7b83d687fc24bcc51ca31bad48135f375088e3e090c925cfa4c010180442603003a79a593142e686c16c0b0748ece0fa85f7e20e82099b7ca044e718565d9d247ad516d4ba03034eed3", 0x6b, 0x8000000)
setsockopt$sock_int(r7, 0x1, 0x1, &(0x7f0000049000-0x4)=0x7fff, 0x4)
[ 50.922688] netlink: 16 bytes leftover after parsing attributes in process `syz-executor4'.
[ 50.947063] kauditd_printk_skb: 220 callbacks suppressed
2017/12/15 11:53:27 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = creat(&(0x7f0000215000-0x8)="2e2f66696c653000", 0xfffffffffffffffe)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
socket$inet6_icmp_raw(0xa, 0x3, 0x3a)
mmap(&(0x7f0000000000/0x2000)=nil, 0x2000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
clock_gettime(0x0, &(0x7f0000f42000-0x10)={0x0, 0x0})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pselect6(0x40, &(0x7f00008fb000-0x40)={0x2aa6, 0x8001, 0x1, 0x5, 0x1000000000023, 0x1, 0x0, 0x6}, &(0x7f0000001000-0x40)={0x2, 0x4, 0xfffffffffffffff9, 0x100000002, 0x800, 0x6, 0xfffffffeffffffff, 0x3}, &(0x7f0000707000-0x40)={0x4, 0xf9, 0xfffffffb, 0x80000000, 0xfffffffffffffffe, 0x0, 0x0, 0x7}, &(0x7f0000ce4000-0x8)={0x77359400, 0x0}, &(0x7f0000f24000)={&(0x7f0000001000-0x8)={0x80000003}, 0x8})
mmap(&(0x7f0000000000/0xf84000)=nil, 0xf84000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfda000)=nil, 0xfda000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket$unix(0x1, 0x1, 0x0)
mmap(&(0x7f0000fda000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bind$unix(r1, &(0x7f0000ad0000)=@abs={0x1, 0x0, 0x2}, 0x8)
bind$unix(r1, &(0x7f0000c1b000)=@file={0x1, ""}, 0x2)
listen(r1, 0x0)
mmap(&(0x7f0000fdb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = accept4(r0, &(0x7f0000fdc000-0x60)=@nfc_llcp={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0}, &(0x7f0000ea9000-0x4)=0x58, 0x0)
ioctl$sock_SIOCINQ(r2, 0x541b, &(0x7f000045b000)=0x0)
shutdown(r1, 0x0)
mmap(&(0x7f0000fdc000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp_SCTP_PEER_ADDR_THLDS(r2, 0x84, 0x1f, &(0x7f0000fdc000)={0x0, @in6={{0xa, 0x0, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x7f}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x200, 0x10001}, 0x98)
r3 = socket$inet6(0xa, 0x400000002, 0x0)
mmap(&(0x7f0000fdd000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getrusage(0x1, &(0x7f000084a000-0x48)={{0x0, 0x0}, {0x0, <r4=>0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
utimensat(r0, &(0x7f00002da000-0x8)="2e2f66696c653000", &(0x7f0000fdd000)={{0x77359400, 0x0}, {0x0, r4}}, 0x100)
sendmsg(r3, &(0x7f0000f66000-0x38)={&(0x7f00008d4000-0x80)=@generic={0xa, "daf8ffe6ffffff0001f20000000000b61b340e63f8ab691822e903e7d64ac8fef9507f000daec57f844686fbbf26093d6b53efc1cb2b880001186a68506776e9eba5ebd039273202a52700faccec35120ec64fc333c1c99287b26eaece2900727e347f814dc256ce82cb2c8080000000bff900000000000000076167b456"}, 0x80, &(0x7f0000f6c000)=[], 0x0, &(0x7f0000f6c000)=[], 0x0, 0x0}, 0x0)
syz_open_procfs(0x0, &(0x7f0000001000)="6e65742f75647000")
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0x5000)=nil, 0x5000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$llc(0x1a, 0x3, 0x0)
setsockopt$SO_TIMESTAMPING(r0, 0x1, 0x25, &(0x7f0000002000)=0x1, 0x4)
r1 = syz_fuseblk_mount(&(0x7f0000000000)="2e2f66696c653000", &(0x7f0000001000)="2e2f66696c653000", 0x0, 0x0, 0x0, 0x0, 0x7fffffff, 0xfffffffffffffffe)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = socket$inet6_icmp_raw(0xa, 0x3, 0x3a)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_CREATE_DEVICE(0xffffffffffffffff, 0xc00caee0, &(0x7f0000064000-0xc)={0x1, <r3=>r1, 0x1})
perf_event_open(&(0x7f0000483000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11, 0x8, 0x80000040fc, 0x100000000, 0x0, 0x0, 0x0, 0x1000, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xfffffffffff7ffff, r3, 0x8)
getpid()
ioctl$sock_SIOCGPGRP(r2, 0x8904, &(0x7f000016a000-0x4)=<r4=>0x0)
fcntl$lock(r3, 0x8, &(0x7f0000a59000-0x20)={0x3, 0x0, 0x4, 0x8002, r4})
fcntl$lock(r1, 0x7, &(0x7f000082b000)={0x0, 0x0, 0x0, 0x9, 0x0})
close(r0)
mmap(&(0x7f0000000000/0xdec000)=nil, 0xdec000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r5 = socket$inet6(0xa, 0x1000000000003, 0x100000000004)
ioctl$sock_inet6_tcp_SIOCATMARK(r5, 0x8905, &(0x7f0000b83000-0x4)=0x0)
ioctl$sock_SIOCGPGRP(0xffffffffffffffff, 0x8904, &(0x7f00009dd000-0x4)=0x0)
getsockopt$inet_pktinfo(0xffffffffffffffff, 0x0, 0x8, &(0x7f000006a000-0xc)={<r6=>0x0, @remote={0x0, 0x0, 0x0, 0x0}, @loopback=0x0}, &(0x7f00005b9000)=0xc)
setsockopt$inet6_group_source_req(r2, 0x29, 0x2b, &(0x7f00005da000)={0x4, {{0xa, 0x1, 0x5, @loopback={0x0, 0x1}, 0x20}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0xa, 0x2, 0x9, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x800}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x108)
ioctl$sock_SIOCGIFINDEX(r5, 0x8933, &(0x7f00002bf000)={@common="73697430000000000000000000000000", r6, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$sock_SIOCGIFINDEX(0xffffffffffffffff, 0x8933, &(0x7f0000194000-0x28)={@generic="95a7545d8c97fecc27f26e4d97bac4f3", <r7=>r6, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$sock_inet6_SIOCADDRT(r5, 0x890b, &(0x7f0000d04000-0x50)={@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x80000001, 0x7, 0x0, 0x400, 0x2, 0xc100bf, r7})
socket$inet(0x2, 0x0, 0x10001)
connect$inet6(r5, &(0x7f0000788000)={0xa, 0x1, 0xfd, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x4}, 0x1c)
mmap(&(0x7f0000dec000/0x1000)=nil, 0x1000, 0xfffffffffffffffe, 0x14010, r1, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet6_tcp_SIOCINQ(r3, 0x541b, &(0x7f0000e2c000-0x4)=0x0)
ustat(0xffffffffffffff7c, &(0x7f0000834000-0x20)={0x0, 0x0, 0x0, 0x0, 0x0})
socket$netlink(0x10, 0x3, 0x15)
[ 50.947068] audit: type=1400 audit(1513338807.198:1146): avc: denied { getrlimit } for pid=7428 comm="syz-executor2" scontext=unconfined_u:system_r:insmod_t:s0-s0:c0.c1023 tcontext=unconfined_u:system_r:insmod_t:s0-s0:c0.c1023 tclass=process permissive=1
[ 50.986708] netlink: 9 bytes leftover after parsing attributes in process `syz-executor5'.
2017/12/15 11:53:27 executing program 2:
mmap(&(0x7f0000000000/0xee7000)=nil, 0xee7000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f0000277000-0x8)={0xffffffffffffffff, <r0=>0xffffffffffffffff})
connect$netlink(r0, &(0x7f0000ee7000)={0x10, 0x0, 0x1f, 0x0}, 0xc)
r1 = socket(0x11, 0x3, 0x1)
socket$inet_tcp(0x2, 0x1, 0x0)
mmap(&(0x7f0000ee9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_MCAST_JOIN_GROUP(r1, 0x0, 0x2a, &(0x7f0000ee9000)={0x3, {{0x2, 0x1, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x90)
setsockopt(r1, 0x107, 0xf, &(0x7f0000155000)="2040016f", 0x4)
sendmmsg$nfc_llcp(r1, &(0x7f00009bf000+0xfab)=[{&(0x7f00002b0000)={0x27, 0x4, 0x0, 0x0, 0x0, 0x0, "a284027e94775bb0a61c0a37f98a86d1539bcef05a11311b56eb8e513afa218479b8c54121276c0a006715b1dd24ab77a39ed8c2a4da5ab82afb820330e4fe", 0x4}, 0x60, &(0x7f0000887000-0x20)=[{&(0x7f0000ee8000-0xd7)="06000000acd8d2a9db76dd0ee402ac94a2c02307d7ba52664daaddcd66b0765b4c31dd367e8bb450819c5d65db8f69febe99f87382d77ebe61190f6dd72c71f11c7b86a0c84d45a56b3544baa5ef882e7f712534c1e7e18c8394db6fe93982fd04ffed6c860052ba8864828a38156029ce3a130b93490e0b4848f7045a9e0c141f54f158b97aca9a5b7bc26a1b22aeeb048998d417c4828b00cff9fb0bf74f6d74f485fb4040401344ab9c9a1e4bda6520640979115e450b667f20d9f65c7ae8b28cf1a7637441a5b8fd5d0b54749f84ce4dbf1f246aca", 0xd7}, {&(0x7f000050d000-0xa8)="26533bc4100684dad1dd3728bd0f7dc9c9ce7c086bce8a11a20218ef2f7a5a50b22ed6ee4425aae21893901e4c642f009e6113cbebbbc1667062f16e4a89c75ec9a7cc0c97a1e9e279af8c6fbc0d28f426af3fc9471d366548ddbecae317bda100907fed4dbcdbd0215881c0a60cce3bbe1266e4a91630dfd4463c00ed92d703879adaf833b1038b882e4fb814a0c7391b78017d18f888772f4519d238222cc84d7ef0bb15bf5fe7", 0xa8}], 0x2, &(0x7f00008ae000-0xf0)={0x10, 0x0, 0x0, ""}, 0x10, 0x0}], 0x1, 0x0)
socketpair$unix(0x1, 0x2, 0x0, &(0x7f0000653000)={0xffffffffffffffff, 0xffffffffffffffff})
mmap(&(0x7f0000000000/0x5e1000)=nil, 0x5e1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f00009a2000-0x8)={<r2=>0xffffffffffffffff, <r3=>0xffffffffffffffff})
vmsplice(r3, &(0x7f00005df000)=[{&(0x7f00005e0000-0xbb)="31", 0x1}, {&(0x7f00002d5000)="0369d2149b561180da2ed3b35bcb44d24b3605a3ba2af34cd8406525d080e3c746009739ffb4507fad5832b1d28be74afd178905a7bc7c5921d30b7fcdfc04bdb7eeb25ca8f0bc67bb39ef2d395eba261e85b6e6e37085918ef51097f1f1d8870552c815f3", 0x65}, {&(0x7f00005dc000)="98c5a6bd6af02ec875048eb70c8b24a6b141c87cf888d0e2b16b95b118b1302dc17114fcf76efa01c3f37c579697e8c971e5b24663b73823ad6b13c31539110635528c2eb79713dc27fb565e0b4b573910d5d6b8394b04232e57836d7f3bd46e3680a6ca8c80279dcb6515a014998c6f1950ff06e8092b53dd2cae94c7032e781fdfad4b912ea25c741bd62615d2fe5ebd4f2db59288fa5a268cbe8dec4df7c23c4e18d45489ebec8a6dc82b8874a2c3e43595f2e5f27065dac30f430af2dc527c9aabaa259824c153000000a4009d617f78b2294930b6f3282dd544be250ec22de87612d9ca2987041aca82286b2e9ad4aa146543e85e1a53", 0xf9}, {&(0x7f00001ac000)="b1fac83360726cffc0b7ae242b6b043417eccaf7a8fc19a59b39866d3388c1e409b2a4a5944327596585d0380d9c35ee182936eb8ea749237e2d3ccac42e9146bda01634c48786e45b33d18750d594f26f124efb00b6f8cb2c570144a5b1ba", 0x5f}], 0x4, 0x1)
vmsplice(r3, &(0x7f00004e8000)=[{&(0x7f00005c1000)="693f9b353c0105ec29f23a401f98333bb19178e37abf82b13b0e9407e1f9e190d47bfb04703392389dcb915d6e63cdef20ab1b889d424840226a87853c9ebb8b50b9eb1e84de01fdecedde0ebc5eeeec47e6f784e1f681ffc34e3f95b6279d29eef2fdba7b3c", 0x66}, {&(0x7f0000068000-0x3a)="938f6269772c941e127df3598ca6e083a7e2d5fb172888b672670d100c382c5fb8d72411a73eff1393691eb5a6e89963fa27f99fe45cd0a147aa", 0x3a}, {&(0x7f00005cc000)="2c1ed2c6e46a222a0c818cc958eaf633fc3568c46960f9fbfd334721834b8386f4a5810110ed1e9f57c6b862acb84de255ee85fcaac10906c8832a62fdb6e93f9ad757142a18411b1a0164048863302c0f981aa1add2920d9473e2b18bbfa0570e1b942b8697212a838c38357a254de87a3dc2579e46", 0x76}, {&(0x7f00005cf000-0x2a)="86f6ed9e30bf60b8df5f342da795201d616dc48a1c1ed3f704ab7fdf775108aecc9303804b8cb3ba58f1", 0x2a}, {&(0x7f00005cf000)="3bec1c5d5a3fcaa326b94943cdc70e1e45cfa6444da55da5c8fe54cbc7ce98a281d956aae2b4dbad4c8b042b38bfcf91852a604f801a32be79da7a47c9d8f376", 0x40}], 0x5, 0x0)
mmap(&(0x7f00005e1000/0x1000)=nil, 0x1000, 0x3, 0x32, r3, 0x0)
mmap(&(0x7f0000ee9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
connect$llc(r2, &(0x7f0000eea000-0x10)={0x1a, 0x15, 0x0, 0x6, 0x8, 0x5, @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [0x0, 0x0]}, 0x10)
ioctl$DRM_IOCTL_GEM_OPEN(r3, 0xc010640b, &(0x7f00005df000-0x10)={0x0, 0x0, 0x400})
r4 = epoll_create(0x5)
mmap(&(0x7f0000ee9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ee9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000eea000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000eea000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_GET_MAP_INFO(0xf, &(0x7f0000a32000-0x10)={r3, 0x18, &(0x7f0000961000-0x18)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 0x10)
mmap(&(0x7f0000eeb000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_GET_MAP_INFO(0xf, &(0x7f00000c3000)={r0, 0x18, &(0x7f0000eeb000)={0x0, <r5=>0x0, 0x0, 0x0, 0x0, 0x0}}, 0x10)
r6 = bpf$BPF_MAP_GET_FD_BY_ID(0xe, &(0x7f0000599000-0x4)=r5, 0x4)
mmap(&(0x7f0000eea000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000eec000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000eec000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$BPF_GET_MAP_INFO(0xf, &(0x7f0000eec000)={r6, 0x18, &(0x7f0000eed000-0x18)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 0x10)
epoll_ctl$EPOLL_CTL_ADD(r4, 0x1, r2, &(0x7f000001d000)={0x10, 0x0})
vmsplice(r3, &(0x7f0000586000)=[{&(0x7f00005ae000)="", 0x0}, {&(0x7f00002c9000)="", 0x0}, {&(0x7f00005db000-0xfc)="7a0806226a8e850d423de441083f7542652f60dede4b8ae0a4b6f1f849d830a852d692cbe33720396d3e145a281f784d70486f140847338a3b6c9fc7be24211fc4911642b5b7231221dcad337fa55a5e21babaeafae8d9d565cc6c9c3d9c25d5bbd70356ff3cf39fa44e200bedb498cadf404587add7118dadb28ebea02d546b42ea1e16e322a6f85b715ff4aaacc680c9c4663b1d60eaadab315d1431c4d0d0436cea311c1b11c6d0f5069c9ce67024cb1bef5a3e12b3b4b5af88b1330a852a3fbe16acfb819327ad4d596b114a871669f1dbdb46adb7a0dd0123cb6204631c44d57b924a0c63528a0b597e5fb19abdfb180f20ea6792b54837304b", 0xfc}, {&(0x7f00005da000)="e694c58f72b6b7aadac4d231ab08b5e8a154beda67ce6bd42dde49a53edeca70c5a7d5e7a34e9c5ce20b58a7e84205dab4274c34a8978918f5f3c2adc96b59c047dd431e326e47dcaf6856537d10f8e09d1a0b5a2463f8e6194f9d8d6e29b517e8ece1b36e8abae679b9c6254609d6b7e33a0a33e78798836f9283fb11e2d41ef5281fb15eb8abe37a339a5bc35f755d990d3c0ff1809ef48e79cead5bd223c64181b6ab1da8c187ee4d350b0571b26a2263d43764c2b548dcd47a31f18dc62d2651a42f35a0e8322d1ae5a9e715b1ddac1b8db537d320461961fb0f09c75bf7451b4f4f1cf7119fc1340c3dcf61dd8ef68ec6ffe31f30004e64333d16968c64b54d06603d22ac6617880f9f333fca4c36fde16b308a072816352fe73e3fe5a3ab4a828d9fd1f9bf4041d20fc9533ceb33653055c6df8ad03c6514f87a52e70c91431640c1f095550a5522e6a90890ddef2ef3905bf381965c04c67e777a8a01e6c08499e032a536ca5a57dd02b08fe478c7cb2c3e4e2f71d871039e55ef5bad4aaf1e415321f5d697cabaa2735e521c8d093067e4e8f4178342f2bf7de2230774dbc2f43204a27aa2c2f87407b9f3dd812c7c9f85f20d8df38a8bd131da2c8a6d7962112a04660469e8c12ec9bc6c0673adfe7b40c34d9ac0ebba12fe53579cfbc3feaf5b302f92a60e0ba7d58990205e8138b039c9a242fdd665d10d9fa5497828abe210aaf02507ea011aae3b62a7530f8c1813f2d75befc9bb1a245d7f8862e2f863ff5838548282477a6f54a9d67f87912f443faffbe20ba3d772e5971266c5af3cb9196a962abac5c692384d001cb22d7dd37638cc86566430a9d52e7672b5bd6546139d5b5a2e3571872d622c55a49beb684b06d21513ff95bccd20558c4dae6f7bdaab127d3118ece05bc910d596e4c6d9dc39ebca5a77840ecd1f9afad02863d52cc5a37fd99570d075c2c1217f36e7572beabbc93f4f669ebdd1dbca62dfeb2a40d98747b9b0d2db07920fc478ac4a98c387d696ece3d3109eda612e925f5c34eba7c7cd5b477e7273b1f1aa37d2f030fa24bd0b74bb667af850d1a2142c5658fa50909033e16b42c00ac7ad4c6010a5c6f2ccfa811cf3a7746888f8f83ec2b8fb240476d473a32fd63b2ba3f0972f36209e52b57d915041cb4ceef2ced6ad2755de702fef4872384f748ea02dc4925ce91ab9fa5df8dc5d1f9d034e22136b9f80dc505496f5986f732265745421eef04d3cb491891673b16cd10d77d7323abc610a4614e823c9e9f8b854babda2744e06abe8779229933ec8675b54ebd6a5b66e324440ed40208c9eaa0ec8ed61835657c222a745580dea5b76a981a5191619fd61b416201c52172da249a2968f1d3a5ab1b2f94b5806c136b5dcbfe3b9006b8e9a1fa0518f563263ba686b5ffa444528022a0ac01bc460957a25cd6d2b05f4d374c68003e8c3206dd6d2fe1eb3b2496688441b1b0413466e4a7740105d8b140bca5cb4bcafe5af147adc36f6747f850696e5f031e771f6877336eea29ff35f65b24560c12567dad1ebaa6f2b7e0f77c998dc4795c15612dd99ecb74c0fd53c4c0f21a3fc77a717bfc6f012da3b275d77dbcb1910b01af6effc85486cb7204728a2bf36d80386c85a4350950907767a6c5ced52b7bf95ae810a1f1a6af95c8eb89cd5a33d58bccb8cc8840d8169a91cef3bb99aa41deaf6bb141cc48653a897f4b21c51dcb7df3b4c87cb4e1d91816120d077c815b6d82037832e9751050af8e66c2ee3123739618b478a72a3aa92dda579657917d59d2351fdb53993c3cf710bcb82049f30eb3923569ca403548330df8e3e05d06a8680f249a134dd0adef222eed0fecbeedf1ad87e0fefed5af64e9be16149978fc0848a76a96e9653a86a2cce644137af59e4a7781d6ec192d0ee8423beb91c289f602aa38dbf9c81d70ac75a280f280103161ca54739175cb49b2f180aa3c0ef1f1b7f47bee9519df323827c52a08cb4e0f1311aa075e09ced40e67a583cc82944511549361f6bb72ecc59dc8cdc9b2af8e52310ab4cdffd5546a87197329c19b5db689016a721ed0929f83f8f50903c8d5d18208871e57543f6d4a844a56850694b0c5affa380584ee26c67e45febde9fd1d98c3eec3ac55410a3cee4c10da57601c8e69b764949600110e9b952ba38623bce60c5a29a171a26332e73c75cad1a46b0ccd842bd1a6e809294a45f222281b4233cec37c4fb4438a4d5e71b56d1af16d0b53ef2a9eec684e9ba82b2d8edc1233ef2e10969db99d06d57d8245cfb0fee5fcc458a9ac687a3624aa3c2a2e0490d36fca1ac734eca3d930b7544143b47726094e65797a370c0668cccc653a69e33965b7db55dd022fab9686c8387fdaa676567094214d4fc53f32bdb1a623003163dc0b9619e7b2ef7643524229df13dd67e0fc7f75cb43aa255ca1593aa433074a259a2f1e2484b8005c459a000ab327c5a9d69f52805bc6c9893df1da8ee19c48f5def08aaf7d2ba3f59ba9c1f818d21dbf8a6a8e696530dac78712119ca7003ca4df41ddff365503cca845e70a42f1e50eb244cf642ae0ed94f7f507f3be866ce7c1af6d33e7c8f50095cba15fb43b93751d33d3dcef32aa4d3b8fa538f323b5d5a27e29c3ccb6cfe4f349a8876111220f42b74cc384ca49cef5b785447353345fb7149df1df66632a050732c28603c56d8317fb65141ed2b63094132f45620f17084d3b28ef20ca2c8d56355142a28a940ca1409063b4fc81ea9a432e1e252e082d6cad4e4c28076b1e4f84202902dbacb8056e37585f6528c444c23a1075a7cc549df5411506aba606ed682c95eb0bb6142f48ed66bcefc5865e654e19d6496fb1249911645a2e6f1d0a846ed402f0ec57d5abfd8c32c97cc3655c61766b031864585a63bdcfc7f44ab0d3bcea6d993e1f4160ae81c5e90cc1a149bfd02473fd95c09c1393883b71ef5e7a1e887f5c0cd1f9a4e2121e8f734684899b5cc1c45763d0e0291df97f98894c69fc991fb22f8d1712bfd3ddc56b7a2eed2ebb1df72e697c58be65f7fd210b7b7266f8ee5ff1d3d2e634d9e88fad7ff7396addd8378420ff57bfb8ae5c2137e6013e20a26d530632dc27913dbc7247aad511737691b8a4933efa2d7a9a6a14206a042cf421f260d70905b8824cb1a7386d88c0fc72a5b78f3a5adb31802c8d159886b1368ee621de182c5d1b7f68626c17c21fdf50c3917a0c5b1d0253668dbede4ff4902cba03d271d8d6938cdc20b32d849037eefc7261bd5eed02861bbefd34604eee5c0f87ea13ae0de32c694d755506b42483236d2d65e56692223e96c1bc0ce795ce5a8ce840f7ea5d116973b9dd6baac1652b0d6ca9221dc6142b1d188c927d6a814ec1f23a4569e8b0f6baaad9010cd5b491615b064914e7aa6da151293020901ca97338d083af539cf516036f30ed55c621a13116cdfddee925791156ed96715d54c7f4cc46f262eb87b0dd1f0461d6881fd1200698ee5112bfbbe0323622a585d46ff166c3b4673990219974ed576153d9070ec8d86c2bac51b8ea0af39c8669f5bdb2f45e69bdf7b0c0a034ddf8b05d97236cf6f74d1737fcbea7cd5a64aa636d64e20a601019943e00c0ecec6512a85a16a120cdf0ee0eab2ba4e346977bd4a6f1d09905be422b5a60813744e5e6aab0ad8d3b28a4a9892346a5a1faf1cfeaa742b61acca24657a88cfc1fc5d321058f8f25f9a55208cc3e640818b17eabadbcf0b95a2554d732e7806989f30d8082f5971c55f81531dd0ba79e57b36e9613c3d2d209981efde46c1efb00f954a49da27a1f4c741bead57c439011f7a03962a81b562328ec8d423faa02bcb3bf5ac8b135a82dea3061fb74c42ad9b81423f61526e3efda76a3bc8cdea91eed5429d3ff40c8bfcccbb198450ba3f06dcbb75337bbed43a2b0fbd91c58e244e8cbd40a9ae51562acfcb5ef2fa6c1de5580660353ca0f84882509998fa793b930d0f65317f0a3dc37daaa83a86e6ac519e0870509212fa6e9404d9fb5e3993da4330a119c263c3b74474e6eb86ff907e88b74dccc8eb5b988442401eb9f6e77b1da52838c115f0137df05ace5675b3c0455ffdb096200fed048eee4ecf1819cb8e95d98202ebe183737eaf2e1d4b4d9c8e159801aefaaca53eb419b2a710ca51be7f1b970f148b7602a412c7b3dcaf7e89f22ff2a9abb0726c13d444936210bccc915646004c47830eef0b85f5826953a2e30a98aa37ffd97c2f158b62f9d2bd69dc8b567703d2cf4c211115dedf7d93f8d70d34728114c6f2068a6be487ad4edc381d90478c2bb4181aa11423dbfdfeb5a2928d29fb16c651fe83d900cc5c6403c0875d473c0a862e947b9556fe9d9ebd666dab3195777909f143aa541e3482c7b34600c17f9f81314fcaf589fee8cca2aacffdf5f2a9a95223f0f2f58a4d70098d90bf02985bd06af7c20b0935cc8dc5c4dbff86e2bbf11416343ada64437a126fe49f1ba82ceffbe578a1091e4d82434ce049a00c7b3c689633563630c09bfbf8c0a3d981ad37efd6474e1d0130796dbc2990c271c1569b671e9a9774d80cb0994a28e408460593f9d6bb8415ed27a6876d265295ef9dd1821d838c8d22992baa13630a7097812c9affd004477509a7ca19c983989c54be2a68d2048fef13dd42b234d5674856849f5d4ea5e5a6285273629f45a9bfb97cec3e9cb44fa639f4622da6e7abd9b9cc70b6d01bad68dda64222d9cc853ab1f0695d497fe8ed72e15aa561b8bd924334237594649325103e3de6c2bf95b9cb91eee09084ae4d7589e3537e4f4c1d7874b015ea5e1270a57669c2cc60fae0de20038fbc8545c8d99d2bf55b0ac4a5399cbc50bb2087b5e18382c077b21517c1f4d5e0d6da9cf891b2e566a3ac63c3bfb14e81b956c7ae485248c4898e341a31792ff50044047c4d1f95f5eaa5b3843e46f53575104b351e6cae4ae048f4f64b948248a6d49de07bbd7f096f113319621b81b03bcfd929b0afc4abc15eb615d535464ca6e0ce993388c36228dd0f0f9ff8d0f21baeb40e78050d345be086dab56959e4f1b0b5a173baa8ba63eb8c2dcea98772331f1ea2481dfefbd8dee78556e8e2fc18c9ee6ad1ba32989add9e5486d3027f3c28fd7be649ee8e18e3cc83844abf8e591b12e202495ccd2d4eea49d1e63203046b81ac03171c707c7965126e77f88a15b7bb777366fec70a096a810f729c99e6ba22e3863f0bd727f1813daf2bdf67a4d9550a7d95c98381f652974910beca6ad5c2689b3b81e25b95550c16e2a1417644a338b8d6e308c721e90584293b3bfe3510924211fb957bcc61a599557b3010d954c6478d514e658974e3f2310c2352c4212024c89ec9aa7b8d7082f94ed7e76b8f7424a9706784420cee05ac7c9469a8114806efb25325999f65aa06176b899087c1bf1250351964278c6eaf401468069ddd48fa27cf0cf8da29fe50c70bfec042b8cdf2306206487668b2f0e8b200603ef8129cd3fb1c3279f213b03bd483cb18105928fc2364802c220824a70d333fc23a3475acfb12d60ea4c6be25cfb85312baa06545c25828531ededf2ec8a6c31f991db589d79390431c7278cfe518cea894c4e0e56d8fe483c572d2a073cb38ff6548ba7b8b4316b01d2837f14f4e182338f27e8eff31a7b2ce81c7f88ca089b449ae2199b068c202c72588b9f8c043feea306d07569f3f729b4156a63651988f3649ca4ec9007ba136d8c711e3fdeebdb2d2092e41760d3f4c21d17a082daf1ad8c76d6df9f5b95d", 0x1000}, {&(0x7f00005da000)="7cd96e255e679ce49df9d81edeaca03c8c7cd4c6a52d6e5d317e0d5a7320f0f7e6e806e7199bc80396e03f123d44800002dad7eaf267919ef1c1bd5e4c9df83d8e93cef97281d5fefcd92b4119ebe4a2568338da9016665d5704eb5be28c610899bee9e136f4dd300fe79e04dc4d4d3058efd7f55bd89e601da13fadaa07c0db4692942ef154504e23b532e5c9ef74f70b0e164a8edeb36ffe505c68080f3160fa", 0xa1}, {&(0x7f00005db000-0x2)="aea4", 0x2}, {&(0x7f000015d000)="82045b3bf5bad0c4264f0eef0b7997b920467a520e435b0027aface9a4b9d343113ac2219fb3e227842a3b442e47217d21c620bd4b10a6a30dcb134ecfbf5212ea4697917cb9c05758ee54eb8ad6cb1a562fc212f14cd0e7d2afab75351bdf", 0x5f}], 0x7, 0xc)
mmap(&(0x7f00005e1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
writev(r3, &(0x7f00003f1000-0x40)=[{&(0x7f00009e2000)="cf803cfe0327079c8d1117bd5d2f5407991947d66e1c2aea0ff89349e2e35794f59f5fc26000a71efb2f9e5e6e6e8017e64a93974b9992ec6b23e9d0ac2c82e43f327a", 0x43}, {&(0x7f0000591000)="d9eac12a890e", 0x6}, {&(0x7f00005e1000)="1a72b5a01d62bddf93709bcff5f8f26cad96caf9d60bb777fcc80bea3201fea42470b660f9f5be2066e3063fdda2561672de0db6a7c8faed553acb3bf8a0969995f9616e3e68bb2c3e33eddf24a7523bd7e37f97e0e19f9d12e43d3f5e029e13d9456b99e5f01c1a0ae9937931143b6166126338385e13e15c5e36690ee60139e947c784ddcff04aba177cfa82ca891459173d7dccf550b54a3ecbdf14679b4632f25bf114e925079ddcc14e8d18e43a0f3e473be19345152813bcece5dea06c17d7f1d9f95a8fc37945d90e6bb0e3718f9fb5800b9118e0c651e774f6d89ad52bf1aa41e13d77cf6e6ad1f6ad412c8119d0e4c3613f09fbc7cf3806fe6be71ad9cac1d613fbcd60d1453e6ccf627f5eb2f196cfbf44febd216df53fce988f221e9f412f13f69315eff84a6110f3d6e26cce54294e592a4072f2b34d0645bbef2f34a88613380fba4d19008a961313e83ba74986ba1e7190ca131742dbfc696a4eb72dbf481bdf23bb8b8951fe82f398f65d5241c42ba662d7350d1a46d6b2fd34049fae7eb4863bfb60da15b7e5617534153fa2a1cd285de4be515489cc1f558335007e66e16049f290cd9154ec1d1ef34eb22ce3ca82d3acd02ccde3b9d068dc087663fc77acfae4ed53e8b9abad905e2d9806d12ad3fb93b7d38255ecac4a5c69bd891b1f56ad1e23fc0355a388ab5640bdb71d8f9607f457ffe9c96c85fa42dfd4e9e4bc629b085a08134acdeb2418ddf1c972a00ce41d2f749273697cc734210dc1bacf3d920703514dd4c337efe47e9fe94e0f2532735d67ca78f73d6a7ab767e615ba7c14101e1f363146773617baffae5ffef939435cac22b5dc872e5bf14866e978fd040166e30d3ace68170019b004caff93dbecc676bc53fd261709acbe4c36834c0d46dd74ebbc9ced25db42bb477779a1db76c69cd2b64e7ef76e96837e0a5cf96691d29d75fcdb08f73902cce160067e732e2fd02c94f3fff6635fe7981dffe58dbc3f4a5ee21e1b377a3f40aec1105808591b5762cebae496d826b276d5c1748e120fb2554cde01056199e7897e6cd4a1ece902116af1e9ba9eb132d2a0439634e3b5a58c02aea694388a1ab67d2ad18aafc446eef2eb3903fc09b6eb240263862af73ee04357da0b66eaa11952d2b003e3ee7747256f9863e08ec08026c6df949d4554150ba578563a5e7bc8251fb544e449251da119605001d99012aa2d5ecb7e81c97c84353b3a20f1c107aae7351f72f6a6b1a5caf087b74249c4fa5e1582d4362787af2ae093e65dd60ca661c3be00f92a7b30788c1d5984c8ce7f8633eef5765032e6ca37ba9eb71d3d9c7cecc47aa8147972664556ae67c215fd3f2a3affb881cfae888cf654b6a0acc4c462bcc2ca5a9035941c503c1aeebf62474b536934300f47302f19ab17c85443fd1f584c63643b226c34843b62184d6adfb6c632ba7b57fd870fdd0850de159c2316420410828946d216829cafed172d2a24b57703ac0099a07b983194108815f7fef73efd7993cdefa137752373bd38a980ce26dff1cdeaad1aefa49e46de0fbdcdd3ec9c2e1e81919fbb360f48608588bbbd9eed5d6feb8d3d792df2a203b3b7127cfbf3143de501fc6f5b2d7bd6e7793c22c3437b75ddb9d405572b97d31f9089df3b00a07eed945a4b4d44ebc62320d4dc1f2f5cc1a7afa3d7593328cd79c0764ba198060f0af992ace71e06b59a81ee2b5db54e47da7d466f5f6b8c15901b16007674d4cdd59f95a31203d72f10d1a89936b5172d22b9f892f76165380322c11a0506e75dc6279eb02e95d3b03d64b02bead860162a636e8708447854e953e4f603e60f4afd7d733cf0e9fc1581b0d3824f6e64a7610a91c2dc5daf2786337dd1ce657bba7e3653bee40be5498a851007f053c672cef502d05cadf1290c4b6cb729f05bbed468b9a1d670e721a6f1b188912930cc2825d84651c5c68a56126a82e5db4f5a25903983e4dec706173e3c7339d45794c00c6259fd46044e87eb5d2b9a0a69ea0e409963c6d8515db3b32ece34500c46f744ceb9c6166a0a7c675a1d013dd17522f8b07c676cdd552b453ef8141e1d3b4aa819836defc8eeebb9f3e4d10f5a1838623489b82365ea2a12ef4c28fd24fead6885f3791fa939f3ced2a2c4b2e58fb940137c5bc6e1ec6cf217376b38edb24680c656ce6c324f9d02df583f644ac65c8112d54a1d41b87e23529c78d29598d7f3d12add9cadc0773e739edddfa3f9c4b146abb19bbff673d99cb102deadabea98e26b86384fe369e3d2736b2b7632a7533165e9aa18d1dfd37d263280ede2ceb170097fec0d0a38e9f6c10b1b6f03e3abc2873468f3f0ae0c8a6e2ee674efd6bdc1ce936cf3bf040e7c3aeccca14735f78286ccba7eaece55113c1c68f51705fde538aaa4e80e2b869fcafd52d29ee5b27ade01269bf2c53a06487b71285eb29c26a31f6b1f9467a740320c51031e37ba034635e9c6b06828dcb7284c8538d20c688cb450f7857bb4f22b4dc87b129308b3d33764e6cdafc7abf1d220748d3e5d176cb083935bace23eb9d071475bab262cad74d422cdd08b2d3d0d8eab2544a3f07241d632d2d49524c8114da06b376d96e42db4cbbe9120d7a954f40cc6b3bc443d0c16d4c31934f4a2b8e93b73d38848110059e88c48190ebd4ccc42a19615db39a961ff0124c4ca810d42cbea6041ed60f37c018fbb0c6b452f70c2d10d746d9fe4e39079232cdd59d4a9a0f326297ba5d979b67d4514166d8eb23f703d38c8de34bee48bf93b0c3b2d7727ca7fbe9fbca891c58e00dc0f31f42d1ffac3bef9cba3c8b0f20530bcec23cacc4deeec1f0a81e77136d3a41a790764e6c42b9a13008d3a374d9bc55377c2913793796c702e6406adaa38a983277b5a0e725661c17aeaa16f62340ae5ad2fa3969686efda7fd98dd9bfa0ebdb52d7edac9203c4aa9a9c3dc30d86c470fe4c68a6e488782ca995a6c15de4c4e14cc6364c4dd3bd601003d7edbf8d63c29c5c3984c606c6399f04ee0340b5306c5fdaa59bd0f39adf167d33a9858f28724d2197929f22a8eb2557ea1a7e2577614253a2daa2de326ccafda13c79cd2eaa4925d36a878353201e3ba4d90352c0dddf3781558b8b099402de295d1f611788819904e5e6c36e9db1884c90c35f76613ebb1b5af57bf0c81fa8b59cfd77f69d1b4c633103a686452d3396b85fff909eead298baa20ab0bab37775a675454fdf0746a8ac1bbbad21e0bb0ce806a2ad026fdfb7a83c915ea41ad24c14d931d87480794ef8f425d03fc2a18693349c3b52611f57014933ac92f9eaf8224166e11ee7a4db0be34c070bdf8363ed2b36637b984bd1a179f0f005e0f98d2b3c12d7ef2e144248df5687909774e9a49d87395594bcd0c7c3231d33e9239849af23f3ea3cd0220146f6204853eba0007911bc6580dccdbdd642131a2cfc89bdee13493f738ff40d110f7516997fc85fce9aa4d8fe3d31991d44c8912d350f67f338466296c973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0xfff}, {&(0x7f0000422000-0x1000)="f601749d27849b5884e5dab64b7b0cddd34e0bc8b7d64103b11a37d395b77c9deba183595793355f659d3e8ee88881e8989d734508b38e850f52e653fdb0aeb68c77f1569b360c8163d3d36118c3b2b14d02fe4dd70cc5081e4aa10c7c90881699803a850f50239227169e992ef962f4d5f676a632f378af11e74c30889c1f15a27800b5e0a76d6ef9f39b7399cc33e13588aa965c1cb50190d11f2bf7f1172b23be30b328aca152bcab7ec2e46a7a117ebb69071f60d18bf9e1c5067391a48dc01d464769badd8b44e2c8ee020b24e94334f0a2b5f68a691544c41942d217c298d607b879f07c938324ea649388af1e4e1d990f1789f4b3a77ce5ca3c2caf02c546798d24cf73add15cb64f2960958da5ee5f16b7d15e011bcc0b17141e8c89b4ef5bfa5bc5edb8c4249e70671876c8fbd0e8c5bc6c953e0fa7470d942d9b0ad09806760e71645f8df241eca970262af5aabdf5c028f7ff7b37be99c321ad37f4698eb8f6883f3c699c419e3ddbbbc21906c086da514b408b41cb493c76555b7654d2435db984418689d806a43b7a4bf40fb048bb1a8e2f602f9398e12fdbdc9d151d6346176ca4a064f750e9d1159da23e2e68bd157739a329f4fdbbcece40896af5c96564d508fd06a63676b8d30f97dc123c0e41a310b2d03609eb7f3026cd3d177445dba40edc6bb34e8ab2c178d8b780efee132fc511bdb0c025828b37ff79f9c2521194bf2ade550d1fb866c57cd2b343917341e3d684359e187ce723e57d507f22832ff2240c58eefe42670db5e3ae4d7cb10dee440a30336e30d9db031c2652c6949414c016c262fc7d8e3798572a1427c75bda756fb3d99bf0731c2c6948e5795c807ce455ed0915cfff8185ff32458e388bf157a170d756ba79a7639c5f181a10b1b0decad0b4d1be5eeef8ea9adaf6ec3e94946cddd6b753f207c3e5664b7ec79cf1023491ac5b94e128df9b62f4700b208aee427074e071e7af1eddc43eb9e1a89f4f41c322f71ec2a437ff1127bcdd14e7f04a372ed295ce75889892f3e37cb09c044d44cfd51f6166af78d37490fbdc34dffb97aa40a1dde536096aa99b9065eb708f80952b9f940af269801823239d8da1efe5c99ec34527e3c21a1dfd6ffe86c69f7238a93d662b58d6200576adec4537e9259ac1160500e3bc9c283ef84590132e6fc4bb1e4e28f89d2b3edcba483b90a6e1fe8fac7f547e12e54ee39b752c362bbedc39317e180a8c7fffb6d75d9c49f06d0127a259b470e0f98e0a7bf05015f611d8efcc8274784c611c84af4ec15725d864e26dc92e87fe61a94c5b4bcc86d5588646dd7de7b181da277476c71829c0ce54ce09cbd5916d53597cb048892730e0ae4f9c3400b5de649f90042134e01b8bff984d7939f909436fe1411e9a70c951dc6a4de1c28538e04e0d72ab10cc98e526ffb0fcfe7bccdc1a8cfc9f7d99d74c807b553e8024657128be13c90915658d3c63fae01d75e832e67df92b9b9447265b8171d3dd04f5ff285ea080b057fca85eb8da633468704a65e11abbc8b0ea38af4c838edeb864ab8b3b6dbd564dc3ef944647564ea1f25f7d50707a721ae6b300b6f572fc26325576c1257e4bb06cc9d659215564965a0ca283e5ca82a8a1df6c448faf0e981e2d763f176a345a46298008c9a886919e9f28b119c30fd81a87d5e271a56186b1138871a735c03b39aef477bafaaa51f9665483f5f2ac6e17cae324cd8a50d4c3b2e29107a1a02a97073768c843979d15f77eaf41b4fffeb0d05dbef73b712494e4395b1fd5b2064d9f082f5c54a4a7eb845f16aa63ae455d4541bae0d9db9adec04d25ac868ec00a4b2cf262045c5ee8a32a0967b2194bd887855a269e171d860fefc391e01be6cb76f8f14fe75b7696e8e3a40e3c85fd9bcc7d7e194012ac3ce5da60bd4f9bc4489478502969c5e7230d471ba1592ee6ce581a33da5148b7220a82a0edfe1c62ffaf51c4fc1d55bf404f52e6c0ab45ea23a47313bf4cae3ab66082506f2b016cce3ba0824a8f92ca35466b6e85a87d63ca0ae49f56f1a123bcdc7be3f95554b5b918168162c523736bfff723e6d46cecfa16e826f5d20436d1f91d2ce0923c9cdb18f1867d82fa31ce52bd5e8257b7963c6ff703eb3dbbe3fe327b2dfe020c24d715b3ca8726c270853d3195a7eb5b885fd4e6e5ad4406258212f9d5ddc28d6e14b2134a85b66a49ed373cfe6e36adbea1b89ac82663ba3bc287342e2b9b9335d6d820d2d45f982160f5f030e22b51e437a7e045d2126c9456e4f656501f091de3c2cc2e7a17bcde895671d7ff3be87210c90fce8eaa8d2b594bcc5be5aa6e93730abc1514f7c630e908877bcc899263885a31c397da214bbf69aef26770034193815d4e77f3b51f851b419c0b38dbeba47d8724112847f776c082d92cdcf541525e502cf5a59393823a2cec5e6b6f3a68b9cf0cf45feb56c8e2c11ca23185d8b6d16f097c5a695f43747d03f7633add7b485d80358c1a195e4492d5c8b6b2fdbfbd78c1ac71ce5a8227e395f10ddb26acacf7246fe9ac73830eaed8cb68279536534ba0df5795ff8bd695eec88930a438f7d6e1d5d58a2efbd0c9449f0e6045c6d821630cbe00cf32413675e32a9a43063396180e46832c069a51100695329f843fd63d9a77b95819b6faa0b9fe656662247cad0756b19a9ed67c1d5e8efbf2bd3dbb72d2eb0876cf8455330dfef5461bf865e2b32b154d40d8cc195ce86f5dd9804c81aaf350b834a30ebd2fec6e9f0e10ff768f89a0f104607cffeba6fd247f1dcdb18dd7106a04bddc23325ac2c4996d922a7d3e5cb59e05da1aea7ace6eeaba7dcc2a491e2ca51bc881c8e81ca87d2ae52f552a951fc0c5c4ed2ef8cf09181ccaa80fc8574f60cab3177d46197c07a45ccfb24e958b36fe0addea45c3943fc32e5ae9935c17737b3194ac375422ab1e7a4173e48e66f9a803768004250cbd2a7e5463d0065981b92e4b9c57a49db5bedc0da1c8a1ff02ae6f3578f04f7159b9fd1e3ed0b6096a372ff8fc621d91736a248482a09c3b6a128cd862476d7919766f0263729f9fd2dbd5eb530c4c9caa5805e2d68d27cbfd03b380cea034cc1f3ccb39424c4d75433109ae44adcda605bac61e931787a79d2af95edd380a5261da3f7a8e4b672a4875377c3ad3180ded8fec5c5c1a0269b6d018c1cda1ed35ce5682a622446f46be2680a7a37cde56c91c7d14a74b95de96540d30f2cb2aaf2ada785c220a491a3b0162cf2509e47386a041dcd057bfcd10e2a4dff373886cdb58d0517445e118c563eb6948597f2b4d0fd022b9d5e925fa3597d4c6320f0bf31a28f69cdc44d1da76acfad9bbe2a1541aaab3e17ee9659d138ef7024f54645a2d7f887e70222427e54461425317fb1e51dd6d07ea443a171810fb6023f754e5bf0a04db17a028120000556193eba671f05744d7eea19b6f9b2074fab4511374ccbb12a0d75d5a0c347996ab69e43affb554d97fc679531094420f44774d51e5dbf861964d6fa15e97cbb35c429f6c76dd8746d140e60601c593960a35c6d64ba901bf486490d2ee0b0326c0c3e8092e333836d23891af1f8a3fdd8f12dab8d6159d2808f803c981a4113d1c616b38c02a5007e6c3fc4e7bb7014e76232e64915452ceb3e1c2c38bec06d739b63721d96e834d8fd1fb7f1da07dd5e316c86ae6cbdcfa6cd8028f40c3b660bce3da8d35d84a7e2031fc04979e63daf3a8c4fbbe1fc2ba7b38ce4a30502a0b3e1bcc5c08b6fc31d614fb592331c22ea605e757bf4cabc7016402b7b649adbd33b545a2735f017de86a7e99d115778159879fa8d0ef44ba14de4722559ee6bdcb9f5106d150d95dda42d75f087c69f187fadb3df3fdd492aa36cfe38a408d3e716208c1bb0a5f7a013389dab3ea6f2efac9bcb8e2e5e0eab971dfb8e2d6b1e7a256d1712e518cd84c6f308ed5a18cd2c7f58f0745fa6d7b8220aed5e12939848a5cb8df739d34313f8f9fa1f37a02ee7527b3cc13ffa4df534eed45c3b3333b228f311cf37db1aee9b64b7894a4aed47827ec05785b15a692fe18b9a69e472152c16d918663e0834501b698e34ef3a92ce6920467ae356d896a4c3706f96e89e4d71c4a9cfffb93123b05de2cd5301e7ec687a7b5d8087177b82cc0bc0e9a0b88263135668f6e649dea8afced4d1d73ef43c139bd9b569d5a2d3c59107d10503c3c28f4c37ba32539fe44e535e395e80c2003ac3451d958cdfc67fe444dddac459ef6f98ed16bdc7dee71e6fb9b3bee6269b6ee80c60e3b92a15c9bdab43fd1c1e5702da83a2ab7d95a0d4f53034aab9bf36a463dea632dafa9c93dc34f38373cab2f8fbd99d3ed41fb73be6923397efbd8ad9eba6bfeca7eaf30fe38bf2e5f3115942aaa9a46761f3954ee0b57493d71e8657cc6f53cf9137a89398498ca6f9760301b39b191e8de24ae3844e57bd6332c7a43a6248ce87b49ca383cf48b100b971f532eb8b51b3086b8c7ef0748e4ac123bae9feecdaf74d4fe91cb33ac6ad5b5e8611638269842723849603ae47e2250901701428adb3c9f7acabfa4aeda57c9d0f612071a76ce5631d4f8735703f90137e61385361e5e0748753660eed404d87d0c623083b06cc8568a30077b84b22df5b5453a986c407fa62730a9586ea3a80b2a4e8144f7a6113b2db151359958618d401dedf53e96207d62ee39c0164aedfa3c9717473d6f8608d2b92d40bf3217e9238c912b7d2310defefef761abe0049969a81ae6fffd0789e4e8a8ed2829edcd77108a8500e8fff137c4bc3eeb94435994cd52cd896943085eda116a926427677515a72c14088cf98f617e6a0633ec0bede1db55cb781beabeb33fe30137be643253d39708691ecb7c7a22436a74dd2f2f2c509cb766bf4c93357a072491c1bb60bc2bdeb9975b2cdee7a85b36408fe2177be1c6cfdcf3385d18b24ddbc0e9ce37a44774a3e11b8d38ce66fc3cda164cd3e60f19485963e6754a667f6d9a8c8032e56ba2fa6898891298ca1204aae3625c45b49e3557ca7c93754d1d47b164e1c9c6a41e9e24e36a4babc1a272d5815551bcc0132e3cdb05b3458422cc364d992e8d7070153ad6844d1f97d9865e291077f4f76ea96c95f7da9939e5c41496f31930b75679a159a36498287aae0e991a76b13a425f5af64e453a0f68dadefe89977e30807c323280ccad1249a73d93b6250fe8946d107c4b63b39bfc66dee08ac659dfa5d47ba919237de19e1417cbe90ecd994ab642be0cd7d3c460b452d95af524694ab031eff9d12b00e99f85c2dcf5114e13bddd469371c4637e8f62bad3883b07c94119a72b7552a4c35972e03dfdef5a63a52999e37c40164ba94e16c4ebc2b3bf8e1d58f5b2a8f6d0552382ed966b0b03e56da0e2ea4d7d4935553bfb639fcf8fdbd5d1953c3724287410815bf4d1e01bedf556b762bf03c49b730d6868d7f2de713685503b13345826a5b45afc5f1021ddde9061b4549b1b8bb354df56b28d64ae2912bd2784f1a8896c20c1419b74aefc8add8754b5cec1d20f9cda3763a679d87fd8583c7ffa25b2c7d93a21aec66eef033b053af9eed27bbe26b643b63b66b87eef7a495a1546dc6a774a32e140dfa3dc048d02cc6b0ac801e442f999539932b533f5d19312aff5f7ac6d2748f1f2b3f33a4ed3e296924ec6ed38f29d3d631b4ad6d5f5ef2e6ab17b6ea8b46490d3415d0465deb435a6fa18d71290d08763ccc3f5165e9f8380c0877d45f13c5e6b254e69eb2a2caf1b6216dfe3aac24ac49b409a7f", 0x1000}], 0x4)
vmsplice(r2, &(0x7f000017f000)=[{&(0x7f0000e70000-0x8b)="0596d078000000000000ffff0d1e1c87e60af7881bce7f2c673a2c3ed35f3f64d624934ce73271a46d45ed291b14022cb60c87cf65cabdf14a9ce2449ac10b1e5e06e4c4030000008a8d5952dcc49f1a5a5bd93848f9b0b5d828285b73c53b5fff50b62bc6fc49ebc5de5244bdd2d2967ee19b8f97d6684924cecfc5192ebae35fabce043c6f3697fa84f2", 0x8b}, {&(0x7f00004a3000)="0118edc572494be733e6be3208feb470c7f4fd4f8db1c54027a4a57289027538d06a0b613f7d6e95029e92b156cc8b906f63030108fc77d326b43c288573fa717b0a450e48feef3c93dcc2c76d000000003e13a055a4dc5fbcf5c83932f0faaebe2c3b183fbf99c78225b4a4975f2d830b4f37f8e15766cecb06fa0004f153c587e4254b8e81565f717ad313633959d3e96fed6be863502e399066003f44724e7a7dd468fe6bf15644fe6d3b6ebe8ecea9b4d68397c93d53312c9e76", 0xbc}], 0x2, 0x1)
2017/12/15 11:53:27 executing program 0:
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = accept4$inet(0xffffffffffffffff, &(0x7f0000000000)={0x0, 0x0, @broadcast=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000000000)=0x10, 0x7fffd)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_tcp_TCP_CONGESTION(r0, 0x6, 0xd, &(0x7f0000000000)="6874637000", 0x5)
mmap(&(0x7f0000000000/0xef7000)=nil, 0xef7000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x1, 0x0, &(0x7f0000066000)={<r1=>0xffffffffffffffff, <r2=>0xffffffffffffffff})
pipe(&(0x7f0000067000)={<r3=>0xffffffffffffffff, <r4=>0xffffffffffffffff})
splice(r2, 0x0, r4, 0x0, 0x58, 0x0)
r5 = dup2(r1, r1)
fcntl$setpipe(r3, 0x407, 0x0)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
writev(r5, &(0x7f000090a000+0x1ad)=[], 0x0)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef9000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
read(r5, &(0x7f0000efa000-0xaf)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf)
getsockopt$inet_sctp6_SCTP_CONTEXT(r4, 0x84, 0x11, &(0x7f0000e69000)={<r6=>0x0, 0x2}, &(0x7f00005db000)=0x8)
mmap(&(0x7f0000ef7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_GET_ASSOC_STATS(r4, 0x84, 0x70, &(0x7f0000305000)={r6, @in6={{0xa, 0x1, 0x4, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x200}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x6, 0xa134, 0x6, 0x0, 0x101, 0x80000, 0x9000000000000000, 0x7ff, 0x4, 0x1, 0x8, 0x4, 0x9ea, 0xc3, 0xffffffffffffffff]}, &(0x7f0000ef7000)=0x108)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r7 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$inet_tcp_buf(r7, 0x6, 0x8000000000007, &(0x7f0000f12000-0x2)="", 0x0)
ioctl$sock_inet_SIOCSIFFLAGS(r5, 0x8914, &(0x7f0000b6d000)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_addrs={0x2, 0x3, @rand_addr=0x4, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
ioctl$sock_inet_SIOCRTMSG(r7, 0x890d, &(0x7f0000e8c000)={0xe05, {0x2, 0x2, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x2, 0x3, @rand_addr=0x1ff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x2, 0x3, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1, 0x3, 0x5, 0x2, 0x100, &(0x7f0000299000-0x10)=@common="69666230000000000000000000000000", 0xffffffffffffffe0, 0x9, 0x16e})
r8 = socket$inet(0x2, 0x100000002, 0x0)
pipe(&(0x7f0000e59000)={0x0, 0x0})
setsockopt$inet_mtu(r8, 0x0, 0xa, &(0x7f0000466000)=0x3, 0x4)
connect$inet(r8, &(0x7f00003c5000-0x10)={0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
sendto$inet(r8, &(0x7f000000d000-0x1000)="9b411fe87308bda68cf69b00fc456354c7329f7c247c5ae03e1974135e8db80e3a8ad4c76c4f7bd9611378c3b492084207feb8cd52e4aab2e576ffb0dafcf1c7579fcccd74875824b762d27e483eb885e18579131a87c4309c05830e357f575c0a7f7f346d0d61b5459ada9ca0d895d6279639c67a49b5763273aeb5f2a9a47d128b01a19caefd5e8de29ef02bc69f88e990313a5c6ca4d7553293ff5db0766407e37e5746f7a94d3a1ed3f1d9efc93ba833a7ae86b08fec0f30236f17d5ecf9bf6459b385c3079c62aa19450926de608f13b8493004baa0ea070257347a686123aa5e37ea428ab6d90aa0a5aaa0178237d8e1e8e31f920ba1c328085b98598721dec8437363864f82c9594f77be5c44effc3bcbc548045eb63044f435aea680eb14f53fa6156a06068b4ef0eb113753f6b0ba538e9ef2aabb9c92b8ab68304bd61a1330bdfde693aa838cbda772f976db33d1a7f1481af25358350c1513113389a6dc66d074c98d60eb6b70a2a7484596fa666813eb4af421ea906022f10bd0b4683312a5d46ef3d746ee68e67b923c7e663316f74ada47485e0df9d3bb20b0e5a6296fb95f8e787146115709bc8c913d953cf33a6066cb52507627e2cd95be580b756a40ec7f7b5875c41ad1941737c7ff0127c7ecac001c3679105cbf2ea81ed4685194e5d19d46b8fb1add32d3fe0717a555ac5c12aed602a406c9acd2be01b8cf5b180e4da32a34c1b624316da27bd16797fb28665e3b8af33189494bae59477d92d936babbe9f6697bfa9e22bebcc139683c2a00fd59d91034e6ac258b9de2ffb1268815754c1e4faebbf0dd5f30319dbcc077e29ae756744f19e4f495b7fb1c45b0aeefa6e8ef5932527967d965282300e32b5507a7d4ffc9fd5bb583cf6bc1d3b88ec5ac079aad45f32a3412cf6d3685f74f865369d6f7c965d842e9dc4a34a89e4f6e92aa1add55388c4101355fb944f67d902b7ef45547d761199710bcc9a9019b15ab652ced16ff77a4bc5592d1efb3f562b1ef062bb7c4761129c3c9a09ed6c54a3ae3bb26a5d7fc481738500ec5bd38bc27d0d9b758ca5397dbe1856eeb4d55a94cccaaf47df693e87bf2a966550ba7fb5cd44da3d88c112a2d07d584ec5b02c5c90955cffc5767aadac21291ad9693d6a5c2ec4e9ef6630045681bf824aac7e1d908fa7ebbd5fd2f5d637ecae2d1b993b6387527aa471478fe3df974102046c6656341a5eb0d7629e491f2c7e28db50ca5d72de48fe1f9f953ee5a68c9164e325b93f5c5ebdb35aeac338abe5072aa398048995359ae23760a2ce29df382dde331d6f6949e3b5e4e1e1dadf225f0b841c2eadf27f2694abfcaa811c68ab8c00bf017e965f8ee20a6af917725dc944b8f3795f58d0f080a48582588a577c321e939f8de6e113257b38f8ff6df98e9b00d9299f0b4fa60f7ac2dbe62bfc8244cb12d6ee131c01556e5d4701d79a84cb320fb9d43d1d74b8b5141866713a6418a2353d29868756da348f22c09fd4cd80803e1ff82652cbc8610c8ae2b63259368311d5ebd062bd0c961075d0d70a480bd75b7dcac004767a7bc311532d9e2f11f5dbeebfa2c4bdcb5b7f4d0a5916f3886a402ef56722e355924832b0f84a0184870f69b40a8df2e03b7b61428c3a4f3164c8b34a32aac9801c04b8e323ce5d88720859e98480f498b83a73bc99f5d6b6577cb874a46ad8330f4061939f2a3d3df5f2ab144127a6bd02425f3cb12a9b50ec8b2c517b36253a3a3751a534ade6b59f797d2433a803a3d1c18c55b0d9cc64a755310efa7d3ea74408fdac39f7de85842b7ad7646ed86a2f8e28c77a7b646b4782f22c42908212eeef69139c67b44615f85288b5ad04ff048a6d35857c79ca43c1359fd502ceb7ecc0bbbcda7d4112342e69c26273c28049e4918bdf0215e4f9001f71516d07f67a5428dcbf9befa290a4261d12af6da5022afda7c88e58aec7c320c8ed2b85c06e2beca5591ed72fd4fad0200000096df33e795bdbc1b34efee33e2eade9e422e491fd10d4c6d6bd5f05485b35fffaac75e24ca58150e9e6c3e59fbc5439024c189c1a1b0dabfa332cada0c2d365323ad1486f9e01b8058df85365796d4f373642412805b9429f8e8695ba78a028f97024fd600d8a3bc89a4da4030259ce8a3b14749fa634f9079a97b4c49a58de23239935e3ccde88f362a1a2d97d568af37466ca0f35202607751a58f1987bc1728c8dd7f6db7165bc6d499f47bb59a63db97486e2e78cf1ae985de34f1c80f82839e0e5b029a6690841fb6dbd651208834d5325cabd885156d0f7dfee328d62b27643c1560067445711a25a88532a876822c91a917ed23ca70ae404eca7404405ba5f80fc8c7a16af576df4f30bdeb0f50a7a8e212f8e24f83650c4cf1e815ae68a436a62d42b1cc2be18ccd0085fbc7a766f87456a43b062dfc2a295327111f45dbb55a66322012464834ba317e5c6bad483040957e8134c9c9d62176007502f62a1b383a4300883f44739effd2369b90584ede093cbd7b44a92a78d87934e673275883139ac0baf5f175039790521013273fac972f70bc6f9554cc72a950d4805b6c606c06fcb86e3f036aa6ccea10bbcb3df7d2b89582b5be6b6b38b536d5a0faaf0ec93c1496655ed8ee24999cf9f7c42de91fa1184ee9c7d663521c3fa72a2cb7bed3538ecbc9e53fa0c20c31f859155acd4f2781b9a7d1a04e33e003f766cbd365026eb4bf6eacc19a4b1aa0f0be28b0b4dd6f9cb38d385c7b7658fa1414eef0c0a0021a419f1466036207b994160de7c3722600acf63523ed9e2b7cd617ca16d3f0df8ac6f3a92e36b826df6d25289a7faff820930f96f68c798549f34be02fc5fe5199b523b8fcb80b559fb731404aec4587b06c5d3098f8525ed2e162ef7c19371e4a5ce88203253e1b0958a7fde8fa34ed5964ecc0cc8130cde376bd28ad388db3afc99cf4cbac62469dc339a46eecbc012ff5a0d89aabf4a95c82120aa23ed076751e278fff9c91d49ed986e842aa7118cc8e40e1aa2293b17bcf328a226ab708314e7803f56e39bbcc76ee97cdab11d6b3051d6e7558277f2359c03795c8846682488d41c61b03ce43df8faf3902ddd2899d454ce1b2635a9d248ecd83b34e430021d2431433cd96e12eea464a9c99251787501d13492c3932e1f9522347cae76c72c71cdda92047a1fe02a9742dc014a9fa7433f8f9abbc663b121e37624750621609eee5274a6494999af3c342bee1a11d1a3005eda02004085c67e7782ff754db4ee9fd997e4d2579485b64d3bd7224785812ab564d4f3b4f345d574e2d54ffa0ad217bfd008c3990bfee6842b60ee77992721542acd84994ee54dda82fbc896f3a14779a7d2b44ecda60e9ab7a8ef1b9c75208d816c5ba1201df6b554532d3c27fb5e442b2e6c28ff67137ba9927c4a1e3ccd06818898f4cd25af73ab10e8e224520d81c25128fdf25fe2f68811ae93807f9acfed139a3e3d83fbd023ff268eefc1e3b054bff5494e8bcb7a3556791e9e8a9a766500c3e0c5ba1051eef28f1e16d90bdd6555d318cf75420736e4ca01443676a118a233f07c9d60e769b75d318a735cd44144cac2563c3d214d2e304f04e666a5c7f4479a9878ab46344d8224131803367f45ab51a15432a5a9f30a34a1172d79bc4fa233d445e2e55b2473917228649637d2dbd6177cfdd06464de70f36a3aef482497f8571eeb4669450c30b318e2a20974c907ad43941222fe029e79fd30cc9f84f0da6dc577920c9c5ead93bcb7746f4201e6210e9d99f439f97c0824c37150f965d80b7a3aac46e49f16096af7933aeb54dc8f04047b43be1032ffae0cbcdc58194a1eac73cffdef63811c706963dd36f1329cb1aea2f1b0b81a9cfa740cfb7c7cf861e0b276eac87b609edde17e1211c832da3294d16f4a32d0f50e3e8e55579b7f2c48c1ca5d9f1942e5509826edfcd03cfb603d9ec482413196489e8309fb1703bf3e7772158d304d634639938f2617363efd1264d895c60735f45ca60a1273baf6d398af4410ba26a66ef1bf7e366f926e6b88bef695c42ad4b1a7ff520e368cf7faf322457a963f0fe1ccbf95917e2197834307248366ede3b367bcb419b54ece1bcb1701a83bc77d19c6c8b161ec95502402a3792ed3d42ece621c4962f", 0xffec, 0x0, &(0x7f000000a000)={0x2, 0x2, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
ioctl$sock_inet6_udp_SIOCINQ(r4, 0x541b, &(0x7f0000132000-0x4)=0x0)
clone(0x0, &(0x7f0000ef3000-0x1)="3b", &(0x7f0000f13000)=0x0, &(0x7f0000df6000-0x4)=0x0, &(0x7f00007a4000)="0102")
r9 = getpgid(0xffffffffffffffff)
getpgrp(r9)
writev(r5, &(0x7f00001ae000-0x10)=[{&(0x7f0000058000-0xe9d)="ad", 0x1}], 0x1)
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = memfd_create(&(0x7f0000f0d000)="7a", 0x0)
r1 = ioctl$LOOP_CTL_GET_FREE(r0, 0x4c82)
getsockopt$inet_sctp6_SCTP_HMAC_IDENT(r0, 0x84, 0x16, &(0x7f000061d000-0x6)={0x1, [0x5]}, &(0x7f0000966000)=0x6)
ioctl$LOOP_CTL_ADD(r0, 0x4c80, r1)
pwrite64(r0, &(0x7f0000f0d000)="f7", 0x1, 0xfffffffffffffffd)
fallocate(r0, 0x3, 0xc0, 0x20002)
connect$bt_rfcomm(r0, &(0x7f0000153000-0x9)={0x1f, {0x4, 0x3, 0x1fffc000000000, 0x6f, 0x3, 0xfffffffffffffe00}, 0x4}, 0x9)
seccomp(0x1, 0x0, &(0x7f0000001000-0x10)={0x1, &(0x7f0000000000)=[{0x5, 0x0, 0x0, 0xffffffff}]})
r2 = memfd_create(&(0x7f0000f5b000-0x21)="7472757374656473656c6673656c696e757847504c656d31747275737465642e00", 0x1)
socket$inet6(0xa, 0x2, 0x0)
r3 = socket(0x400000000811, 0x0, 0x8)
setsockopt$inet_MCAST_LEAVE_GROUP(r0, 0x0, 0x2d, &(0x7f000035c000-0x90)={0x8, {{0x2, 0x0, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x90)
r4 = socket(0x10, 0x3, 0x0)
fcntl$getflags(r0, 0x40a)
getpeername$inet6(r4, &(0x7f0000765000)={0x0, 0x0, 0x0, @remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0}, &(0x7f0000130000)=0x1c)
ioctl$fiemap(r4, 0xc020660b, &(0x7f00003ca000-0x58)={0x1, 0x4e69, 0x6, 0x101, 0x1, [{0x100, 0xbc, 0xec, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0}]})
socketpair(0x3, 0x7, 0x7, &(0x7f0000ce6000)={<r5=>0x0, <r6=>0x0})
epoll_ctl$EPOLL_CTL_ADD(r5, 0x1, r3, &(0x7f0000dcb000)={0x10, 0x0})
fcntl$getflags(r0, 0x1)
ioctl$DRM_IOCTL_PRIME_FD_TO_HANDLE(r5, 0xc00c642e, &(0x7f0000acc000)={<r7=>0x0, 0x80000, r2})
sendmmsg(r2, &(0x7f0000871000)=[{{0x0, 0x0, &(0x7f0000d8d000)=[{&(0x7f00009a4000)="acf1bad6287babdd8fd72ab93f5db753e8731fe4dd910edb1faf7f0fe6b2596c688667d2209d3f0eeb4f72041c4fec84cf39062a66d4016421d03ec9ced79653a4512f921bbeb774c88c648877285981bfb86c89738d5562276068f3a1988d521ab9d334c929066411eaf47a3fa9fb9e3933fedfde0b2b23915f3004b68a07f9cda3a6ded70da195337d37adf18e786758f3879a8ea71e3b5eacbf8c40c644e4b265c2ed1867cfef39a2d2e91ef7fcf79a3d0d4c0176a19af5a487ed2395bda8e9782c569ac7256ba2e1f744048e5f2122902c6d123024ec77887dcb56ae1faba01478efa30c02e10c8ead51756dfad7c45078a90fdefc8f0c7936e9a8789ff4c9202dab4373ef0bf4c505fedcb3a537231e458c8c19b02d213e671de50740742891a666c66ca8d0146ec1c00e9944901a89f8c13c987659c8da744e908abc2240831afaedcca2af221eb2d2fde63e8ea5407de6f4a958315526c9b69f0661aa63922c50fb19acc5b3c3cee8a81468b6ff50e0b5589e0f43f4e6103c7f410ba396152b83712328efb1586f0fe1ce77729a333e47d98dffd8098f5b35cd8ae04c9b598c3dfcbc0aa671393e4f2d1c25edf4af91c077d1cb5bcbc6eeb93162f372b7939966d4d4b386d0e901f1ed28301036542fc40d1e098ff521304b8a0102d48f12cc7f1c12d1257764d2f239386f0c7211b59d814243adf37bb240882411b236e40d49ca63bfeee84b34eb8aff8dfe1ab97ff13f72f35acd0bfd9a18cd96371b7a1859cb5ec29e58fcaa2cddf38fd2c307349eb9647431c3a46c915a70ea53e7ba66bdce3a220b7f04c878be53f83f02ecab265e8d0cf48b160e72e77268eb7f6017a6619f86e80880e00913575a4a1e82760ae10af5cc7533d3b59a0280d03d6723015398acfb9267ea2d8b6bc5dbdd9c409258728849bff0213de778221cc4cac55a059101c7656d18d35d260c9f0508e300cb521f3107d92cdfe8bb6f40a7c8e35be97e36dd45bf412e622c012da5b5727772fff744e500edb87bf522fdb4dc3206d2aeb43c0d2dcf22da02685bc717ac5a273a4d30d137f113b87e1c217235fece0551327c4fc564d137851babef44310ec06cfdb5937038578047a77676471019b964de953bc44f022878eeb8c848e72b89ef4b3a27d6c801dafd9f2fe63cf6d8aabb4680c070f6e1ff5548aea46064759bcbc92e84b5ee70f15e47c1602f98ef9a4d9801ba9114ea268da98c09c4eca3c012cda826709dc61054cb82dbc5e93d778adb0a3b36f3e14fde929b5a35295f99c9f274d506b67ab8478e055ff8972e5ffa22aa6871c21e232606c85c41b0ba035dc257ee2f23b7dabed16f313258de197717d2f5d6c2d4f450716f91887d3cf9f9c12bc356fbc06f6ed09743d138e39b9aefa99c5510ce86f368bd31f3240c94d187bdcc68629cacbb4f03b45455a91731e1be690f861f2fde6c11d104f576a0d1acfd433e7f96332bf7d23f88ab05e273f2ce9e94622680b158decaa60b1d38c2f4d3b76c10da042b4d7eca94c7033d5a14c39efac9013a4a0911419cda771bed6939fc73b17f0510077e93b1aa2ed95bbab279b9a178707e5c627bdf21d7618da8650db82c2db7bcc5c507221db80282b026a4d19d7bba9f268f8a1063a2a2ebbc9eafa7c74e5239317a56c0f2f89abcd471799e7f74ceb08791f20a1ff5bb6befaec076e3aa918c11862874e8125a8945cad8ce38370f3408f0f1a83c3ae90f448c06c88b5cd67521afd7b489d1d4a5f45392ad83872c3449ae348463915623e4ae99be93f747a90f2c87f74d299e9599ec2be43cc0c3b85a540c975420fb3662e89895ef6eda9f1e13d9b45fdff4d6aef2bc846ce1c334599d87b1001d05dab7d8ce8b4cde1ba2af0dbbfdacddccecff0101868eeadd6d86149677efee3e8b8ae6fb900d8280566b7c473f6be0c84d6ab8ff6144e90420bcf7c3c5c06a9bd7104d23b21121c018f5d2a98cf9da3b3f23e3295dbb54a6a6758d0eee4ea6a74ebcd8fd6dd3787959cf0dcc80e80e5ee86c7c0fa589c7a39ae8d6daba368ec364ea5927670e71d21572e7c08afab943536ca93fd5600a373b191b4b1517a82428326c3b7594488bdab7e4b6dae6b3c4c5197fc2f9aada3b69107be40014239ac71aca5a48283bceba3aa9a6ccb2c28b79ce4c205cddb71d4e716c6e37b1508760ed871b4e9c167f95278c8664766e98130958bf5a6ae4be4c0eaf9c57f158d8b6017148b744dc5094cc9d6fc0959bb7f483542ddf5ad3d1845fe000df0a41af53aacb6a64233aa52c713b69eb2006201f4af4f681af3d60ec683c803cb60bb1754aadf77ef77715fcf3fb806ecaa3de8da5afe286d891d318f6bf78b5a9319d2f13da4f3937bf80f3244021d5f28c01bc125bd2c66f0dc2826b10a9a7f803fcc72168efc0248ed8ab197b8885e90fe97d176412c8e07fef2e77eec7e2615c47ebb879616b0317c6fc01203d69cd1a2ad54ed73ed8f14ee8b26a41f4197d889f8063c8268a47fc136de3673cd6f8afdf6f399368dabdf6ec564b2cb4c6c26d2e7a278fc204066f432ed499e0564a0cdacd2bc5565386ab4a88851835c39f607ddc9f10204ab74159dffbe5642528c6fecc0a941fcc3e71109a420021d352ecbf9ba31c13c1d6a27de1b0e7d84d09a8d7483fd5b0a624e6f200817dd2be0b1c3d8308e38ae5ef89dc7f0042f1df1cabe1606707316460baab6e997bad808bd07e9666743a2f64f4348225b1bc2593751e9c311561de24142c0608bab711c430178ca20debdf48ef642effb2501487c151668021ca33aa28af94a3dc4049ef85e7facb3b1624eaa097e401207ac0bc9c9b6acfe2d61dc0a9bd3c8a0f0e8b107569e7ad4b4412516aa8b8bf37c2dd28db710bfd736db052eb97fb43be227365bc13cac860fb774b8f0c5f3e0cb6ae7f05c19b246664230e3eaa5c491faff8fe6e340c3a663beb9c1186026c3bf31b776325965b6209cb25f2aa6a5bdfe57849c38d189765dd47080d2c4b43e9cdd396dd668de8c378f078f3f0ee4d1f1e8a9e9008c4d05b234cbca47c1a8d08e1492ca32f47dbc73ef4c9aed5ea2e9c99e338f562e3d1b0be7640b04f770b093c431c43c501ea94539503367894632690c76642c9c8679c798418c9419e4171a6d817e5506280988e9a1da9dccd6b7fef072039369b14779fc1aabf24a390234b0becce138ca9adc1eeb5bdb98da47ad524f259ccaf441e1b0edc409ce27cace5011811317b428012b41f13ed13c869dfbae124a29374ec33913e2a97b177cb430c834e3a2b2edb29dbf63bbe834d05ee180ac6f07a1586d2673ad43bac7c87897d12294483e4793f2d3a84c4f144615571a416e4895e81ed51c7395f8ed298b6de282832c6acff3f9a3ef4647777f7af8f41c4588d1daac77f5fbb22c4882d766896795e348926afa9f8072c0232c3cb81a9aa7fce57fc12f535238ed1d092c2c2a936c26c78f07cfde8504a92782dd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0x1000}, {&(0x7f0000915000-0x98)="3ee8e68784be0ef36dd08635a7987c4ee6937c946658adf4e24c9740a68d78397a812d9e6cb2cb5379daae3854485fafffb68a7436e6b1488a9ada2ecf87f0257cbe771e5975a9d0eeff91f66a97129e5a171d6b9a5fd06f3fb9c09d2dac8fa8bf0b92c311f90a97104573cceebf46056b4e49c49a321bb00cee5bb90c91595ba8ed04f5e14ee66df371674ea139613b67dfb6e6c87251e7", 0x98}, {&(0x7f0000a63000)="29dd364d57bff9a59918e1f4fd76225ff13b82876447c0c88d66cee722361a7874d4bcaae494fdc90a08f1a009955fe335601baeadfed1aa672fb100d0f58b265779556cb33a4f4919aed8b655aed72f596aad39c00f7f9ffc53329eac384d415de487d0ef00eb3ee209cfd9442e46624fa6e4c6560256857d664765df749237a58ffa0bf4dc636c1183ac4827cf1b12c553d6e60c", 0x95}, {&(0x7f0000eee000)="3b0d4dd00ee2c4299056ea3c5ab776a8ceb66c96a25849f63ba5aa4e14cc84568b478f5bbc12433f5b59077476ef", 0x2e}, {&(0x7f0000ca6000)="c781e7cd0fdb1491e1cc3958fe98f127ce647ecc40150452b3880128b0b0584582c01b5d9ad17bb4c9ba775940014930f79a40cf2c19cb9537026cd9022e9336dd8524eb1869170ca3fade03cec16bde99ee546daa", 0x55}], 0x8, &(0x7f00003bd000-0x90)=[{0x90, 0x11, 0x1f, "d5029b516499571c771ab9a76040353501e9d71af2310da3a25e74c86201dfc22f1910957ede4565f2f3a757ce7ff05bfb1caa0c46de82b83421dbfddac2a46dac21b482d4019915603c08e7dc505227d48e279daf6523a8fe1eb1eca71f452a76651d700de97935cf6c2199b42dc125b87c9219950325f6714550d8858094"}], 0x1, 0x4004800}, 0x1b}, {{0x0, 0x0, &(0x7f0000e58000)=[], 0x0, &(0x7f0000689000)=[{0x100, 0x10f, 0x401, "ca6abc4422d58a66a3c0d175909cdb7e2b05957de6aabe864eb9b52b583e14e55a6c29131787d02821746d83d1ca71cfbcf397f15b8f5add9a72c9d0c37c2efe059c7a60a816c745eb68362a04158413128bb99adb193fa258d338d43530955fadf178b9ed595f6350ff03aa33e175cde61cbc29e0d54bb9f361c24131aa8541b9cb2a6978bf1f7f4c5b63508b6ec9c489a58ab083a9f05142ff71d5ee6c9b83073da5b4dea6100f8f034f25fe79dfde87a99c90615f42dc1ea7f37f5616815ba72af912025f09b689ad4c9ff3d838c3c9f192efc91fbeac1e89c677d396c642f2ebe5155804af87eecce3"}], 0x1, 0xc004}, 0xffffffff}, {{&(0x7f00001de000)=@sco={0x1f, {0x8, 0x8, 0x3, 0x6b80, 0x3, 0x7}}, 0x8, &(0x7f0000da2000)=[{&(0x7f0000c33000-0xb5)="7df62c08f6a6b017303e4f59b8a1965080dbe41e07587e853c362fe45fa7f082977306b018e31bf181b3886658bc72f47bc889229219a01ee4f19e21738d30acb95a4040786aa86b462f50fd17296b017372fc6426529f8dbcbb7ef6b195e7014a67aa2a98d3401e55b9540b8e38dbed37657e93288bd2037fa55b93776e86bb4b59f4e00edcb9201974d1acdb97cea8f2457e11ee032f1d6250bdd5b1a320322d720cbd022e48d3b00cd0e134a127c58f95c2b904", 0xb5}, {&(0x7f0000073000-0xef)="bd2ac35a37fc74192a845acbbaf3e66d78d35663fd705179fd716d2ba6d218e53d059fbaa90b74d5542ac721166a1c48cefc1eafc1312cc3a8485ff534cdb57d76eaf2615b8976716daf5c913eecb96a949c4b4d0809e280004c464bf6f479c3351d460eb261c24960b5b3f732e30066c87348c3188d46dbbeb95fc459d5e3133f1de65e3ce046334566b5ef2b8487b26f96032a0c2ae460d6be5f1466f194e8062970677fe6cedf25773dd96fb6de2feb7a836059d1065a411bf4629afcf02c1edb51b409ec3c01f9f3d1a29a496b0e91be7b840ace5ee5ae7be9f6f8c27247098010c764079f37f6cbdb5d8f81b3", 0xef}, {&(0x7f0000a73000-0x96)="ff148fc9e6e303948ca46d9223654cad064961ec227d3b369878a5520db63124fc8519a4da0804bc0c35e5df4dc1c3fe80778f1eb14f143bb5621b346203189a88921d71e48c2763f388c33b4d5334301dd856bcbb4bbfffeb5663ca15ddcb9a1f5368045c787b50ea0b43310c6fe1144bfbce6516a54bfa7de346a7ce83cd6e401866890668fd654b7627729217e2b32e770fd8c26c", 0x96}, {&(0x7f0000296000-0xac)="214ce259d1f77ff26c08858e5526cedde663b9a80257ec567c6f7744a541eea0a7bfc0e85bcbece77df6c315a5e5c28f936a05f7cdd7b6722436e5e44e845684da4e4630d2765f941294ef868be78c811fee283e650e9e5e1824553c27136f5f33ec113bd603035d496a691a4a00a9025667e7cffdaa3e289c2601594de1affbcaff52841285dc8978f581bbdbf30b1cc194717d7df166278094281d30dde2c1761c6ab544fe897d22e16d77", 0xac}, {&(0x7f00005ec000)="8335460d944f20a02d5fd76fc36af8dd7518c4c6df925b39d264eb48da148e8d7015c70e397eed5f27326f36588316876f6c5165c4f93fd3414b1e1363214b46892cd8e2166d9150277e68819344239141d914dff1205838b8a005e262d3a99f83a86bd043642e4efd467248bfba6a28346bc38a8257399dc7656cbe69760be7b57121aaa52ba29a7429a6160cad36d85783923da99570d2e990bbc762c3746b398b267705bcc54a02bf740d3e5623854afb5222c5e55dbd2c8b47d1101a99cf9a6cf809b6287b9b22d920f97aec2485b6c1b8d657eb591c", 0xd8}, {&(0x7f0000211000-0x7a)="ff8b4d7f093fc1147ed05b1a8fca26ea85ca97469f40db639fe211768ceb9077e663d13e8071547cf454598071ef2adc35b6b25d19355b9c5e3603a4c1ec7cdd568d5d2a221f0d27cbb4d97408fc63ed2c2144bf94114d28dd59f563e43ea51c37d1d84a6dedc9f5e3aa8fe77c01802f98834e5f23b46b008852", 0x7a}, {&(0x7f0000276000-0x45)="ce9276c572f6ec36aedba3f7b78c5c462ce9876b1dc7bf3848c1a7ca4d317d8bf0c7d90a48b7bf58e86edee9c2e34f0410458eb423b23a112e310a97d9741d3d7e404dba0a", 0x45}, {&(0x7f0000f45000)="09167418860ee5c04e925d1ef6f828cecf90159bdb1b3c863ff2fda90f1c61cc35713088bfb0c1588f83c7c4f69da6725e387f05bb0a7f8e8aad8e908cca109002e30f81a0fedada94b0dbb520a891644aa01bb1b26ba4b8bf84044f7ac1b80667b3b4ffffd71a4fe379577457d93dbfc39abbefd4df8b1e9a2d17df99c4fb5c05fd0fce2cd8218db0ae35a4eab144a95a2fe4f06f09eeb6b63d1102b4505eed1e81141b87ddaeed42ffb2ec5372058cfc5f0975b7fd700684a63049bb21287f7c50fa355b3dac088e8a38d67e92e7ae07e2006670d4ba599c332c003d", 0xdd}, {&(0x7f000099d000)="848a01a27836465bad7bb897bbaf2a07d646714f56cebb8d06c8a7a27f5989005a076160108127ceeaa32aa5ba107e0ff9d7ec30ad6869ba62a0", 0x3a}, {&(0x7f00006b9000-0x14)="42d9d456464471f2027c800148ba2931a1309aff", 0x14}], 0xa, &(0x7f0000f2a000)=[{0x38, 0x11f, 0x80000001, "fd9cfa20bdaa7145146a1365ba27e171e5f29324bfae5907d6f0efb412a6ca34d87fe591ae84"}, {0xe8, 0x111, 0x1f, "756099e39336dbf86442df52036fcbf3e0fa1d024689cdb726a196ef6f4923ba0c5e382455ce7539a13455f61974a29661d57a09118c02ebafec6db4542ee0a8cc86fdec89e6aa6eb0ce20b901cca7f124cc4069ccd88be99ad62aad9860a2336b5cb60446ed9392197aedad8054de961c0bcd18dfa0c1d27bc3a43425a25f6326a32c2b8706def49db6f270f80751f9c0f7e4fbf09fd6f4d7d5f41dbb20520649b2c70a6b3f04d5b7188630799be843cc127445c065c51d1f4eb9a9c1d5686f26a3ec14f134aa445a4c9a7ceb3f9b22a3cff4"}, {0x48, 0x0, 0xa5, "ba7edaa61095d631802bd5b8a6c3d81eda99b3c224395a8a75445c2fe1b1bcb5e796a4b456c2364475daf1363883a079aa4345d39919e84f"}, {0x50, 0x107, 0x1, "dc83e3de2d84e688a892ba5171a48ff2b41f57fe53d508391af161b85a4594365a9cc9882e0911631c3b9265c429ac081e679020b9dc5ec536"}, {0x48, 0x129, 0x2, "f8b0ac764b8460528211e6ddc68b9bf4b5f78148cfb8ffb034a43d843a8de233677d70c0bec35620781565ef230235a13f034ffb215c22"}, {0x40, 0x118, 0x0, "4bdd82fc66602cf43ab239b45095c870dc14be2e534cb231b6c2902ca54cf8cfc1083d5366aa6725796d241f50abc25b"}, {0x40, 0xff, 0xfff, "cf4f1883ed1a74666cca6751de748e58b6096cc2622e933e7209635b4321bfc804fe0eb0d0b9b54e325e32befe"}, {0xd0, 0x10f, 0x80000000, "e766f09012e25ee1d8e8a49b412331980ddba5088dd6d6a4a0899fc9fbf2bcf87479531575e5484416adadddde2a0aa5735f247a6cb63f2e770df322aa0ad1f76ee8d2c67f7d7f0173b4f0b8562a786b9cffa6658d719d6b2c10d805b0d64d0c3af4aa753d1d4415eae1696aee98b59dc6d17452cb0612fe449f6f36522c5c2d7217850121e2ebed0f8c1b4cadb31d1bdb5def61a54d46b9a614b7bc3478592714f88c966d1e956b54dbb5036e2d391c01cc06104dde9cf9bd2c9891"}, {0x48, 0x13a, 0x697, "c8395721b80586d3a8968ca2126028c0efee78c4f0688427ebb958282756632149709819471a6feba54c9f1034330ec563d3"}], 0x9, 0x4000}, 0x4}], 0x3, 0x20000880)
ioctl$DRM_IOCTL_PRIME_FD_TO_HANDLE(r2, 0xc00c642e, &(0x7f0000170000-0xc)={r7, 0x0, r0})
ioctl$RNDADDENTROPY(r6, 0x40085203, &(0x7f00005dc000)={0x80, 0x87, "4d8b89614e9a5e542c1604147a861fed93a3fad5eb1a12be78e389625250905f23835000aee48b2f77a873784328d0af774d8fcc55183b57a870d499e2346110ad74c9a69cbc14bc0b27c70640c75692981b2888db5ac6d4c701c73e636b472a3d2d6113d56fdd7a38b37acfd07dedbb477808a86784cf8bad5ccde265e54617b61b69281cfc8c"})
getsockopt$inet_sctp_SCTP_ADAPTATION_LAYER(r4, 0x84, 0x7, &(0x7f000024e000-0x4)={0x0}, &(0x7f0000103000-0x4)=0x4)
bind$netlink(r4, &(0x7f0000028000)={0x10, 0x0, 0x0, 0x3ff}, 0xc)
setsockopt$SO_ATTACH_FILTER(r4, 0x1, 0x1a, &(0x7f0000fa4000)={0x1, &(0x7f0000f96000-0x10)=[{0x400000000000006, 0x0, 0x100, 0x0}]}, 0x10)
ioctl$TIOCGPGRP(r6, 0x540f, &(0x7f000082b000-0x4)=<r8=>0x0)
ioprio_set$pid(0x3, r8, 0x1000)
write(r4, &(0x7f0000203000)="26000000130047f10701c1b00e000000000000000100000009ef18ffff00f132050014006e35", 0x26)
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$cuse(0xffffffffffffff9c, &(0x7f0000141000)="2f6465762f6375736500", 0x280, 0x0)
setsockopt$bt_l2cap_L2CAP_LM(r0, 0x6, 0x3, &(0x7f0000b97000)=0x1, 0x4)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_open_dev$vcsa(&(0x7f00001de000)="2f6465762f766373612300", 0x1ffffffc, 0x400)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = socket(0x1, 0x80000, 0xd)
mmap(&(0x7f0000000000/0xeef000)=nil, 0xeef000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = bpf$MAP_CREATE(0x0, &(0x7f0000a55000)={0x5, 0x1, 0x5, 0x9, 0x0, 0x0, 0x4000000}, 0x1c)
r3 = bpf$MAP_CREATE(0x0, &(0x7f00004cc000)={0x1, 0x4, 0x4, 0x100000001, 0x4, r2, 0x0}, 0x1c)
bpf$MAP_UPDATE_ELEM(0x2, &(0x7f0000b7f000-0x20)={r3, &(0x7f000093e000-0x18)="7f000000402662b5557cbd48d45861cd80ff0000009b24b0", &(0x7f0000bed000)="e78191a0a07f549871304e03772da97cce23030139ba4eadd4df6dbe7d3f395c9f72872aceb7c75b53016559acb0697a3e243389eee5351f91ffdf9c276ad1052c41c29deb98f4e425b34b1054ad057af3d91fcd181cec6aeda60981f73479157b90aefc24dddf7659205292fd783bf6cf68d2dc6ff82eb7058d6fa150256a5f41c333b2448d34a14e12d30b91b0308c19e226e7a55676f5e71154bac381f8fbd47828aa1661420e185503d26a38c3965c3b6c1abb8b04578beb30543a360b1970abc25c5dedb8332e10a1c5ede788a6a71cb37931ea7575ea531b3e0a269ef486033ecfbd47", 0x80000000}, 0x20)
mmap(&(0x7f0000eef000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_SET_MP_STATE(r0, 0x4004ae99, &(0x7f000013b000-0x4)=0x1000001)
mmap(&(0x7f0000ef0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = signalfd(r1, &(0x7f0000ef0000)={0x38e4ad8a}, 0x8)
r5 = accept4$inet(0xffffffffffffff9c, &(0x7f0000151000-0x10)={0x0, 0x0, @local={0x0, 0x0, 0x0, 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000aa0000-0x4)=0x10, 0x80000)
mmap(&(0x7f0000ef1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ef1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt(r5, 0x0, 0x7ff, &(0x7f0000ef2000-0x4b)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000ef1000)=0x4b)
getsockopt$inet_sctp6_SCTP_PEER_ADDR_THLDS(r1, 0x84, 0x1f, &(0x7f00005b8000)={0x0, @in6={{0xa, 0x3, 0x4, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x8000}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x132, 0x7}, &(0x7f0000912000-0x4)=0x98)
creat(&(0x7f0000666000)="2e2f66696c653000", 0x0)
syz_open_pts(r4, 0x3ffffe)
accept4$inet(r1, &(0x7f0000dd2000-0x10)={0x0, 0x0, @rand_addr=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f00003b6000-0x4)=0x10, 0x800)
mmap(&(0x7f0000eef000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
gettid()
bpf$MAP_LOOKUP_ELEM(0x1, &(0x7f0000eef000)={r3, &(0x7f0000642000)="", &(0x7f0000ad4000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x18)
mmap(&(0x7f0000eef000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$MAP_DELETE_ELEM(0x3, &(0x7f0000b3a000-0x10)={r3, &(0x7f0000eef000)=""}, 0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:27 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$selinux_enforce(0xffffffffffffff9c, &(0x7f0000c9d000-0x11)="2f73656c696e75782f656e666f72636500", 0x400200, 0x0)
ioctl$sock_bt_cmtp_CMTPGETCONNINFO(r0, 0x800443d3, &(0x7f0000a09000)={{0x5, 0x4, 0x80, 0x5, 0x8, 0x3ed7}, 0x200, 0x3, 0x1})
creat(&(0x7f0000c8a000)="2e2f66696c653000", 0x42)
modify_ldt$write(0x1, &(0x7f0000b9a000)={0x2, 0x20001000, 0x400, 0x5, 0x5, 0x3, 0x1, 0x2, 0xa91b, 0x1}, 0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = dup(0xffffffffffffffff)
ioctl$TIOCSWINSZ(r1, 0x5414, &(0x7f00001d4000)={0x8, 0x3, 0x5, 0x1006})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x10000000000000, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = syz_open_dev$vcsa(&(0x7f000077d000-0xb)="2f6465762f766373612300", 0x40000073, 0x3fffff)
r3 = socket$netlink(0x10, 0x3, 0xfffffffffffffffe)
sendmsg$netlink(r3, &(0x7f0000011000-0x38)={&(0x7f00008e0000)={0x10, 0x0, 0x0, 0x0}, 0xc, &(0x7f0000014000)=[{&(0x7f0000a42000)=[{0xe6, 0x0, 0x500, 0x2, 0x803, "9399ee68c33afb35294ad2daf5319c3fcd06352e6a49973111aa9c9a653f83216565d61bf7929ed3a46604c5895059f8c066ff3b88ed8412c34bc9db0bc813043bebf0bffc093bbbd6c799c8287e37b9c118f5a605ee9dec69325a6b912bf91f7ac3af45c0efbce1e2dc7b926cec9c3cf89f73c63d5a715f73c2758f3dbb1c371c3cf4f923c159b4460dce0e79b55b81ae55c6046dba7089b07f88b00b3b7cb4cf929eb879e966e1fff04b8790fc869dcb4b8a58af90600f5015e19d7c61406346e630c6e4b30ce87853b78d84deff2c0d33839492a7"}, {0x1a, 0x9, 0x400, 0xfffffffffffffffb, 0x3, "ce7464228f580d4c32ae"}, {0xb8, 0x9c, 0x2, 0x8, 0xfffffffffffff801, "e357dc44ea16b1bbb1c3fe95900d5b31390fad71e2c892c07ed7ed16d2d47c0bd4fd93d1516f11b9113e46a704f3c150313a9c186736bf47d0e5ade1656fee7bed03ddd010a1fedfe756d3095a26732ea3fceacf108e875b38e545db87ed225d17d74952ba2c7fd6b7a7fd230d06b89bf270cce1ccf69933060e0f3e33fcb3372144dd5a77b11d4fff323f5d2a36030f42185f42c6711ac3a0d369512402a1c953c56263fcf7a8c2"}, {0xcc, 0x1, 0x200, 0x2, 0x0, "d6efc86e68eeeaa66fb76f1f838c2c55fd920540813a40dc222f5f3ca675ede55b265ac80e62fc142c974c921f779ebf8f6acaf946e420d05a16eef918f63fc628b0e11114b6b3184966c69ad86422a8c6a77c7c8bfc6a177f3ca218ec45c9ebe88195b8a8c9e1a4a71b2e3b03a04635e4ce4609db4634bb27820276a7a3945b5fde172017bdb6f34d3cca129f8f47295c62e00d6479350edf782d789178d5be9744555c9d7976d6df00acce54616d14b0251e1e3407b372ae913d4e"}, {0xc7, 0x800, 0x2, 0x0, 0x800, "0e7683eb1fe8238ab6593bf0f23b6666f1d9d7dbe188c0fe2bdbdb95796f40c2ef0afcae31f48ff517228565978c5d6788c29c4159876e7c2906e50347fa306127e12b637ae42ad3a63cbf812678beecb9868e084e56d88be0ebfb3bf2531596e3798deaac1f68130162b216573978d1abf83630a760579c8bc563809776b811f06129975095aba72ae0be94e88d7ab364f4dfb3f79b5d3bce251fc95d7d8f1ce98458202acce6d9729a710be029b25251d84fab564b7f"}, {0x2e, 0x2, 0x10, 0xfff, 0xe310, "eeb389f1bc5679f8f529e82955776a4ea49f8795ad27e8b8a8926c4c2c4e"}, {0x46, 0x4, 0x4, 0x4, 0x0, "c7e977fc0a979f109d8cf16cbf3f47e8b0071b33fc7a61bb3089216a9daf0efa4c62da9595d6c1aaf117475963c12170015c632006e2"}], 0x3bf}], 0x1, &(0x7f000001b000-0x98)=[], 0x0, 0x0}, 0x0)
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r1, 0x84, 0x18, &(0x7f0000417000)={<r4=>0x0, 0x2}, &(0x7f000047e000-0x4)=0x6)
setsockopt$inet_sctp6_SCTP_RESET_ASSOC(r1, 0x84, 0x78, &(0x7f0000e73000)=r4, 0x4)
r5 = accept$netrom(0xffffffffffffffff, &(0x7f0000d72000)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f0000a0e000-0x4)=0x10)
fcntl$setstatus(r5, 0x4, 0x6000)
accept$inet6(r2, 0x0, &(0x7f000092f000-0x4)=0x0)
r6 = socket$netlink(0x10, 0x3, 0xc)
r7 = request_key(&(0x7f00002df000)="69645f7265736f6c76657200", &(0x7f00005c3000-0x5)={0x73, 0x79, 0x7a, 0x3, 0x0}, &(0x7f0000107000-0xb)="2f6465762f766373612300", 0xffffffffffffffff)
r8 = add_key(&(0x7f000062d000-0xb)="706b6373375f7465737400", &(0x7f0000b96000-0x5)={0x73, 0x79, 0x7a, 0x2, 0x0}, 0x0, 0x0, r7)
r9 = add_key$keyring(&(0x7f0000c03000)="6b657972696e6700", &(0x7f00003d9000)={0x73, 0x79, 0x7a, 0x2, 0x0}, 0x0, 0x0, r8)
keyctl$link(0x8, r8, r9)
r10 = socket$inet6_tcp(0xa, 0x1, 0x0)
setsockopt$inet6_buf(r10, 0x29, 0x400000000000003c, &(0x7f000078f000)="bc", 0x1)
writev(r6, &(0x7f0000c9d000)=[{&(0x7f0000804000)="290000001800ffffffff6800000a00080308ef0c060000000000000000000000000310ec010019ff00", 0x29}], 0x1)
setsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX(r2, 0x84, 0x6e, &(0x7f00006c6000)=[@in6={0xa, 0x2, 0x3a, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x0}, @in6={0xa, 0x1, 0x1f, @loopback={0x0, 0x1}, 0x8}, @in={0x2, 0x2, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x3, 0x573, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x18a2}, @in={0x2, 0x1, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}], 0x84)
r11 = socket$inet(0x2, 0x3, 0x649b)
getsockopt(r11, 0xff, 0x2, &(0x7f0000dee000)="", &(0x7f0000c1c000-0x4)=0x0)
setsockopt$inet6_tcp_TCP_CONGESTION(r10, 0x6, 0xd, &(0x7f00007f3000-0x5)="72656e6f00", 0x5)
getsockopt$inet_sctp6_SCTP_INITMSG(r2, 0x84, 0x2, &(0x7f0000a44000-0x8)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000689000-0x4)=0x8)
2017/12/15 11:53:27 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe2(&(0x7f00002bd000)={<r0=>0x0, <r1=>0x0}, 0x800)
ioctl$sock_SIOCBRDELBR(r1, 0x89a1, &(0x7f0000ea7000-0x10)=@syzn={0x73, 0x79, 0x7a, 0x0, 0x0})
r2 = openat$sequencer2(0xffffffffffffff9c, &(0x7f00008b2000)="2f6465762f73657175656e6365723200", 0x40040, 0x0)
ioctl$KDSKBMETA(r2, 0x4b63, &(0x7f0000722000-0x8)=0x2)
fcntl$setlease(r2, 0x400, 0x1)
r3 = geteuid()
ioctl$KVM_GET_MSRS(r1, 0xc008ae88, &(0x7f0000ded000-0x88)={0x8, 0x0, [{0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}, {0x0, 0x0, 0x0}]})
getresgid(&(0x7f0000e68000-0x4)=0x0, &(0x7f000079c000)=<r4=>0x0, &(0x7f0000d55000-0x4)=0x0)
fchown(r0, r3, r4)
execve(&(0x7f0000001000)="2e2f66696c653000", &(0x7f0000f29000)=[&(0x7f0000964000)="2f6465762f73657175656e6365723200", &(0x7f0000ce5000-0x10)="2f6465762f73657175656e6365723200", &(0x7f0000e53000-0x2)="71"], &(0x7f00009fa000-0x10)=[&(0x7f0000bb3000)="73797374656d6574683175736572626465766367726f757063707573657400", &(0x7f0000865000-0x3)="2a3300"])
r5 = fcntl$getown(0xffffffffffffff9c, 0x9)
getpriority(0x4, r5)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_GET_PEER_ADDRS(r2, 0x84, 0x6c, &(0x7f0000902000-0x1008)={<r6=>0x0, 0xfff, "8141d9de2d7def1187a0a5314f8c5f32ce77ef595cb0ac4939df18e062c469b2558be1d82c69690ba9c39780fb95d8393584ba8e8d936f6e99f6128aa74a4180eb44727659086795215a6b112076d11e8c9d6a0b89b548301620632c49c71fd2bab129d81fd2bf2ea2b89d15025f1bc7088b017437d50bfdca1422507ba5d0cb58b0614df47d0a05bb8739211ff02d728c4c1137b9b86ffacc8806901c820b12f9742fd003f384dac6e3f52afc75e4e3a32df778f52e75d8e01b7eb3dee42b8fb47b60aca0aabfc0624020acf7b1b150d05e455c77258d159c49a48b5a6b11bbf916ce6ab3d51138135362bca1e28e99c3150608c2fb79946db842ac66bc75c54767bb615b51c3e00fd84f814ce463a169968e3d9b02e65e08de37153cb834367301eeb762d1f9da6b79daf0b6ffa012684923b779416e9294ecb823fc01e292f5fd9caad13a80b4d099f1510fc0140b3655b3058b090261581e895bdf5e15b403bec2b0d6f74ff610eef290cbf22983b1c807b06e7ec455740274869b32cf35b9b3fae97f9ec3f6c55a9c3383a2ac296573d906f688cf6142868b4bfdfca9a0be4456c0d840f119dccf4c1f8d1b5c18a7de3cc5e2f48e95bb40e6578f8ef0ee86b62d985d9a0403994f190bed1c758f02f4401763c5ea0a7fb4bfec04020f49fd92e681a4aff817c3a8f2180960926db6fa26da3a3eedec71af0541141aae0489bc3dd2cdb9ab7e640a8a8efa86d4b4e3083709d6e1c868cdb786865889bc313fb504b9df5505a4f14ab28e1b6f502c094e071616b108bb4ba6e95751272f90ca3d4e3191a546d292c6eff8ac3d1bf5254e33adac497f661b43f410607a74954c0f33e0827a1a8a02fe4fd9e73e91e32cf3171f61834089d528ce555535a57e0e93a0331ad7896d180c826f1c746c05ba7441887dee0c5cecd8e5447ec522976ed7ea330f5e1df0bcae97acc2ce1b353e2950e0752170073a3ffb95e6aded16cad1b75c97a122304d5956e8b6ab56f97a882a646d6898cf17bba094b1bee8cd3f634235946dcba692b9d5dedc31749b950ec99f3a14aac5a0c9380f9b14728be2e6ca2acebe19b3cf67da01b7f8fd52318135330042918b99e3be69722516892f44b5d8b496a12aa8ee637e3809da8c8f85127cdf6d6aa1ee96d60cf92d2b4a43d8b8bbeb28ea1b0eae638b3ae0c1f3a5d045102c0a39b38ad57355b52203625de1af8ffe70298f3e6bc540f5c41cde2cdb4dcfe369d8236839148c921b7504e51aaa7af05b5dac02af188554f5480ec8324a1a74886a1e59d12f7f70fe076102561e12c3fda3ddf5de29f40492d059ec22dd753c11bf760e4609760ad7821ef300da27d7c51781f62dd0c78810309fdfd28125db5cf79732c2e0f21b86e110ac7571a902305e5d29b4ef23365de84d40196a39bd64cf0e2d1d05d2db85d233e0eccea2df2b2e8795ece8c52af82d19691eabad1e5c54d5f4b6bf6a90a7e784085f1a92ce04462bdbb2efab85e7b4197d6f5b189e9fa021df67da67804752d71e7606b62cd8852d49e1afdf6d8c9ae2446ab3f2f9d8145ccb13f078a6e8e44ab0e3a312c9d8899ebe14636ddc8ad6e76b95ea8671c7d8f746c5f21dc9b1f55c9330942d24e80eca6d1bc72ffce2487f53ec30c12cf916a953ec0769ad8485124b1663dcbfbb5afde548cadcbc8cf42caf3604cb5c4263be21e9ee8a6f79281d68200260ef579cc1755e1ff1b59cbbae120b203baa184eeda9c48225fd2e8f3f3380069bfd64c90fa3b532fc66878b9b84eefdee980f8d4b350ff86ee859f556242a4d7997db548bbcc4c9c7a1a9ba115c30cc44c3503381c79082cf73180ef8ea217b434e408ca22f4a9f7616e6a0610c33c387fb66d35ee77b46a06a6db5f47cc0a4f0866a4533dab446b699f4e3e8e6e81541cbd69e25f782f04af4df187cc80f9481b1138ce4c3a615a771a43b16cce516a3555b6323817c7dd593f313052b216e9f1c13f180e5a9432a26a33e85e1a5ad749a8f89fc614328c05d272c8b570ba71bea16142558b77741496e772be391268fe7f86ee5d2589e7ffec0ef520e5fc5033c85d1a22ae62ae44e8b5754f8b6efe6c9c87a05fb89eab10d2aa1a0c9bd86109608c5509dc24ad71b453c57717d9a7b23678322e1d234a2fb6de98ef2a301c0ec3bed82295f03fd00b8b2e27802a0898b575263d2c63bd49e2315ae113658a409dbd22a9697570adfa3b759ca6c46569f45d8bf640f3cbbfcf7f64dd67eddc6b85ac3fd12d69e7dfd52bbf60ee7f9625455787350df87223b6b28c3d4b58af56dfa5e3312e0481b4221f9819b73bcb2de05e8809b8310a54e58284475e778e4a89b863fd5712803bd480c917486390d3ebd34d0e8c011c472797b5cfbe85cd94c1fbcd3dd1023954df70971f60bfea0f4fe72e038482f1d2a2eb9270e86a3ef6770962cfa35c67b09d4a75be8f8e637ca147d17671c04f49643e7eb858de313ced793e820c2b9e69455a9f48cf97eb309adb1183ca42bf75ba058886dd55959367e65686babaff12ff09a98c4f66f5d024ffa0e6c18e9727628d61b027b628fe02719c7c2f2b8f17159d227ba327202bc57c97bef18bd54396ee2eb6ed10743ba68557b74960ca34288927b3cd46d75d645a5f90d0a4487d7f3a9df215b60903da9e135381aa72818f67c84f4a1f94e46a06225c394afbb33511ae3a316b60bf36ba817ca3af9278cefba3577396e734a7cf96dba1c119270723d89511976c07783f00f852f76aab855616145112928afea45b455ce5b17746574d1818a8dafb480e336874eefa0c16644850c242af94acb9318a9770b596e1ddad27c56024abb9563c1aa472b98d4c8c99132017ea358d4f42c4883160ec1e10100341569c91ed20ad0b3e67565d2cc3b1994654052a56438c1092badb11e43a8f889f9abe3d4f225f596fc37fece7dced1f2612b585b2c1451aca4c51b12f99ce44142080a82a7663e39efd89a76c65468084c2bab3e8b374ea93907102b16851e3d9459b1c3c8ce58f707454089d522e2c1e5ece8900db3fb73ef454c2ea58ebb4d45022a19cbf9bd1b9f8f5eeb3fe54fe96c5551cb2a0c2707f5f61e833d91b4540027cd0e7a0c43599a0fe52b694b704b7bcb16eff741ef0d51b216e1193616cf0797220e1d57949de99d396de70f453d3d6bb59c017eb998f43ef9eaaaba6c8409d294d10a6989d17bc8a27bae4f58b564d6c07e8c7e23d26fb9a41331c4b1ed0c4d9e5f2cb2054fddd00e1833d70dfed40a683cff0a52ffd110a31efadac2bd84ccb1e9d25e6d8785358258792ba1dec0c3c061eb5942f98b927ae6b9035bb5063003eb444dd60a93381bc507869663f44cb5bc9ae40a69304b79f2fe3429c26282aa11a6f6e3fd9a69f8abc4da7b8d9a97a9abd134e741837e6e16a5d89e4451c6130157cfa5b465609f1f555fc02d4f025af394ba117a70d8fe41d6adb6572d27bea6469fa333aa387eb1fe796521cad66c7307871688e171038e0b8aa7d0dcb975f8242f5b96366aa893650ed8101d4e378533e1eb44581dee53518a26fb4930d75db4cbb9b3bf802eb32022f4dbf8544e8e3ec5859b63eb3bdf04ff68cf76db5ab08e11ad9a7c270e067576d5db16bb38e31481806066523582e9b4629aae898a4b73865942a09376e8a407ffedb6cf9844027bd678e1f3525c2bf68239e10b7f55c4ac048924236643af4a365c34a989d7e07195ee21a2fafcc707baabccbe6b87c66b98f0df961e452d18c88e03b4280e4968000eab4c873b54bd6475397d6c9bd0c6cbe378824cebe477cbff6fa9224016a97c4979807399bb3aa103355a840159d3f301520a4ec4953fb60282d86649dd9549dd3bbb6395361db6fa7b7b9934415f971ece21fbd8b1ed4c8dbcc44982ab20a24bdb82984e22205b1d134767027ef0fc8bd4b7092e38a17393519afc016adbd2afa9de046b44d576f502c562c89a821e20ab4817a42b754be49b8cca51f27d1eff4c9309283d8c45dc7238ca553ba91f6afe9fbf1d922ff29f0663268bc92d1e4d809a7e21a3118c09bf4ba0a3ad8b4c5141836f00ab84ace60fa18a0bd4e87f7342c9369807613842aad209b589e5c0722a2fba2dd4d5068fb634fa6a92196a690182b51820f0d54c5bb59dfa6cb6f085442da50166f69b2539f9de57f412c05775f36806ef402cd1307395668decb30f8294467a1f529d9550eb161fe6643c244cccfc4df9bf0218852ce90d40c192e34634662870b2ab519124276b6928a11b9d3c37a0b14f319d53d0c6a15151d408ab7aa2eeade34daa206d3bfcbc8f6b6d63d3f9dfdceef8a1bb104143a10e0f7de7289002e5aaf641cb6f386a50b10bff91aed7232ed346279d1084ef804d145469f5266e36159c632aaabdfd3726ed7887edf311a7b82b3bd0ddc1da5782e0deceaf4e9f4397ed845d0ed9de683327b03d7c637300145322c16a52181d8183fc9b51d0ac0edc3c4efee2b61e370a4627c45fb1a4e2366fb418407f6ef1ec5c0bfd786a591f20dd8c1bf3f99f75422fd179968ad0f7e8307d30b84fa304f99ce57adc371850259d607bb94b76d82346d4b27d910e82dafd6a54bb73dd8a7e551bba6a122a65c14d06cdad3a327541cf3e2fce6fbbe5d428e4cffdc0f732350c1a9de9281c177c4fa1477511dc4acd9b4d881e135e294fe68304a56f94cfb091be77b2988e1f92f17b79215a1fd8eaeb4b384bbdc7209ca472bc65a47acae7d0d9218c8688117a6002ebe792300f2399f0d70243488f9133b0aa91ad3bee34b2c22f901b2bb21b4b7dd6ccdf2cb62a318abcd21b9374ba8df04abfd774608754d2f955208ee94bf8eeae8cbb44963b81cf8fa4790d3954b9af86c838f1c7567444c7847d43d3d4d675183fcc499b1039dda57b990e6bac299dd7bb97a72bc2947055e8973554a3cf401fbac4238c846cdfaeb1753f7a89674833856ed55c989570046cab65e38969b49f4f2606f7f5e7569e6f83321a3b0ea9bb6aa7a7e965c7136bd4cfd6b181fa61deae55b40af38c820e06f0175d444e7f15dddc9fc8fedd1ee2cf9933b0c7e5376f1bc555f90bd4de8a7300914e22ab77a8632e9ae06bce327f9e732d79cbed3696e3d10ea36b036d15592d38d74318b3d3b189e482e42b446a7af1f12cdd3c531de58d6acb59a115952870f81aabbc068d170f803ac6a719b24cd5003d6bfb585f822a27256b87e580d0784f622f7295ff337b3b92aa90eac4b613b022d6b7e45944c57018b5cffc31ba9524fbfe10a653d91924cc7cee088cf31adda5583087acb19affdb5373d1edb95c9749a8c590aa71d3e1a50f8008317f5d831bb7d8652be9a3a6dfa2c05ad0b5108d9c533d82f41fbd17f35301e4ce09c9a353f8c72a9db50a1dea193740aaf5a5c6bfe2fe2a1a2d525aaea7d8075f451f403dfba5ca386053b4c20fd38f9c73dd1c0eae3139f2e3f94fd34e278f499c9e65539c287824e396a3dcb0a9fe00ee5a5902a2b0bd3456db0444b086a1573e7544b526e56028e58dd4b11e32b4637ed91a40136040f98c7a5c1a5d1718c82db7908a0c263627e736e86b2611df647013f59ce1ddb8be04fdf40ff644a87207598acac2325e7d91638b5e2b9a68ed08ffa24155866275067fb3a4ca77ff8d4de6483f477be6733206d04ffe06abdaa7868e9732487b478425fa862f266c260e4845e34297741d65fa060000df10acab8c96d8d5665e2d64da6afd54e688df4df9e36173c956c1c16858282d30a6606817344f7d"}, &(0x7f0000cd0000-0x4)=0x1007)
getsockopt$inet_sctp6_SCTP_GET_LOCAL_ADDRS(r0, 0x84, 0x6d, &(0x7f0000534000-0x31)={r6, 0x29, "412bf96a8e221ee5de51dedf1b8687b8d4849acaa443d84fa735af4d5880d7fb47d9c1a57762d18819"}, &(0x7f00002a4000-0x4)=0x31)
r7 = openat$rfkill(0xffffffffffffff9c, &(0x7f0000046000-0xc)="2f6465762f72666b696c6c00", 0x1, 0x0)
ioctl$LOOP_GET_STATUS(r2, 0x4c03, &(0x7f0000343000-0x98)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", "0000000000000000000000000000000000000000000000000000000000000000", [0x0, 0x0], 0x0})
openat$autofs(0xffffffffffffff9c, &(0x7f000005d000)="2f6465762f6175746f667300", 0x4, 0x0)
timer_create(0xfffffffffffffffe, &(0x7f00007a0000)={0x0, 0x1f, 0x0, @thr={&(0x7f0000921000)="474f07a08e9378e0e7fc3b2e2c04e346a71ba48f788350ab759265ae364ae4bdff5f1bfaf9f4f3d5675e3934bf7cc31333f6f06b44b8851533636b4945144610150d0a", &(0x7f0000569000-0x2c)="479421606a0ff1102d142d2fcc8d98b062b01b020eb9df1665726ebd6c04bc1d3318db705dd05d2d29e7332c"}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f00001e7000-0x4)=<r8=>0x0)
clone(0x0, &(0x7f00007b5000-0x4)="2a3ab350", &(0x7f000081e000-0x4)=0x0, &(0x7f0000585000-0x4)=0x0, &(0x7f000019e000-0x11)="8b42a068e8c5cd1433feaa7667a434be")
timer_delete(r8)
setsockopt$SO_TIMESTAMPING(r7, 0x1, 0x25, &(0x7f0000341000)=0x90, 0x4)
set_robust_list(&(0x7f0000a78000-0x18)={&(0x7f0000970000/0x3000)=nil, 0x7, &(0x7f0000e77000/0x4000)=nil}, 0x18)
syz_emit_ethernet(0xbe, &(0x7f0000fe6000)={@local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [], {{0x800, @ipv4={{0x5, 0x4, 0x0, 0x0, 0xb0, 0x0, 0x0, 0x0, 0x1, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, @local={0xac, 0x14, 0x0, 0xaa}, {[]}}, @icmp=@dest_unreach={0x3, 0x4, 0x0, 0x0, 0x0, 0x0, {0x25, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x11, 0x0, @loopback=0x7f000001, @empty=0x0, {[@end={0x0}, @timestamp={0x44, 0x14, 0x0, 0x0, 0x0, [{[@empty=0x0], 0x0}, {[@rand_addr=0x0], 0x0}]}, @ssrr={0x89, 0x1f, 0x0, [@remote={0xac, 0x14, 0x0, 0xbb}, @rand_addr=0x2, @broadcast=0xffffffff, @remote={0xac, 0x14, 0x0, 0xbb}, @multicast2=0xe0000002, @empty=0x0, @rand_addr=0x0]}, @lsrr={0x83, 0x13, 0x0, [@multicast2=0xe0000002, @rand_addr=0x0, @rand_addr=0xfffffffffffffffe, @multicast2=0xe0000002]}, @lsrr={0x83, 0x23, 0x0, [@multicast1=0xe0000001, @multicast1=0xe0000001, @multicast1=0xe0000001, @broadcast=0xffffffff, @local={0xac, 0x14, 0x0, 0xaa}, @multicast1=0xe0000001, @rand_addr=0x0, @multicast2=0xe0000002]}, @cipso={0x86, 0x13, 0x0, [{0x0, 0xd, "df21741175882f00000009"}]}]}}, ""}}}}}, 0x0)
ioctl$FIONREAD(r1, 0x541b, &(0x7f0000cb9000-0x4)=0x0)
r9 = socket(0x10, 0x3, 0x0)
readahead(r9, 0x9, 0x9)
ioctl$sock_ifreq(r9, 0x89f7, &(0x7f0000f41000-0x28)={@generic="86b522e451b2954b24a58ac02c94e51c", @ifru_ivalue=0x0})
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfdf000)=nil, 0xfdf000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$kvm(0xffffffffffffff9c, &(0x7f0000014000-0x9)="2f6465762f6b766d00", 0x0, 0x0)
r1 = ioctl$KVM_CREATE_VM(r0, 0xae01, 0x0)
r2 = ioctl$KVM_CREATE_VCPU(r1, 0xae41, 0x0)
syz_kvm_setup_cpu$x86(r1, 0xffffffffffffffff, &(0x7f0000004000/0x18000)=nil, &(0x7f0000020000)=[@text16={0x10, &(0x7f000003c000)="66b9800000c00f326635001000000f303e3e671109260fc75edc2667e100ba420066b80001c0fe66ef6c3e0f01d766b80500000066b93b3c00000f01c1bad004b00dee65d84cb2", 0x47}], 0x1, 0x0, &(0x7f000002a000)=[], 0x0)
sendmsg$netlink(0xffffffffffffffff, &(0x7f0000029000-0x38)={&(0x7f0000fde000-0xc)={0x0, 0x0, 0x0, 0x0}, 0xc, &(0x7f000002a000)=[{&(0x7f0000005000-0x10e0)=[{0x9c, 0x0, 0x0, 0x0, 0x0, "a1fcbb03cf350684172bb18014c84673232325c57233bae56b7cff943bfbf0a009ac5f41e928269a0687e6a80720d91ecea91f4efe30d7430ca318903373357c67c674d07530b8bacec8d59ffc8cbfa0bdb420d65551f702d65679d82b6e3a5aaab19209ec38efa0fc91cd3138516a2f888210720531defdeb7f7834705d88d749ffb7faea7db6764fa8c5cb"}, {0x84, 0x4, 0x800104, 0xd078, 0x2, "8214e0a96ee5e6176ed7500c45a2409d05e7c3aa6ee97c70969ff29268faea6dda8e586dc84d54da82e17017c2070014d2b37daf909bf8e68c83b223b33d1616d09d6d21b0e65c499e926b52aeeb2b5ccb1b56012fb54e570a150318339100f8744b2e8feb8f8fb25dedb14ed183424b16392584"}], 0x120}, {&(0x7f0000fde000-0x51)=[{0x51, 0x7, 0x40000000020, 0x800, 0x7fff, "6d4bc50ec07a8442f4c5ee7a8380edd487d41dd3f2f233f063e7176059eb0eb829d68c4f10880587debe5af5e10fcdf48a1c7d1c1c4b9d0339587ce9bb413667b2"}], 0x51}, {&(0x7f0000016000)=[{0x1010, 0x12, 0x100, 0x0, 0x3, "3e69ba10ed7a9647b1172ca5d14b679930143a8e9d7c2fe01a1f400d3f31cb34756e80715fa5e6ade8ce51a0edd2400ac08b3104c87f55378f3f78c46ef9e1323c7674df2cdc59e0e24728ba7def683da98b63780caaa913ddb768a4c77d63e48b6459fe05b513fa7148344b5332446c36f21b6e434bad8f5e7a07aae5c5f85f06ff5df97bfdfcc444d62e758865bbc9560ebf676dd826c3a056b79c066490bcfbda9046a9f180306096d278892af26385b1b0d3a58ea5cb9bb19365363166a88f9320080ddf1b42624af6088992b55502fdfc3a2766500a515f62eb6179d89713c6834096f2f88aa1bad7edce70f159e78f05b1defc8c0b1ddfd3ec236311b38fa762b54e69fb3c25ba2f5356047e8c080d79dd4fc4e45876de357af3413e1939dc344e9bdee97ba529dfba9281269022f0f2015f332dbbcbbcc044d4dd36282121e41d1381a82cc3df4f01caf5d89f8c325784ad2167755dfe6473578128c0b99346a4ae745dd8e45eeb0bb63c67c64b5448d11057d0e17751fc00a336391ec727b0dec3042744e0a0ffe35debcb6bdacc4c9d6a5b56d6a4387bf4d93abf95f0d7a36234d2490b342812c8c64192ccba8f7d3c404baee4c78cc03baf249f8172937197597bb69b7f4fdd8294c1aabf4e434617904e0f11c669ed76ace510740823c894c2e4e2e3177f7d4a0b86d5c095f1758a53ecc437ef50f6ae04af1531f3f8198b42d7e4c0f0f17a0c6c3f6ff2b1e3772bbbc02dd8117d5d65bf0e7410369449b3d08efbedb933895ffa8040008445e1264eb13475c3a868c0f98e7b0447024bab425417e80a0a48fc580882a308b9f9ff319717a92715829aaa4e511609474245fe4368188c8aa335bebe1a59d5f321e321de5477f8246c2a3d8270dd35ccc5a777f704b9afc8f2e9d3e441faa9f92c795e183bb78359646edc3f1e07e14fab797ac33b381eccf2f8e341786921534faf0ddee527c39ccdd94529261e31148d82f15446202dfcd8136ef490d6748e02b4e2070a151687fac3488c21b1bfab3cc2158c1254e7f4de75db67af6783c78b366ce8a8833acf1b83af9b42d19a25371e7cd31d24cec1c87fd9f7139be3a4cbbe19e8a27f718356b13dd2e8fe86d1eb840bd70290230885e7f77563770d33ce711921994c4d1c1fead9d21754c707857719473bd52f9b953631eae762944cb42aa8ce6034c8def66c5f6abb114a6b6e48682dd43c635768d99e28db592382249209e39bdff6c1049777fcd853350942bcc20b59f9a1d8dffeac631393cd27ce25dba5b3d075700dc6c7090c631b8e163ffa0745ff96d35b2e63b5dfab3a39d3589ae1399937823f4a790b0231fc67f8fe236ab7ca85aea88415acf072727ae59ed9c236bd722afd7b4aa71258fd256cc6b9094bebb5166a58af13f8fb7d0b48a61d6b63b78c62e9b7b09bfda03e262ac008b5f4dcac4c97e2c54168fd611862786a2ab8e4b18efd78a47878852e543b2539d08422cf4f05eb72e8923641cce97cd21be8c8f9107e32cd08e96c9bd6c79155fc05b0ccca662a71af92ad453d91d863de7f2a2625499ae6471cdb5aadd7f7028c8e502543ea63accf5c6cf4c1962a089606e5bac1bd27e7133912ed6d35f52104d055128021ff18b7fd5d981730916ef7801ca20999d88c28685a9619d31079f28dbddabe6c66cf4aac151c158e48d712b06d14196d057db5cbe8f27c7ed29c03f9c623dbb8fe099464d7251e4b19dc77e2afeff1d8e5068689253e38215c96de7be5866413d0608ba1bc512a9ecbdff5c0cf4519844797cd1bda4a2984c26a59a481837f5bccf928051ef48ed5379eeedcb7787926dc0bec609912ef9b53cdb04be5e089a26b6d354eec1431091d2c44e59aaaca124d78939a51e17e8eff08e570cfbdd8865a9a7c6f6c33260d3479fe7f3f7fe84e16c5b4812dd37d5c0eac81024decefa52291fae2ff7f266bf1dfa50c00d47cf4283595cde33ee046a2010a2729ee3fa9b49c4b8a4646bcde4f16ba511e71316afbd1300cc5651e8e4ad9aacdb0b73740cac2748afca64a447cdeda26569bd12bccd18a5bf7808b5df675ab4f14c47cf20c2e580fef6a170f88b538e2f08728722ffbe2e79ae168db0e2435718388cef085491919574d0c5dfc0149aef155932adbd96ceebd4b686999d224f457a2a148e8fc767855141e821ea4a4f3db03c3c9d5d8fc5a0286ec8cf9a155b9626521fd3c88fb5ed313f78e7516036ebd0fdd04ed137f8d4c1280f7c22678309bb01422c161708f185c2a25ab6a6b9cfc32a79037f5981cae935de615e96eda2b8c16ca14582db2e24535f6c6396465b3dce9674a9b0a801154ba4ba5c164c7dc50d9686711c7cb0faf285c19beead3213a6c7276bd86b7261d0d4d344c1c6b1de9d85bdcaa64dd5102f7f7f22858d4f3d601d22611de4fe5a97e4146096d2b4c998634d79b2df750b917b5658d7c9109d682a4da1f676bfd5ca00d308c868df570a9278ae7f93f80b212f94905a552138c21a67cadb173af70211dd7ef8f0789b0c1faf92586810ad2d9b040ab839108700fa7c59dc75f6bd292f01f219e6a17b6bbc2d3693dd48020d10669718305a8543e0603c212209d0b3554245391e9f42123ad6478b53cde76b04cd6b7e74775b4345cba8f7c4bda42e1ed8f050eed207c8d738a5ffbb6103c68958404c62553a5b2f3d501b8c7c4d2e189c377844a463c7e55d57feaf794425dd778eaa7ff71a66227e0faab18ad8d3e2765fe2eba91f9c0c60cf32cf3eb4c2a42c732cb5bea0638ee21902c92b0cf5e05a3742aa5c1e27c236421f4dece0b156f21eb156effc98eaf6a6c68113631ffb9b770b4a57f4980374126aaaeb1b93bf024ebdda4ff27dba4f9bbf3bea59e405cd3f3d2560a4bcdec69f038ae19fab49dfcb116e5a25bdb8dcb84807d019630cf26ecfa985685631cd51dacb7c983e11aa557048ef23f28ebbdb550d8b5e8fbdf2b9fe3078d7644c3501cdc696eaa6832566d02833e884cff87d167738847e0491efaab3fea17fc1c583108d25ff8c5ff9134f8e9f0e446624c86bafd3dfdc86237dabd298b74a2ee7cd05f8bdbbc60569fc7e5425a24416b69550c3609153a1ffef01a42af86c92489518ac475d7b2ea92d19b2bec388af7bca40fda864933402c350df7e701d04d474f420ed8e5c6253e08d9de81aa4ac6bf6ea105338857bb3186b3f2bed931f5c1313877c05e8d1878a144d5dfebbbf6f4c7ded0cbbf076f3c4056fb8ed783b74f5e9845c19c9633852bc8c62c0b1ef4fe47401e58973cfba669dd627f2990b329f97cd136194b965da27d036ed8293d3b3d88aa136a9012a72be4fafe9c66b3d2b6f5d18ac7e245e5d1f1f794ae1dc17101908cda8fc74021e6748c33008246240d53724661f721f5a28cb4affabec2ba209073a5f2e9e4212f9f0fa0aca619cc8a5a3a1e0e0332d3badf667ec97ba5b08ef1fc97101184aa31b0da637ed2a5e41e91ebadb96110d7e63890f7e4e284b4059c640656c542efa0bebca77aac1457b75b2017efdeb844f25a609c99f4a64eff1607e1b96f899dc353201a00001f45a96636489060cfa5d8852599210011f06d4ae504fe85f317a65cd5cfa0b2c7e921bac91df601cea2089b4001c6c6a4487bf0491420a139a7afd089a8a82f8215f2260e296e075de7bcd8dc2b0dd9fa20910ab20235d303061248fc4dee0f6b64e6ec3a634f5ab4fd85d0e321da41606ec5759a70cb24b539b727fb42619b86b2a9b0aa868e2dc3f238cc17e70f8e4ecba58a550876311d0def3ae239121694df67d75af6860d8e3b26be914fc89764cf1c6210231aee2fd1b7c26ddcc28dcbc28cf860a7ff4367f2adb4ef62b07e59774c9219328d03800b822523a7f4013bb5bcd8fc5dcb565676e88aafa1eddcf99a11b5981de0511592021ce5d53f877077ad8bf1c3410f0e518305ae455b6c697451e06f4b82b05ec0c01b34ab634689627a31bfbdb7e818c4b3d1480e59976f6cf9fc411250362d03b0008242d2130df38b8ac82eda45e042818e5234f36eeff1b7f85997802938e39aae96b55c039a2b5909cb11904d4ba54be828e808e5033242b6b8f96bbf96f453805ebba49190be070b373606fea9e0027d5407615599cef2c70841c28ad42dcf9a4b4177c3b7484777c06e540c8ec08af3a9ba635052d26811ebc58799b4ba2020bd2eb57c691ac4eeecd80660d300c2ae561cfa84fecd5318d2ef6f40654e6739e8efe5f7a267cabfd87b2aaff8229737d41d66b6bb5b46307dee46af788615f72a5b4707a883f44cd3a7211225d072689aaf50e538ff68aa2202d4c5b93f015d692d17015188063c8e29ad938744f85112198ee7fa8fffde371682f9d8b9837078c2ba6dee26c8191330f1097a205e119c1c3778620d0a926b819e64e3a396a2a8533413b49857ed40eaf750cf1168bf48b8b66ef307763f0eca978365f10120b7c89ad0cf24ed0bd4aefa39629f8f9482258149d90caf502057d840a659b18c26fd36e46b8cf501f1764820719006abc6591a72e44952fa79f6415812a008864098caceb438bea2753b1f3b96398b0341976f16eb2f905e5eb8fcbb998a28bef1b7b78136a87dfd9f611d32329d1a7e21f77e33c248f11fc84eac47bce85d7a70e634fa962233a02704fbd4eb9e45a746f3f2abd6c5e50570ee9550e3dc92df455d3c1ba8c4f8c95222453cb866f4f0bf19ab71799e1a206f1c2d2d9e0a691cf9071ac99db668fb3b036cd970c0433211669fb30800dc6036f381079b7d3c44e6dca4a8ef0f98fb55ad91acb566a844e704c09d870579c739c39a56108f2c9d6babfe40d16d3836fcc5b3af4818c24a2e1160093cc8212e1d24e5283d129f12d654398e3c6496787ffa9db98228e704c0196c25d522844e9872a081040b3f9d61235cb59d3d521e0b09448cfd5d88316e497ece01f6ee779ce0fab62fe9bae9bee628ffd5f33ac79564b7a59c9b087cc5520d514f2870853f62ebf160013866c099bb357b09bfb28d1c5a3b0846dc0734d43786ccff341f65ae9daf8f0bbf02d5fc705cc69ab4d2dd764e6851a68ae9fb3fe13be8fbddcab9c162aa8b1fa0dce0a5104ed8435df29b99cb255036413e395fbdd625e3e6e5e981b3e56086b86e8e586e4836fd4db0085806a7d70de5d7f337c1dca758babbfe2a724aecb7c31172fe0612268e4208f0e656229a09e13fb6f992f8d0d14c704c7fbf8b68cb883b0de97f4f3004e1345e0f2d60489c233b2f0ecd9b9c47f702fa1d5f805c19ca8f58f52c20be2d10c53890c26f926dcb8855189250bc137c61e8a28ca97dff7e40f909194df3ee01c226961a5c55bf7e3d0f402f020c84435a1e6ea55dfe4e272f79fc3678dd442962fc88825d8266adfebfdb0b9f7fce0439a9ce746ddc10cd1ca0ffa3ebbe8ba1a95a85e933e91a0e019945135c8b56f9128ad932e7f379647ca1b2c017e466f87c2cd6f39447a59ec2d45ed9d397ca63254048e1870eaeb0b2246d5a54f958840de9e5569e83a52eff628004440e1c02bd9e9da9e9846aec2a34305269a1a0210cde43672bb1e0a7832b1d707fb040afb1241d13f42d0425da46d1c230af38cc8874b9592f4bacfe99a2ac9c874f0c651828e016c9dd85e10918d3b6bcab35434daf8bca15e6055eb2941893b42538f44988d3e7d3ffbe0b3633535863bef54979279b51d4c24049ad5259135615141d1fe70bbf586ef4d2559148cf6c67a2fcc355bc272786e653e848e5220c9b6293c2d59d"}, {0x6e, 0x1, 0x108, 0x100000001, 0x438, "e36bb35ea5f7e0b53c83405175abdd7505e039ac27cc53970c9bf4344a5927b46c4dbd5933d5b2ce96d8714aa53b467f6cc093e36f29d4a4b191d89be0130e17c4516d92213dfd1c9f7e1daa2b70260527e15469b7e8c061754abb447eca"}], 0x107e}, {&(0x7f000002a000)=[], 0x0}], 0x4, 0x0, 0x0, 0x80}, 0x4000)
r3 = openat$selinux_enforce(0xffffffffffffff9c, &(0x7f0000a73000)="2f73656c696e75782f656e666f72636500", 0x100, 0x0)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_GET_LOCAL_ADDRS(0xffffffffffffffff, 0x84, 0x6d, &(0x7f0000fdf000)={<r4=>0x0, 0xeb, "1278edd3c67d7346efaca9bccbbc0f3c444787491a712aebd2e4dad21a1b394c74a010fa186c320180894b7188f927cd9370c27ac422a54c86c5093c524cdadef17fd60672812b4a4c580eca0575487fe73647fa143fd538f895dd2142fedb5d7aaf1347d6b8d939c74fa3c1964d9f4ec6b8c4a973da77d670e3b6b0de392572972f5ab5f429ba0feb51986331347a75c95b98dcc8214e78e4d525eee8ba6513c198f5a0e69fd0fe7bc1220efd794f1a0bcd9ac5602d429101022918eb07d5de9af4a016fb697bfb9f5bf4ddf6eb4d320a3f906ab10a6cf2a54dc0a04ff421cffa158d837a85d24ea161b3"}, &(0x7f0000fc7000-0x4)=0xf3)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(r3, 0x84, 0xa, &(0x7f0000fe0000-0x20)={0x5, 0xffffffffffffffff, 0x9, 0x2, 0x8000, 0x2, 0xffffffff, 0xffff, r4}, 0x20)
ioctl$sock_FIOGETOWN(0xffffffffffffff9c, 0x8903, &(0x7f000091b000-0x4)=<r5=>0x0)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = syz_open_procfs(r5, &(0x7f0000fdf000)="6e65742f6970365f7461626c65735f6e616d657300")
syz_kvm_setup_cpu$x86(0xffffffffffffffff, r2, &(0x7f0000005000/0x18000)=nil, &(0x7f000000f000-0x18)=[@text16={0x10, &(0x7f000002a000-0x85)="ea7e00d500660fdcebbaf80c66b817c5448f66efbafc0cecf0290564ae2ef3a7b8ae0066b90408000066ba000000000f3066b8cc6200000f23c80f21f86635080050000f23f8f1ec6766c7442400c300000067c74424020f0000006766c744240600000000670f011c2466b80a9000000f20d86635200000000f22d866750000000e0f23f8", 0x85}], 0x1, 0x7a, &(0x7f000001c000)=[@cr4={0x1, 0x240000}, @vmwrite={0x8, 0x0, 0x9, 0x0, 0x2000000000000, 0x0, 0xfff, 0x0, 0x401}], 0x2)
setsockopt$netrom_NETROM_T4(0xffffffffffffffff, 0x103, 0x6, &(0x7f0000004000)=0x8, 0x4)
ioctl$KVM_RUN(r2, 0xae80, 0x0)
ioctl$KVM_GET_XCRS(r6, 0x8188aea6, &(0x7f0000823000-0x98)={0x9, 0x8, [{0x4, 0x0, 0x2}, {0x9, 0x0, 0x5}, {0xfffffffffffffffc, 0x0, 0x20}, {0xd2, 0x0, 0x1ff}, {0x5, 0x0, 0x5}, {0x8e4, 0x0, 0xff}, {0x400, 0x0, 0x6}, {0x4, 0x0, 0x70}, {0x1, 0x0, 0x9}]})
[ 51.005592] audit: type=1400 audit(1513338807.257:1147): avc: denied { map } for pid=7450 comm="syz-executor3" path="/dev/fuse" dev="devtmpfs" ino=8836 scontext=unconfined_u:system_r:insmod_t:s0-s0:c0.c1023 tcontext=system_u:object_r:fuse_device_t:s0 tclass=chr_file permissive=1
[ 51.023693] netlink: 29 bytes leftover after parsing attributes in process `syz-executor7'.
[ 51.058439] netlink: 9 bytes leftover after parsing attributes in process `syz-executor5'.
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0xc51000)=nil, 0xc51000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat$selinux_context(0xffffffffffffff9c, &(0x7f00009fc000-0x11)="2f73656c696e75782f636f6e7465787400", 0x2, 0x0)
mmap(&(0x7f0000c51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$selinux_user(0xffffffffffffff9c, &(0x7f0000c51000)="2f73656c696e75782f7573657200", 0x2, 0x0)
renameat(r0, &(0x7f0000391000)="2e2f66696c653000", r1, &(0x7f0000280000-0x8)="2e2f66696c653000")
mmap(&(0x7f0000c52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_ADD_CTX(r1, 0xc0086420, &(0x7f00007ea000-0x8)={<r2=>0x0, 0x0})
mmap(&(0x7f0000c52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_RM_CTX(r0, 0xc0086421, &(0x7f0000c52000)={r2, 0x3})
mmap(&(0x7f0000c51000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000c52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$vga_arbiter(0xffffffffffffff9c, &(0x7f0000c52000)="2f6465762f7667615f6172626974657200", 0x2, 0x0)
mmap(&(0x7f0000c53000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000c53000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getpeername$netrom(r0, &(0x7f0000c54000-0x48)=@full={{0x0, {"00000000000000"}, 0x0}, [{"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}, {"00000000000000"}]}, &(0x7f0000c53000)=0x48)
r3 = openat$selinux_context(0xffffffffffffff9c, &(0x7f0000c51000+0x416)="2f73656c696e75782f636f6e7465787400", 0x2, 0x0)
ioctl$KDSIGACCEPT(r3, 0x4b4e, 0x2)
ioctl$TIOCGSID(0xffffffffffffffff, 0x540f, &(0x7f00007e9000)=<r4=>0x0)
fcntl$setown(r3, 0x8, r4)
setsockopt$inet_sctp_SCTP_INITMSG(r1, 0x84, 0x2, &(0x7f000061c000)={0xfffffffffffffff8, 0x6, 0x1, 0x40}, 0x8)
mmap(&(0x7f0000c52000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$packet_rx_ring(r0, 0x107, 0x5, &(0x7f0000c53000-0x1c)=@req3={0x2, 0x0, 0x8, 0x3, 0x1, 0x7, 0xfffffffffffff800}, 0x1c)
r5 = socket(0x11, 0x3, 0x0)
mmap(&(0x7f0000c53000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$SO_TIMESTAMPING(r5, 0x1, 0x25, &(0x7f000059a000-0x4)=0x100, 0x4)
sendmsg$nfc_llcp(r5, &(0x7f0000792000)={&(0x7f0000035000-0x60)={0x27, 0x2, 0x0, 0x0, 0x0, 0x0, "29c193e1dfff1e3cef501775ff0b40b6b14468d601d77e25c173d597b5789c73c0fa772ec6df150137d2043ce9be611c31b89c2eb9211180285787659fcfbc", 0x0}, 0x60, &(0x7f0000793000-0x10)=[], 0x0, &(0x7f0000c4a000-0xe0)={0x10, 0x0, 0x0, ""}, 0x10, 0x0}, 0x0)
recvfrom(r5, &(0x7f0000c4a000-0x85)="", 0x0, 0x2000, &(0x7f00005bb000-0x80)=@hci={0x1f, 0x0, 0x0}, 0x6)
renameat(r1, &(0x7f0000699000)="2e2f66696c653000", r0, &(0x7f00009fd000)="2e2f66696c653000")
mmap(&(0x7f0000c54000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_udp_int(r0, 0x11, 0x66, &(0x7f0000649000)=0x0, &(0x7f0000c55000-0x4)=0x4)
2017/12/15 11:53:27 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$sndtimer(&(0x7f0000fa6000)="2f6465762f736e642f74696d657200", 0x0, 0xfffffffffffffffe)
ioctl$SNDRV_TIMER_IOCTL_SELECT(r0, 0x40345410, &(0x7f0000001000)={{0x100000007, 0x0, 0x0, 0x0, 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
r1 = syz_open_dev$mouse(&(0x7f0000153000)="2f6465762f696e7075742f6d6f7573652300", 0x0, 0x40)
ioctl$DRM_IOCTL_GET_CAP(r1, 0xc010640c, &(0x7f0000600000-0x10)={0x7ff, 0xfff})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x2e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
ioctl$EVIOCSCLOCKID(r1, 0x400445a0, &(0x7f0000980000)=0x6)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = socket$netlink(0x10, 0x3, 0x0)
sysfs$1(0x1, &(0x7f0000911000-0x8)="402d2b7070703000")
writev(r2, &(0x7f0000618000)=[{&(0x7f00004ae000)="39000000120009040f00dd00004000000700004a03000000450001070000001408002e00040000fa0000000006080000000000000000693e4e", 0x39}], 0x1)
ioctl$sock_kcm_SIOCKCMCLONE(0xffffffffffffffff, 0x89e2, &(0x7f0000fed000-0x4)={<r3=>r2})
setsockopt$inet6_MCAST_JOIN_GROUP(r3, 0x29, 0x2a, &(0x7f0000b4f000-0x88)={0x3f, {{0xa, 0x2, 0x8001, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1000000}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x88)
r4 = openat$rtc(0xffffffffffffff9c, &(0x7f0000019000-0x9)="2f6465762f72746300", 0x402000, 0x0)
connect(r2, &(0x7f0000029000-0x10)=@nfc={0x27, 0x7, 0x2, 0x2}, 0x10)
r5 = ioctl$LOOP_CTL_GET_FREE(0xffffffffffffffff, 0x4c82)
ioctl$LOOP_CTL_REMOVE(r4, 0x4c81, r5)
r6 = accept4$llc(r1, &(0x7f0000d36000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @remote={[0x0, 0x0, 0x0, 0x0, 0x0], 0x0}, [0x0, 0x0]}, &(0x7f00003c4000-0x4)=0x10, 0x880)
getsockopt$inet_sctp6_SCTP_DISABLE_FRAGMENTS(r3, 0x84, 0x8, &(0x7f0000c38000)=0x0, &(0x7f00009d2000)=0x4)
faccessat(r4, &(0x7f000029b000)="2e2f66696c653000", 0x2, 0x200)
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r4, 0x84, 0x18, &(0x7f0000508000)={<r7=>0x0, 0x24000080000001}, &(0x7f00007bf000-0x4)=0x6)
setsockopt$inet_sctp_SCTP_AUTH_DELETE_KEY(r6, 0x84, 0x19, &(0x7f0000aa4000-0x2)={r7, 0x0}, 0x6)
getsockopt$inet_sctp_SCTP_I_WANT_MAPPED_V4_ADDR(r3, 0x84, 0xc, &(0x7f0000f37000)=0x0, &(0x7f0000142000-0x3)=0x4)
r8 = openat(0xffffffffffffff9c, &(0x7f00003e6000-0x8)="2e2f66696c653000", 0x2, 0x1a)
ioctl$TCXONC(r8, 0x540a, 0x6)
restart_syscall()
close(r6)
[ 51.114080] audit: type=1400 audit(1513338807.257:1148): avc: denied { create } for pid=7450 comm="syz-executor3" scontext=unconfined_u:system_r:insmod_t:s0-s0:c0.c1023 tcontext=unconfined_u:system_r:insmod_t:s0-s0:c0.c1023 tclass=netlink_crypto_socket permissive=1
[ 51.171060] netlink: 17 bytes leftover after parsing attributes in process `syz-executor5'.
2017/12/15 11:53:27 executing program 7:
mmap(&(0x7f0000000000/0xf11000)=nil, 0xf11000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x2, 0x0)
setsockopt$inet6_int(r0, 0x29, 0x1a, &(0x7f000004c000)=0x23, 0x4)
getsockopt$inet_sctp6_SCTP_DEFAULT_SNDINFO(r0, 0x84, 0x22, &(0x7f0000f12000-0x10)={0x1, 0x2, 0x8, 0x5, <r1=>0x0}, &(0x7f0000961000)=0x10)
mmap(&(0x7f0000f11000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_CONTEXT(r0, 0x84, 0x11, &(0x7f0000758000-0x8)={<r2=>r1, 0x1}, &(0x7f0000f12000-0x4)=0x8)
mmap(&(0x7f0000f11000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_DEFAULT_SEND_PARAM(0xffffffffffffff9c, 0x84, 0xa, &(0x7f00000df000-0x20)={0x7fffffff, 0x9, 0x4, 0x2, 0x4b4, 0x6, 0x9, 0x80000000, 0x0}, &(0x7f0000745000)=0x20)
r3 = socket(0xa, 0x5, 0x3ff)
getsockopt$inet_sctp_SCTP_RESET_STREAMS(r3, 0x84, 0x77, &(0x7f000034b000-0x8)={r2, 0x4}, &(0x7f000031a000)=0x8)
getsockopt$inet_sctp6_SCTP_INITMSG(r3, 0x84, 0x2, &(0x7f00002da000)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000f0f000)=0x8)
setsockopt$sock_int(r0, 0x1, 0xf, &(0x7f0000f10000)=0x8000, 0x4)
r4 = socket$inet_udp(0x2, 0x2, 0x0)
mmap(&(0x7f0000f11000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f12000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f13000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_extract_tcp_res(&(0x7f0000f14000-0x8)={0x0, 0x0}, 0x80000000, 0x654)
bind$inet(r4, &(0x7f000086f000-0x10)={0x2, 0x2, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
mmap(&(0x7f0000f14000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f14000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockname$inet(r4, &(0x7f0000f14000)={0x0, 0x0, @multicast2=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000c46000)=0x10)
mmap(&(0x7f0000f11000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_MRT6_ADD_MFC_PROXY(r0, 0x29, 0xd2, &(0x7f0000f11000)={{0xa, 0x1, 0x30d, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x53}, {0xa, 0x0, 0x14, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0xdd}, 0x3, [0x1, 0x20000003ff, 0x0, 0xed, 0x80, 0x7, 0x200, 0xa]}, 0x5c)
bind$inet6(r0, &(0x7f0000a71000-0x1c)={0xa, 0x2, 0x0, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x4}, 0x1c)
socketpair(0x3, 0x6, 0x74, &(0x7f0000f10000-0x8)={0xffffffffffffffff, <r5=>0xffffffffffffffff})
getsockopt$inet_buf(r5, 0x0, 0x25, &(0x7f0000f11000-0x74)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f0000e3b000-0x4)=0x74)
syz_emit_ethernet(0x2a, &(0x7f0000b52000)={@remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [], {{0x800000800, @ipv4={{0x5, 0x4, 0x0, 0x0, 0x1c, 0x0, 0x0, 0x0, 0x11, 0x0, @empty=0x0, @multicast1=0xe0000001, {[]}}, @udp={0x0, 0x2, 0x8, 0x0, ""}}}}}, 0x0)
mmap(&(0x7f0000f13000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f13000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f13000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f13000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe(&(0x7f000036c000)={<r6=>0xffffffffffffffff, 0xffffffffffffffff})
socket$inet6_udp(0xa, 0x2, 0x0)
splice(r6, 0x0, 0xffffffffffffffff, 0x0, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0x2d000)=nil, 0x2d000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000002f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000002f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = accept4$inet6(0xffffffffffffffff, &(0x7f000002f000)={0x0, 0x0, 0x0, @loopback={0x0, 0x0}, 0x0}, &(0x7f0000030000-0x4)=0x1c, 0x80800)
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000002e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_SOCKOPT_CONNECTX3(0xffffffffffffffff, 0x84, 0x6f, &(0x7f000000c000-0x10)={0x0, 0x5, &(0x7f0000004000)=[@in6={0xa, 0x0, 0x9, @loopback={0x0, 0x1}, 0xffff}, @in={0x2, 0x1, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in={0x2, 0x1, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x1, 0x1, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1004}, @in={0x2, 0x3, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}]}, &(0x7f000002f000-0x4)=0x10)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_tcp_TCP_REPAIR_OPTIONS(0xffffffffffffffff, 0x6, 0x16, &(0x7f00006f1000)=[{0x48, 0x80000000}, {0x2, 0x4}, {0xb, 0x0}, {0x1000000000, 0x80000001}, {0x4, 0x7}, {0x8, 0xffffffffffffff01}], 0x6)
r1 = accept(0xffffffffffffff9c, &(0x7f0000f48000-0x10)=@ipx={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, &(0x7f0000536000-0x4)=0x10)
getsockopt$SO_BINDTODEVICE(r1, 0x1, 0x19, &(0x7f0000779000-0x10)=@common="00000000000000000000000000000000", 0x10)
syz_emit_ethernet(0x2e, &(0x7f0000a72000-0x30)={@random="0b234a87f2e1", @local={[0xaa, 0xaa, 0xaa, 0xaa, 0xaa], 0x0}, [], {{0x800, @ipv4={{0x5, 0x4, 0x0, 0x0, 0x20, 0x0, 0x0, 0x0, 0x2, 0x0, @rand_addr=0x0, @multicast1=0xe0000001, {[]}}, @igmp={0x800014, 0x0, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, "09d90000"}}}}}, 0x0)
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$unix(0x1, 0x5, 0x0, &(0x7f000001a000)={0xffffffffffffffff, <r2=>0xffffffffffffffff})
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f000002d000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$SO_ATTACH_FILTER(r2, 0x1, 0x1a, &(0x7f000002e000-0x10)={0x2, &(0x7f000002e000-0x10)=[{0x0, 0x7, 0x1, 0x57d}, {0x2, 0x1, 0x80000000, 0x4}]}, 0x10)
mmap(&(0x7f000002e000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$SO_ATTACH_FILTER(r2, 0x1, 0x1a, &(0x7f000002f000-0x10)={0x2, &(0x7f0000001000-0x10)=[{0x28, 0x0, 0x40000000000000, 0xfffffffffffff00c}, {0x80000006, 0x0, 0x0, 0x1001}]}, 0x10)
setsockopt$inet6_IPV6_FLOWLABEL_MGR(r1, 0x29, 0x20, &(0x7f0000df9000+0x84d)={@local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x22, 0x1, 0xff, 0x1, 0xfff, 0x401, 0xc29}, 0x20)
r3 = socket$inet(0x2, 0x80b, 0x3)
mmap(&(0x7f000002f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000030000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_IPV6_XFRM_POLICY(r0, 0x29, 0x23, &(0x7f000000f000)={{{@in=@broadcast=0x0, @in=@rand_addr=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@broadcast=0x0, 0x0, 0x0}, 0x0, @in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000030000)=0xe8)
setsockopt$inet_group_source_req(r1, 0x0, 0x2f, &(0x7f000002f000)={0x7fffffff, {{0x2, 0x3, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0x2, 0x3, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x118)
mmap(&(0x7f0000031000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
accept$inet6(r0, &(0x7f0000031000)={0x0, 0x0, 0x0, @loopback={0x0, 0x0}, 0x0}, &(0x7f0000032000-0x4)=0x1c)
mmap(&(0x7f000002f000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000031000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$SO_TIMESTAMPING(r0, 0x1, 0x25, &(0x7f0000031000+0x253)=0x0, &(0x7f000000b000)=0x4)
setsockopt$inet_sctp_SCTP_INITMSG(r3, 0x84, 0x2, &(0x7f00006f3000)={0x13, 0x8, 0x3f, 0x6}, 0x8)
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0xfe1000)=nil, 0xfe1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
openat$ptmx(0xffffffffffffff9c, &(0x7f0000fdd000-0xa)="2f6465762f70746d7800", 0x169800, 0x0)
read(0xffffffffffffffff, &(0x7f0000fdd000)="", 0x0)
openat$selinux_validatetrans(0xffffffffffffff9c, &(0x7f0000160000-0x17)="2f73656c696e75782f76616c69646174657472616e7300", 0x1, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = syz_open_dev$sg(&(0x7f0000402000)="2f6465762f73672300", 0x100000000, 0x80001)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = syz_open_dev$usbmon(&(0x7f0000000000)="2f6465762f7573626d6f6e2300", 0x0, 0x3)
openat$hwrng(0xffffffffffffff9c, &(0x7f000016e000-0xb)="2f6465762f6877726e6700", 0x0, 0x0)
timerfd_create(0x0, 0x0)
pselect6(0x40, &(0x7f00000ac000-0x40)={0x3ffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000768000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000086000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000349000)={<r2=>0x0, 0x989680}, &(0x7f0000f14000)={&(0x7f00001da000)={0x0}, 0x8})
socket$nfc_raw(0x27, 0x3, 0x0)
r3 = epoll_create1(0x0)
r4 = socket$nfc_llcp(0x27, 0x2, 0x1)
ioctl$sock_inet_SIOCGIFBRDADDR(r4, 0x8919, &(0x7f0000de7000)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_flags=0x3})
epoll_wait(r1, &(0x7f00007cc000)=[{0x0, 0x0}], 0x1, 0xfffffffffffffffa)
r5 = timerfd_create(0x0, 0x0)
epoll_ctl$EPOLL_CTL_ADD(r3, 0x1, r5, &(0x7f0000a53000-0xc)={0x80003, 0x0})
timerfd_settime(r5, 0x3, &(0x7f0000001000-0x20)={{0x0, 0x0}, {r2, 0x989680}}, &(0x7f0000037000)={{0x0, 0x0}, {0x0, 0x0}})
epoll_ctl$EPOLL_CTL_MOD(r3, 0x3, r5, &(0x7f000003d000-0xc)={0x7, 0x0})
getsockopt$SO_TIMESTAMPING(r1, 0x1, 0x25, &(0x7f000051f000-0x4)=0x0, &(0x7f0000306000-0x4)=0x4)
r6 = syz_open_dev$sg(&(0x7f00009e4000)="2f6465762f73672300", 0xfe, 0x80)
getsockopt$inet6_IPV6_IPSEC_POLICY(r6, 0x29, 0x22, &(0x7f00001b9000-0xe8)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6=@local={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r7=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@remote={0x0, 0x0, 0x0, 0x0}, 0x0, 0x0}, 0x0, @in=@rand_addr=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000910000)=0xe8)
setsockopt$inet6_mreq(r6, 0x29, 0x16, &(0x7f0000526000)={@local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, r7}, 0x14)
getsockopt$inet_sctp6_SCTP_LOCAL_AUTH_CHUNKS(0xffffffffffffffff, 0x84, 0x1b, &(0x7f000023e000+0x1b6)={0x0, 0x58, "76dc3955e2f817b1aa72c5c6aed3a8d7bd29737920c0149161832a2e124ce5062245ad17199e202b3fe4f9c200d77500000300000000000000d5d200052d3b1d801e290b00050000000000000083078343b424bb69ef2cbf"}, &(0x7f0000f79000-0x4)=0x60)
userfaultfd(0x40000000000003)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_SET_UNIQUE(r0, 0x40106410, &(0x7f0000f32000)={0x8d, &(0x7f0000d2e000-0x8d)="cda6f3e24cac61cde0127d6d5c4b4f294facd9afe57a4e16824a5ae85c8cb2970430a4165569ea15b46b38881ca4b83495eb6995294dc2bf2ae69ad76f6fdf4a30b360e7c8c7881dc077a2a5dcd2dcbd2085888fcea13a97989346e8a7cf7aff72a50020c30ecaf2537b0fb70f19a9c1023f4b0e24f04411af88c861e6da9b01d422cf043b631ac86148a459f5"})
getpgrp(0x0)
2017/12/15 11:53:27 executing program 2:
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2000, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r0 = msgget$private(0x0, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair(0x1f, 0x80806, 0x3ff, &(0x7f00006be000)={<r1=>0x0, 0x0})
ioctl$DRM_IOCTL_AGP_ALLOC(0xffffffffffffff9c, 0xc0206434, &(0x7f000041f000-0x20)={0x480000, <r2=>0x0, 0x10001, 0x27764669})
ioctl$DRM_IOCTL_SG_ALLOC(r1, 0xc0106438, &(0x7f00008db000-0x10)={0x4, r2})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
msgctl$MSG_STAT(r0, 0xb, &(0x7f0000236000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
msgctl$MSG_STAT(r0, 0xb, &(0x7f00008a5000)="00000000000000000000000000000000")
r3 = openat$rfkill(0xffffffffffffff9c, &(0x7f0000a72000-0xc)="2f6465762f72666b696c6c00", 0x5, 0x0)
ioctl$RNDADDTOENTCNT(r3, 0x40045201, &(0x7f0000523000)=0x1fffd)
getsockopt$inet6_IPV6_IPSEC_POLICY(r3, 0x29, 0x22, &(0x7f0000c58000)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in=@multicast2=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in6=@remote={0x0, 0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0}, 0x0, 0x0}, 0x0, @in=@multicast2=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000c13000)=0xe8)
ioctl$LOOP_GET_STATUS(r3, 0x4c03, &(0x7f0000c8a000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", "0000000000000000000000000000000000000000000000000000000000000000", [0x0, 0x0], 0x0})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x8000000003, 0x32, 0xffffffffffffffff, 0x0)
r4 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x71, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r5 = epoll_create(0x10000000007)
accept$unix(r3, &(0x7f0000387000)=@abs={0x0, 0x0, 0x0}, &(0x7f0000900000-0x4)=0x8)
epoll_ctl$EPOLL_CTL_ADD(r5, 0x1, r4, &(0x7f00000f8000-0xc)={0x0, 0x0})
perf_event_open(&(0x7f000002f000-0x78)={0x1, 0x78, 0x0, 0x0, 0x0, 0x20000000000, 0x0, 0x0, 0x0, 0x0, 0x7fffffff, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
setsockopt$netlink_NETLINK_NO_ENOBUFS(r1, 0x10e, 0x5, &(0x7f0000997000-0x4)=0xfffffffffffffc00, 0x4)
ioctl$TIOCGSID(r3, 0x540f, &(0x7f00004ab000-0x4)=0x0)
setsockopt$bt_BT_POWER(0xffffffffffffffff, 0x112, 0x9, &(0x7f0000c8e000-0x1)=0x1000000000101002, 0x1)
socketpair$unix(0x1, 0x1, 0x0, &(0x7f0000658000)={<r6=>0xffffffffffffffff, <r7=>0xffffffffffffffff})
perf_event_open(&(0x7f0000001000-0x78)={0x5, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x2, 0x3, 0x20000000, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getpeername(r7, &(0x7f0000006000-0xc)=@nl={0x0, 0x0, 0x0, 0x0}, &(0x7f0000000000)=0xc)
ioctl$sock_SIOCETHTOOL(r6, 0x8946, &(0x7f0000002000-0x28)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, &(0x7f0000000000)=@ethtool_gfeatures={0x3a, 0x0, []}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
2017/12/15 11:53:27 executing program 4:
r0 = openat$selinux_load(0xffffffffffffff9c, &(0x7f0000ab5000)="2f73656c696e75782f6c6f616400", 0x2, 0x0)
ioctl$KVM_PPC_GET_PVINFO(r0, 0x4080aea1, &(0x7f00000ab000-0xd8)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
lgetxattr(&(0x7f0000e9b000)="2e2f66696c653000", &(0x7f0000000000)=@random={"747275737465642e00", "2f73656c696e75782f6c6f616400"}, &(0x7f0000001000-0xb4)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb4)
ftruncate(r0, 0x603)
ioctl$KVM_GET_MSRS(r0, 0xc008ae88, &(0x7f0000000000)={0x1, 0x0, [{0x0, 0x0, 0x0}]})
r1 = openat$selinux_avc_cache_stats(0xffffffffffffff9c, &(0x7f0000000000)="2f73656c696e75782f6176632f63616368655f737461747300", 0x0, 0x0)
ioctl$KVM_GET_DIRTY_LOG(r0, 0x4010ae42, &(0x7f0000001000-0x10)={0x1, 0x0, &(0x7f000092b000/0x4000)=nil})
ioctl$KVM_SET_GSI_ROUTING(r0, 0x4008ae6a, &(0x7f0000001000-0x1b8)={0x9, 0x0, [{0x7fff, 0x3, 0x0, 0x0, @adapter={0x2, 0x6, 0x5, 0xfffffff800000000, 0x1}}, {0x5, 0x4, 0x0, 0x0, @msi={0x8, 0x6, 0x800}}, {0x5, 0x0, 0x0, 0x0, @sint={0x6, 0x4}}, {0xfffffffffffffffc, 0x4, 0x0, 0x0, @sint={0x62, 0x1ff}}, {0x1f, 0x7, 0x0, 0x0, @msi={0x22, 0x3, 0x0}}, {0x3941ce7a, 0x4, 0x0, 0x0, @irqchip={0x1, 0x80000000}}, {0xa246, 0x7, 0x0, 0x0, @sint={0x3ff, 0xffffffffffff0001}}, {0x6, 0x3, 0x0, 0x0, @sint={0x4, 0xfffffffffffffe78}}, {0x7, 0x3, 0x0, 0x0, @msi={0x7ff, 0xffff, 0x5}}]})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$BINDER_WRITE_READ(r1, 0xc0306201, &(0x7f0000000000)={0x150, 0x0, &(0x7f0000001000-0x150)=[@decrefs={0x40046307, 0x3}, @dead_binder_done={0x40086310, 0x4}, @reply_sg={0x40486312, {{0x4, 0x0, 0x4, 0x0, 0x11, 0x0, 0x0, 0x58, 0x20, &(0x7f0000001000-0x58)=[@fd={0x66642a85, 0x0, r1, 0x0, 0x2}, @fda={0x66646185, 0x8, 0x4, 0x1c}, @fda={0x66646185, 0x9, 0x0, 0x0}], &(0x7f0000001000-0x20)=[0x20, 0x38, 0x0, 0x20]}, 0x100000001}}, @register_looper={0x630b}, @reply_sg={0x40486312, {{0x3, 0x0, 0x2, 0x0, 0x11, 0x0, 0x0, 0x18, 0x38, &(0x7f0000001000)=[@fd={0x66642a85, 0x0, r1, 0x0, 0x0}], &(0x7f0000002000-0x38)=[0x78, 0x38, 0x28, 0x18, 0x38, 0x78, 0x28]}, 0x967c}}, @dead_binder_done={0x40086310, 0x3}, @enter_looper={0x630c}, @transaction={0x40406300, {0x4, 0x0, 0x2, 0x0, 0x10, 0x0, 0x0, 0x0, 0x10, &(0x7f0000001000)=[], &(0x7f0000002000-0x10)=[0x28, 0x48]}}, @reply_sg={0x40486312, {{0x1, 0x0, 0x2, 0x0, 0x10, 0x0, 0x0, 0x68, 0x18, &(0x7f0000001000-0x68)=[@fda={0x66646185, 0x9, 0x2, 0x17}, @ptr={0x70742a85, 0x1, &(0x7f0000001000-0x1)=0x0, 0x1, 0x3, 0x2a}, @fda={0x66646185, 0x0, 0x2, 0x30}], &(0x7f0000001000-0x18)=[0x38, 0x38, 0x78]}, 0x1000000000}}], 0x7f, 0x0, &(0x7f0000000000)="24affc428252293eaaedce2acdc2423050aa6ccdf531ddb50b97b905f672aa39034b1023c2e1c771b825df37747efcd2a3b88e34eaeed68ecce6cb758e3a8fe4cf6cd45be5b22657f3ba0b98ec72d5ce14941f1335c2af019a97f8d5d04dcb4a3c9ea6f6a8f04305ab1e4b90b88a687053af1a2829c1de25aa44af19e63857"})
syz_kvm_setup_cpu$x86(r1, r1, &(0x7f0000bf9000/0x18000)=nil, &(0x7f0000000000)=[@text32={0x20, &(0x7f0000001000-0x6b)="0fc71c1c9a00180000460066baf80cb8e0587083ef66bafc0cb800000000ef2e0f2291c4e17b70ba0d00000000260f1cac40165f00000f01c8b805000000b9a1170cab0f01d9c744240087810000c7442402e5000000c7442406000000000f011424650fc7ac3ef9ffffff", 0x6b}], 0x1, 0x71, &(0x7f0000001000-0x20)=[@flags={0x3, 0x2}, @cr4={0x1, 0x24000}], 0x2)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bpf$MAP_LOOKUP_ELEM(0x1, &(0x7f0000002000-0x18)={r1, &(0x7f0000000000)="749a7a8c781ac4026a5b28cd010c175613e1281c70241b5fd4", &(0x7f0000003000-0x90)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x18)
getgid()
r2 = openat$selinux_avc_cache_stats(0xffffffffffffff9c, &(0x7f0000002000-0x19)="2f73656c696e75782f6176632f63616368655f737461747300", 0x0, 0x0)
inotify_add_watch(r0, &(0x7f0000002000)="2e2f66696c653000", 0x1000002)
bpf$MAP_DELETE_ELEM(0x3, &(0x7f0000001000)={r2, &(0x7f0000002000-0x13)="35a37f26f236bc5d6ffcf6fe29b2c0f49e044d"}, 0x10)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = openat$selinux_access(0xffffffffffffff9c, &(0x7f0000004000-0x10)="2f73656c696e75782f61636365737300", 0x2, 0x0)
setsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(r3, 0x84, 0x13, &(0x7f0000000000)=0x7fff, 0x4)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mq_notify(r0, &(0x7f0000002000)={0x0, 0x5, 0x0, @thr={&(0x7f0000005000-0x32)="45f18150c513856a18914160297312e8399248e796fd1f0af06dd80c63bc8153d40e7163957ad91617f1dc7fcd42e417c59f", &(0x7f0000003000-0xda)="16c7bf30730e3cad7610c3efff21f6719a9b88f0f736bedce0769cefa054ab3ff1d11c43876d0893fa86182d6fbd1142afb0939890ea3945cf4cb1f09abbde51f1450e1b1f096662bf3ad1fb5c14d519622bf697ec8d6b542c9d403e8e7c9bd257a867e4c244d3c3732d6845f99f1923c5a3af3fcb0fb8f1683668ed68036ccf3e51b84da34c4f700125dcc415785209b734843069ff24586560ed64efe23da77075fbfb567882d3ee3b3cc5a1e4fc6221acb0d493b4948ca3977ae53dfff890e335f7b5afbc7d6aea82bf9d7b0e22d90dd0b995c46fc23f0023"}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$DRM_IOCTL_AGP_RELEASE(r0, 0x6431)
ioctl$KVM_CREATE_VCPU(r3, 0xae41, 0x1)
syz_open_dev$vcsa(&(0x7f0000003000)="2f6465762f766373612300", 0x8000, 0xc40)
2017/12/15 11:53:27 executing program 5:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$packet(0x11, 0x3, 0x300)
ioctl$TIOCGSID(0xffffffffffffff9c, 0x540f, &(0x7f000035b000-0x4)=<r0=>0x0)
r1 = syz_open_procfs(r0, &(0x7f000031a000)="6e65742f7564703600")
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
preadv(r1, &(0x7f000069e000)=[{&(0x7f0000bae000-0xb3)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb3}, {&(0x7f0000cdc000)="000000000000000000000000000000000000", 0x12}, {&(0x7f000053f000-0x95)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x95}, {&(0x7f000031b000-0x48)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x48}, {&(0x7f0000941000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xf4}, {&(0x7f0000f5c000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x28}], 0x6, 0x400000000000)
fgetxattr(r1, &(0x7f00008f7000-0x15)=@known="73797374656d2e736f636b70726f746f6e616d6500", &(0x7f0000dbe000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe3)
recvmsg(r1, &(0x7f0000a3c000)={&(0x7f0000be7000)=@llc={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, @empty=[0x0, 0x0, 0x0, 0x0, 0x0, 0x0], [0x0, 0x0]}, 0x10, &(0x7f000026f000)=[{&(0x7f0000aca000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x94}, {&(0x7f00005f1000-0x9c)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9c}, {&(0x7f00003ca000)="00000000000000000000000000000000000000000000000000000000", 0x1c}, {&(0x7f0000399000-0xe7)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe7}, {&(0x7f0000e7c000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x44}], 0x5, 0x0, 0x0, 0x8}, 0x20)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = openat$vcs(0xffffffffffffff9c, &(0x7f0000aa7000-0x9)="2f6465762f76637300", 0x10040, 0x0)
write(r1, &(0x7f000088b000-0x5b)="6122bb079f0c5219ffd539aa47ad67a1f919c405bb48363beb6f070579b0b272655886dbe21c835377a19f1eccc7a1412b22bd8a3a97206565fb165dbd9488783b5b160628fd305243672dd6199aac9dc89e7cb3a3bca34fec1ddd9fcf044eff73d5b1d537f7e9f05de69bf6b3f964c476e756c870b67f3ecb534611d93bf3cbc53245436695b14a58fd8f7d9e2b557bfdae1d12b17c9b48230efc7a95c0bc120d6b400b0d02385502fc3df59a177a0e08dd58ec7ffe5cd65ff8b509f2", 0xbd)
connect$nfc_llcp(r2, &(0x7f0000a0b000-0x60)={0x27, 0x97, 0x3, 0x7, 0x3, 0xfff, "8545d548b828bc6fd8cd1e853d332510a8e158dfeaf569ce497bc50cdb774cc26f9a2721808e3be50db22530f08839be75562a9dfb2018081900f8b66812d1", 0x3}, 0x60)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = getpgrp(0x0)
setpriority(0x0, r3, 0x7b)
r4 = openat$kvm(0xffffffffffffff9c, &(0x7f0000c2c000-0x9)="2f6465762f6b766d00", 0x40402, 0x0)
r5 = ioctl$KVM_CREATE_VM(r4, 0xae01, 0x0)
r6 = ioctl$KVM_CREATE_VCPU(r5, 0xae41, 0x0)
ioctl$KVM_GET_MP_STATE(r6, 0x8004ae98, &(0x7f0000f93000)=0x0)
syz_kvm_setup_cpu$x86(r5, r6, &(0x7f0000960000/0x18000)=nil, &(0x7f0000239000-0x18)=[@textreal={0x8, &(0x7f000066a000-0x69)="2e64650fc78f6a2f0f008c09802e660f127d4666b95908000066b86048000066ba000000000f30baf80c66b8c07d0a8766efbafc0c66ed0fae2e76d6baf80c66b8ec880e8766efbafc0cb8f3fbef0f0926260f01cb66b92c08000066b80078000066ba000000000f30", 0x69}], 0x1, 0x4, &(0x7f0000158000)=[@dstype3={0x7, 0x1}, @cr4={0x1, 0x2000}], 0x2)
r7 = socket$kcm(0x29, 0x2, 0x0)
getsockopt$sock_cred(r7, 0x1, 0x11, &(0x7f0000259000)={0x0, 0x0, 0x0}, &(0x7f0000e3f000)=0xc)
syz_kvm_setup_cpu$x86(r5, r6, &(0x7f0000c36000/0x18000)=nil, &(0x7f0000574000)=[@text16={0x10, &(0x7f0000a03000-0x34)="66b80500000066b94a3000000f01c167880a26990f22420f38f19bff27ba210066edf264360f22172e0f350f01cbba4300b000ee", 0x34}], 0x1, 0xffffffffffffffff, &(0x7f0000dfd000)=[], 0x0)
r8 = openat$vga_arbiter(0xffffffffffffff9c, &(0x7f00007c6000-0x11)="2f6465762f7667615f6172626974657200", 0x4002, 0x0)
getsockopt$inet_sctp6_SCTP_PEER_AUTH_CHUNKS(r8, 0x84, 0x1a, &(0x7f00003d6000)={<r9=>0x0, 0x45, "94937848b391f6f93544aeba6b2f8bc09acb410bb323c364e096c341c593f6d96bd99ba3c94d789c1e095694c4edb23b2e24fa465d7b2bf6d6c27a41fccfa4a4505231a8e7"}, &(0x7f00005cf000-0x4)=0x4d)
getsockopt$inet_sctp_SCTP_SOCKOPT_CONNECTX3(0xffffffffffffffff, 0x84, 0x6f, &(0x7f0000c7b000)={r9, 0x54, &(0x7f0000235000)=[@in6={0xa, 0x0, 0x454b3bf9, @loopback={0x0, 0x1}, 0x5}, @in6={0xa, 0x3, 0x0, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x4}, @in6={0xa, 0x1, 0x100000000, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x9}]}, &(0x7f00004e9000)=0x10)
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r8, 0x84, 0x18, &(0x7f0000d5b000-0x6)={<r10=>r9, 0x4}, &(0x7f00001fb000-0x4)=0x6)
fcntl$setflags(r8, 0x2, 0xffffffffffffffff)
accept$inet(r4, &(0x7f000023d000)={0x0, 0x0, @broadcast=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000676000+0x96e)=0x10)
getsockopt$inet_sctp_SCTP_DEFAULT_PRINFO(r8, 0x84, 0x72, &(0x7f000061b000)={r10, 0x2, 0x30}, &(0x7f00003f5000)=0xc)
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
openat$kvm(0xffffffffffffff9c, &(0x7f00002ea000-0x9)="2f6465762f6b766d00", 0x1000000000000, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
socket$inet6(0xa, 0x8000000000003, 0x100000004)
ioctl$sock_SIOCGPGRP(0xffffffffffffff9c, 0x8904, &(0x7f00005f8000)=<r0=>0x0)
r1 = syz_open_dev$vcsn(&(0x7f0000e44000)="2f6465762f7663732300", 0x100000000, 0x80000)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x400, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2000000000, 0x0, 0x0, 0x0, 0x0, 0x0}, r0, 0x0, r1, 0x8)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x8, 0x8000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x20000, 0x0, 0x0, 0x0, 0x0, 0xff, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x0, 0x78, 0xdb, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0xfe, 0x2, 0x0, 0x0, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
socket$netlink(0x10, 0x3, 0x8)
accept(0xffffffffffffffff, &(0x7f00009e3000)=@nl={0x0, 0x0, 0x0, 0x0}, &(0x7f00001d7000)=0xc)
r2 = syz_open_dev$tun(&(0x7f0000e26000-0xd)="2f6465762f6e65742f74756e00", 0x0, 0x20000)
ioctl$TUNSETIFINDEX(r2, 0x400454da, &(0x7f0000410000-0x4)=0x101)
r3 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$inet_tcp_int(r3, 0x6, 0x0, &(0x7f0000188000)=0x0, 0x4)
set_robust_list(&(0x7f00004a0000)={&(0x7f0000f95000/0x1000)=nil, 0x89, &(0x7f0000036000/0x4000)=nil}, 0x18)
r4 = fcntl$getown(r1, 0x9)
syz_open_dev$tun(&(0x7f0000c48000)="2f6465762f6e65742f74756e00", 0x0, 0x101003)
clone(0x0, &(0x7f0000107000-0x37)="", &(0x7f0000a9e000-0x4)=0x0, &(0x7f0000362000)=0x0, &(0x7f0000f2b000)="")
mprotect(&(0x7f0000a03000/0x1000)=nil, 0x1000, 0x0)
perf_event_open(&(0x7f0000940000)={0x0, 0x78, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r4, 0x0, 0xffffffffffffffff, 0x0)
mkdir(&(0x7f0000632000)="2e2f66696c653000", 0x8)
mount(&(0x7f0000528000-0x8)="2e2f66696c653000", &(0x7f0000a17000+0x964)="2e2f66696c653000", &(0x7f0000014000)="70726f6300", 0x0, &(0x7f0000fc9000)="")
r5 = open(&(0x7f0000304000-0x8)="2e2f66696c653000", 0x161400, 0xc)
mount(&(0x7f0000d0c000)="2e2f66696c653000", &(0x7f0000c78000-0x8)="2e2f66696c653000", &(0x7f0000ec2000)="72616d667300", 0x800, &(0x7f000002d000)="")
getdents(r5, &(0x7f0000ae3000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe0)
getdents64(r5, &(0x7f0000505000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6c0)
wait4(0x0, &(0x7f00001f5000)=0x0, 0x8, &(0x7f0000561000-0x90)={{0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
2017/12/15 11:53:27 executing program 4:
r0 = socket$inet6_icmp(0xa, 0x2, 0x3a)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
set_mempolicy(0x1, &(0x7f00000de000)=0x0, 0x7f)
r1 = socket$inet_tcp(0x2, 0x1, 0x0)
mmap(&(0x7f0000000000/0xef3000)=nil, 0xef3000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = socket$inet_tcp(0x2, 0x1, 0x0)
setsockopt$inet_buf(r2, 0x0, 0x10, &(0x7f00003d3000-0x20)="02000000020001000000be8c5ee18c0000000681d429438b567a627a21bf328c", 0x20)
setsockopt$inet_buf(r1, 0x0, 0x10, &(0x7f0000ef1000)="18000000020001000000be8c5eff8c88360000f1010300ec0000000000040000f7b933d898055bf748bb6a8807567e59dba67e1947b3550400000067a1e2010067fc2163e000000000000453ff1f00000000000000c88ebbff060100000b01000000b121ad1474d722f542002700ec008b00cf000000047ee87ccc000000080000c50fff04e9e9f57406aa01100b0004000000cc08000020ffe3c5452c1adb8a335bd8b2d17fffa21b571068395533b5affa00041ad0b4c2c23eef679567fcda", 0xc0)
r3 = accept4(r2, &(0x7f0000ab2000)=@alg={0x0, "0000000000000000000000000000", 0x0, 0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f0000685000)=0x58, 0x80800)
fcntl$getownex(r3, 0x10, &(0x7f0000e2e000-0x8)={0x0, <r4=>0x0})
getpriority(0x3, r4)
r5 = dup2(r1, r2)
ioctl$VT_WAITACTIVE(r5, 0x5607)
setsockopt$inet_tcp_int(r1, 0x6, 0x15, &(0x7f0000b7e000-0x4)=0x5, 0x4)
mmap(&(0x7f0000ef3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$sock_inet_SIOCDARP(r5, 0x8953, &(0x7f0000ef3000)={{0x2, 0x0, @broadcast=0xffffffff, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x0, @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x8, {0x2, 0x0, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @syzn={0x73, 0x79, 0x7a, 0x0, 0x0}})
socket$inet_sctp(0x2, 0x5, 0x84)
r6 = getpid()
fcntl$setownex(r0, 0xf, &(0x7f0000a7b000)={0x1, r6})
openat(0xffffffffffffffff, &(0x7f0000927000)="2e2f66696c653000", 0xfffffffffffffffc, 0x110)
ptrace(0xffffffffffffffff, r4)
mmap(&(0x7f0000000000/0xec2000)=nil, 0xec2000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r7 = socket$netlink(0x10, 0x3, 0xfffffffffffffffd)
writev(r7, &(0x7f0000a65000)=[{&(0x7f00009dc000-0x3b)="39000000100009a1690000007fffffeb1800000d000000000006010700004f1419001b000000ea0000000022000000000000011c00621e0500709d", 0x3b}], 0x1)
mmap(&(0x7f0000ec3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$inet(0x2, 0x805, 0x1)
msync(&(0x7f0000952000/0x2000)=nil, 0x87abbe8d1cc6ad9, 0x4)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
2017/12/15 11:53:27 executing program 0:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$inet6_sctp(0xa, 0x0, 0x84, &(0x7f00000ff000)={<r0=>0x0, 0x0})
getsockopt$inet_sctp6_SCTP_NODELAY(r0, 0x84, 0x3, &(0x7f0000ceb000)=0x0, &(0x7f0000404000)=0x4)
r1 = socket(0x17, 0x5, 0x6)
ioctl$sock_inet6_udp_SIOCOUTQ(r1, 0x5411, &(0x7f000055e000)=0x0)
bpf$PROG_LOAD(0x5, &(0x7f0000ee7000-0x30)={0x1, 0x1, &(0x7f0000ee7000-0x10)=[@generic={0x0, 0x0, 0xa7, 0x0}], &(0x7f000000a000)="87797374656d00", 0xffffff7ffffffff9, 0x80, &(0x7f000000a000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x0, 0x0}, 0x30)
mmap(&(0x7f0000000000/0xf73000)=nil, 0xf73000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socket$alg(0x26, 0x5, 0x0)
close(r0)
r2 = socket$alg(0x26, 0x5, 0x0)
setsockopt$ALG_SET_AEAD_AUTHSIZE(r2, 0x117, 0x5, 0x0, 0x0)
r3 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r3, &(0x7f0000bc5000)={0x26, "736b636970686572000000000000", 0x0, 0x800, "7874732d73657270656e742d61767800000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, 0x58)
setsockopt$inet_tcp_TCP_REPAIR_OPTIONS(0xffffffffffffffff, 0x6, 0x16, &(0x7f000033f000-0x48)=[{0x2, 0x2a88}, {0x2, 0xa75}, {0xa, 0x71}, {0x0, 0x8}, {0x8, 0x8000}, {0x7, 0x3}, {0xb, 0x1ff}, {0x3, 0x7}, {0xb, 0xfff}], 0x9)
setsockopt$ALG_SET_KEY(r3, 0x117, 0x1, &(0x7f0000647000-0x20)="0a0775b0d5e383e5b3b60ced5c54dbb7295df0df8217ad4000000000000000e6", 0x20)
r4 = accept$alg(r3, 0x0, 0x0)
close(r3)
recvmsg(r3, &(0x7f0000f11000-0x38)={0x0, 0x0, &(0x7f00001db000-0x80)=[{&(0x7f0000f70000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xbd}, {&(0x7f0000dc0000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe8}, {&(0x7f0000f71000-0x1000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1000}, {&(0x7f0000a33000-0xaf)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xaf}, {&(0x7f000081f000-0x7e)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x7e}, {&(0x7f0000f70000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6d}, {&(0x7f000020d000-0xe1)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xe1}, {&(0x7f0000030000-0xfe)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xfe}], 0x8, &(0x7f00001d3000)="0000000000000000000000000000000000000000", 0x14, 0x3}, 0x3d5a1db4cedf06e6)
mmap(&(0x7f0000f73000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f74000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f75000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
recvmsg(r4, &(0x7f000022f000-0x38)={&(0x7f0000f6f000-0x10)=@ethernet={0x0, @random="000000000000", [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000893000-0x50)=[{&(0x7f0000e72000-0x84)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x84}, {&(0x7f0000f6f000-0x79)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x79}, {&(0x7f0000f73000-0xd5)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xd5}, {&(0x7f0000e69000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xb0}, {&(0x7f0000f6e000)="000000000000000000000000", 0xc}], 0x5, &(0x7f00008ae000-0x46)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x46, 0x8}, 0x2)
2017/12/15 11:53:27 executing program 3:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$netlink(0x10, 0x3, 0x0)
setsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX(0xffffffffffffffff, 0x84, 0x6e, &(0x7f0000439000-0x1c)=[@in6={0xa, 0x2, 0x7fffffff, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0}], 0x1c)
r1 = syz_open_dev$vcsa(&(0x7f0000923000-0xb)="2f6465762f766373612300", 0x8, 0xc2)
getsockopt$inet_mreqn(r1, 0x0, 0x27, &(0x7f0000091000)={@loopback=0x0, @local={0x0, 0x0, 0x0, 0x0}, <r2=>0x0}, &(0x7f00007df000)=0xc)
ioctl$sock_SIOCGIFINDEX(r1, 0x8933, &(0x7f00007b6000-0x28)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, <r3=>r2, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
bind$packet(r1, &(0x7f0000277000)={0x11, 0x10, r3, 0x1, 0x5, 0x6, @random="ecd398ef135b", [0x0, 0x0]}, 0x14)
ioctl$DRM_IOCTL_RES_CTX(r1, 0xc0106426, &(0x7f000023d000-0x10)={0x7, &(0x7f0000e59000)=[{0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {<r4=>0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}, {0x0, 0x0}]})
ioctl$DRM_IOCTL_LOCK(r1, 0x4008642a, &(0x7f0000566000-0x8)={r4, 0x209})
socketpair$inet_dccp(0x2, 0x6, 0x0, &(0x7f00001ce000)={<r5=>0x0, <r6=>0x0})
ioctl$KVM_CREATE_DEVICE(r1, 0xc00caee0, &(0x7f000023e000-0xc)={0x0, <r7=>r6, 0x0})
bind$bt_l2cap(r1, &(0x7f0000c47000)={0x1f, 0x0, {0xfffffffffffffffb, 0x5, 0x9ca, 0x8, 0x4, 0x18}, 0x6, 0x2}, 0xe)
ioctl$LOOP_CHANGE_FD(r7, 0x4c00, r6)
setsockopt$inet6_MCAST_JOIN_GROUP(r7, 0x29, 0x2a, &(0x7f0000ce1000-0x88)={0x2, {{0xa, 0x1, 0x76c5b4af, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x88)
ioctl$TCSBRK(r1, 0x5409, 0x100000003)
ioctl$sock_SIOCOUTQNSD(r6, 0x894b, &(0x7f0000ed1000-0x4)=0x0)
setsockopt(r5, 0xb6, 0x49, &(0x7f0000636000-0xbd)="292e4a0a4e9600a15e02ec5f269e4b4d3ccac7f7f3d832fc60ef297e150e2c8062bf01cb5007cc3a0d6698c02713a0a32f76087988870003adb2cc88caa160379d9f5d196acaaefc4d1189a23cae9d4103b7c1871b6c10784af2f25d5215263a313c6b8d7d5b7b508c4aea89c02bfb5f2bdc5a839a899d8618c9f073292d61bd7f02ce1709962988115b1e0a340904fc3e584d92563ecd4f7094f9177f1874b8bcd29d2b9dc770769d3dd5d2660576a09f8b33729acb9fee02c5ec3884", 0xbd)
getsockopt$sock_cred(r5, 0x1, 0x11, &(0x7f000003d000-0xc)={0x0, 0x0, 0x0}, &(0x7f0000863000)=0xc)
r8 = signalfd4(r5, &(0x7f0000fe9000)={0xffffffff}, 0x8, 0x80000)
openat$selinux_enforce(0xffffffffffffff9c, &(0x7f00007ed000-0x11)="2f73656c696e75782f656e666f72636500", 0x2000, 0x0)
fsync(r8)
readv(r8, &(0x7f000006f000-0x10)=[{&(0x7f00007c1000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x80}], 0x1)
r9 = open(&(0x7f00009b1000-0x8)="2e2f66696c653000", 0x0, 0x4)
unshare(0x400)
r10 = signalfd4(r8, &(0x7f0000a9c000-0x8)={0x4}, 0x8, 0x80000)
ioctl$KVM_SET_CLOCK(r9, 0x4030ae7b, &(0x7f0000502000+0xb47)={0x9, 0x5, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
socket(0x0, 0xa, 0x10000)
signalfd(r10, &(0x7f0000519000-0x8)={0xffffdffc}, 0x8)
writev(r0, &(0x7f0000d27000-0x10)=[{&(0x7f00005c0000)="290000001800fffd3ffdff00000a05210200e3330008000700feff55080008000000020000e900c000", 0x29}], 0x1)
2017/12/15 11:53:27 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x3e2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
gettid()
r0 = gettid()
r1 = syz_open_procfs(r0, &(0x7f0000f47000)="6eb15ecf30706300c7a48effe0e446e43c4e25c993d4dc523e3d6f0e461dcd2470aa641be0ad2e883d770d2ab834324878dc12ee874489ee3406595b344914efaf890a984ebb9771445c58eb13a261b7166447a37e")
r2 = openat(r1, &(0x7f00009f2000)="2e2f66696c653000", 0x43, 0x80000)
ioctl$SNDRV_SEQ_IOCTL_SET_QUEUE_CLIENT(r2, 0x404c534a, &(0x7f00004cb000-0x4c)={0xa7, 0x6, 0x1, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
perf_event_open(&(0x7f0000fee000)={0x6, 0x78, 0x0, 0x0, 0x2, 0xfffffffffffffffd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x400000a00000002, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
ioctl$EVIOCGREP(r1, 0x80084503, &(0x7f0000f9b000-0xe1)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")
ioctl$KVM_GET_REGS(r2, 0x8090ae81, &(0x7f0000733000-0x90)={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0x0})
semget(0x3, 0x2, 0x1000000000000002)
mount(&(0x7f0000144000)="2e2f66696c653000", &(0x7f00009f7000-0x8)="2e2f66696c653000", &(0x7f000057c000-0x4)="6e667300", 0x0, &(0x7f000000a000)="")
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat(0xffffffffffffffff, &(0x7f000079d000)="2e2f66696c653000", 0x200100, 0x10)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x800, 0x0, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x9, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x4, 0x2, 0x0, 0x0, 0x3, 0x3, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, r0, 0x0)
r1 = memfd_create(&(0x7f0000151000-0x2)="e681", 0xfffffffffffffffd)
pipe(&(0x7f00002b7000-0x8)={<r2=>0xffffffffffffffff, 0xffffffffffffffff})
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9448, 0x0, 0x0, 0x10000, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r3 = perf_event_open(&(0x7f00008a8000-0x78)={0x4000000002, 0x78, 0xdc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfc, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r4 = socket(0x4000000000000011, 0x8000000000000803, 0xfffffffffffffffe)
fremovexattr(r3, &(0x7f0000a06000)=@known="73797374656d2e61647669736500")
r5 = openat$rtc(0xffffffffffffff9c, &(0x7f0000807000-0x9)="2f6465762f72746300", 0x200, 0x0)
ioctl$sock_FIOGETOWN(r5, 0x8903, &(0x7f0000e51000-0x4)=<r6=>0x0)
gettid()
bind(r4, &(0x7f0000fe1000-0x80)=@generic={0x11, "0000030000000000080044944eeba71a4976e252922cb18f6e2e3aba000000012e0b3836005404b0e0301a4ce875f2e3de4d163ee340b76795dae5786a12374bea0101b8255802039e15775027ecce66fd792bbf0e5bf5ff1b0816f3f6db1cb8150169585daf476e49740000000000000006ad8e5ecc326d3a09ffc2c654"}, 0x80)
msgget$private(0x0, 0x220)
sched_setattr(r6, &(0x7f0000c46000-0x30)={0x30, 0x2, 0x1, 0x80, 0x0, 0x5, 0xfffffffffffffeff, 0x8}, 0x0)
r7 = socket$inet6(0xa, 0x20000000000005, 0x9)
ioctl$sock_inet_SIOCSIFFLAGS(r7, 0x8914, &(0x7f00007e2000)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_addrs={0x2, 0x1, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
ioctl$sock_inet_SIOCSIFFLAGS(r1, 0x8914, &(0x7f00008bf000-0x20)={@syzn={0x73, 0x79, 0x7a, 0x0, 0x0}, @ifru_addrs={0x2, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}})
socketpair$unix(0x1, 0x10000000002001, 0x0, &(0x7f0000a68000)={0xffffffffffffffff, <r8=>0xffffffffffffffff})
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdf, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
ioprio_get$pid(0x3, 0x0)
mkdir(&(0x7f0000baa000-0x8)="2e2f66696c653000", 0x0)
pivot_root(&(0x7f00008f5000-0x8)="2e2f66696c653000", &(0x7f0000ff6000)="2e2f66696c65302f66696c653000")
setsockopt$inet_sctp_SCTP_DISABLE_FRAGMENTS(r2, 0x84, 0x8, &(0x7f00001d1000)=0xf20, 0x4)
mount(&(0x7f0000061000)="2e2f66696c653000", &(0x7f000094b000)="2e2f66696c653000", &(0x7f0000060000-0x6)="6632667300", 0x4004, &(0x7f000088b000-0x1)="7e")
connect$unix(r8, &(0x7f0000896000-0xa)=@abs={0x1, 0x0, 0x3}, 0x8)
keyctl$revoke(0x3, 0xfffffffffffffffe)
r9 = syz_open_dev$vcsa(&(0x7f0000e98000)="2f6465762f766373612300", 0x3, 0x1)
getsockname$unix(r9, &(0x7f0000ee4000-0x57)=@file={0x0, "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f0000773000)=0x57)
sendmmsg$alg(r4, &(0x7f0000c2f000)=[{0x0, 0x0, &(0x7f0000e17000)=[{&(0x7f0000e34000)="aa811dc5c0d28cf367b60bd95c195a09b8c382195ddd612c1708aac12e2b22734a08a1e39173012acc9aa66ef60491e5da40162000d55a3d154b159ff677be0a2ebc661edfd8234424781eeb281200fc388b618981c7c4870bad633a01aad04dcf14c36fd817fbfcd1634204e63fae4b91e01cafd5445893441a86fcf85b91b9ed3efc5557ddd6f471e5aca5a87db2be85a3af65e87a67934ee960e5cd2ad3343ec389e7715b755cf5e5d418abca7e5d90835618123fc1cbc6dfea10e46e0578f295cf4e1ec7d704f7cd023432d68d9747e37e43417d60717fc8956813ccd62486a01f429fe2", 0xe6}], 0x1, &(0x7f0000c03000-0x30)=[@op={0x18, 0x117, 0x3, 0x7c}, @op={0x18, 0x117, 0x3, 0x2}], 0x30, 0x10}, {0x0, 0x0, &(0x7f0000f91000-0x40)=[{&(0x7f0000cf2000-0xb)="86c93edddcc97e9ab07d1c", 0xb}, {&(0x7f0000899000)="", 0x0}, {&(0x7f000026b000-0xbd)="a0680e12a13734fe2bf3e081c7d93440ff26bf155d6bebb738c02e1f0e5ac132933345e17c62170c955346215d61854f31cb26e316f09699c867136d500ad79bb600d5ba65d4f535525f3151f2dafcc4e52a5300d2622b174228b7f84da9622397ec14515b36ca3c963dfd0bcf1bb87109b4404c63f942b459c730b27acbf2f521de448a103a034f2a6911ef5a82b2555dd5d5afc63633c24187c649a25e03f7e7fe78cf722fde8fdf5e74e8e5dc7cf4ed387ef2a2d4ab7415cfbccf2f", 0xbd}, {&(0x7f0000017000)="45cc39afeba5d2d10935eec6c2c5a326b1c12815d0731d0acf5a03446dea6e45f15aa85ca1e5f3297c829e144cf5277b4dd21a1f657a0c11b7b07237e7ce9c1919d1ea02956ab70a19c9940614dcdf8fbd41d6ebc99d05cb5b49391aa543f432e344f2633979c664959dc4182790c44ab55a0aceb37b00dea0df35300573c64d5ef569d7401be62dd440ddfe3e51c1d932d4bfddadf9d4788e2f530713cd8fec812cf5d5751fe40b496c4fd32fbd3d5b0a56ec1ba57dad5efee12a58", 0xbc}], 0x4, &(0x7f000043c000-0x1a0)=[@iv={0xd8, 0x117, 0x2, 0xc0, "e50f8b9e0f176d3fc96c9c10373cda8bf292b71f0abd02c10fd65a968402d704f69e619e5ad55a2a035e0e217a7070fc0e492c3e6fc00e7334774d348e98b3122413ac05df873fc16664c27ef8358e5437b9839d8115ac2589f3db945d5493fc047b2bd0603952be87f0bcd805ed253b0b3cbb4469da2ce03860bbd79211fb4a5a307f88772eb5d1d14bef5e814978e8fb4c96290586dd7147a38917fb716abd486b3e91f3232aacfb89b66eac7eef408aecadb6a3d83db2836c850bdb93bf01"}, @iv={0x98, 0x117, 0x2, 0x7e, "bcfeaf9f234469277187f4861c8c29a4249b9ea660d37b6908bd08a1d9553f67639406398da449ed17ac0d364d0319a32d816762031fd76d6df9b1f8c3cebc5f67798a9ae30369275abbccd9852d351a6339c51743fa2e419146899b0cdce46db3e3efe855c2e23885adc72b8efd4448c4c1f2c16f7b5e95d95d11ad6d08"}, @assoc={0x18, 0x117, 0x4, 0x401}, @assoc={0x18, 0x117, 0x4, 0x100000000}], 0x1a0, 0x8000}, {0x0, 0x0, &(0x7f0000162000)=[{&(0x7f000099e000-0x83)="4b769fc5ce229ea044923c35f2dfea81d5502a0f579edb5946a7da2ec74738ca8ef9209b67e54b9924f11838385613aad3db34674ca8e1b719891b95e28cef71169e849f4a271b49f2313a5deccb2a032309cc9fe76e8f748da26e82fede91709e5631120f917119bd0d8ac2039900b8ff5586a571569fd0b97a8fb6a3cd4cb83c1553", 0x83}, {&(0x7f0000ace000)="55bdaa39777d361d145255d25a0d6d359f788208d7fb6c70e93b515126d49ae2a1debb55112bacb879e23b2174b1d764aef1906cec50", 0x36}, {&(0x7f0000378000-0xfe)="9bd7b306596d1318a28b87f176ceed1e3f3f5e149a0b3875c6b17ed4d7eed70efbcdab36d769931cf37f301c7ad24bb17fdbbf0c6be907bdb46b98c88583ba750159a744f3513deeb7693f2ef0e787d702a8ad9133fbb146f3f4a0f9582fe6ae122ea3d2f8a845350321713b299c1a9b0bd8e259e3512f87f847ca4821200fc2ff00ba06cbc68ffa1c224d55d6d81c7cd5d97c530375cebc7299f1b3f7fe9d29f37b6b94f0b872cebc519d18615a2f37ff34cd7c557951f39c2f7a3918bb2d19b76ca0fa01380207e4589e1e042c74d57380dba7ddcd7ec33116e8c4daa72c4ec73c1855d873306ca53383f7f52657e8cf41665f869058819492c4af183e", 0xfe}], 0x3, &(0x7f0000fd4000-0x18)=[@assoc={0x18, 0x117, 0x4, 0x6}], 0x18, 0x20004810}, {0x0, 0x0, &(0x7f0000821000-0x20)=[{&(0x7f0000fcb000)="eb5a6de0d6ab27e119b454026fcc7bff3e231dc506841c321aaf507b97148356824ff4e7404562779e8dc8ca5081484e4e9b32adde7642dbded57a0db477b4ceac395d3179ce609eb5", 0x49}, {&(0x7f00004a3000-0x95)="35dc4a63db91b594763dbda017416c0728c491ed9abf7678adb945ea374737de016e958be192b0f8aa5fe37fa6aa668afb81a598cc759eea9f737ac0e53fabc19b5d1ac603210ef5c8cfd5b23bcbe63a16f51b2b1282f5971c4bcdf26e6db1894ab0d94d144d227ac19824ba841ccde493d4cab5bc88cbbffc8fcacdd9182a6b8e5b1a0bcda64614bd56b1a5f846f62f4b36a3214d", 0x95}], 0x2, &(0x7f0000d70000-0xe0)=[@assoc={0x18, 0x117, 0x4, 0x2}, @op={0x18, 0x117, 0x3, 0xfffffffffffffa96}, @assoc={0x18, 0x117, 0x4, 0x6}, @iv={0x68, 0x117, 0x2, 0x4d, "aaa493714d9fb22994eda8cc253480096fbf35a906354e4e53cc8477a3776baf0d591657aaf0ccfd512f37ec26af033bc8d62362b9144e033cba5abd6d9836909406ac794ef5e238438d255702"}, @op={0x18, 0x117, 0x3, 0x130}, @op={0x18, 0x117, 0x3, 0x4}], 0xe0, 0x0}, {0x0, 0x0, &(0x7f00006aa000)=[{&(0x7f0000e45000-0x9f)="b1622274940aaa5d608658e10bc0e570f5536cc5b0d33e05eb4a99371b0e9c07b25251a4d7d0e3981df33ab09680534ca1934d05adbc97859fb63c5673f6ead021246ca1ce5a8101ea5c873045c82d1d006ffea5b0449df5aad015f8fb6d230f227a7c9ff0811317e907e02aa08ed805a09978e2cd42a8d59c047f0e110a6bd0398f28eaa25d6b15b280e84f047b7c5d399a48bdaf9cbe04ef8a95cd648032", 0x9f}, {&(0x7f0000d3f000-0xb3)="68f88b7e675caac8791f7a06f2284790f613b1d9e30ef85ab09c0dfce51e8a26c184392aaa266e60d66441e5981150538ea9b0cb7fea5e1c794c95f343309043e6a6aa9ac87e2d86fafe609f9a42341135d53cdca0ed962d03def5789a267306520579917485d8cee75737bce37dd1c50fa1bfe0b608a7d5f3002bd36df2fa8e7b24c04e3a983569c8ed124a8d30271fe5855b4deba0740dc8f921ad3f48d87a4e6b2cbb7b009f3205ac7f465ee10cb90fc788", 0xb3}, {&(0x7f00006b9000-0x4)="3ea6cbba", 0x4}, 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"3fae442f267ab277dc29fe7c9f8471079f60e405f50d2df8ca3a4ebff553662b611dd5f0268b8d183604d641b8ed960492804253f72dfff719e8b16c305b714f7316b612c037a0bcd91907247ae2f2a72d1afb0d40482786555557b3562e396c05a2f20a397719c10137999a37ab30b60e88a78a50e05ab69bb638f69a95357fb1a837f428a3c5ad2e5abdb9147b436f694855268ed2ed654f6f0dae147d66636e1ecec63b143fa5b9d3ff"}], 0x298, 0x40000}, {0x0, 0x0, &(0x7f000052e000)=[{&(0x7f00003ff000)="c628", 0x2}, {&(0x7f0000761000)="301efdd983fc3518bdc63ae7dcc51c9d0bff8e8fd9879b7d96ba7e4b24a9eebbe5fae6d3e54ea627acec3bc6d2aa824a3a9013d776f670b85eb7d80da862a80277e4647c317b1d33e1902f5946ef0f11d8e6f079f848040cc223cf026f6b0989cdedd52a7d2ed4d081d2078454ea7b3bff5e3ad962416e605e310490b32fca99e422d59130295ad6284e632932c6ca7d89c1b9a5035b40792e9694a9d273ac5aac576cd29961cd25ed319f5049c49ca464032bad03f29fc16878089bf58fbd0ac1ff633cef1ece28fa61915639c818035b7e0da25a80cf726cee83b7d11b2bc794e3549118cc76a18d63c7520dc972f6ffc9b658aac1e3ee2acce9708a", 0xfd}, {&(0x7f0000856000)="10e695f6081f98f8a30bd427c62dccbb560ca9d64e0bd2c29ec9358aea1b7b03a0036258df005a6d7e167b287afaeff6d400c20ca98543bcfc50799484be4ba541052592a71f97a68685f144c40f5fcdde6de24fb69d49fd781f22659d91e94597c9", 0x62}, {&(0x7f0000aef000)="beac3ee79d4c82eb3f455e7641769958df165a952e6af906b7a6adb052d2a19b8c42badc2b6d6a4a70be8289b803f979b1ab814a79d0e2dfc48f65e5b2a070a0a8480b86fb7229fa31c87472f945d31bfb5e981b84135b99b869570e21c890e7f40621d2fa65fec3af9567cf706122202861896f21798434b7ef5d157137e133a48f4090eb22504176d5fbbf33c884e1d58a4ea86320254c2e03235d4cb3ee27a2e5ab71c28655c91e93c6f41d9d9270785359a68a5fbdc861f0d5be520d423376874cf89047a430f7470f6c", 0xcc}, {&(0x7f0000984000-0x2d)="5be366eb35280f6c5d386fe1da70c157fba20a4c946b51a3b0e33d3451a9e5bf4e567de742f42d5da662691868", 0x2d}, {&(0x7f0000bb5000-0xe4)="3f02a99077d570510ec2b3b84b09d0e7d559327cd2122aad1c69238694a6e8051779a589198e1da4210a31587399eb1d852de54eaeeceffea6ece58aa80af1705a8aa8c8cf3e87ade9be63936fabb8768f853f17cf5b46a247cac6a5237fb28396bf12bad392cc997d8126c1eb84b9509c934a219841c5912a4689708351944f399e0345ed5df3b955ea6678c74e61b33d45cfa7ae496e5d8d58b6b58126d3124407852978db0616fd0e1b67303dda3a2ecc48542c5a82e4c34698f302cf8c22be8ebb3cd5034b568dc47a31b72e59672457dc8784885fdce34b3b69577f68acd8e135f2", 0xe4}, {&(0x7f000071c000)="053cabc88690c5dd07ce628945da4554e9a189ca227d44150eb0846a5038b8243a36024d1adfce5b7eac307a37c9300f1d20376185f861d0482951d2d53757a2acdf83e41f7c89d6c44bcb1fb4af4b40a1d8def98b2fe1948db22d1ccf3eb54335e203c82d570deb74ee6099b0cccae88b223fae9256c311717e5c2ed18818e022a5bc7e15e1ee90c5ca6181431f6c1e1cb204a661e5be06debadf1aca7e9523bf3a1c059b0d201b7ec7d55342a559c68b0ec0d3d45d25673f007022bb68a26074b113194158259fa03e93cfea27de8d", 0xd0}, {&(0x7f0000738000)="d4a02c8ff8ea9429f346e566c0558b3e", 0x10}], 0x8, &(0x7f00006ed000-0x48)=[@op={0x18, 0x117, 0x3, 0x5}, @op={0x18, 0x117, 0x3, 0x5}, @assoc={0x18, 0x117, 0x4, 0x55}], 0x48, 0x0}], 0x6, 0x40)
mkdirat(0xffffffffffffffff, &(0x7f0000050000+0x545)="2e2f66696c653000", 0x4)
setsockopt$netlink_NETLINK_CAP_ACK(r2, 0x10e, 0xa, &(0x7f0000023000-0x4)=0x5, 0x4)
2017/12/15 11:53:27 executing program 7:
mmap(&(0x7f0000000000/0xfde000)=nil, 0xfde000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xf69000)=nil, 0xf69000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x2, 0x0)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x3, 0x32, r0, 0x0)
setsockopt$inet6_mtu(r0, 0x29, 0x17, &(0x7f00000a9000)=0x2, 0x4)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$SO_TIMESTAMPING(r0, 0x1, 0x25, &(0x7f000091f000-0x4)=0x8, 0x4)
setsockopt$inet6_int(r0, 0x29, 0x43, &(0x7f0000d61000-0x4)=0x6, 0x4)
mmap(&(0x7f0000fde000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_int(r0, 0x29, 0x19, &(0x7f0000fdf000-0x4)=0x2, 0x4)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$DRM_IOCTL_VERSION(0xffffffffffffffff, 0xc0406400, &(0x7f00004d2000)={0x4, 0xffffffff, 0x5, 0x6e, &(0x7f0000f69000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x1000, &(0x7f0000f6a000-0x1000)="000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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0x0, &(0x7f0000683000)=""})
sendto$inet6(r0, &(0x7f00001ea000)="", 0x0, 0x0, &(0x7f0000f5b000-0x1c)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x0}, 0x1c)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fe0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
sendto$inet6(r0, &(0x7f0000fe1000-0x59a)="d6cdddf6785b2010c70c0e53a7b8dc46fb08eb86a063c48af64531b6d0b5e54fc637a8ce449a0b9e9bc58337badcb8b328730000000000000000d5af77d601c926a964d38709a01500c77d7f1db3dec18d2d3622d251666f5ee4723301548b798edf884d4ec51c76d0cc08d1a40051c9123b925e030e86296d2f292c596ebcd8548189ed3217ad11850252b4bf8d3586df05325e80ef836926eb2206588aa95d0374723daf2a574b8cbc080db80b5bb82cfda253f60f52303155726f41ed8eb9e8926f5e2471eefa9f20bb87c97f8ca5d5ab2fe8e7b33258064b19f1fce68e2bd76173823280dde3ff0bdd43965a3224c4888751d958dbda5412d855c3104a56fc2dd2756cec6488513f1c72fc760e90cbbaeb031ce7e3969a1d7d941520e47963083f6804564c1be136ac8e10b64ebee48f6d9a719988633f001b611ed60a71b1a7a1b595be3ab1a5d876cf9a0d86e26c5dfc4ceb2963937ecbd0a7873500b85d115d88af3838ed2b9b4c1a5aaf8d546786b2172bed07527d72f5b5bb15c5cd7339089fec4154bbc0dc37b92c7c91af56880a3699f728d121082be998c8000a9f282b3c80cbb815a723dec3ef1c7db995e326b31f1cfdf714f46e31464d32d54539720910680b1034ee6af9cc574be349fa1d1cf7666b5715d392558f16cadbcc2cd0b67e5e80005959d3445de0be4798f7a1e3bc003abce01a36ec36e41c90028bec1fac8227c6665d82b821c50bf2dd1725bfd257ff9d0fcd9da635b4fcd3d129c6401cc03fe108ac5b719ef6f2d6adc79eeb8dbfaf89487ba4e13fab495977668b9ee4b261627abe77094ba1411274b69e644482e3e4a9463a32146f0c5cb0495475a80c392a9f8c1f785f647bfcc14897fdeb74c326335d511dd03ffe548b1055f7b2378ba31701a9b09273c8ee41d9702358714d15ae958cae8f2e46b858ba5c9240390d86989e88489c77898e37d54bfd8de73b17fa1a57e0177a950c981e3174783c93cdc31dc5133298164511d89875179792783f5d1bc36789309f65d3e85034a578f159688751e2c49daae0ff8b50a501c7a7eb7c5f2cce063ec1bc0b35500d132f3379e827eef7919d488da4dee22fffb3581bd8cdc3a6af7ef4844c754a31c1519fdaca546726c259d27e01111bf44e18462c229d57582d22ca38214ad06c6aa3af9425be3b3b72d00ee1feb764f7bf8cb57452133b1a96f73d40462b0b51a80b3523c5b936a92200d7179b4c705c8ca2d3481c21349844ddde0400b19c54388fa465dfeb61d41ffde3e3f9abc6913b9acba43362c8869ce47995e38f06e29222f3ee256526bc1511b215550747bba3cc8b516946107e9d2fe79f955efa36c5d567b24735b18fa5cffd924b355c61808f103fb8d28128f8658a7e197785b66c5252557f174740f93886286f0981475c7699fa8552201ae3ce3cd20b3b0b1c5e166ecbca3f4f484bbfd4a5e2be556d0b0a44bae81a6e3c2a67e381ffaeef4b3b0fe74785d1991bf193c8eea1686db19c1867726d1fe37df19d26fe4eb78f79754e72a0ff66fa381675bac1d90406b5a62784caca11f51f5802d29ace1e64e71e86f213f70b35002688d4556605fe6351451a03c06ceeea64f6d1014adc68309c6dab7fa38ebf2b8a1b8ba6a3ec3e5c04c1d81f0ac02b0d1e7874496e978f78f29d15891b3dae69c8af582f3448d489c576cc3a28577a96c872c1fc69cbb053f4ce6b1770e1a674fa99f13037934a6ef9f408c4036506f08ef95a0de742e894ed23a611e96864f4f1e6a764ef3dd0f6048201e8e225a67587b19141850249ba55e30f3883ceee97a37205121d09c9f35776108922ab57cadd5758f2d656379100d9ce6280fb4d06527078bb1a75c686ddb44f45634939224c91f89bd7f29d12298e72cffabe02a81a9b7d26899f5d90401c3aefff2b340076d831c5f62a121ae56ca16df1b90987bca1907778b04e639a77a1cbe1bbb1e57f1a0c21cab036c0b4f020e4572792b0447874d31266d0b649e29acd2e", 0x59a, 0x40000007, &(0x7f0000b2e000)={0xa, 0x2, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x82000003}, 0x1c)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000f6a000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_tcp_TCP_MD5SIG(r0, 0x6, 0xe, &(0x7f0000f6a000)={{{{0x2, 0x2, @multicast1=0xe0000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0xa, 0x3, 0xa, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x4}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x5, 0xfffffffffffffff8, 0x9, "ead0e50f5ed3dd449bd606f5a652a805a7050de86ea5f38eba84cdf1b13bb1b74f831ee89a7e11ca97a334770cd090ca414fa15664a5f5923b76bf7a4735d7f2467228354a5ace10a0772af63ee037b8"}, 0x160)
mmap(&(0x7f0000f6b000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fde000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fdf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
recvfrom$inet6(r0, &(0x7f0000129000)="000000000000000000", 0x9, 0xffffffffffffffff, &(0x7f0000fdf000)={0xa, 0x0, 0x7, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x41}, 0x1c)
mmap(&(0x7f0000f69000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = accept(r0, &(0x7f0000c0e000)=@un=@file={0x0, "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"}, &(0x7f00002f2000)=0x6e)
r2 = socket$netlink(0x10, 0x3, 0xc)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x5, 0x32, r2, 0x0)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f00006ca000/0x3000)=nil, 0x3000, 0x3, 0x31, r1, 0x0)
setsockopt(r2, 0x10e, 0x4, &(0x7f0000003000-0x2)="2d84", 0x2)
mmap(&(0x7f0000fde000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$sock_int(r1, 0x1, 0x27, &(0x7f0000877000)=0x1, 0x4)
2017/12/15 11:53:27 executing program 2:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
syz_emit_ethernet(0x8a, &(0x7f00004f7000)={@random="1d389ebd93e4", @remote={[0xbb, 0xbb, 0xbb, 0xbb, 0xbb], 0x0}, [], {{0x800000800, @ipv4={{0x5, 0x4, 0x1000000000, 0x0, 0x7c, 0x0, 0x0, 0x0, 0x11, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, @multicast1=0xe0000001, {[]}}, @icmp=@time_exceeded={0xb, 0x1, 0x0, 0x0, 0x1c, 0x0, {0x16, 0x4, 0xfff, 0x0, 0x3, 0x0, 0x0, 0x1, 0xde, 0x7, @remote={0xac, 0x14, 0x0, 0xbb}, @remote={0xac, 0x14, 0x0, 0xbb}, {[@lsrr={0x83, 0x17, 0x3, [@rand_addr=0xfffffffffffffff9, @multicast1=0xe0000001, @local={0xac, 0x14, 0x0, 0xaa}, @multicast1=0xe0000001, @local={0xac, 0x14, 0x0, 0xaa}]}, @rr={0x7, 0xb, 0xdc, [@empty=0x0, @rand_addr=0x3bb]}, @noop={0x1}, @generic={0x7, 0x11, "b3395e057581cf256b715bea731b70"}, @ssrr={0x89, 0x7, 0x85, [@multicast2=0xe0000002]}, @ra={0x94, 0x6, 0x4}]}}, "6a98354794fc6357"}}}}}, 0x0)
r0 = perf_event_open(&(0x7f00009e2000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfffffffffffffffe, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r1 = perf_event_open(&(0x7f00002db000+0x89f)={0x2, 0x78, 0xd4e3, 0x0, 0x0, 0x0, 0x0, 0x2000000000000, 0x0, 0x0, 0x2022, 0x0, 0x1, 0x0, 0x0, 0xaa3, 0x0, 0x80, 0x0, 0x8000, 0xfffffffffffffffe, 0x8000000000, 0x1, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x7, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd9, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0xfffffffffffffffe, 0xfe, 0x0, 0x0, 0x0, 0x0, 0xbb7, 0x20000000000000, 0x0, 0xfffdfffffffffffc, 0x40, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r2 = openat$cuse(0xffffffffffffff9c, &(0x7f0000e66000-0xa)="2f6465762f6375736500", 0x400000, 0x0)
ioctl$sock_kcm_SIOCKCMUNATTACH(r1, 0x89e1, &(0x7f00001ed000)={r2})
ioctl$KVM_CREATE_DEVICE(0xffffffffffffff9c, 0xc00caee0, &(0x7f0000760000)={0x7, <r3=>r0, 0x1})
getsockname$netlink(r3, &(0x7f00003b0000-0xc)={0x0, 0x0, 0x0, 0x0}, &(0x7f0000129000-0x4)=0xc)
ioctl$sock_FIOGETOWN(0xffffffffffffffff, 0x8903, &(0x7f0000963000)=0x0)
socketpair$inet_tcp(0x2, 0x1, 0x0, &(0x7f00009d5000-0x8)={0x0, <r4=>0x0})
perf_event_open(&(0x7f0000300000-0x78)={0x200000002, 0x78, 0x553, 0x100000001, 0x0, 0xfffffffffffffffc, 0x0, 0x0, 0x0, 0x0, 0xfe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x80, 0x0, 0x0, 0x20, 0x80000000, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, r1, 0x0)
getsockopt$inet_sctp6_SCTP_DEFAULT_PRINFO(0xffffffffffffffff, 0x84, 0x72, &(0x7f00001b4000)={0x0, 0x1ff, 0x30}, &(0x7f0000f8c000-0x4)=0xc)
r5 = openat$sequencer(0xffffffffffffff9c, &(0x7f00003d3000)="2f6465762f73657175656e63657200", 0x2000001ffc, 0x0)
ioctl$fiemap(r4, 0xc020660b, &(0x7f0000276000-0x170)={0xf9b9, 0x0, 0x1, 0x28, 0x0, []})
socket(0x8, 0x5, 0x2)
fsync(r5)
ioctl$KVM_S390_INTERRUPT_CPU(0xffffffffffffffff, 0x4010ae94, &(0x7f0000fdb000)={0xc, 0x7, 0x7f})
connect$ipx(0xffffffffffffffff, &(0x7f0000fa7000)={0x4, 0x0, 0x4, "76e8c48950ff", 0x100000000, 0x0}, 0x10)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_RTOINFO(0xffffffffffffffff, 0x84, 0x0, &(0x7f0000071000-0x10)={0x0, 0x7855, 0x101, 0x3}, &(0x7f00003e9000)=0x10)
r6 = syz_open_dev$usbmon(&(0x7f00007f2000-0xd)="2f6465762f7573626d6f6e2300", 0x4, 0x8100)
getsockname$netrom(r6, &(0x7f0000565000-0x10)=@ax25={0x0, {"00000000000000"}, 0x0}, &(0x7f0000a53000-0x4)=0x10)
ioctl$sock_proto_private(0xffffffffffffffff, 0x89ea, &(0x7f000063c000-0x92)="78b3f23f12dab4d9f41c658493826950295c7da62bc8e4919313fbdb6233a19988f9a4eae45c43d4cff37182356a5f3d2df3063ade1accd2329bed258d7b6b73416827e8b338b2b916ff50cadd2d5a1271c735ddd7539161f8c326cf8d1425788e6a959d598d461edfe7c41e4fd3f2fc1f4ec3bc198c494552e88df4d760013a5ffa465e94c67f53a6a81f78292acdd4c238")
ioctl$sock_ipx_SIOCSIFADDR(0xffffffffffffffff, 0x8916, &(0x7f000000f000)={"0f9c4ea1d3887db1000000a103055102", {0x4, 0xffffffffffffffff, 0x0, "00005ae1ae6b", 0x7c, 0x0}})
ioctl$sock_bt(r6, 0x541b, &(0x7f0000449000-0xff)="1586f2c272be12c80549095593cc89b458c919add267ab7e9e6c04886d5089bda1d63805797c00f5d7449333370dd53c3485482c4a44412ec5f0d08d287126d18dbed0e59ab4832d2d7ba5782bbb6d01795daa308e7407af6fdff46181a8010d21075d1975ea16d165eb99f7bc4deff7cb1ca333bf0daff07778d059801d6fa3e14d6ae42852286294965e08e2e320c2410acb8e9d06c68765719e46bcd3ded95f98e4e34939aac958dfe623bc39bcab58b4f697ce93feabe125e0714ea35205c57f3f3f6b1276f3358ebb5b8d283f0f34de20428809e13c93714e680a6a4dd94e627c3da8f73bc7e33b4b2c3b5fcd1ef6fa956b8a12d4820c6469d8616e4b")
getsockopt$bt_hci(0xffffffffffffffff, 0x0, 0x4, &(0x7f00002c7000-0xf4)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", &(0x7f00004b5000)=0xf4)
openat$cuse(0xffffffffffffff9c, &(0x7f0000543000)="2f6465762f6375736500", 0x101000, 0x0)
r7 = socket(0x10, 0x2, 0x10)
getsockopt$SO_BINDTODEVICE(r6, 0x1, 0x19, &(0x7f0000adc000)=@common="00000000000000000000000000000000", 0x10)
write(r7, &(0x7f000048e000)="240000001d00130000000000000000040a3907af100004000c000100f7ff000000000000", 0x24)
socket$inet_udp(0x2, 0x2, 0x0)
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x400000000001, 0x6)
getsockopt$inet6_mtu(r0, 0x29, 0x17, &(0x7f0000125000)=0x0, &(0x7f000060b000-0x4)=0x4)
getsockopt$SO_PEERCRED(r0, 0x1, 0x11, &(0x7f0000194000)={<r1=>0x0, <r2=>0x0, <r3=>0x0}, 0xc)
setsockopt$sock_cred(r0, 0x1, 0x11, &(0x7f0000790000)={r1, r2, r3}, 0xc)
setsockopt$inet6_int(r0, 0x29, 0x42, &(0x7f000002a000-0x4)=0xa, 0x4)
r4 = openat$vga_arbiter(0xffffffffffffff9c, &(0x7f0000e8d000-0x11)="2f6465762f7667615f6172626974657200", 0x10002, 0x0)
setsockopt$sock_int(r4, 0x1, 0x28, &(0x7f000021f000)=0xffffffffffffffff, 0x4)
setsockopt$inet_sctp6_SCTP_PARTIAL_DELIVERY_POINT(r4, 0x84, 0x13, &(0x7f00006eb000)=0x38c, 0x4)
setsockopt$inet6_tcp_int(r0, 0x6, 0x17, &(0x7f0000998000)=0x400000009, 0x4)
r5 = dup(r0)
getsockopt$inet_IP_IPSEC_POLICY(r4, 0x0, 0x10, &(0x7f00000b6000)={{{@in6=@empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6=@loopback={0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, <r6=>0x0, 0x0}, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, {{@in=@loopback=0x0, 0x0, 0x0}, 0x0, @in=@multicast1=0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, &(0x7f0000153000-0x4)=0xe8)
ioctl$sock_SIOCGIFINDEX(r0, 0x8933, &(0x7f000061d000-0x28)={@common="73697430000000000000000000000000", r6, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
setsockopt$inet_sctp_SCTP_DISABLE_FRAGMENTS(r5, 0x84, 0x8, &(0x7f0000f8f000-0x4)=0x8000000000008004, 0x4)
fcntl$setstatus(r0, 0x4, 0x2000)
r7 = dup3(r4, r0, 0x80000)
setsockopt$inet_tcp_TCP_MD5SIG(r5, 0x6, 0xe, &(0x7f00002d4000)={{{{0x2, 0x3, @loopback=0x7f000001, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {{0xa, 0x2, 0x100, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x100000000000001}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, 0x5, 0x20, 0x1155, "f881304f031e2d8b49ed86eaa3ebcba3e0a607ff561743228025da5dc9f381eb1878a7a8e9da176cced5d86d9ef83b002604361a59f93ceed95736a71b43c54e012034cac54c644825fd4b36517ae568"}, 0x160)
setsockopt$inet6_mtu(r7, 0x29, 0x17, &(0x7f0000c22000)=0x5, 0x4)
bind$inet6(r0, &(0x7f0000710000-0x1d)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x1}, 0x20)
getsockopt$inet_sctp6_SCTP_DELAYED_SACK(r7, 0x84, 0x10, &(0x7f000083f000)=@assoc_value={<r8=>0x0, 0x1}, &(0x7f000040d000)=0x8)
sendto$inet6(r5, &(0x7f00009a1000-0x1)="07", 0x1, 0x20000001, &(0x7f00008d7000)={0xa, 0x0, 0x4, @loopback={0x0, 0x1}, 0x0}, 0x1c)
setsockopt$sock_int(r0, 0x1, 0xa, &(0x7f0000783000-0x4)=0x263, 0x4)
getsockopt$SO_PEERCRED(r4, 0x1, 0x11, &(0x7f00005ed000-0xc)={0x0, 0x0, 0x0}, 0xc)
socket$inet6(0xa, 0x80000, 0x492)
getsockopt$inet6_int(r5, 0x29, 0x1, &(0x7f000047d000-0x4)=0x0, &(0x7f0000a45000-0x4)=0x4)
setsockopt$inet_sctp_SCTP_AUTH_DELETE_KEY(r4, 0x84, 0x19, &(0x7f00007d8000)={r8, 0x393}, 0x6)
fcntl$setsig(r4, 0xa, 0x1f)
setsockopt$inet6_int(r5, 0x29, 0x400000038, &(0x7f0000307000)=0x0, 0x4)
fcntl$setown(r4, 0x8, r1)
sendto$inet6(r0, &(0x7f0000367000)="744136e0c9e7472238d0e51375a830155f9f2fd324540a30d7c3a1082e29c214b863347943fcc1a6d4c3e1aa2c9544e3de8e5a46f75f9afcd592ae50a02d3ef77e7634fca456afbf3642824125670a0f4d580c83ed702cc59fedd9fe457cb1cd803767f0d7c1f1f58986465df795b41e17d649735a987a559f0043743ff011414bb89b990c8d7ea1d7c42698d25c23cbe0d6f2b4b5e1258fee8d01b10608d71ec50b7730172d6ee61157779b538b9b9db1915ae654c1521350064f49ee608ace2bc34cb6e90afd28a06b07fbab416b9a18b097c8c64cc3e839508cb381af297a4af4bbb6aa4be0453b2ac75674018cf8b9b97fddc7cf1209e37ba5151d4719a34cff8fb756488a0898a94b1b5569f8a8940d2f27d6f16b1d5796e6950faa462e0eb6791e6fae5aa0be660531790a86e5a6683120a9ca958ce3d9f3efcd255f5708e41c21d4d690c7346973fe4f7a8e8e580426e3a132af427ebcc1ce594c6eb2400d4f181b45a50ab3e30244c467eed4af0efd01e00154d2efda6035286130594bc0f833b2691d79391e95bf2a70129723dda5faef8b2392b3b4e4320cfdb3cb187b2ddf5e6157f9ee48e9dabbfb819adb49f6ebfc1223f128794b7497f37a0f5601be377332f2bacb23b4415b0666e7392afdb8106f6b4fbf2a65e2539e99086e4c10dbcd8661a143a14491a494f75ac6e2d10d911200585bda372f2c7c80d7548d923342fad2631a4618865e8768a544dc1a30ecce4c858c1250df6d348d698ab96fde7f8f464745783680dec9af4bcc5c72aa39ca96da28c5129e6abed1650cbe7ecdb4958b9d77cd6f5bf046d86d8f8ad5ffafffc66ae4854ec7d79bfd03cf8ee4efcae855e71263cf37778962cd516fe0736c25767dce54ec306e877ba738e38741fda1a82996d0858ccb6d450fe7a506f0934d66f30ce86f35ec6967910e57da49509e4b59d435f50a9a160c002425fe1b508b27f7e6c8472f576cc801d1423aceaded07ac776ed6420a4b1292e6a07418d0ee8791ba0e97f4326d47b29fd4c309458f104213e6c2373f776979de6101c5bcf215502e45524b997cb2bd663e13e93b00f811b0d2758abbc71a3168ae73e6f5950e236a6a8f07e7e85693699192033aeaf6edf1930efc20d8cea61a2181362b43788097d22bb72f0744f93f87131df61a0fd204ef1b869ff7b78a1e8b9b469cc79e6e181ce38ca209e9246c1f422b4739075f142fa0a430cf439211ffb6bae03505ad7ef8f8dfb8bdb87083cb8d5022c7c635e3d485653bf56d220f6a04300b932d8b028abf53b22ac54ef304c7dac724149b5c7fe7beaf7bf8bf95353a7b7cffe1c91596044f5708c94c0d743e1a60f695dadae80c0b964540780fcf431ad001c0f787d7a4ffa43aa55e52dfd42782ed68c1b050cec26445056a8f45ceb2956821c4f6f818ce35f24382f40c40602713ec0499181f0e461a168d075c290ffc5ef1208bfb020c7e36d7703227e6e719e74fd9461eaceb0d4dd090be6649a372a639b6185676619ab9e03df32afc4fbc8de4bb21dc64d04b27610bdc1195a52ff6736bac3b1f48031fcf0b18b0bede406f2bb9b531a241140bae2e0086502efa94bf9471650e0ed8be38ce4b80de364a277d4b25b479d7a8680985ccf675c71ab9a1eefaf572f0240c5a79e08e37b9c69630a45871e5af998a9855d8c80376da8e8ff820ab47be59ad7ec84e79250463d2e6f32de5ce7bd8b9d61abbeee8ab3fd773642fc7197b9311ec795c971041bb782b56c70c64706de94a8d0459d06774e9e174aa1f85ba2cccd613c1698f1f51e0c2f6faec02b3e541f267a7f32791eb4f0ad2cce047767a0f1ce8d0412ad6fd040b698f613d515891c8be10a740b6d6a17909e8de12de5854ff7064826f8f3283e94d9cda8eb5d90333bf9ef4f0b942d1de13017428fe4cfee4c749effbd0a52808233d22c6da101d5037ba8b97b4734e9395244438892a6b9f17c093898a18f081b0277f612fe6a66552f0ccb60a79c2a7151d516ca8deed61490de0146ce1298ba5de167c12e7db9779047cd4d481650548c13bfe88b883af04751bf34bb0e2eda328c04f788d9d3f8fc70534053a697f64ec26c5863991295ae6493e0b72050c5739b42c54710034fce360c71cd4e8032de0875f179b32373d91cc34978b89843ef491de3536258c6b48fbe40b1f32aad88dfe3b59bbae8d00dce50d88878129e5bbd9ecddbcbb882cb7135bfad8befb92413361e18cfef01b9de4cec3a43e62295ab6a177235dbe8fb5333405f85447e045b5a9c3a81c8628cbdf5417cd2ed5772b20826f19638beb2473fff82f9748931e842e4510e88e835fa073b09bc228dab4d03045d7fafb5e7e0a36fc3152a699079ee1fbe9c7e4587ded1c72975e7ec8f28221b8d03ff83d5aa2854363549537e1fd5e7f31b6e7af2ac35a1543ac1eba7a637d139467b2b08bc54aede06f775f0837ce2836c66c8b10a63b7f2db7b4a51965fd6eee4216f6505b1058c413f4064daba55161cc79158a1a1a8eb3058d5c9fc637f9a23388100595420f251a81a4e93b4f38e2b4eddbe56d0048dd0626d7be5b79141292c949efc4904d5ffbe559acd4547fefa834e4c4c85516720414c39fa6a4cecbd68bf4756d4c43ac86b30c49e071ce43f97180f8445386e5ba4a41cd47688f059b842e1bf2714066d801a1587397fd7e364b5b2c4f4afcfc3a00d8f55cd687d6d9a69f2ba056495114cc11b8c7af899ad76a60e0ee99697f1b9f43749653bbff1c86834d6da65e4475717f3c1a806eb6b407412d56732b6c6b77d359a7d76f9d82eea13ac277ce64d74243ffb2eda77f337f7243145063de61209fdf6a66b5cf9c185c58c6b0b441d4ccd2f6850edb5b508b24d664c8f2824fb9d21dc9bd8c2df8457e915fee9bf3b84d4e989d4eef7c5137fd2cf9e1f2f213beaa6539b3dcd62244b4e019733ab15d6b12fd83e2b2a53cecaf932dcf03526b531e0ed929c68024a418458be42aff7631f54bffbd3f0103131dc0a905d8cd30c4a79e2715a8f3d064ba7bdd5072b88f93d83f08a0243e939b6014297bf9c190bebc7a445153b90762036f874923bbf7cd410b563d6286c6f44383fa63fb87b41526c8593ed2e75966209415f391bdc6fbe4f81e5afbd785445262a284748c1aed9da0bf899ad141a02bb52c4ea2c2b4ff965788ede8572c064e41ae7313908db1f6142ff8c4a17a92fd7d7a1081b585fb283dc065507db3f4964974394713c09dbe54183dde1b538ee6c65ca82b4617879bd07b49ef4214a77041eb7432471273c8b215b1e2572f01c2c276e7c1626972c7e13461eaa242ad545a1b99a1f165028478faf1d1f4bc323c0ba48694174772a0cab32a8a92f9392f325f1a982f8dd3d0bb82f85f72891319b203b92bf34ed5aee3ed5ff85ce0ab49287c252e79de675133b81db3b607dd8a25a576daf4a6e96b91cfc441fcedeb26cbc49ebc27cfbb6ce7b025093811bb69b1d03d0f813bc187073a2782cc58d95f65e79bd94c0808c82c61ad5f965bb36044d3e2eb4c8ebc451038bc08d01c9dcc7aff294adcc38cf4f22e10c3c1fdcb31ee98f7c5285d9e69bdc3b8939c0cdb72eb16e3909c55c970be907c646c04364103f0d27ebd853fdad9d587f3932295bc3c3a871497beebe143a8ebe77231b5e232b9bad80a8a55727b9fbc3016d6a244d712d9c6238208513147ea3086bb9e051b0bd0db75be37f90a87d54c2280e109a1d39609e4d01a8f6a883f5782d878ca8e21fa0d517ddb6b6e0a7275b181863f1294f6ab3eb2f93be796ca351ba1958b639cb6d68be4f164d4166bc3f0a3b770b8f5a8c94648c5f844ba964465a10630b2b0ef9e3359c5066ba5ef260c4b2e7b13b7a80a3f45e25fae1ce21b523113543cb5595468dfe048d1cc86ebf232bcc789bfcda37c0b4a378a618b750f33200c54c423e442a905984b3090968ab6404f2b51947f79668467c3fc96a0ec022c6f87dea8a1579839c18e188c53eab15699e388645f98aa23e099636f5835334e4be88bdc4ac99654426a30904213787ff790a5cc4a65bb806aa273645eaaa8d41fbfe8948e4b1faa4512979767e47b51e87a5552e39b137d8c124866f1a0b166a7654affdd216b6cea0bb478826c2948b9b60254421fc4458d801fecc9a4b26d49b6fa555815b079da7049816d78c9f6f0a6fd3da83b8d69695ec5e7608022dfc2143f89bf10b8e890ab6f45283e9ed03890cd491e2b062a8188640562b02064e17fcce29b5915f3c54d0e153ffbfd7a3cd161e3d232cf301401ee803df3cfbde16dff9ac14a6676dc074ea28863fb5aebd1f3814ab4fd16ed497039c8a84520f21f696015ba3bed8ba1eb7e62f8c561915623b7f4a95f6165233c7823af9d129a6dc674b1ed54f03318566b3f75d200c94b12d6b90e568a46717af4523fdea96d8f876af4a804253d2d5b06006a861abf35a37831e3148f69d68efb046b1bbd55d84cd30f69dbed5662993cf914366da3e2ed5e969b0c4daf93f69beab4210c7b7370db5ecc7537c02d3d5003a047f7455b8fc079db1e02ab215a7a072917cf12fb77d8b366738773f1341209e0612b8196ab486d902a485318ebc7c801b6695e5a8bda9a9b0771988bfad9b60c375f77757578204e5251db5c174430e09089ded887376fb72334042a6cb170e0aa3f76d615c8e009105eba979d9308296a2c0c9cc191b4a47903819238974514d7c133a9c874a05b9d9a9ca88306d1930c1a9d47b07720d48aa73332a9286a566b659b5a3a69f0bc388c7a95a4cc7b7295df548d6ef6186213efd67701117e08802dd5be2307e45b2c6be93ac4fbf20297f5a29ede44cfca1dd61e8263e2e5b6c1b4a1dd3cac6bba8cbb87b9d1f2712d6381562ebe38282df04fb7df2338ae6233189c203fbb40194ddfda34919bfaab7466b72def1e0c9886641442b9c25e837aff49674d5b73c7e30099bc5726b2ba460990cb958869d9fc155307906e33f249702061aecefa5ee194f2b878c37e697a801671cacd8dd1c72dc124dd84bcfad78030db162f73fd208d93ca12cc3193c06d54b560d5d999f2a0092adcc5d1a6f9a2bcdae5dfbcbbcefb8be5979a476679b840008b64ceb64f62e7abbdc302cf0e48ebff2b83a9f0049ea821b3e61b3a134dd29bf5fcb456321493c9382c3077cc81b1480fb9ab1679003846b0cab9c429734d3e1f39c11f49b80cd5b826f4b864284bc556d2ee2f2b83fa5afa869183c85c226752ed9ac0aac0d4de251168442e2ccc680577467fb837c031d476788d0ca1a8248b3464453e8b0c353b910681c6349c5aa621022028ef3aa33ebd2e7940d0d7963b5dc44fb5396233f8513ae828eaeb7e2a2c247526aba84aa27b2255fec4e3903c0c9a6f95a2c130087b64c560bfdca53143a9acd4734e1c9ee5add3c9e97ca7b4ca96e684947fc7dc1cad92be4104fffdcd6504e145b9f5f2a4c7881058fd47b47f7bc42d678686bf4ea77ec5f12db579acb220072abfffefeea39358ed2072369a3acd2509c915d324c7c67a8924e864d506c4b4edab305c40559aa3d91e72d9c45d2519fb9371ddf6df90865c1c15b2c0955fbae66090dc8aba00d20270fc3d77a779d65fb5a38265dcfde964b75cd042a9d24c245578aaa183fe2482b93a5f1dda596e8eaec143537ff8bae160cc2b6f8f91b028c5d1312e939d7668d27a00000002f746729d852474ef2ee1ae1342a718510b3cf33426697f9d697e18a9b6535914c4dd8bcc8251dd566e9ae5c5", 0x1001, 0x31, 0x0, 0x0)
2017/12/15 11:53:27 executing program 1:
mmap(&(0x7f0000000000/0xfb3000)=nil, 0xfb3000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = getpid()
r1 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xdd, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0xf6, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xffffffffffffffff, 0x0, 0x0, 0x0, 0x0, 0x0}, r0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x4032, 0xffffffffffffffff, 0x0)
r2 = getpgrp(r0)
r3 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xde, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xfb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x7f, 0x0, 0x667, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r2, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfd6000)=nil, 0xfd6000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
futex(&(0x7f000000d000-0x4)=0x4, 0x80000000000b, 0x4, &(0x7f000000b000)={0x77359400, 0x0}, &(0x7f0000048000)=0x0, 0x0)
timer_settime(0x0, 0x0, &(0x7f00009b6000)={{0x0, 0x1c9c380}, {0x77359400, 0x0}}, &(0x7f0000e4f000-0x20)={{0x0, 0x0}, {0x0, 0x0}})
clock_gettime(0x0, &(0x7f00001ef000)={0x0, <r4=>0x0})
timer_settime(0x0, 0x0, &(0x7f0000b33000-0x20)={{0x0, 0x989680}, {0x0, 0x0}}, &(0x7f000030b000)={{0x0, 0x0}, {<r5=>0x0, 0x0}})
futex(&(0x7f000000d000-0x4)=0x100, 0x0, 0x4, &(0x7f000000b000)={r5, r4+30000000}, &(0x7f0000048000)=0x0, 0x0)
futex(&(0x7f0000bf8000-0x4)=0x0, 0xc, 0x1, &(0x7f0000a51000-0x10)={0x0, 0x1000989680}, &(0x7f0000048000)=0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xc3f000)=nil, 0xc3f000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r6 = socket$alg(0x26, 0x5, 0x0)
bind$alg(r6, &(0x7f0000b17000)={0x26, "6861736800000000000000000000", 0xf, 0x20001002, "7874732890657270656e742900000000000000fffffffa0000000000000000000000000002000000000000000000000000000000000000000000000000000000"}, 0x58)
set_mempolicy(0x1, &(0x7f00000e0000)=0x1f, 0x81)
sched_setaffinity(0x0, 0x8, &(0x7f0000092000-0x8)=0x40000ecd9)
ioctl$PERF_EVENT_IOC_ENABLE(r3, 0x2400, 0x8000000000000)
mmap(&(0x7f0000677000/0x3000)=nil, 0x3000, 0x8, 0x13, r3, 0x0)
setrlimit(0x800000e, &(0x7f0000959000-0x10)={0xcbe2, 0xfffffffffffffffd})
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r7 = perf_event_open(&(0x7f0000001000-0x78)={0x5, 0x78, 0x0, 0x9, 0x0, 0x80000000, 0x0, 0x0, 0x0, 0x0, 0x668, 0x0, 0x2, 0x0, 0x0, 0x0, 0x3, 0x20000000, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r8 = socket(0xa, 0x80002, 0x0)
setsockopt$bt_BT_DEFER_SETUP(r8, 0x112, 0x7, &(0x7f0000539000-0x4)=0x1000, 0x4)
r9 = dup2(r7, r1)
ioctl$TCSETSW(r9, 0x5402, &(0x7f0000000000)={0x3, 0x401, 0x2cb, 0x1, 0x3, 0xffffffffffff8001, 0x8000, 0x6, 0x3, 0x3, 0x800, 0x0})
mmap(&(0x7f00002c6000/0x3000)=nil, 0x3000, 0x0, 0x801d, r1, 0x30)
getresgid(&(0x7f000068d000-0x4)=0x0, &(0x7f0000000000)=0x0, &(0x7f0000000000)=0x0)
mmap(&(0x7f0000283000/0x4000)=nil, 0x4000, 0x8, 0x51, r7, 0x0)
select(0x40, &(0x7f0000feb000)={0xd21, 0x3ff, 0x80000000008, 0x10000, 0x981, 0x9, 0xfff, 0xca2}, &(0x7f0000535000)={0xe5cc, 0xfffffffffffffffb, 0x6, 0x44c, 0x1, 0x2, 0x4000000000000000, 0x4}, &(0x7f0000366000-0x40)={0x8, 0x1f36, 0x0, 0x4, 0x5, 0x80000001, 0x4, 0xfffffffffffffffe}, &(0x7f0000965000-0x10)={0x0, 0x2710})
wait4(r0, 0x0, 0x1000000, &(0x7f0000b99000-0x90)={{0x0, 0x0}, {0x0, 0x0}, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
timer_gettime(0x0, &(0x7f0000039000-0x20)={{0x0, <r10=>0x0}, {0x0, 0x0}})
sched_rr_get_interval(r0, &(0x7f0000b5e000)={<r11=>0x0, 0x0})
clock_settime(0xbd104e44da26b44b, &(0x7f0000cdb000)={r11, r10})
syz_open_dev$sndseq(&(0x7f0000049000)="2f6465762f736e642f73657100", 0x0, 0x8a002)
2017/12/15 11:53:27 executing program 7:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = openat(0xffffffffffffff9c, &(0x7f0000c04000)="2e2f66696c653000", 0x111101, 0x1)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0x3e3, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x400000000000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, r0, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xd4e7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2001000000000fa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
r1 = getpgrp(0xffffffffffffffff)
r2 = perf_event_open(&(0x7f0000001000-0x78)={0x4000000000000005, 0x78, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x666, 0x0, 0x0, 0xfffffffffffffffd, 0x0, 0x0, 0x3, 0x20000000, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, r1, 0x0, 0xffffffffffffffff, 0x6)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r3 = socket$inet(0x2, 0x5, 0xffffffffffffffdf)
mmap(&(0x7f0000000000/0xed5000)=nil, 0xed5000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r4 = socket$inet6_tcp(0xa, 0x1, 0x0)
mmap(&(0x7f0000ed7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ed7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000ed7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockname$inet(r3, &(0x7f000072c000-0x10)={0x0, 0x0, @multicast1=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, &(0x7f0000feb000-0x4)=0x10)
ioctl$sock_inet6_tcp_SIOCOUTQNSD(r4, 0x890b, &(0x7f000055a000-0x4)=0x0)
fcntl$F_SET_FILE_RW_HINT(r2, 0x40d, &(0x7f0000335000)=0x3)
bind$inet(0xffffffffffffffff, &(0x7f0000703000)={0x2, 0x1, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10)
r5 = socket(0x10, 0x2, 0x0)
setsockopt$inet6_MCAST_MSFILTER(r5, 0x29, 0x30, &(0x7f0000ba5000-0x210)={0x5, {{0xa, 0x2, 0x1, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x1000001, 0x0, []}, 0x90)
setsockopt$sock_int(r5, 0x1, 0x22, &(0x7f00006ac000-0x4)=0xfffffffffffffa70, 0x4)
r6 = openat$vcs(0xffffffffffffff9c, &(0x7f0000001000-0x9)="2f6465762f76637300", 0x0, 0x0)
getsockopt$inet_sctp_SCTP_MAXSEG(r3, 0x84, 0xd, &(0x7f0000c6a000-0x8)=@assoc_value={<r7=>0x0, 0x8b4f}, &(0x7f0000529000-0x4)=0x8)
setsockopt$inet_sctp6_SCTP_ENABLE_STREAM_RESET(r5, 0x84, 0x76, &(0x7f00007da000)={r7, 0x8}, 0x8)
chmod(&(0x7f0000665000)="2e2f66696c653000", 0x1)
r8 = socket$inet6_sctp(0xa, 0x2040000000000001, 0x84)
sendmmsg$inet_sctp(r8, &(0x7f000045f000-0x118)=[{&(0x7f0000249000-0x10)=@in={0x2, 0x0, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f0000455000)=[{&(0x7f000045f000-0x2)="93", 0x1}], 0x1, &(0x7f000045f000-0x60)=[], 0x0, 0x0}, {&(0x7f000006e000)=@in={0x2, 0x0, @remote={0xac, 0x14, 0x0, 0xbb}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x10, &(0x7f000045e000)=[], 0x0, &(0x7f000045f000-0xf0)=[@init={0x18, 0x84, 0x0, {0x0, 0x0, 0x0, 0x0}}], 0x1, 0x0}, {&(0x7f000002e000-0x1c)=@in6={0xa, 0x0, 0x0, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x0}, 0x1c, &(0x7f00009ab000)=[], 0x0, &(0x7f000045f000-0x60)=[@init={0x18, 0x84, 0x0, {0x0, 0x0, 0x0, 0x0}}, @sndrcv={0x30, 0x84, 0x1, {0x6, 0x0, 0x205, 0x8000, 0x1, 0x2, 0x2, 0xa8, 0x401}}], 0x2, 0x0}], 0x3, 0x40)
ioctl$DRM_IOCTL_ADD_CTX(r6, 0xc0086420, &(0x7f000078e000)={0x0, 0x0})
mmap(&(0x7f0000ed7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
write(r5, &(0x7f0000016000-0x26)="26000000220047019353ff07008a0000000200e6000000ff00c0d7e3ff495180e532c7033500", 0x26)
2017/12/15 11:53:27 executing program 4:
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x6, 0x0)
r1 = syz_open_dev$sg(&(0x7f0000ada000-0x9)="2f6465762f73672300", 0x1, 0x40000)
ioctl$sock_inet_SIOCDELRT(r1, 0x890c, &(0x7f0000b9c000-0x78)={0x1, {0x2, 0x3, @empty=0x0, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x2, 0x3, @rand_addr=0x400, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, {0x2, 0x3, @local={0xac, 0x14, 0x0, 0xaa}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x0, 0x40, 0x80000001, 0x6, 0x6, 0x0, 0x6, 0x7fff, 0xf078})
r2 = syz_open_dev$tun(&(0x7f00005d0000-0xd)="2f6465762f6e65742f74756e00", 0x0, 0x28004)
r3 = fcntl$dupfd(r2, 0x406, r2)
openat$qat_adf_ctl(0xffffffffffffff9c, &(0x7f0000007000+0x20c)="2f6465762f7161745f6164665f63746c00", 0x503000, 0x0)
ioctl$TUNSETIFF(r3, 0x400454ca, &(0x7f0000db4000-0x28)={@common="67726530000000000000000000000000", @ifru_names=@generic="16f1a03340487c8735db24a266325d59"})
bpf$BPF_GET_MAP_INFO(0xf, &(0x7f0000237000-0x10)={0xffffffffffffffff, 0x18, &(0x7f0000d02000)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}, 0x10)
bpf$OBJ_PIN_MAP(0x6, &(0x7f0000727000)={&(0x7f00009bc000-0x8)="2e2f66696c653000", r3}, 0xc)
ioctl$sock_FIOGETOWN(r0, 0x8903, &(0x7f0000cf8000-0x4)=<r4=>0x0)
ptrace$setsig(0x4203, r4, 0x101, &(0x7f0000f26000-0x10)={0x3b, 0xfffffffeffffffff, 0x4, 0x0})
lremovexattr(&(0x7f0000da0000-0x8)="2e2f66696c653000", &(0x7f0000ab3000-0xa)=@random={"747275737465642e00", "00"})
r5 = syz_open_dev$tun(&(0x7f0000481000)="2f6465762f6e65742f74756e00", 0x0, 0x1000000000000000)
r6 = fcntl$dupfd(r5, 0x0, r5)
ioctl$TUNSETIFF(r6, 0x400454ca, &(0x7f0000928000-0x28)={@common="67726530000000000000000000000000", @ifru_settings={0x7db, 0x0, @te1=&(0x7f000032f000)={0x10000000000, 0x0, 0x3, 0x3}}})
setxattr(&(0x7f00000e6000)="2e2f66696c653000", &(0x7f0000d7e000)=@random={"747275737465642e00", "00"}, &(0x7f0000201000-0x1)="00", 0x1, 0x3)
syz_open_dev$usbmon(&(0x7f0000b69000)="2f6465762f7573626d6f6e2300", 0x80000001, 0x40000)
ioctl$sock_inet_SIOCSIFFLAGS(r0, 0x8914, &(0x7f0000cf6000-0x20)={@common="677265300000e4000000000000000000", @ifru_flags=0x2fd})
openat$rfkill(0xffffffffffffff9c, &(0x7f0000113000)="2f6465762f72666b696c6c00", 0x2000, 0x0)
r7 = socket(0x10, 0x4000000002, 0x0)
sendmsg$netlink(r7, &(0x7f000061f000-0x38)={0x0, 0x0, &(0x7f000047d000-0x40)=[{&(0x7f000057d000)=[{0x24, 0x26, 0xffffffffffffffff, 0x0, 0x0, "d45029db0300000000000000ffffffffff"}], 0x24}], 0x1, &(0x7f0000cdb000)=[], 0x0, 0x0}, 0x0)
mknodat(r6, &(0x7f0000bae000)="2e2f66696c653000", 0x4, 0x0)
2017/12/15 11:53:27 executing program 2:
r0 = timerfd_create(0x5, 0x80000)
setns(r0, 0x8000000)
mmap(&(0x7f0000000000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
get_thread_area(&(0x7f0000000000)={0x3, 0x0, 0x2400, 0x2, 0x1, 0x7, 0x100000000000, 0x10000, 0x5, 0x3})
r1 = syz_open_dev$usbmon(&(0x7f0000001000-0xd)="2f6465762f7573626d6f6e2300", 0x3, 0xe0000)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r2 = getpgrp(0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
stat(&(0x7f0000002000-0x8)="2e2f66696c653000", &(0x7f0000001000)={0x0, 0x0, 0x0, 0x0, <r3=>0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000001000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getresgid(&(0x7f0000002000-0x4)=0x0, &(0x7f0000002000-0x4)=0x0, &(0x7f0000001000-0x4)=<r4=>0x0)
sendmsg$netlink(r1, &(0x7f0000000000)={&(0x7f0000001000)={0x10, 0x0, 0xfffffffffffffffd, 0x1}, 0xc, &(0x7f0000001000-0x70)=[{&(0x7f00001b8000-0x12f5)=[{0xc2, 0x7, 0x8, 0x2, 0xea2, "8d5a0a36342e5e2ad3c566103b876481119637c85b8848a1811d4a0941677a0a4bf6d542923db64ba9e1cfa2a3b3e6b6115c3bcddf0cb2640ed7e3fba4b0ad105de6351ed0bea6ded87123db177c685adfd003dbe79838d6b0b41927d6c4201588e96af6eabd1f165c53f8917f1a3e9a4ce4e899892dcfe603e48bd0856efe302a773f7de9189719313b832daddc337584e0a0bbd0f1c6fb8243c5439bcd43e7dd3ee5c075400521c4f02db306eaeba7650b"}, {0x27, 0x6, 0x400, 0xfffffffffffffffd, 0x8e, "2666cb667fe27b4c0ef537e66d5b8bee74ef23cc8337df"}, {0x76, 0x5de1, 0xc04, 0x1, 0x400, "d114cb6a0850b603bb13dbe6fc3049a17c84b02001f3f9aa282ea7df937a0a80f3f04eb3948e3946c87f41389a3729c5a7393d47c0d53f950ac5f21c484e9a657840e7ff0bd2c9b3bdf2e34354563aec662534622e707c961ba8074313c590ae19a671c61932"}, {0x87, 0x6, 0x10, 0x101, 0x0, "858de21bf048f0db9fe9a150e2ec9931f7c0a0604c93804c3a1a18535ac5cfbea5dd1ac5fca4ab275f512454dadc1b19ab73df46deb9c42d106ce035ad13fdb5b798322446e4e9ff8a0903c60f399773932022b60e8243ec26466c6ce7620cad96fceee113414ac41cf70d1ac44371d6f75e2cedd5443a"}, {0x1010, 0x8, 0x87809c782f4eea25, 0x3d90, 0x3af, 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"d241eb92ae441d22e952785d60e109ffb95798c7d0d8d6e85c0c00cd5d3a17659ec9ade7b923ba1cf34f756a8b3e6174fa9a1e8480ffb532102599e758533bc2eab025c9545dbc77656d734205efd1f1c26c1317dcc1cb47ae316aa52e4977e33d54f5557f689054c52452024a9030436370fbe7398d1797242f173a923e102f7f8d2f25fb879fb100d5b98b2dc5dbbffa22be2b7b1917620b20e9c352ebc33fb572439944b13c1d8f85fa8241eafdaa7191c3ab248ab1b5384936cfb0f6c9d4ff"}], 0x2fc}, {&(0x7f0000001000)=[{0xbc, 0x0, 0x402, 0x4, 0x4, "7450afb931a9cc86d80d8f4e563e1ddff6fc581dd4afb6f38b93f663e90f011f25c180e3d6bbaa0f017662dfd0111ee39550143a606fa9096e120148bddf7ec5de288c26a902242b017182ff2d6dc49d405eb04325dc9f10a4c9dd3edf34cc0a541bd7daad0b7a35856c369f5d4ff14c56fe5a95ea61dc2256c3621cf45163aea1b2296e627fcd1c82ea8b4d493bd7b388beddf871833e4114a7e4f7878354c9316ef7757455266d7adfba26"}], 0xbc}, {&(0x7f0000001000)=[{0x5a, 0x40, 0x200, 0x6, 0x5, "4828a2a0d6d1d64003c2e35197220632784a0fd021e71503ce857414e4d5e0d5359abceebd15e37c1086870aab836890f790b4babc5e5c76b5573fa2b50913fcf627e4407313488d9fdd"}, {0x103, 0x62, 0x200, 0x7, 0x2, "5f7033af578ac4af603fb80df2fc1e00afaa41db932b1c64be45fc06d22ae8880fd3f2cd5decb327d04bf78c81e16f3aa4e19e740bb09b9e367333c659578b357c04f08235d7c42fa065f742dce540dd54ba84905cbcd237ebbb7a2cff1e30120a5f4070635d242e159df498aff4cb396e8698f42a87ce4488ccd6da83531e2211c00f94beab56ab9aa4e0de55cbb0aa3d71bd80e46100b3b79b6714fe3fa63687d380bdd61c6fbfa496e8f7dffe13b9ae624ab8bb6ba88fa7c398ac17dabf136269b563e2ef3e1998cb5357c4dbf47d742aa6f9879c067eee5946ec0b6ec097c31a8cbf0ecb47f8cd8ddb03e47c3b2a55bb13"}, {0x8e, 0xf1, 0x300, 0x3, 0x3, "6ababd1d2d0caecaf08d2f7c00b8aad9ccafad0bb149d19e20a9b264e38b1163dc122e9344f282f7f02f95c6c34e2246752e7c0abc0febe97cffe719324d2e3d5a68250e80c215b096a815720149a009877b222bf9eda5c6f441fd7a7b057433777c46ec32dd0bcf304ef59fb054abc3cdcd3884b0f6e06cd449fe4dae24"}, {0x106, 0xffff, 0x2, 0x6, 0xfffffffffffffffa, "bc3f6dbe1d34007db5918c945b916c7be83c089eb45b8e9882ded2db52c07d4be2fb594a14d3507767501574261eeb75ac2aad24fa601697c6ea27925c53737d5bad72374e4b5f4947a6989d6ffcf22dec69380013423f61085b57c1d67a341bf6144611c2406f260f9f043c735089e3dc8fd60694b0a0d044039cbb2d38a052d0c0ebb281c3afc56e05b29a759897e192291b37d1db49a411425c7340cb203a6ea4489c3124acfa4291bdeb3263ba88770aa99a420fa43e64e597ee65fe3637dfbf7ab26ef0a3f519482258d465b8e8bbda39eceac3c7a4ec3e550f31909736c243f30508f3573f22e76d0d415eeb9e19301031d750"}], 0x2f1}, {&(0x7f0000001000-0x29a)=[{0x91, 0x80000001, 0xc04, 0x8000, 0x80000001, "4aa35d1254373a22e9512dc85836636808bce56d99f7c24e353976ee92e9d794093edf0dbffeff4440fbf56273428204317818822857d57fe63eb3fe0d213b8bc703fff69cbb04277cfe6fafa9c8537d3740b978c73589182ddd463ad8b2de0c2510d5f91e895a57bfa71bdf30a6743cede154c30339f9677eaa6b51391d2317af"}, {0xb5, 0x1, 0x1, 0x8, 0x7, "92730dbf9e026a3e88c4edc74aa72c196c4e01b556626e9e4469095cbbba07a3f04d7563d503ff6dcfb8f4550ccc297d5e7ed3721901cc32a01565f46d240a8a0b6c7909cfca67720da2c6c9063575fcf823ec06e5368f53b68d68a8d63ffc1b534f8f925deaf0f62f1f98cfe7656647460dfaafe8fa755d1f19365355a12610989f0fcfb33f961dc8aa0f44694074d7ed346339a717faf90743271799cd747612290b0cac"}, {0x5c, 0x0, 0x4, 0x201, 0xa0, "8ff9a8fb037cab2e4899820e6bea97e5d1f13292cf52fba507646aed5a911cd40c2921f9604d606e9ece7ede92918c5b5498364ef7eb89ed618cc4d21de8ace6905a66fbedbe88c988b26e35"}, {0x10, 0xffffffffffffff81, 0x8, 0x2, 0xffffffffffff7b6d, ""}, {0xe8, 0x0, 0xf04, 0x1f, 0x81, "24b37765c982a78f0fa4f6e6d4af7ebb65430a329348116a11a26799a8f3657ec4d069f30d3f04725170810cbf92b4752a4c50ee2d67fe57499ad357eb3c2743d240cedb1508d4118d418bead73c8c4d24c37027b5ff6c52376e48682f2c564aa6b55859e4a55d5727cba4c41d8b54a8ce66f9168745507450188c42c777e0f34fc92ef5deee056dced99d060d58b3e55131eab0d6c321fa4ed9ae18006849bef43c9ee0dced7af36815680106204b60b3dfca734106d40e5f85114ed11f425f6d48ca77d02b0ae872575d65f18a798cf005b0dde4d27257"}], 0x29a}], 0x7, &(0x7f0000001000-0x98)=[@rights={0x18, 0x1, 0x1, [r0]}, @rights={0x20, 0x1, 0x1, [r0, r0, r0, r0]}, @rights={0x18, 0x1, 0x1, [r0]}, @rights={0x28, 0x1, 0x1, [r0, r0, r0, r0, r0]}, @cred={0x20, 0x1, 0x2, r2, r3, r4}], 0x98, 0x0}, 0x0)
sendto$ipx(r1, &(0x7f0000000000)="9bc02d5914725935f589782ab920a722bc0b24721731d6", 0x17, 0x0, &(0x7f0000002000-0x10)={0x4, 0xff, 0x1ff, "7ec97bc97388", 0x2, 0x0}, 0x10)
r5 = socket(0x5, 0x8000a, 0x802)
mmap(&(0x7f0000002000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_dccp_int(r5, 0x21, 0x5, &(0x7f0000002000)=0x0, &(0x7f0000000000)=0x4)
mmap(&(0x7f0000003000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockname(r5, &(0x7f0000000000)=@ipx={0x0, 0x0, 0x0, "000000000000", 0x0, 0x0}, &(0x7f0000003000)=0x10)
mmap(&(0x7f0000004000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$KVM_ASSIGN_DEV_IRQ(r1, 0x4040ae70, &(0x7f0000004000)={0x7, 0x5, 0x1000, 0x100})
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000005000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_DISABLE_FRAGMENTS(r1, 0x84, 0x8, &(0x7f0000006000-0x4)=0x0, &(0x7f0000005000)=0x4)
mmap(&(0x7f0000006000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
ioctl$SNDRV_SEQ_IOCTL_UNSUBSCRIBE_PORT(r1, 0x40505331, &(0x7f0000007000-0x50)={{0x9f, 0x3}, {0xfffffffffffffffa, 0x80000001}, 0x6, 0x4, 0x20, [0x0, 0x0, 0x0], [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
2017/12/15 11:53:27 executing program 0:
mmap(&(0x7f0000000000/0xfce000)=nil, 0xfce000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = socket$inet6(0xa, 0x8000000000000001, 0x8010802000000084)
mmap(&(0x7f0000fce000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fcf000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
bind$inet6(r0, &(0x7f0000fcf000)={0xa, 0x0, 0x1, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x20000000023c}, 0x1c)
r1 = socket$bt_l2cap(0x1f, 0x3, 0x0)
mmap(&(0x7f0000fce000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$bt_l2cap_L2CAP_OPTIONS(r1, 0x6, 0x1, &(0x7f00007b4000-0xc)={0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000058000-0x4)=0xc)
mmap(&(0x7f0000fd1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_MAXSEG(0xffffffffffffffff, 0x84, 0xd, &(0x7f0000fd2000-0x8)=@assoc_value={<r2=>0x0, 0x80}, &(0x7f0000fd2000-0x2)=0x8)
getsockopt$inet_sctp6_SCTP_DEFAULT_SEND_PARAM(r0, 0x84, 0xa, &(0x7f0000ce4000-0x20)={0x81, 0x2, 0x1, 0x100000001, 0x3, 0x9, 0x1004005, 0x50, <r3=>r2}, &(0x7f0000fca000)=0x20)
socketpair(0x4, 0x7, 0x3aa8, &(0x7f000094a000)={<r4=>0x0, <r5=>0x0})
getsockopt$inet_sctp_SCTP_AUTH_ACTIVE_KEY(r4, 0x84, 0x18, &(0x7f0000e47000-0x6)={<r6=>r3, 0x136}, &(0x7f00002f6000-0x4)=0x6)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_ENABLE_STREAM_RESET(r0, 0x84, 0x76, &(0x7f0000fd1000-0x8)={r6, 0x0}, &(0x7f0000fd3000)=0x8)
mmap(&(0x7f0000fd2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x100032, r1, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd4000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd4000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp_SCTP_ENABLE_STREAM_RESET(0xffffffffffffffff, 0x84, 0x76, &(0x7f0000fd4000-0x8)={r3, 0x6}, &(0x7f0000ac0000)=0x8)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, r0, 0x3c)
mmap(&(0x7f0000557000/0x2000)=nil, 0x2000, 0x3, 0x32, 0xffffffffffffffff, 0x3)
mmap(&(0x7f0000fd5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet6_tcp_TCP_REPAIR_WINDOW(r5, 0x6, 0x1d, &(0x7f000045a000-0x14)={0x0, 0x0, 0x0, 0x0, 0x0}, &(0x7f0000fd7000-0x4)=0x14)
mmap(&(0x7f0000fd6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_PRIMARY_ADDR(r0, 0x84, 0x6, &(0x7f0000b20000-0x8c)={r6, @in6={{0xa, 0x3, 0x3, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x7f}, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}}, &(0x7f00009a9000-0x4)=0x8c)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd2000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
setsockopt$inet6_buf(r0, 0x29, 0xd9, &(0x7f0000fd2000)="99daa6d752cb8bb74d743618237f86e4779fa3cb220e4978e29ccd43d9d34959cddc25006080d87293aaaf0085ac2b21ca490e6767a776aaa00ef4804b063f9340701004677992baeef27b10c27a43547f02873fcde7aa706f0088b22396cc37637c77bb30e3952264f5e291a83d5ce75ed22828389ff1acb8d3de3175c427e3094c95655c480a0eecd447ac1b61a8eaa7c714c73702127c7d9dde7a303b692c6490000000000000000000de61d21d", 0xaf)
socketpair(0x2, 0x7, 0x405, &(0x7f00006f2000-0x3)={<r7=>0x0, 0x0})
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd5000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
getsockopt$inet_sctp6_SCTP_RECVNXTINFO(r4, 0x84, 0x21, &(0x7f0000fd6000-0x4)=0x0, &(0x7f0000fd3000)=0x4)
sendto$inet6(r0, &(0x7f0000d2a000-0x1)="10", 0x1, 0x0, &(0x7f0000b4b000)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x9dd7}, 0x1c)
sendto$inet6(r0, &(0x7f0000a76000-0xdb)="ab", 0x1, 0x4004004, &(0x7f000046c000)={0xa, 0x0, 0x3, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x2}, 0x1c)
mmap(&(0x7f0000fd7000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd8000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
accept4(r5, &(0x7f0000fcd000)=@rc={0x0, {0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0}, &(0x7f00004ee000)=0x9, 0x80000)
r8 = accept4(r7, &(0x7f0000fd3000)=@hci={0x0, 0x0, 0x0}, &(0x7f0000252000)=0x6, 0x90080000)
ioctl$sock_SIOCGSKNS(r8, 0x894c, &(0x7f0000fcd000)=0x7d4)
sendto$inet6(r0, &(0x7f0000c9c000-0x1)="c3", 0x34000, 0x0, &(0x7f0000a46000)={0xa, 0x0, 0x0, @loopback={0x0, 0x1}, 0x0}, 0x1c)
shutdown(r0, 0x1)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd0000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd1000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd3000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000fd6000/0x1000)=nil, 0x1000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
socketpair$ipx(0x4, 0x2, 0x0, &(0x7f0000fd7000-0x8)={0x0, 0x0})
2017/12/15 11:53:27 executing program 6:
mmap(&(0x7f0000000000/0x5dc000)=nil, 0x5dc000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r0 = perf_event_open(&(0x7f000001d000)={0x2, 0x78, 0xe3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80000040fe, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0xffffffffffffffff, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
mmap(&(0x7f0000000000/0xfff000)=nil, 0xfff000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
r1 = openat$ptmx(0xffffffffffffff9c, &(0x7f00002c2000-0xa)="2f6465762f70746d7800", 0x0, 0x0)
mmap(&(0x7f0000000000/0x1f000)=nil, 0x1f000, 0x3, 0x32, 0xffffffffffffffff, 0x0)
pipe2(&(0x7f00009b1000)={<r2=>0x0, <r3=>0x0}, 0x800)
ioctl$KVM_GET_EMULATED_CPUID(r3, 0xc008ae09, &(0x7f0000e2e000)="00000000")
ioctl$KVM_X86_SETUP_MCE(r2, 0x4008ae9c, &(0x7f0000069000)={0x1e, 0x1, 0x81, 0x0})
modify_ldt$read_default(0x2, &(0x7f000083f000)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x4d)
r4 = getpgrp(0x0)
getsockopt$inet_sctp_SCTP_AUTOCLOSE(r2, 0x84, 0x4, &(0x7f0000358000-0x4)=0x0, &(0x7f00005ed000)=0x4)
ioctl$DRM_IOCTL_RES_CTX(r2, 0xc0086426, &(0x7f0000d8f000)={0x4, &(0x7f0000405000-0x20)=[{0x0, 0x0}, {0x0, 0x0}, {<r5=>0x0, 0x0}, {0x0, 0x0}]})
ioctl$DRM_IOCTL_GET_CTX(r3, 0xc0086423, &(0x7f0000582000)={r5, 0x3})
process_vm_readv(r4, &(0x7f000001e000-0x80)=[{&(0x7f0000ca5000)="00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6d}], 0x1, &(0x7f000001e000-0x60)=[{&(0x7f000001e000-0x6d)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x6e}], 0x1, 0x0)
ioctl$TIOCSWINSZ(0xffffffffffffffff, 0x5414, &(0x7f000064c000)={0x0, 0x0, 0x0, 0x0})
ioctl$TIOCGWINSZ(r1, 0x5413, &(0x7f00000fa000-0x8)={0x0, 0x0, 0x0, 0x0})
ioctl$TUNGETIFF(r2, 0x800454d2, &(0x7f0000522000-0x4)=0x0)
r6 = syz_open_dev$sg(&(0x7f0000ba1000-0x9)="2f6465762f73672300", 0x8000, 0x40000000000)
process_vm_readv(0x0, &(0x7f00000e6000)=[], 0x0, &(0x7f000093d000)=[{&(0x7f0000816000-0x9b)="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0x9b}], 0x1, 0x0)
ioctl$sock_ipx_SIOCIPXNCPCONN(r6, 0x89e3, &(0x7f000085a000-0x2)=0x1)
inotify_add_watch(r0, &(0x7f0000915000)="2e2f66696c653000", 0x4)
gettid()
getsockopt$inet_sctp6_SCTP_SOCKOPT_CONNECTX3(r6, 0x84, 0x6f, &(0x7f0000063000-0x10)={<r7=>0x0, 0x8, &(0x7f00004dd000)=[@in={0x2, 0x2, @multicast2=0xe0000002, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, @in6={0xa, 0x2, 0x9e2, @loopback={0x0, 0x1}, 0x1}, @in6={0xa, 0x3, 0xffffffffffff8001, @loopback={0x0, 0x1}, 0x0}, @in6={0xa, 0x1, 0xb17e, @empty={[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]}, 0x7fffffff}, @in6={0xa, 0x0, 0x5, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0x1000}, @in6={0xa, 0x2, 0x81, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x488}, @in6={0xa, 0x1, 0x7000000000000000, @local={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xaa}, 0x1}, @in6={0xa, 0x0, 0xb42, @remote={0xfe, 0x80, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0], 0x0, 0xbb}, 0xffff}]}, &(0x7f00002e2000-0x4)=0x10)
getsockopt$inet_sctp6_SCTP_RESET_STREAMS(r2, 0x84, 0x77, &(0x7f0000604000-0x8)={r7, 0x2000000000000000}, &(0x7f0000fb7000-0x4)=0x8)
perf_event_open(&(0x7f0000075000-0x44)={0x4, 0x78, 0x0, 0x0, 0x3, 0x1, 0x0, 0x0, 0x20080, 0x0, 0xfe, 0xfffffffffffffffc, 0xfffffffffffffffb, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4, 0x0, 0x3, 0xfffffffffffffffe, 0x0, 0x0, 0x0, 0x0, 0x0}, 0x0, 0x0, r6, 0x4)
r8 = syz_open_dev$sndseq(&(0x7f0000142000-0xd)="2f6465762f736e642f73657100", 0x0, 0x4)
ioctl$SNDRV_SEQ_IOCTL_CREATE_QUEUE(r8, 0xc08c5332, &(0x7f0000cb2000-0x8c)={0x0, 0x0, 0x0, "71756575653100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", 0xfffffffffffffffc, [0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0]})
ioctl$sock_inet_SIOCGIFBRDADDR(r6, 0x8919, &(0x7f0000d44000)={@generic="f084000055c0d6bc3ddaa11bfffc7299", @ifru_flags=0x400})
openat$autofs(0xffffffffffffff9c, &(0x7f00000f1000)="2f6465762f6175746f667300", 0x2000, 0x0)
[ 51.505246] BUG: unable to handle kernel NULL pointer dereference at (null)
[ 51.513275] IP: tc_fill_qdisc+0xc8/0x4b0
[ 51.517316] PGD 1dc5d4067 P4D 1dc5d4067 PUD 1db5fa067 PMD 0
[ 51.523109] Oops: 0000 [#1] SMP
[ 51.526379] Dumping ftrace buffer:
[ 51.529898] (ftrace buffer empty)
[ 51.533585] Modules linked in:
[ 51.536764] CPU: 0 PID: 7609 Comm: syz-executor4 Not tainted 4.15.0-rc3-next-20171214+ #67
[ 51.545229] Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
[ 51.554559] RIP: 0010:tc_fill_qdisc+0xc8/0x4b0
[ 51.559118] RSP: 0018:ffffc90000ea38c8 EFLAGS: 00010212
[ 51.564448] RAX: 0000000000000000 RBX: ffff880216ac3c00 RCX: ffffffff8212563c
[ 51.571687] RDX: 0000000000000a02 RSI: ffffc90004f53000 RDI: ffff8801dc6a20b0
[ 51.578927] RBP: ffffc90000ea3970 R08: 0000000000000014 R09: ffff8801dc6a20b0
[ 51.586163] R10: ffffc90000ea37d8 R11: 0000000000000002 R12: ffff880214161b00
[ 51.593400] R13: ffff8801dc6a208c R14: 0000000000000000 R15: 0000000000000002
[ 51.600814] FS: 00007f6db5bc5700(0000) GS:ffff88021fc00000(0000) knlGS:0000000000000000
[ 51.609007] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 51.614857] CR2: 0000000000000000 CR3: 00000001dc75a000 CR4: 00000000001426f0
[ 51.622097] DR0: 0000000020000000 DR1: 0000000000000000 DR2: 0000000000000000
[ 51.629334] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600
[ 51.636568] Call Trace:
[ 51.639142] tc_dump_qdisc_root+0x1f1/0x220
[ 51.643439] tc_dump_qdisc+0x1a1/0x280
[ 51.647311] netlink_dump+0x14e/0x360
[ 51.651085] __netlink_dump_start+0x1bb/0x210
[ 51.655551] rtnetlink_rcv_msg+0x44f/0x5d0
[ 51.659760] ? tclass_notify.constprop.31+0xe0/0xe0
[ 51.664741] ? tclass_notify.constprop.31+0xe0/0xe0
[ 51.669727] ? validate_linkmsg+0x470/0x470
[ 51.674020] netlink_rcv_skb+0x92/0x160
[ 51.677968] rtnetlink_rcv+0x1c/0x20
[ 51.681648] netlink_unicast+0x1d4/0x290
[ 51.685680] netlink_sendmsg+0x345/0x470
[ 51.689722] sock_sendmsg+0x51/0x70
[ 51.693319] ___sys_sendmsg+0x35e/0x3b0
[ 51.697267] ? find_held_lock+0x35/0xa0
[ 51.701211] ? __fget+0x137/0x290
[ 51.704639] ? __fget+0x160/0x290
[ 51.708078] ? __fget_light+0x93/0xa0
[ 51.711846] ? __fdget+0x18/0x20
[ 51.715185] __sys_sendmsg+0x50/0x90
[ 51.718864] ? __sys_sendmsg+0x50/0x90
[ 51.722733] SyS_sendmsg+0x2d/0x50
[ 51.726249] entry_SYSCALL_64_fastpath+0x1f/0x96
[ 51.730971] RIP: 0033:0x452a39
[ 51.734127] RSP: 002b:00007f6db5bc4c58 EFLAGS: 00000212 ORIG_RAX: 000000000000002e
[ 51.741801] RAX: ffffffffffffffda RBX: 0000000000758020 RCX: 0000000000452a39
[ 51.749037] RDX: 0000000000000000 RSI: 000000002061efc8 RDI: 000000000000001c
[ 51.756273] RBP: 0000000000000343 R08: 0000000000000000 R09: 0000000000000000
[ 51.763509] R10: 0000000000000000 R11: 0000000000000212 R12: 00000000006f2ee8
[ 51.770749] R13: 00000000ffffffff R14: 00007f6db5bc56d4 R15: 0000000000000000
[ 51.778087] Code: 41 b8 14 00 00 00 4c 89 e7 e8 05 17 01 00 48 85 c0 49 89 c5 0f 84 cb 02 00 00 e8 04 4d 19 ff 41 c7 45 10 00 00 00 00 48 8b 43 40 <48> 8b 00 8b 80 08 01 00 00 45 89 75 1c 41 89 45 14 8b 43 38 41
[ 51.797221] RIP: tc_fill_qdisc+0xc8/0x4b0 RSP: ffffc90000ea38c8
[ 51.803242] CR2: 0000000000000000
[ 51.806793] ---[ end trace dffd1876816a33a6 ]---
[ 51.815572] Kernel panic - not syncing: Fatal exception
[ 51.821291] Dumping ftrace buffer:
[ 51.824798] (ftrace buffer empty)
[ 51.828472] Kernel Offset: disabled
[ 51.832065] Rebooting in 86400 seconds..
^ permalink raw reply
* Re: [trivial PATCH] treewide: Align function definition open/close braces
From: Mauro Carvalho Chehab @ 2017-12-19 13:04 UTC (permalink / raw)
To: Joe Perches
Cc: Jiri Kosina, Linus Torvalds, linux-kernel, linux-acpi, amd-gfx,
dri-devel, linux-media, MPT-FusionLinux.pdl, linux-scsi, netdev,
linux-wireless, acpi4asus-user, platform-driver-x86, linux-rtc,
linux-fsdevel, ocfs2-devel, linux-xfs, linux-audit, alsa-devel,
linuxppc-dev
In-Reply-To: <1513556924.31581.51.camel@perches.com>
Em Sun, 17 Dec 2017 16:28:44 -0800
Joe Perches <joe@perches.com> escreveu:
> Some functions definitions have either the initial open brace and/or
> the closing brace outside of column 1.
>
> Move those braces to column 1.
>
> This allows various function analyzers like gnu complexity to work
> properly for these modified functions.
>
> Miscellanea:
>
> o Remove extra trailing ; and blank line from xfs_agf_verify
>
> Signed-off-by: Joe Perches <joe@perches.com>
For the media patch:
Acked-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
> ---
> git diff -w shows no difference other than the above 'Miscellanea'
>
> (this is against -next, but it applies against Linus' tree
> with a couple offsets)
>
> arch/x86/include/asm/atomic64_32.h | 2 +-
> drivers/acpi/custom_method.c | 2 +-
> drivers/acpi/fan.c | 2 +-
> drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
> drivers/media/i2c/msp3400-kthreads.c | 2 +-
> drivers/message/fusion/mptsas.c | 2 +-
> drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c | 2 +-
> drivers/net/wireless/ath/ath9k/xmit.c | 2 +-
> drivers/platform/x86/eeepc-laptop.c | 2 +-
> drivers/rtc/rtc-ab-b5ze-s3.c | 2 +-
> drivers/scsi/dpt_i2o.c | 2 +-
> drivers/scsi/sym53c8xx_2/sym_glue.c | 2 +-
> fs/locks.c | 2 +-
> fs/ocfs2/stack_user.c | 2 +-
> fs/xfs/libxfs/xfs_alloc.c | 5 ++---
> fs/xfs/xfs_export.c | 2 +-
> kernel/audit.c | 6 +++---
> kernel/trace/trace_printk.c | 4 ++--
> lib/raid6/sse2.c | 14 +++++++-------
> sound/soc/fsl/fsl_dma.c | 2 +-
> 20 files changed, 30 insertions(+), 31 deletions(-)
>
> diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
> index 97c46b8169b7..d4d4883080fa 100644
> --- a/arch/x86/include/asm/atomic64_32.h
> +++ b/arch/x86/include/asm/atomic64_32.h
> @@ -122,7 +122,7 @@ static inline long long atomic64_read(const atomic64_t *v)
> long long r;
> alternative_atomic64(read, "=&A" (r), "c" (v) : "memory");
> return r;
> - }
> +}
>
> /**
> * atomic64_add_return - add and return
> diff --git a/drivers/acpi/custom_method.c b/drivers/acpi/custom_method.c
> index c68e72414a67..e967c1173ba3 100644
> --- a/drivers/acpi/custom_method.c
> +++ b/drivers/acpi/custom_method.c
> @@ -94,7 +94,7 @@ static void __exit acpi_custom_method_exit(void)
> {
> if (cm_dentry)
> debugfs_remove(cm_dentry);
> - }
> +}
>
> module_init(acpi_custom_method_init);
> module_exit(acpi_custom_method_exit);
> diff --git a/drivers/acpi/fan.c b/drivers/acpi/fan.c
> index 6cf4988206f2..3563103590c6 100644
> --- a/drivers/acpi/fan.c
> +++ b/drivers/acpi/fan.c
> @@ -219,7 +219,7 @@ fan_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
> return fan_set_state_acpi4(device, state);
> else
> return fan_set_state(device, state);
> - }
> +}
>
> static const struct thermal_cooling_device_ops fan_cooling_ops = {
> .get_max_state = fan_get_max_state,
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index d1488d5ee028..1e0d1e7c5324 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -461,7 +461,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
> ******************************************************************************/
>
> struct dc *dc_create(const struct dc_init_data *init_params)
> - {
> +{
> struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
> unsigned int full_pipe_count;
>
> diff --git a/drivers/media/i2c/msp3400-kthreads.c b/drivers/media/i2c/msp3400-kthreads.c
> index 4dd01e9f553b..dc6cb8d475b3 100644
> --- a/drivers/media/i2c/msp3400-kthreads.c
> +++ b/drivers/media/i2c/msp3400-kthreads.c
> @@ -885,7 +885,7 @@ static int msp34xxg_modus(struct i2c_client *client)
> }
>
> static void msp34xxg_set_source(struct i2c_client *client, u16 reg, int in)
> - {
> +{
> struct msp_state *state = to_state(i2c_get_clientdata(client));
> int source, matrix;
>
> diff --git a/drivers/message/fusion/mptsas.c b/drivers/message/fusion/mptsas.c
> index 345f6035599e..69a62d23514b 100644
> --- a/drivers/message/fusion/mptsas.c
> +++ b/drivers/message/fusion/mptsas.c
> @@ -2968,7 +2968,7 @@ mptsas_exp_repmanufacture_info(MPT_ADAPTER *ioc,
> mutex_unlock(&ioc->sas_mgmt.mutex);
> out:
> return ret;
> - }
> +}
>
> static void
> mptsas_parse_device_info(struct sas_identify *identify,
> diff --git a/drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c b/drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
> index 3dd973475125..0ea141ece19e 100644
> --- a/drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
> +++ b/drivers/net/ethernet/qlogic/netxen/netxen_nic_init.c
> @@ -603,7 +603,7 @@ static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
>
> static int
> netxen_nic_validate_header(struct netxen_adapter *adapter)
> - {
> +{
> const u8 *unirom = adapter->fw->data;
> struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
> u32 fw_file_size = adapter->fw->size;
> diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
> index bd438062a6db..baedc7186b10 100644
> --- a/drivers/net/wireless/ath/ath9k/xmit.c
> +++ b/drivers/net/wireless/ath/ath9k/xmit.c
> @@ -196,7 +196,7 @@ ath_tid_pull(struct ath_atx_tid *tid)
> }
>
> return skb;
> - }
> +}
>
> static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
> {
> diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c
> index 5a681962899c..4c38904a8a32 100644
> --- a/drivers/platform/x86/eeepc-laptop.c
> +++ b/drivers/platform/x86/eeepc-laptop.c
> @@ -492,7 +492,7 @@ static void eeepc_platform_exit(struct eeepc_laptop *eeepc)
> * potentially bad time, such as a timer interrupt.
> */
> static void tpd_led_update(struct work_struct *work)
> - {
> +{
> struct eeepc_laptop *eeepc;
>
> eeepc = container_of(work, struct eeepc_laptop, tpd_led_work);
> diff --git a/drivers/rtc/rtc-ab-b5ze-s3.c b/drivers/rtc/rtc-ab-b5ze-s3.c
> index a319bf1e49de..ef5c16dfabfa 100644
> --- a/drivers/rtc/rtc-ab-b5ze-s3.c
> +++ b/drivers/rtc/rtc-ab-b5ze-s3.c
> @@ -648,7 +648,7 @@ static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
> ret);
>
> return ret;
> - }
> +}
>
> /* Enable or disable battery low irq generation */
> static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
> diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c
> index fd172b0890d3..a00d822e3142 100644
> --- a/drivers/scsi/dpt_i2o.c
> +++ b/drivers/scsi/dpt_i2o.c
> @@ -3524,7 +3524,7 @@ static int adpt_i2o_systab_send(adpt_hba* pHba)
> #endif
>
> return ret;
> - }
> +}
>
>
> /*============================================================================
> diff --git a/drivers/scsi/sym53c8xx_2/sym_glue.c b/drivers/scsi/sym53c8xx_2/sym_glue.c
> index 791a2182de53..7320d5fe4cbc 100644
> --- a/drivers/scsi/sym53c8xx_2/sym_glue.c
> +++ b/drivers/scsi/sym53c8xx_2/sym_glue.c
> @@ -1393,7 +1393,7 @@ static struct Scsi_Host *sym_attach(struct scsi_host_template *tpnt, int unit,
> scsi_host_put(shost);
>
> return NULL;
> - }
> +}
>
>
> /*
> diff --git a/fs/locks.c b/fs/locks.c
> index 21b4dfa289ee..d2399d001afe 100644
> --- a/fs/locks.c
> +++ b/fs/locks.c
> @@ -559,7 +559,7 @@ static const struct lock_manager_operations lease_manager_ops = {
> * Initialize a lease, use the default lock manager operations
> */
> static int lease_init(struct file *filp, long type, struct file_lock *fl)
> - {
> +{
> if (assign_type(fl, type) != 0)
> return -EINVAL;
>
> diff --git a/fs/ocfs2/stack_user.c b/fs/ocfs2/stack_user.c
> index dae9eb7c441e..d2fb97b173da 100644
> --- a/fs/ocfs2/stack_user.c
> +++ b/fs/ocfs2/stack_user.c
> @@ -398,7 +398,7 @@ static int ocfs2_control_do_setnode_msg(struct file *file,
>
> static int ocfs2_control_do_setversion_msg(struct file *file,
> struct ocfs2_control_message_setv *msg)
> - {
> +{
> long major, minor;
> char *ptr = NULL;
> struct ocfs2_control_private *p = file->private_data;
> diff --git a/fs/xfs/libxfs/xfs_alloc.c b/fs/xfs/libxfs/xfs_alloc.c
> index 0da80019a917..217108f765d5 100644
> --- a/fs/xfs/libxfs/xfs_alloc.c
> +++ b/fs/xfs/libxfs/xfs_alloc.c
> @@ -2401,7 +2401,7 @@ static bool
> xfs_agf_verify(
> struct xfs_mount *mp,
> struct xfs_buf *bp)
> - {
> +{
> struct xfs_agf *agf = XFS_BUF_TO_AGF(bp);
>
> if (xfs_sb_version_hascrc(&mp->m_sb)) {
> @@ -2449,8 +2449,7 @@ xfs_agf_verify(
> be32_to_cpu(agf->agf_refcount_level) > XFS_BTREE_MAXLEVELS))
> return false;
>
> - return true;;
> -
> + return true;
> }
>
> static void
> diff --git a/fs/xfs/xfs_export.c b/fs/xfs/xfs_export.c
> index fe1bfee35898..7d5c355d78b5 100644
> --- a/fs/xfs/xfs_export.c
> +++ b/fs/xfs/xfs_export.c
> @@ -122,7 +122,7 @@ xfs_nfs_get_inode(
> struct super_block *sb,
> u64 ino,
> u32 generation)
> - {
> +{
> xfs_mount_t *mp = XFS_M(sb);
> xfs_inode_t *ip;
> int error;
> diff --git a/kernel/audit.c b/kernel/audit.c
> index 227db99b0f19..d97e8f0f73ca 100644
> --- a/kernel/audit.c
> +++ b/kernel/audit.c
> @@ -443,15 +443,15 @@ static int audit_set_failure(u32 state)
> * Drop any references inside the auditd connection tracking struct and free
> * the memory.
> */
> - static void auditd_conn_free(struct rcu_head *rcu)
> - {
> +static void auditd_conn_free(struct rcu_head *rcu)
> +{
> struct auditd_connection *ac;
>
> ac = container_of(rcu, struct auditd_connection, rcu);
> put_pid(ac->pid);
> put_net(ac->net);
> kfree(ac);
> - }
> +}
>
> /**
> * auditd_set - Set/Reset the auditd connection state
> diff --git a/kernel/trace/trace_printk.c b/kernel/trace/trace_printk.c
> index ad1d6164e946..50f44b7b2b32 100644
> --- a/kernel/trace/trace_printk.c
> +++ b/kernel/trace/trace_printk.c
> @@ -196,7 +196,7 @@ struct notifier_block module_trace_bprintk_format_nb = {
> };
>
> int __trace_bprintk(unsigned long ip, const char *fmt, ...)
> - {
> +{
> int ret;
> va_list ap;
>
> @@ -214,7 +214,7 @@ int __trace_bprintk(unsigned long ip, const char *fmt, ...)
> EXPORT_SYMBOL_GPL(__trace_bprintk);
>
> int __ftrace_vbprintk(unsigned long ip, const char *fmt, va_list ap)
> - {
> +{
> if (unlikely(!fmt))
> return 0;
>
> diff --git a/lib/raid6/sse2.c b/lib/raid6/sse2.c
> index 1d2276b007ee..8191e1d0d2fb 100644
> --- a/lib/raid6/sse2.c
> +++ b/lib/raid6/sse2.c
> @@ -91,7 +91,7 @@ static void raid6_sse21_gen_syndrome(int disks, size_t bytes, void **ptrs)
>
> static void raid6_sse21_xor_syndrome(int disks, int start, int stop,
> size_t bytes, void **ptrs)
> - {
> +{
> u8 **dptr = (u8 **)ptrs;
> u8 *p, *q;
> int d, z, z0;
> @@ -200,9 +200,9 @@ static void raid6_sse22_gen_syndrome(int disks, size_t bytes, void **ptrs)
> kernel_fpu_end();
> }
>
> - static void raid6_sse22_xor_syndrome(int disks, int start, int stop,
> +static void raid6_sse22_xor_syndrome(int disks, int start, int stop,
> size_t bytes, void **ptrs)
> - {
> +{
> u8 **dptr = (u8 **)ptrs;
> u8 *p, *q;
> int d, z, z0;
> @@ -265,7 +265,7 @@ static void raid6_sse22_gen_syndrome(int disks, size_t bytes, void **ptrs)
>
> asm volatile("sfence" : : : "memory");
> kernel_fpu_end();
> - }
> +}
>
> const struct raid6_calls raid6_sse2x2 = {
> raid6_sse22_gen_syndrome,
> @@ -366,9 +366,9 @@ static void raid6_sse24_gen_syndrome(int disks, size_t bytes, void **ptrs)
> kernel_fpu_end();
> }
>
> - static void raid6_sse24_xor_syndrome(int disks, int start, int stop,
> +static void raid6_sse24_xor_syndrome(int disks, int start, int stop,
> size_t bytes, void **ptrs)
> - {
> +{
> u8 **dptr = (u8 **)ptrs;
> u8 *p, *q;
> int d, z, z0;
> @@ -471,7 +471,7 @@ static void raid6_sse24_gen_syndrome(int disks, size_t bytes, void **ptrs)
> }
> asm volatile("sfence" : : : "memory");
> kernel_fpu_end();
> - }
> +}
>
>
> const struct raid6_calls raid6_sse2x4 = {
> diff --git a/sound/soc/fsl/fsl_dma.c b/sound/soc/fsl/fsl_dma.c
> index 0c11f434a374..ec619f51d336 100644
> --- a/sound/soc/fsl/fsl_dma.c
> +++ b/sound/soc/fsl/fsl_dma.c
> @@ -879,7 +879,7 @@ static const struct snd_pcm_ops fsl_dma_ops = {
> };
>
> static int fsl_soc_dma_probe(struct platform_device *pdev)
> - {
> +{
> struct dma_object *dma;
> struct device_node *np = pdev->dev.of_node;
> struct device_node *ssi_np;
>
Thanks,
Mauro
^ permalink raw reply
* Reading header and payload at sock_recvmsg() and sock_sendmsg()
From: Stefan Geißler @ 2017-12-19 12:40 UTC (permalink / raw)
To: netdev
Hello netdev mailing list,
I am a PhD student from Germany and currently working on a project that
involves monitoring packets as they are passed from kernel space towards
user space applications. To achieve this, I applied the attached patch
to Kernel v4.4 and implemented the two functions below that are called
from - and with the parameters of - sock_recvmsg() and sock_sendmsg().
For every incoming packet I check if it belongs to the process I want to
monitor. If so, I get the header information as well as the payload and
save the current timestamp. Finally and set the current state to monitor
for the transmission of this packet. Then I compare the payloads of
outgoing packets until a match is found and print the time it took this
packet to travel through the user space.
However, I seem to be unable to get the socket information and data for
incoming packets in __i3_recv_monitor(), as the debug output is always
something like
Dec 19 08:49:51 localhost kernel: [413608.826373] [Packet received]
(13739)0.0.0.0;0;0.0.0.0;0;0;413595528124549
Dec 19 08:49:51 localhost kernel: [413608.831397] [Received data] (null)
Regarding outgoing packets in __i3_send_monitor(), I am at least able to
get the network information from the socket. My data pointer is empty as
well.
Dec 19 09:00:20 localhost kernel: [414238.178057] [Packet send]
(13739)192.168.200.19;36628;192.168.200.20;45110;6;414224859396846
Dec 19 09:00:20 localhost kernel: [414238.181216] [Send data] (null)
The context is that I want to monitor packet processing times of user
space applications that do not alter the payload before retransmitting
packets.
I was hoping that someone with more experience of the network stack
could point me towards what I am missing or doing wrong here.
I hope this is not totally the wrong place to ask such a question and
already thank you in advance!
Best regards,
Stefan
--------------------------------------------------------
void __i3_recv_monitor(struct socket * sock, struct msghdr * msg, size_t
len, int flags) {
int i = 0;
const struct iovec * iov;
if (unlikely(current_state == WAIT_FOR_RECV) && ktime_to_ns(recv_time)
== 0 && current->pid == vnf_pid) {
recv_time = ktime_get();
if (unlikely(debug>=2)) printk(KERN_INFO "[Packet received]
(%u)%pI4;%u;%pI4;%d;%d;%lld\n",
current->pid,
&sock->sk->sk_rcv_saddr,
sock->sk->sk_num,
&sock->sk->sk_daddr,
sock->sk->sk_dport,
sock->sk->sk_protocol,
ktime_to_ns(recv_time));
iov = msg->msg_iter.iov;
recv_data = (char *)kmalloc(iov->iov_len, GFP_KERNEL);
copy_from_user(recv_data, iov->iov_base, iov->iov_len);
printk(KERN_INFO "[Received data] %s\n", *recv_data);
current_state = WAIT_FOR_SEND;
}
}
void __i3_send_monitor(struct socket * sock, struct msghdr * msg) {
int i = 0;
const struct iovec * iov;
// I don't like this approach at all... think about something
different!!
if (unlikely(current_state == WAIT_FOR_SEND) && current->pid == vnf_pid) {
send_time = ktime_get();
if (unlikely(debug>=2)) printk(KERN_INFO "[Packet send]
(%u)%pI4;%u;%pI4;%d;%d;%lld\n",
current->pid,
&sock->sk->sk_rcv_saddr,
sock->sk->sk_num,
&sock->sk->sk_daddr,
sock->sk->sk_dport,
sock->sk->sk_protocol,
ktime_to_ns(send_time));
if (ktime_to_ns(recv_time) != 0) {
iov = msg->msg_iter.iov;
send_data = (char *)kmalloc(iov->iov_len, GFP_KERNEL);
copy_from_user(send_data, iov->iov_base, iov->iov_len);
printk(KERN_INFO "[Send data] %s\n", *send_data);
if (unlikely(*recv_data == *send_data)) {
proc_time = ktime_sub(send_time, recv_time);
if (unlikely(debug>=2)) printk(KERN_INFO "[Processing time] %lld\n",
ktime_to_ns(proc_time));
recv_time = ktime_set(0, 0);
current_state = SLEEP;
kfree(recv_data);
}
kfree(send_data);
}
}
}
--------------------------------------------------------
>From 7ef3d1efe53fbfb937e0c1e5200e1a8e40e220e9 Mon Sep 17 00:00:00 2001
From: Stefan Geissler <stefan.geissler@informatik.uni-wuerzburg.de>
Date: Tue, 14 Nov 2017 12:05:39 +0100
Subject: [PATCH 1/2] Added pointers to hook into socket calls for monitoring
reasons
---
net/socket.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/net/socket.c b/net/socket.c
index d730ef9..57ee946 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -113,6 +113,13 @@ unsigned int sysctl_net_busy_read __read_mostly;
unsigned int sysctl_net_busy_poll __read_mostly;
#endif
+// Setup pointer to fill with external wrapper functions to monitor sockets
+void (*__i3_send_monitor_ptr)(struct sock *, struct msghdr *);
+void (*__i3_recv_monitor_ptr)(struct sock *, struct msghdr *, size_t ,
int);
+EXPORT_SYMBOL(__i3_send_monitor_ptr);
+EXPORT_SYMBOL(__i3_recv_monitor_ptr);
+
+
static ssize_t sock_read_iter(struct kiocb *iocb, struct iov_iter *to);
static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from);
static int sock_mmap(struct file *file, struct vm_area_struct *vma);
@@ -615,6 +622,8 @@ static inline int sock_sendmsg_nosec(struct socket
*sock, struct msghdr *msg)
int sock_sendmsg(struct socket *sock, struct msghdr *msg)
{
+ if ((unlikely(__i3_send_monitor_ptr))
+ (*__i3_send_monitor_ptr)(sock, msg);
int err = security_socket_sendmsg(sock, msg,
msg_data_left(msg));
@@ -716,6 +725,8 @@ static inline int sock_recvmsg_nosec(struct socket
*sock, struct msghdr *msg,
int sock_recvmsg(struct socket *sock, struct msghdr *msg, size_t size,
int flags)
{
+ if (unlikely(__i3_recv_monitor_ptr))
+ (*__i3_recv_monitor_ptr)(sock, msg, size, flags);
int err = security_socket_recvmsg(sock, msg, size, flags);
return err ?: sock_recvmsg_nosec(sock, msg, size, flags);
@@ -2479,6 +2490,11 @@ EXPORT_SYMBOL(sock_unregister);
static int __init sock_init(void)
{
+ // Ensure pointers are set to NULL as long as no module is loaded.
+ // Unsetting the pointers has to be handled by the module upon exit.
+ __i3_recv_monitor_ptr = NULL;
+ __i3_send_monitor_ptr = NULL;
+
int err;
/*
* Initialize the network sysctl infrastructure.
--
2.7.4
>From 262cf38d4c576f6399851e6f5ecbd3a73a62d416 Mon Sep 17 00:00:00 2001
From: Stefan Geissler <stefan.geissler@informatik.uni-wuerzburg.de>
Date: Tue, 14 Nov 2017 14:04:56 +0100
Subject: [PATCH 2/2] Fixed ISO C90 Warnings
---
net/socket.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/net/socket.c b/net/socket.c
index 57ee946..2e840a8 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -114,8 +114,8 @@ unsigned int sysctl_net_busy_poll __read_mostly;
#endif
// Setup pointer to fill with external wrapper functions to monitor sockets
-void (*__i3_send_monitor_ptr)(struct sock *, struct msghdr *);
-void (*__i3_recv_monitor_ptr)(struct sock *, struct msghdr *, size_t ,
int);
+void (*__i3_send_monitor_ptr)(struct socket *, struct msghdr *);
+void (*__i3_recv_monitor_ptr)(struct socket *, struct msghdr *, size_t
, int);
EXPORT_SYMBOL(__i3_send_monitor_ptr);
EXPORT_SYMBOL(__i3_recv_monitor_ptr);
@@ -622,9 +622,10 @@ static inline int sock_sendmsg_nosec(struct socket
*sock, struct msghdr *msg)
int sock_sendmsg(struct socket *sock, struct msghdr *msg)
{
- if ((unlikely(__i3_send_monitor_ptr))
+ int err;
+ if (unlikely(__i3_send_monitor_ptr))
(*__i3_send_monitor_ptr)(sock, msg);
- int err = security_socket_sendmsg(sock, msg,
+ err = security_socket_sendmsg(sock, msg,
msg_data_left(msg));
return err ?: sock_sendmsg_nosec(sock, msg);
@@ -725,9 +726,10 @@ static inline int sock_recvmsg_nosec(struct socket
*sock, struct msghdr *msg,
int sock_recvmsg(struct socket *sock, struct msghdr *msg, size_t size,
int flags)
{
+ int err;
if (unlikely(__i3_recv_monitor_ptr))
(*__i3_recv_monitor_ptr)(sock, msg, size, flags);
- int err = security_socket_recvmsg(sock, msg, size, flags);
+ err = security_socket_recvmsg(sock, msg, size, flags);
return err ?: sock_recvmsg_nosec(sock, msg, size, flags);
}
@@ -2489,13 +2491,14 @@ void sock_unregister(int family)
EXPORT_SYMBOL(sock_unregister);
static int __init sock_init(void)
-{
+{
+ int err;
+
// Ensure pointers are set to NULL as long as no module is loaded.
// Unsetting the pointers has to be handled by the module upon exit.
__i3_recv_monitor_ptr = NULL;
__i3_send_monitor_ptr = NULL;
-
- int err;
+
/*
* Initialize the network sysctl infrastructure.
*/
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V4 14/26] pch_gbe: deprecate pci_get_bus_and_slot()
From: Andy Shevchenko @ 2017-12-19 13:24 UTC (permalink / raw)
To: Sinan Kaya, linux-pci, timur
Cc: linux-arm-msm, linux-arm-kernel, David S. Miller, Kees Cook,
Eric Dumazet, Tobias Klauser, open list:NETWORKING DRIVERS,
open list
In-Reply-To: <ef7d09ce-06af-ad3e-1048-3b413cc32e9b@codeaurora.org>
On Tue, 2017-12-19 at 07:17 -0500, Sinan Kaya wrote:
> On 12/19/2017 5:45 AM, Andy Shevchenko wrote:
> > On Tue, 2017-12-19 at 00:37 -0500, Sinan Kaya wrote:
> > >
> > pci_get_bus_and_slot() still might be useful for the wired devices
> > in
> > SoC where we know for sure that domain == 0.
> >
>
> Then hard code the domain number as 0 while calling
> pci_get_domain_bus_and_slot()
> if you know for sure that this device will never work on a non-zero
> domain.
Thanks for so detailed explanation.
Okay, I suppose you did estimate the amount of drivers / modules that
may look better with pci_get_bus_and_slot() and the result is comparable
small.
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* BUG: unable to handle kernel NULL pointer dereference in qdisc_match_from_root
From: syzbot @ 2017-12-19 13:43 UTC (permalink / raw)
To: davem, jhs, jiri, linux-kernel, netdev, syzkaller-bugs,
xiyou.wangcong
[-- Attachment #1: Type: text/plain, Size: 4185 bytes --]
Hello,
syzkaller hit the following crash on
6084b576dca2e898f5c101baef151f7bfdbb606d
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/master
compiler: gcc (GCC) 7.1.1 20170620
.config is attached
Raw console output is attached.
Unfortunately, I don't have any reproducer for this bug yet.
netlink: 1 bytes leftover after parsing attributes in process
`syz-executor6'.
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: qdisc_dev include/net/sch_generic.h:379 [inline]
IP: qdisc_match_from_root+0x19/0xd0 net/sched/sch_api.c:266
PGD 1db153067 P4D 1db153067 PUD 1da621067 PMD 0
Oops: 0000 [#1] SMP
Dumping ftrace buffer:
(ftrace buffer empty)
Modules linked in:
CPU: 0 PID: 15445 Comm: syz-executor5 Not tainted 4.15.0-rc3-next-20171214+
#67
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS
Google 01/01/2011
RIP: 0010:qdisc_dev include/net/sch_generic.h:379 [inline]
RIP: 0010:qdisc_match_from_root+0x19/0xd0 net/sched/sch_api.c:266
RSP: 0018:ffffc90000dafac8 EFLAGS: 00010216
RAX: 0000000000000000 RBX: ffff8801de311c00 RCX: ffffffff82123f94
RDX: 000000000000027f RSI: ffffc90004086000 RDI: ffff8801db4de400
RBP: ffffc90000dafae0 R08: 0000000000000000 R09: ffffc90000dafb30
R10: ffffc90000dafbb8 R11: 0000000000000004 R12: ffff8801db4de400
R13: 0000000005000000 R14: ffff8801dfa1e1c0 R15: 0000000005000000
FS: 00007f98eef31700(0000) GS:ffff88021fc00000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000000 CR3: 00000001da7ef000 CR4: 00000000001406f0
DR0: 0000000020000000 DR1: 0000000020000000 DR2: 0000000000000000
DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000600
Call Trace:
qdisc_lookup+0x2d/0x140 net/sched/sch_api.c:306
tc_get_qdisc+0xe2/0x380 net/sched/sch_api.c:1259
rtnetlink_rcv_msg+0x333/0x5d0 net/core/rtnetlink.c:4522
netlink_rcv_skb+0x92/0x160 net/netlink/af_netlink.c:2441
rtnetlink_rcv+0x1c/0x20 net/core/rtnetlink.c:4540
netlink_unicast_kernel net/netlink/af_netlink.c:1308 [inline]
netlink_unicast+0x1d4/0x290 net/netlink/af_netlink.c:1334
netlink_sendmsg+0x345/0x470 net/netlink/af_netlink.c:1897
sock_sendmsg_nosec net/socket.c:636 [inline]
sock_sendmsg+0x51/0x70 net/socket.c:646
sock_write_iter+0xa4/0x100 net/socket.c:915
call_write_iter include/linux/fs.h:1776 [inline]
new_sync_write fs/read_write.c:469 [inline]
__vfs_write+0x15b/0x1e0 fs/read_write.c:482
vfs_write+0xf0/0x230 fs/read_write.c:544
SYSC_write fs/read_write.c:589 [inline]
SyS_write+0x57/0xd0 fs/read_write.c:581
entry_SYSCALL_64_fastpath+0x1f/0x96
RIP: 0033:0x452a39
RSP: 002b:00007f98eef30c58 EFLAGS: 00000212 ORIG_RAX: 0000000000000001
RAX: ffffffffffffffda RBX: 0000000000758020 RCX: 0000000000452a39
RDX: 000000000000005e RSI: 0000000020fab000 RDI: 0000000000000013
RBP: 000000000000039b R08: 0000000000000000 R09: 0000000000000000
R10: 0000000000000000 R11: 0000000000000212 R12: 00000000006f3728
R13: 00000000ffffffff R14: 00007f98eef316d4 R15: 0000000000000000
Code: 49 c7 c4 28 76 ff 83 eb dd 66 0f 1f 84 00 00 00 00 00 55 48 89 e5 41
55 41 54 53 49 89 fc 41 89 f5 e8 ac 63 19 ff 49 8b 44 24 40 <48> 8b 18 48
85 db 0f 84 8b 00 00 00 e8 96 63 19 ff 41 f6 44 24
RIP: qdisc_dev include/net/sch_generic.h:379 [inline] RSP: ffffc90000dafac8
RIP: qdisc_match_from_root+0x19/0xd0 net/sched/sch_api.c:266 RSP:
ffffc90000dafac8
CR2: 0000000000000000
---[ end trace c23e90bc7d735c44 ]---
---
This bug is generated by a dumb bot. It may contain errors.
See https://goo.gl/tpsmEJ for details.
Direct all questions to syzkaller@googlegroups.com.
Please credit me with: Reported-by: syzbot <syzkaller@googlegroups.com>
syzbot will keep track of this bug report.
Once a fix for this bug is merged into any tree, reply to this email with:
#syz fix: exact-commit-title
To mark this as a duplicate of another syzbot report, please reply with:
#syz dup: exact-subject-of-another-report
If it's a one-off invalid bug report, please reply with:
#syz invalid
Note: if the crash happens again, it will cause creation of a new bug
report.
Note: all commands must start from beginning of the line in the email body.
[-- Attachment #2: config.txt --]
[-- Type: text/plain, Size: 126475 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# Linux/x86 4.15.0-rc2 Kernel Configuration
#
CONFIG_64BIT=y
CONFIG_X86_64=y
CONFIG_X86=y
CONFIG_INSTRUCTION_DECODER=y
CONFIG_OUTPUT_FORMAT="elf64-x86-64"
CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig"
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_MMU=y
CONFIG_ARCH_MMAP_RND_BITS_MIN=28
CONFIG_ARCH_MMAP_RND_BITS_MAX=32
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_HAS_CPU_RELAX=y
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
CONFIG_ZONE_DMA32=y
CONFIG_AUDIT_ARCH=y
CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_KASAN_SHADOW_OFFSET=0xdffffc0000000000
CONFIG_HAVE_INTEL_TXT=y
CONFIG_X86_64_SMP=y
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_PGTABLE_LEVELS=4
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
CONFIG_IRQ_WORK=y
CONFIG_BUILDTIME_EXTABLE_SORT=y
CONFIG_THREAD_INFO_IN_TASK=y
#
# General setup
#
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE=""
# CONFIG_COMPILE_TEST is not set
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_HAVE_KERNEL_LZ4=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
# CONFIG_KERNEL_LZ4 is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_POSIX_MQUEUE=y
CONFIG_POSIX_MQUEUE_SYSCTL=y
CONFIG_CROSS_MEMORY_ATTACH=y
CONFIG_USELIB=y
CONFIG_AUDIT=y
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
CONFIG_AUDITSYSCALL=y
CONFIG_AUDIT_WATCH=y
CONFIG_AUDIT_TREE=y
#
# IRQ subsystem
#
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_PENDING_IRQ=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_SPARSE_IRQ=y
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
CONFIG_CLOCKSOURCE_WATCHDOG=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
CONFIG_GENERIC_CMOS_UPDATE=y
#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ_COMMON=y
# CONFIG_HZ_PERIODIC is not set
CONFIG_NO_HZ_IDLE=y
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
#
# CPU/Task time and stats accounting
#
CONFIG_TICK_CPU_ACCOUNTING=y
# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
# CONFIG_IRQ_TIME_ACCOUNTING is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_CPU_ISOLATION is not set
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_RCU_EXPERT is not set
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
# CONFIG_TASKS_RCU is not set
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
# CONFIG_BUILD_BIN2C is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=12
CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
CONFIG_ARCH_SUPPORTS_INT128=y
CONFIG_NUMA_BALANCING=y
CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
CONFIG_CGROUPS=y
CONFIG_PAGE_COUNTER=y
CONFIG_MEMCG=y
CONFIG_MEMCG_SWAP=y
CONFIG_MEMCG_SWAP_ENABLED=y
CONFIG_BLK_CGROUP=y
# CONFIG_DEBUG_BLK_CGROUP is not set
CONFIG_CGROUP_WRITEBACK=y
CONFIG_CGROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_CFS_BANDWIDTH is not set
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_PROC_PID_CPUSET=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
# CONFIG_CGROUP_DEBUG is not set
CONFIG_SOCK_CGROUP_DATA=y
CONFIG_NAMESPACES=y
CONFIG_UTS_NS=y
CONFIG_IPC_NS=y
CONFIG_USER_NS=y
CONFIG_PID_NS=y
CONFIG_NET_NS=y
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_HAVE_UID16=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_HAVE_PCSPKR_PLATFORM=y
CONFIG_BPF=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_MULTIUSER=y
CONFIG_SGETMASK_SYSCALL=y
CONFIG_SYSFS_SYSCALL=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_FHANDLE=y
CONFIG_POSIX_TIMERS=y
CONFIG_PRINTK=y
CONFIG_PRINTK_NMI=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_PCSPKR_PLATFORM=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_FUTEX_PI=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_ADVISE_SYSCALLS=y
CONFIG_MEMBARRIER=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
CONFIG_KALLSYMS_BASE_RELATIVE=y
CONFIG_BPF_SYSCALL=y
CONFIG_USERFAULTFD=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
# CONFIG_PC104 is not set
#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_SLAB_MERGE_DEFAULT=y
# CONFIG_SLAB_FREELIST_RANDOM is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_CRASH_CORE=y
CONFIG_KEXEC_CORE=y
# CONFIG_OPROFILE is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_OPROFILE_NMI_TIMER=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
# CONFIG_STATIC_KEYS_SELFTEST is not set
CONFIG_OPTPROBES=y
CONFIG_UPROBES=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_KRETPROBES=y
CONFIG_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_OPTPROBES=y
CONFIG_HAVE_KPROBES_ON_FTRACE=y
CONFIG_HAVE_NMI=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
CONFIG_ARCH_HAS_SET_MEMORY=y
CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_HW_BREAKPOINT=y
CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
CONFIG_HAVE_USER_RETURN_NOTIFIER=y
CONFIG_HAVE_PERF_EVENTS_NMI=y
CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HAVE_PERF_REGS=y
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
CONFIG_HAVE_CMPXCHG_LOCAL=y
CONFIG_HAVE_CMPXCHG_DOUBLE=y
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_SECCOMP_FILTER=y
CONFIG_HAVE_GCC_PLUGINS=y
CONFIG_GCC_PLUGINS=y
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
CONFIG_GCC_PLUGIN_SANCOV=y
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
# CONFIG_GCC_PLUGIN_STRUCTLEAK is not set
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
CONFIG_HAVE_CC_STACKPROTECTOR=y
# CONFIG_CC_STACKPROTECTOR is not set
CONFIG_CC_STACKPROTECTOR_NONE=y
# CONFIG_CC_STACKPROTECTOR_REGULAR is not set
# CONFIG_CC_STACKPROTECTOR_STRONG is not set
CONFIG_THIN_ARCHIVES=y
CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
CONFIG_HAVE_ARCH_HUGE_VMAP=y
CONFIG_HAVE_ARCH_SOFT_DIRTY=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_MODULES_USE_ELF_RELA=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
CONFIG_HAVE_EXIT_THREAD=y
CONFIG_ARCH_MMAP_RND_BITS=28
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_STACK_VALIDATION=y
# CONFIG_HAVE_ARCH_HASH is not set
# CONFIG_ISA_BUS_API is not set
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_COMPAT_OLD_SIGACTION=y
# CONFIG_CPU_NO_EFFICIENT_FFS is not set
CONFIG_HAVE_ARCH_VMAP_STACK=y
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
CONFIG_STRICT_KERNEL_RWX=y
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
CONFIG_STRICT_MODULE_RWX=y
CONFIG_ARCH_HAS_REFCOUNT=y
CONFIG_REFCOUNT_FULL=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_MODVERSIONS is not set
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_MODULE_SIG is not set
# CONFIG_MODULE_COMPRESS is not set
# CONFIG_TRIM_UNUSED_KSYMS is not set
CONFIG_MODULES_TREE_LOOKUP=y
CONFIG_BLOCK=y
CONFIG_BLK_SCSI_REQUEST=y
CONFIG_BLK_DEV_BSG=y
CONFIG_BLK_DEV_BSGLIB=y
CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_BLK_DEV_ZONED=y
CONFIG_BLK_DEV_THROTTLING=y
# CONFIG_BLK_DEV_THROTTLING_LOW is not set
# CONFIG_BLK_CMDLINE_PARSER is not set
CONFIG_BLK_WBT=y
# CONFIG_BLK_WBT_SQ is not set
CONFIG_BLK_WBT_MQ=y
# CONFIG_BLK_DEBUG_FS is not set
# CONFIG_BLK_SED_OPAL is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_AIX_PARTITION is not set
CONFIG_OSF_PARTITION=y
CONFIG_AMIGA_PARTITION=y
# CONFIG_ATARI_PARTITION is not set
CONFIG_MAC_PARTITION=y
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
# CONFIG_LDM_PARTITION is not set
CONFIG_SGI_PARTITION=y
# CONFIG_ULTRIX_PARTITION is not set
CONFIG_SUN_PARTITION=y
CONFIG_KARMA_PARTITION=y
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
# CONFIG_CMDLINE_PARTITION is not set
CONFIG_BLOCK_COMPAT=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CFQ_GROUP_IOSCHED=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_MQ_IOSCHED_DEADLINE=y
CONFIG_MQ_IOSCHED_KYBER=y
CONFIG_IOSCHED_BFQ=y
CONFIG_BFQ_GROUP_IOSCHED=y
CONFIG_PREEMPT_NOTIFIERS=y
CONFIG_PADATA=y
CONFIG_ASN1=y
CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_FREEZER=y
#
# Processor type and features
#
CONFIG_ZONE_DMA=y
CONFIG_SMP=y
CONFIG_X86_FEATURE_NAMES=y
CONFIG_X86_FAST_FEATURE_TESTS=y
CONFIG_X86_X2APIC=y
CONFIG_X86_MPPARSE=y
# CONFIG_GOLDFISH is not set
# CONFIG_INTEL_RDT is not set
CONFIG_X86_EXTENDED_PLATFORM=y
# CONFIG_X86_NUMACHIP is not set
# CONFIG_X86_VSMP is not set
# CONFIG_X86_UV is not set
# CONFIG_X86_GOLDFISH is not set
# CONFIG_X86_INTEL_MID is not set
# CONFIG_X86_INTEL_LPSS is not set
# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
CONFIG_IOSF_MBI=y
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_HYPERVISOR_GUEST=y
CONFIG_PARAVIRT=y
CONFIG_PARAVIRT_DEBUG=y
CONFIG_PARAVIRT_SPINLOCKS=y
# CONFIG_QUEUED_LOCK_STAT is not set
CONFIG_XEN=y
CONFIG_XEN_PV=y
CONFIG_XEN_PV_SMP=y
CONFIG_XEN_DOM0=y
CONFIG_XEN_PVHVM=y
CONFIG_XEN_PVHVM_SMP=y
CONFIG_XEN_512GB=y
CONFIG_XEN_SAVE_RESTORE=y
# CONFIG_XEN_DEBUG_FS is not set
CONFIG_XEN_PVH=y
CONFIG_KVM_GUEST=y
# CONFIG_KVM_DEBUG_FS is not set
# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set
CONFIG_PARAVIRT_CLOCK=y
CONFIG_NO_BOOTMEM=y
# CONFIG_MK8 is not set
# CONFIG_MPSC is not set
# CONFIG_MCORE2 is not set
# CONFIG_MATOM is not set
CONFIG_GENERIC_CPU=y
CONFIG_X86_INTERNODE_CACHE_SHIFT=6
CONFIG_X86_L1_CACHE_SHIFT=6
CONFIG_X86_TSC=y
CONFIG_X86_CMPXCHG64=y
CONFIG_X86_CMOV=y
CONFIG_X86_MINIMUM_CPU_FAMILY=64
CONFIG_X86_DEBUGCTLMSR=y
# CONFIG_PROCESSOR_SELECT is not set
CONFIG_CPU_SUP_INTEL=y
CONFIG_CPU_SUP_AMD=y
CONFIG_CPU_SUP_CENTAUR=y
CONFIG_HPET_TIMER=y
CONFIG_HPET_EMULATE_RTC=y
CONFIG_DMI=y
# CONFIG_GART_IOMMU is not set
CONFIG_CALGARY_IOMMU=y
CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y
CONFIG_SWIOTLB=y
CONFIG_IOMMU_HELPER=y
# CONFIG_MAXSMP is not set
CONFIG_NR_CPUS=64
CONFIG_SCHED_SMT=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_MC_PRIO=y
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_PREEMPT_COUNT=y
CONFIG_X86_LOCAL_APIC=y
CONFIG_X86_IO_APIC=y
CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
CONFIG_X86_MCE=y
# CONFIG_X86_MCELOG_LEGACY is not set
CONFIG_X86_MCE_INTEL=y
CONFIG_X86_MCE_AMD=y
CONFIG_X86_MCE_THRESHOLD=y
CONFIG_X86_MCE_INJECT=y
CONFIG_X86_THERMAL_VECTOR=y
#
# Performance monitoring
#
CONFIG_PERF_EVENTS_INTEL_UNCORE=y
CONFIG_PERF_EVENTS_INTEL_RAPL=y
CONFIG_PERF_EVENTS_INTEL_CSTATE=y
# CONFIG_PERF_EVENTS_AMD_POWER is not set
# CONFIG_VM86 is not set
CONFIG_X86_16BIT=y
CONFIG_X86_ESPFIX64=y
CONFIG_X86_VSYSCALL_EMULATION=y
# CONFIG_I8K is not set
CONFIG_MICROCODE=y
CONFIG_MICROCODE_INTEL=y
CONFIG_MICROCODE_AMD=y
CONFIG_MICROCODE_OLD_INTERFACE=y
CONFIG_X86_MSR=y
CONFIG_X86_CPUID=y
# CONFIG_X86_5LEVEL is not set
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_X86_DIRECT_GBPAGES=y
CONFIG_ARCH_HAS_MEM_ENCRYPT=y
# CONFIG_AMD_MEM_ENCRYPT is not set
CONFIG_NUMA=y
CONFIG_AMD_NUMA=y
CONFIG_X86_64_ACPI_NUMA=y
CONFIG_NODES_SPAN_OTHER_NODES=y
# CONFIG_NUMA_EMU is not set
CONFIG_NODES_SHIFT=6
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_SPARSEMEM=y
CONFIG_NEED_MULTIPLE_NODES=y
CONFIG_HAVE_MEMORY_PRESENT=y
CONFIG_SPARSEMEM_EXTREME=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSEMEM_ALLOC_MEM_MAP_TOGETHER=y
CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_GENERIC_GUP=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
# CONFIG_MEMORY_HOTPLUG is not set
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
CONFIG_COMPACTION=y
CONFIG_MIGRATION=y
CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
CONFIG_ARCH_ENABLE_THP_MIGRATION=y
CONFIG_PHYS_ADDR_T_64BIT=y
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_MMU_NOTIFIER=y
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
# CONFIG_MEMORY_FAILURE is not set
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
CONFIG_ARCH_WANTS_THP_SWAP=y
CONFIG_THP_SWAP=y
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
# CONFIG_CMA is not set
# CONFIG_MEM_SOFT_DIRTY is not set
# CONFIG_ZPOOL is not set
# CONFIG_ZBUD is not set
# CONFIG_ZSMALLOC is not set
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT=y
# CONFIG_IDLE_PAGE_TRACKING is not set
CONFIG_ARCH_HAS_ZONE_DEVICE=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARCH_HAS_PKEYS=y
# CONFIG_PERCPU_STATS is not set
# CONFIG_GUP_BENCHMARK is not set
# CONFIG_X86_PMEM_LEGACY is not set
CONFIG_X86_CHECK_BIOS_CORRUPTION=y
CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y
CONFIG_X86_RESERVE_LOW=64
CONFIG_MTRR=y
CONFIG_MTRR_SANITIZER=y
CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
CONFIG_X86_PAT=y
CONFIG_ARCH_USES_PG_UNCACHED=y
CONFIG_ARCH_RANDOM=y
CONFIG_X86_SMAP=y
# CONFIG_X86_INTEL_UMIP is not set
CONFIG_X86_INTEL_MPX=y
CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
CONFIG_EFI=y
# CONFIG_EFI_STUB is not set
CONFIG_SECCOMP=y
# CONFIG_HZ_100 is not set
# CONFIG_HZ_250 is not set
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
CONFIG_SCHED_HRTICK=y
CONFIG_KEXEC=y
# CONFIG_KEXEC_FILE is not set
CONFIG_CRASH_DUMP=y
# CONFIG_KEXEC_JUMP is not set
CONFIG_PHYSICAL_START=0x1000000
CONFIG_RELOCATABLE=y
# CONFIG_RANDOMIZE_BASE is not set
CONFIG_PHYSICAL_ALIGN=0x200000
CONFIG_HOTPLUG_CPU=y
# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
# CONFIG_COMPAT_VDSO is not set
# CONFIG_LEGACY_VSYSCALL_NATIVE is not set
CONFIG_LEGACY_VSYSCALL_EMULATE=y
# CONFIG_LEGACY_VSYSCALL_NONE is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_MODIFY_LDT_SYSCALL=y
CONFIG_HAVE_LIVEPATCH=y
CONFIG_ARCH_HAS_ADD_PAGES=y
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
#
# Power management and ACPI options
#
CONFIG_ARCH_HIBERNATION_HEADER=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_SUSPEND_SKIP_SYNC is not set
CONFIG_HIBERNATE_CALLBACKS=y
CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION=""
CONFIG_PM_SLEEP=y
CONFIG_PM_SLEEP_SMP=y
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_ADVANCED_DEBUG is not set
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_PM_SLEEP_DEBUG=y
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_CLK=y
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
CONFIG_ACPI=y
CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
# CONFIG_ACPI_DEBUGGER is not set
CONFIG_ACPI_LPIT=y
CONFIG_ACPI_SLEEP=y
# CONFIG_ACPI_PROCFS_POWER is not set
CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
# CONFIG_ACPI_EC_DEBUGFS is not set
CONFIG_ACPI_AC=y
CONFIG_ACPI_BATTERY=y
CONFIG_ACPI_BUTTON=y
CONFIG_ACPI_VIDEO=y
CONFIG_ACPI_FAN=y
CONFIG_ACPI_DOCK=y
CONFIG_ACPI_CPU_FREQ_PSS=y
CONFIG_ACPI_PROCESSOR_CSTATE=y
CONFIG_ACPI_PROCESSOR_IDLE=y
CONFIG_ACPI_CPPC_LIB=y
CONFIG_ACPI_PROCESSOR=y
CONFIG_ACPI_HOTPLUG_CPU=y
# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
CONFIG_ACPI_THERMAL=y
CONFIG_ACPI_NUMA=y
# CONFIG_ACPI_CUSTOM_DSDT is not set
CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
CONFIG_ACPI_TABLE_UPGRADE=y
# CONFIG_ACPI_DEBUG is not set
# CONFIG_ACPI_PCI_SLOT is not set
CONFIG_X86_PM_TIMER=y
CONFIG_ACPI_CONTAINER=y
CONFIG_ACPI_HOTPLUG_IOAPIC=y
# CONFIG_ACPI_SBS is not set
# CONFIG_ACPI_HED is not set
# CONFIG_ACPI_CUSTOM_METHOD is not set
# CONFIG_ACPI_BGRT is not set
# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
# CONFIG_ACPI_NFIT is not set
CONFIG_HAVE_ACPI_APEI=y
CONFIG_HAVE_ACPI_APEI_NMI=y
# CONFIG_ACPI_APEI is not set
# CONFIG_DPTF_POWER is not set
# CONFIG_ACPI_EXTLOG is not set
# CONFIG_PMIC_OPREGION is not set
# CONFIG_ACPI_CONFIGFS is not set
# CONFIG_SFI is not set
#
# CPU Frequency scaling
#
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set
#
# CPU frequency scaling drivers
#
CONFIG_X86_INTEL_PSTATE=y
# CONFIG_X86_PCC_CPUFREQ is not set
CONFIG_X86_ACPI_CPUFREQ=y
CONFIG_X86_ACPI_CPUFREQ_CPB=y
# CONFIG_X86_POWERNOW_K8 is not set
# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
# CONFIG_X86_P4_CLOCKMOD is not set
#
# shared options
#
# CONFIG_X86_SPEEDSTEP_LIB is not set
#
# CPU Idle
#
CONFIG_CPU_IDLE=y
# CONFIG_CPU_IDLE_GOV_LADDER is not set
CONFIG_CPU_IDLE_GOV_MENU=y
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
# CONFIG_INTEL_IDLE is not set
#
# Bus options (PCI etc.)
#
CONFIG_PCI=y
CONFIG_PCI_DIRECT=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_XEN=y
CONFIG_PCI_DOMAINS=y
# CONFIG_PCI_CNB20LE_QUIRK is not set
CONFIG_PCIEPORTBUS=y
# CONFIG_HOTPLUG_PCI_PCIE is not set
CONFIG_PCIEAER=y
# CONFIG_PCIE_ECRC is not set
# CONFIG_PCIEAER_INJECT is not set
CONFIG_PCIEASPM=y
# CONFIG_PCIEASPM_DEBUG is not set
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
# CONFIG_PCIEASPM_PERFORMANCE is not set
CONFIG_PCIE_PME=y
# CONFIG_PCIE_DPC is not set
# CONFIG_PCIE_PTM is not set
CONFIG_PCI_BUS_ADDR_T_64BIT=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCI_QUIRKS=y
# CONFIG_PCI_DEBUG is not set
# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
# CONFIG_PCI_STUB is not set
CONFIG_XEN_PCIDEV_FRONTEND=y
CONFIG_PCI_ATS=y
CONFIG_PCI_LOCKLESS_CONFIG=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_PCI_LABEL=y
CONFIG_HOTPLUG_PCI=y
# CONFIG_HOTPLUG_PCI_ACPI is not set
# CONFIG_HOTPLUG_PCI_CPCI is not set
# CONFIG_HOTPLUG_PCI_SHPC is not set
#
# DesignWare PCI Core Support
#
# CONFIG_PCIE_DW_PLAT is not set
#
# PCI host controller drivers
#
# CONFIG_VMD is not set
#
# PCI Endpoint
#
CONFIG_PCI_ENDPOINT=y
# CONFIG_PCI_ENDPOINT_CONFIGFS is not set
# CONFIG_PCI_EPF_TEST is not set
#
# PCI switch controller drivers
#
# CONFIG_PCI_SW_SWITCHTEC is not set
# CONFIG_ISA_BUS is not set
CONFIG_ISA_DMA_API=y
CONFIG_AMD_NB=y
CONFIG_PCCARD=y
CONFIG_PCMCIA=y
CONFIG_PCMCIA_LOAD_CIS=y
CONFIG_CARDBUS=y
#
# PC-card bridges
#
CONFIG_YENTA=y
CONFIG_YENTA_O2=y
CONFIG_YENTA_RICOH=y
CONFIG_YENTA_TI=y
CONFIG_YENTA_ENE_TUNE=y
CONFIG_YENTA_TOSHIBA=y
# CONFIG_PD6729 is not set
# CONFIG_I82092 is not set
CONFIG_PCCARD_NONSTATIC=y
# CONFIG_RAPIDIO is not set
# CONFIG_X86_SYSFB is not set
#
# Executable file formats / Emulations
#
CONFIG_BINFMT_ELF=y
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_ELFCORE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_BINFMT_SCRIPT=y
# CONFIG_HAVE_AOUT is not set
CONFIG_BINFMT_MISC=y
CONFIG_COREDUMP=y
CONFIG_IA32_EMULATION=y
# CONFIG_IA32_AOUT is not set
# CONFIG_X86_X32 is not set
CONFIG_COMPAT_32=y
CONFIG_COMPAT=y
CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_X86_DEV_DMA_OPS=y
CONFIG_NET=y
CONFIG_NET_INGRESS=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_DIAG is not set
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
CONFIG_TLS=y
CONFIG_XFRM=y
CONFIG_XFRM_OFFLOAD=y
CONFIG_XFRM_ALGO=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
CONFIG_XFRM_MIGRATE=y
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
CONFIG_NET_KEY_MIGRATE=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
# CONFIG_IP_FIB_TRIE_STATS is not set
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
CONFIG_NET_IP_TUNNEL=y
CONFIG_IP_MROUTE=y
# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
# CONFIG_NET_IPVTI is not set
CONFIG_NET_UDP_TUNNEL=y
# CONFIG_NET_FOU is not set
# CONFIG_NET_FOU_IP_TUNNELS is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
CONFIG_TCP_CONG_CUBIC=y
# CONFIG_TCP_CONG_WESTWOOD is not set
# CONFIG_TCP_CONG_HTCP is not set
# CONFIG_TCP_CONG_HSTCP is not set
# CONFIG_TCP_CONG_HYBLA is not set
# CONFIG_TCP_CONG_VEGAS is not set
# CONFIG_TCP_CONG_NV is not set
# CONFIG_TCP_CONG_SCALABLE is not set
# CONFIG_TCP_CONG_LP is not set
# CONFIG_TCP_CONG_VENO is not set
# CONFIG_TCP_CONG_YEAH is not set
# CONFIG_TCP_CONG_ILLINOIS is not set
# CONFIG_TCP_CONG_DCTCP is not set
# CONFIG_TCP_CONG_CDG is not set
# CONFIG_TCP_CONG_BBR is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_TCP_MD5SIG=y
CONFIG_IPV6=y
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=y
CONFIG_INET6_ESP=y
CONFIG_INET6_ESP_OFFLOAD=y
# CONFIG_INET6_IPCOMP is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_ILA is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
CONFIG_INET6_TUNNEL=y
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
CONFIG_INET6_XFRM_MODE_TUNNEL=y
CONFIG_INET6_XFRM_MODE_BEET=y
# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
# CONFIG_IPV6_VTI is not set
CONFIG_IPV6_SIT=y
# CONFIG_IPV6_SIT_6RD is not set
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=y
# CONFIG_IPV6_FOU is not set
# CONFIG_IPV6_FOU_TUNNEL is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
CONFIG_IPV6_MROUTE=y
# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
# CONFIG_IPV6_PIMSM_V2 is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
CONFIG_NETLABEL=y
CONFIG_NETWORK_SECMARK=y
CONFIG_NET_PTP_CLASSIFY=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_INGRESS=y
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_NETLINK_LOG=y
CONFIG_NF_CONNTRACK=y
CONFIG_NF_LOG_COMMON=y
# CONFIG_NF_LOG_NETDEV is not set
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_PROCFS=y
CONFIG_NF_CONNTRACK_FTP=y
CONFIG_NF_CONNTRACK_IRC=y
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
CONFIG_NF_CONNTRACK_SIP=y
CONFIG_NF_CT_NETLINK=y
# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set
CONFIG_NF_NAT=y
CONFIG_NF_NAT_NEEDED=y
# CONFIG_NF_NAT_AMANDA is not set
CONFIG_NF_NAT_FTP=y
CONFIG_NF_NAT_IRC=y
CONFIG_NF_NAT_SIP=y
# CONFIG_NF_NAT_TFTP is not set
# CONFIG_NF_NAT_REDIRECT is not set
# CONFIG_NF_TABLES is not set
CONFIG_NETFILTER_XTABLES=y
#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
#
# Xtables targets
#
CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_NAT=y
# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set
CONFIG_NETFILTER_XT_TARGET_NFLOG=y
# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
#
# Xtables matches
#
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
CONFIG_NETFILTER_XT_MATCH_POLICY=y
CONFIG_NETFILTER_XT_MATCH_STATE=y
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_CONNTRACK_IPV4=y
# CONFIG_NF_SOCKET_IPV4 is not set
# CONFIG_NF_DUP_IPV4 is not set
CONFIG_NF_LOG_ARP=y
CONFIG_NF_LOG_IPV4=y
CONFIG_NF_REJECT_IPV4=y
CONFIG_NF_NAT_IPV4=y
CONFIG_NF_NAT_MASQUERADE_IPV4=y
# CONFIG_NF_NAT_PPTP is not set
# CONFIG_NF_NAT_H323 is not set
CONFIG_IP_NF_IPTABLES=y
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_NAT=y
CONFIG_IP_NF_TARGET_MASQUERADE=y
CONFIG_IP_NF_MANGLE=y
# CONFIG_IP_NF_RAW is not set
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV6=y
CONFIG_NF_CONNTRACK_IPV6=y
# CONFIG_NF_SOCKET_IPV6 is not set
# CONFIG_NF_DUP_IPV6 is not set
CONFIG_NF_REJECT_IPV6=y
CONFIG_NF_LOG_IPV6=y
CONFIG_IP6_NF_IPTABLES=y
CONFIG_IP6_NF_MATCH_IPV6HEADER=y
CONFIG_IP6_NF_FILTER=y
CONFIG_IP6_NF_TARGET_REJECT=y
CONFIG_IP6_NF_MANGLE=y
# CONFIG_IP6_NF_RAW is not set
# CONFIG_BRIDGE_NF_EBTABLES is not set
CONFIG_IP_DCCP=y
#
# DCCP CCIDs Configuration
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_TFRC_LIB=y
#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
# CONFIG_NET_DCCPPROBE is not set
CONFIG_IP_SCTP=y
# CONFIG_NET_SCTPPROBE is not set
# CONFIG_SCTP_DBG_OBJCNT is not set
CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
CONFIG_SCTP_COOKIE_HMAC_MD5=y
CONFIG_SCTP_COOKIE_HMAC_SHA1=y
CONFIG_RDS=y
CONFIG_RDS_TCP=y
# CONFIG_RDS_DEBUG is not set
CONFIG_TIPC=y
CONFIG_TIPC_MEDIA_UDP=y
CONFIG_ATM=y
CONFIG_ATM_CLIP=y
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=y
CONFIG_ATM_MPOA=y
CONFIG_ATM_BR2684=y
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_L2TP=y
# CONFIG_L2TP_DEBUGFS is not set
# CONFIG_L2TP_V3 is not set
CONFIG_STP=y
CONFIG_BRIDGE=y
CONFIG_BRIDGE_IGMP_SNOOPING=y
# CONFIG_BRIDGE_VLAN_FILTERING is not set
CONFIG_HAVE_NET_DSA=y
CONFIG_NET_DSA=y
CONFIG_VLAN_8021Q=y
# CONFIG_VLAN_8021Q_GVRP is not set
# CONFIG_VLAN_8021Q_MVRP is not set
# CONFIG_DECNET is not set
CONFIG_LLC=y
CONFIG_LLC2=y
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_PHONET is not set
# CONFIG_6LOWPAN is not set
# CONFIG_IEEE802154 is not set
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
# CONFIG_NET_SCH_CBQ is not set
# CONFIG_NET_SCH_HTB is not set
# CONFIG_NET_SCH_HFSC is not set
# CONFIG_NET_SCH_ATM is not set
# CONFIG_NET_SCH_PRIO is not set
# CONFIG_NET_SCH_MULTIQ is not set
# CONFIG_NET_SCH_RED is not set
# CONFIG_NET_SCH_SFB is not set
# CONFIG_NET_SCH_SFQ is not set
# CONFIG_NET_SCH_TEQL is not set
# CONFIG_NET_SCH_TBF is not set
# CONFIG_NET_SCH_CBS is not set
# CONFIG_NET_SCH_GRED is not set
# CONFIG_NET_SCH_DSMARK is not set
# CONFIG_NET_SCH_NETEM is not set
# CONFIG_NET_SCH_DRR is not set
# CONFIG_NET_SCH_MQPRIO is not set
# CONFIG_NET_SCH_CHOKE is not set
# CONFIG_NET_SCH_QFQ is not set
# CONFIG_NET_SCH_CODEL is not set
# CONFIG_NET_SCH_FQ_CODEL is not set
# CONFIG_NET_SCH_FQ is not set
# CONFIG_NET_SCH_HHF is not set
# CONFIG_NET_SCH_PIE is not set
# CONFIG_NET_SCH_INGRESS is not set
# CONFIG_NET_SCH_PLUG is not set
# CONFIG_NET_SCH_DEFAULT is not set
#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=y
# CONFIG_NET_CLS_TCINDEX is not set
# CONFIG_NET_CLS_ROUTE4 is not set
# CONFIG_NET_CLS_FW is not set
# CONFIG_NET_CLS_U32 is not set
# CONFIG_NET_CLS_RSVP is not set
# CONFIG_NET_CLS_RSVP6 is not set
# CONFIG_NET_CLS_FLOW is not set
# CONFIG_NET_CLS_CGROUP is not set
CONFIG_NET_CLS_BPF=y
# CONFIG_NET_CLS_FLOWER is not set
# CONFIG_NET_CLS_MATCHALL is not set
CONFIG_NET_EMATCH=y
CONFIG_NET_EMATCH_STACK=32
# CONFIG_NET_EMATCH_CMP is not set
# CONFIG_NET_EMATCH_NBYTE is not set
# CONFIG_NET_EMATCH_U32 is not set
# CONFIG_NET_EMATCH_META is not set
# CONFIG_NET_EMATCH_TEXT is not set
CONFIG_NET_CLS_ACT=y
# CONFIG_NET_ACT_POLICE is not set
# CONFIG_NET_ACT_GACT is not set
# CONFIG_NET_ACT_MIRRED is not set
CONFIG_NET_ACT_SAMPLE=y
# CONFIG_NET_ACT_IPT is not set
# CONFIG_NET_ACT_NAT is not set
# CONFIG_NET_ACT_PEDIT is not set
# CONFIG_NET_ACT_SIMP is not set
# CONFIG_NET_ACT_SKBEDIT is not set
# CONFIG_NET_ACT_CSUM is not set
# CONFIG_NET_ACT_VLAN is not set
CONFIG_NET_ACT_BPF=y
# CONFIG_NET_ACT_SKBMOD is not set
# CONFIG_NET_ACT_IFE is not set
# CONFIG_NET_ACT_TUNNEL_KEY is not set
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
CONFIG_VSOCKETS=y
CONFIG_VSOCKETS_DIAG=y
CONFIG_VIRTIO_VSOCKETS=y
CONFIG_VIRTIO_VSOCKETS_COMMON=y
# CONFIG_NETLINK_DIAG is not set
# CONFIG_MPLS is not set
# CONFIG_NET_NSH is not set
# CONFIG_HSR is not set
CONFIG_NET_SWITCHDEV=y
# CONFIG_NET_L3_MASTER_DEV is not set
# CONFIG_NET_NCSI is not set
CONFIG_RPS=y
CONFIG_RFS_ACCEL=y
CONFIG_XPS=y
# CONFIG_CGROUP_NET_PRIO is not set
# CONFIG_CGROUP_NET_CLASSID is not set
CONFIG_NET_RX_BUSY_POLL=y
CONFIG_BQL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_STREAM_PARSER=y
CONFIG_NET_FLOW_LIMIT=y
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_TCPPROBE is not set
# CONFIG_NET_DROP_MONITOR is not set
CONFIG_HAMRADIO=y
#
# Packet Radio protocols
#
# CONFIG_AX25 is not set
# CONFIG_CAN is not set
CONFIG_BT=y
CONFIG_BT_BREDR=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
CONFIG_BT_HS=y
CONFIG_BT_LE=y
CONFIG_BT_LEDS=y
# CONFIG_BT_SELFTEST is not set
# CONFIG_BT_DEBUGFS is not set
#
# Bluetooth device drivers
#
CONFIG_BT_INTEL=y
CONFIG_BT_RTL=y
CONFIG_BT_HCIBTUSB=y
# CONFIG_BT_HCIBTUSB_BCM is not set
CONFIG_BT_HCIBTUSB_RTL=y
# CONFIG_BT_HCIUART is not set
# CONFIG_BT_HCIBCM203X is not set
# CONFIG_BT_HCIBFUSB is not set
# CONFIG_BT_HCIDTL1 is not set
# CONFIG_BT_HCIBT3C is not set
# CONFIG_BT_HCIBLUECARD is not set
# CONFIG_BT_HCIBTUART is not set
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
# CONFIG_BT_ATH3K is not set
# CONFIG_AF_RXRPC is not set
CONFIG_AF_KCM=y
CONFIG_STREAM_PARSER=y
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_CFG80211=y
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_WEXT is not set
# CONFIG_LIB80211 is not set
CONFIG_MAC80211=y
CONFIG_MAC80211_HAS_RC=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL_HT=y
# CONFIG_MAC80211_RC_MINSTREL_VHT is not set
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
# CONFIG_MAC80211_MESH is not set
CONFIG_MAC80211_LEDS=y
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
CONFIG_WIMAX=y
CONFIG_WIMAX_DEBUG_LEVEL=8
CONFIG_RFKILL=y
CONFIG_RFKILL_LEDS=y
CONFIG_RFKILL_INPUT=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_NET_9P_XEN=y
# CONFIG_NET_9P_DEBUG is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
CONFIG_NFC=y
CONFIG_NFC_DIGITAL=y
CONFIG_NFC_NCI=y
CONFIG_NFC_NCI_UART=y
CONFIG_NFC_HCI=y
CONFIG_NFC_SHDLC=y
#
# Near Field Communication (NFC) devices
#
CONFIG_NFC_SIM=y
# CONFIG_NFC_PORT100 is not set
CONFIG_NFC_FDP=y
# CONFIG_NFC_FDP_I2C is not set
# CONFIG_NFC_PN544_I2C is not set
# CONFIG_NFC_PN533_USB is not set
# CONFIG_NFC_PN533_I2C is not set
# CONFIG_NFC_MICROREAD_I2C is not set
# CONFIG_NFC_MRVL_USB is not set
# CONFIG_NFC_MRVL_UART is not set
# CONFIG_NFC_ST21NFCA_I2C is not set
# CONFIG_NFC_ST_NCI_I2C is not set
# CONFIG_NFC_NXP_NCI is not set
# CONFIG_NFC_S3FWRN5_I2C is not set
CONFIG_PSAMPLE=y
# CONFIG_NET_IFE is not set
# CONFIG_LWTUNNEL is not set
CONFIG_DST_CACHE=y
CONFIG_GRO_CELLS=y
# CONFIG_NET_DEVLINK is not set
CONFIG_MAY_USE_DEVLINK=y
CONFIG_HAVE_EBPF_JIT=y
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
CONFIG_ALLOW_DEV_COREDUMP=y
# CONFIG_DEBUG_DRIVER is not set
CONFIG_DEBUG_DEVRES=y
# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
CONFIG_SYS_HYPERVISOR=y
# CONFIG_GENERIC_CPU_DEVICES is not set
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
#
# Bus devices
#
CONFIG_CONNECTOR=y
CONFIG_PROC_EVENTS=y
# CONFIG_MTD is not set
# CONFIG_OF is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_PARPORT is not set
CONFIG_PNP=y
CONFIG_PNP_DEBUG_MESSAGES=y
#
# Protocols
#
CONFIG_PNPACPI=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_NULL_BLK=y
# CONFIG_BLK_DEV_FD is not set
CONFIG_CDROM=y
# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_DRBD is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SKD is not set
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_XEN_BLKDEV_FRONTEND=y
# CONFIG_XEN_BLKDEV_BACKEND is not set
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_BLK_SCSI=y
# CONFIG_BLK_DEV_RBD is not set
# CONFIG_BLK_DEV_RSXX is not set
#
# NVME Support
#
# CONFIG_BLK_DEV_NVME is not set
# CONFIG_NVME_FC is not set
# CONFIG_NVME_TARGET is not set
#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_DUMMY_IRQ is not set
# CONFIG_IBM_ASM is not set
# CONFIG_PHANTOM is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_HP_ILO is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
# CONFIG_SRAM is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_EEPROM_IDT_89HPESX is not set
# CONFIG_CB710_CORE is not set
#
# Texas Instruments shared transport line discipline
#
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_ALTERA_STAPL is not set
# CONFIG_INTEL_MEI is not set
# CONFIG_INTEL_MEI_ME is not set
# CONFIG_INTEL_MEI_TXE is not set
# CONFIG_VMWARE_VMCI is not set
#
# Intel MIC & related support
#
#
# Intel MIC Bus Driver
#
# CONFIG_INTEL_MIC_BUS is not set
#
# SCIF Bus Driver
#
# CONFIG_SCIF_BUS is not set
#
# VOP Bus Driver
#
# CONFIG_VOP_BUS is not set
#
# Intel MIC Host Driver
#
#
# Intel MIC Card Driver
#
#
# SCIF Driver
#
#
# Intel MIC Coprocessor State Management (COSM) Drivers
#
#
# VOP Driver
#
# CONFIG_GENWQE is not set
# CONFIG_ECHO is not set
# CONFIG_CXL_BASE is not set
# CONFIG_CXL_AFU_DRIVER_OPS is not set
# CONFIG_CXL_LIB is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_SCSI_MQ_DEFAULT is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=y
# CONFIG_CHR_DEV_SCH is not set
CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
#
# SCSI Transports
#
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_ISCSI_BOOT_SYSFS is not set
# CONFIG_SCSI_CXGB3_ISCSI is not set
# CONFIG_SCSI_CXGB4_ISCSI is not set
# CONFIG_SCSI_BNX2_ISCSI is not set
# CONFIG_BE2ISCSI is not set
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_HPSA is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_AIC94XX is not set
# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_MVUMI is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_ARCMSR is not set
# CONFIG_SCSI_ESAS2R is not set
# CONFIG_MEGARAID_NEWGEN is not set
# CONFIG_MEGARAID_LEGACY is not set
# CONFIG_MEGARAID_SAS is not set
# CONFIG_SCSI_MPT3SAS is not set
# CONFIG_SCSI_MPT2SAS is not set
# CONFIG_SCSI_SMARTPQI is not set
# CONFIG_SCSI_UFSHCD is not set
# CONFIG_SCSI_HPTIOP is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_VMWARE_PVSCSI is not set
# CONFIG_XEN_SCSI_FRONTEND is not set
# CONFIG_SCSI_SNIC is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_ISCI is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_QLA_ISCSI is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_WD719X is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_PMCRAID is not set
# CONFIG_SCSI_PM8001 is not set
CONFIG_SCSI_VIRTIO=y
# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
CONFIG_ATA_VERBOSE_ERROR=y
CONFIG_ATA_ACPI=y
# CONFIG_SATA_ZPODD is not set
CONFIG_SATA_PMP=y
#
# Controllers with non-SFF native interface
#
CONFIG_SATA_AHCI=y
# CONFIG_SATA_AHCI_PLATFORM is not set
# CONFIG_SATA_INIC162X is not set
# CONFIG_SATA_ACARD_AHCI is not set
# CONFIG_SATA_SIL24 is not set
CONFIG_ATA_SFF=y
#
# SFF controllers with custom DMA interface
#
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_SATA_SX4 is not set
CONFIG_ATA_BMDMA=y
#
# SATA SFF controllers with BMDMA
#
CONFIG_ATA_PIIX=y
# CONFIG_SATA_DWC is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_NV is not set
# CONFIG_SATA_PROMISE is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIS is not set
# CONFIG_SATA_SVW is not set
# CONFIG_SATA_ULI is not set
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
#
# PATA SFF controllers with BMDMA
#
# CONFIG_PATA_ALI is not set
CONFIG_PATA_AMD=y
# CONFIG_PATA_ARTOP is not set
# CONFIG_PATA_ATIIXP is not set
# CONFIG_PATA_ATP867X is not set
# CONFIG_PATA_CMD64X is not set
# CONFIG_PATA_CYPRESS is not set
# CONFIG_PATA_EFAR is not set
# CONFIG_PATA_HPT366 is not set
# CONFIG_PATA_HPT37X is not set
# CONFIG_PATA_HPT3X2N is not set
# CONFIG_PATA_HPT3X3 is not set
# CONFIG_PATA_IT8213 is not set
# CONFIG_PATA_IT821X is not set
# CONFIG_PATA_JMICRON is not set
# CONFIG_PATA_MARVELL is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87415 is not set
CONFIG_PATA_OLDPIIX=y
# CONFIG_PATA_OPTIDMA is not set
# CONFIG_PATA_PDC2027X is not set
# CONFIG_PATA_PDC_OLD is not set
# CONFIG_PATA_RADISYS is not set
# CONFIG_PATA_RDC is not set
CONFIG_PATA_SCH=y
# CONFIG_PATA_SERVERWORKS is not set
# CONFIG_PATA_SIL680 is not set
# CONFIG_PATA_SIS is not set
# CONFIG_PATA_TOSHIBA is not set
# CONFIG_PATA_TRIFLEX is not set
# CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set
#
# PIO-only SFF controllers
#
# CONFIG_PATA_CMD640_PCI is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_PATA_PCMCIA is not set
# CONFIG_PATA_PLATFORM is not set
# CONFIG_PATA_RZ1000 is not set
#
# Generic fallback / legacy drivers
#
# CONFIG_PATA_ACPI is not set
# CONFIG_ATA_GENERIC is not set
# CONFIG_PATA_LEGACY is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_AUTODETECT=y
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID10 is not set
# CONFIG_MD_RAID456 is not set
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
# CONFIG_BCACHE is not set
CONFIG_BLK_DEV_DM_BUILTIN=y
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_MQ_DEFAULT is not set
# CONFIG_DM_DEBUG is not set
# CONFIG_DM_CRYPT is not set
# CONFIG_DM_SNAPSHOT is not set
# CONFIG_DM_THIN_PROVISIONING is not set
# CONFIG_DM_CACHE is not set
# CONFIG_DM_ERA is not set
CONFIG_DM_MIRROR=y
# CONFIG_DM_LOG_USERSPACE is not set
# CONFIG_DM_RAID is not set
CONFIG_DM_ZERO=y
# CONFIG_DM_MULTIPATH is not set
# CONFIG_DM_DELAY is not set
# CONFIG_DM_UEVENT is not set
# CONFIG_DM_FLAKEY is not set
# CONFIG_DM_VERITY is not set
# CONFIG_DM_SWITCH is not set
# CONFIG_DM_LOG_WRITES is not set
# CONFIG_DM_INTEGRITY is not set
# CONFIG_DM_ZONED is not set
# CONFIG_TARGET_CORE is not set
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support
#
# CONFIG_FIREWIRE is not set
# CONFIG_FIREWIRE_NOSY is not set
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_MAC_EMUMOUSEBTN=y
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
# CONFIG_NET_FC is not set
# CONFIG_IFB is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_VXLAN is not set
# CONFIG_GENEVE is not set
# CONFIG_GTP is not set
# CONFIG_MACSEC is not set
CONFIG_NETCONSOLE=y
# CONFIG_NETCONSOLE_DYNAMIC is not set
CONFIG_NETPOLL=y
CONFIG_NET_POLL_CONTROLLER=y
CONFIG_TUN=y
# CONFIG_TUN_VNET_CROSS_LE is not set
CONFIG_VETH=y
CONFIG_VIRTIO_NET=y
# CONFIG_NLMON is not set
# CONFIG_ARCNET is not set
CONFIG_ATM_DRIVERS=y
# CONFIG_ATM_DUMMY is not set
CONFIG_ATM_TCP=y
# CONFIG_ATM_LANAI is not set
# CONFIG_ATM_ENI is not set
# CONFIG_ATM_FIRESTREAM is not set
# CONFIG_ATM_ZATM is not set
# CONFIG_ATM_NICSTAR is not set
# CONFIG_ATM_IDT77252 is not set
# CONFIG_ATM_AMBASSADOR is not set
# CONFIG_ATM_HORIZON is not set
# CONFIG_ATM_IA is not set
# CONFIG_ATM_FORE200E is not set
# CONFIG_ATM_HE is not set
# CONFIG_ATM_SOLOS is not set
#
# CAIF transport drivers
#
#
# Distributed Switch Architecture drivers
#
# CONFIG_B53 is not set
# CONFIG_NET_DSA_LOOP is not set
# CONFIG_NET_DSA_MT7530 is not set
# CONFIG_NET_DSA_MV88E6060 is not set
# CONFIG_MICROCHIP_KSZ is not set
# CONFIG_NET_DSA_MV88E6XXX is not set
# CONFIG_NET_DSA_QCA8K is not set
# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set
# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_3COM=y
# CONFIG_PCMCIA_3C574 is not set
# CONFIG_PCMCIA_3C589 is not set
# CONFIG_VORTEX is not set
# CONFIG_TYPHOON is not set
CONFIG_NET_VENDOR_ADAPTEC=y
# CONFIG_ADAPTEC_STARFIRE is not set
CONFIG_NET_VENDOR_AGERE=y
# CONFIG_ET131X is not set
CONFIG_NET_VENDOR_ALACRITECH=y
# CONFIG_SLICOSS is not set
CONFIG_NET_VENDOR_ALTEON=y
# CONFIG_ACENIC is not set
# CONFIG_ALTERA_TSE is not set
CONFIG_NET_VENDOR_AMAZON=y
# CONFIG_ENA_ETHERNET is not set
CONFIG_NET_VENDOR_AMD=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_PCNET32 is not set
# CONFIG_PCMCIA_NMCLAN is not set
# CONFIG_AMD_XGBE is not set
# CONFIG_AMD_XGBE_HAVE_ECC is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
CONFIG_NET_VENDOR_ARC=y
CONFIG_NET_VENDOR_ATHEROS=y
# CONFIG_ATL2 is not set
# CONFIG_ATL1 is not set
# CONFIG_ATL1E is not set
# CONFIG_ATL1C is not set
# CONFIG_ALX is not set
# CONFIG_NET_VENDOR_AURORA is not set
CONFIG_NET_CADENCE=y
# CONFIG_MACB is not set
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_BNX2 is not set
# CONFIG_CNIC is not set
CONFIG_TIGON3=y
CONFIG_TIGON3_HWMON=y
# CONFIG_BNX2X is not set
# CONFIG_BNXT is not set
CONFIG_NET_VENDOR_BROCADE=y
# CONFIG_BNA is not set
CONFIG_NET_VENDOR_CAVIUM=y
# CONFIG_THUNDER_NIC_PF is not set
# CONFIG_THUNDER_NIC_VF is not set
# CONFIG_THUNDER_NIC_BGX is not set
# CONFIG_THUNDER_NIC_RGX is not set
# CONFIG_LIQUIDIO is not set
# CONFIG_LIQUIDIO_VF is not set
CONFIG_NET_VENDOR_CHELSIO=y
# CONFIG_CHELSIO_T1 is not set
# CONFIG_CHELSIO_T3 is not set
# CONFIG_CHELSIO_T4 is not set
# CONFIG_CHELSIO_T4VF is not set
CONFIG_NET_VENDOR_CISCO=y
# CONFIG_ENIC is not set
# CONFIG_CX_ECAT is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_DEC=y
CONFIG_NET_TULIP=y
# CONFIG_DE2104X is not set
# CONFIG_TULIP is not set
# CONFIG_DE4X5 is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_DM9102 is not set
# CONFIG_ULI526X is not set
# CONFIG_PCMCIA_XIRCOM is not set
CONFIG_NET_VENDOR_DLINK=y
# CONFIG_DL2K is not set
# CONFIG_SUNDANCE is not set
CONFIG_NET_VENDOR_EMULEX=y
# CONFIG_BE2NET is not set
CONFIG_NET_VENDOR_EZCHIP=y
CONFIG_NET_VENDOR_EXAR=y
# CONFIG_S2IO is not set
# CONFIG_VXGE is not set
CONFIG_NET_VENDOR_FUJITSU=y
# CONFIG_PCMCIA_FMVJ18X is not set
CONFIG_NET_VENDOR_HP=y
# CONFIG_HP100 is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_E1000E_HWTS=y
# CONFIG_IGB is not set
# CONFIG_IGBVF is not set
# CONFIG_IXGB is not set
# CONFIG_IXGBE is not set
# CONFIG_IXGBEVF is not set
# CONFIG_I40E is not set
# CONFIG_I40EVF is not set
# CONFIG_FM10K is not set
CONFIG_NET_VENDOR_I825XX=y
# CONFIG_JME is not set
CONFIG_NET_VENDOR_MARVELL=y
# CONFIG_MVMDIO is not set
# CONFIG_SKGE is not set
CONFIG_SKY2=y
# CONFIG_SKY2_DEBUG is not set
CONFIG_NET_VENDOR_MELLANOX=y
# CONFIG_MLX4_EN is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_MLX5_CORE is not set
# CONFIG_MLXSW_CORE is not set
# CONFIG_MLXFW is not set
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_KSZ884X_PCI is not set
CONFIG_NET_VENDOR_MYRI=y
# CONFIG_MYRI10GE is not set
# CONFIG_FEALNX is not set
CONFIG_NET_VENDOR_NATSEMI=y
# CONFIG_NATSEMI is not set
# CONFIG_NS83820 is not set
CONFIG_NET_VENDOR_NETRONOME=y
# CONFIG_NFP is not set
CONFIG_NET_VENDOR_8390=y
# CONFIG_PCMCIA_AXNET is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_PCMCIA_PCNET is not set
CONFIG_NET_VENDOR_NVIDIA=y
CONFIG_FORCEDETH=y
CONFIG_NET_VENDOR_OKI=y
# CONFIG_ETHOC is not set
CONFIG_NET_PACKET_ENGINE=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
CONFIG_NET_VENDOR_QLOGIC=y
# CONFIG_QLA3XXX is not set
# CONFIG_QLCNIC is not set
# CONFIG_QLGE is not set
# CONFIG_NETXEN_NIC is not set
# CONFIG_QED is not set
CONFIG_NET_VENDOR_QUALCOMM=y
# CONFIG_QCOM_EMAC is not set
# CONFIG_RMNET is not set
CONFIG_NET_VENDOR_REALTEK=y
# CONFIG_8139CP is not set
CONFIG_8139TOO=y
CONFIG_8139TOO_PIO=y
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_8139_OLD_RX_RESET is not set
# CONFIG_R8169 is not set
CONFIG_NET_VENDOR_RENESAS=y
CONFIG_NET_VENDOR_RDC=y
# CONFIG_R6040 is not set
CONFIG_NET_VENDOR_ROCKER=y
# CONFIG_ROCKER is not set
CONFIG_NET_VENDOR_SAMSUNG=y
# CONFIG_SXGBE_ETH is not set
CONFIG_NET_VENDOR_SEEQ=y
CONFIG_NET_VENDOR_SILAN=y
# CONFIG_SC92031 is not set
CONFIG_NET_VENDOR_SIS=y
# CONFIG_SIS900 is not set
# CONFIG_SIS190 is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_PCMCIA_SMC91C92 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SMSC911X is not set
# CONFIG_SMSC9420 is not set
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_SUN=y
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_CASSINI is not set
# CONFIG_NIU is not set
CONFIG_NET_VENDOR_TEHUTI=y
# CONFIG_TEHUTI is not set
CONFIG_NET_VENDOR_TI=y
# CONFIG_TI_CPSW_ALE is not set
# CONFIG_TLAN is not set
CONFIG_NET_VENDOR_VIA=y
# CONFIG_VIA_RHINE is not set
# CONFIG_VIA_VELOCITY is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
CONFIG_NET_VENDOR_XIRCOM=y
# CONFIG_PCMCIA_XIRC2PS is not set
CONFIG_NET_VENDOR_SYNOPSYS=y
# CONFIG_DWC_XLGMAC is not set
CONFIG_FDDI=y
# CONFIG_DEFXX is not set
# CONFIG_SKFP is not set
# CONFIG_HIPPI is not set
# CONFIG_NET_SB1000 is not set
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_BUS=y
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_THUNDER is not set
CONFIG_PHYLIB=y
# CONFIG_LED_TRIGGER_PHY is not set
#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_AQUANTIA_PHY is not set
# CONFIG_AT803X_PHY is not set
# CONFIG_BCM7XXX_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_CORTINA_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_DP83822_PHY is not set
# CONFIG_DP83848_PHY is not set
# CONFIG_DP83867_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_INTEL_XWAY_PHY is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_MARVELL_10G_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_MICROCHIP_PHY is not set
# CONFIG_MICROSEMI_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_RENESAS_PHY is not set
# CONFIG_ROCKCHIP_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_TERANETICS_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_XILINX_GMII2RGMII is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
CONFIG_USB_NET_DRIVERS=y
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_LAN78XX is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_HSO is not set
# CONFIG_USB_IPHETH is not set
CONFIG_WLAN=y
# CONFIG_WIRELESS_WDS is not set
CONFIG_WLAN_VENDOR_ADMTEK=y
# CONFIG_ADM8211 is not set
CONFIG_WLAN_VENDOR_ATH=y
# CONFIG_ATH_DEBUG is not set
# CONFIG_ATH5K is not set
# CONFIG_ATH5K_PCI is not set
# CONFIG_ATH9K is not set
# CONFIG_ATH9K_HTC is not set
# CONFIG_CARL9170 is not set
# CONFIG_ATH6KL is not set
# CONFIG_AR5523 is not set
# CONFIG_WIL6210 is not set
# CONFIG_ATH10K is not set
# CONFIG_WCN36XX is not set
CONFIG_WLAN_VENDOR_ATMEL=y
# CONFIG_ATMEL is not set
# CONFIG_AT76C50X_USB is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_BRCMSMAC is not set
# CONFIG_BRCMFMAC is not set
CONFIG_WLAN_VENDOR_CISCO=y
# CONFIG_AIRO is not set
# CONFIG_AIRO_CS is not set
CONFIG_WLAN_VENDOR_INTEL=y
# CONFIG_IPW2100 is not set
# CONFIG_IPW2200 is not set
# CONFIG_IWL4965 is not set
# CONFIG_IWL3945 is not set
# CONFIG_IWLWIFI is not set
CONFIG_WLAN_VENDOR_INTERSIL=y
# CONFIG_HOSTAP is not set
# CONFIG_HERMES is not set
# CONFIG_P54_COMMON is not set
# CONFIG_PRISM54 is not set
CONFIG_WLAN_VENDOR_MARVELL=y
# CONFIG_LIBERTAS is not set
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_MWIFIEX is not set
# CONFIG_MWL8K is not set
CONFIG_WLAN_VENDOR_MEDIATEK=y
# CONFIG_MT7601U is not set
CONFIG_WLAN_VENDOR_RALINK=y
# CONFIG_RT2X00 is not set
CONFIG_WLAN_VENDOR_REALTEK=y
# CONFIG_RTL8180 is not set
# CONFIG_RTL8187 is not set
CONFIG_RTL_CARDS=y
# CONFIG_RTL8192CE is not set
# CONFIG_RTL8192SE is not set
# CONFIG_RTL8192DE is not set
# CONFIG_RTL8723AE is not set
# CONFIG_RTL8723BE is not set
# CONFIG_RTL8188EE is not set
# CONFIG_RTL8192EE is not set
# CONFIG_RTL8821AE is not set
# CONFIG_RTL8192CU is not set
# CONFIG_RTL8XXXU is not set
CONFIG_WLAN_VENDOR_RSI=y
# CONFIG_RSI_91X is not set
CONFIG_WLAN_VENDOR_ST=y
# CONFIG_CW1200 is not set
CONFIG_WLAN_VENDOR_TI=y
# CONFIG_WL1251 is not set
# CONFIG_WL12XX is not set
# CONFIG_WL18XX is not set
# CONFIG_WLCORE is not set
CONFIG_WLAN_VENDOR_ZYDAS=y
# CONFIG_USB_ZD1201 is not set
# CONFIG_ZD1211RW is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_PCMCIA_RAYCS is not set
# CONFIG_PCMCIA_WL3501 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
#
# WiMAX Wireless Broadband devices
#
# CONFIG_WIMAX_I2400M_USB is not set
# CONFIG_WAN is not set
CONFIG_XEN_NETDEV_FRONTEND=y
# CONFIG_XEN_NETDEV_BACKEND is not set
# CONFIG_VMXNET3 is not set
# CONFIG_FUJITSU_ES is not set
# CONFIG_ISDN is not set
# CONFIG_NVM is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_LEDS=y
CONFIG_INPUT_FF_MEMLESS=y
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MATRIXKMAP is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_BYD=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
CONFIG_MOUSE_PS2_CYPRESS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
CONFIG_MOUSE_PS2_FOCALTECH=y
# CONFIG_MOUSE_PS2_VMMOUSE is not set
CONFIG_MOUSE_PS2_SMBUS=y
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_MOUSE_SYNAPTICS_USB is not set
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
# CONFIG_JOYSTICK_GRIP is not set
# CONFIG_JOYSTICK_GRIP_MP is not set
# CONFIG_JOYSTICK_GUILLEMOT is not set
# CONFIG_JOYSTICK_INTERACT is not set
# CONFIG_JOYSTICK_SIDEWINDER is not set
# CONFIG_JOYSTICK_TMDC is not set
# CONFIG_JOYSTICK_IFORCE is not set
# CONFIG_JOYSTICK_WARRIOR is not set
# CONFIG_JOYSTICK_MAGELLAN is not set
# CONFIG_JOYSTICK_SPACEORB is not set
# CONFIG_JOYSTICK_SPACEBALL is not set
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
# CONFIG_JOYSTICK_XPAD is not set
CONFIG_INPUT_TABLET=y
# CONFIG_TABLET_USB_ACECAD is not set
# CONFIG_TABLET_USB_AIPTEK is not set
# CONFIG_TABLET_USB_GTCO is not set
# CONFIG_TABLET_USB_HANWANG is not set
# CONFIG_TABLET_USB_KBTAB is not set
# CONFIG_TABLET_USB_PEGASUS is not set
# CONFIG_TABLET_SERIAL_WACOM4 is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_BMA150 is not set
# CONFIG_INPUT_E3X0_BUTTON is not set
# CONFIG_INPUT_PCSPKR is not set
# CONFIG_INPUT_MMA8450 is not set
# CONFIG_INPUT_APANEL is not set
# CONFIG_INPUT_ATLAS_BTNS is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_KXTJ9 is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_IMS_PCU is not set
# CONFIG_INPUT_CMA3000 is not set
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
# CONFIG_INPUT_DRV2665_HAPTICS is not set
# CONFIG_INPUT_DRV2667_HAPTICS is not set
# CONFIG_RMI4_CORE is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_SERIO_PS2MULT is not set
# CONFIG_SERIO_ARC_PS2 is not set
# CONFIG_USERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_TTY=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_VT_CONSOLE_SLEEP=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_ROCKETPORT is not set
# CONFIG_CYCLADES is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_SYNCLINK is not set
# CONFIG_SYNCLINKMP is not set
# CONFIG_SYNCLINK_GT is not set
# CONFIG_NOZOMI is not set
# CONFIG_ISI is not set
# CONFIG_N_HDLC is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
CONFIG_DEVMEM=y
# CONFIG_DEVKMEM is not set
#
# Serial drivers
#
CONFIG_SERIAL_EARLYCON=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
CONFIG_SERIAL_8250_PNP=y
# CONFIG_SERIAL_8250_FINTEK is not set
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_DMA=y
CONFIG_SERIAL_8250_PCI=y
# CONFIG_SERIAL_8250_EXAR is not set
# CONFIG_SERIAL_8250_CS is not set
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
# CONFIG_SERIAL_8250_FSL is not set
# CONFIG_SERIAL_8250_DW is not set
# CONFIG_SERIAL_8250_RT288X is not set
CONFIG_SERIAL_8250_LPSS=y
CONFIG_SERIAL_8250_MID=y
# CONFIG_SERIAL_8250_MOXA is not set
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_SCCNXP is not set
# CONFIG_SERIAL_SC16IS7XX is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
# CONFIG_SERIAL_ARC is not set
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
CONFIG_SERIAL_DEV_BUS=y
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
# CONFIG_TTY_PRINTK is not set
CONFIG_HVC_DRIVER=y
CONFIG_HVC_IRQ=y
CONFIG_HVC_XEN=y
CONFIG_HVC_XEN_FRONTEND=y
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_HW_RANDOM_INTEL is not set
# CONFIG_HW_RANDOM_AMD is not set
CONFIG_HW_RANDOM_VIA=y
# CONFIG_HW_RANDOM_VIRTIO is not set
CONFIG_NVRAM=y
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_CARDMAN_4000 is not set
# CONFIG_CARDMAN_4040 is not set
# CONFIG_SCR24X is not set
# CONFIG_IPWIRELESS is not set
# CONFIG_MWAVE is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_HPET=y
# CONFIG_HPET_MMAP is not set
# CONFIG_HANGCHECK_TIMER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_TELCLOCK is not set
CONFIG_DEVPORT=y
# CONFIG_XILLYBUS is not set
#
# I2C support
#
CONFIG_I2C=y
CONFIG_ACPI_I2C_OPREGION=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
# CONFIG_I2C_CHARDEV is not set
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y
CONFIG_I2C_SMBUS=y
CONFIG_I2C_ALGOBIT=y
#
# I2C Hardware Bus support
#
#
# PC SMBus host controller drivers
#
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
# CONFIG_I2C_ALI15X3 is not set
# CONFIG_I2C_AMD756 is not set
# CONFIG_I2C_AMD8111 is not set
CONFIG_I2C_I801=y
# CONFIG_I2C_ISCH is not set
# CONFIG_I2C_ISMT is not set
# CONFIG_I2C_PIIX4 is not set
# CONFIG_I2C_NFORCE2 is not set
# CONFIG_I2C_SIS5595 is not set
# CONFIG_I2C_SIS630 is not set
# CONFIG_I2C_SIS96X is not set
# CONFIG_I2C_VIA is not set
# CONFIG_I2C_VIAPRO is not set
#
# ACPI drivers
#
# CONFIG_I2C_SCMI is not set
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_DESIGNWARE_PCI is not set
# CONFIG_I2C_EMEV2 is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_MLXCPLD is not set
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_SLAVE is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
CONFIG_PPS=y
# CONFIG_PPS_DEBUG is not set
#
# PPS clients support
#
# CONFIG_PPS_CLIENT_KTIMER is not set
# CONFIG_PPS_CLIENT_LDISC is not set
# CONFIG_PPS_CLIENT_GPIO is not set
#
# PPS generators support
#
#
# PTP clock support
#
CONFIG_PTP_1588_CLOCK=y
#
# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
#
CONFIG_PTP_1588_CLOCK_KVM=y
# CONFIG_PINCTRL is not set
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
# CONFIG_POWER_AVS is not set
# CONFIG_POWER_RESET is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_TEST_POWER is not set
# CONFIG_BATTERY_DS2780 is not set
# CONFIG_BATTERY_DS2781 is not set
# CONFIG_BATTERY_DS2782 is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_CHARGER_SBS is not set
# CONFIG_BATTERY_BQ27XXX is not set
# CONFIG_BATTERY_MAX17040 is not set
# CONFIG_BATTERY_MAX17042 is not set
# CONFIG_CHARGER_MAX8903 is not set
# CONFIG_CHARGER_LP8727 is not set
# CONFIG_CHARGER_BQ2415X is not set
# CONFIG_CHARGER_SMB347 is not set
# CONFIG_BATTERY_GAUGE_LTC2941 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7410 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_K8TEMP is not set
# CONFIG_SENSORS_K10TEMP is not set
# CONFIG_SENSORS_FAM15H_POWER is not set
# CONFIG_SENSORS_APPLESMC is not set
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ASPEED is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_DELL_SMM is not set
# CONFIG_SENSORS_I5K_AMB is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_FSCHMD is not set
# CONFIG_SENSORS_FTSTEUTATES is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_G762 is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_I5500 is not set
# CONFIG_SENSORS_CORETEMP is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_POWR1220 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LTC2945 is not set
# CONFIG_SENSORS_LTC2990 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4222 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4260 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX197 is not set
# CONFIG_SENSORS_MAX6621 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_MAX6697 is not set
# CONFIG_SENSORS_MAX31790 is not set
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_TC654 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LM95234 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_NCT6683 is not set
# CONFIG_SENSORS_NCT6775 is not set
# CONFIG_SENSORS_NCT7802 is not set
# CONFIG_SENSORS_NCT7904 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SHT3x is not set
# CONFIG_SENSORS_SHTC1 is not set
# CONFIG_SENSORS_SIS5595 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_STTS751 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_ADC128D818 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA209 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_INA3221 is not set
# CONFIG_SENSORS_TC74 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP103 is not set
# CONFIG_SENSORS_TMP108 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VIA_CPUTEMP is not set
# CONFIG_SENSORS_VIA686A is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_VT8231 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_XGENE is not set
#
# ACPI drivers
#
# CONFIG_SENSORS_ACPI_POWER is not set
# CONFIG_SENSORS_ATK0110 is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_WRITABLE_TRIPS=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
CONFIG_THERMAL_GOV_STEP_WISE=y
# CONFIG_THERMAL_GOV_BANG_BANG is not set
CONFIG_THERMAL_GOV_USER_SPACE=y
# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_INTEL_POWERCLAMP is not set
CONFIG_X86_PKG_TEMP_THERMAL=y
# CONFIG_INTEL_SOC_DTS_THERMAL is not set
#
# ACPI INT340X thermal drivers
#
# CONFIG_INT340X_THERMAL is not set
# CONFIG_INTEL_PCH_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_CORE is not set
# CONFIG_WATCHDOG_NOWAYOUT is not set
CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y
# CONFIG_WATCHDOG_SYSFS is not set
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_WDAT_WDT is not set
# CONFIG_XILINX_WATCHDOG is not set
# CONFIG_ZIIRAVE_WATCHDOG is not set
# CONFIG_CADENCE_WATCHDOG is not set
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set
# CONFIG_ACQUIRE_WDT is not set
# CONFIG_ADVANTECH_WDT is not set
# CONFIG_ALIM1535_WDT is not set
# CONFIG_ALIM7101_WDT is not set
# CONFIG_F71808E_WDT is not set
# CONFIG_SP5100_TCO is not set
# CONFIG_SBC_FITPC2_WATCHDOG is not set
# CONFIG_EUROTECH_WDT is not set
# CONFIG_IB700_WDT is not set
# CONFIG_IBMASR is not set
# CONFIG_WAFER_WDT is not set
# CONFIG_I6300ESB_WDT is not set
# CONFIG_IE6XX_WDT is not set
# CONFIG_ITCO_WDT is not set
# CONFIG_IT8712F_WDT is not set
# CONFIG_IT87_WDT is not set
# CONFIG_HP_WATCHDOG is not set
# CONFIG_SC1200_WDT is not set
# CONFIG_PC87413_WDT is not set
# CONFIG_NV_TCO is not set
# CONFIG_60XX_WDT is not set
# CONFIG_CPU5_WDT is not set
# CONFIG_SMSC_SCH311X_WDT is not set
# CONFIG_SMSC37B787_WDT is not set
# CONFIG_VIA_WDT is not set
# CONFIG_W83627HF_WDT is not set
# CONFIG_W83877F_WDT is not set
# CONFIG_W83977F_WDT is not set
# CONFIG_MACHZ_WDT is not set
# CONFIG_SBC_EPX_C3_WATCHDOG is not set
# CONFIG_NI903X_WDT is not set
# CONFIG_NIC7018_WDT is not set
# CONFIG_XEN_WDT is not set
#
# PCI-based Watchdog Cards
#
# CONFIG_PCIPCWATCHDOG is not set
# CONFIG_WDTPCI is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
#
# Watchdog Pretimeout Governors
#
# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y
# CONFIG_BCMA is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_AS3711 is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_BCM590XX is not set
# CONFIG_MFD_BD9571MWV is not set
# CONFIG_MFD_AXP20X_I2C is not set
# CONFIG_MFD_CROS_EC is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_MFD_DA9055 is not set
# CONFIG_MFD_DA9062 is not set
# CONFIG_MFD_DA9063 is not set
# CONFIG_MFD_DA9150 is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
# CONFIG_LPC_ICH is not set
# CONFIG_LPC_SCH is not set
# CONFIG_INTEL_SOC_PMIC_CHTWC is not set
# CONFIG_MFD_INTEL_LPSS_ACPI is not set
# CONFIG_MFD_INTEL_LPSS_PCI is not set
# CONFIG_MFD_JANZ_CMODIO is not set
# CONFIG_MFD_KEMPLD is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_MAX14577 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX77843 is not set
# CONFIG_MFD_MAX8907 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_MT6397 is not set
# CONFIG_MFD_MENF21BMC is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_RETU is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_RDC321X is not set
# CONFIG_MFD_RTSX_PCI is not set
# CONFIG_MFD_RT5033 is not set
# CONFIG_MFD_RTSX_USB is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_SI476X_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_SKY81452 is not set
# CONFIG_MFD_SMSC is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_SYSCON is not set
# CONFIG_MFD_TI_AM335X_TSCADC is not set
# CONFIG_MFD_LP3943 is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_TI_LMU is not set
# CONFIG_MFD_PALMAS is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65086 is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_TPS68470 is not set
# CONFIG_MFD_TI_LP873X is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_MFD_TPS80031 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_VX855 is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_REGULATOR is not set
# CONFIG_RC_CORE is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
CONFIG_AGP=y
CONFIG_AGP_AMD64=y
CONFIG_AGP_INTEL=y
# CONFIG_AGP_SIS is not set
# CONFIG_AGP_VIA is not set
CONFIG_INTEL_GTT=y
CONFIG_VGA_ARB=y
CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_VGA_SWITCHEROO is not set
CONFIG_DRM=y
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_MM_SELFTEST is not set
CONFIG_DRM_KMS_HELPER=y
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_TTM=y
CONFIG_DRM_GEM_CMA_HELPER=y
CONFIG_DRM_KMS_CMA_HELPER=y
#
# I2C encoder or helper chips
#
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
CONFIG_DRM_RADEON=y
CONFIG_DRM_RADEON_USERPTR=y
CONFIG_DRM_AMDGPU=y
CONFIG_DRM_AMDGPU_SI=y
CONFIG_DRM_AMDGPU_CIK=y
CONFIG_DRM_AMDGPU_USERPTR=y
# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set
#
# ACP (Audio CoProcessor) Configuration
#
# CONFIG_DRM_AMD_ACP is not set
#
# Display Engine Configuration
#
CONFIG_DRM_AMD_DC=y
# CONFIG_DRM_AMD_DC_PRE_VEGA is not set
# CONFIG_DRM_AMD_DC_FBC is not set
# CONFIG_DRM_AMD_DC_DCN1_0 is not set
# CONFIG_DEBUG_KERNEL_DC is not set
#
# AMD Library routines
#
CONFIG_CHASH=y
# CONFIG_CHASH_STATS is not set
# CONFIG_CHASH_SELFTEST is not set
# CONFIG_DRM_NOUVEAU is not set
CONFIG_DRM_I915=y
CONFIG_DRM_I915_ALPHA_SUPPORT=y
CONFIG_DRM_I915_CAPTURE_ERROR=y
CONFIG_DRM_I915_COMPRESS_ERROR=y
CONFIG_DRM_I915_USERPTR=y
CONFIG_DRM_I915_GVT=y
#
# drm/i915 Debugging
#
# CONFIG_DRM_I915_WERROR is not set
# CONFIG_DRM_I915_DEBUG is not set
# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
# CONFIG_DRM_I915_SELFTEST is not set
# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VMWGFX is not set
# CONFIG_DRM_GMA500 is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_AST is not set
# CONFIG_DRM_MGAG200 is not set
CONFIG_DRM_CIRRUS_QEMU=y
CONFIG_DRM_QXL=y
# CONFIG_DRM_BOCHS is not set
CONFIG_DRM_VIRTIO_GPU=y
CONFIG_DRM_PANEL=y
#
# Display Panels
#
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
CONFIG_DRM_BRIDGE=y
CONFIG_DRM_PANEL_BRIDGE=y
#
# Display Interface Bridges
#
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_HISI_HIBMC is not set
CONFIG_DRM_TINYDRM=y
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIB_RANDOM is not set
#
# Frame buffer Devices
#
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FB_CMDLINE=y
CONFIG_FB_NOTIFY=y
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
#
# Frame buffer hardware drivers
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_ARC is not set
# CONFIG_FB_ASILIANT is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_VGA16 is not set
# CONFIG_FB_UVESA is not set
# CONFIG_FB_VESA is not set
CONFIG_FB_EFI=y
# CONFIG_FB_N411 is not set
# CONFIG_FB_HGA is not set
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_NVIDIA is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_I740 is not set
# CONFIG_FB_LE80578 is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_S3 is not set
# CONFIG_FB_SAVAGE is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_KYRO is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_VT8623 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_ARK is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_CARMINE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_VIRTUAL is not set
CONFIG_XEN_FBDEV_FRONTEND=y
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_AUO_K190X is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SM712 is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_APPLE is not set
# CONFIG_BACKLIGHT_PM8941_WLED is not set
# CONFIG_BACKLIGHT_SAHARA is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_VGASTATE is not set
CONFIG_HDMI=y
#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
CONFIG_VGACON_SOFT_SCROLLBACK=y
CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_DUMMY_CONSOLE_COLUMNS=80
CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_SEQ_DEVICE=y
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_PCM_TIMER=y
CONFIG_SND_HRTIMER=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_MAX_CARDS=32
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_PROC_FS=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
CONFIG_SND_DEBUG=y
# CONFIG_SND_DEBUG_VERBOSE is not set
CONFIG_SND_PCM_XRUN_DEBUG=y
CONFIG_SND_VMASTER=y
CONFIG_SND_DMA_SGBUF=y
CONFIG_SND_SEQUENCER=y
CONFIG_SND_SEQ_DUMMY=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
CONFIG_SND_SEQ_MIDI_EVENT=y
# CONFIG_SND_SEQ_MIDI is not set
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
CONFIG_SND_DRIVERS=y
# CONFIG_SND_PCSP is not set
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_ALOOP is not set
# CONFIG_SND_VIRMIDI is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_PCI=y
# CONFIG_SND_AD1889 is not set
# CONFIG_SND_ALS300 is not set
# CONFIG_SND_ALS4000 is not set
# CONFIG_SND_ALI5451 is not set
# CONFIG_SND_ASIHPI is not set
# CONFIG_SND_ATIIXP is not set
# CONFIG_SND_ATIIXP_MODEM is not set
# CONFIG_SND_AU8810 is not set
# CONFIG_SND_AU8820 is not set
# CONFIG_SND_AU8830 is not set
# CONFIG_SND_AW2 is not set
# CONFIG_SND_AZT3328 is not set
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CTXFI is not set
# CONFIG_SND_DARLA20 is not set
# CONFIG_SND_GINA20 is not set
# CONFIG_SND_LAYLA20 is not set
# CONFIG_SND_DARLA24 is not set
# CONFIG_SND_GINA24 is not set
# CONFIG_SND_LAYLA24 is not set
# CONFIG_SND_MONA is not set
# CONFIG_SND_MIA is not set
# CONFIG_SND_ECHO3G is not set
# CONFIG_SND_INDIGO is not set
# CONFIG_SND_INDIGOIO is not set
# CONFIG_SND_INDIGODJ is not set
# CONFIG_SND_INDIGOIOX is not set
# CONFIG_SND_INDIGODJX is not set
# CONFIG_SND_EMU10K1 is not set
# CONFIG_SND_EMU10K1_SEQ is not set
# CONFIG_SND_EMU10K1X is not set
# CONFIG_SND_ENS1370 is not set
# CONFIG_SND_ENS1371 is not set
# CONFIG_SND_ES1938 is not set
# CONFIG_SND_ES1968 is not set
# CONFIG_SND_FM801 is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
# CONFIG_SND_INTEL8X0M is not set
# CONFIG_SND_KORG1212 is not set
# CONFIG_SND_LOLA is not set
# CONFIG_SND_LX6464ES is not set
# CONFIG_SND_MAESTRO3 is not set
# CONFIG_SND_MIXART is not set
# CONFIG_SND_NM256 is not set
# CONFIG_SND_PCXHR is not set
# CONFIG_SND_RIPTIDE is not set
# CONFIG_SND_RME32 is not set
# CONFIG_SND_RME96 is not set
# CONFIG_SND_RME9652 is not set
# CONFIG_SND_SE6X is not set
# CONFIG_SND_SONICVIBES is not set
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
#
# HD-Audio
#
CONFIG_SND_HDA=y
CONFIG_SND_HDA_INTEL=y
CONFIG_SND_HDA_HWDEP=y
# CONFIG_SND_HDA_RECONFIG is not set
# CONFIG_SND_HDA_INPUT_BEEP is not set
# CONFIG_SND_HDA_PATCH_LOADER is not set
# CONFIG_SND_HDA_CODEC_REALTEK is not set
# CONFIG_SND_HDA_CODEC_ANALOG is not set
# CONFIG_SND_HDA_CODEC_SIGMATEL is not set
# CONFIG_SND_HDA_CODEC_VIA is not set
# CONFIG_SND_HDA_CODEC_HDMI is not set
# CONFIG_SND_HDA_CODEC_CIRRUS is not set
# CONFIG_SND_HDA_CODEC_CONEXANT is not set
# CONFIG_SND_HDA_CODEC_CA0110 is not set
# CONFIG_SND_HDA_CODEC_CA0132 is not set
# CONFIG_SND_HDA_CODEC_CMEDIA is not set
# CONFIG_SND_HDA_CODEC_SI3054 is not set
# CONFIG_SND_HDA_GENERIC is not set
CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
CONFIG_SND_HDA_CORE=y
CONFIG_SND_HDA_I915=y
CONFIG_SND_HDA_PREALLOC_SIZE=64
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_USX2Y is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_US122L is not set
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_BCD2000 is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_VARIAX is not set
CONFIG_SND_PCMCIA=y
# CONFIG_SND_VXPOCKET is not set
# CONFIG_SND_PDAUDIOCF is not set
# CONFIG_SND_SOC is not set
CONFIG_SND_X86=y
CONFIG_HDMI_LPE_AUDIO=y
#
# HID support
#
CONFIG_HID=y
# CONFIG_HID_BATTERY_STRENGTH is not set
CONFIG_HIDRAW=y
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y
#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACCUTOUCH is not set
# CONFIG_HID_ACRUX is not set
CONFIG_HID_APPLE=y
# CONFIG_HID_APPLEIR is not set
# CONFIG_HID_ASUS is not set
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=y
# CONFIG_HID_BETOP_FF is not set
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
# CONFIG_HID_CORSAIR is not set
# CONFIG_HID_PRODIKEYS is not set
# CONFIG_HID_CMEDIA is not set
CONFIG_HID_CYPRESS=y
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_ELO is not set
CONFIG_HID_EZKEY=y
# CONFIG_HID_GEMBIRD is not set
# CONFIG_HID_GFRM is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
CONFIG_HID_GYRATION=y
# CONFIG_HID_ICADE is not set
CONFIG_HID_ITE=y
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=y
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LED is not set
# CONFIG_HID_LENOVO is not set
CONFIG_HID_LOGITECH=y
# CONFIG_HID_LOGITECH_DJ is not set
# CONFIG_HID_LOGITECH_HIDPP is not set
CONFIG_LOGITECH_FF=y
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_LOGIWHEELS_FF=y
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MAYFLASH is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTI is not set
CONFIG_HID_NTRIG=y
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
# CONFIG_HID_PENMOUNT is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RETRODE is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_SONY_FF is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEELSERIES is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_RMI is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
CONFIG_HID_TOPSEED=y
# CONFIG_HID_THINGM is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_WIIMOTE is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_ALPS is not set
#
# USB HID support
#
CONFIG_USB_HID=y
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
#
# I2C HID support
#
# CONFIG_I2C_HID is not set
#
# Intel ISH HID support
#
# CONFIG_INTEL_ISH_HID is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_PCI=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
#
# Miscellaneous USB options
#
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
CONFIG_USB_MON=y
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_EHCI_PCI=y
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_FOTG210_HCD is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PCI=y
# CONFIG_USB_OHCI_HCD_PLATFORM is not set
CONFIG_USB_UHCI_HCD=y
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HCD_TEST_MODE is not set
#
# USB Device Class drivers
#
# CONFIG_USB_ACM is not set
CONFIG_USB_PRINTER=y
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_REALTEK is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_STORAGE_ENE_UB6250 is not set
# CONFIG_USB_UAS is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USBIP_CORE is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_DWC3 is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_CHIPIDEA is not set
# CONFIG_USB_ISP1760 is not set
#
# USB port drivers
#
# CONFIG_USB_SERIAL is not set
#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_SISUSBVGA is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_CHAOSKEY is not set
CONFIG_USB_ATM=y
# CONFIG_USB_SPEEDTOUCH is not set
# CONFIG_USB_CXACRU is not set
# CONFIG_USB_UEAGLEATM is not set
# CONFIG_USB_XUSBATM is not set
#
# USB Physical Layer drivers
#
# CONFIG_USB_PHY is not set
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_GADGET is not set
CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=y
# CONFIG_TYPEC_FUSB302 is not set
CONFIG_TYPEC_UCSI=y
CONFIG_UCSI_ACPI=y
# CONFIG_TYPEC_TPS6598X is not set
# CONFIG_USB_LED_TRIG is not set
# CONFIG_USB_ULPI_BUS is not set
# CONFIG_UWB is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_CLASS_FLASH is not set
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
#
# LED drivers
#
# CONFIG_LEDS_APU is not set
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_LM3642 is not set
# CONFIG_LEDS_PCA9532 is not set
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_LP5562 is not set
# CONFIG_LEDS_LP8501 is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_CLEVO_MAIL is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA963X is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_INTEL_SS4200 is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_TLC591XX is not set
# CONFIG_LEDS_LM355x is not set
#
# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
#
# CONFIG_LEDS_BLINKM is not set
# CONFIG_LEDS_MLXCPLD is not set
# CONFIG_LEDS_USER is not set
# CONFIG_LEDS_NIC78BX is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
# CONFIG_LEDS_TRIGGER_TIMER is not set
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
# CONFIG_LEDS_TRIGGER_DISK is not set
# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
# CONFIG_LEDS_TRIGGER_CPU is not set
# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
# CONFIG_LEDS_TRIGGER_CAMERA is not set
# CONFIG_LEDS_TRIGGER_PANIC is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EDAC=y
CONFIG_EDAC_LEGACY_SYSFS=y
# CONFIG_EDAC_DEBUG is not set
CONFIG_EDAC_DECODE_MCE=y
# CONFIG_EDAC_AMD64 is not set
# CONFIG_EDAC_E752X is not set
# CONFIG_EDAC_I82975X is not set
# CONFIG_EDAC_I3000 is not set
# CONFIG_EDAC_I3200 is not set
# CONFIG_EDAC_IE31200 is not set
# CONFIG_EDAC_X38 is not set
# CONFIG_EDAC_I5400 is not set
# CONFIG_EDAC_I7CORE is not set
# CONFIG_EDAC_I5000 is not set
# CONFIG_EDAC_I5100 is not set
# CONFIG_EDAC_I7300 is not set
# CONFIG_EDAC_SBRIDGE is not set
# CONFIG_EDAC_SKX is not set
# CONFIG_EDAC_PND2 is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_SYSTOHC=y
CONFIG_RTC_SYSTOHC_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
# CONFIG_RTC_NVMEM is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_ABB5ZES3 is not set
# CONFIG_RTC_DRV_ABX80X is not set
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8523 is not set
# CONFIG_RTC_DRV_PCF85063 is not set
# CONFIG_RTC_DRV_PCF85363 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8010 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV8803 is not set
#
# SPI RTC drivers
#
CONFIG_RTC_I2C_AND_SPI=y
#
# SPI and I2C RTC drivers
#
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_PCF2127 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set
#
# Platform RTC drivers
#
CONFIG_RTC_DRV_CMOS=y
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1685_FAMILY is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_DS2404 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_FTRTC010 is not set
#
# HID Sensor RTC drivers
#
# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set
#
# DMA Devices
#
CONFIG_DMA_ENGINE=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DMA_ACPI=y
# CONFIG_ALTERA_MSGDMA is not set
# CONFIG_INTEL_IDMA64 is not set
# CONFIG_INTEL_IOATDMA is not set
# CONFIG_QCOM_HIDMA_MGMT is not set
# CONFIG_QCOM_HIDMA is not set
CONFIG_DW_DMAC_CORE=y
# CONFIG_DW_DMAC is not set
# CONFIG_DW_DMAC_PCI is not set
CONFIG_HSU_DMA=y
#
# DMA Clients
#
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
#
# DMABUF options
#
CONFIG_SYNC_FILE=y
# CONFIG_SW_SYNC is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
CONFIG_IRQ_BYPASS_MANAGER=y
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRTIO=y
#
# Virtio drivers
#
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
# CONFIG_VIRTIO_BALLOON is not set
CONFIG_VIRTIO_INPUT=y
# CONFIG_VIRTIO_MMIO is not set
#
# Microsoft Hyper-V guest support
#
# CONFIG_HYPERV is not set
# CONFIG_HYPERV_TSCPAGE is not set
#
# Xen driver support
#
CONFIG_XEN_BALLOON=y
CONFIG_XEN_SCRUB_PAGES=y
CONFIG_XEN_DEV_EVTCHN=y
CONFIG_XEN_BACKEND=y
CONFIG_XENFS=y
CONFIG_XEN_COMPAT_XENFS=y
CONFIG_XEN_SYS_HYPERVISOR=y
CONFIG_XEN_XENBUS_FRONTEND=y
CONFIG_XEN_GNTDEV=y
CONFIG_XEN_GRANT_DEV_ALLOC=y
CONFIG_SWIOTLB_XEN=y
CONFIG_XEN_PCIDEV_BACKEND=y
CONFIG_XEN_PVCALLS_FRONTEND=y
CONFIG_XEN_PVCALLS_BACKEND=y
CONFIG_XEN_PRIVCMD=y
CONFIG_XEN_ACPI_PROCESSOR=y
CONFIG_XEN_MCE_LOG=y
CONFIG_XEN_HAVE_PVMMU=y
CONFIG_XEN_EFI=y
CONFIG_XEN_AUTO_XLATE=y
CONFIG_XEN_ACPI=y
CONFIG_XEN_SYMS=y
CONFIG_XEN_HAVE_VPMU=y
# CONFIG_STAGING is not set
CONFIG_X86_PLATFORM_DEVICES=y
# CONFIG_ACERHDF is not set
# CONFIG_ASUS_LAPTOP is not set
# CONFIG_DELL_LAPTOP is not set
# CONFIG_DELL_SMO8800 is not set
# CONFIG_DELL_RBTN is not set
# CONFIG_FUJITSU_LAPTOP is not set
# CONFIG_FUJITSU_TABLET is not set
# CONFIG_AMILO_RFKILL is not set
# CONFIG_HP_ACCEL is not set
# CONFIG_HP_WIRELESS is not set
# CONFIG_MSI_LAPTOP is not set
# CONFIG_PANASONIC_LAPTOP is not set
# CONFIG_COMPAL_LAPTOP is not set
# CONFIG_SONY_LAPTOP is not set
# CONFIG_IDEAPAD_LAPTOP is not set
# CONFIG_THINKPAD_ACPI is not set
# CONFIG_SENSORS_HDAPS is not set
# CONFIG_INTEL_MENLOW is not set
CONFIG_EEEPC_LAPTOP=y
# CONFIG_ASUS_WIRELESS is not set
# CONFIG_ACPI_WMI is not set
# CONFIG_TOPSTAR_LAPTOP is not set
# CONFIG_TOSHIBA_BT_RFKILL is not set
# CONFIG_TOSHIBA_HAPS is not set
# CONFIG_ACPI_CMPC is not set
# CONFIG_INTEL_HID_EVENT is not set
# CONFIG_INTEL_VBTN is not set
# CONFIG_INTEL_IPS is not set
# CONFIG_INTEL_PMC_CORE is not set
# CONFIG_IBM_RTL is not set
# CONFIG_SAMSUNG_LAPTOP is not set
# CONFIG_INTEL_OAKTRAIL is not set
# CONFIG_SAMSUNG_Q10 is not set
# CONFIG_APPLE_GMUX is not set
# CONFIG_INTEL_RST is not set
# CONFIG_INTEL_SMARTCONNECT is not set
# CONFIG_PVPANIC is not set
# CONFIG_INTEL_PMC_IPC is not set
# CONFIG_SURFACE_PRO3_BUTTON is not set
# CONFIG_INTEL_PUNIT_IPC is not set
# CONFIG_MLX_PLATFORM is not set
# CONFIG_MLX_CPLD_PLATFORM is not set
# CONFIG_INTEL_TURBO_MAX_3 is not set
CONFIG_PMC_ATOM=y
# CONFIG_CHROME_PLATFORMS is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y
#
# Common Clock Framework
#
# CONFIG_COMMON_CLK_SI5351 is not set
# CONFIG_COMMON_CLK_CDCE706 is not set
# CONFIG_COMMON_CLK_CS2000_CP is not set
# CONFIG_COMMON_CLK_NXP is not set
# CONFIG_COMMON_CLK_PXA is not set
# CONFIG_COMMON_CLK_PIC32 is not set
# CONFIG_HWSPINLOCK is not set
#
# Clock Source drivers
#
CONFIG_CLKEVT_I8253=y
CONFIG_I8253_LOCK=y
CONFIG_CLKBLD_I8253=y
# CONFIG_ATMEL_PIT is not set
# CONFIG_SH_TIMER_CMT is not set
# CONFIG_SH_TIMER_MTU2 is not set
# CONFIG_SH_TIMER_TMU is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_MAILBOX=y
CONFIG_PCC=y
# CONFIG_ALTERA_MBOX is not set
CONFIG_IOMMU_API=y
CONFIG_IOMMU_SUPPORT=y
#
# Generic IOMMU Pagetable Support
#
CONFIG_IOMMU_IOVA=y
CONFIG_AMD_IOMMU=y
# CONFIG_AMD_IOMMU_V2 is not set
CONFIG_DMAR_TABLE=y
CONFIG_INTEL_IOMMU=y
# CONFIG_INTEL_IOMMU_SVM is not set
# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
CONFIG_INTEL_IOMMU_FLOPPY_WA=y
# CONFIG_IRQ_REMAP is not set
#
# Remoteproc drivers
#
# CONFIG_REMOTEPROC is not set
#
# Rpmsg drivers
#
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_VIRTIO is not set
#
# SOC (System On Chip) specific Drivers
#
#
# Amlogic SoC drivers
#
#
# Broadcom SoC drivers
#
#
# i.MX SoC drivers
#
#
# Qualcomm SoC drivers
#
# CONFIG_SUNXI_SRAM is not set
# CONFIG_SOC_TI is not set
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_NTB is not set
# CONFIG_VME_BUS is not set
# CONFIG_PWM is not set
#
# IRQ chip support
#
CONFIG_ARM_GIC_MAX_NR=1
# CONFIG_ARM_GIC_V3_ITS is not set
# CONFIG_IPACK_BUS is not set
# CONFIG_RESET_CONTROLLER is not set
# CONFIG_FMC is not set
#
# PHY Subsystem
#
# CONFIG_GENERIC_PHY is not set
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_PXA_28NM_HSIC is not set
# CONFIG_PHY_PXA_28NM_USB2 is not set
# CONFIG_POWERCAP is not set
# CONFIG_MCB is not set
#
# Performance monitor support
#
CONFIG_RAS=y
# CONFIG_THUNDERBOLT is not set
#
# Android
#
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
CONFIG_ANDROID_BINDER_DEVICES="binder0,binder1,binder2,binder3,binder4,binder5,binder6,binder7,binder8,binder9,binder10,binder11,binder12,binder13,binder14,binder15,binder16,binder17,binder18,binder19,binder20,binder21,binder22,binder23,binder24,binder25,binder26,binder27,binder28,binder29,binder30,binder31"
# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set
# CONFIG_LIBNVDIMM is not set
CONFIG_DAX=y
# CONFIG_DEV_DAX is not set
# CONFIG_NVMEM is not set
# CONFIG_STM is not set
# CONFIG_INTEL_TH is not set
# CONFIG_FPGA is not set
#
# FSI support
#
# CONFIG_FSI is not set
#
# Firmware Drivers
#
# CONFIG_EDD is not set
CONFIG_FIRMWARE_MEMMAP=y
# CONFIG_DELL_RBU is not set
# CONFIG_DCDBAS is not set
CONFIG_DMIID=y
# CONFIG_DMI_SYSFS is not set
CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
# CONFIG_ISCSI_IBFT_FIND is not set
# CONFIG_FW_CFG_SYSFS is not set
# CONFIG_GOOGLE_FIRMWARE is not set
#
# EFI (Extensible Firmware Interface) Support
#
CONFIG_EFI_VARS=y
CONFIG_EFI_ESRT=y
CONFIG_EFI_RUNTIME_MAP=y
# CONFIG_EFI_FAKE_MEMMAP is not set
CONFIG_EFI_RUNTIME_WRAPPERS=y
# CONFIG_EFI_BOOTLOADER_CONTROL is not set
# CONFIG_EFI_CAPSULE_LOADER is not set
# CONFIG_EFI_TEST is not set
# CONFIG_EFI_DEV_PATH_PARSER is not set
#
# Tegra firmware driver
#
#
# File systems
#
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_FS_IOMAP=y
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
CONFIG_EXT4_FS=y
CONFIG_EXT4_USE_FOR_EXT2=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_EXT4_FS_ENCRYPTION=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
# CONFIG_F2FS_FS is not set
# CONFIG_FS_DAX is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_EXPORTFS=y
# CONFIG_EXPORTFS_BLOCK_OPS is not set
CONFIG_FILE_LOCKING=y
CONFIG_MANDATORY_FILE_LOCKING=y
CONFIG_FS_ENCRYPTION=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
# CONFIG_QUOTA_DEBUG is not set
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
CONFIG_QUOTACTL_COMPAT=y
CONFIG_AUTOFS4_FS=y
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_OVERLAY_FS=y
CONFIG_OVERLAY_FS_REDIRECT_DIR=y
CONFIG_OVERLAY_FS_INDEX=y
#
# Caches
#
CONFIG_FSCACHE=y
# CONFIG_FSCACHE_STATS is not set
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
# CONFIG_CACHEFILES is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_PROC_CHILDREN=y
CONFIG_KERNFS=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
CONFIG_HUGETLBFS=y
CONFIG_HUGETLB_PAGE=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
# CONFIG_NFS_V4_1 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_FSCACHE is not set
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
# CONFIG_NFSD is not set
CONFIG_GRACE_PERIOD=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_9P_FS=y
# CONFIG_9P_FSCACHE is not set
# CONFIG_9P_FS_POSIX_ACL is not set
# CONFIG_9P_FS_SECURITY is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
#
# printk and dmesg options
#
CONFIG_PRINTK_TIME=y
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_DYNAMIC_DEBUG is not set
#
# Compile-time checks and compiler options
#
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
# CONFIG_GDB_SCRIPTS is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_READABLE_ASM is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_PAGE_OWNER is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
CONFIG_SECTION_MISMATCH_WARN_ONLY=y
CONFIG_FRAME_POINTER=y
# CONFIG_STACK_VALIDATION is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
CONFIG_MAGIC_SYSRQ=y
CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
CONFIG_MAGIC_SYSRQ_SERIAL=y
CONFIG_DEBUG_KERNEL=y
#
# Memory Debugging
#
CONFIG_PAGE_EXTENSION=y
# CONFIG_DEBUG_PAGEALLOC is not set
CONFIG_PAGE_POISONING=y
CONFIG_PAGE_POISONING_NO_SANITY=y
# CONFIG_PAGE_POISONING_ZERO is not set
# CONFIG_DEBUG_PAGE_REF is not set
# CONFIG_DEBUG_RODATA_TEST is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
CONFIG_HAVE_DEBUG_KMEMLEAK=y
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_VM=y
CONFIG_DEBUG_VM_VMACACHE=y
# CONFIG_DEBUG_VM_RB is not set
# CONFIG_DEBUG_VM_PGFLAGS is not set
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
# CONFIG_DEBUG_VIRTUAL is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PER_CPU_MAPS is not set
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_ARCH_KASAN=y
CONFIG_KASAN=y
# CONFIG_KASAN_OUTLINE is not set
CONFIG_KASAN_INLINE=y
# CONFIG_TEST_KASAN is not set
CONFIG_ARCH_HAS_KCOV=y
CONFIG_KCOV=y
CONFIG_KCOV_ENABLE_COMPARISONS=y
CONFIG_KCOV_INSTRUMENT_ALL=y
# CONFIG_DEBUG_SHIRQ is not set
#
# Debug Lockups and Hangs
#
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_HARDLOCKUP_DETECTOR_PERF=y
CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=1
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
CONFIG_WQ_WATCHDOG=y
CONFIG_PANIC_ON_OOPS=y
CONFIG_PANIC_ON_OOPS_VALUE=1
CONFIG_PANIC_TIMEOUT=86400
# CONFIG_SCHED_DEBUG is not set
CONFIG_SCHED_INFO=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_STACK_END_CHECK=y
# CONFIG_DEBUG_TIMEKEEPING is not set
#
# Lock Debugging (spinlocks, mutexes, etc...)
#
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
CONFIG_DEBUG_LOCK_ALLOC=y
CONFIG_PROVE_LOCKING=y
CONFIG_LOCKDEP=y
# CONFIG_LOCK_STAT is not set
CONFIG_LOCKDEP_CROSSRELEASE=y
CONFIG_LOCKDEP_COMPLETIONS=y
CONFIG_BOOTPARAM_LOCKDEP_CROSSRELEASE_FULLSTACK=y
# CONFIG_DEBUG_LOCKDEP is not set
CONFIG_DEBUG_ATOMIC_SLEEP=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
CONFIG_TRACE_IRQFLAGS=y
CONFIG_STACKTRACE=y
# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
# CONFIG_DEBUG_KOBJECT is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_PI_LIST=y
# CONFIG_DEBUG_SG is not set
CONFIG_DEBUG_NOTIFIERS=y
# CONFIG_DEBUG_CREDENTIALS is not set
#
# RCU Debugging
#
CONFIG_PROVE_RCU=y
# CONFIG_TORTURE_TEST is not set
# CONFIG_RCU_PERF_TEST is not set
# CONFIG_RCU_TORTURE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=120
# CONFIG_RCU_TRACE is not set
# CONFIG_RCU_EQS_DEBUG is not set
# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
# CONFIG_NOTIFIER_ERROR_INJECTION is not set
CONFIG_FAULT_INJECTION=y
CONFIG_FAILSLAB=y
CONFIG_FAIL_PAGE_ALLOC=y
CONFIG_FAIL_MAKE_REQUEST=y
CONFIG_FAIL_IO_TIMEOUT=y
CONFIG_FAIL_FUTEX=y
CONFIG_FAULT_INJECTION_DEBUG_FS=y
# CONFIG_LATENCYTOP is not set
CONFIG_USER_STACKTRACE_SUPPORT=y
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_FENTRY=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACE_CLOCK=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_TRACING=y
CONFIG_GENERIC_TRACER=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_HWLAT_TRACER is not set
# CONFIG_FTRACE_SYSCALLS is not set
# CONFIG_TRACER_SNAPSHOT is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KPROBE_EVENTS=y
CONFIG_UPROBE_EVENTS=y
CONFIG_BPF_EVENTS=y
CONFIG_PROBE_EVENTS=y
# CONFIG_FTRACE_STARTUP_TEST is not set
# CONFIG_MMIOTRACE is not set
# CONFIG_HIST_TRIGGERS is not set
# CONFIG_TRACEPOINT_BENCHMARK is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_RING_BUFFER_STARTUP_TEST is not set
# CONFIG_TRACE_EVAL_MAP_FILE is not set
CONFIG_PROVIDE_OHCI1394_DMA_INIT=y
# CONFIG_DMA_API_DEBUG is not set
#
# Runtime Testing
#
# CONFIG_LKDTM is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_SORT is not set
# CONFIG_KPROBES_SANITY_TEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_INTERVAL_TREE_TEST is not set
# CONFIG_PERCPU_TEST is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_FIND_BIT is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_MEMTEST is not set
CONFIG_BUG_ON_DATA_CORRUPTION=y
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set
# CONFIG_UBSAN is not set
CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
# CONFIG_STRICT_DEVMEM is not set
CONFIG_EARLY_PRINTK_USB=y
CONFIG_X86_VERBOSE_BOOTUP=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_DBGP=y
# CONFIG_EARLY_PRINTK_EFI is not set
# CONFIG_EARLY_PRINTK_USB_XDBC is not set
# CONFIG_X86_PTDUMP_CORE is not set
# CONFIG_X86_PTDUMP is not set
# CONFIG_EFI_PGT_DUMP is not set
# CONFIG_DEBUG_WX is not set
CONFIG_DOUBLEFAULT=y
# CONFIG_DEBUG_TLBFLUSH is not set
# CONFIG_IOMMU_STRESS is not set
CONFIG_HAVE_MMIOTRACE_SUPPORT=y
# CONFIG_X86_DECODER_SELFTEST is not set
CONFIG_IO_DELAY_TYPE_0X80=0
CONFIG_IO_DELAY_TYPE_0XED=1
CONFIG_IO_DELAY_TYPE_UDELAY=2
CONFIG_IO_DELAY_TYPE_NONE=3
CONFIG_IO_DELAY_0X80=y
# CONFIG_IO_DELAY_0XED is not set
# CONFIG_IO_DELAY_UDELAY is not set
# CONFIG_IO_DELAY_NONE is not set
CONFIG_DEFAULT_IO_DELAY_TYPE=0
CONFIG_DEBUG_BOOT_PARAMS=y
# CONFIG_CPA_DEBUG is not set
CONFIG_OPTIMIZE_INLINING=y
# CONFIG_DEBUG_ENTRY is not set
# CONFIG_DEBUG_NMI_SELFTEST is not set
CONFIG_X86_DEBUG_FPU=y
# CONFIG_PUNIT_ATOM_DEBUG is not set
# CONFIG_UNWINDER_ORC is not set
CONFIG_UNWINDER_FRAME_POINTER=y
# CONFIG_UNWINDER_GUESS is not set
#
# Security options
#
CONFIG_KEYS=y
CONFIG_KEYS_COMPAT=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_BIG_KEYS=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEY_DH_OPERATIONS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITY_WRITABLE_HOOKS=y
# CONFIG_SECURITYFS is not set
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
# CONFIG_INTEL_TXT is not set
CONFIG_LSM_MMAP_MIN_ADDR=65536
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
CONFIG_HARDENED_USERCOPY=y
# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set
CONFIG_FORTIFY_SOURCE=y
# CONFIG_STATIC_USERMODEHELPER is not set
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_LOADPIN is not set
# CONFIG_SECURITY_YAMA is not set
CONFIG_INTEGRITY=y
# CONFIG_INTEGRITY_SIGNATURE is not set
CONFIG_INTEGRITY_AUDIT=y
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_DEFAULT_SECURITY="selinux"
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_KPP=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECDH=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_USER=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_PCRYPT=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_MCRYPTD=y
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set
CONFIG_CRYPTO_ABLK_HELPER=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_GLUE_HELPER_X86=y
CONFIG_CRYPTO_ENGINE=y
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=y
CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_ECHAINIV=y
#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_CTS=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_KEYWRAP=y
#
# Hash modes
#
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_XCBC=y
CONFIG_CRYPTO_VMAC=y
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_CRC32C_INTEL=y
CONFIG_CRYPTO_CRC32=y
CONFIG_CRYPTO_CRC32_PCLMUL=y
CONFIG_CRYPTO_CRCT10DIF=y
CONFIG_CRYPTO_CRCT10DIF_PCLMUL=y
CONFIG_CRYPTO_GHASH=y
CONFIG_CRYPTO_POLY1305=y
CONFIG_CRYPTO_POLY1305_X86_64=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_RMD256=y
CONFIG_CRYPTO_RMD320=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA1_SSSE3=y
CONFIG_CRYPTO_SHA256_SSSE3=y
CONFIG_CRYPTO_SHA512_SSSE3=y
CONFIG_CRYPTO_SHA1_MB=y
CONFIG_CRYPTO_SHA256_MB=y
CONFIG_CRYPTO_SHA512_MB=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SM3=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y
CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL=y
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_AES_TI=y
CONFIG_CRYPTO_AES_X86_64=y
CONFIG_CRYPTO_AES_NI_INTEL=y
CONFIG_CRYPTO_ANUBIS=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_BLOWFISH_COMMON=y
CONFIG_CRYPTO_BLOWFISH_X86_64=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAMELLIA_X86_64=y
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64=y
CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64=y
CONFIG_CRYPTO_CAST_COMMON=y
CONFIG_CRYPTO_CAST5=y
CONFIG_CRYPTO_CAST5_AVX_X86_64=y
CONFIG_CRYPTO_CAST6=y
CONFIG_CRYPTO_CAST6_AVX_X86_64=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DES3_EDE_X86_64=y
CONFIG_CRYPTO_FCRYPT=y
CONFIG_CRYPTO_KHAZAD=y
CONFIG_CRYPTO_SALSA20=y
CONFIG_CRYPTO_SALSA20_X86_64=y
CONFIG_CRYPTO_CHACHA20=y
CONFIG_CRYPTO_CHACHA20_X86_64=y
CONFIG_CRYPTO_SEED=y
CONFIG_CRYPTO_SERPENT=y
CONFIG_CRYPTO_SERPENT_SSE2_X86_64=y
CONFIG_CRYPTO_SERPENT_AVX_X86_64=y
CONFIG_CRYPTO_SERPENT_AVX2_X86_64=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_TWOFISH_COMMON=y
CONFIG_CRYPTO_TWOFISH_X86_64=y
CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=y
CONFIG_CRYPTO_TWOFISH_AVX_X86_64=y
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=y
CONFIG_CRYPTO_LZ4HC=y
#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_HASH=y
CONFIG_CRYPTO_DRBG_CTR=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_USER_API=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_USER_API_AEAD=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_DEV_PADLOCK=y
CONFIG_CRYPTO_DEV_PADLOCK_AES=y
CONFIG_CRYPTO_DEV_PADLOCK_SHA=y
# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
CONFIG_CRYPTO_DEV_CCP=y
CONFIG_CRYPTO_DEV_CCP_DD=y
# CONFIG_CRYPTO_DEV_SP_CCP is not set
CONFIG_CRYPTO_DEV_QAT=y
CONFIG_CRYPTO_DEV_QAT_DH895xCC=y
CONFIG_CRYPTO_DEV_QAT_C3XXX=y
CONFIG_CRYPTO_DEV_QAT_C62X=y
CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=y
CONFIG_CRYPTO_DEV_QAT_C3XXXVF=y
CONFIG_CRYPTO_DEV_QAT_C62XVF=y
# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
CONFIG_CRYPTO_DEV_VIRTIO=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_PKCS7_TEST_KEY=y
CONFIG_SIGNED_PE_FILE_VERIFICATION=y
#
# Certificates for signature checking
#
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
CONFIG_SECONDARY_TRUSTED_KEYRING=y
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
CONFIG_HAVE_KVM=y
CONFIG_HAVE_KVM_IRQCHIP=y
CONFIG_HAVE_KVM_IRQFD=y
CONFIG_HAVE_KVM_IRQ_ROUTING=y
CONFIG_HAVE_KVM_EVENTFD=y
CONFIG_KVM_MMIO=y
CONFIG_KVM_ASYNC_PF=y
CONFIG_HAVE_KVM_MSI=y
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
CONFIG_KVM_VFIO=y
CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
CONFIG_KVM_COMPAT=y
CONFIG_HAVE_KVM_IRQ_BYPASS=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=y
CONFIG_KVM_INTEL=y
CONFIG_KVM_AMD=y
# CONFIG_KVM_MMU_AUDIT is not set
CONFIG_VHOST_NET=y
# CONFIG_VHOST_VSOCK is not set
CONFIG_VHOST=y
# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_RATIONAL=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_NET_UTILS=y
CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
CONFIG_CRC4=y
# CONFIG_CRC7 is not set
CONFIG_LIBCRC32C=y
# CONFIG_CRC8 is not set
# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_LZ4_COMPRESS=y
CONFIG_LZ4HC_COMPRESS=y
CONFIG_LZ4_DECOMPRESS=y
CONFIG_XZ_DEC=y
CONFIG_XZ_DEC_X86=y
CONFIG_XZ_DEC_POWERPC=y
CONFIG_XZ_DEC_IA64=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_XZ_DEC_SPARC=y
CONFIG_XZ_DEC_BCJ=y
# CONFIG_XZ_DEC_TEST is not set
CONFIG_DECOMPRESS_GZIP=y
CONFIG_DECOMPRESS_BZIP2=y
CONFIG_DECOMPRESS_LZMA=y
CONFIG_DECOMPRESS_XZ=y
CONFIG_DECOMPRESS_LZO=y
CONFIG_DECOMPRESS_LZ4=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_INTERVAL_TREE=y
CONFIG_RADIX_TREE_MULTIORDER=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAS_DMA=y
# CONFIG_DMA_NOOP_OPS is not set
# CONFIG_DMA_VIRT_OPS is not set
CONFIG_CHECK_SIGNATURE=y
CONFIG_CPU_RMAP=y
CONFIG_DQL=y
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_NLATTR=y
CONFIG_CLZ_TAB=y
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set
# CONFIG_IRQ_POLL is not set
CONFIG_MPILIB=y
CONFIG_OID_REGISTRY=y
CONFIG_UCS2_STRING=y
CONFIG_FONT_SUPPORT=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
# CONFIG_SG_SPLIT is not set
CONFIG_SG_POOL=y
CONFIG_ARCH_HAS_SG_CHAIN=y
CONFIG_ARCH_HAS_PMEM_API=y
CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
CONFIG_STACKDEPOT=y
CONFIG_SBITMAP=y
# CONFIG_STRING_SELFTEST is not set
[-- Attachment #3: raw.log --]
[-- Type: application/octet-stream, Size: 1048576 bytes --]
^ permalink raw reply
* [PATCH net-next v4] ip6_vti: adjust vti mtu according to mtu of lower device
From: Alexey Kodanev @ 2017-12-19 13:59 UTC (permalink / raw)
To: netdev
Cc: Steffen Klassert, David Miller, Petr Vorel, Shannon Nelson,
Alexey Kodanev
LTP/udp6_ipsec_vti tests fail when sending large UDP datagrams over
ip6_vti that require fragmentation and the underlying device has an
MTU smaller than 1500 plus some extra space for headers. This happens
because ip6_vti, by default, sets MTU to ETH_DATA_LEN and not updating
it depending on a destination address or link parameter. Further
attempts to send UDP packets may succeed because pmtu gets updated on
ICMPV6_PKT_TOOBIG in vti6_err().
In case the lower device has larger MTU size, e.g. 9000, ip6_vti works
but not using the possible maximum size, output packets have 1500 limit.
The above cases require manual MTU setup after ip6_vti creation. However
ip_vti already updates MTU based on lower device with ip_tunnel_bind_dev().
Here is the example when the lower device MTU is set to 9000:
# ip a sh ltp_ns_veth2
ltp_ns_veth2@if7: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 9000 ...
inet 10.0.0.2/24 scope global ltp_ns_veth2
inet6 fd00::2/64 scope global
# ip li add vti6 type vti6 local fd00::2 remote fd00::1
# ip li show vti6
vti6@NONE: <POINTOPOINT,NOARP> mtu 1500 ...
link/tunnel6 fd00::2 peer fd00::1
After the patch:
# ip li add vti6 type vti6 local fd00::2 remote fd00::1
# ip li show vti6
vti6@NONE: <POINTOPOINT,NOARP> mtu 8832 ...
link/tunnel6 fd00::2 peer fd00::1
Reported-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Alexey Kodanev <alexey.kodanev@oracle.com>
---
v4: * remove an empty line between variable declarations
* update the commit message to reflect unexpected behavior with an MTU
larger than 1500.
v3: * fix style issue with curly braces around single-statement if block
v2: * cleanup commit message issues (thanks to Shannon)
* handle the case when we don't have route but have device parameter
* cast new MTU to int and then check the maximum (tdev->mtu can be
less than dev->hard_header_len)
net/ipv6/ip6_vti.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/net/ipv6/ip6_vti.c b/net/ipv6/ip6_vti.c
index dbb74f3..18caa95 100644
--- a/net/ipv6/ip6_vti.c
+++ b/net/ipv6/ip6_vti.c
@@ -626,6 +626,7 @@ static void vti6_link_config(struct ip6_tnl *t)
{
struct net_device *dev = t->dev;
struct __ip6_tnl_parm *p = &t->parms;
+ struct net_device *tdev = NULL;
memcpy(dev->dev_addr, &p->laddr, sizeof(struct in6_addr));
memcpy(dev->broadcast, &p->raddr, sizeof(struct in6_addr));
@@ -638,6 +639,25 @@ static void vti6_link_config(struct ip6_tnl *t)
dev->flags |= IFF_POINTOPOINT;
else
dev->flags &= ~IFF_POINTOPOINT;
+
+ if (p->flags & IP6_TNL_F_CAP_XMIT) {
+ int strict = (ipv6_addr_type(&p->raddr) &
+ (IPV6_ADDR_MULTICAST | IPV6_ADDR_LINKLOCAL));
+ struct rt6_info *rt = rt6_lookup(t->net,
+ &p->raddr, &p->laddr,
+ p->link, strict);
+
+ if (rt)
+ tdev = rt->dst.dev;
+ ip6_rt_put(rt);
+ }
+
+ if (!tdev && p->link)
+ tdev = __dev_get_by_index(t->net, p->link);
+
+ if (tdev)
+ dev->mtu = max_t(int, tdev->mtu - dev->hard_header_len,
+ IPV6_MIN_MTU);
}
/**
--
1.7.1
^ permalink raw reply related
* [PATCH net-next] qed*: Utilize FW 8.33.1.0
From: Tomer Tayar @ 2017-12-19 14:05 UTC (permalink / raw)
To: davem, netdev
Cc: linux-rdma, linux-scsi, Tomer Tayar, Ariel Elior, Michal Kalderon,
Yuval Bason, Ram Amrani, Manish Chopra, Chad Dupuis,
Manish Rangankar
This patch advances all qed* drivers to use firmware 8.33.1.0.
This includes:
Modify core driver (qed) to utilize the new FW and initialize the device
with it. This is the lion's share of the patch, and includes changes to FW
interface files, device initialization flows, FW interaction flows, and
debug collection flows.
Modify Ethernet driver (qede) to make use of new FW in fastpath.
Modify RoCE/iWARP driver (qedr) to make use of new FW in fastpath.
Modify FCoE driver (qedf) to make use of new FW in fastpath.
Modify iSCSI driver (qedi) to make use of new FW in fastpath.
The changes are mostly in qed, and include changes in the FW interface
files, as well as updating the FW initialization and debug collection
code. Some modifications fix styling issues, and some are renaming ones
to allow distinction between different types of HW.
The protocol drivers have minor functional changes for this firmware.
Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: Yuval Bason <Yuval.Bason@cavium.com>
Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com>
Signed-off-by: Manish Chopra <Manish.Chopra@cavium.com>
Signed-off-by: Chad Dupuis <Chad.Dupuis@cavium.com>
Signed-off-by: Manish Rangankar <Manish.Rangankar@cavium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
---
Hi Dave,
Sorry for the very long patch.
The firmware changes are spread all over w/o a good modularity.
Please consider applying this to 'net-next'.
Thanks,
Tomer
---
drivers/infiniband/hw/qedr/main.c | 2 +-
drivers/infiniband/hw/qedr/qedr_hsi_rdma.h | 42 +-
drivers/net/ethernet/qlogic/qed/qed.h | 10 +-
drivers/net/ethernet/qlogic/qed/qed_cxt.c | 37 +-
drivers/net/ethernet/qlogic/qed/qed_cxt.h | 4 +-
drivers/net/ethernet/qlogic/qed/qed_dcbx.c | 4 +-
drivers/net/ethernet/qlogic/qed/qed_debug.c | 1168 +-
drivers/net/ethernet/qlogic/qed/qed_dev.c | 15 +-
drivers/net/ethernet/qlogic/qed/qed_fcoe.c | 10 +-
drivers/net/ethernet/qlogic/qed/qed_hsi.h | 10603 ++++++++++---------
drivers/net/ethernet/qlogic/qed/qed_hw.c | 70 +
drivers/net/ethernet/qlogic/qed/qed_hw.h | 4 +
.../net/ethernet/qlogic/qed/qed_init_fw_funcs.c | 1088 +-
drivers/net/ethernet/qlogic/qed/qed_init_ops.c | 22 +-
drivers/net/ethernet/qlogic/qed/qed_int.c | 8 +-
drivers/net/ethernet/qlogic/qed/qed_int.h | 2 +-
drivers/net/ethernet/qlogic/qed/qed_iscsi.c | 58 +-
drivers/net/ethernet/qlogic/qed/qed_iwarp.c | 33 +-
drivers/net/ethernet/qlogic/qed/qed_iwarp.h | 3 +-
drivers/net/ethernet/qlogic/qed/qed_l2.c | 118 +-
drivers/net/ethernet/qlogic/qed/qed_l2.h | 33 +-
drivers/net/ethernet/qlogic/qed/qed_ll2.c | 28 +-
drivers/net/ethernet/qlogic/qed/qed_mcp.c | 2 +-
drivers/net/ethernet/qlogic/qed/qed_rdma.c | 2 +-
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | 190 +-
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c | 8 +-
drivers/net/ethernet/qlogic/qed/qed_spq.c | 8 +-
drivers/net/ethernet/qlogic/qed/qed_sriov.c | 22 +-
drivers/net/ethernet/qlogic/qed/qed_sriov.h | 24 +
drivers/net/ethernet/qlogic/qede/qede.h | 6 +-
drivers/net/ethernet/qlogic/qede/qede_filter.c | 26 +-
drivers/net/ethernet/qlogic/qede/qede_main.c | 2 +-
drivers/scsi/qedf/drv_fcoe_fw_funcs.c | 35 +-
drivers/scsi/qedf/drv_fcoe_fw_funcs.h | 2 +-
drivers/scsi/qedf/qedf.h | 4 +-
drivers/scsi/qedf/qedf_els.c | 2 +-
drivers/scsi/qedf/qedf_hsi.h | 68 -
drivers/scsi/qedf/qedf_io.c | 22 +-
drivers/scsi/qedf/qedf_main.c | 12 +-
drivers/scsi/qedf/qedf_version.h | 8 +-
drivers/scsi/qedi/qedi_debugfs.c | 4 +-
drivers/scsi/qedi/qedi_fw.c | 59 +-
drivers/scsi/qedi/qedi_fw_api.c | 139 +-
drivers/scsi/qedi/qedi_fw_iscsi.h | 2 +-
drivers/scsi/qedi/qedi_gbl.h | 5 +-
drivers/scsi/qedi/qedi_iscsi.c | 9 +-
drivers/scsi/qedi/qedi_iscsi.h | 2 +-
drivers/scsi/qedi/qedi_main.c | 29 +-
drivers/scsi/qedi/qedi_version.h | 8 +-
include/linux/qed/common_hsi.h | 1264 ++-
include/linux/qed/eth_common.h | 396 +-
include/linux/qed/fcoe_common.h | 940 +-
include/linux/qed/iscsi_common.h | 1585 +--
include/linux/qed/iwarp_common.h | 17 +-
include/linux/qed/qed_eth_if.h | 38 +-
include/linux/qed/qed_if.h | 36 +-
include/linux/qed/qed_iscsi_if.h | 4 +-
include/linux/qed/qed_ll2_if.h | 2 +-
include/linux/qed/rdma_common.h | 25 +-
include/linux/qed/roce_common.h | 15 +-
include/linux/qed/storage_common.h | 91 +-
include/linux/qed/tcp_common.h | 165 +-
62 files changed, 10194 insertions(+), 8446 deletions(-)
diff --git a/drivers/infiniband/hw/qedr/main.c b/drivers/infiniband/hw/qedr/main.c
index 50812b3..a9c3378 100644
--- a/drivers/infiniband/hw/qedr/main.c
+++ b/drivers/infiniband/hw/qedr/main.c
@@ -264,7 +264,7 @@ static int qedr_register_device(struct qedr_dev *dev)
static int qedr_alloc_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int rc;
diff --git a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
index b7587f1..9df9322 100644
--- a/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
+++ b/drivers/infiniband/hw/qedr/qedr_hsi_rdma.h
@@ -164,6 +164,13 @@ struct rdma_srq_sge {
__le32 l_key;
};
+/* Rdma doorbell data for flags update */
+struct rdma_pwm_flags_data {
+ __le16 icid /* internal CID */;
+ u8 agg_flags /* aggregative flags */;
+ u8 reserved;
+};
+
/* Rdma doorbell data for SQ and RQ */
struct rdma_pwm_val16_data {
__le16 icid;
@@ -180,12 +187,16 @@ struct rdma_pwm_val32_data {
__le16 icid;
u8 agg_flags;
u8 params;
-#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3
-#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0
-#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
-#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2
-#define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x1F
-#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 3
+#define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3
+#define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0
+#define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
+#define RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2
+#define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1
+#define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT 3
+#define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1
+#define RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT 4
+#define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x7
+#define RDMA_PWM_VAL32_DATA_RESERVED_SHIFT 5
__le32 value;
};
@@ -492,8 +503,11 @@ struct rdma_sq_fmr_wqe {
#define RDMA_SQ_FMR_WQE_DIF_VALIDATE_APP_TAG_SHIFT 5
#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_MASK 0x1
#define RDMA_SQ_FMR_WQE_DIF_CRC_SEED_SHIFT 6
-#define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0x1FF
-#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 7
+#define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_MASK 0x1
+#define RDMA_SQ_FMR_WQE_DIF_RX_REF_TAG_CONST_SHIFT 7
+#define RDMA_SQ_FMR_WQE_RESERVED4_MASK 0xFF
+#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 8
+
__le32 Reserved5;
};
@@ -572,8 +586,10 @@ struct rdma_sq_fmr_wqe_3rd {
#define RDMA_SQ_FMR_WQE_3RD_DIF_VALIDATE_APP_TAG_SHIFT 5
#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_MASK 0x1
#define RDMA_SQ_FMR_WQE_3RD_DIF_CRC_SEED_SHIFT 6
-#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0x1FF
-#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_SHIFT 7
+#define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_MASK 0x1
+#define RDMA_SQ_FMR_WQE_3RD_DIF_RX_REF_TAG_CONST_SHIFT 7
+#define RDMA_SQ_FMR_WQE_3RD_RESERVED4_MASK 0xFF
+#define RDMA_SQ_FMR_WQE_RESERVED4_SHIFT 8
__le32 Reserved5;
};
@@ -618,8 +634,10 @@ struct rdma_sq_rdma_wqe {
#define RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4
#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1
#define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT 5
-#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK 0x3
-#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT 6
+#define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK 0x1
+#define RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT 6
+#define RDMA_SQ_RDMA_WQE_RESERVED0_MASK 0x1
+#define RDMA_SQ_RDMA_WQE_RESERVED0_SHIFT 7
u8 wqe_size;
u8 prev_wqe_size;
struct regpair remote_va;
diff --git a/drivers/net/ethernet/qlogic/qed/qed.h b/drivers/net/ethernet/qlogic/qed/qed.h
index 91003bc..a76185d 100644
--- a/drivers/net/ethernet/qlogic/qed/qed.h
+++ b/drivers/net/ethernet/qlogic/qed/qed.h
@@ -52,10 +52,10 @@
extern const struct qed_common_ops qed_common_ops_pass;
-#define QED_MAJOR_VERSION 8
-#define QED_MINOR_VERSION 10
-#define QED_REVISION_VERSION 11
-#define QED_ENGINEERING_VERSION 21
+#define QED_MAJOR_VERSION 8
+#define QED_MINOR_VERSION 33
+#define QED_REVISION_VERSION 0
+#define QED_ENGINEERING_VERSION 20
#define QED_VERSION \
((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
@@ -778,8 +778,8 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
return sw_fid;
}
-#define PURE_LB_TC 8
#define PKT_LB_TC 9
+#define MAX_NUM_VOQS_E4 20
int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.c b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
index afd07ad..08d6b87 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_cxt.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.c
@@ -86,22 +86,22 @@
/* connection context union */
union conn_context {
- struct core_conn_context core_ctx;
- struct eth_conn_context eth_ctx;
- struct iscsi_conn_context iscsi_ctx;
- struct fcoe_conn_context fcoe_ctx;
- struct roce_conn_context roce_ctx;
+ struct e4_core_conn_context core_ctx;
+ struct e4_eth_conn_context eth_ctx;
+ struct e4_iscsi_conn_context iscsi_ctx;
+ struct e4_fcoe_conn_context fcoe_ctx;
+ struct e4_roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
- struct iscsi_task_context iscsi_ctx;
- struct fcoe_task_context fcoe_ctx;
+ struct e4_iscsi_task_context iscsi_ctx;
+ struct e4_fcoe_task_context fcoe_ctx;
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
- struct rdma_task_context roce_ctx;
+ struct e4_rdma_task_context roce_ctx;
};
struct src_ent {
@@ -109,8 +109,8 @@ struct src_ent {
u64 next;
};
-#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
-#define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
+#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
+#define CDUT_SEG_ALIGNMET_IN_BYTES BIT((CDUT_SEG_ALIGNMET + 12))
#define CONN_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
@@ -742,7 +742,7 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count)
p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]);
qed_cxt_qm_iids(p_hwfn, &qm_iids);
- total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
+ total = qed_qm_pf_mem_size(qm_iids.cids,
qm_iids.vf_cids, qm_iids.tids,
p_hwfn->qm_info.num_pqs,
p_hwfn->qm_info.num_vf_pqs);
@@ -1496,20 +1496,24 @@ static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn)
}
}
-void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
+void qed_qm_init_pf(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, bool is_pf_loading)
{
- struct qed_qm_pf_rt_init_params params;
struct qed_qm_info *qm_info = &p_hwfn->qm_info;
+ struct qed_qm_pf_rt_init_params params;
+ struct qed_mcp_link_state *p_link;
struct qed_qm_iids iids;
memset(&iids, 0, sizeof(iids));
qed_cxt_qm_iids(p_hwfn, &iids);
+ p_link = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;
+
memset(¶ms, 0, sizeof(params));
params.port_id = p_hwfn->port_id;
params.pf_id = p_hwfn->rel_pf_id;
params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
- params.is_first_pf = p_hwfn->first_on_engine;
+ params.is_pf_loading = is_pf_loading;
params.num_pf_cids = iids.cids;
params.num_vf_cids = iids.vf_cids;
params.num_tids = iids.tids;
@@ -1520,6 +1524,7 @@ void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
params.num_vports = qm_info->num_vports;
params.pf_wfq = qm_info->pf_wfq;
params.pf_rl = qm_info->pf_rl;
+ params.link_speed = p_link->speed;
params.pq_params = qm_info->qm_pq_params;
params.vport_params = qm_info->qm_vport_params;
@@ -1883,7 +1888,7 @@ void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn)
void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
- qed_qm_init_pf(p_hwfn, p_ptt);
+ qed_qm_init_pf(p_hwfn, p_ptt, true);
qed_cm_init_pf(p_hwfn);
qed_dq_init_pf(p_hwfn);
qed_cdu_init_pf(p_hwfn);
@@ -2326,7 +2331,7 @@ int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
elem = (union type1_task_context *)elem_start;
SET_FIELD(elem->roce_ctx.tdif_context.flags1,
- TDIF_TASK_CONTEXT_REFTAGMASK, 0xf);
+ TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
}
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_cxt.h b/drivers/net/ethernet/qlogic/qed/qed_cxt.h
index 1783634..a4e9586 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_cxt.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_cxt.h
@@ -169,8 +169,10 @@ u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
*
* @param p_hwfn
* @param p_ptt
+ * @param is_pf_loading
*/
-void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
+void qed_qm_init_pf(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, bool is_pf_loading);
/**
* @brief Reconfigures QM pf on the fly
diff --git a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
index fe7c1f2..449777f 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dcbx.c
@@ -954,9 +954,7 @@ void qed_dcbx_set_pf_update_params(struct qed_dcbx_results *p_src,
struct pf_update_ramrod_data *p_dest)
{
struct protocol_dcb_data *p_dcb_data;
- bool update_flag = false;
-
- p_dest->pf_id = p_src->pf_id;
+ u8 update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_FCOE].update;
p_dest->update_fcoe_dcb_data_mode = update_flag;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_debug.c b/drivers/net/ethernet/qlogic/qed/qed_debug.c
index 03c3cf7..f694135 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_debug.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_debug.c
@@ -21,25 +21,26 @@ enum mem_groups {
MEM_GROUP_DMAE_MEM,
MEM_GROUP_CM_MEM,
MEM_GROUP_QM_MEM,
- MEM_GROUP_TM_MEM,
+ MEM_GROUP_DORQ_MEM,
MEM_GROUP_BRB_RAM,
MEM_GROUP_BRB_MEM,
MEM_GROUP_PRS_MEM,
- MEM_GROUP_SDM_MEM,
MEM_GROUP_IOR,
- MEM_GROUP_RAM,
MEM_GROUP_BTB_RAM,
- MEM_GROUP_RDIF_CTX,
- MEM_GROUP_TDIF_CTX,
- MEM_GROUP_CFC_MEM,
MEM_GROUP_CONN_CFC_MEM,
MEM_GROUP_TASK_CFC_MEM,
MEM_GROUP_CAU_PI,
MEM_GROUP_CAU_MEM,
MEM_GROUP_PXP_ILT,
+ MEM_GROUP_TM_MEM,
+ MEM_GROUP_SDM_MEM,
MEM_GROUP_PBUF,
+ MEM_GROUP_RAM,
MEM_GROUP_MULD_MEM,
MEM_GROUP_BTB_MEM,
+ MEM_GROUP_RDIF_CTX,
+ MEM_GROUP_TDIF_CTX,
+ MEM_GROUP_CFC_MEM,
MEM_GROUP_IGU_MEM,
MEM_GROUP_IGU_MSIX,
MEM_GROUP_CAU_SB,
@@ -54,25 +55,26 @@ enum mem_groups {
"DMAE_MEM",
"CM_MEM",
"QM_MEM",
- "TM_MEM",
+ "DORQ_MEM",
"BRB_RAM",
"BRB_MEM",
"PRS_MEM",
- "SDM_MEM",
"IOR",
- "RAM",
"BTB_RAM",
- "RDIF_CTX",
- "TDIF_CTX",
- "CFC_MEM",
"CONN_CFC_MEM",
"TASK_CFC_MEM",
"CAU_PI",
"CAU_MEM",
"PXP_ILT",
+ "TM_MEM",
+ "SDM_MEM",
"PBUF",
+ "RAM",
"MULD_MEM",
"BTB_MEM",
+ "RDIF_CTX",
+ "TDIF_CTX",
+ "CFC_MEM",
"IGU_MEM",
"IGU_MSIX",
"CAU_SB",
@@ -92,11 +94,6 @@ static u32 cond7(const u32 *r, const u32 *imm)
return ((r[0] >> imm[0]) & imm[1]) != imm[2];
}
-static u32 cond14(const u32 *r, const u32 *imm)
-{
- return (r[0] != imm[0]) && (((r[1] >> imm[1]) & imm[2]) == imm[3]);
-}
-
static u32 cond6(const u32 *r, const u32 *imm)
{
return (r[0] & imm[0]) != imm[1];
@@ -174,7 +171,6 @@ static u32(*cond_arr[]) (const u32 *r, const u32 *imm) = {
cond11,
cond12,
cond13,
- cond14,
};
/******************************* Data Types **********************************/
@@ -203,6 +199,8 @@ struct chip_defs {
struct platform_defs {
const char *name;
u32 delay_factor;
+ u32 dmae_thresh;
+ u32 log_thresh;
};
/* Storm constant definitions.
@@ -234,7 +232,7 @@ struct storm_defs {
/* Block constant definitions */
struct block_defs {
const char *name;
- bool has_dbg_bus[MAX_CHIP_IDS];
+ bool exists[MAX_CHIP_IDS];
bool associated_to_storm;
/* Valid only if associated_to_storm is true */
@@ -258,8 +256,8 @@ struct block_defs {
/* Reset register definitions */
struct reset_reg_defs {
u32 addr;
- u32 unreset_val;
bool exists[MAX_CHIP_IDS];
+ u32 unreset_val[MAX_CHIP_IDS];
};
struct grc_param_defs {
@@ -276,8 +274,8 @@ struct rss_mem_defs {
const char *mem_name;
const char *type_name;
u32 addr;
+ u32 entry_width;
u32 num_entries[MAX_CHIP_IDS];
- u32 entry_width[MAX_CHIP_IDS];
};
struct vfc_ram_defs {
@@ -294,7 +292,9 @@ struct big_ram_defs {
enum dbg_grc_params grc_param;
u32 addr_reg_addr;
u32 data_reg_addr;
- u32 num_of_blocks[MAX_CHIP_IDS];
+ u32 is_256b_reg_addr;
+ u32 is_256b_bit_offset[MAX_CHIP_IDS];
+ u32 ram_size[MAX_CHIP_IDS]; /* In dwords */
};
struct phy_defs {
@@ -358,20 +358,14 @@ struct phy_defs {
(arr)[i] = qed_rd(dev, ptt, addr); \
} while (0)
-#ifndef DWORDS_TO_BYTES
#define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD)
-#endif
-#ifndef BYTES_TO_DWORDS
#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
-#endif
-/* extra lines include a signature line + optional latency events line */
-#ifndef NUM_DBG_LINES
+/* Extra lines include a signature line + optional latency events line */
#define NUM_EXTRA_DBG_LINES(block_desc) \
(1 + ((block_desc)->has_latency_events ? 1 : 0))
#define NUM_DBG_LINES(block_desc) \
((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
-#endif
#define RAM_LINES_TO_DWORDS(lines) ((lines) * 2)
#define RAM_LINES_TO_BYTES(lines) \
@@ -424,9 +418,6 @@ struct phy_defs {
#define NUM_RSS_MEM_TYPES 5
#define NUM_BIG_RAM_TYPES 3
-#define BIG_RAM_BLOCK_SIZE_BYTES 128
-#define BIG_RAM_BLOCK_SIZE_DWORDS \
- BYTES_TO_DWORDS(BIG_RAM_BLOCK_SIZE_BYTES)
#define NUM_PHY_TBUS_ADDRESSES 2048
#define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2)
@@ -441,23 +432,17 @@ struct phy_defs {
#define FW_IMG_MAIN 1
-#ifndef REG_FIFO_ELEMENT_DWORDS
#define REG_FIFO_ELEMENT_DWORDS 2
-#endif
#define REG_FIFO_DEPTH_ELEMENTS 32
#define REG_FIFO_DEPTH_DWORDS \
(REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS)
-#ifndef IGU_FIFO_ELEMENT_DWORDS
#define IGU_FIFO_ELEMENT_DWORDS 4
-#endif
#define IGU_FIFO_DEPTH_ELEMENTS 64
#define IGU_FIFO_DEPTH_DWORDS \
(IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS)
-#ifndef PROTECTION_OVERRIDE_ELEMENT_DWORDS
#define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2
-#endif
#define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20
#define PROTECTION_OVERRIDE_DEPTH_DWORDS \
(PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \
@@ -491,6 +476,11 @@ struct dbg_array {
{{MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2},
{0, 0, 0},
{0, 0, 0},
+ {0, 0, 0} } },
+ { "reserved",
+ {{0, 0, 0},
+ {0, 0, 0},
+ {0, 0, 0},
{0, 0, 0} } }
};
@@ -498,7 +488,8 @@ struct dbg_array {
static struct storm_defs s_storm_defs[] = {
/* Tstorm */
{'T', BLOCK_TSEM,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, true,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT,
+ DBG_BUS_CLIENT_RBCT}, true,
TSEM_REG_FAST_MEMORY,
TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -511,7 +502,8 @@ struct dbg_array {
/* Mstorm */
{'M', BLOCK_MSEM,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM}, false,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM,
+ DBG_BUS_CLIENT_RBCM}, false,
MSEM_REG_FAST_MEMORY,
MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -524,7 +516,8 @@ struct dbg_array {
/* Ustorm */
{'U', BLOCK_USEM,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, false,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
+ DBG_BUS_CLIENT_RBCU}, false,
USEM_REG_FAST_MEMORY,
USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -537,7 +530,8 @@ struct dbg_array {
/* Xstorm */
{'X', BLOCK_XSEM,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, false,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX,
+ DBG_BUS_CLIENT_RBCX}, false,
XSEM_REG_FAST_MEMORY,
XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -550,7 +544,8 @@ struct dbg_array {
/* Ystorm */
{'Y', BLOCK_YSEM,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY}, false,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY,
+ DBG_BUS_CLIENT_RBCY}, false,
YSEM_REG_FAST_MEMORY,
YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -563,7 +558,8 @@ struct dbg_array {
/* Pstorm */
{'P', BLOCK_PSEM,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, true,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS,
+ DBG_BUS_CLIENT_RBCS}, true,
PSEM_REG_FAST_MEMORY,
PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
@@ -579,8 +575,8 @@ struct dbg_array {
static struct block_defs block_grc_defs = {
"grc",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
GRC_REG_DBG_FORCE_FRAME,
@@ -588,30 +584,30 @@ struct dbg_array {
};
static struct block_defs block_miscs_defs = {
- "miscs", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "miscs", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_misc_defs = {
- "misc", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "misc", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_dbu_defs = {
- "dbu", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "dbu", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_pglue_b_defs = {
"pglue_b",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH},
PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
PGLUE_B_REG_DBG_FORCE_FRAME,
@@ -620,25 +616,26 @@ struct dbg_array {
static struct block_defs block_cnig_defs = {
"cnig",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- CNIG_REG_DBG_SELECT_K2, CNIG_REG_DBG_DWORD_ENABLE_K2,
- CNIG_REG_DBG_SHIFT_K2, CNIG_REG_DBG_FORCE_VALID_K2,
- CNIG_REG_DBG_FORCE_FRAME_K2,
+ {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW,
+ DBG_BUS_CLIENT_RBCW},
+ CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
+ CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
+ CNIG_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 0
};
static struct block_defs block_cpmu_defs = {
- "cpmu", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "cpmu", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 8
};
static struct block_defs block_ncsi_defs = {
"ncsi",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
NCSI_REG_DBG_FORCE_FRAME,
@@ -646,16 +643,16 @@ struct dbg_array {
};
static struct block_defs block_opte_defs = {
- "opte", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "opte", {true, true, false}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 4
};
static struct block_defs block_bmb_defs = {
"bmb",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB},
BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
BMB_REG_DBG_FORCE_FRAME,
@@ -664,27 +661,28 @@ struct dbg_array {
static struct block_defs block_pcie_defs = {
"pcie",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PCIE_REG_DBG_COMMON_SELECT_K2,
- PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,
- PCIE_REG_DBG_COMMON_SHIFT_K2,
- PCIE_REG_DBG_COMMON_FORCE_VALID_K2,
- PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,
+ {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
+ DBG_BUS_CLIENT_RBCH},
+ PCIE_REG_DBG_COMMON_SELECT_K2_E5,
+ PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
+ PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_mcp_defs = {
- "mcp", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "mcp", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_mcp2_defs = {
"mcp2",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
MCP2_REG_DBG_FORCE_FRAME,
@@ -693,8 +691,8 @@ struct dbg_array {
static struct block_defs block_pswhst_defs = {
"pswhst",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
PSWHST_REG_DBG_FORCE_FRAME,
@@ -703,8 +701,8 @@ struct dbg_array {
static struct block_defs block_pswhst2_defs = {
"pswhst2",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
PSWHST2_REG_DBG_FORCE_FRAME,
@@ -713,8 +711,8 @@ struct dbg_array {
static struct block_defs block_pswrd_defs = {
"pswrd",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
PSWRD_REG_DBG_FORCE_FRAME,
@@ -723,8 +721,8 @@ struct dbg_array {
static struct block_defs block_pswrd2_defs = {
"pswrd2",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID,
PSWRD2_REG_DBG_FORCE_FRAME,
@@ -733,8 +731,8 @@ struct dbg_array {
static struct block_defs block_pswwr_defs = {
"pswwr",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
PSWWR_REG_DBG_FORCE_FRAME,
@@ -742,16 +740,16 @@ struct dbg_array {
};
static struct block_defs block_pswwr2_defs = {
- "pswwr2", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "pswwr2", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISC_PL_HV, 3
};
static struct block_defs block_pswrq_defs = {
"pswrq",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
PSWRQ_REG_DBG_FORCE_FRAME,
@@ -760,8 +758,8 @@ struct dbg_array {
static struct block_defs block_pswrq2_defs = {
"pswrq2",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
PSWRQ2_REG_DBG_FORCE_FRAME,
@@ -770,18 +768,19 @@ struct dbg_array {
static struct block_defs block_pglcs_defs = {
"pglcs",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PGLCS_REG_DBG_SELECT_K2, PGLCS_REG_DBG_DWORD_ENABLE_K2,
- PGLCS_REG_DBG_SHIFT_K2, PGLCS_REG_DBG_FORCE_VALID_K2,
- PGLCS_REG_DBG_FORCE_FRAME_K2,
+ {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
+ DBG_BUS_CLIENT_RBCH},
+ PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
+ PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
+ PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 2
};
static struct block_defs block_ptu_defs = {
"ptu",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
PTU_REG_DBG_FORCE_FRAME,
@@ -790,8 +789,8 @@ struct dbg_array {
static struct block_defs block_dmae_defs = {
"dmae",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
DMAE_REG_DBG_FORCE_FRAME,
@@ -800,8 +799,8 @@ struct dbg_array {
static struct block_defs block_tcm_defs = {
"tcm",
- {true, true}, true, DBG_TSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
+ {true, true, true}, true, DBG_TSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
TCM_REG_DBG_FORCE_FRAME,
@@ -810,8 +809,8 @@ struct dbg_array {
static struct block_defs block_mcm_defs = {
"mcm",
- {true, true}, true, DBG_MSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, true, DBG_MSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
MCM_REG_DBG_FORCE_FRAME,
@@ -820,8 +819,8 @@ struct dbg_array {
static struct block_defs block_ucm_defs = {
"ucm",
- {true, true}, true, DBG_USTORM_ID,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
+ {true, true, true}, true, DBG_USTORM_ID,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
UCM_REG_DBG_FORCE_FRAME,
@@ -830,8 +829,8 @@ struct dbg_array {
static struct block_defs block_xcm_defs = {
"xcm",
- {true, true}, true, DBG_XSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
+ {true, true, true}, true, DBG_XSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
XCM_REG_DBG_FORCE_FRAME,
@@ -840,8 +839,8 @@ struct dbg_array {
static struct block_defs block_ycm_defs = {
"ycm",
- {true, true}, true, DBG_YSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
+ {true, true, true}, true, DBG_YSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
YCM_REG_DBG_FORCE_FRAME,
@@ -850,8 +849,8 @@ struct dbg_array {
static struct block_defs block_pcm_defs = {
"pcm",
- {true, true}, true, DBG_PSTORM_ID,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
+ {true, true, true}, true, DBG_PSTORM_ID,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
PCM_REG_DBG_FORCE_FRAME,
@@ -860,8 +859,8 @@ struct dbg_array {
static struct block_defs block_qm_defs = {
"qm",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ},
QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
QM_REG_DBG_FORCE_FRAME,
@@ -870,8 +869,8 @@ struct dbg_array {
static struct block_defs block_tm_defs = {
"tm",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
TM_REG_DBG_FORCE_FRAME,
@@ -880,8 +879,8 @@ struct dbg_array {
static struct block_defs block_dorq_defs = {
"dorq",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
DORQ_REG_DBG_FORCE_FRAME,
@@ -890,8 +889,8 @@ struct dbg_array {
static struct block_defs block_brb_defs = {
"brb",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
BRB_REG_DBG_FORCE_FRAME,
@@ -900,8 +899,8 @@ struct dbg_array {
static struct block_defs block_src_defs = {
"src",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
SRC_REG_DBG_FORCE_FRAME,
@@ -910,8 +909,8 @@ struct dbg_array {
static struct block_defs block_prs_defs = {
"prs",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
PRS_REG_DBG_FORCE_FRAME,
@@ -920,8 +919,8 @@ struct dbg_array {
static struct block_defs block_tsdm_defs = {
"tsdm",
- {true, true}, true, DBG_TSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
+ {true, true, true}, true, DBG_TSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
TSDM_REG_DBG_FORCE_FRAME,
@@ -930,8 +929,8 @@ struct dbg_array {
static struct block_defs block_msdm_defs = {
"msdm",
- {true, true}, true, DBG_MSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, true, DBG_MSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
MSDM_REG_DBG_FORCE_FRAME,
@@ -940,8 +939,8 @@ struct dbg_array {
static struct block_defs block_usdm_defs = {
"usdm",
- {true, true}, true, DBG_USTORM_ID,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
+ {true, true, true}, true, DBG_USTORM_ID,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
USDM_REG_DBG_FORCE_FRAME,
@@ -950,8 +949,8 @@ struct dbg_array {
static struct block_defs block_xsdm_defs = {
"xsdm",
- {true, true}, true, DBG_XSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
+ {true, true, true}, true, DBG_XSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
XSDM_REG_DBG_FORCE_FRAME,
@@ -960,8 +959,8 @@ struct dbg_array {
static struct block_defs block_ysdm_defs = {
"ysdm",
- {true, true}, true, DBG_YSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
+ {true, true, true}, true, DBG_YSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
YSDM_REG_DBG_FORCE_FRAME,
@@ -970,8 +969,8 @@ struct dbg_array {
static struct block_defs block_psdm_defs = {
"psdm",
- {true, true}, true, DBG_PSTORM_ID,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
+ {true, true, true}, true, DBG_PSTORM_ID,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
PSDM_REG_DBG_FORCE_FRAME,
@@ -980,8 +979,8 @@ struct dbg_array {
static struct block_defs block_tsem_defs = {
"tsem",
- {true, true}, true, DBG_TSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
+ {true, true, true}, true, DBG_TSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
TSEM_REG_DBG_FORCE_FRAME,
@@ -990,8 +989,8 @@ struct dbg_array {
static struct block_defs block_msem_defs = {
"msem",
- {true, true}, true, DBG_MSTORM_ID,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, true, DBG_MSTORM_ID,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
MSEM_REG_DBG_FORCE_FRAME,
@@ -1000,8 +999,8 @@ struct dbg_array {
static struct block_defs block_usem_defs = {
"usem",
- {true, true}, true, DBG_USTORM_ID,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
+ {true, true, true}, true, DBG_USTORM_ID,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
USEM_REG_DBG_FORCE_FRAME,
@@ -1010,8 +1009,8 @@ struct dbg_array {
static struct block_defs block_xsem_defs = {
"xsem",
- {true, true}, true, DBG_XSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
+ {true, true, true}, true, DBG_XSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,
XSEM_REG_DBG_FORCE_FRAME,
@@ -1020,8 +1019,8 @@ struct dbg_array {
static struct block_defs block_ysem_defs = {
"ysem",
- {true, true}, true, DBG_YSTORM_ID,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
+ {true, true, true}, true, DBG_YSTORM_ID,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
YSEM_REG_DBG_FORCE_FRAME,
@@ -1030,8 +1029,8 @@ struct dbg_array {
static struct block_defs block_psem_defs = {
"psem",
- {true, true}, true, DBG_PSTORM_ID,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
+ {true, true, true}, true, DBG_PSTORM_ID,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
PSEM_REG_DBG_FORCE_FRAME,
@@ -1040,8 +1039,8 @@ struct dbg_array {
static struct block_defs block_rss_defs = {
"rss",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
RSS_REG_DBG_FORCE_FRAME,
@@ -1050,8 +1049,8 @@ struct dbg_array {
static struct block_defs block_tmld_defs = {
"tmld",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
TMLD_REG_DBG_FORCE_FRAME,
@@ -1060,8 +1059,8 @@ struct dbg_array {
static struct block_defs block_muld_defs = {
"muld",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
MULD_REG_DBG_FORCE_FRAME,
@@ -1070,8 +1069,9 @@ struct dbg_array {
static struct block_defs block_yuld_defs = {
"yuld",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
+ {true, true, false}, false, 0,
+ {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
+ MAX_DBG_BUS_CLIENTS},
YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
YULD_REG_DBG_FORCE_FRAME_BB_K2,
@@ -1081,18 +1081,40 @@ struct dbg_array {
static struct block_defs block_xyld_defs = {
"xyld",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
XYLD_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
};
+static struct block_defs block_ptld_defs = {
+ "ptld",
+ {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT},
+ PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5,
+ PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5,
+ PTLD_REG_DBG_FORCE_FRAME_E5,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
+ 28
+};
+
+static struct block_defs block_ypld_defs = {
+ "ypld",
+ {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS},
+ YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5,
+ YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5,
+ YPLD_REG_DBG_FORCE_FRAME_E5,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
+ 27
+};
+
static struct block_defs block_prm_defs = {
"prm",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
PRM_REG_DBG_FORCE_FRAME,
@@ -1101,8 +1123,8 @@ struct dbg_array {
static struct block_defs block_pbf_pb1_defs = {
"pbf_pb1",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
PBF_PB1_REG_DBG_FORCE_FRAME,
@@ -1112,8 +1134,8 @@ struct dbg_array {
static struct block_defs block_pbf_pb2_defs = {
"pbf_pb2",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
PBF_PB2_REG_DBG_FORCE_FRAME,
@@ -1123,8 +1145,8 @@ struct dbg_array {
static struct block_defs block_rpb_defs = {
"rpb",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
RPB_REG_DBG_FORCE_FRAME,
@@ -1133,8 +1155,8 @@ struct dbg_array {
static struct block_defs block_btb_defs = {
"btb",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
BTB_REG_DBG_FORCE_FRAME,
@@ -1143,8 +1165,8 @@ struct dbg_array {
static struct block_defs block_pbf_defs = {
"pbf",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
PBF_REG_DBG_FORCE_FRAME,
@@ -1153,8 +1175,8 @@ struct dbg_array {
static struct block_defs block_rdif_defs = {
"rdif",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
RDIF_REG_DBG_FORCE_FRAME,
@@ -1163,8 +1185,8 @@ struct dbg_array {
static struct block_defs block_tdif_defs = {
"tdif",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
TDIF_REG_DBG_FORCE_FRAME,
@@ -1173,8 +1195,8 @@ struct dbg_array {
static struct block_defs block_cdu_defs = {
"cdu",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
CDU_REG_DBG_FORCE_FRAME,
@@ -1183,8 +1205,8 @@ struct dbg_array {
static struct block_defs block_ccfc_defs = {
"ccfc",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
CCFC_REG_DBG_FORCE_FRAME,
@@ -1193,8 +1215,8 @@ struct dbg_array {
static struct block_defs block_tcfc_defs = {
"tcfc",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
TCFC_REG_DBG_FORCE_FRAME,
@@ -1203,8 +1225,8 @@ struct dbg_array {
static struct block_defs block_igu_defs = {
"igu",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
IGU_REG_DBG_FORCE_FRAME,
@@ -1213,42 +1235,79 @@ struct dbg_array {
static struct block_defs block_cau_defs = {
"cau",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
CAU_REG_DBG_FORCE_FRAME,
true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
};
+static struct block_defs block_rgfs_defs = {
+ "rgfs", {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ 0, 0, 0, 0, 0,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29
+};
+
+static struct block_defs block_rgsrc_defs = {
+ "rgsrc",
+ {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
+ RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5,
+ RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5,
+ RGSRC_REG_DBG_FORCE_FRAME_E5,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
+ 30
+};
+
+static struct block_defs block_tgfs_defs = {
+ "tgfs", {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ 0, 0, 0, 0, 0,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30
+};
+
+static struct block_defs block_tgsrc_defs = {
+ "tgsrc",
+ {false, false, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV},
+ TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5,
+ TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5,
+ TGSRC_REG_DBG_FORCE_FRAME_E5,
+ true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
+ 31
+};
+
static struct block_defs block_umac_defs = {
"umac",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- UMAC_REG_DBG_SELECT_K2, UMAC_REG_DBG_DWORD_ENABLE_K2,
- UMAC_REG_DBG_SHIFT_K2, UMAC_REG_DBG_FORCE_VALID_K2,
- UMAC_REG_DBG_FORCE_FRAME_K2,
+ {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ,
+ DBG_BUS_CLIENT_RBCZ},
+ UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
+ UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
+ UMAC_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 6
};
static struct block_defs block_xmac_defs = {
- "xmac", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "xmac", {true, false, false}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_dbg_defs = {
- "dbg", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "dbg", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3
};
static struct block_defs block_nig_defs = {
"nig",
- {true, true}, false, 0,
- {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
+ {true, true, true}, false, 0,
+ {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
NIG_REG_DBG_FORCE_FRAME,
@@ -1257,139 +1316,106 @@ struct dbg_array {
static struct block_defs block_wol_defs = {
"wol",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- WOL_REG_DBG_SELECT_K2, WOL_REG_DBG_DWORD_ENABLE_K2,
- WOL_REG_DBG_SHIFT_K2, WOL_REG_DBG_FORCE_VALID_K2,
- WOL_REG_DBG_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
+ WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
+ WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
+ WOL_REG_DBG_FORCE_FRAME_K2_E5,
true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
};
static struct block_defs block_bmbn_defs = {
"bmbn",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB},
- BMBN_REG_DBG_SELECT_K2, BMBN_REG_DBG_DWORD_ENABLE_K2,
- BMBN_REG_DBG_SHIFT_K2, BMBN_REG_DBG_FORCE_VALID_K2,
- BMBN_REG_DBG_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB,
+ DBG_BUS_CLIENT_RBCB},
+ BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
+ BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
+ BMBN_REG_DBG_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_ipc_defs = {
- "ipc", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "ipc", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_UA, 8
};
static struct block_defs block_nwm_defs = {
"nwm",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- NWM_REG_DBG_SELECT_K2, NWM_REG_DBG_DWORD_ENABLE_K2,
- NWM_REG_DBG_SHIFT_K2, NWM_REG_DBG_FORCE_VALID_K2,
- NWM_REG_DBG_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
+ NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
+ NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
+ NWM_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
};
static struct block_defs block_nws_defs = {
"nws",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW},
- NWS_REG_DBG_SELECT_K2, NWS_REG_DBG_DWORD_ENABLE_K2,
- NWS_REG_DBG_SHIFT_K2, NWS_REG_DBG_FORCE_VALID_K2,
- NWS_REG_DBG_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
+ NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
+ NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
+ NWS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 12
};
static struct block_defs block_ms_defs = {
"ms",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ},
- MS_REG_DBG_SELECT_K2, MS_REG_DBG_DWORD_ENABLE_K2,
- MS_REG_DBG_SHIFT_K2, MS_REG_DBG_FORCE_VALID_K2,
- MS_REG_DBG_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
+ MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
+ MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
+ MS_REG_DBG_FORCE_FRAME_K2_E5,
true, false, DBG_RESET_REG_MISCS_PL_HV, 13
};
static struct block_defs block_phy_pcie_defs = {
"phy_pcie",
- {false, true}, false, 0,
- {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
- PCIE_REG_DBG_COMMON_SELECT_K2,
- PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2,
- PCIE_REG_DBG_COMMON_SHIFT_K2,
- PCIE_REG_DBG_COMMON_FORCE_VALID_K2,
- PCIE_REG_DBG_COMMON_FORCE_FRAME_K2,
+ {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
+ DBG_BUS_CLIENT_RBCH},
+ PCIE_REG_DBG_COMMON_SELECT_K2_E5,
+ PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
+ PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
+ PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_led_defs = {
- "led", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "led", {false, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_HV, 14
};
static struct block_defs block_avs_wrap_defs = {
- "avs_wrap", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "avs_wrap", {false, true, false}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
true, false, DBG_RESET_REG_MISCS_PL_UA, 11
};
-static struct block_defs block_rgfs_defs = {
- "rgfs", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
- 0, 0, 0, 0, 0,
- false, false, MAX_DBG_RESET_REGS, 0
-};
-
-static struct block_defs block_rgsrc_defs = {
- "rgsrc", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
- 0, 0, 0, 0, 0,
- false, false, MAX_DBG_RESET_REGS, 0
-};
-
-static struct block_defs block_tgfs_defs = {
- "tgfs", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
- 0, 0, 0, 0, 0,
- false, false, MAX_DBG_RESET_REGS, 0
-};
-
-static struct block_defs block_tgsrc_defs = {
- "tgsrc", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
- 0, 0, 0, 0, 0,
- false, false, MAX_DBG_RESET_REGS, 0
-};
-
-static struct block_defs block_ptld_defs = {
- "ptld", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
- 0, 0, 0, 0, 0,
- false, false, MAX_DBG_RESET_REGS, 0
-};
-
-static struct block_defs block_ypld_defs = {
- "ypld", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+static struct block_defs block_pxpreqbus_defs = {
+ "pxpreqbus", {false, false, false}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_misc_aeu_defs = {
- "misc_aeu", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "misc_aeu", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
static struct block_defs block_bar0_map_defs = {
- "bar0_map", {false, false}, false, 0,
- {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
+ "bar0_map", {true, true, true}, false, 0,
+ {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
0, 0, 0, 0, 0,
false, false, MAX_DBG_RESET_REGS, 0
};
@@ -1480,164 +1506,160 @@ struct dbg_array {
&block_phy_pcie_defs,
&block_led_defs,
&block_avs_wrap_defs,
+ &block_pxpreqbus_defs,
&block_misc_aeu_defs,
&block_bar0_map_defs,
};
static struct platform_defs s_platform_defs[] = {
- {"asic", 1},
- {"reserved", 0},
- {"reserved2", 0},
- {"reserved3", 0}
+ {"asic", 1, 256, 32768},
+ {"reserved", 0, 0, 0},
+ {"reserved2", 0, 0, 0},
+ {"reserved3", 0, 0, 0}
};
static struct grc_param_defs s_grc_param_defs[] = {
/* DBG_GRC_PARAM_DUMP_TSTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_MSTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_USTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_XSTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_YSTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_PSTORM */
- {{1, 1}, 0, 1, false, 1, 1},
+ {{1, 1, 1}, 0, 1, false, 1, 1},
/* DBG_GRC_PARAM_DUMP_REGS */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_RAM */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_PBUF */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_IOR */
- {{0, 0}, 0, 1, false, 0, 1},
+ {{0, 0, 0}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_VFC */
- {{0, 0}, 0, 1, false, 0, 1},
+ {{0, 0, 0}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_CM_CTX */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_ILT */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_RSS */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_CAU */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_QM */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_MCP */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_RESERVED */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_CFC */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_IGU */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_BRB */
- {{0, 0}, 0, 1, false, 0, 1},
+ {{0, 0, 0}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_BTB */
- {{0, 0}, 0, 1, false, 0, 1},
+ {{0, 0, 0}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_BMB */
- {{0, 0}, 0, 1, false, 0, 1},
+ {{0, 0, 0}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_NIG */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_MULD */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_PRS */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_DMAE */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_TM */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_SDM */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_DIF */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_STATIC */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_UNSTALL */
- {{0, 0}, 0, 1, false, 0, 0},
+ {{0, 0, 0}, 0, 1, false, 0, 0},
/* DBG_GRC_PARAM_NUM_LCIDS */
- {{MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, MAX_LCIDS,
+ {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, MAX_LCIDS,
MAX_LCIDS},
/* DBG_GRC_PARAM_NUM_LTIDS */
- {{MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, MAX_LTIDS,
+ {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, MAX_LTIDS,
MAX_LTIDS},
/* DBG_GRC_PARAM_EXCLUDE_ALL */
- {{0, 0}, 0, 1, true, 0, 0},
+ {{0, 0, 0}, 0, 1, true, 0, 0},
/* DBG_GRC_PARAM_CRASH */
- {{0, 0}, 0, 1, true, 0, 0},
+ {{0, 0, 0}, 0, 1, true, 0, 0},
/* DBG_GRC_PARAM_PARITY_SAFE */
- {{0, 0}, 0, 1, false, 1, 0},
+ {{0, 0, 0}, 0, 1, false, 1, 0},
/* DBG_GRC_PARAM_DUMP_CM */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_DUMP_PHY */
- {{1, 1}, 0, 1, false, 0, 1},
+ {{1, 1, 1}, 0, 1, false, 0, 1},
/* DBG_GRC_PARAM_NO_MCP */
- {{0, 0}, 0, 1, false, 0, 0},
+ {{0, 0, 0}, 0, 1, false, 0, 0},
/* DBG_GRC_PARAM_NO_FW_VER */
- {{0, 0}, 0, 1, false, 0, 0}
+ {{0, 0, 0}, 0, 1, false, 0, 0}
};
static struct rss_mem_defs s_rss_mem_defs[] = {
- { "rss_mem_cid", "rss_cid", 0,
- {256, 320},
- {32, 32} },
+ { "rss_mem_cid", "rss_cid", 0, 32,
+ {256, 320, 512} },
- { "rss_mem_key_msb", "rss_key", 1024,
- {128, 208},
- {256, 256} },
+ { "rss_mem_key_msb", "rss_key", 1024, 256,
+ {128, 208, 257} },
- { "rss_mem_key_lsb", "rss_key", 2048,
- {128, 208},
- {64, 64} },
+ { "rss_mem_key_lsb", "rss_key", 2048, 64,
+ {128, 208, 257} },
- { "rss_mem_info", "rss_info", 3072,
- {128, 208},
- {16, 16} },
+ { "rss_mem_info", "rss_info", 3072, 16,
+ {128, 208, 256} },
- { "rss_mem_ind", "rss_ind", 4096,
- {16384, 26624},
- {16, 16} }
+ { "rss_mem_ind", "rss_ind", 4096, 16,
+ {16384, 26624, 32768} }
};
static struct vfc_ram_defs s_vfc_ram_defs[] = {
@@ -1650,72 +1672,75 @@ struct dbg_array {
static struct big_ram_defs s_big_ram_defs[] = {
{ "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
- {4800, 5632} },
+ MISC_REG_BLOCK_256B_EN, {0, 0, 0},
+ {153600, 180224, 282624} },
{ "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
- {2880, 3680} },
+ MISC_REG_BLOCK_256B_EN, {0, 1, 1},
+ {92160, 117760, 168960} },
{ "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
- {1152, 1152} }
+ MISCS_REG_BLOCK_256B_EN, {0, 0, 0},
+ {36864, 36864, 36864} }
};
static struct reset_reg_defs s_reset_regs_defs[] = {
/* DBG_RESET_REG_MISCS_PL_UA */
- { MISCS_REG_RESET_PL_UA, 0x0,
- {true, true} },
+ { MISCS_REG_RESET_PL_UA,
+ {true, true, true}, {0x0, 0x0, 0x0} },
/* DBG_RESET_REG_MISCS_PL_HV */
- { MISCS_REG_RESET_PL_HV, 0x0,
- {true, true} },
+ { MISCS_REG_RESET_PL_HV,
+ {true, true, true}, {0x0, 0x400, 0x600} },
/* DBG_RESET_REG_MISCS_PL_HV_2 */
- { MISCS_REG_RESET_PL_HV_2_K2, 0x0,
- {false, true} },
+ { MISCS_REG_RESET_PL_HV_2_K2_E5,
+ {false, true, true}, {0x0, 0x0, 0x0} },
/* DBG_RESET_REG_MISC_PL_UA */
- { MISC_REG_RESET_PL_UA, 0x0,
- {true, true} },
+ { MISC_REG_RESET_PL_UA,
+ {true, true, true}, {0x0, 0x0, 0x0} },
/* DBG_RESET_REG_MISC_PL_HV */
- { MISC_REG_RESET_PL_HV, 0x0,
- {true, true} },
+ { MISC_REG_RESET_PL_HV,
+ {true, true, true}, {0x0, 0x0, 0x0} },
/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
- { MISC_REG_RESET_PL_PDA_VMAIN_1, 0x4404040,
- {true, true} },
+ { MISC_REG_RESET_PL_PDA_VMAIN_1,
+ {true, true, true}, {0x4404040, 0x4404040, 0x404040} },
/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
- { MISC_REG_RESET_PL_PDA_VMAIN_2, 0x7c00007,
- {true, true} },
+ { MISC_REG_RESET_PL_PDA_VMAIN_2,
+ {true, true, true}, {0x7, 0x7c00007, 0x5c08007} },
/* DBG_RESET_REG_MISC_PL_PDA_VAUX */
- { MISC_REG_RESET_PL_PDA_VAUX, 0x2,
- {true, true} },
+ { MISC_REG_RESET_PL_PDA_VAUX,
+ {true, true, true}, {0x2, 0x2, 0x2} },
};
static struct phy_defs s_phy_defs[] = {
{"nw_phy", NWS_REG_NWS_CMU_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2,
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2},
- {"sgmii_phy", MS_REG_MS_CMU_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2},
- {"pcie_phy0", PHY_PCIE_REG_PHY0_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},
- {"pcie_phy1", PHY_PCIE_REG_PHY1_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2,
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2},
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5,
+ PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5},
+ {"sgmii_phy", MS_REG_MS_CMU_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
+ {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
+ {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5,
+ PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5},
};
/**************************** Private Functions ******************************/
@@ -1774,7 +1799,9 @@ static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn,
/* Initializes the GRC parameters */
qed_dbg_grc_init_params(p_hwfn);
- dev_data->initialized = true;
+ dev_data->use_dmae = true;
+ dev_data->num_regs_read = 0;
+ dev_data->initialized = 1;
return DBG_STATUS_OK;
}
@@ -1807,7 +1834,7 @@ static void qed_read_fw_info(struct qed_hwfn *p_hwfn,
* The address is located in the last line of the Storm RAM.
*/
addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
- DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) -
+ DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
sizeof(fw_info_location);
dest = (u32 *)&fw_info_location;
@@ -2071,8 +2098,7 @@ static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn,
/* Writes the "last" section (including CRC) to the specified buffer at the
* given offset. Returns the dumped size in dwords.
*/
-static u32 qed_dump_last_section(struct qed_hwfn *p_hwfn,
- u32 *dump_buf, u32 offset, bool dump)
+static u32 qed_dump_last_section(u32 *dump_buf, u32 offset, bool dump)
{
u32 start_offset = offset;
@@ -2235,7 +2261,8 @@ static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn,
case MEM_GROUP_CFC_MEM:
case MEM_GROUP_CONN_CFC_MEM:
case MEM_GROUP_TASK_CFC_MEM:
- return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC);
+ return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) ||
+ qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX);
case MEM_GROUP_IGU_MEM:
case MEM_GROUP_IGU_MSIX:
return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU);
@@ -2293,7 +2320,8 @@ static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn,
for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
struct block_defs *block = s_block_defs[block_id];
- if (block->has_reset_bit && block->unreset)
+ if (block->exists[dev_data->chip_id] && block->has_reset_bit &&
+ block->unreset)
reg_val[block->reset_reg] |=
BIT(block->reset_bit_offset);
}
@@ -2303,7 +2331,8 @@ static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn,
if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
continue;
- reg_val[i] |= s_reset_regs_defs[i].unreset_val;
+ reg_val[i] |=
+ s_reset_regs_defs[i].unreset_val[dev_data->chip_id];
if (reg_val[i])
qed_wr(p_hwfn,
@@ -2413,6 +2442,18 @@ static u32 qed_grc_dump_regs_hdr(u32 *dump_buf,
return offset;
}
+/* Reads the specified registers into the specified buffer.
+ * The addr and len arguments are specified in dwords.
+ */
+void qed_read_regs(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len)
+{
+ u32 i;
+
+ for (i = 0; i < len; i++)
+ buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i));
+}
+
/* Dumps the GRC registers in the specified address range.
* Returns the dumped size in dwords.
* The addr and len arguments are specified in dwords.
@@ -2422,15 +2463,39 @@ static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn,
u32 *dump_buf,
bool dump, u32 addr, u32 len, bool wide_bus)
{
- u32 byte_addr = DWORDS_TO_BYTES(addr), offset = 0, i;
+ struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
if (!dump)
return len;
- for (i = 0; i < len; i++, byte_addr += BYTES_IN_DWORD, offset++)
- *(dump_buf + offset) = qed_rd(p_hwfn, p_ptt, byte_addr);
+ /* Print log if needed */
+ dev_data->num_regs_read += len;
+ if (dev_data->num_regs_read >=
+ s_platform_defs[dev_data->platform_id].log_thresh) {
+ DP_VERBOSE(p_hwfn,
+ QED_MSG_DEBUG,
+ "Dumping %d registers...\n",
+ dev_data->num_regs_read);
+ dev_data->num_regs_read = 0;
+ }
- return offset;
+ /* Try reading using DMAE */
+ if (dev_data->use_dmae &&
+ (len >= s_platform_defs[dev_data->platform_id].dmae_thresh ||
+ wide_bus)) {
+ if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr),
+ (u64)(uintptr_t)(dump_buf), len, 0))
+ return len;
+ dev_data->use_dmae = 0;
+ DP_VERBOSE(p_hwfn,
+ QED_MSG_DEBUG,
+ "Failed reading from chip using DMAE, using GRC instead\n");
+ }
+
+ /* Read registers */
+ qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len);
+
+ return len;
}
/* Dumps GRC registers sequence header. Returns the dumped size in dwords.
@@ -2630,9 +2695,6 @@ static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn,
chip = &s_chip_defs[dev_data->chip_id];
chip_platform = &chip->per_platform[dev_data->platform_id];
- if (dump)
- DP_VERBOSE(p_hwfn, QED_MSG_DEBUG, "Dumping registers...\n");
-
while (input_offset <
s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) {
const struct dbg_dump_split_hdr *split_hdr;
@@ -2966,22 +3028,12 @@ static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn,
offset += qed_dump_str_param(dump_buf + offset,
dump, "name", buf);
- if (dump)
- DP_VERBOSE(p_hwfn,
- QED_MSG_DEBUG,
- "Dumping %d registers from %s...\n",
- len, buf);
} else {
/* Dump address */
u32 addr_in_bytes = DWORDS_TO_BYTES(addr);
offset += qed_dump_num_param(dump_buf + offset,
dump, "addr", addr_in_bytes);
- if (dump && len > 64)
- DP_VERBOSE(p_hwfn,
- QED_MSG_DEBUG,
- "Dumping %d registers from address 0x%x...\n",
- len, addr_in_bytes);
}
/* Dump len */
@@ -3530,17 +3582,16 @@ static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn,
u8 rss_mem_id;
for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) {
- u32 rss_addr, num_entries, entry_width, total_dwords, i;
+ u32 rss_addr, num_entries, total_dwords;
struct rss_mem_defs *rss_defs;
- u32 addr, size;
+ u32 addr, num_dwords_to_read;
bool packed;
rss_defs = &s_rss_mem_defs[rss_mem_id];
rss_addr = rss_defs->addr;
num_entries = rss_defs->num_entries[dev_data->chip_id];
- entry_width = rss_defs->entry_width[dev_data->chip_id];
- total_dwords = (num_entries * entry_width) / 32;
- packed = (entry_width == 16);
+ total_dwords = (num_entries * rss_defs->entry_width) / 32;
+ packed = (rss_defs->entry_width == 16);
offset += qed_grc_dump_mem_hdr(p_hwfn,
dump_buf + offset,
@@ -3548,7 +3599,7 @@ static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn,
rss_defs->mem_name,
0,
total_dwords,
- entry_width,
+ rss_defs->entry_width,
packed,
rss_defs->type_name, false, 0);
@@ -3559,16 +3610,20 @@ static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn,
}
addr = BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA);
- size = RSS_REG_RSS_RAM_DATA_SIZE;
- for (i = 0; i < total_dwords; i += size, rss_addr++) {
+ while (total_dwords) {
+ num_dwords_to_read = min_t(u32,
+ RSS_REG_RSS_RAM_DATA_SIZE,
+ total_dwords);
qed_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr);
offset += qed_grc_dump_addr_range(p_hwfn,
p_ptt,
dump_buf + offset,
dump,
addr,
- size,
+ num_dwords_to_read,
false);
+ total_dwords -= num_dwords_to_read;
+ rss_addr++;
}
}
@@ -3581,14 +3636,18 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn,
u32 *dump_buf, bool dump, u8 big_ram_id)
{
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
- u32 total_blocks, ram_size, offset = 0, i;
+ u32 block_size, ram_size, offset = 0, reg_val, i;
char mem_name[12] = "???_BIG_RAM";
char type_name[8] = "???_RAM";
struct big_ram_defs *big_ram;
big_ram = &s_big_ram_defs[big_ram_id];
- total_blocks = big_ram->num_of_blocks[dev_data->chip_id];
- ram_size = total_blocks * BIG_RAM_BLOCK_SIZE_DWORDS;
+ ram_size = big_ram->ram_size[dev_data->chip_id];
+
+ reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr);
+ block_size = reg_val &
+ BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256
+ : 128;
strncpy(type_name, big_ram->instance_name,
strlen(big_ram->instance_name));
@@ -3602,7 +3661,7 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn,
mem_name,
0,
ram_size,
- BIG_RAM_BLOCK_SIZE_BYTES * 8,
+ block_size * 8,
false, type_name, false, 0);
/* Read and dump Big RAM data */
@@ -3610,12 +3669,13 @@ static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn,
return offset + ram_size;
/* Dump Big RAM */
- for (i = 0; i < total_blocks / 2; i++) {
+ for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE);
+ i++) {
u32 addr, len;
qed_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i);
addr = BYTES_TO_DWORDS(big_ram->data_reg_addr);
- len = 2 * BIG_RAM_BLOCK_SIZE_DWORDS;
+ len = BRB_REG_BIG_RAM_DATA_SIZE;
offset += qed_grc_dump_addr_range(p_hwfn,
p_ptt,
dump_buf + offset,
@@ -3649,7 +3709,7 @@ static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
dump,
NULL,
BYTES_TO_DWORDS(MCP_REG_SCRATCH),
- MCP_REG_SCRATCH_SIZE,
+ MCP_REG_SCRATCH_SIZE_BB_K2,
false, 0, false, "MCP", false, 0);
/* Dump MCP cpu_reg_file */
@@ -3710,7 +3770,6 @@ static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn,
phy_defs->tbus_data_lo_addr;
data_hi_addr = phy_defs->base_addr +
phy_defs->tbus_data_hi_addr;
- bytes_buf = (u8 *)(dump_buf + offset);
if (snprintf(mem_name, sizeof(mem_name), "tbus_%s",
phy_defs->phy_name) < 0)
@@ -3730,6 +3789,7 @@ static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn,
continue;
}
+ bytes_buf = (u8 *)(dump_buf + offset);
for (tbus_hi_offset = 0;
tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8);
tbus_hi_offset++) {
@@ -3778,19 +3838,17 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn,
struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
u32 block_id, line_id, offset = 0;
- /* Skip static debug if a debug bus recording is in progress */
- if (qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
+ /* Don't dump static debug if a debug bus recording is in progress */
+ if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
return 0;
if (dump) {
- DP_VERBOSE(p_hwfn,
- QED_MSG_DEBUG, "Dumping static debug data...\n");
-
/* Disable all blocks debug output */
for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
struct block_defs *block = s_block_defs[block_id];
- if (block->has_dbg_bus[dev_data->chip_id])
+ if (block->dbg_client_id[dev_data->chip_id] !=
+ MAX_DBG_BUS_CLIENTS)
qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr,
0);
}
@@ -3811,12 +3869,12 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn,
u32 block_dwords, addr, len;
u8 dbg_client_id;
- if (!block->has_dbg_bus[dev_data->chip_id])
+ if (block->dbg_client_id[dev_data->chip_id] ==
+ MAX_DBG_BUS_CLIENTS)
continue;
- block_desc =
- get_dbg_bus_block_desc(p_hwfn,
- (enum block_id)block_id);
+ block_desc = get_dbg_bus_block_desc(p_hwfn,
+ (enum block_id)block_id);
block_dwords = NUM_DBG_LINES(block_desc) *
STATIC_DEBUG_LINE_DWORDS;
@@ -3847,7 +3905,6 @@ static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn,
qed_bus_enable_clients(p_hwfn,
p_ptt,
BIT(dbg_client_id));
-
addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA);
len = STATIC_DEBUG_LINE_DWORDS;
for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc);
@@ -4044,7 +4101,7 @@ static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn,
dump_buf + offset, dump);
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
if (dump) {
/* Unstall storms */
@@ -4253,30 +4310,33 @@ static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn,
if (!check_rule && dump)
continue;
+ if (!dump) {
+ u32 entry_dump_size =
+ qed_idle_chk_dump_failure(p_hwfn,
+ p_ptt,
+ dump_buf + offset,
+ false,
+ rule->rule_id,
+ rule,
+ 0,
+ NULL);
+
+ offset += num_reg_entries * entry_dump_size;
+ (*num_failing_rules) += num_reg_entries;
+ continue;
+ }
+
/* Go over all register entries (number of entries is the same
* for all condition registers).
*/
for (entry_id = 0; entry_id < num_reg_entries; entry_id++) {
u32 next_reg_offset = 0;
- if (!dump) {
- offset += qed_idle_chk_dump_failure(p_hwfn,
- p_ptt,
- dump_buf + offset,
- false,
- rule->rule_id,
- rule,
- entry_id,
- NULL);
- (*num_failing_rules)++;
- break;
- }
-
/* Read current entry of all condition registers */
for (reg_id = 0; reg_id < rule->num_cond_regs;
reg_id++) {
const struct dbg_idle_chk_cond_reg *reg =
- &cond_regs[reg_id];
+ &cond_regs[reg_id];
u32 padded_entry_size, addr;
bool wide_bus;
@@ -4291,9 +4351,9 @@ static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn,
if (reg->num_entries > 1 ||
reg->start_entry > 0) {
padded_entry_size =
- reg->entry_size > 1 ?
- roundup_pow_of_two(reg->entry_size)
- : 1;
+ reg->entry_size > 1 ?
+ roundup_pow_of_two(reg->entry_size) :
+ 1;
addr += (reg->start_entry + entry_id) *
padded_entry_size;
}
@@ -4329,7 +4389,6 @@ static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn,
entry_id,
cond_reg_values);
(*num_failing_rules)++;
- break;
}
}
}
@@ -4402,7 +4461,7 @@ static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn,
dump, "num_rules", num_failing_rules);
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
return offset;
}
@@ -4474,7 +4533,7 @@ static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn,
(nvram_offset_bytes +
read_offset) |
(bytes_to_copy <<
- DRV_MB_PARAM_NVM_LEN_SHIFT),
+ DRV_MB_PARAM_NVM_LEN_OFFSET),
&ret_mcp_resp, &ret_mcp_param,
&ret_read_size,
(u32 *)((u8 *)ret_buf + read_offset)))
@@ -4701,7 +4760,7 @@ static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn,
offset += trace_meta_size_dwords;
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
*num_dumped_dwords = offset;
@@ -4717,7 +4776,7 @@ static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn,
u32 *dump_buf,
bool dump, u32 *num_dumped_dwords)
{
- u32 dwords_read, size_param_offset, offset = 0;
+ u32 dwords_read, size_param_offset, offset = 0, addr, len;
bool fifo_has_data;
*num_dumped_dwords = 0;
@@ -4753,14 +4812,18 @@ static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn,
* buffer size since more entries could be added to the buffer as we are
* emptying it.
*/
+ addr = BYTES_TO_DWORDS(GRC_REG_TRACE_FIFO);
+ len = REG_FIFO_ELEMENT_DWORDS;
for (dwords_read = 0;
fifo_has_data && dwords_read < REG_FIFO_DEPTH_DWORDS;
- dwords_read += REG_FIFO_ELEMENT_DWORDS, offset +=
- REG_FIFO_ELEMENT_DWORDS) {
- if (qed_dmae_grc2host(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO,
- (u64)(uintptr_t)(&dump_buf[offset]),
- REG_FIFO_ELEMENT_DWORDS, 0))
- return DBG_STATUS_DMAE_FAILED;
+ dwords_read += REG_FIFO_ELEMENT_DWORDS) {
+ offset += qed_grc_dump_addr_range(p_hwfn,
+ p_ptt,
+ dump_buf + offset,
+ true,
+ addr,
+ len,
+ true);
fifo_has_data = qed_rd(p_hwfn, p_ptt,
GRC_REG_TRACE_FIFO_VALID_DATA) > 0;
}
@@ -4769,7 +4832,7 @@ static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn,
dwords_read);
out:
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
*num_dumped_dwords = offset;
@@ -4782,7 +4845,7 @@ static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn,
u32 *dump_buf,
bool dump, u32 *num_dumped_dwords)
{
- u32 dwords_read, size_param_offset, offset = 0;
+ u32 dwords_read, size_param_offset, offset = 0, addr, len;
bool fifo_has_data;
*num_dumped_dwords = 0;
@@ -4818,16 +4881,19 @@ static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn,
* buffer size since more entries could be added to the buffer as we are
* emptying it.
*/
+ addr = BYTES_TO_DWORDS(IGU_REG_ERROR_HANDLING_MEMORY);
+ len = IGU_FIFO_ELEMENT_DWORDS;
for (dwords_read = 0;
fifo_has_data && dwords_read < IGU_FIFO_DEPTH_DWORDS;
- dwords_read += IGU_FIFO_ELEMENT_DWORDS, offset +=
- IGU_FIFO_ELEMENT_DWORDS) {
- if (qed_dmae_grc2host(p_hwfn, p_ptt,
- IGU_REG_ERROR_HANDLING_MEMORY,
- (u64)(uintptr_t)(&dump_buf[offset]),
- IGU_FIFO_ELEMENT_DWORDS, 0))
- return DBG_STATUS_DMAE_FAILED;
- fifo_has_data = qed_rd(p_hwfn, p_ptt,
+ dwords_read += IGU_FIFO_ELEMENT_DWORDS) {
+ offset += qed_grc_dump_addr_range(p_hwfn,
+ p_ptt,
+ dump_buf + offset,
+ true,
+ addr,
+ len,
+ true);
+ fifo_has_data = qed_rd(p_hwfn, p_ptt,
IGU_REG_ERROR_HANDLING_DATA_VALID) > 0;
}
@@ -4835,7 +4901,7 @@ static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn,
dwords_read);
out:
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
*num_dumped_dwords = offset;
@@ -4849,7 +4915,7 @@ static enum dbg_status qed_protection_override_dump(struct qed_hwfn *p_hwfn,
bool dump,
u32 *num_dumped_dwords)
{
- u32 size_param_offset, override_window_dwords, offset = 0;
+ u32 size_param_offset, override_window_dwords, offset = 0, addr;
*num_dumped_dwords = 0;
@@ -4875,20 +4941,21 @@ static enum dbg_status qed_protection_override_dump(struct qed_hwfn *p_hwfn,
/* Add override window info to buffer */
override_window_dwords =
- qed_rd(p_hwfn, p_ptt,
- GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) *
- PROTECTION_OVERRIDE_ELEMENT_DWORDS;
- if (qed_dmae_grc2host(p_hwfn, p_ptt,
- GRC_REG_PROTECTION_OVERRIDE_WINDOW,
- (u64)(uintptr_t)(dump_buf + offset),
- override_window_dwords, 0))
- return DBG_STATUS_DMAE_FAILED;
- offset += override_window_dwords;
+ qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) *
+ PROTECTION_OVERRIDE_ELEMENT_DWORDS;
+ addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW);
+ offset += qed_grc_dump_addr_range(p_hwfn,
+ p_ptt,
+ dump_buf + offset,
+ true,
+ addr,
+ override_window_dwords,
+ true);
qed_dump_num_param(dump_buf + size_param_offset, dump, "size",
override_window_dwords);
out:
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
*num_dumped_dwords = offset;
@@ -4952,9 +5019,9 @@ static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn,
next_list_idx_addr = fw_asserts_section_addr +
DWORDS_TO_BYTES(asserts->list_next_index_dword_offset);
next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr);
- last_list_idx = (next_list_idx > 0
- ? next_list_idx
- : asserts->list_num_elements) - 1;
+ last_list_idx = (next_list_idx > 0 ?
+ next_list_idx :
+ asserts->list_num_elements) - 1;
addr = BYTES_TO_DWORDS(fw_asserts_section_addr) +
asserts->list_dword_offset +
last_list_idx * asserts->list_element_dword_size;
@@ -4967,7 +5034,7 @@ static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn,
}
/* Dump last section */
- offset += qed_dump_last_section(p_hwfn, dump_buf, offset, dump);
+ offset += qed_dump_last_section(dump_buf, offset, dump);
return offset;
}
@@ -5596,10 +5663,6 @@ struct igu_fifo_addr_data {
#define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4
-/********************************* Macros ************************************/
-
-#define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD)
-
/***************************** Constant Arrays *******************************/
struct user_dbg_array {
@@ -5698,6 +5761,7 @@ struct user_dbg_array {
{"phy_pcie", BLOCK_PHY_PCIE},
{"led", BLOCK_LED},
{"avs_wrap", BLOCK_AVS_WRAP},
+ {"pxpreqbus", BLOCK_PXPREQBUS},
{"misc_aeu", BLOCK_MISC_AEU},
{"bar0_map", BLOCK_BAR0_MAP}
};
@@ -5830,8 +5894,8 @@ struct user_dbg_array {
/* DBG_STATUS_MCP_COULD_NOT_RESUME */
"Failed to resume MCP after halt",
- /* DBG_STATUS_DMAE_FAILED */
- "DMAE transaction failed",
+ /* DBG_STATUS_RESERVED2 */
+ "Reserved debug status - shouldn't be returned",
/* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */
"Failed to empty SEMI sync FIFO",
@@ -6109,6 +6173,7 @@ static u32 qed_read_param(u32 *dump_buf,
if (*(char_buf + offset++)) {
/* String param */
*param_str_val = char_buf + offset;
+ *param_num_val = 0;
offset += strlen(*param_str_val) + 1;
if (offset & 0x3)
offset += (4 - (offset & 0x3));
@@ -6177,8 +6242,7 @@ static u32 qed_print_section_params(u32 *dump_buf,
/* Parses the idle check rules and returns the number of characters printed.
* In case of parsing error, returns 0.
*/
-static u32 qed_parse_idle_chk_dump_rules(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
+static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf,
u32 *dump_buf_end,
u32 num_rules,
bool print_fw_idle_chk,
@@ -6322,8 +6386,7 @@ static u32 qed_parse_idle_chk_dump_rules(struct qed_hwfn *p_hwfn,
* parsed_results_bytes.
* The parsing status is returned.
*/
-static enum dbg_status qed_parse_idle_chk_dump(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
+static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf,
u32 num_dumped_dwords,
char *results_buf,
u32 *parsed_results_bytes,
@@ -6375,13 +6438,16 @@ static enum dbg_status qed_parse_idle_chk_dump(struct qed_hwfn *p_hwfn,
results_offset),
"FW_IDLE_CHECK:\n");
rules_print_size =
- qed_parse_idle_chk_dump_rules(p_hwfn, dump_buf,
- dump_buf_end, num_rules,
+ qed_parse_idle_chk_dump_rules(dump_buf,
+ dump_buf_end,
+ num_rules,
true,
results_buf ?
results_buf +
- results_offset : NULL,
- num_errors, num_warnings);
+ results_offset :
+ NULL,
+ num_errors,
+ num_warnings);
results_offset += rules_print_size;
if (!rules_print_size)
return DBG_STATUS_IDLE_CHK_PARSE_FAILED;
@@ -6392,13 +6458,16 @@ static enum dbg_status qed_parse_idle_chk_dump(struct qed_hwfn *p_hwfn,
results_offset),
"\nLSI_IDLE_CHECK:\n");
rules_print_size =
- qed_parse_idle_chk_dump_rules(p_hwfn, dump_buf,
- dump_buf_end, num_rules,
+ qed_parse_idle_chk_dump_rules(dump_buf,
+ dump_buf_end,
+ num_rules,
false,
results_buf ?
results_buf +
- results_offset : NULL,
- num_errors, num_warnings);
+ results_offset :
+ NULL,
+ num_errors,
+ num_warnings);
results_offset += rules_print_size;
if (!rules_print_size)
return DBG_STATUS_IDLE_CHK_PARSE_FAILED;
@@ -6537,7 +6606,6 @@ static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn,
*/
static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn,
u32 *dump_buf,
- u32 num_dumped_dwords,
char *results_buf,
u32 *parsed_results_bytes)
{
@@ -6725,9 +6793,7 @@ static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn,
* parsed_results_bytes.
* The parsing status is returned.
*/
-static enum dbg_status qed_parse_reg_fifo_dump(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
- u32 num_dumped_dwords,
+static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf,
char *results_buf,
u32 *parsed_results_bytes)
{
@@ -6834,8 +6900,7 @@ static enum dbg_status qed_parse_reg_fifo_dump(struct qed_hwfn *p_hwfn,
static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element
*element, char
*results_buf,
- u32 *results_offset,
- u32 *parsed_results_bytes)
+ u32 *results_offset)
{
const struct igu_fifo_addr_data *found_addr = NULL;
u8 source, err_type, i, is_cleanup;
@@ -6933,9 +6998,9 @@ static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element
"cmd_type: prod/cons update, prod/cons: 0x%x, update_flag: %s, en_dis_int_for_sb : %s, segment : %s, timer_mask = %d, ",
prod_cons,
update_flag ? "update" : "nop",
- en_dis_int_for_sb
- ? (en_dis_int_for_sb == 1 ? "disable" : "nop")
- : "enable",
+ en_dis_int_for_sb ?
+ (en_dis_int_for_sb == 1 ? "disable" : "nop") :
+ "enable",
segment ? "attn" : "regular",
timer_mask);
}
@@ -6969,9 +7034,7 @@ static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element
* parsed_results_bytes.
* The parsing status is returned.
*/
-static enum dbg_status qed_parse_igu_fifo_dump(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
- u32 num_dumped_dwords,
+static enum dbg_status qed_parse_igu_fifo_dump(u32 *dump_buf,
char *results_buf,
u32 *parsed_results_bytes)
{
@@ -7011,8 +7074,7 @@ static enum dbg_status qed_parse_igu_fifo_dump(struct qed_hwfn *p_hwfn,
for (i = 0; i < num_elements; i++) {
status = qed_parse_igu_fifo_element(&elements[i],
results_buf,
- &results_offset,
- parsed_results_bytes);
+ &results_offset);
if (status != DBG_STATUS_OK)
return status;
}
@@ -7028,9 +7090,7 @@ static enum dbg_status qed_parse_igu_fifo_dump(struct qed_hwfn *p_hwfn,
}
static enum dbg_status
-qed_parse_protection_override_dump(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
- u32 num_dumped_dwords,
+qed_parse_protection_override_dump(u32 *dump_buf,
char *results_buf,
u32 *parsed_results_bytes)
{
@@ -7105,9 +7165,7 @@ static enum dbg_status qed_parse_igu_fifo_dump(struct qed_hwfn *p_hwfn,
* parsed_results_bytes.
* The parsing status is returned.
*/
-static enum dbg_status qed_parse_fw_asserts_dump(struct qed_hwfn *p_hwfn,
- u32 *dump_buf,
- u32 num_dumped_dwords,
+static enum dbg_status qed_parse_fw_asserts_dump(u32 *dump_buf,
char *results_buf,
u32 *parsed_results_bytes)
{
@@ -7209,8 +7267,7 @@ enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
{
u32 num_errors, num_warnings;
- return qed_parse_idle_chk_dump(p_hwfn,
- dump_buf,
+ return qed_parse_idle_chk_dump(dump_buf,
num_dumped_dwords,
NULL,
results_buf_size,
@@ -7221,12 +7278,12 @@ enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
u32 *dump_buf,
u32 num_dumped_dwords,
char *results_buf,
- u32 *num_errors, u32 *num_warnings)
+ u32 *num_errors,
+ u32 *num_warnings)
{
u32 parsed_buf_size;
- return qed_parse_idle_chk_dump(p_hwfn,
- dump_buf,
+ return qed_parse_idle_chk_dump(dump_buf,
num_dumped_dwords,
results_buf,
&parsed_buf_size,
@@ -7245,9 +7302,7 @@ enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
u32 *results_buf_size)
{
return qed_parse_mcp_trace_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- NULL, results_buf_size);
+ dump_buf, NULL, results_buf_size);
}
enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
@@ -7259,7 +7314,6 @@ enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
return qed_parse_mcp_trace_dump(p_hwfn,
dump_buf,
- num_dumped_dwords,
results_buf, &parsed_buf_size);
}
@@ -7268,10 +7322,7 @@ enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
u32 num_dumped_dwords,
u32 *results_buf_size)
{
- return qed_parse_reg_fifo_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- NULL, results_buf_size);
+ return qed_parse_reg_fifo_dump(dump_buf, NULL, results_buf_size);
}
enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
@@ -7281,10 +7332,7 @@ enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
{
u32 parsed_buf_size;
- return qed_parse_reg_fifo_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- results_buf, &parsed_buf_size);
+ return qed_parse_reg_fifo_dump(dump_buf, results_buf, &parsed_buf_size);
}
enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
@@ -7292,10 +7340,7 @@ enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
u32 num_dumped_dwords,
u32 *results_buf_size)
{
- return qed_parse_igu_fifo_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- NULL, results_buf_size);
+ return qed_parse_igu_fifo_dump(dump_buf, NULL, results_buf_size);
}
enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
@@ -7305,10 +7350,7 @@ enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
{
u32 parsed_buf_size;
- return qed_parse_igu_fifo_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- results_buf, &parsed_buf_size);
+ return qed_parse_igu_fifo_dump(dump_buf, results_buf, &parsed_buf_size);
}
enum dbg_status
@@ -7317,9 +7359,7 @@ enum dbg_status
u32 num_dumped_dwords,
u32 *results_buf_size)
{
- return qed_parse_protection_override_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
+ return qed_parse_protection_override_dump(dump_buf,
NULL, results_buf_size);
}
@@ -7330,9 +7370,7 @@ enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
{
u32 parsed_buf_size;
- return qed_parse_protection_override_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
+ return qed_parse_protection_override_dump(dump_buf,
results_buf,
&parsed_buf_size);
}
@@ -7342,10 +7380,7 @@ enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
u32 num_dumped_dwords,
u32 *results_buf_size)
{
- return qed_parse_fw_asserts_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
- NULL, results_buf_size);
+ return qed_parse_fw_asserts_dump(dump_buf, NULL, results_buf_size);
}
enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
@@ -7355,9 +7390,7 @@ enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
{
u32 parsed_buf_size;
- return qed_parse_fw_asserts_dump(p_hwfn,
- dump_buf,
- num_dumped_dwords,
+ return qed_parse_fw_asserts_dump(dump_buf,
results_buf, &parsed_buf_size);
}
@@ -7386,30 +7419,30 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
/* Go over registers with a non-zero attention status */
for (i = 0; i < num_regs; i++) {
+ struct dbg_attn_bit_mapping *bit_mapping;
struct dbg_attn_reg_result *reg_result;
- struct dbg_attn_bit_mapping *mapping;
u8 num_reg_attn, bit_idx = 0;
reg_result = &results->reg_results[i];
num_reg_attn = GET_FIELD(reg_result->data,
DBG_ATTN_REG_RESULT_NUM_REG_ATTN);
block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES];
- mapping = &((struct dbg_attn_bit_mapping *)
- block_attn->ptr)[reg_result->block_attn_offset];
+ bit_mapping = &((struct dbg_attn_bit_mapping *)
+ block_attn->ptr)[reg_result->block_attn_offset];
pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS];
/* Go over attention status bits */
for (j = 0; j < num_reg_attn; j++) {
- u16 attn_idx_val = GET_FIELD(mapping[j].data,
+ u16 attn_idx_val = GET_FIELD(bit_mapping[j].data,
DBG_ATTN_BIT_MAPPING_VAL);
const char *attn_name, *attn_type_str, *masked_str;
- u32 name_offset, sts_addr;
+ u32 attn_name_offset, sts_addr;
/* Check if bit mask should be advanced (due to unused
* bits).
*/
- if (GET_FIELD(mapping[j].data,
+ if (GET_FIELD(bit_mapping[j].data,
DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT)) {
bit_idx += (u8)attn_idx_val;
continue;
@@ -7422,9 +7455,10 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
}
/* Find attention name */
- name_offset = block_attn_name_offsets[attn_idx_val];
+ attn_name_offset =
+ block_attn_name_offsets[attn_idx_val];
attn_name = &((const char *)
- pstrings->ptr)[name_offset];
+ pstrings->ptr)[attn_name_offset];
attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ?
"Interrupt" : "Parity";
masked_str = reg_result->mask_val & BIT(bit_idx) ?
diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c
index 58a689f..19adb6e 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_dev.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c
@@ -758,7 +758,7 @@ static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
/* This function reconfigures the QM pf on the fly.
* For this purpose we:
* 1. reconfigure the QM database
- * 2. set new values to runtime arrat
+ * 2. set new values to runtime array
* 3. send an sdm_qm_cmd through the rbc interface to stop the QM
* 4. activate init tool in QM_PF stage
* 5. send an sdm_qm_cmd through rbc interface to release the QM
@@ -784,7 +784,7 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
qed_init_clear_rt_data(p_hwfn);
/* prepare QM portion of runtime array */
- qed_qm_init_pf(p_hwfn, p_ptt);
+ qed_qm_init_pf(p_hwfn, p_ptt, false);
/* activate init tool on runtime array */
rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
@@ -1515,7 +1515,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
}
- /* Protocl Configuration */
+ /* Protocl Configuration */
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
(p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
@@ -1527,6 +1527,11 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
if (rc)
return rc;
+ /* Sanity check before the PF init sequence that uses DMAE */
+ rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
+ if (rc)
+ return rc;
+
/* PF Init sequence */
rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
if (rc)
@@ -2192,7 +2197,7 @@ const char *qed_hw_get_resc_name(enum qed_resources res_id)
/* No need for a case for QED_CMDQS_CQS since
* CNQ/CMDQS are the same resource.
*/
- resc_max_val = NUM_OF_CMDQS_CQS;
+ resc_max_val = NUM_OF_GLOBAL_QUEUES;
break;
case QED_RDMA_STATS_QUEUE:
resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
@@ -2267,7 +2272,7 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
case QED_RDMA_CNQ_RAM:
case QED_CMDQS_CQS:
/* CNQ/CMDQS are the same resource */
- *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
+ *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
break;
case QED_RDMA_STATS_QUEUE:
*p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
diff --git a/drivers/net/ethernet/qlogic/qed/qed_fcoe.c b/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
index df195c0..2dc9b31 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_fcoe.c
@@ -115,7 +115,7 @@ struct qed_fcoe_conn {
struct qed_fcoe_pf_params *fcoe_pf_params = NULL;
struct fcoe_init_ramrod_params *p_ramrod = NULL;
struct fcoe_init_func_ramrod_data *p_data;
- struct fcoe_conn_context *p_cxt = NULL;
+ struct e4_fcoe_conn_context *p_cxt = NULL;
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
struct qed_cxt_info cxt_info;
@@ -167,7 +167,7 @@ struct qed_fcoe_conn {
}
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->tstorm_ag_context.flags3,
- TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
+ E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
fcoe_pf_params->dummy_icid = (u16)dummy_cid;
@@ -568,7 +568,7 @@ int qed_fcoe_alloc(struct qed_hwfn *p_hwfn)
void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
{
- struct fcoe_task_context *p_task_ctx = NULL;
+ struct e4_fcoe_task_context *p_task_ctx = NULL;
int rc;
u32 i;
@@ -580,13 +580,13 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
if (rc)
continue;
- memset(p_task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(p_task_ctx, 0, sizeof(struct e4_fcoe_task_context));
SET_FIELD(p_task_ctx->timer_context.logical_client_0,
TIMERS_CONTEXT_VALIDLC0, 1);
SET_FIELD(p_task_ctx->timer_context.logical_client_1,
TIMERS_CONTEXT_VALIDLC1, 1);
SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,
- TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
+ E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
}
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
index 3427fe70..17d508e 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
@@ -54,7 +54,7 @@
struct qed_hwfn;
struct qed_ptt;
-/* opcodes for the event ring */
+/* Opcodes for the event ring */
enum common_event_opcode {
COMMON_EVENT_PF_START,
COMMON_EVENT_PF_STOP,
@@ -82,487 +82,7 @@ enum common_ramrod_cmd_id {
MAX_COMMON_RAMROD_CMD_ID
};
-/* The core storm context for the Ystorm */
-struct ystorm_core_conn_st_ctx {
- __le32 reserved[4];
-};
-
-/* The core storm context for the Pstorm */
-struct pstorm_core_conn_st_ctx {
- __le32 reserved[4];
-};
-
-/* Core Slowpath Connection storm context of Xstorm */
-struct xstorm_core_conn_st_ctx {
- __le32 spq_base_lo;
- __le32 spq_base_hi;
- struct regpair consolid_base_addr;
- __le16 spq_cons;
- __le16 consolid_cons;
- __le32 reserved0[55];
-};
-
-struct xstorm_core_conn_ag_ctx {
- u8 reserved0;
- u8 core_state;
- u8 flags0;
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
- u8 flags1;
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
- u8 flags2;
-#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
- u8 flags3;
-#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
- u8 flags4;
-#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
- u8 flags5;
-#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
- u8 flags6;
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
- u8 flags7;
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
- u8 flags8;
-#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
- u8 flags9;
-#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
- u8 flags10;
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
- u8 flags11;
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
- u8 flags12;
-#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
- u8 flags13;
-#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
- u8 flags14;
-#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
- u8 byte2;
- __le16 physical_q0;
- __le16 consolid_prod;
- __le16 reserved16;
- __le16 tx_bd_cons;
- __le16 tx_bd_or_spq_prod;
- __le16 word5;
- __le16 conn_dpi;
- u8 byte3;
- u8 byte4;
- u8 byte5;
- u8 byte6;
- __le32 reg0;
- __le32 reg1;
- __le32 reg2;
- __le32 reg3;
- __le32 reg4;
- __le32 reg5;
- __le32 reg6;
- __le16 word7;
- __le16 word8;
- __le16 word9;
- __le16 word10;
- __le32 reg7;
- __le32 reg8;
- __le32 reg9;
- u8 byte7;
- u8 byte8;
- u8 byte9;
- u8 byte10;
- u8 byte11;
- u8 byte12;
- u8 byte13;
- u8 byte14;
- u8 byte15;
- u8 e5_reserved;
- __le16 word11;
- __le32 reg10;
- __le32 reg11;
- __le32 reg12;
- __le32 reg13;
- __le32 reg14;
- __le32 reg15;
- __le32 reg16;
- __le32 reg17;
- __le32 reg18;
- __le32 reg19;
- __le16 word12;
- __le16 word13;
- __le16 word14;
- __le16 word15;
-};
-
-struct tstorm_core_conn_ag_ctx {
- u8 byte0;
- u8 byte1;
- u8 flags0;
-#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */
-#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
-#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
- u8 flags1;
-#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
-#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
-#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
-#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
-#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
- u8 flags2;
-#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
-#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
-#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
-#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
-#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
- u8 flags3;
-#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
-#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
-#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
-#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
-#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
-#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */
-#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
- u8 flags4;
-#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */
-#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */
-#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */
-#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */
-#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */
-#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */
-#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */
-#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
- u8 flags5;
-#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */
-#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
- __le32 reg0;
- __le32 reg1;
- __le32 reg2;
- __le32 reg3;
- __le32 reg4;
- __le32 reg5;
- __le32 reg6;
- __le32 reg7;
- __le32 reg8;
- u8 byte2;
- u8 byte3;
- __le16 word0;
- u8 byte4;
- u8 byte5;
- __le16 word1;
- __le16 word2;
- __le16 word3;
- __le32 reg9;
- __le32 reg10;
-};
-
-struct ustorm_core_conn_ag_ctx {
- u8 reserved;
- u8 byte1;
- u8 flags0;
-#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
- u8 flags1;
-#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
- u8 flags2;
-#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
- u8 flags3;
-#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
- u8 byte2;
- u8 byte3;
- __le16 word0;
- __le16 word1;
- __le32 rx_producers;
- __le32 reg1;
- __le32 reg2;
- __le32 reg3;
- __le16 word2;
- __le16 word3;
-};
-
-/* The core storm context for the Mstorm */
-struct mstorm_core_conn_st_ctx {
- __le32 reserved[24];
-};
-
-/* The core storm context for the Ustorm */
-struct ustorm_core_conn_st_ctx {
- __le32 reserved[4];
-};
-
-/* core connection context */
-struct core_conn_context {
- struct ystorm_core_conn_st_ctx ystorm_st_context;
- struct regpair ystorm_st_padding[2];
- struct pstorm_core_conn_st_ctx pstorm_st_context;
- struct regpair pstorm_st_padding[2];
- struct xstorm_core_conn_st_ctx xstorm_st_context;
- struct xstorm_core_conn_ag_ctx xstorm_ag_context;
- struct tstorm_core_conn_ag_ctx tstorm_ag_context;
- struct ustorm_core_conn_ag_ctx ustorm_ag_context;
- struct mstorm_core_conn_st_ctx mstorm_st_context;
- struct ustorm_core_conn_st_ctx ustorm_st_context;
- struct regpair ustorm_st_padding[2];
-};
-
+/* How ll2 should deal with packet upon errors */
enum core_error_handle {
LL2_DROP_PACKET,
LL2_DO_NOTHING,
@@ -570,21 +90,25 @@ enum core_error_handle {
MAX_CORE_ERROR_HANDLE
};
+/* Opcodes for the event ring */
enum core_event_opcode {
CORE_EVENT_TX_QUEUE_START,
CORE_EVENT_TX_QUEUE_STOP,
CORE_EVENT_RX_QUEUE_START,
CORE_EVENT_RX_QUEUE_STOP,
CORE_EVENT_RX_QUEUE_FLUSH,
+ CORE_EVENT_TX_QUEUE_UPDATE,
MAX_CORE_EVENT_OPCODE
};
+/* The L4 pseudo checksum mode for Core */
enum core_l4_pseudo_checksum_mode {
CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
};
+/* Light-L2 RX Producers in Tstorm RAM */
struct core_ll2_port_stats {
struct regpair gsi_invalid_hdr;
struct regpair gsi_invalid_pkt_length;
@@ -592,6 +116,7 @@ struct core_ll2_port_stats {
struct regpair gsi_crcchksm_error;
};
+/* Ethernet TX Per Queue Stats */
struct core_ll2_pstorm_per_queue_stat {
struct regpair sent_ucast_bytes;
struct regpair sent_mcast_bytes;
@@ -601,6 +126,7 @@ struct core_ll2_pstorm_per_queue_stat {
struct regpair sent_bcast_pkts;
};
+/* Light-L2 RX Producers in Tstorm RAM */
struct core_ll2_rx_prod {
__le16 bd_prod;
__le16 cqe_prod;
@@ -621,6 +147,7 @@ struct core_ll2_ustorm_per_queue_stat {
struct regpair rcv_bcast_pkts;
};
+/* Core Ramrod Command IDs (light L2) */
enum core_ramrod_cmd_id {
CORE_RAMROD_UNUSED,
CORE_RAMROD_RX_QUEUE_START,
@@ -628,45 +155,55 @@ enum core_ramrod_cmd_id {
CORE_RAMROD_RX_QUEUE_STOP,
CORE_RAMROD_TX_QUEUE_STOP,
CORE_RAMROD_RX_QUEUE_FLUSH,
+ CORE_RAMROD_TX_QUEUE_UPDATE,
MAX_CORE_RAMROD_CMD_ID
};
+/* Core RX CQE Type for Light L2 */
enum core_roce_flavor_type {
CORE_ROCE,
CORE_RROCE,
MAX_CORE_ROCE_FLAVOR_TYPE
};
+/* Specifies how ll2 should deal with packets errors: packet_too_big and
+ * no_buff.
+ */
struct core_rx_action_on_error {
u8 error_type;
#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
-#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
-#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
-#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
-#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
-#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
+#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
+#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
+#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
+#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
+#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
};
+/* Core RX BD for Light L2 */
struct core_rx_bd {
struct regpair addr;
__le16 reserved[4];
};
+/* Core RX CM offload BD for Light L2 */
struct core_rx_bd_with_buff_len {
struct regpair addr;
__le16 buff_length;
__le16 reserved[3];
};
+/* Core RX CM offload BD for Light L2 */
union core_rx_bd_union {
struct core_rx_bd rx_bd;
struct core_rx_bd_with_buff_len rx_bd_with_len;
};
+/* Opaque Data for Light L2 RX CQE */
struct core_rx_cqe_opaque_data {
__le32 data[2];
};
+/* Core RX CQE Type for Light L2 */
enum core_rx_cqe_type {
CORE_RX_CQE_ILLIGAL_TYPE,
CORE_RX_CQE_TYPE_REGULAR,
@@ -675,6 +212,7 @@ enum core_rx_cqe_type {
MAX_CORE_RX_CQE_TYPE
};
+/* Core RX CQE for Light L2 */
struct core_rx_fast_path_cqe {
u8 type;
u8 placement_offset;
@@ -687,6 +225,7 @@ struct core_rx_fast_path_cqe {
__le32 reserved1[3];
};
+/* Core Rx CM offload CQE */
struct core_rx_gsi_offload_cqe {
u8 type;
u8 data_length_error;
@@ -696,9 +235,11 @@ struct core_rx_gsi_offload_cqe {
__le32 src_mac_addrhi;
__le16 src_mac_addrlo;
__le16 qp_id;
- __le32 gid_dst[4];
+ __le32 src_qp;
+ __le32 reserved[3];
};
+/* Core RX CQE for Light L2 */
struct core_rx_slow_path_cqe {
u8 type;
u8 ramrod_cmd_id;
@@ -707,12 +248,14 @@ struct core_rx_slow_path_cqe {
__le32 reserved1[5];
};
+/* Core RX CM offload BD for Light L2 */
union core_rx_cqe_union {
struct core_rx_fast_path_cqe rx_cqe_fp;
struct core_rx_gsi_offload_cqe rx_cqe_gsi;
struct core_rx_slow_path_cqe rx_cqe_sp;
};
+/* Ramrod data for rx queue start ramrod */
struct core_rx_start_ramrod_data {
struct regpair bd_base;
struct regpair cqe_pbl_addr;
@@ -723,16 +266,18 @@ struct core_rx_start_ramrod_data {
u8 complete_event_flg;
u8 drop_ttl0_flg;
__le16 num_of_pbl_pages;
- u8 inner_vlan_removal_en;
+ u8 inner_vlan_stripping_en;
+ u8 report_outer_vlan;
u8 queue_id;
u8 main_func_queue;
u8 mf_si_bcast_accept_all;
u8 mf_si_mcast_accept_all;
struct core_rx_action_on_error action_on_error;
u8 gsi_offload_flag;
- u8 reserved[7];
+ u8 reserved[6];
};
+/* Ramrod data for rx queue stop ramrod */
struct core_rx_stop_ramrod_data {
u8 complete_cqe_flg;
u8 complete_event_flg;
@@ -741,46 +286,51 @@ struct core_rx_stop_ramrod_data {
__le16 reserved2[2];
};
+/* Flags for Core TX BD */
struct core_tx_bd_data {
__le16 as_bitfield;
-#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
-#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
-#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
-#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
-#define CORE_TX_BD_DATA_START_BD_MASK 0x1
-#define CORE_TX_BD_DATA_START_BD_SHIFT 2
-#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
-#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
-#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
-#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
-#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
-#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
-#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
-#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
+#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
+#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
+#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
+#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
+#define CORE_TX_BD_DATA_START_BD_MASK 0x1
+#define CORE_TX_BD_DATA_START_BD_SHIFT 2
+#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
+#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
+#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
+#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
+#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
+#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
+#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
+#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
-#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
-#define CORE_TX_BD_DATA_NBDS_MASK 0xF
-#define CORE_TX_BD_DATA_NBDS_SHIFT 8
-#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
-#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
-#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
-#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
-#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
-#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
-};
-
+#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
+#define CORE_TX_BD_DATA_NBDS_MASK 0xF
+#define CORE_TX_BD_DATA_NBDS_SHIFT 8
+#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
+#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
+#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
+#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
+#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
+#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
+#define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
+#define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
+};
+
+/* Core TX BD for Light L2 */
struct core_tx_bd {
struct regpair addr;
__le16 nbytes;
__le16 nw_vlan_or_lb_echo;
struct core_tx_bd_data bd_data;
__le16 bitfield1;
-#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
-#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
-#define CORE_TX_BD_TX_DST_MASK 0x3
-#define CORE_TX_BD_TX_DST_SHIFT 14
+#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
+#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
+#define CORE_TX_BD_TX_DST_MASK 0x3
+#define CORE_TX_BD_TX_DST_SHIFT 14
};
+/* Light L2 TX Destination */
enum core_tx_dest {
CORE_TX_DEST_NW,
CORE_TX_DEST_LB,
@@ -789,6 +339,7 @@ enum core_tx_dest {
MAX_CORE_TX_DEST
};
+/* Ramrod data for tx queue start ramrod */
struct core_tx_start_ramrod_data {
struct regpair pbl_base_addr;
__le16 mtu;
@@ -803,10 +354,20 @@ struct core_tx_start_ramrod_data {
u8 resrved[3];
};
+/* Ramrod data for tx queue stop ramrod */
struct core_tx_stop_ramrod_data {
__le32 reserved0[2];
};
+/* Ramrod data for tx queue update ramrod */
+struct core_tx_update_ramrod_data {
+ u8 update_qm_pq_id_flg;
+ u8 reserved0;
+ __le16 qm_pq_id;
+ __le32 reserved1[1];
+};
+
+/* Enum flag for what type of dcb data to update */
enum dcb_dscp_update_mode {
DONT_UPDATE_DCB_DSCP,
UPDATE_DCB,
@@ -815,6 +376,487 @@ enum dcb_dscp_update_mode {
MAX_DCB_DSCP_UPDATE_MODE
};
+/* The core storm context for the Ystorm */
+struct ystorm_core_conn_st_ctx {
+ __le32 reserved[4];
+};
+
+/* The core storm context for the Pstorm */
+struct pstorm_core_conn_st_ctx {
+ __le32 reserved[4];
+};
+
+/* Core Slowpath Connection storm context of Xstorm */
+struct xstorm_core_conn_st_ctx {
+ __le32 spq_base_lo;
+ __le32 spq_base_hi;
+ struct regpair consolid_base_addr;
+ __le16 spq_cons;
+ __le16 consolid_cons;
+ __le32 reserved0[55];
+};
+
+struct e4_xstorm_core_conn_ag_ctx {
+ u8 reserved0;
+ u8 state;
+ u8 flags0;
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
+ u8 flags1;
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+ u8 flags2;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
+ u8 flags3;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
+ u8 flags4;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
+ u8 flags5;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
+ u8 flags6;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+ u8 flags7;
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
+ u8 flags8;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
+ u8 flags9;
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
+ u8 flags10;
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
+ u8 flags11;
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
+ u8 flags12;
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
+ u8 flags13;
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+ u8 flags14;
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
+ u8 byte2;
+ __le16 physical_q0;
+ __le16 consolid_prod;
+ __le16 reserved16;
+ __le16 tx_bd_cons;
+ __le16 tx_bd_or_spq_prod;
+ __le16 word5;
+ __le16 conn_dpi;
+ u8 byte3;
+ u8 byte4;
+ u8 byte5;
+ u8 byte6;
+ __le32 reg0;
+ __le32 reg1;
+ __le32 reg2;
+ __le32 reg3;
+ __le32 reg4;
+ __le32 reg5;
+ __le32 reg6;
+ __le16 word7;
+ __le16 word8;
+ __le16 word9;
+ __le16 word10;
+ __le32 reg7;
+ __le32 reg8;
+ __le32 reg9;
+ u8 byte7;
+ u8 byte8;
+ u8 byte9;
+ u8 byte10;
+ u8 byte11;
+ u8 byte12;
+ u8 byte13;
+ u8 byte14;
+ u8 byte15;
+ u8 e5_reserved;
+ __le16 word11;
+ __le32 reg10;
+ __le32 reg11;
+ __le32 reg12;
+ __le32 reg13;
+ __le32 reg14;
+ __le32 reg15;
+ __le32 reg16;
+ __le32 reg17;
+ __le32 reg18;
+ __le32 reg19;
+ __le16 word12;
+ __le16 word13;
+ __le16 word14;
+ __le16 word15;
+};
+
+struct e4_tstorm_core_conn_ag_ctx {
+ u8 byte0;
+ u8 byte1;
+ u8 flags0;
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
+ u8 flags1;
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
+ u8 flags2;
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
+ u8 flags3;
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
+ u8 flags4;
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
+ u8 flags5;
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
+ __le32 reg0;
+ __le32 reg1;
+ __le32 reg2;
+ __le32 reg3;
+ __le32 reg4;
+ __le32 reg5;
+ __le32 reg6;
+ __le32 reg7;
+ __le32 reg8;
+ u8 byte2;
+ u8 byte3;
+ __le16 word0;
+ u8 byte4;
+ u8 byte5;
+ __le16 word1;
+ __le16 word2;
+ __le16 word3;
+ __le32 reg9;
+ __le32 reg10;
+};
+
+struct e4_ustorm_core_conn_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ u8 flags0;
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+ u8 flags1;
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
+ u8 flags2;
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
+ u8 flags3;
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
+ u8 byte2;
+ u8 byte3;
+ __le16 word0;
+ __le16 word1;
+ __le32 rx_producers;
+ __le32 reg1;
+ __le32 reg2;
+ __le32 reg3;
+ __le16 word2;
+ __le16 word3;
+};
+
+/* The core storm context for the Mstorm */
+struct mstorm_core_conn_st_ctx {
+ __le32 reserved[24];
+};
+
+/* The core storm context for the Ustorm */
+struct ustorm_core_conn_st_ctx {
+ __le32 reserved[4];
+};
+
+/* core connection context */
+struct e4_core_conn_context {
+ struct ystorm_core_conn_st_ctx ystorm_st_context;
+ struct regpair ystorm_st_padding[2];
+ struct pstorm_core_conn_st_ctx pstorm_st_context;
+ struct regpair pstorm_st_padding[2];
+ struct xstorm_core_conn_st_ctx xstorm_st_context;
+ struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
+ struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
+ struct mstorm_core_conn_st_ctx mstorm_st_context;
+ struct ustorm_core_conn_st_ctx ustorm_st_context;
+ struct regpair ustorm_st_padding[2];
+};
+
struct eth_mstorm_per_pf_stat {
struct regpair gre_discard_pkts;
struct regpair vxlan_discard_pkts;
@@ -896,6 +938,50 @@ struct eth_ustorm_per_queue_stat {
struct regpair rcv_bcast_pkts;
};
+/* Event Ring VF-PF Channel data */
+struct vf_pf_channel_eqe_data {
+ struct regpair msg_addr;
+};
+
+/* Event Ring malicious VF data */
+struct malicious_vf_eqe_data {
+ u8 vf_id;
+ u8 err_id;
+ __le16 reserved[3];
+};
+
+/* Event Ring initial cleanup data */
+struct initial_cleanup_eqe_data {
+ u8 vf_id;
+ u8 reserved[7];
+};
+
+/* Event Data Union */
+union event_ring_data {
+ u8 bytes[8];
+ struct vf_pf_channel_eqe_data vf_pf_channel;
+ struct iscsi_eqe_data iscsi_info;
+ struct iscsi_connect_done_results iscsi_conn_done_info;
+ union rdma_eqe_data rdma_data;
+ struct malicious_vf_eqe_data malicious_vf;
+ struct initial_cleanup_eqe_data vf_init_cleanup;
+};
+
+/* Event Ring Entry */
+struct event_ring_entry {
+ u8 protocol_id;
+ u8 opcode;
+ __le16 reserved0;
+ __le16 echo;
+ u8 fw_return_code;
+ u8 flags;
+#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
+#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
+#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
+#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
+ union event_ring_data data;
+};
+
/* Event Ring Next Page Address */
struct event_ring_next_addr {
struct regpair addr;
@@ -908,27 +994,37 @@ struct event_ring_next_addr {
struct event_ring_next_addr next_addr;
};
+/* Ports mode */
enum fw_flow_ctrl_mode {
flow_ctrl_pause,
flow_ctrl_pfc,
MAX_FW_FLOW_CTRL_MODE
};
+/* GFT profile type */
+enum gft_profile_type {
+ GFT_PROFILE_TYPE_4_TUPLE,
+ GFT_PROFILE_TYPE_L4_DST_PORT,
+ GFT_PROFILE_TYPE_IP_DST_PORT,
+ MAX_GFT_PROFILE_TYPE
+};
+
/* Major and Minor hsi Versions */
struct hsi_fp_ver_struct {
u8 minor_ver_arr[2];
u8 major_ver_arr[2];
};
+/* Ports mode */
enum iwarp_ll2_tx_queues {
- IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
+ IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
IWARP_LL2_ALIGNED_TX_QUEUE,
IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
IWARP_LL2_ERROR,
MAX_IWARP_LL2_TX_QUEUES
};
-/* Mstorm non-triggering VF zone */
+/* Malicious VF error ID */
enum malicious_vf_error_id {
MALICIOUS_VF_NO_ERROR,
VF_PF_CHANNEL_NOT_READY,
@@ -951,9 +1047,11 @@ enum malicious_vf_error_id {
ETH_TUNN_IPV6_EXT_NBD_ERR,
ETH_CONTROL_PACKET_VIOLATION,
ETH_ANTI_SPOOFING_ERR,
+ ETH_PACKET_SIZE_TOO_LARGE,
MAX_MALICIOUS_VF_ERROR_ID
};
+/* Mstorm non-triggering VF zone */
struct mstorm_non_trigger_vf_zone {
struct eth_mstorm_per_queue_stat eth_queue_stat;
struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
@@ -962,7 +1060,21 @@ struct mstorm_non_trigger_vf_zone {
/* Mstorm VF zone */
struct mstorm_vf_zone {
struct mstorm_non_trigger_vf_zone non_trigger;
+};
+
+/* vlan header including TPID and TCI fields */
+struct vlan_header {
+ __le16 tpid;
+ __le16 tci;
+};
+/* outer tag configurations */
+struct outer_tag_config_struct {
+ u8 enable_stag_pri_change;
+ u8 pri_map_valid;
+ u8 reserved[2];
+ struct vlan_header outer_tag;
+ u8 inner_to_outer_pri_map[8];
};
/* personality per PF */
@@ -974,7 +1086,7 @@ enum personality_type {
PERSONALITY_RDMA,
PERSONALITY_CORE,
PERSONALITY_ETH,
- PERSONALITY_RESERVED4,
+ PERSONALITY_RESERVED,
MAX_PERSONALITY_TYPE
};
@@ -997,7 +1109,7 @@ struct pf_start_ramrod_data {
struct regpair event_ring_pbl_addr;
struct regpair consolid_q_pbl_addr;
struct pf_start_tunnel_config tunnel_config;
- __le32 reserved;
+
__le16 event_ring_sb_id;
u8 base_vf_id;
u8 num_vfs;
@@ -1011,21 +1123,23 @@ struct pf_start_ramrod_data {
u8 mf_mode;
u8 integ_phase;
u8 allow_npar_tx_switching;
- u8 inner_to_outer_pri_map[8];
- u8 pri_map_valid;
- __le32 outer_tag;
+
+ u8 reserved0;
struct hsi_fp_ver_struct hsi_fp_ver;
+ struct outer_tag_config_struct outer_tag_config;
};
+/* Data for port update ramrod */
struct protocol_dcb_data {
u8 dcb_enable_flag;
- u8 reserved_a;
+ u8 dscp_enable_flag;
u8 dcb_priority;
u8 dcb_tc;
- u8 reserved_b;
+ u8 dscp_val;
u8 reserved0;
};
+/* Update tunnel configuration */
struct pf_update_tunnel_config {
u8 update_rx_pf_clss;
u8 update_rx_def_ucast_clss;
@@ -1042,8 +1156,8 @@ struct pf_update_tunnel_config {
__le16 reserved;
};
+/* Data for port update ramrod */
struct pf_update_ramrod_data {
- u8 pf_id;
u8 update_eth_dcb_data_mode;
u8 update_fcoe_dcb_data_mode;
u8 update_iscsi_dcb_data_mode;
@@ -1051,6 +1165,7 @@ struct pf_update_ramrod_data {
u8 update_rroce_dcb_data_mode;
u8 update_iwarp_dcb_data_mode;
u8 update_mf_vlan_flag;
+ u8 update_enable_stag_pri_change;
struct protocol_dcb_data eth_dcb_data;
struct protocol_dcb_data fcoe_dcb_data;
struct protocol_dcb_data iscsi_dcb_data;
@@ -1058,7 +1173,8 @@ struct pf_update_ramrod_data {
struct protocol_dcb_data rroce_dcb_data;
struct protocol_dcb_data iwarp_dcb_data;
__le16 mf_vlan;
- __le16 reserved;
+ u8 enable_stag_pri_change;
+ u8 reserved;
struct pf_update_tunnel_config tunnel_config;
};
@@ -1079,11 +1195,13 @@ enum protocol_version_array_key {
MAX_PROTOCOL_VERSION_ARRAY_KEY
};
+/* RDMA TX Stats */
struct rdma_sent_stats {
struct regpair sent_bytes;
struct regpair sent_pkts;
};
+/* Pstorm non-triggering VF zone */
struct pstorm_non_trigger_vf_zone {
struct eth_pstorm_per_queue_stat eth_queue_stat;
struct rdma_sent_stats rdma_stats;
@@ -1103,11 +1221,34 @@ struct ramrod_header {
__le16 echo;
};
+/* RDMA RX Stats */
struct rdma_rcv_stats {
struct regpair rcv_bytes;
struct regpair rcv_pkts;
};
+/* Data for update QCN/DCQCN RL ramrod */
+struct rl_update_ramrod_data {
+ u8 qcn_update_param_flg;
+ u8 dcqcn_update_param_flg;
+ u8 rl_init_flg;
+ u8 rl_start_flg;
+ u8 rl_stop_flg;
+ u8 rl_id_first;
+ u8 rl_id_last;
+ u8 rl_dc_qcn_flg;
+ __le32 rl_bc_rate;
+ __le16 rl_max_rate;
+ __le16 rl_r_ai;
+ __le16 rl_r_hai;
+ __le16 dcqcn_g;
+ __le32 dcqcn_k_us;
+ __le32 dcqcn_timeuot_us;
+ __le32 qcn_timeuot_us;
+ __le32 reserved[2];
+};
+
+/* Slowpath Element (SPQE) */
struct slow_path_element {
struct ramrod_header hdr;
struct regpair data_ptr;
@@ -1130,11 +1271,12 @@ struct tstorm_per_port_stat {
struct regpair roce_irregular_pkt;
struct regpair iwarp_irregular_pkt;
struct regpair eth_irregular_pkt;
- struct regpair reserved1;
+ struct regpair toe_irregular_pkt;
struct regpair preroce_irregular_pkt;
struct regpair eth_gre_tunn_filter_discard;
struct regpair eth_vxlan_tunn_filter_discard;
struct regpair eth_geneve_tunn_filter_discard;
+ struct regpair eth_gft_drop_pkt;
};
/* Tstorm VF zone */
@@ -1197,6 +1339,7 @@ struct vf_stop_ramrod_data {
__le32 reserved2;
};
+/* VF zone size mode */
enum vf_zone_size_mode {
VF_ZONE_SIZE_MODE_DEFAULT,
VF_ZONE_SIZE_MODE_DOUBLE,
@@ -1204,6 +1347,7 @@ enum vf_zone_size_mode {
MAX_VF_ZONE_SIZE_MODE
};
+/* Attentions status block */
struct atten_status_block {
__le32 atten_bits;
__le32 atten_ack;
@@ -1212,11 +1356,6 @@ struct atten_status_block {
__le32 reserved1;
};
-enum command_type_bit {
- IGU_COMMAND_TYPE_NOP = 0,
- IGU_COMMAND_TYPE_SET = 1,
- MAX_COMMAND_TYPE_BIT
-};
/* DMAE command */
struct dmae_cmd {
@@ -1327,74 +1466,74 @@ enum dmae_cmd_src_enum {
MAX_DMAE_CMD_SRC_ENUM
};
-struct mstorm_core_conn_ag_ctx {
+struct e4_mstorm_core_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct ystorm_core_conn_ag_ctx {
+struct e4_ystorm_core_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -1545,22 +1684,22 @@ struct qm_rf_opportunistic_mask {
};
/* QM hardware structure of QM map memory */
-struct qm_rf_pq_map {
+struct qm_rf_pq_map_e4 {
__le32 reg;
-#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
-#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
-#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
-#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
-#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
-#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
-#define QM_RF_PQ_MAP_VOQ_MASK 0x1F
-#define QM_RF_PQ_MAP_VOQ_SHIFT 18
-#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
-#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
-#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
-#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
-#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
-#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
+#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
+#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
+#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
+#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
+#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
+#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
+#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
+#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
+#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
+#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
+#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
+#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
+#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
+#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
};
/* Completion params for aggregated interrupt completion */
@@ -1643,8 +1782,8 @@ enum block_addr {
GRCBASE_MULD = 0x4e0000,
GRCBASE_YULD = 0x4c8000,
GRCBASE_XYLD = 0x4c0000,
- GRCBASE_PTLD = 0x590000,
- GRCBASE_YPLD = 0x5b0000,
+ GRCBASE_PTLD = 0x5a0000,
+ GRCBASE_YPLD = 0x5c0000,
GRCBASE_PRM = 0x230000,
GRCBASE_PBF_PB1 = 0xda0000,
GRCBASE_PBF_PB2 = 0xda4000,
@@ -1675,6 +1814,7 @@ enum block_addr {
GRCBASE_PHY_PCIE = 0x620000,
GRCBASE_LED = 0x6b8000,
GRCBASE_AVS_WRAP = 0x6b0000,
+ GRCBASE_PXPREQBUS = 0x56000,
GRCBASE_MISC_AEU = 0x8000,
GRCBASE_BAR0_MAP = 0x1c00000,
MAX_BLOCK_ADDR
@@ -1766,6 +1906,7 @@ enum block_id {
BLOCK_PHY_PCIE,
BLOCK_LED,
BLOCK_AVS_WRAP,
+ BLOCK_PXPREQBUS,
BLOCK_MISC_AEU,
BLOCK_BAR0_MAP,
MAX_BLOCK_ID
@@ -1841,7 +1982,7 @@ struct dbg_attn_block_result {
struct dbg_attn_reg_result reg_results[15];
};
-/* mode header */
+/* Mode header */
struct dbg_mode_hdr {
__le16 data;
#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
@@ -1863,80 +2004,83 @@ struct dbg_attn_reg {
__le32 mask_address;
};
-/* attention types */
+/* Attention types */
enum dbg_attn_type {
ATTN_TYPE_INTERRUPT,
ATTN_TYPE_PARITY,
MAX_DBG_ATTN_TYPE
};
+/* Debug Bus block data */
struct dbg_bus_block {
u8 num_of_lines;
u8 has_latency_events;
__le16 lines_offset;
};
+/* Debug Bus block user data */
struct dbg_bus_block_user_data {
u8 num_of_lines;
u8 has_latency_events;
__le16 names_offset;
};
+/* Block Debug line data */
struct dbg_bus_line {
u8 data;
-#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
-#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
-#define DBG_BUS_LINE_IS_256B_MASK 0x1
-#define DBG_BUS_LINE_IS_256B_SHIFT 4
-#define DBG_BUS_LINE_RESERVED_MASK 0x7
-#define DBG_BUS_LINE_RESERVED_SHIFT 5
+#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
+#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
+#define DBG_BUS_LINE_IS_256B_MASK 0x1
+#define DBG_BUS_LINE_IS_256B_SHIFT 4
+#define DBG_BUS_LINE_RESERVED_MASK 0x7
+#define DBG_BUS_LINE_RESERVED_SHIFT 5
u8 group_sizes;
};
-/* condition header for registers dump */
+/* Condition header for registers dump */
struct dbg_dump_cond_hdr {
struct dbg_mode_hdr mode; /* Mode header */
u8 block_id; /* block ID */
u8 data_size; /* size in dwords of the data following this header */
};
-/* memory data for registers dump */
+/* Memory data for registers dump */
struct dbg_dump_mem {
__le32 dword0;
-#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
-#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
-#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
-#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
+#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
+#define DBG_DUMP_MEM_ADDRESS_SHIFT 0
+#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
+#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
__le32 dword1;
-#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
-#define DBG_DUMP_MEM_LENGTH_SHIFT 0
-#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
-#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
-#define DBG_DUMP_MEM_RESERVED_MASK 0x7F
-#define DBG_DUMP_MEM_RESERVED_SHIFT 25
+#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
+#define DBG_DUMP_MEM_LENGTH_SHIFT 0
+#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
+#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
+#define DBG_DUMP_MEM_RESERVED_MASK 0x7F
+#define DBG_DUMP_MEM_RESERVED_SHIFT 25
};
-/* register data for registers dump */
+/* Register data for registers dump */
struct dbg_dump_reg {
__le32 data;
-#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */
-#define DBG_DUMP_REG_ADDRESS_SHIFT 0
-#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates register is wide-bus */
-#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
-#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */
-#define DBG_DUMP_REG_LENGTH_SHIFT 24
+#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
+#define DBG_DUMP_REG_ADDRESS_SHIFT 0
+#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
+#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
+#define DBG_DUMP_REG_LENGTH_MASK 0xFF
+#define DBG_DUMP_REG_LENGTH_SHIFT 24
};
-/* split header for registers dump */
+/* Split header for registers dump */
struct dbg_dump_split_hdr {
__le32 hdr;
-#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
-#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
-#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
-#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
+#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
+#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
};
-/* condition header for idle check */
+/* Condition header for idle check */
struct dbg_idle_chk_cond_hdr {
struct dbg_mode_hdr mode; /* Mode header */
__le16 data_size; /* size in dwords of the data following this header */
@@ -1945,12 +2089,12 @@ struct dbg_idle_chk_cond_hdr {
/* Idle Check condition register */
struct dbg_idle_chk_cond_reg {
__le32 data;
-#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
-#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
-#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
-#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
-#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
-#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
+#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
+#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
+#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
+#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
+#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
__le16 num_entries;
u8 entry_size;
u8 start_entry;
@@ -1959,12 +2103,12 @@ struct dbg_idle_chk_cond_reg {
/* Idle Check info register */
struct dbg_idle_chk_info_reg {
__le32 data;
-#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
-#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
-#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
-#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
-#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
-#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
+#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
+#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
+#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
+#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
__le16 size; /* register size in dwords */
struct dbg_mode_hdr mode; /* Mode header */
};
@@ -2016,13 +2160,13 @@ struct dbg_idle_chk_rule {
/* Idle Check rule parsing data */
struct dbg_idle_chk_rule_parsing_data {
__le32 data;
-#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
-#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
-#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
-#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
+#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
};
-/* idle check severity types */
+/* Idle check severity types */
enum dbg_idle_chk_severity_types {
/* idle check failure should cause an error */
IDLE_CHK_SEVERITY_ERROR,
@@ -2036,14 +2180,14 @@ enum dbg_idle_chk_severity_types {
/* Debug Bus block data */
struct dbg_bus_block_data {
__le16 data;
-#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
-#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
-#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
-#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
-#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
-#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
-#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
-#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
+#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
+#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
+#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
+#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
+#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
+#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
+#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
+#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
u8 line_num;
u8 hw_id;
};
@@ -2072,6 +2216,7 @@ enum dbg_bus_clients {
MAX_DBG_BUS_CLIENTS
};
+/* Debug Bus constraint operation types */
enum dbg_bus_constraint_ops {
DBG_BUS_CONSTRAINT_OP_EQ,
DBG_BUS_CONSTRAINT_OP_NE,
@@ -2086,12 +2231,13 @@ enum dbg_bus_constraint_ops {
MAX_DBG_BUS_CONSTRAINT_OPS
};
+/* Debug Bus trigger state data */
struct dbg_bus_trigger_state_data {
u8 data;
-#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
-#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
-#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
-#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
+#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
+#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
+#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
+#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
};
/* Debug Bus memory address */
@@ -2165,6 +2311,7 @@ struct dbg_bus_data {
struct dbg_bus_storm_data storms[6];
};
+/* Debug bus filter types */
enum dbg_bus_filter_types {
DBG_BUS_FILTER_TYPE_OFF,
DBG_BUS_FILTER_TYPE_PRE,
@@ -2181,6 +2328,7 @@ enum dbg_bus_frame_modes {
MAX_DBG_BUS_FRAME_MODES
};
+/* Debug bus other engine mode */
enum dbg_bus_other_engine_modes {
DBG_BUS_OTHER_ENGINE_MODE_NONE,
DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
@@ -2190,12 +2338,14 @@ enum dbg_bus_other_engine_modes {
MAX_DBG_BUS_OTHER_ENGINE_MODES
};
+/* Debug bus post-trigger recording types */
enum dbg_bus_post_trigger_types {
DBG_BUS_POST_TRIGGER_RECORD,
DBG_BUS_POST_TRIGGER_DROP,
MAX_DBG_BUS_POST_TRIGGER_TYPES
};
+/* Debug bus pre-trigger recording types */
enum dbg_bus_pre_trigger_types {
DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
@@ -2203,11 +2353,10 @@ enum dbg_bus_pre_trigger_types {
MAX_DBG_BUS_PRE_TRIGGER_TYPES
};
+/* Debug bus SEMI frame modes */
enum dbg_bus_semi_frame_modes {
- DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST =
- 0,
- DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST =
- 3,
+ DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
+ DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
MAX_DBG_BUS_SEMI_FRAME_MODES
};
@@ -2220,6 +2369,7 @@ enum dbg_bus_states {
MAX_DBG_BUS_STATES
};
+/* Debug Bus Storm modes */
enum dbg_bus_storm_modes {
DBG_BUS_STORM_MODE_PRINTF,
DBG_BUS_STORM_MODE_PRAM_ADDR,
@@ -2352,7 +2502,7 @@ enum dbg_status {
DBG_STATUS_MCP_TRACE_NO_META,
DBG_STATUS_MCP_COULD_NOT_HALT,
DBG_STATUS_MCP_COULD_NOT_RESUME,
- DBG_STATUS_DMAE_FAILED,
+ DBG_STATUS_RESERVED2,
DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
DBG_STATUS_IGU_FIFO_BAD_DATA,
DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
@@ -2396,7 +2546,8 @@ struct dbg_tools_data {
u8 chip_id;
u8 platform_id;
u8 initialized;
- u8 reserved;
+ u8 use_dmae;
+ __le32 num_regs_read;
};
/********************************/
@@ -2406,6 +2557,7 @@ struct dbg_tools_data {
/* Number of VLAN priorities */
#define NUM_OF_VLAN_PRIORITIES 8
+/* BRB RAM init requirements */
struct init_brb_ram_req {
__le32 guranteed_per_tc;
__le32 headroom_per_tc;
@@ -2414,17 +2566,20 @@ struct init_brb_ram_req {
u8 num_active_tcs[MAX_NUM_PORTS];
};
+/* ETS per-TC init requirements */
struct init_ets_tc_req {
u8 use_sp;
u8 use_wfq;
__le16 weight;
};
+/* ETS init requirements */
struct init_ets_req {
__le32 mtu;
struct init_ets_tc_req tc_req[NUM_OF_TCS];
};
+/* NIG LB RL init requirements */
struct init_nig_lb_rl_req {
__le16 lb_mac_rate;
__le16 lb_rate;
@@ -2432,15 +2587,18 @@ struct init_nig_lb_rl_req {
__le16 tc_rate[NUM_OF_PHYS_TCS];
};
+/* NIG TC mapping for each priority */
struct init_nig_pri_tc_map_entry {
u8 tc_id;
u8 valid;
};
+/* NIG priority to TC map init requirements */
struct init_nig_pri_tc_map_req {
struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
};
+/* QM per-port init parameters */
struct init_qm_port_params {
u8 active;
u8 active_phys_tcs;
@@ -2563,7 +2721,7 @@ struct bin_buffer_hdr {
__le32 length;
};
-/* binary init buffer types */
+/* Binary init buffer types */
enum bin_init_buffer_type {
BIN_BUF_INIT_FW_VER_INFO,
BIN_BUF_INIT_CMD,
@@ -2793,6 +2951,7 @@ struct iro {
};
/***************************** Public Functions *******************************/
+
/**
* @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
* arrays.
@@ -2802,6 +2961,18 @@ struct iro {
enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
/**
+ * @brief qed_read_regs - Reads registers into a buffer (using GRC).
+ *
+ * @param p_hwfn - HW device data
+ * @param p_ptt - Ptt window used for writing the registers.
+ * @param buf - Destination buffer.
+ * @param addr - Source GRC address in dwords.
+ * @param len - Number of registers to read.
+ */
+void qed_read_regs(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
+
+/**
* @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
* default value.
*
@@ -3119,6 +3290,7 @@ enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
#define MAX_NAME_LEN 16
/***************************** Public Functions *******************************/
+
/**
* @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
* debug arrays.
@@ -3172,6 +3344,18 @@ enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
u32 *num_warnings);
/**
+ * @brief qed_dbg_mcp_trace_set_meta_data - Sets a pointer to the MCP Trace
+ * meta data.
+ *
+ * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
+ * no NVRAM access).
+ *
+ * @param data - pointer to MCP Trace meta data
+ * @param size - size of MCP Trace meta data in dwords
+ */
+void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size);
+
+/**
* @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
* for MCP Trace results (in bytes).
*
@@ -3607,6 +3791,9 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
0x00000000, /* bar0_map, bb, 0 lines */
0x00000000, /* bar0_map, k2, 0 lines */
0x00000000,
+ 0x00000000, /* bar0_map, bb, 0 lines */
+ 0x00000000, /* bar0_map, k2, 0 lines */
+ 0x00000000,
};
/* Win 2 */
@@ -3645,7 +3832,6 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
* Returns the required host memory size in 4KB units.
* Must be called before all QM init HSI functions.
*
- * @param pf_id - physical function ID
* @param num_pf_cids - number of connections used by this PF
* @param num_vf_cids - number of connections used by VFs of this PF
* @param num_tids - number of tasks used by this PF
@@ -3654,8 +3840,7 @@ enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
*
* @return The required host memory size in 4KB units.
*/
-u32 qed_qm_pf_mem_size(u8 pf_id,
- u32 num_pf_cids,
+u32 qed_qm_pf_mem_size(u32 num_pf_cids,
u32 num_vf_cids,
u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
@@ -3676,7 +3861,7 @@ struct qed_qm_pf_rt_init_params {
u8 port_id;
u8 pf_id;
u8 max_phys_tcs_per_port;
- bool is_first_pf;
+ bool is_pf_loading;
u32 num_pf_cids;
u32 num_vf_cids;
u32 num_tids;
@@ -3687,6 +3872,7 @@ struct qed_qm_pf_rt_init_params {
u8 num_vports;
u16 pf_wfq;
u32 pf_rl;
+ u32 link_speed;
struct init_qm_pq_params *pq_params;
struct init_qm_vport_params *vport_params;
};
@@ -3744,11 +3930,14 @@ int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
* @param p_ptt - ptt window used for writing the registers
* @param vport_id - VPORT ID
* @param vport_rl - rate limit in Mb/sec units
+ * @param link_speed - link speed in Mbps.
*
* @return 0 on success, -1 on error.
*/
int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl);
+ struct qed_ptt *p_ptt,
+ u8 vport_id, u32 vport_rl, u32 link_speed);
+
/**
* @brief qed_send_qm_stop_cmd Sends a stop command to the QM
*
@@ -3759,7 +3948,8 @@ int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
* @param start_pq - first PQ ID to stop
* @param num_pqs - Number of PQs to stop, starting from start_pq.
*
- * @return bool, true if successful, false if timeout occured while waiting for QM command done.
+ * @return bool, true if successful, false if timeout occurred while waiting for
+ * QM command done.
*/
bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@@ -3769,6 +3959,7 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
/**
* @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
*
+ * @param p_hwfn
* @param p_ptt - ptt window used for writing the registers.
* @param dest_port - vxlan destination udp port.
*/
@@ -3778,6 +3969,7 @@ void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
/**
* @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
*
+ * @param p_hwfn
* @param p_ptt - ptt window used for writing the registers.
* @param vxlan_enable - vxlan enable flag.
*/
@@ -3787,6 +3979,7 @@ void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
/**
* @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
*
+ * @param p_hwfn
* @param p_ptt - ptt window used for writing the registers.
* @param eth_gre_enable - eth GRE enable enable flag.
* @param ip_gre_enable - IP GRE enable enable flag.
@@ -3798,6 +3991,7 @@ void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
/**
* @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
*
+ * @param p_hwfn
* @param p_ptt - ptt window used for writing the registers.
* @param dest_port - geneve destination udp port.
*/
@@ -3814,612 +4008,921 @@ void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
bool eth_geneve_enable, bool ip_geneve_enable);
-void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt, u16 pf_id);
-void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
- u16 pf_id, bool tcp, bool udp,
- bool ipv4, bool ipv6);
-
-#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
-#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
-#define TSTORM_PORT_STAT_OFFSET(port_id) \
+
+/**
+ * @brief qed_gft_disable - Disable GFT
+ *
+ * @param p_hwfn
+ * @param p_ptt - ptt window used for writing the registers.
+ * @param pf_id - pf on which to disable GFT.
+ */
+void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
+
+/**
+ * @brief qed_gft_config - Enable and configure HW for GFT
+ *
+ * @param p_hwfn
+ * @param p_ptt - ptt window used for writing the registers.
+ * @param pf_id - pf on which to enable GFT.
+ * @param tcp - set profile tcp packets.
+ * @param udp - set profile udp packet.
+ * @param ipv4 - set profile ipv4 packet.
+ * @param ipv6 - set profile ipv6 packet.
+ * @param profile_type - define packet same fields. Use enum gft_profile_type.
+ */
+void qed_gft_config(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ u16 pf_id,
+ bool tcp,
+ bool udp,
+ bool ipv4, bool ipv6, enum gft_profile_type profile_type);
+
+/**
+ * @brief qed_enable_context_validation - Enable and configure context
+ * validation.
+ *
+ * @param p_hwfn
+ * @param p_ptt - ptt window used for writing the registers.
+ */
+void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt);
+
+/**
+ * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
+ * session context.
+ *
+ * @param p_ctx_mem - pointer to context memory.
+ * @param ctx_size - context size.
+ * @param ctx_type - context type.
+ * @param cid - context cid.
+ */
+void qed_calc_session_ctx_validation(void *p_ctx_mem,
+ u16 ctx_size, u8 ctx_type, u32 cid);
+
+/**
+ * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
+ * context.
+ *
+ * @param p_ctx_mem - pointer to context memory.
+ * @param ctx_size - context size.
+ * @param ctx_type - context type.
+ * @param tid - context tid.
+ */
+void qed_calc_task_ctx_validation(void *p_ctx_mem,
+ u16 ctx_size, u8 ctx_type, u32 tid);
+
+/**
+ * @brief qed_memset_session_ctx - Memset session context to 0 while
+ * preserving validation bytes.
+ *
+ * @param p_hwfn -
+ * @param p_ctx_mem - pointer to context memory.
+ * @param ctx_size - size to initialzie.
+ * @param ctx_type - context type.
+ */
+void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
+
+/**
+ * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
+ * validation bytes.
+ *
+ * @param p_ctx_mem - pointer to context memory.
+ * @param ctx_size - size to initialzie.
+ * @param ctx_type - context type.
+ */
+void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
+
+/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
+#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
+#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
+
+/* Tstorm port statistics */
+#define TSTORM_PORT_STAT_OFFSET(port_id) \
(IRO[1].base + ((port_id) * IRO[1].m1))
-#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
+#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
+
+/* Tstorm ll2 port statistics */
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
(IRO[2].base + ((port_id) * IRO[2].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
-#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
+
+/* Ustorm VF-PF Channel ready flag */
+#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
(IRO[3].base + ((vf_id) * IRO[3].m1))
-#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
-#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
- (IRO[4].base + (pf_id) * IRO[4].m1)
-#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
-#define USTORM_EQE_CONS_OFFSET(pf_id) \
+#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
+
+/* Ustorm Final flr cleanup ack */
+#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
+ (IRO[4].base + ((pf_id) * IRO[4].m1))
+#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
+
+/* Ustorm Event ring consumer */
+#define USTORM_EQE_CONS_OFFSET(pf_id) \
(IRO[5].base + ((pf_id) * IRO[5].m1))
-#define USTORM_EQE_CONS_SIZE (IRO[5].size)
-#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
+#define USTORM_EQE_CONS_SIZE (IRO[5].size)
+
+/* Ustorm eth queue zone */
+#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
(IRO[6].base + ((queue_zone_id) * IRO[6].m1))
-#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
-#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
+#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
+
+/* Ustorm Common Queue ring consumer */
+#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
-#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
+#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
+
+/* Xstorm Integration Test Data */
+#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
+#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
+
+/* Ystorm Integration Test Data */
+#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
+#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
+
+/* Pstorm Integration Test Data */
+#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
+#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
+
+/* Tstorm Integration Test Data */
+#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
+#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
+
+/* Mstorm Integration Test Data */
+#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
+#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
+
+/* Ustorm Integration Test Data */
+#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
+#define USTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
+
+/* Tstorm producers */
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
- (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
+ (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
+
+/* Tstorm LightL2 queue statistics */
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
+
+/* Ustorm LiteL2 queue statistics */
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
- (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
+ (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
+
+/* Pstorm LiteL2 queue statistics */
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
- (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
-#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
-#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
+ (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
+#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size)
+
+/* Mstorm queue statistics */
+#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[18].base + ((stat_counter_id) * IRO[18].m1))
-#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
-#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
+#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
+
+/* Mstorm ETH PF queues producers */
+#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
(IRO[19].base + ((queue_id) * IRO[19].m1))
-#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
+#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
+
+/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
+ * mode.
+ */
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
- (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
+ (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
-#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
-#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
-#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
+
+/* TPA agregation timeout in us resolution (on ASIC) */
+#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
+#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
+
+/* Mstorm pf statistics */
+#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[22].base + ((pf_id) * IRO[22].m1))
-#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
-#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
+#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
+
+/* Ustorm queue statistics */
+#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[23].base + ((stat_counter_id) * IRO[23].m1))
-#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
-#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
+#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
+
+/* Ustorm pf statistics */
+#define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
(IRO[24].base + ((pf_id) * IRO[24].m1))
-#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
-#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
+#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
+
+/* Pstorm queue statistics */
+#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[25].base + ((stat_counter_id) * IRO[25].m1))
-#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
-#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
+#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
+
+/* Pstorm pf statistics */
+#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[26].base + ((pf_id) * IRO[26].m1))
-#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
-#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
- (IRO[27].base + ((ethtype) * IRO[27].m1))
-#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
-#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
-#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
-#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
+#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
+
+/* Control frame's EthType configuration for TX control frame security */
+#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
+ (IRO[27].base + ((eth_type_id) * IRO[27].m1))
+#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
+
+/* Tstorm last parser message */
+#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
+#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
+
+/* Tstorm Eth limit Rx rate */
+#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
(IRO[29].base + ((pf_id) * IRO[29].m1))
-#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
-#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
+#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
+
+/* Xstorm queue zone */
+#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
(IRO[30].base + ((queue_id) * IRO[30].m1))
-#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
+#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
+
+/* Ystorm cqe producer */
+#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
+ (IRO[31].base + ((rss_id) * IRO[31].m1))
+#define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size)
+
+/* Ustorm cqe producer */
+#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
+ (IRO[32].base + ((rss_id) * IRO[32].m1))
+#define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size)
+
+/* Ustorm grq producer */
+#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
+ (IRO[33].base + ((pf_id) * IRO[33].m1))
+#define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size)
+
+/* Tstorm cmdq-cons of given command queue-id */
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
- (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
-#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
+ (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
+#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
+
+/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
+ * BDqueue-id.
+ */
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
- (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
-#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
+ (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
+#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
+
+/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
- (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
-#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
+ (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
+#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
+
+/* Tstorm iSCSI RX stats */
#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
- (IRO[37].base + ((pf_id) * IRO[37].m1))
-#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
+ (IRO[37].base + ((pf_id) * IRO[37].m1))
+#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
+
+/* Mstorm iSCSI RX stats */
#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
- (IRO[38].base + ((pf_id) * IRO[38].m1))
-#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
+ (IRO[38].base + ((pf_id) * IRO[38].m1))
+#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
+
+/* Ustorm iSCSI RX stats */
#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
- (IRO[39].base + ((pf_id) * IRO[39].m1))
-#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
+ (IRO[39].base + ((pf_id) * IRO[39].m1))
+#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
+
+/* Xstorm iSCSI TX stats */
#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
- (IRO[40].base + ((pf_id) * IRO[40].m1))
-#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
+ (IRO[40].base + ((pf_id) * IRO[40].m1))
+#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
+
+/* Ystorm iSCSI TX stats */
#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
- (IRO[41].base + ((pf_id) * IRO[41].m1))
-#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
+ (IRO[41].base + ((pf_id) * IRO[41].m1))
+#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
+
+/* Pstorm iSCSI TX stats */
#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
- (IRO[42].base + ((pf_id) * IRO[42].m1))
-#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
-#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
- (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
-#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
-#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
- (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
-#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
+ (IRO[42].base + ((pf_id) * IRO[42].m1))
+#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
+
+/* Tstorm FCoE RX stats */
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
- (IRO[43].base + ((pf_id) * IRO[43].m1))
+ (IRO[43].base + ((pf_id) * IRO[43].m1))
+#define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size)
+
+/* Pstorm FCoE TX stats */
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
(IRO[44].base + ((pf_id) * IRO[44].m1))
+#define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size)
+
+/* Pstorm RDMA queue statistics */
+#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
+ (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
+#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
-static const struct iro iro_arr[49] = {
+/* Tstorm RDMA queue statistics */
+#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
+ (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
+#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
+
+/* Xstorm iWARP rxmit stats */
+#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
+ (IRO[47].base + ((pf_id) * IRO[47].m1))
+#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[47].size)
+
+/* Tstorm RoCE Event Statistics */
+#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
+ (IRO[48].base + ((roce_pf_id) * IRO[48].m1))
+#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[48].size)
+
+/* DCQCN Received Statistics */
+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
+ (IRO[49].base + ((roce_pf_id) * IRO[49].m1))
+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[49].size)
+
+/* DCQCN Sent Statistics */
+#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
+ (IRO[50].base + ((roce_pf_id) * IRO[50].m1))
+#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[50].size)
+
+static const struct iro iro_arr[51] = {
{0x0, 0x0, 0x0, 0x0, 0x8},
- {0x4cb0, 0x80, 0x0, 0x0, 0x80},
- {0x6518, 0x20, 0x0, 0x0, 0x20},
+ {0x4cb8, 0x88, 0x0, 0x0, 0x88},
+ {0x6530, 0x20, 0x0, 0x0, 0x20},
{0xb00, 0x8, 0x0, 0x0, 0x4},
{0xa80, 0x8, 0x0, 0x0, 0x4},
{0x0, 0x8, 0x0, 0x0, 0x2},
{0x80, 0x8, 0x0, 0x0, 0x4},
{0x84, 0x8, 0x0, 0x0, 0x2},
+ {0x4c48, 0x0, 0x0, 0x0, 0x78},
+ {0x3e18, 0x0, 0x0, 0x0, 0x78},
+ {0x2b58, 0x0, 0x0, 0x0, 0x78},
{0x4c40, 0x0, 0x0, 0x0, 0x78},
- {0x3df0, 0x0, 0x0, 0x0, 0x78},
- {0x29b0, 0x0, 0x0, 0x0, 0x78},
- {0x4c38, 0x0, 0x0, 0x0, 0x78},
- {0x4990, 0x0, 0x0, 0x0, 0x78},
- {0x7f48, 0x0, 0x0, 0x0, 0x78},
+ {0x4998, 0x0, 0x0, 0x0, 0x78},
+ {0x7f50, 0x0, 0x0, 0x0, 0x78},
{0xa28, 0x8, 0x0, 0x0, 0x8},
- {0x61f8, 0x10, 0x0, 0x0, 0x10},
- {0xbd20, 0x30, 0x0, 0x0, 0x30},
- {0x95b8, 0x30, 0x0, 0x0, 0x30},
- {0x4b60, 0x80, 0x0, 0x0, 0x40},
+ {0x6210, 0x10, 0x0, 0x0, 0x10},
+ {0xb820, 0x30, 0x0, 0x0, 0x30},
+ {0x96c0, 0x30, 0x0, 0x0, 0x30},
+ {0x4b68, 0x80, 0x0, 0x0, 0x40},
{0x1f8, 0x4, 0x0, 0x0, 0x4},
- {0x53a0, 0x80, 0x4, 0x0, 0x4},
- {0xc7c8, 0x0, 0x0, 0x0, 0x4},
- {0x4ba0, 0x80, 0x0, 0x0, 0x20},
- {0x8150, 0x40, 0x0, 0x0, 0x30},
- {0xec70, 0x60, 0x0, 0x0, 0x60},
- {0x2b48, 0x80, 0x0, 0x0, 0x38},
- {0xf1b0, 0x78, 0x0, 0x0, 0x78},
+ {0x53a8, 0x80, 0x4, 0x0, 0x4},
+ {0xc7d0, 0x0, 0x0, 0x0, 0x4},
+ {0x4ba8, 0x80, 0x0, 0x0, 0x20},
+ {0x8158, 0x40, 0x0, 0x0, 0x30},
+ {0xe770, 0x60, 0x0, 0x0, 0x60},
+ {0x2cf0, 0x80, 0x0, 0x0, 0x38},
+ {0xf2b8, 0x78, 0x0, 0x0, 0x78},
{0x1f8, 0x4, 0x0, 0x0, 0x4},
- {0xaef8, 0x0, 0x0, 0x0, 0xf0},
- {0xafe8, 0x8, 0x0, 0x0, 0x8},
+ {0xaf20, 0x0, 0x0, 0x0, 0xf0},
+ {0xb010, 0x8, 0x0, 0x0, 0x8},
{0x1f8, 0x8, 0x0, 0x0, 0x8},
{0xac0, 0x8, 0x0, 0x0, 0x8},
{0x2578, 0x8, 0x0, 0x0, 0x8},
{0x24f8, 0x8, 0x0, 0x0, 0x8},
{0x0, 0x8, 0x0, 0x0, 0x8},
- {0x200, 0x10, 0x8, 0x0, 0x8},
- {0xb78, 0x10, 0x8, 0x0, 0x2},
- {0xd9a8, 0x38, 0x0, 0x0, 0x24},
- {0x12988, 0x10, 0x0, 0x0, 0x8},
- {0x11fa0, 0x38, 0x0, 0x0, 0x18},
- {0xa580, 0x38, 0x0, 0x0, 0x10},
- {0x86f8, 0x30, 0x0, 0x0, 0x18},
- {0x101f8, 0x10, 0x0, 0x0, 0x10},
- {0xde28, 0x48, 0x0, 0x0, 0x38},
- {0x10660, 0x20, 0x0, 0x0, 0x20},
- {0x2b80, 0x80, 0x0, 0x0, 0x10},
- {0x5020, 0x10, 0x0, 0x0, 0x10},
- {0xc9b0, 0x30, 0x0, 0x0, 0x10},
- {0xeec0, 0x10, 0x0, 0x0, 0x10},
+ {0x400, 0x18, 0x8, 0x0, 0x8},
+ {0xb78, 0x18, 0x8, 0x0, 0x2},
+ {0xd898, 0x50, 0x0, 0x0, 0x3c},
+ {0x12908, 0x18, 0x0, 0x0, 0x10},
+ {0x11aa8, 0x40, 0x0, 0x0, 0x18},
+ {0xa588, 0x50, 0x0, 0x0, 0x20},
+ {0x8700, 0x40, 0x0, 0x0, 0x28},
+ {0x10300, 0x18, 0x0, 0x0, 0x10},
+ {0xde48, 0x48, 0x0, 0x0, 0x38},
+ {0x10768, 0x20, 0x0, 0x0, 0x20},
+ {0x2d28, 0x80, 0x0, 0x0, 0x10},
+ {0x5048, 0x10, 0x0, 0x0, 0x10},
+ {0xc9b8, 0x30, 0x0, 0x0, 0x10},
+ {0xeee0, 0x10, 0x0, 0x0, 0x10},
+ {0xa3a0, 0x10, 0x0, 0x0, 0x10},
+ {0x13108, 0x8, 0x0, 0x0, 0x8},
};
/* Runtime array offsets */
-#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
-#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
-#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
-#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
-#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
-#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
-#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
-#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
-#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
-#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
-#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
-#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
-#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
-#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
-#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
-#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
-#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
-#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
-#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
-#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
-#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
-#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
-#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
-#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
-#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
-#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
-#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
-#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
-#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
-#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
-#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
-#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
-#define CAU_REG_PI_MEMORY_RT_SIZE 4416
-#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
-#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
-#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
-#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
-#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
-#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
-#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
-#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
-#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
-#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
-#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
-#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
-#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
-#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
-#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
-#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
-#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
-#define SRC_REG_FIRSTFREE_RT_SIZE 2
-#define SRC_REG_LASTFREE_RT_OFFSET 6667
-#define SRC_REG_LASTFREE_RT_SIZE 2
-#define SRC_REG_COUNTFREE_RT_OFFSET 6669
-#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
-#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
-#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
-#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
-#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
-#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
-#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
-#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
-#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
-#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
-#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
-#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
-#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
-#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
-#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
-#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
-#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
-#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
-#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
-#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
-#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
-#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
-#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
-#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
-#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
-#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
-#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
-#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
-#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
-#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
-#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700
-#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701
-#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702
-#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
-#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702
-#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703
-#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704
-#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
-#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
-#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
-#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
-#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
-#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
-#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
-#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
-#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
-#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
-#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
-#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
-#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
-#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738
-#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739
-#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740
-#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741
-#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742
-#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743
-#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744
-#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745
-#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746
-#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747
-#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748
-#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749
-#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750
-#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751
-#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752
-#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753
-#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754
-#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755
-#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756
-#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757
-#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758
-#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759
-#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760
-#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761
-#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762
-#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763
-#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764
-#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765
-#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766
-#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767
-#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768
-#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769
-#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770
-#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771
-#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772
-#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773
-#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774
-#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775
-#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776
-#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777
-#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778
-#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779
-#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780
-#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781
-#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782
-#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783
-#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784
-#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785
-#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786
-#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787
-#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788
-#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789
-#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790
-#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791
-#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792
-#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793
-#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794
-#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795
-#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796
-#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797
-#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798
-#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799
-#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800
-#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801
-#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802
-#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803
-#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804
-#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805
-#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
-#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933
-#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934
-#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935
-#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936
-#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937
-#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938
-#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939
-#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940
-#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941
-#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942
-#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943
-#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944
-#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945
-#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946
-#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947
-#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948
-#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949
-#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950
-#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951
-#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952
-#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953
-#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954
-#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955
-#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956
-#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957
-#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958
-#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959
-#define QM_REG_PQTX2PF_0_RT_OFFSET 29960
-#define QM_REG_PQTX2PF_1_RT_OFFSET 29961
-#define QM_REG_PQTX2PF_2_RT_OFFSET 29962
-#define QM_REG_PQTX2PF_3_RT_OFFSET 29963
-#define QM_REG_PQTX2PF_4_RT_OFFSET 29964
-#define QM_REG_PQTX2PF_5_RT_OFFSET 29965
-#define QM_REG_PQTX2PF_6_RT_OFFSET 29966
-#define QM_REG_PQTX2PF_7_RT_OFFSET 29967
-#define QM_REG_PQTX2PF_8_RT_OFFSET 29968
-#define QM_REG_PQTX2PF_9_RT_OFFSET 29969
-#define QM_REG_PQTX2PF_10_RT_OFFSET 29970
-#define QM_REG_PQTX2PF_11_RT_OFFSET 29971
-#define QM_REG_PQTX2PF_12_RT_OFFSET 29972
-#define QM_REG_PQTX2PF_13_RT_OFFSET 29973
-#define QM_REG_PQTX2PF_14_RT_OFFSET 29974
-#define QM_REG_PQTX2PF_15_RT_OFFSET 29975
-#define QM_REG_PQTX2PF_16_RT_OFFSET 29976
-#define QM_REG_PQTX2PF_17_RT_OFFSET 29977
-#define QM_REG_PQTX2PF_18_RT_OFFSET 29978
-#define QM_REG_PQTX2PF_19_RT_OFFSET 29979
-#define QM_REG_PQTX2PF_20_RT_OFFSET 29980
-#define QM_REG_PQTX2PF_21_RT_OFFSET 29981
-#define QM_REG_PQTX2PF_22_RT_OFFSET 29982
-#define QM_REG_PQTX2PF_23_RT_OFFSET 29983
-#define QM_REG_PQTX2PF_24_RT_OFFSET 29984
-#define QM_REG_PQTX2PF_25_RT_OFFSET 29985
-#define QM_REG_PQTX2PF_26_RT_OFFSET 29986
-#define QM_REG_PQTX2PF_27_RT_OFFSET 29987
-#define QM_REG_PQTX2PF_28_RT_OFFSET 29988
-#define QM_REG_PQTX2PF_29_RT_OFFSET 29989
-#define QM_REG_PQTX2PF_30_RT_OFFSET 29990
-#define QM_REG_PQTX2PF_31_RT_OFFSET 29991
-#define QM_REG_PQTX2PF_32_RT_OFFSET 29992
-#define QM_REG_PQTX2PF_33_RT_OFFSET 29993
-#define QM_REG_PQTX2PF_34_RT_OFFSET 29994
-#define QM_REG_PQTX2PF_35_RT_OFFSET 29995
-#define QM_REG_PQTX2PF_36_RT_OFFSET 29996
-#define QM_REG_PQTX2PF_37_RT_OFFSET 29997
-#define QM_REG_PQTX2PF_38_RT_OFFSET 29998
-#define QM_REG_PQTX2PF_39_RT_OFFSET 29999
-#define QM_REG_PQTX2PF_40_RT_OFFSET 30000
-#define QM_REG_PQTX2PF_41_RT_OFFSET 30001
-#define QM_REG_PQTX2PF_42_RT_OFFSET 30002
-#define QM_REG_PQTX2PF_43_RT_OFFSET 30003
-#define QM_REG_PQTX2PF_44_RT_OFFSET 30004
-#define QM_REG_PQTX2PF_45_RT_OFFSET 30005
-#define QM_REG_PQTX2PF_46_RT_OFFSET 30006
-#define QM_REG_PQTX2PF_47_RT_OFFSET 30007
-#define QM_REG_PQTX2PF_48_RT_OFFSET 30008
-#define QM_REG_PQTX2PF_49_RT_OFFSET 30009
-#define QM_REG_PQTX2PF_50_RT_OFFSET 30010
-#define QM_REG_PQTX2PF_51_RT_OFFSET 30011
-#define QM_REG_PQTX2PF_52_RT_OFFSET 30012
-#define QM_REG_PQTX2PF_53_RT_OFFSET 30013
-#define QM_REG_PQTX2PF_54_RT_OFFSET 30014
-#define QM_REG_PQTX2PF_55_RT_OFFSET 30015
-#define QM_REG_PQTX2PF_56_RT_OFFSET 30016
-#define QM_REG_PQTX2PF_57_RT_OFFSET 30017
-#define QM_REG_PQTX2PF_58_RT_OFFSET 30018
-#define QM_REG_PQTX2PF_59_RT_OFFSET 30019
-#define QM_REG_PQTX2PF_60_RT_OFFSET 30020
-#define QM_REG_PQTX2PF_61_RT_OFFSET 30021
-#define QM_REG_PQTX2PF_62_RT_OFFSET 30022
-#define QM_REG_PQTX2PF_63_RT_OFFSET 30023
-#define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024
-#define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025
-#define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026
-#define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027
-#define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028
-#define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029
-#define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030
-#define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031
-#define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032
-#define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033
-#define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034
-#define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035
-#define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036
-#define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037
-#define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038
-#define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039
-#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040
-#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041
-#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042
-#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043
-#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044
-#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045
-#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046
-#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047
-#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048
-#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049
-#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050
-#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051
-#define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052
-#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
-#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308
-#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
-#define QM_REG_RLGLBLCRD_RT_OFFSET 30564
-#define QM_REG_RLGLBLCRD_RT_SIZE 256
-#define QM_REG_RLGLBLENABLE_RT_OFFSET 30820
-#define QM_REG_RLPFPERIOD_RT_OFFSET 30821
-#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822
-#define QM_REG_RLPFINCVAL_RT_OFFSET 30823
-#define QM_REG_RLPFINCVAL_RT_SIZE 16
-#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839
-#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
-#define QM_REG_RLPFCRD_RT_OFFSET 30855
-#define QM_REG_RLPFCRD_RT_SIZE 16
-#define QM_REG_RLPFENABLE_RT_OFFSET 30871
-#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872
-#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873
-#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
-#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889
-#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
-#define QM_REG_WFQPFCRD_RT_OFFSET 30905
-#define QM_REG_WFQPFCRD_RT_SIZE 256
-#define QM_REG_WFQPFENABLE_RT_OFFSET 31161
-#define QM_REG_WFQVPENABLE_RT_OFFSET 31162
-#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163
-#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
-#define QM_REG_TXPQMAP_RT_OFFSET 31675
-#define QM_REG_TXPQMAP_RT_SIZE 512
-#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187
-#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
-#define QM_REG_WFQVPCRD_RT_OFFSET 32699
-#define QM_REG_WFQVPCRD_RT_SIZE 512
-#define QM_REG_WFQVPMAP_RT_OFFSET 33211
-#define QM_REG_WFQVPMAP_RT_SIZE 512
-#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723
-#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
-#define QM_REG_VOQCRDLINE_RT_OFFSET 34043
-#define QM_REG_VOQCRDLINE_RT_SIZE 36
-#define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079
-#define QM_REG_VOQINITCRDLINE_RT_SIZE 36
-#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115
-#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116
-#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117
-#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118
-#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119
-#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120
-#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121
-#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122
-#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
-#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126
-#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
-#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130
-#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
-#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134
-#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135
-#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
-#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167
-#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
-#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183
-#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
-#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199
-#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215
-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
-#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231
-#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232
-#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233
-#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234
-#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235
-#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236
-#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237
-#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238
-#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239
-#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240
-#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241
-#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242
-#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243
-#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244
-#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245
-#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246
-#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248
-#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251
-#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254
-#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257
-#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260
-#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263
-#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266
-#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269
-#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272
-#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275
-#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278
-#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281
-#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284
-#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287
-#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290
-#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293
-#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296
-#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299
-#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302
-#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304
-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305
-#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306
-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307
-#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308
-
-#define RUNTIME_ARRAY_SIZE 34309
+#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
+#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
+#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
+#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
+#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
+#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
+#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
+#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
+#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
+#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
+#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
+#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
+#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
+#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
+#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
+#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
+#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
+#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
+#define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18
+#define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19
+#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20
+#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21
+#define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22
+#define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23
+#define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24
+#define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25
+#define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26
+#define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27
+#define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28
+#define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32
+#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36
+#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37
+#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38
+#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39
+#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40
+#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41
+#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42
+#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43
+#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44
+#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45
+#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024
+#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069
+#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024
+#define CAU_REG_PI_MEMORY_RT_OFFSET 2093
+#define CAU_REG_PI_MEMORY_RT_SIZE 4416
+#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509
+#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510
+#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511
+#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512
+#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513
+#define PRS_REG_SEARCH_TCP_RT_OFFSET 6514
+#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515
+#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516
+#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517
+#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518
+#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519
+#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520
+#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521
+#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522
+#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523
+#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524
+#define SRC_REG_FIRSTFREE_RT_OFFSET 6525
+#define SRC_REG_FIRSTFREE_RT_SIZE 2
+#define SRC_REG_LASTFREE_RT_OFFSET 6527
+#define SRC_REG_LASTFREE_RT_SIZE 2
+#define SRC_REG_COUNTFREE_RT_OFFSET 6529
+#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530
+#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531
+#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532
+#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533
+#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534
+#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535
+#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536
+#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537
+#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538
+#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539
+#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540
+#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541
+#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542
+#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543
+#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544
+#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545
+#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546
+#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547
+#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548
+#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549
+#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550
+#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551
+#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552
+#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553
+#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554
+#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555
+#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556
+#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557
+#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558
+#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559
+#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560
+#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561
+#define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562
+#define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563
+#define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564
+#define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565
+#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566
+#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414
+#define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980
+#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981
+#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982
+#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983
+#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984
+#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985
+#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986
+#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987
+#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988
+#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989
+#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990
+#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991
+#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992
+#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
+#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408
+#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
+#define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016
+#define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017
+#define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018
+#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019
+#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020
+#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021
+#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022
+#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023
+#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024
+#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025
+#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026
+#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027
+#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028
+#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029
+#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030
+#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031
+#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032
+#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033
+#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034
+#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035
+#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036
+#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037
+#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038
+#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039
+#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040
+#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041
+#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042
+#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043
+#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044
+#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045
+#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046
+#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047
+#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048
+#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049
+#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050
+#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051
+#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052
+#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053
+#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054
+#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055
+#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056
+#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057
+#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058
+#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059
+#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060
+#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061
+#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062
+#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063
+#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064
+#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065
+#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066
+#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067
+#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068
+#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069
+#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070
+#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071
+#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072
+#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073
+#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074
+#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075
+#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076
+#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077
+#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078
+#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079
+#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080
+#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081
+#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082
+#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083
+#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
+#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211
+#define QM_REG_PTRTBLOTHER_RT_SIZE 256
+#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467
+#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468
+#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469
+#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470
+#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471
+#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472
+#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473
+#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474
+#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475
+#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476
+#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477
+#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478
+#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479
+#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480
+#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481
+#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482
+#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483
+#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484
+#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485
+#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486
+#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487
+#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488
+#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489
+#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490
+#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491
+#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492
+#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493
+#define QM_REG_PQTX2PF_0_RT_OFFSET 34494
+#define QM_REG_PQTX2PF_1_RT_OFFSET 34495
+#define QM_REG_PQTX2PF_2_RT_OFFSET 34496
+#define QM_REG_PQTX2PF_3_RT_OFFSET 34497
+#define QM_REG_PQTX2PF_4_RT_OFFSET 34498
+#define QM_REG_PQTX2PF_5_RT_OFFSET 34499
+#define QM_REG_PQTX2PF_6_RT_OFFSET 34500
+#define QM_REG_PQTX2PF_7_RT_OFFSET 34501
+#define QM_REG_PQTX2PF_8_RT_OFFSET 34502
+#define QM_REG_PQTX2PF_9_RT_OFFSET 34503
+#define QM_REG_PQTX2PF_10_RT_OFFSET 34504
+#define QM_REG_PQTX2PF_11_RT_OFFSET 34505
+#define QM_REG_PQTX2PF_12_RT_OFFSET 34506
+#define QM_REG_PQTX2PF_13_RT_OFFSET 34507
+#define QM_REG_PQTX2PF_14_RT_OFFSET 34508
+#define QM_REG_PQTX2PF_15_RT_OFFSET 34509
+#define QM_REG_PQTX2PF_16_RT_OFFSET 34510
+#define QM_REG_PQTX2PF_17_RT_OFFSET 34511
+#define QM_REG_PQTX2PF_18_RT_OFFSET 34512
+#define QM_REG_PQTX2PF_19_RT_OFFSET 34513
+#define QM_REG_PQTX2PF_20_RT_OFFSET 34514
+#define QM_REG_PQTX2PF_21_RT_OFFSET 34515
+#define QM_REG_PQTX2PF_22_RT_OFFSET 34516
+#define QM_REG_PQTX2PF_23_RT_OFFSET 34517
+#define QM_REG_PQTX2PF_24_RT_OFFSET 34518
+#define QM_REG_PQTX2PF_25_RT_OFFSET 34519
+#define QM_REG_PQTX2PF_26_RT_OFFSET 34520
+#define QM_REG_PQTX2PF_27_RT_OFFSET 34521
+#define QM_REG_PQTX2PF_28_RT_OFFSET 34522
+#define QM_REG_PQTX2PF_29_RT_OFFSET 34523
+#define QM_REG_PQTX2PF_30_RT_OFFSET 34524
+#define QM_REG_PQTX2PF_31_RT_OFFSET 34525
+#define QM_REG_PQTX2PF_32_RT_OFFSET 34526
+#define QM_REG_PQTX2PF_33_RT_OFFSET 34527
+#define QM_REG_PQTX2PF_34_RT_OFFSET 34528
+#define QM_REG_PQTX2PF_35_RT_OFFSET 34529
+#define QM_REG_PQTX2PF_36_RT_OFFSET 34530
+#define QM_REG_PQTX2PF_37_RT_OFFSET 34531
+#define QM_REG_PQTX2PF_38_RT_OFFSET 34532
+#define QM_REG_PQTX2PF_39_RT_OFFSET 34533
+#define QM_REG_PQTX2PF_40_RT_OFFSET 34534
+#define QM_REG_PQTX2PF_41_RT_OFFSET 34535
+#define QM_REG_PQTX2PF_42_RT_OFFSET 34536
+#define QM_REG_PQTX2PF_43_RT_OFFSET 34537
+#define QM_REG_PQTX2PF_44_RT_OFFSET 34538
+#define QM_REG_PQTX2PF_45_RT_OFFSET 34539
+#define QM_REG_PQTX2PF_46_RT_OFFSET 34540
+#define QM_REG_PQTX2PF_47_RT_OFFSET 34541
+#define QM_REG_PQTX2PF_48_RT_OFFSET 34542
+#define QM_REG_PQTX2PF_49_RT_OFFSET 34543
+#define QM_REG_PQTX2PF_50_RT_OFFSET 34544
+#define QM_REG_PQTX2PF_51_RT_OFFSET 34545
+#define QM_REG_PQTX2PF_52_RT_OFFSET 34546
+#define QM_REG_PQTX2PF_53_RT_OFFSET 34547
+#define QM_REG_PQTX2PF_54_RT_OFFSET 34548
+#define QM_REG_PQTX2PF_55_RT_OFFSET 34549
+#define QM_REG_PQTX2PF_56_RT_OFFSET 34550
+#define QM_REG_PQTX2PF_57_RT_OFFSET 34551
+#define QM_REG_PQTX2PF_58_RT_OFFSET 34552
+#define QM_REG_PQTX2PF_59_RT_OFFSET 34553
+#define QM_REG_PQTX2PF_60_RT_OFFSET 34554
+#define QM_REG_PQTX2PF_61_RT_OFFSET 34555
+#define QM_REG_PQTX2PF_62_RT_OFFSET 34556
+#define QM_REG_PQTX2PF_63_RT_OFFSET 34557
+#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558
+#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559
+#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560
+#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561
+#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562
+#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563
+#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564
+#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565
+#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566
+#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567
+#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568
+#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569
+#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570
+#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571
+#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572
+#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573
+#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574
+#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575
+#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576
+#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577
+#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578
+#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579
+#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580
+#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581
+#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582
+#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583
+#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584
+#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585
+#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586
+#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
+#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842
+#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
+#define QM_REG_RLGLBLCRD_RT_OFFSET 35098
+#define QM_REG_RLGLBLCRD_RT_SIZE 256
+#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354
+#define QM_REG_RLPFPERIOD_RT_OFFSET 35355
+#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356
+#define QM_REG_RLPFINCVAL_RT_OFFSET 35357
+#define QM_REG_RLPFINCVAL_RT_SIZE 16
+#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373
+#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
+#define QM_REG_RLPFCRD_RT_OFFSET 35389
+#define QM_REG_RLPFCRD_RT_SIZE 16
+#define QM_REG_RLPFENABLE_RT_OFFSET 35405
+#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406
+#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407
+#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
+#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423
+#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
+#define QM_REG_WFQPFCRD_RT_OFFSET 35439
+#define QM_REG_WFQPFCRD_RT_SIZE 256
+#define QM_REG_WFQPFENABLE_RT_OFFSET 35695
+#define QM_REG_WFQVPENABLE_RT_OFFSET 35696
+#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697
+#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
+#define QM_REG_TXPQMAP_RT_OFFSET 36209
+#define QM_REG_TXPQMAP_RT_SIZE 512
+#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721
+#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
+#define QM_REG_WFQVPCRD_RT_OFFSET 37233
+#define QM_REG_WFQVPCRD_RT_SIZE 512
+#define QM_REG_WFQVPMAP_RT_OFFSET 37745
+#define QM_REG_WFQVPMAP_RT_SIZE 512
+#define QM_REG_PTRTBLTX_RT_OFFSET 38257
+#define QM_REG_PTRTBLTX_RT_SIZE 1024
+#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281
+#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
+#define QM_REG_VOQCRDLINE_RT_OFFSET 39601
+#define QM_REG_VOQCRDLINE_RT_SIZE 36
+#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637
+#define QM_REG_VOQINITCRDLINE_RT_SIZE 36
+#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673
+#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674
+#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675
+#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676
+#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677
+#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678
+#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679
+#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680
+#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681
+#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
+#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685
+#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
+#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689
+#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
+#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721
+#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
+#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737
+#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753
+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769
+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
+#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785
+#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 39786
+#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39787
+#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39795
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40819
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41331
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41843
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42355
+#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512
+#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42867
+#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32
+#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42899
+#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42900
+#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42901
+#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42902
+#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42903
+#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42904
+#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42905
+#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42906
+#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42907
+#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42908
+#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42909
+#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42910
+#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42911
+#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42912
+#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42913
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42914
+#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42915
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42916
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42917
+#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42918
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42919
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42920
+#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42921
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42922
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42923
+#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42924
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42925
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42926
+#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42927
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42928
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42929
+#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42930
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42931
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42932
+#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42933
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42934
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42935
+#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42936
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42937
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42938
+#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42939
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42940
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42941
+#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42942
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42943
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42944
+#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42945
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42946
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42947
+#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42948
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42949
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42950
+#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42951
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42952
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42953
+#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42954
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42955
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42956
+#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42957
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42958
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42959
+#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42960
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42961
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42962
+#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42963
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42964
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42965
+#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42966
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42967
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42968
+#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42969
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42970
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42971
+#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42972
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42973
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42974
+#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42975
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42976
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42977
+#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42978
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42979
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42980
+#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42981
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42982
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42983
+#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42984
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42985
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42986
+#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42987
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42988
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42989
+#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42990
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42991
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42992
+#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42993
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42994
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42995
+#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42996
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42997
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42998
+#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42999
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 43000
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43001
+#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43002
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43003
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43004
+#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43005
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43006
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43007
+#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43008
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43009
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43010
+#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43011
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43012
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43013
+#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43014
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43015
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43016
+#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43017
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43018
+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43019
+#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43020
+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43021
+#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43022
+
+#define RUNTIME_ARRAY_SIZE 43023
+
+/* Init Callbacks */
+#define DMAE_READY_CB 0
/* The eth storm context for the Tstorm */
struct tstorm_eth_conn_st_ctx {
@@ -4436,219 +4939,219 @@ struct xstorm_eth_conn_st_ctx {
__le32 reserved[60];
};
-struct xstorm_eth_conn_ag_ctx {
+struct e4_xstorm_eth_conn_ag_ctx {
u8 reserved0;
- u8 eth_state;
+ u8 state;
u8 flags0;
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
-#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
+#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
+#define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -4681,7 +5184,7 @@ struct xstorm_eth_conn_ag_ctx {
u8 byte13;
u8 byte14;
u8 byte15;
- u8 ereserved;
+ u8 e5_reserved;
__le16 word11;
__le32 reg10;
__le32 reg11;
@@ -4704,37 +5207,37 @@ struct ystorm_eth_conn_st_ctx {
__le32 reserved[8];
};
-struct ystorm_eth_conn_ag_ctx {
+struct e4_ystorm_eth_conn_ag_ctx {
u8 byte0;
u8 state;
u8 flags0;
-#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
-#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
-#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 tx_q0_int_coallecing_timeset;
u8 byte3;
__le16 word0;
@@ -4748,89 +5251,89 @@ struct ystorm_eth_conn_ag_ctx {
__le32 reg3;
};
-struct tstorm_eth_conn_ag_ctx {
+struct e4_tstorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
u8 flags4;
-#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
-#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -4852,63 +5355,63 @@ struct tstorm_eth_conn_ag_ctx {
__le32 reg10;
};
-struct ustorm_eth_conn_ag_ctx {
+struct e4_ustorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
u8 flags2;
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
-#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -4932,20 +5435,21 @@ struct mstorm_eth_conn_st_ctx {
};
/* eth connection context */
-struct eth_conn_context {
+struct e4_eth_conn_context {
struct tstorm_eth_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct pstorm_eth_conn_st_ctx pstorm_st_context;
struct xstorm_eth_conn_st_ctx xstorm_st_context;
- struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
+ struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
struct ystorm_eth_conn_st_ctx ystorm_st_context;
- struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
- struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
- struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
+ struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
+ struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
+ struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
struct ustorm_eth_conn_st_ctx ustorm_st_context;
struct mstorm_eth_conn_st_ctx mstorm_st_context;
};
+/* Ethernet filter types: mac/vlan/pair */
enum eth_error_code {
ETH_OK = 0x00,
ETH_FILTERS_MAC_ADD_FAIL_FULL,
@@ -4972,6 +5476,7 @@ enum eth_error_code {
MAX_ETH_ERROR_CODE
};
+/* Opcodes for the event ring */
enum eth_event_opcode {
ETH_EVENT_UNUSED,
ETH_EVENT_VPORT_START,
@@ -4983,13 +5488,14 @@ enum eth_event_opcode {
ETH_EVENT_RX_QUEUE_UPDATE,
ETH_EVENT_RX_QUEUE_STOP,
ETH_EVENT_FILTERS_UPDATE,
- ETH_EVENT_RESERVED,
- ETH_EVENT_RESERVED2,
- ETH_EVENT_RESERVED3,
+ ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
+ ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
+ ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
ETH_EVENT_RX_ADD_UDP_FILTER,
ETH_EVENT_RX_DELETE_UDP_FILTER,
- ETH_EVENT_RESERVED4,
- ETH_EVENT_RESERVED5,
+ ETH_EVENT_RX_CREATE_GFT_ACTION,
+ ETH_EVENT_RX_GFT_UPDATE_FILTER,
+ ETH_EVENT_TX_QUEUE_UPDATE,
MAX_ETH_EVENT_OPCODE
};
@@ -5039,6 +5545,7 @@ enum eth_filter_type {
MAX_ETH_FILTER_TYPE
};
+/* Eth IPv4 Fragment Type */
enum eth_ipv4_frag_type {
ETH_IPV4_NOT_FRAG,
ETH_IPV4_FIRST_FRAG,
@@ -5046,12 +5553,14 @@ enum eth_ipv4_frag_type {
MAX_ETH_IPV4_FRAG_TYPE
};
+/* eth IPv4 Fragment Type */
enum eth_ip_type {
ETH_IPV4,
ETH_IPV6,
MAX_ETH_IP_TYPE
};
+/* Ethernet Ramrod Command IDs */
enum eth_ramrod_cmd_id {
ETH_RAMROD_UNUSED,
ETH_RAMROD_VPORT_START,
@@ -5070,10 +5579,11 @@ enum eth_ramrod_cmd_id {
ETH_RAMROD_RX_DELETE_UDP_FILTER,
ETH_RAMROD_RX_CREATE_GFT_ACTION,
ETH_RAMROD_GFT_UPDATE_FILTER,
+ ETH_RAMROD_TX_QUEUE_UPDATE,
MAX_ETH_RAMROD_CMD_ID
};
-/* return code from eth sp ramrods */
+/* Return code from eth sp ramrods */
struct eth_return_code {
u8 value;
#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
@@ -5209,18 +5719,14 @@ struct eth_vport_tx_mode {
__le16 reserved2[3];
};
+/* GFT filter update action type */
enum gft_filter_update_action {
GFT_ADD_FILTER,
GFT_DELETE_FILTER,
MAX_GFT_FILTER_UPDATE_ACTION
};
-enum gft_logic_filter_type {
- GFT_FILTER_TYPE,
- RFS_FILTER_TYPE,
- MAX_GFT_LOGIC_FILTER_TYPE
-};
-
+/* Ramrod data for rx add openflow filter */
struct rx_add_openflow_filter_data {
__le16 action_icid;
u8 priority;
@@ -5244,11 +5750,13 @@ struct rx_add_openflow_filter_data {
__le16 l4_src_port;
};
+/* Ramrod data for rx create gft action */
struct rx_create_gft_action_data {
u8 vport_id;
u8 reserved[7];
};
+/* Ramrod data for rx create openflow action */
struct rx_create_openflow_action_data {
u8 vport_id;
u8 reserved[7];
@@ -5286,7 +5794,7 @@ struct rx_queue_start_ramrod_data {
struct regpair reserved2;
};
-/* Ramrod data for rx queue start ramrod */
+/* Ramrod data for rx queue stop ramrod */
struct rx_queue_stop_ramrod_data {
__le16 rx_queue_id;
u8 complete_cqe_flg;
@@ -5324,14 +5832,22 @@ struct rx_udp_filter_data {
__le32 tenant_id;
};
+/* Add or delete GFT filter - filter is packet header of type of packet wished
+ * to pass certain FW flow.
+ */
struct rx_update_gft_filter_data {
struct regpair pkt_hdr_addr;
__le16 pkt_hdr_length;
- __le16 rx_qid_or_action_icid;
- u8 vport_id;
- u8 filter_type;
+ __le16 action_icid;
+ __le16 rx_qid;
+ __le16 flow_id;
+ __le16 vport_id;
+ u8 action_icid_valid;
+ u8 rx_qid_valid;
+ u8 flow_id_valid;
u8 filter_action;
u8 assert_on_error;
+ u8 reserved;
};
/* Ramrod data for rx queue start ramrod */
@@ -5377,6 +5893,14 @@ struct tx_queue_stop_ramrod_data {
__le16 reserved[4];
};
+/* Ramrod data for tx queue update ramrod */
+struct tx_queue_update_ramrod_data {
+ __le16 update_qm_pq_id_flg;
+ __le16 qm_pq_id;
+ __le32 reserved0;
+ struct regpair reserved1[5];
+};
+
/* Ramrod data for vport update ramrod */
struct vport_filter_update_ramrod_data {
struct eth_filter_cmd_header filter_cmd_hdr;
@@ -5477,219 +6001,219 @@ struct vport_update_ramrod_data {
struct eth_vport_rss_config rss_config;
};
-struct xstorm_eth_conn_agctxdq_ext_ldpart {
+struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
u8 reserved0;
- u8 eth_state;
+ u8 state;
u8 flags0;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
u8 flags3;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
u8 flags4;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
u8 flags5;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
u8 flags6;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
-#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
+#define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -5706,256 +6230,256 @@ struct xstorm_eth_conn_agctxdq_ext_ldpart {
__le32 reg4;
};
-struct mstorm_eth_conn_ag_ctx {
+struct e4_mstorm_eth_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct xstorm_eth_hw_conn_ag_ctx {
+struct e4_xstorm_eth_hw_conn_ag_ctx {
u8 reserved0;
- u8 eth_state;
+ u8 state;
u8 flags0;
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
u8 flags2;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
u8 flags7;
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
u8 flags10;
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
-#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
-#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
-#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
+#define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id;
__le16 physical_q0;
- __le16 ereserved1;
+ __le16 e5_reserved1;
__le16 edpm_num_bds;
__le16 tx_bd_cons;
__le16 tx_bd_prod;
@@ -5963,6 +6487,7 @@ struct xstorm_eth_hw_conn_ag_ctx {
__le16 conn_dpi;
};
+/* GFT CAM line struct */
struct gft_cam_line {
__le32 camline;
#define GFT_CAM_LINE_VALID_MASK 0x1
@@ -5975,6 +6500,7 @@ struct gft_cam_line {
#define GFT_CAM_LINE_RESERVED1_SHIFT 29
};
+/* GFT CAM line struct with fields breakout */
struct gft_cam_line_mapped {
__le32 camline;
#define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
@@ -6008,28 +6534,31 @@ struct gft_cam_line_mapped {
struct gft_cam_line_mapped cam_line_mapped;
};
+/* Used in gft_profile_key: Indication for ip version */
enum gft_profile_ip_version {
GFT_PROFILE_IPV4 = 0,
GFT_PROFILE_IPV6 = 1,
MAX_GFT_PROFILE_IP_VERSION
};
+/* Profile key stucr fot GFT logic in Prs */
struct gft_profile_key {
__le16 profile_key;
-#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
-#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
-#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
-#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
-#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
-#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
-#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
-#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
-#define GFT_PROFILE_KEY_PF_ID_MASK 0xF
-#define GFT_PROFILE_KEY_PF_ID_SHIFT 10
-#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
-#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
-};
-
+#define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
+#define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
+#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
+#define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
+#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
+#define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
+#define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
+#define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
+#define GFT_PROFILE_KEY_PF_ID_MASK 0xF
+#define GFT_PROFILE_KEY_PF_ID_SHIFT 10
+#define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
+#define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
+};
+
+/* Used in gft_profile_key: Indication for tunnel type */
enum gft_profile_tunnel_type {
GFT_PROFILE_NO_TUNNEL = 0,
GFT_PROFILE_VXLAN_TUNNEL = 1,
@@ -6040,6 +6569,7 @@ enum gft_profile_tunnel_type {
MAX_GFT_PROFILE_TUNNEL_TYPE
};
+/* Used in gft_profile_key: Indication for protocol type */
enum gft_profile_upper_protocol_type {
GFT_PROFILE_ROCE_PROTOCOL = 0,
GFT_PROFILE_RROCE_PROTOCOL = 1,
@@ -6060,6 +6590,7 @@ enum gft_profile_upper_protocol_type {
MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
};
+/* GFT RAM line struct */
struct gft_ram_line {
__le32 lo;
#define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
@@ -6149,6 +6680,7 @@ struct gft_ram_line {
#define GFT_RAM_LINE_RESERVED1_SHIFT 10
};
+/* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
enum gft_vlan_select {
INNER_PROVIDER_VLAN = 0,
INNER_VLAN = 1,
@@ -6157,10 +6689,205 @@ enum gft_vlan_select {
MAX_GFT_VLAN_SELECT
};
+/* The rdma task context of Mstorm */
+struct ystorm_rdma_task_st_ctx {
+ struct regpair temp[4];
+};
+
+struct e4_ystorm_rdma_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 msem_ctx_upd_seq;
+ u8 flags0;
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 key;
+ __le32 mw_cnt;
+ u8 ref_cnt_seq;
+ u8 ctx_upd_seq;
+ __le16 dif_flags;
+ __le16 tx_ref_count;
+ __le16 last_used_ltid;
+ __le16 parent_mr_lo;
+ __le16 parent_mr_hi;
+ __le32 fbo_lo;
+ __le32 fbo_hi;
+};
+
+struct e4_mstorm_rdma_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 icid;
+ u8 flags0;
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 key;
+ __le32 mw_cnt;
+ u8 ref_cnt_seq;
+ u8 ctx_upd_seq;
+ __le16 dif_flags;
+ __le16 tx_ref_count;
+ __le16 last_used_ltid;
+ __le16 parent_mr_lo;
+ __le16 parent_mr_hi;
+ __le32 fbo_lo;
+ __le32 fbo_hi;
+};
+
+/* The roce task context of Mstorm */
struct mstorm_rdma_task_st_ctx {
struct regpair temp[4];
};
+/* The roce task context of Ustorm */
+struct ustorm_rdma_task_st_ctx {
+ struct regpair temp[2];
+};
+
+struct e4_ustorm_rdma_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 icid;
+ u8 flags0;
+#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
+ u8 flags1;
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+ u8 flags2;
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
+ u8 flags3;
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+ __le32 dif_err_intervals;
+ __le32 dif_error_1st_interval;
+ __le32 reg2;
+ __le32 dif_runt_value;
+ __le32 reg4;
+ __le32 reg5;
+};
+
+/* RDMA task context */
+struct e4_rdma_task_context {
+ struct ystorm_rdma_task_st_ctx ystorm_st_context;
+ struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
+ struct tdif_task_context tdif_context;
+ struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
+ struct mstorm_rdma_task_st_ctx mstorm_st_context;
+ struct rdif_task_context rdif_context;
+ struct ustorm_rdma_task_st_ctx ustorm_st_context;
+ struct regpair ustorm_st_padding[2];
+ struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
+};
+
+/* rdma function init ramrod data */
struct rdma_close_func_ramrod_data {
u8 cnq_start_offset;
u8 num_cnqs;
@@ -6169,6 +6896,7 @@ struct rdma_close_func_ramrod_data {
u8 reserved[4];
};
+/* rdma function init CNQ parameters */
struct rdma_cnq_params {
__le16 sb_num;
u8 sb_index;
@@ -6179,6 +6907,7 @@ struct rdma_cnq_params {
u8 reserved1[6];
};
+/* rdma create cq ramrod data */
struct rdma_create_cq_ramrod_data {
struct regpair cq_handle;
struct regpair pbl_addr;
@@ -6193,21 +6922,25 @@ struct rdma_create_cq_ramrod_data {
__le16 reserved1;
};
+/* rdma deregister tid ramrod data */
struct rdma_deregister_tid_ramrod_data {
__le32 itid;
__le32 reserved;
};
+/* rdma destroy cq output params */
struct rdma_destroy_cq_output_params {
__le16 cnq_num;
__le16 reserved0;
__le32 reserved1;
};
+/* rdma destroy cq ramrod data */
struct rdma_destroy_cq_ramrod_data {
struct regpair output_params_addr;
};
+/* RDMA slow path EQ cmd IDs */
enum rdma_event_opcode {
RDMA_EVENT_UNUSED,
RDMA_EVENT_FUNC_INIT,
@@ -6223,6 +6956,7 @@ enum rdma_event_opcode {
MAX_RDMA_EVENT_OPCODE
};
+/* RDMA FW return code for slow path ramrods */
enum rdma_fw_return_code {
RDMA_RETURN_OK = 0,
RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
@@ -6232,20 +6966,24 @@ enum rdma_fw_return_code {
MAX_RDMA_FW_RETURN_CODE
};
+/* rdma function init header */
struct rdma_init_func_hdr {
u8 cnq_start_offset;
u8 num_cnqs;
u8 cq_ring_mode;
u8 vf_id;
u8 vf_valid;
- u8 reserved[3];
+ u8 relaxed_ordering;
+ u8 reserved[2];
};
+/* rdma function init ramrod data */
struct rdma_init_func_ramrod_data {
struct rdma_init_func_hdr params_header;
struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
};
+/* RDMA ramrod command IDs */
enum rdma_ramrod_cmd_id {
RDMA_RAMROD_UNUSED,
RDMA_RAMROD_FUNC_INIT,
@@ -6261,42 +6999,43 @@ enum rdma_ramrod_cmd_id {
MAX_RDMA_RAMROD_CMD_ID
};
+/* rdma register tid ramrod data */
struct rdma_register_tid_ramrod_data {
__le16 flags;
#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
-#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
-#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
-#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
-#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
+#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
+#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
+#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
-#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
-#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
+#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
+#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
-#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
-#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
+#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
+#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
u8 flags1;
#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
-#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
-#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
-#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
+#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
+#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
+#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
u8 flags2;
-#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
-#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
+#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
+#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
-#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
-#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
+#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
+#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
u8 key;
u8 length_hi;
u8 vf_id;
@@ -6313,19 +7052,21 @@ struct rdma_register_tid_ramrod_data {
__le32 reserved4[2];
};
+/* rdma resize cq output params */
struct rdma_resize_cq_output_params {
__le32 old_cq_cons;
__le32 old_cq_prod;
};
+/* rdma resize cq ramrod data */
struct rdma_resize_cq_ramrod_data {
u8 flags;
-#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
-#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
-#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
-#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
-#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
-#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
+#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
+#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
+#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
+#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
u8 pbl_log_page_size;
__le16 pbl_num_pages;
__le32 max_cqes;
@@ -6333,10 +7074,12 @@ struct rdma_resize_cq_ramrod_data {
struct regpair output_params_addr;
};
+/* The rdma storm context of Mstorm */
struct rdma_srq_context {
struct regpair temp[8];
};
+/* rdma create qp requester ramrod data */
struct rdma_srq_create_ramrod_data {
struct regpair pbl_base_addr;
__le16 pages_in_srq_pbl;
@@ -6348,206 +7091,19 @@ struct rdma_srq_create_ramrod_data {
struct regpair producers_addr;
};
+/* rdma create qp requester ramrod data */
struct rdma_srq_destroy_ramrod_data {
struct rdma_srq_id srq_id;
__le32 reserved;
};
+/* rdma create qp requester ramrod data */
struct rdma_srq_modify_ramrod_data {
struct rdma_srq_id srq_id;
__le32 wqe_limit;
};
-struct ystorm_rdma_task_st_ctx {
- struct regpair temp[4];
-};
-
-struct ystorm_rdma_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 msem_ctx_upd_seq;
- u8 flags0;
-#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 key;
- __le32 mw_cnt;
- u8 ref_cnt_seq;
- u8 ctx_upd_seq;
- __le16 dif_flags;
- __le16 tx_ref_count;
- __le16 last_used_ltid;
- __le16 parent_mr_lo;
- __le16 parent_mr_hi;
- __le32 fbo_lo;
- __le32 fbo_hi;
-};
-
-struct mstorm_rdma_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 icid;
- u8 flags0;
-#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 key;
- __le32 mw_cnt;
- u8 ref_cnt_seq;
- u8 ctx_upd_seq;
- __le16 dif_flags;
- __le16 tx_ref_count;
- __le16 last_used_ltid;
- __le16 parent_mr_lo;
- __le16 parent_mr_hi;
- __le32 fbo_lo;
- __le32 fbo_hi;
-};
-
-struct ustorm_rdma_task_st_ctx {
- struct regpair temp[2];
-};
-
-struct ustorm_rdma_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 icid;
- u8 flags0;
-#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
- u8 flags1;
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
- u8 flags2;
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
-#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
- u8 flags3;
-#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
- __le32 dif_err_intervals;
- __le32 dif_error_1st_interval;
- __le32 reg2;
- __le32 dif_runt_value;
- __le32 reg4;
- __le32 reg5;
-};
-
-struct rdma_task_context {
- struct ystorm_rdma_task_st_ctx ystorm_st_context;
- struct ystorm_rdma_task_ag_ctx ystorm_ag_context;
- struct tdif_task_context tdif_context;
- struct mstorm_rdma_task_ag_ctx mstorm_ag_context;
- struct mstorm_rdma_task_st_ctx mstorm_st_context;
- struct rdif_task_context rdif_context;
- struct ustorm_rdma_task_st_ctx ustorm_st_context;
- struct regpair ustorm_st_padding[2];
- struct ustorm_rdma_task_ag_ctx ustorm_ag_context;
-};
-
+/* RDMA Tid type enumeration (for register_tid ramrod) */
enum rdma_tid_type {
RDMA_TID_REGISTERED_MR,
RDMA_TID_FMR,
@@ -6556,214 +7112,214 @@ enum rdma_tid_type {
MAX_RDMA_TID_TYPE
};
-struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
+struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
u8 flags1;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
u8 flags3;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
u8 flags5;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
u8 flags6;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
u8 flags7;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
-#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
-#define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -6783,126 +7339,126 @@ struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
__le32 reg4;
};
-struct mstorm_rdma_conn_ag_ctx {
+struct e4_mstorm_rdma_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct tstorm_rdma_conn_ag_ctx {
+struct e4_tstorm_rdma_conn_ag_ctx {
u8 reserved0;
u8 byte1;
u8 flags0;
-#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -6924,73 +7480,73 @@ struct tstorm_rdma_conn_ag_ctx {
__le32 reg10;
};
-struct tstorm_rdma_task_ag_ctx {
+struct e4_tstorm_rdma_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
-#define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
-#define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
-#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
-#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
-#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
@@ -7003,63 +7559,63 @@ struct tstorm_rdma_task_ag_ctx {
__le32 reg2;
};
-struct ustorm_rdma_conn_ag_ctx {
+struct e4_ustorm_rdma_conn_ag_ctx {
u8 reserved;
u8 byte1;
u8 flags0;
-#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
-#define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
u8 flags3;
-#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
-#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 conn_dpi;
@@ -7072,214 +7628,214 @@ struct ustorm_rdma_conn_ag_ctx {
__le16 word3;
};
-struct xstorm_rdma_conn_ag_ctx {
+struct e4_xstorm_rdma_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
-#define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
-#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
-#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4
+#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -7301,37 +7857,37 @@ struct xstorm_rdma_conn_ag_ctx {
__le32 reg6;
};
-struct ystorm_rdma_conn_ag_ctx {
+struct e4_ystorm_rdma_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -7345,62 +7901,70 @@ struct ystorm_rdma_conn_ag_ctx {
__le32 reg3;
};
-struct mstorm_roce_conn_st_ctx {
- struct regpair temp[6];
+/* The roce storm context of Ystorm */
+struct ystorm_roce_conn_st_ctx {
+ struct regpair temp[2];
};
+/* The roce storm context of Mstorm */
struct pstorm_roce_conn_st_ctx {
struct regpair temp[16];
};
-struct ystorm_roce_conn_st_ctx {
- struct regpair temp[2];
-};
-
+/* The roce storm context of Xstorm */
struct xstorm_roce_conn_st_ctx {
struct regpair temp[24];
};
+/* The roce storm context of Tstorm */
struct tstorm_roce_conn_st_ctx {
struct regpair temp[30];
};
+/* The roce storm context of Mstorm */
+struct mstorm_roce_conn_st_ctx {
+ struct regpair temp[6];
+};
+
+/* The roce storm context of Ystorm */
struct ustorm_roce_conn_st_ctx {
struct regpair temp[12];
};
-struct roce_conn_context {
+/* roce connection context */
+struct e4_roce_conn_context {
struct ystorm_roce_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_roce_conn_st_ctx pstorm_st_context;
struct xstorm_roce_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_rdma_conn_ag_ctx xstorm_ag_context;
- struct tstorm_rdma_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
- struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
struct tstorm_roce_conn_st_ctx tstorm_st_context;
struct mstorm_roce_conn_st_ctx mstorm_st_context;
struct ustorm_roce_conn_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
};
+/* roce create qp requester ramrod data */
struct roce_create_qp_req_ramrod_data {
__le16 flags;
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
-#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
u8 max_ord;
u8 traffic_class;
u8 hop_limit;
@@ -7431,26 +7995,27 @@ struct roce_create_qp_req_ramrod_data {
__le16 dpi;
};
+/* roce create qp responder ramrod data */
struct roce_create_qp_resp_ramrod_data {
__le16 flags;
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
u8 max_ird;
u8 traffic_class;
u8 hop_limit;
@@ -7482,24 +8047,40 @@ struct roce_create_qp_resp_ramrod_data {
__le16 dpi;
};
+/* roce DCQCN received statistics */
+struct roce_dcqcn_received_stats {
+ struct regpair ecn_pkt_rcv;
+ struct regpair cnp_pkt_rcv;
+};
+
+/* roce DCQCN sent statistics */
+struct roce_dcqcn_sent_stats {
+ struct regpair cnp_pkt_sent;
+};
+
+/* RoCE destroy qp requester output params */
struct roce_destroy_qp_req_output_params {
__le32 num_bound_mw;
__le32 cq_prod;
};
+/* RoCE destroy qp requester ramrod data */
struct roce_destroy_qp_req_ramrod_data {
struct regpair output_params_addr;
};
+/* RoCE destroy qp responder output params */
struct roce_destroy_qp_resp_output_params {
__le32 num_invalidated_mw;
__le32 cq_prod;
};
+/* RoCE destroy qp responder ramrod data */
struct roce_destroy_qp_resp_ramrod_data {
struct regpair output_params_addr;
};
+/* roce special events statistics */
struct roce_events_stats {
__le16 silent_drops;
__le16 rnr_naks_sent;
@@ -7508,6 +8089,7 @@ struct roce_events_stats {
__le32 reserved;
};
+/* ROCE slow path EQ cmd IDs */
enum roce_event_opcode {
ROCE_EVENT_CREATE_QP = 11,
ROCE_EVENT_MODIFY_QP,
@@ -7518,6 +8100,7 @@ enum roce_event_opcode {
MAX_ROCE_EVENT_OPCODE
};
+/* roce func init ramrod data */
struct roce_init_func_params {
u8 ll2_queue_id;
u8 cnp_vlan_priority;
@@ -7526,42 +8109,46 @@ struct roce_init_func_params {
__le32 cnp_send_timeout;
};
+/* roce func init ramrod data */
struct roce_init_func_ramrod_data {
struct rdma_init_func_ramrod_data rdma;
struct roce_init_func_params roce;
};
+/* roce modify qp requester ramrod data */
struct roce_modify_qp_req_ramrod_data {
__le16 flags;
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14
u8 fields;
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
u8 max_ord;
u8 traffic_class;
u8 hop_limit;
@@ -7570,66 +8157,76 @@ struct roce_modify_qp_req_ramrod_data {
__le32 ack_timeout_val;
__le16 mtu;
__le16 reserved2;
- __le32 reserved3[3];
+ __le32 reserved3[2];
+ __le16 low_latency_phy_queue;
+ __le16 regular_latency_phy_queue;
__le32 src_gid[4];
__le32 dst_gid[4];
};
+/* roce modify qp responder ramrod data */
struct roce_modify_qp_resp_ramrod_data {
__le16 flags;
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11
u8 fields;
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
u8 max_ird;
u8 traffic_class;
u8 hop_limit;
__le16 p_key;
__le32 flow_label;
__le16 mtu;
- __le16 reserved2;
+ __le16 low_latency_phy_queue;
+ __le16 regular_latency_phy_queue;
+ u8 reserved2[6];
__le32 src_gid[4];
__le32 dst_gid[4];
};
+/* RoCE query qp requester output params */
struct roce_query_qp_req_output_params {
__le32 psn;
__le32 flags;
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
-#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
+#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
};
+/* RoCE query qp requester ramrod data */
struct roce_query_qp_req_ramrod_data {
struct regpair output_params_addr;
};
+/* RoCE query qp responder output params */
struct roce_query_qp_resp_output_params {
__le32 psn;
__le32 err_flag;
@@ -7639,10 +8236,12 @@ struct roce_query_qp_resp_output_params {
#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
};
+/* RoCE query qp responder ramrod data */
struct roce_query_qp_resp_ramrod_data {
struct regpair output_params_addr;
};
+/* ROCE ramrod command IDs */
enum roce_ramrod_cmd_id {
ROCE_RAMROD_CREATE_QP = 11,
ROCE_RAMROD_MODIFY_QP,
@@ -7653,163 +8252,163 @@ enum roce_ramrod_cmd_id {
MAX_ROCE_RAMROD_CMD_ID
};
-struct mstorm_roce_req_conn_ag_ctx {
+struct e4_mstorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct mstorm_roce_resp_conn_ag_ctx {
+struct e4_mstorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
-struct tstorm_roce_req_conn_ag_ctx {
+struct e4_tstorm_roce_req_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
u8 flags1;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
u8 flags3;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 snd_nxt_psn;
__le32 snd_max_psn;
@@ -7825,95 +8424,95 @@ struct tstorm_roce_req_conn_ag_ctx {
u8 byte4;
u8 byte5;
__le16 snd_sq_cons;
- __le16 word2;
+ __le16 conn_dpi;
__le16 word3;
__le32 reg9;
__le32 reg10;
};
-struct tstorm_roce_resp_conn_ag_ctx {
+struct e4_tstorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 state;
u8 flags0;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags2;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
u8 flags4;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 psn_and_rxmit_id_echo;
__le32 reg1;
__le32 reg2;
@@ -7935,63 +8534,63 @@ struct tstorm_roce_resp_conn_ag_ctx {
__le32 reg10;
};
-struct ustorm_roce_req_conn_ag_ctx {
+struct e4_ustorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8004,63 +8603,63 @@ struct ustorm_roce_req_conn_ag_ctx {
__le16 word3;
};
-struct ustorm_roce_resp_conn_ag_ctx {
+struct e4_ustorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8073,214 +8672,214 @@ struct ustorm_roce_resp_conn_ag_ctx {
__le16 word3;
};
-struct xstorm_roce_req_conn_ag_ctx {
+struct e4_xstorm_roce_req_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
u8 flags13;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -8302,224 +8901,224 @@ struct xstorm_roce_req_conn_ag_ctx {
__le32 orq_cons;
};
-struct xstorm_roce_resp_conn_ag_ctx {
+struct e4_xstorm_roce_resp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
u8 flags2;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
u8 flags4;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
u8 flags7;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
u8 flags11;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
- __le16 word1;
- __le16 irq_prod;
- __le16 word3;
- __le16 word4;
- __le16 ereserved1;
+ __le16 irq_prod_shadow;
+ __le16 word2;
__le16 irq_cons;
+ __le16 irq_prod;
+ __le16 e5_reserved1;
+ __le16 conn_dpi;
u8 rxmit_opcode;
u8 byte4;
u8 byte5;
@@ -8533,37 +9132,37 @@ struct xstorm_roce_resp_conn_ag_ctx {
__le32 msn_and_syndrome;
};
-struct ystorm_roce_req_conn_ag_ctx {
+struct e4_ystorm_roce_req_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8577,37 +9176,37 @@ struct ystorm_roce_req_conn_ag_ctx {
__le32 reg3;
};
-struct ystorm_roce_resp_conn_ag_ctx {
+struct e4_ystorm_roce_resp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -8621,6 +9220,7 @@ struct ystorm_roce_resp_conn_ag_ctx {
__le32 reg3;
};
+/* Roce doorbell data */
enum roce_flavor {
PLAIN_ROCE,
RROCE_IPV4,
@@ -8628,228 +9228,231 @@ enum roce_flavor {
MAX_ROCE_FLAVOR
};
+/* The iwarp storm context of Ystorm */
struct ystorm_iwarp_conn_st_ctx {
__le32 reserved[4];
};
+/* The iwarp storm context of Pstorm */
struct pstorm_iwarp_conn_st_ctx {
__le32 reserved[36];
};
+/* The iwarp storm context of Xstorm */
struct xstorm_iwarp_conn_st_ctx {
__le32 reserved[44];
};
-struct xstorm_iwarp_conn_ag_ctx {
+struct e4_xstorm_iwarp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
u8 flags2;
-#define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
u8 flags3;
-#define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
u8 flags7;
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
u8 flags11;
-#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
-#define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
-#define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
+#define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 physical_q1;
@@ -8897,89 +9500,89 @@ struct xstorm_iwarp_conn_ag_ctx {
__le32 reg17;
};
-struct tstorm_iwarp_conn_ag_ctx {
+struct e4_tstorm_iwarp_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
u8 flags4;
-#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
-#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 unaligned_nxt_seq;
@@ -9001,51 +9604,56 @@ struct tstorm_iwarp_conn_ag_ctx {
__le32 last_hq_sequence;
};
+/* The iwarp storm context of Tstorm */
struct tstorm_iwarp_conn_st_ctx {
__le32 reserved[60];
};
+/* The iwarp storm context of Mstorm */
struct mstorm_iwarp_conn_st_ctx {
__le32 reserved[32];
};
+/* The iwarp storm context of Ustorm */
struct ustorm_iwarp_conn_st_ctx {
__le32 reserved[24];
};
-struct iwarp_conn_context {
+/* iwarp connection context */
+struct e4_iwarp_conn_context {
struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
- struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
- struct ustorm_rdma_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
};
+/* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
struct iwarp_create_qp_ramrod_data {
u8 flags;
#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
-#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
-#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
-#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
-#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
-#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
-#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
-#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
-#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
+#define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
+#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
+#define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
+#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
+#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
+#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
+#define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
+#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
+#define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
+#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
+#define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
+#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3
+#define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6
u8 reserved1;
__le16 pd;
__le16 sq_num_pages;
@@ -9061,6 +9669,7 @@ struct iwarp_create_qp_ramrod_data {
u8 reserved2[6];
};
+/* iWARP completion queue types */
enum iwarp_eqe_async_opcode {
IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
@@ -9083,6 +9692,7 @@ struct iwarp_eqe_data_tcp_async_completion {
u8 reserved[5];
};
+/* iWARP completion queue types */
enum iwarp_eqe_sync_opcode {
IWARP_EVENT_TYPE_TCP_OFFLOAD =
11,
@@ -9095,6 +9705,7 @@ enum iwarp_eqe_sync_opcode {
MAX_IWARP_EQE_SYNC_OPCODE
};
+/* iWARP EQE completion status */
enum iwarp_fw_return_code {
IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
IWARP_CONN_ERROR_TCP_CONNECTION_RST,
@@ -9125,54 +9736,60 @@ enum iwarp_fw_return_code {
MAX_IWARP_FW_RETURN_CODE
};
+/* unaligned opaque data received from LL2 */
struct iwarp_init_func_params {
u8 ll2_ooo_q_index;
u8 reserved1[7];
};
+/* iwarp func init ramrod data */
struct iwarp_init_func_ramrod_data {
struct rdma_init_func_ramrod_data rdma;
struct tcp_init_params tcp;
struct iwarp_init_func_params iwarp;
};
+/* iWARP QP - possible states to transition to */
enum iwarp_modify_qp_new_state_type {
IWARP_MODIFY_QP_STATE_CLOSING = 1,
- IWARP_MODIFY_QP_STATE_ERROR =
- 2,
+ IWARP_MODIFY_QP_STATE_ERROR = 2,
MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
};
+/* iwarp modify qp responder ramrod data */
struct iwarp_modify_qp_ramrod_data {
__le16 transition_to_state;
__le16 flags;
-#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
-#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
-#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
-#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
-#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
-#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
-#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
+#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
+#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
+#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
+#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
+#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
+#define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
+#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
#define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
-#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
-#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
-#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
+#define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
+#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF
+#define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5
__le32 reserved3[3];
__le32 reserved4[8];
};
+/* MPA params for Enhanced mode */
struct mpa_rq_params {
__le32 ird;
__le32 ord;
};
+/* MPA host Address-Len for private data */
struct mpa_ulp_buffer {
struct regpair addr;
__le16 len;
__le16 reserved[3];
};
+/* iWARP MPA offload params common to Basic and Enhanced modes */
struct mpa_outgoing_params {
u8 crc_needed;
u8 reject;
@@ -9181,6 +9798,9 @@ struct mpa_outgoing_params {
struct mpa_ulp_buffer outgoing_ulp_buffer;
};
+/* iWARP MPA offload params passed by driver to FW in MPA Offload Request
+ * Ramrod.
+ */
struct iwarp_mpa_offload_ramrod_data {
struct mpa_outgoing_params common;
__le32 tcp_cid;
@@ -9188,18 +9808,20 @@ struct iwarp_mpa_offload_ramrod_data {
u8 tcp_connect_side;
u8 rtr_pref;
#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
-#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
-#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
-#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
+#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
+#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
+#define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
u8 reserved2;
struct mpa_ulp_buffer incoming_ulp_buffer;
struct regpair async_eqe_output_buf;
struct regpair handle_for_async;
struct regpair shared_queue_addr;
+ __le16 rcv_wnd;
u8 stats_counter_id;
- u8 reserved3[15];
+ u8 reserved3[13];
};
+/* iWARP TCP connection offload params passed by driver to FW */
struct iwarp_offload_params {
struct mpa_ulp_buffer incoming_ulp_buffer;
struct regpair async_eqe_output_buf;
@@ -9211,22 +9833,24 @@ struct iwarp_offload_params {
u8 reserved[10];
};
+/* iWARP query QP output params */
struct iwarp_query_qp_output_params {
__le32 flags;
#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
-#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
+#define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
-#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
+#define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
u8 reserved1[4];
};
+/* iWARP query QP ramrod data */
struct iwarp_query_qp_ramrod_data {
struct regpair output_params_addr;
};
+/* * iWARP Ramrod Command IDs */
enum iwarp_ramrod_cmd_id {
- IWARP_RAMROD_CMD_ID_TCP_OFFLOAD =
- 11,
+ IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
IWARP_RAMROD_CMD_ID_CREATE_QP,
@@ -9236,22 +9860,28 @@ enum iwarp_ramrod_cmd_id {
MAX_IWARP_RAMROD_CMD_ID
};
+/* Per PF iWARP retransmit path statistics */
struct iwarp_rxmit_stats_drv {
struct regpair tx_go_to_slow_start_event_cnt;
struct regpair tx_fast_retransmit_event_cnt;
};
+/* iWARP and TCP connection offload params passed by driver to FW in iWARP
+ * offload ramrod.
+ */
struct iwarp_tcp_offload_ramrod_data {
struct iwarp_offload_params iwarp;
struct tcp_offload_params_opt2 tcp;
};
+/* iWARP MPA negotiation types */
enum mpa_negotiation_mode {
MPA_NEGOTIATION_TYPE_BASIC = 1,
MPA_NEGOTIATION_TYPE_ENHANCED = 2,
MAX_MPA_NEGOTIATION_MODE
};
+/* iWARP MPA Enhanced mode RTR types */
enum mpa_rtr_type {
MPA_RTR_TYPE_NONE = 0,
MPA_RTR_TYPE_ZERO_SEND = 1,
@@ -9264,113 +9894,114 @@ enum mpa_rtr_type {
MAX_MPA_RTR_TYPE
};
+/* unaligned opaque data received from LL2 */
struct unaligned_opaque_data {
__le16 first_mpa_offset;
u8 tcp_payload_offset;
u8 flags;
#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
-#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
-#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
-#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
-#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
-#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
+#define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
+#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
+#define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
+#define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
+#define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
__le32 cid;
};
-struct mstorm_iwarp_conn_ag_ctx {
+struct e4_mstorm_iwarp_conn_ag_ctx {
u8 reserved;
u8 state;
u8 flags0;
-#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
-#define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
-#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
-#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 rcq_cons;
__le16 rcq_cons_th;
__le32 reg0;
__le32 reg1;
};
-struct ustorm_iwarp_conn_ag_ctx {
+struct e4_ustorm_iwarp_conn_ag_ctx {
u8 reserved;
u8 byte1;
u8 flags0;
-#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
-#define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
u8 flags3;
-#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
-#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -9383,37 +10014,37 @@ struct ustorm_iwarp_conn_ag_ctx {
__le16 word3;
};
-struct ystorm_iwarp_conn_ag_ctx {
+struct e4_ystorm_iwarp_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -9427,6 +10058,7 @@ struct ystorm_iwarp_conn_ag_ctx {
__le32 reg3;
};
+/* The fcoe storm context of Ystorm */
struct ystorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 cos;
@@ -9442,45 +10074,49 @@ struct ystorm_fcoe_conn_st_ctx {
struct regpair reserved;
__le16 min_frame_size;
u8 protection_info_flags;
-#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
-#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
-#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
-#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
-#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
-#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
+#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
+#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
+#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
+#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
+#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
+#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
u8 dst_protection_per_mss;
u8 src_protection_per_mss;
u8 ptu_log_page_size;
u8 flags;
-#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
-#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
-#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
-#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
-#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
-#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
+#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
+#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
+#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
+#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
+#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
+#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
u8 fcp_xfer_size;
};
+/* FCoE 16-bits vlan structure */
struct fcoe_vlan_fields {
__le16 fields;
-#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
-#define FCOE_VLAN_FIELDS_VID_SHIFT 0
-#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
-#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
-#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
-#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
+#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
+#define FCOE_VLAN_FIELDS_VID_SHIFT 0
+#define FCOE_VLAN_FIELDS_CLI_MASK 0x1
+#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
+#define FCOE_VLAN_FIELDS_PRI_MASK 0x7
+#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
};
+/* FCoE 16-bits vlan union */
union fcoe_vlan_field_union {
struct fcoe_vlan_fields fields;
__le16 val;
};
+/* FCoE 16-bits vlan, vif union */
union fcoe_vlan_vif_field_union {
union fcoe_vlan_field_union vlan;
__le16 vif;
};
+/* Ethernet context section */
struct pstorm_fcoe_eth_context_section {
u8 remote_addr_3;
u8 remote_addr_2;
@@ -9500,6 +10136,7 @@ struct pstorm_fcoe_eth_context_section {
__le16 inner_eth_type;
};
+/* The fcoe storm context of Pstorm */
struct pstorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 cos;
@@ -9513,16 +10150,18 @@ struct pstorm_fcoe_conn_st_ctx {
u8 sid_1;
u8 sid_0;
u8 flags;
-#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
-#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
-#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
-#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
-#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
-#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
-#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
-#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
-#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF
-#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4
+#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
+#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
+#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
+#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
+#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
+#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
+#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
+#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
+#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
+#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4
+#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
+#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5
u8 did_2;
u8 did_1;
u8 did_0;
@@ -9532,6 +10171,7 @@ struct pstorm_fcoe_conn_st_ctx {
u8 reserved1;
};
+/* The fcoe storm context of Xstorm */
struct xstorm_fcoe_conn_st_ctx {
u8 func_mode;
u8 src_mac_index;
@@ -9539,16 +10179,16 @@ struct xstorm_fcoe_conn_st_ctx {
u8 cached_wqes_avail;
__le16 stat_ram_addr;
u8 flags;
-#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
-#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
-#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
-#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
-#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
-#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
-#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
+#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
+#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
+#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
+#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
+#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
+#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
+#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
u8 cached_wqes_offset;
u8 reserved2;
u8 eth_hdr_size;
@@ -9574,18 +10214,18 @@ struct xstorm_fcoe_conn_st_ctx {
u8 fcp_cmd_byte_credit;
u8 fcp_rsp_byte_credit;
__le16 protection_info;
-#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
-#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
-#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
-#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
-#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
-#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
-#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
-#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
-#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
+#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
+#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
+#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
+#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
+#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
+#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
+#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
+#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
+#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
__le16 xferq_pbl_next_index;
__le16 page_size;
u8 mid_seq;
@@ -9594,216 +10234,216 @@ struct xstorm_fcoe_conn_st_ctx {
struct fcoe_wqe cached_wqes[16];
};
-struct xstorm_fcoe_conn_ag_ctx {
+struct e4_xstorm_fcoe_conn_ag_ctx {
u8 reserved0;
- u8 fcoe_state;
+ u8 state;
u8 flags0;
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
u8 flags1;
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
u8 flags2;
-#define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
u8 flags3;
-#define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
u8 flags6;
-#define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
u8 flags7;
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
u8 flags11;
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
u8 flags12;
-#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
-#define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
-#define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
-#define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
+#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
+#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 word1;
@@ -9831,6 +10471,7 @@ struct xstorm_fcoe_conn_ag_ctx {
__le32 reg8;
};
+/* The fcoe storm context of Ustorm */
struct ustorm_fcoe_conn_st_ctx {
struct regpair respq_pbl_addr;
__le16 num_pages_in_pbl;
@@ -9840,150 +10481,150 @@ struct ustorm_fcoe_conn_st_ctx {
u8 reserved[2];
};
-struct tstorm_fcoe_conn_ag_ctx {
+struct e4_tstorm_fcoe_conn_ag_ctx {
u8 reserved0;
- u8 fcoe_state;
+ u8 state;
u8 flags0;
-#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
u8 flags1;
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
};
-struct ustorm_fcoe_conn_ag_ctx {
+struct e4_ustorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -9996,72 +10637,76 @@ struct ustorm_fcoe_conn_ag_ctx {
__le16 word3;
};
+/* The fcoe storm context of Tstorm */
struct tstorm_fcoe_conn_st_ctx {
__le16 stat_ram_addr;
__le16 rx_max_fc_payload_len;
__le16 e_d_tov_val;
u8 flags;
-#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
-#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
-#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
-#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
-#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
-#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
+#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
+#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
+#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
+#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
+#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
+#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
u8 timers_cleanup_invocation_cnt;
__le32 reserved1[2];
- __le32 dst_mac_address_bytes0to3;
- __le16 dst_mac_address_bytes4to5;
+ __le32 dst_mac_address_bytes_0_to_3;
+ __le16 dst_mac_address_bytes_4_to_5;
__le16 ramrod_echo;
u8 flags1;
-#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
-#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
-#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
-#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
- u8 q_relative_offset;
+#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
+#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
+#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
+#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
+ u8 cq_relative_offset;
+ u8 cmdq_relative_offset;
u8 bdq_resource_id;
- u8 reserved0[5];
+ u8 reserved0[4];
};
-struct mstorm_fcoe_conn_ag_ctx {
+struct e4_mstorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
+/* Fast path part of the fcoe storm context of Mstorm */
struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
__le16 xfer_prod;
- __le16 reserved1;
+ u8 num_cqs;
+ u8 reserved1;
u8 protection_info;
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
@@ -10073,6 +10718,7 @@ struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
u8 reserved2[2];
};
+/* Non fast path part of the fcoe storm context of Mstorm */
struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
__le16 conn_id;
__le16 stat_ram_addr;
@@ -10088,37 +10734,46 @@ struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
struct regpair reserved2[3];
};
+/* The fcoe storm context of Mstorm */
struct mstorm_fcoe_conn_st_ctx {
struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
};
-struct fcoe_conn_context {
+/* fcoe connection context */
+struct e4_fcoe_conn_context {
struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
- struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
+ struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
struct regpair xstorm_ag_padding[6];
struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
struct regpair ustorm_st_padding[2];
- struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
+ struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
struct regpair tstorm_ag_padding[2];
struct timers_context timer_context;
- struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
- struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
};
+/* FCoE connection offload params passed by driver to FW in FCoE offload
+ * ramrod.
+ */
struct fcoe_conn_offload_ramrod_params {
struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
};
+/* FCoE connection terminate params passed by driver to FW in FCoE terminate
+ * conn ramrod.
+ */
struct fcoe_conn_terminate_ramrod_params {
struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
};
+/* FCoE event type */
enum fcoe_event_type {
FCOE_EVENT_INIT_FUNC,
FCOE_EVENT_DESTROY_FUNC,
@@ -10129,10 +10784,12 @@ enum fcoe_event_type {
MAX_FCOE_EVENT_TYPE
};
+/* FCoE init params passed by driver to FW in FCoE init ramrod */
struct fcoe_init_ramrod_params {
struct fcoe_init_func_ramrod_data init_ramrod_data;
};
+/* FCoE ramrod Command IDs */
enum fcoe_ramrod_cmd_id {
FCOE_RAMROD_CMD_ID_INIT_FUNC,
FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
@@ -10142,41 +10799,44 @@ enum fcoe_ramrod_cmd_id {
MAX_FCOE_RAMROD_CMD_ID
};
+/* FCoE statistics params buffer passed by driver to FW in FCoE statistics
+ * ramrod.
+ */
struct fcoe_stat_ramrod_params {
struct fcoe_stat_ramrod_data stat_ramrod_data;
};
-struct ystorm_fcoe_conn_ag_ctx {
+struct e4_ystorm_fcoe_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -10190,230 +10850,233 @@ struct ystorm_fcoe_conn_ag_ctx {
__le32 reg3;
};
+/* The iscsi storm connection context of Ystorm */
struct ystorm_iscsi_conn_st_ctx {
- __le32 reserved[4];
+ __le32 reserved[8];
};
+/* Combined iSCSI and TCP storm connection of Pstorm */
struct pstorm_iscsi_tcp_conn_st_ctx {
__le32 tcp[32];
__le32 iscsi[4];
};
+/* The combined tcp and iscsi storm context of Xstorm */
struct xstorm_iscsi_tcp_conn_st_ctx {
- __le32 reserved_iscsi[40];
__le32 reserved_tcp[4];
+ __le32 reserved_iscsi[44];
};
-struct xstorm_iscsi_conn_ag_ctx {
+struct e4_xstorm_iscsi_conn_ag_ctx {
u8 cdu_validation;
u8 state;
u8 flags0;
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
u8 flags1;
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
u8 flags2;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
u8 flags3;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
u8 flags4;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
u8 flags5;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
u8 flags6;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
u8 flags7;
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
u8 flags8;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
u8 flags9;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
u8 flags10;
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
u8 flags11;
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
u8 flags12;
-#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
u8 flags13;
-#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
u8 flags14;
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
-#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
-#define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
-#define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
+#define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
u8 byte2;
__le16 physical_q0;
__le16 physical_q1;
@@ -10449,7 +11112,7 @@ struct xstorm_iscsi_conn_ag_ctx {
u8 byte13;
u8 byte14;
u8 byte15;
- u8 ereserved;
+ u8 e5_reserved;
__le16 word11;
__le32 reg10;
__le32 reg11;
@@ -10461,89 +11124,89 @@ struct xstorm_iscsi_conn_ag_ctx {
__le32 reg17;
};
-struct tstorm_iscsi_conn_ag_ctx {
+struct e4_tstorm_iscsi_conn_ag_ctx {
u8 reserved0;
u8 state;
u8 flags0;
-#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
u8 flags2;
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
u8 flags3;
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
u8 flags4;
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags5;
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
__le32 reg0;
__le32 reg1;
__le32 reg2;
@@ -10558,63 +11221,63 @@ struct tstorm_iscsi_conn_ag_ctx {
__le16 word0;
};
-struct ustorm_iscsi_conn_ag_ctx {
+struct e4_ustorm_iscsi_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
-#define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
u8 flags2;
-#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
-#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
-#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
u8 flags3;
-#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
-#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
-#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
-#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
-#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
-#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
-#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
-#define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
+#define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -10627,113 +11290,117 @@ struct ustorm_iscsi_conn_ag_ctx {
__le16 word3;
};
+/* The iscsi storm connection context of Tstorm */
struct tstorm_iscsi_conn_st_ctx {
- __le32 reserved[40];
+ __le32 reserved[44];
};
-struct mstorm_iscsi_conn_ag_ctx {
+struct e4_mstorm_iscsi_conn_ag_ctx {
u8 reserved;
u8 state;
u8 flags0;
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
__le16 word0;
__le16 word1;
__le32 reg0;
__le32 reg1;
};
+/* Combined iSCSI and TCP storm connection of Mstorm */
struct mstorm_iscsi_tcp_conn_st_ctx {
__le32 reserved_tcp[20];
- __le32 reserved_iscsi[8];
+ __le32 reserved_iscsi[12];
};
+/* The iscsi storm context of Ustorm */
struct ustorm_iscsi_conn_st_ctx {
__le32 reserved[52];
};
-struct iscsi_conn_context {
+/* iscsi connection context */
+struct e4_iscsi_conn_context {
struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
- struct regpair ystorm_st_padding[2];
struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
struct regpair pstorm_st_padding[2];
struct pb_context xpb2_context;
struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
struct regpair xstorm_st_padding[2];
- struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
- struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
+ struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
+ struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
struct regpair tstorm_ag_padding[2];
struct timers_context timer_context;
- struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
struct pb_context upb_context;
struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
- struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
};
+/* iSCSI init params passed by driver to FW in iSCSI init ramrod */
struct iscsi_init_ramrod_params {
struct iscsi_spe_func_init iscsi_init_spe;
struct tcp_init_params tcp_init;
};
-struct ystorm_iscsi_conn_ag_ctx {
+struct e4_ystorm_iscsi_conn_ag_ctx {
u8 byte0;
u8 byte1;
u8 flags0;
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
u8 flags1;
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2;
u8 byte3;
__le16 word0;
@@ -11613,7 +12280,7 @@ struct public_drv_mb {
#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
-#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
+#define DRV_MB_PARAM_NVM_LEN_OFFSET 24
#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hw.c b/drivers/net/ethernet/qlogic/qed/qed_hw.c
index a05feb3..8efec90 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hw.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_hw.c
@@ -807,3 +807,73 @@ int qed_dmae_host2host(struct qed_hwfn *p_hwfn,
return rc;
}
+int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, const char *phase)
+{
+ u32 size = PAGE_SIZE / 2, val;
+ struct qed_dmae_params params;
+ int rc = 0;
+ dma_addr_t p_phys;
+ void *p_virt;
+ u32 *p_tmp;
+
+ p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
+ 2 * size, &p_phys, GFP_KERNEL);
+ if (!p_virt) {
+ DP_NOTICE(p_hwfn,
+ "DMAE sanity [%s]: failed to allocate memory\n",
+ phase);
+ return -ENOMEM;
+ }
+
+ /* Fill the bottom half of the allocated memory with a known pattern */
+ for (p_tmp = (u32 *)p_virt;
+ p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) {
+ /* Save the address itself as the value */
+ val = (u32)(uintptr_t)p_tmp;
+ *p_tmp = val;
+ }
+
+ /* Zero the top half of the allocated memory */
+ memset((u8 *)p_virt + size, 0, size);
+
+ DP_VERBOSE(p_hwfn,
+ QED_MSG_SP,
+ "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n",
+ phase,
+ (unsigned long long)p_phys,
+ p_virt,
+ (unsigned long long)(p_phys + size),
+ (u8 *)p_virt + size, size);
+
+ memset(¶ms, 0, sizeof(params));
+ rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
+ size / 4 /* size_in_dwords */, ¶ms);
+ if (rc) {
+ DP_NOTICE(p_hwfn,
+ "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n",
+ phase, rc);
+ goto out;
+ }
+
+ /* Verify that the top half of the allocated memory has the pattern */
+ for (p_tmp = (u32 *)((u8 *)p_virt + size);
+ p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) {
+ /* The corresponding address in the bottom half */
+ val = (u32)(uintptr_t)p_tmp - size;
+
+ if (*p_tmp != val) {
+ DP_NOTICE(p_hwfn,
+ "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
+ phase,
+ p_phys + (u32)((u8 *)p_tmp - (u8 *)p_virt),
+ p_tmp, *p_tmp, val);
+ rc = -EINVAL;
+ goto out;
+ }
+ }
+
+out:
+ dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys);
+ return rc;
+}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_hw.h b/drivers/net/ethernet/qlogic/qed/qed_hw.h
index f2505c6..8db2839 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_hw.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_hw.h
@@ -299,4 +299,8 @@ void qed_port_unpretend(struct qed_hwfn *p_hwfn,
int qed_init_fw_data(struct qed_dev *cdev,
const u8 *fw_data);
+
+int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt, const char *phase);
+
#endif
diff --git a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
index b069ad0..409cf0e 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
@@ -31,6 +31,7 @@
*/
#include <linux/types.h>
+#include <linux/crc8.h>
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -40,102 +41,196 @@
#include "qed_init_ops.h"
#include "qed_reg_addr.h"
+#define CDU_VALIDATION_DEFAULT_CFG 61
+
+static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
+ {400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */
+ {528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */
+ {608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */
+};
+
+static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
+ {240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
+};
+
/* General constants */
#define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
QM_PQ_ELEMENT_SIZE, \
0x1000) : 0)
#define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \
0x100) - 1 : 0)
-#define QM_INVALID_PQ_ID 0xffff
+#define QM_INVALID_PQ_ID 0xffff
+
/* Feature enable */
-#define QM_BYPASS_EN 1
-#define QM_BYTE_CRD_EN 1
+#define QM_BYPASS_EN 1
+#define QM_BYTE_CRD_EN 1
+
/* Other PQ constants */
-#define QM_OTHER_PQS_PER_PF 4
+#define QM_OTHER_PQS_PER_PF 4
+
/* WFQ constants */
+
+/* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
#define QM_WFQ_UPPER_BOUND 62500000
-#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
-#define QM_WFQ_VP_PQ_PF_SHIFT 5
-#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
-#define QM_WFQ_MAX_INC_VAL 43750000
+
+/* Bit of VOQ in WFQ VP PQ map */
+#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
+
+/* Bit of PF in WFQ VP PQ map */
+#define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
+
+/* 0x9000 = 4*9*1024 */
+#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
+
+/* Max WFQ increment value is 0.7 * upper bound */
+#define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10)
/* RL constants */
-#define QM_RL_UPPER_BOUND 62500000
-#define QM_RL_PERIOD 5 /* in us */
-#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
-#define QM_RL_MAX_INC_VAL 43750000
-#define QM_RL_INC_VAL(rate) max_t(u32, \
- (u32)(((rate ? rate : \
- 1000000) * \
- QM_RL_PERIOD * \
- 101) / (8 * 100)), 1)
+
+/* Period in us */
+#define QM_RL_PERIOD 5
+/* Period in 25MHz cycles */
+#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
+
+/* RL increment value - rate is specified in mbps */
+#define QM_RL_INC_VAL(rate) ({ \
+ typeof(rate) __rate = (rate); \
+ max_t(u32, \
+ (u32)(((__rate ? __rate : 1000000) * QM_RL_PERIOD * 101) / \
+ (8 * 100)), \
+ 1); })
+
+/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
+#define QM_PF_RL_UPPER_BOUND 62500000
+
+/* Max PF RL increment value is 0.7 * upper bound */
+#define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10)
+
+/* Vport RL Upper bound, link speed is in Mpbs */
+#define QM_VP_RL_UPPER_BOUND(speed) ((u32)max_t(u32, \
+ QM_RL_INC_VAL(speed), \
+ 9700 + 1000))
+
+/* Max Vport RL increment value is the Vport RL upper bound */
+#define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed)
+
+/* Vport RL credit threshold in case of QM bypass */
+#define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
+
/* AFullOprtnstcCrdMask constants */
-#define QM_OPPOR_LINE_VOQ_DEF 1
-#define QM_OPPOR_FW_STOP_DEF 0
-#define QM_OPPOR_PQ_EMPTY_DEF 1
+#define QM_OPPOR_LINE_VOQ_DEF 1
+#define QM_OPPOR_FW_STOP_DEF 0
+#define QM_OPPOR_PQ_EMPTY_DEF 1
+
/* Command Queue constants */
-#define PBF_CMDQ_PURE_LB_LINES 150
-#define PBF_CMDQ_LINES_RT_OFFSET(voq) ( \
- PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \
- (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
- PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
-#define PBF_BTB_GUARANTEED_RT_OFFSET(voq) ( \
- PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \
- (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
- PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
-#define QM_VOQ_LINE_CRD(pbf_cmd_lines) ((((pbf_cmd_lines) - \
- 4) * \
- 2) | QM_LINE_CRD_REG_SIGN_BIT)
+
+/* Pure LB CmdQ lines (+spare) */
+#define PBF_CMDQ_PURE_LB_LINES 150
+
+#define PBF_CMDQ_LINES_E5_RSVD_RATIO 8
+
+#define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
+ (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
+ (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
+ PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
+
+#define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
+ (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
+ (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
+ PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
+
+#define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
+ ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
+
/* BTB: blocks constants (block size = 256B) */
-#define BTB_JUMBO_PKT_BLOCKS 38
-#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
-#define BTB_PURE_LB_FACTOR 10
-#define BTB_PURE_LB_RATIO 7
+
+/* 256B blocks in 9700B packet */
+#define BTB_JUMBO_PKT_BLOCKS 38
+
+/* Headroom per-port */
+#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
+#define BTB_PURE_LB_FACTOR 10
+
+/* Factored (hence really 0.7) */
+#define BTB_PURE_LB_RATIO 7
+
/* QM stop command constants */
-#define QM_STOP_PQ_MASK_WIDTH 32
-#define QM_STOP_CMD_ADDR 2
-#define QM_STOP_CMD_STRUCT_SIZE 2
-#define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
-#define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
-#define QM_STOP_CMD_PAUSE_MASK_MASK -1
-#define QM_STOP_CMD_GROUP_ID_OFFSET 1
-#define QM_STOP_CMD_GROUP_ID_SHIFT 16
-#define QM_STOP_CMD_GROUP_ID_MASK 15
-#define QM_STOP_CMD_PQ_TYPE_OFFSET 1
-#define QM_STOP_CMD_PQ_TYPE_SHIFT 24
-#define QM_STOP_CMD_PQ_TYPE_MASK 1
-#define QM_STOP_CMD_MAX_POLL_COUNT 100
-#define QM_STOP_CMD_POLL_PERIOD_US 500
+#define QM_STOP_PQ_MASK_WIDTH 32
+#define QM_STOP_CMD_ADDR 2
+#define QM_STOP_CMD_STRUCT_SIZE 2
+#define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
+#define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
+#define QM_STOP_CMD_PAUSE_MASK_MASK -1
+#define QM_STOP_CMD_GROUP_ID_OFFSET 1
+#define QM_STOP_CMD_GROUP_ID_SHIFT 16
+#define QM_STOP_CMD_GROUP_ID_MASK 15
+#define QM_STOP_CMD_PQ_TYPE_OFFSET 1
+#define QM_STOP_CMD_PQ_TYPE_SHIFT 24
+#define QM_STOP_CMD_PQ_TYPE_MASK 1
+#define QM_STOP_CMD_MAX_POLL_COUNT 100
+#define QM_STOP_CMD_POLL_PERIOD_US 500
/* QM command macros */
-#define QM_CMD_STRUCT_SIZE(cmd) cmd ## \
- _STRUCT_SIZE
-#define QM_CMD_SET_FIELD(var, cmd, field, \
- value) SET_FIELD(var[cmd ## _ ## field ## \
- _OFFSET], \
- cmd ## _ ## field, \
- value)
-/* QM: VOQ macros */
-#define PHYS_VOQ(port, tc, max_phys_tcs_per_port) ((port) * \
- (max_phys_tcs_per_port) + \
- (tc))
-#define LB_VOQ(port) ( \
- MAX_PHYS_VOQS + (port))
-#define VOQ(port, tc, max_phy_tcs_pr_port) \
- ((tc) < \
- LB_TC ? PHYS_VOQ(port, \
- tc, \
- max_phy_tcs_pr_port) \
- : LB_VOQ(port))
+#define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
+#define QM_CMD_SET_FIELD(var, cmd, field, value) \
+ SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
+ cmd ## _ ## field, \
+ value)
+
+#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, vp_pq_id, rl_id, \
+ ext_voq, wrr) \
+ do { \
+ typeof(map) __map; \
+ memset(&__map, 0, sizeof(__map)); \
+ SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _PQ_VALID, 1); \
+ SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_VALID, \
+ rl_valid); \
+ SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VP_PQ_ID, \
+ vp_pq_id); \
+ SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_ID, rl_id); \
+ SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VOQ, ext_voq); \
+ SET_FIELD(__map.reg, \
+ QM_RF_PQ_MAP_ ## chip ## _WRR_WEIGHT_GROUP, wrr); \
+ STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
+ *((u32 *)&__map)); \
+ (map) = __map; \
+ } while (0)
+
+#define WRITE_PQ_INFO_TO_RAM 1
+#define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \
+ (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \
+ ((rl_valid) << 22) | ((rl) << 24))
+#define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
+ (XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 21776 + (pq_id) * 4)
+
/******************** INTERNAL IMPLEMENTATION *********************/
+
+/* Returns the external VOQ number */
+static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn,
+ u8 port_id, u8 tc, u8 max_phys_tcs_per_port)
+{
+ if (tc == PURE_LB_TC)
+ return NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + port_id;
+ else
+ return port_id * max_phys_tcs_per_port + tc;
+}
+
/* Prepare PF RL enable/disable runtime init values */
static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
{
STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
if (pf_rl_en) {
+ u8 num_ext_voqs = MAX_NUM_VOQS_E4;
+ u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
+
/* Enable RLs for all VOQs */
- STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
- (1 << MAX_NUM_VOQS) - 1);
+ STORE_RT_REG(p_hwfn,
+ QM_REG_RLPFVOQENABLE_RT_OFFSET,
+ (u32)voq_bit_mask);
+ if (num_ext_voqs >= 32)
+ STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET,
+ (u32)(voq_bit_mask >> 32));
+
/* Write RL period */
STORE_RT_REG(p_hwfn,
QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
@@ -147,7 +242,7 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
- QM_RL_UPPER_BOUND);
+ QM_PF_RL_UPPER_BOUND);
}
}
@@ -181,7 +276,7 @@ static void qed_enable_vport_rl(struct qed_hwfn *p_hwfn, bool vport_rl_en)
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
- QM_RL_UPPER_BOUND);
+ QM_VP_RL_BYPASS_THRESH_SPEED);
}
}
@@ -202,15 +297,15 @@ static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
* the specified VOQ.
*/
static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
- u8 voq, u16 cmdq_lines)
+ u8 ext_voq, u16 cmdq_lines)
{
- u32 qm_line_crd;
+ u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
- qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
- OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq),
+ OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq),
(u32)cmdq_lines);
- STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
- STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq,
+ STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq,
+ qm_line_crd);
+ STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq,
qm_line_crd);
}
@@ -221,43 +316,52 @@ static void qed_cmdq_lines_rt_init(
u8 max_phys_tcs_per_port,
struct init_qm_port_params port_params[MAX_NUM_PORTS])
{
- u8 tc, voq, port_id, num_tcs_in_port;
+ u8 tc, ext_voq, port_id, num_tcs_in_port;
+ u8 num_ext_voqs = MAX_NUM_VOQS_E4;
+
+ /* Clear PBF lines of all VOQs */
+ for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
+ STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);
- /* Clear PBF lines for all VOQs */
- for (voq = 0; voq < MAX_NUM_VOQS; voq++)
- STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
- if (port_params[port_id].active) {
- u16 phys_lines, phys_lines_per_tc;
-
- /* find #lines to divide between active phys TCs */
- phys_lines = port_params[port_id].num_pbf_cmd_lines -
- PBF_CMDQ_PURE_LB_LINES;
- /* find #lines per active physical TC */
- num_tcs_in_port = 0;
- for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
- if (((port_params[port_id].active_phys_tcs >>
- tc) & 0x1) == 1)
- num_tcs_in_port++;
- }
+ u16 phys_lines, phys_lines_per_tc;
- phys_lines_per_tc = phys_lines / num_tcs_in_port;
- /* init registers per active TC */
- for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
- if (((port_params[port_id].active_phys_tcs >>
- tc) & 0x1) != 1)
- continue;
+ if (!port_params[port_id].active)
+ continue;
- voq = PHYS_VOQ(port_id, tc,
- max_phys_tcs_per_port);
- qed_cmdq_lines_voq_rt_init(p_hwfn, voq,
- phys_lines_per_tc);
- }
+ /* Find number of command queue lines to divide between the
+ * active physical TCs. In E5, 1/8 of the lines are reserved.
+ * the lines for pure LB TC are subtracted.
+ */
+ phys_lines = port_params[port_id].num_pbf_cmd_lines;
+ phys_lines -= PBF_CMDQ_PURE_LB_LINES;
+
+ /* Find #lines per active physical TC */
+ num_tcs_in_port = 0;
+ for (tc = 0; tc < max_phys_tcs_per_port; tc++)
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1)
+ num_tcs_in_port++;
+ phys_lines_per_tc = phys_lines / num_tcs_in_port;
- /* init registers for pure LB TC */
- qed_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
- PBF_CMDQ_PURE_LB_LINES);
+ /* Init registers per active TC */
+ for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
+ ext_voq = qed_get_ext_voq(p_hwfn,
+ port_id,
+ tc, max_phys_tcs_per_port);
+ if (((port_params[port_id].active_phys_tcs >>
+ tc) & 0x1) == 1)
+ qed_cmdq_lines_voq_rt_init(p_hwfn,
+ ext_voq,
+ phys_lines_per_tc);
}
+
+ /* Init registers for pure LB TC */
+ ext_voq = qed_get_ext_voq(p_hwfn,
+ port_id,
+ PURE_LB_TC, max_phys_tcs_per_port);
+ qed_cmdq_lines_voq_rt_init(p_hwfn,
+ ext_voq, PBF_CMDQ_PURE_LB_LINES);
}
}
@@ -268,11 +372,9 @@ static void qed_btb_blocks_rt_init(
struct init_qm_port_params port_params[MAX_NUM_PORTS])
{
u32 usable_blocks, pure_lb_blocks, phys_blocks;
- u8 tc, voq, port_id, num_tcs_in_port;
+ u8 tc, ext_voq, port_id, num_tcs_in_port;
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
- u32 temp;
-
if (!port_params[port_id].active)
continue;
@@ -280,13 +382,14 @@ static void qed_btb_blocks_rt_init(
usable_blocks = port_params[port_id].num_btb_blocks -
BTB_HEADROOM_BLOCKS;
- /* find blocks per physical TC */
+ /* Find blocks per physical TC. use factor to avoid floating
+ * arithmethic.
+ */
num_tcs_in_port = 0;
- for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
+ for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
if (((port_params[port_id].active_phys_tcs >>
tc) & 0x1) == 1)
num_tcs_in_port++;
- }
pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
(num_tcs_in_port * BTB_PURE_LB_FACTOR +
@@ -299,47 +402,55 @@ static void qed_btb_blocks_rt_init(
/* Init physical TCs */
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
if (((port_params[port_id].active_phys_tcs >>
- tc) & 0x1) != 1)
- continue;
-
- voq = PHYS_VOQ(port_id, tc,
- max_phys_tcs_per_port);
- STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq),
- phys_blocks);
+ tc) & 0x1) == 1) {
+ ext_voq =
+ qed_get_ext_voq(p_hwfn,
+ port_id,
+ tc,
+ max_phys_tcs_per_port);
+ STORE_RT_REG(p_hwfn,
+ PBF_BTB_GUARANTEED_RT_OFFSET
+ (ext_voq), phys_blocks);
+ }
}
/* Init pure LB TC */
- temp = LB_VOQ(port_id);
- STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(temp),
+ ext_voq = qed_get_ext_voq(p_hwfn,
+ port_id,
+ PURE_LB_TC, max_phys_tcs_per_port);
+ STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
pure_lb_blocks);
}
}
/* Prepare Tx PQ mapping runtime init values for the specified PF */
-static void qed_tx_pq_map_rt_init(
- struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt,
- struct qed_qm_pf_rt_init_params *p_params,
- u32 base_mem_addr_4kb)
+static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ struct qed_qm_pf_rt_init_params *p_params,
+ u32 base_mem_addr_4kb)
{
- struct init_qm_vport_params *vport_params = p_params->vport_params;
- u16 num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
- u16 first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE;
- u16 last_pq_group = (p_params->start_pq + num_pqs - 1) /
- QM_PF_QUEUE_GROUP_SIZE;
- u16 i, pq_id, pq_group;
-
- /* A bit per Tx PQ indicating if the PQ is associated with a VF */
u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
+ struct init_qm_vport_params *vport_params = p_params->vport_params;
u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
- u32 pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
- u32 vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
- u32 mem_addr_4kb = base_mem_addr_4kb;
+ u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group;
+ struct init_qm_pq_params *pq_params = p_params->pq_params;
+ u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
+
+ num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
+
+ first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE;
+ last_pq_group = (p_params->start_pq + num_pqs - 1) /
+ QM_PF_QUEUE_GROUP_SIZE;
+
+ pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
+ vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
+ mem_addr_4kb = base_mem_addr_4kb;
/* Set mapping from PQ group to PF */
for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
(u32)(p_params->pf_id));
+
/* Set PQ sizes */
STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
QM_PQ_SIZE_256B(p_params->num_pf_cids));
@@ -348,58 +459,82 @@ static void qed_tx_pq_map_rt_init(
/* Go over all Tx PQs */
for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
- u8 voq = VOQ(p_params->port_id, p_params->pq_params[i].tc_id,
- p_params->max_phys_tcs_per_port);
- bool is_vf_pq = (i >= p_params->num_pf_pqs);
- struct qm_rf_pq_map tx_pq_map;
-
- bool rl_valid = p_params->pq_params[i].rl_valid &&
- (p_params->pq_params[i].vport_id <
- MAX_QM_GLOBAL_RLS);
+ u8 ext_voq, vport_id_in_pf, tc_id = pq_params[i].tc_id;
+ u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
+ struct qm_rf_pq_map_e4 tx_pq_map;
+ bool is_vf_pq, rl_valid;
+ u16 *p_first_tx_pq_id;
+
+ ext_voq = qed_get_ext_voq(p_hwfn,
+ p_params->port_id,
+ tc_id,
+ p_params->max_phys_tcs_per_port);
+ is_vf_pq = (i >= p_params->num_pf_pqs);
+ rl_valid = pq_params[i].rl_valid &&
+ pq_params[i].vport_id < max_qm_global_rls;
/* Update first Tx PQ of VPORT/TC */
- u8 vport_id_in_pf = p_params->pq_params[i].vport_id -
- p_params->start_vport;
- u16 *pq_ids = &vport_params[vport_id_in_pf].first_tx_pq_id[0];
- u16 first_tx_pq_id = pq_ids[p_params->pq_params[i].tc_id];
+ vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport;
+ p_first_tx_pq_id =
+ &vport_params[vport_id_in_pf].first_tx_pq_id[tc_id];
+ if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
+ u32 map_val =
+ (ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
+ (p_params->pf_id << QM_WFQ_VP_PQ_PF_E4_SHIFT);
- if (first_tx_pq_id == QM_INVALID_PQ_ID) {
/* Create new VP PQ */
- pq_ids[p_params->pq_params[i].tc_id] = pq_id;
- first_tx_pq_id = pq_id;
+ *p_first_tx_pq_id = pq_id;
/* Map VP PQ to VOQ and PF */
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPMAP_RT_OFFSET +
- first_tx_pq_id,
- (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
- (p_params->pf_id <<
- QM_WFQ_VP_PQ_PF_SHIFT));
+ *p_first_tx_pq_id,
+ map_val);
}
- if (p_params->pq_params[i].rl_valid && !rl_valid)
+ /* Check RL ID */
+ if (pq_params[i].rl_valid && pq_params[i].vport_id >=
+ max_qm_global_rls)
DP_NOTICE(p_hwfn,
- "Invalid VPORT ID for rate limiter configuration");
- /* Fill PQ map entry */
- memset(&tx_pq_map, 0, sizeof(tx_pq_map));
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
- SET_FIELD(tx_pq_map.reg,
- QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID,
- rl_valid ?
- p_params->pq_params[i].vport_id : 0);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
- SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
- p_params->pq_params[i].wrr_group);
- /* Write PQ map entry to CAM */
- STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id,
- *((u32 *)&tx_pq_map));
- /* Set base address */
+ "Invalid VPORT ID for rate limiter configuration\n");
+
+ /* Prepare PQ map entry */
+ QM_INIT_TX_PQ_MAP(p_hwfn,
+ tx_pq_map,
+ E4,
+ pq_id,
+ rl_valid ? 1 : 0,
+ *p_first_tx_pq_id,
+ rl_valid ? pq_params[i].vport_id : 0,
+ ext_voq, pq_params[i].wrr_group);
+
+ /* Set PQ base address */
STORE_RT_REG(p_hwfn,
QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
mem_addr_4kb);
+ /* Clear PQ pointer table entry (64 bit) */
+ if (p_params->is_pf_loading)
+ for (j = 0; j < 2; j++)
+ STORE_RT_REG(p_hwfn,
+ QM_REG_PTRTBLTX_RT_OFFSET +
+ (pq_id * 2) + j, 0);
+
+ /* Write PQ info to RAM */
+ if (WRITE_PQ_INFO_TO_RAM != 0) {
+ u32 pq_info = 0;
+
+ pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id,
+ p_params->pf_id,
+ tc_id,
+ p_params->port_id,
+ rl_valid ? 1 : 0,
+ rl_valid ?
+ pq_params[i].vport_id : 0);
+ qed_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
+ pq_info);
+ }
+
/* If VF PQ, add indication to PQ VF mask */
if (is_vf_pq) {
tx_pq_vf_mask[pq_id /
@@ -421,16 +556,16 @@ static void qed_tx_pq_map_rt_init(
/* Prepare Other PQ mapping runtime init values for the specified PF */
static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
- u8 port_id,
u8 pf_id,
+ bool is_pf_loading,
u32 num_pf_cids,
u32 num_tids, u32 base_mem_addr_4kb)
{
u32 pq_size, pq_mem_4kb, mem_addr_4kb;
- u16 i, pq_id, pq_group;
+ u16 i, j, pq_id, pq_group;
- /* a single other PQ group is used in each PF,
- * where PQ group i is used in PF i.
+ /* A single other PQ group is used in each PF, where PQ group i is used
+ * in PF i.
*/
pq_group = pf_id;
pq_size = num_pf_cids + num_tids;
@@ -440,16 +575,25 @@ static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
/* Map PQ group to PF */
STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
(u32)(pf_id));
+
/* Set PQ sizes */
STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
QM_PQ_SIZE_256B(pq_size));
- /* Set base address */
for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
+ /* Set PQ base address */
STORE_RT_REG(p_hwfn,
QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
mem_addr_4kb);
+
+ /* Clear PQ pointer table entry */
+ if (is_pf_loading)
+ for (j = 0; j < 2; j++)
+ STORE_RT_REG(p_hwfn,
+ QM_REG_PTRTBLOTHER_RT_OFFSET +
+ (pq_id * 2) + j, 0);
+
mem_addr_4kb += pq_mem_4kb;
}
}
@@ -461,16 +605,11 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
struct qed_qm_pf_rt_init_params *p_params)
{
u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
- u32 crd_reg_offset;
- u32 inc_val;
+ struct init_qm_pq_params *pq_params = p_params->pq_params;
+ u32 inc_val, crd_reg_offset;
+ u8 ext_voq;
u16 i;
- if (p_params->pf_id < MAX_NUM_PFS_BB)
- crd_reg_offset = QM_REG_WFQPFCRD_RT_OFFSET;
- else
- crd_reg_offset = QM_REG_WFQPFCRD_MSB_RT_OFFSET;
- crd_reg_offset += p_params->pf_id % MAX_NUM_PFS_BB;
-
inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
@@ -478,19 +617,26 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
}
for (i = 0; i < num_tx_pqs; i++) {
- u8 voq = VOQ(p_params->port_id, p_params->pq_params[i].tc_id,
- p_params->max_phys_tcs_per_port);
-
+ ext_voq = qed_get_ext_voq(p_hwfn,
+ p_params->port_id,
+ pq_params[i].tc_id,
+ p_params->max_phys_tcs_per_port);
+ crd_reg_offset =
+ (p_params->pf_id < MAX_NUM_PFS_BB ?
+ QM_REG_WFQPFCRD_RT_OFFSET :
+ QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
+ ext_voq * MAX_NUM_PFS_BB +
+ (p_params->pf_id % MAX_NUM_PFS_BB);
OVERWRITE_RT_REG(p_hwfn,
- crd_reg_offset + voq * MAX_NUM_PFS_BB,
- QM_WFQ_CRD_REG_SIGN_BIT);
+ crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
}
STORE_RT_REG(p_hwfn,
QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id,
- QM_WFQ_UPPER_BOUND | QM_WFQ_CRD_REG_SIGN_BIT);
+ QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id,
inc_val);
+
return 0;
}
@@ -501,15 +647,19 @@ static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
{
u32 inc_val = QM_RL_INC_VAL(pf_rl);
- if (inc_val > QM_RL_MAX_INC_VAL) {
+ if (inc_val > QM_PF_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
return -1;
}
- STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
- QM_RL_CRD_REG_SIGN_BIT);
- STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
- QM_RL_UPPER_BOUND | QM_RL_CRD_REG_SIGN_BIT);
+
+ STORE_RT_REG(p_hwfn,
+ QM_REG_RLPFCRD_RT_OFFSET + pf_id,
+ (u32)QM_RL_CRD_REG_SIGN_BIT);
+ STORE_RT_REG(p_hwfn,
+ QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
+ QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
+
return 0;
}
@@ -520,12 +670,12 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
u8 num_vports,
struct init_qm_vport_params *vport_params)
{
+ u16 vport_pq_id;
u32 inc_val;
u8 tc, i;
/* Go over all PF VPORTs */
for (i = 0; i < num_vports; i++) {
-
if (!vport_params[i].vport_wfq)
continue;
@@ -536,17 +686,14 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
return -1;
}
- /* each VPORT can have several VPORT PQ IDs for
- * different TCs
- */
+ /* Each VPORT can have several VPORT PQ IDs for various TCs */
for (tc = 0; tc < NUM_OF_TCS; tc++) {
- u16 vport_pq_id = vport_params[i].first_tx_pq_id[tc];
-
+ vport_pq_id = vport_params[i].first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID) {
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPCRD_RT_OFFSET +
vport_pq_id,
- QM_WFQ_CRD_REG_SIGN_BIT);
+ (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPWEIGHT_RT_OFFSET +
vport_pq_id, inc_val);
@@ -557,12 +704,17 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
return 0;
}
+/* Prepare VPORT RL runtime init values for the specified VPORTs.
+ * Return -1 on error.
+ */
static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
u8 start_vport,
u8 num_vports,
+ u32 link_speed,
struct init_qm_vport_params *vport_params)
{
u8 i, vport_id;
+ u32 inc_val;
if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
DP_NOTICE(p_hwfn,
@@ -572,22 +724,22 @@ static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
/* Go over all PF VPORTs */
for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
- u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
-
- if (inc_val > QM_RL_MAX_INC_VAL) {
+ inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl ?
+ vport_params[i].vport_rl :
+ link_speed);
+ if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
DP_NOTICE(p_hwfn,
"Invalid VPORT rate-limit configuration\n");
return -1;
}
- STORE_RT_REG(p_hwfn,
- QM_REG_RLGLBLCRD_RT_OFFSET + vport_id,
- QM_RL_CRD_REG_SIGN_BIT);
+ STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id,
+ (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id,
- QM_RL_UPPER_BOUND | QM_RL_CRD_REG_SIGN_BIT);
- STORE_RT_REG(p_hwfn,
- QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
+ QM_VP_RL_UPPER_BOUND(link_speed) |
+ (u32)QM_RL_CRD_REG_SIGN_BIT);
+ STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
inc_val);
}
@@ -599,7 +751,7 @@ static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn,
{
u32 reg_val, i;
- for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && reg_val == 0;
+ for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
i++) {
udelay(QM_STOP_CMD_POLL_PERIOD_US);
reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
@@ -632,8 +784,8 @@ static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn,
}
/******************** INTERFACE IMPLEMENTATION *********************/
-u32 qed_qm_pf_mem_size(u8 pf_id,
- u32 num_pf_cids,
+
+u32 qed_qm_pf_mem_size(u32 num_pf_cids,
u32 num_vf_cids,
u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs)
{
@@ -642,11 +794,10 @@ u32 qed_qm_pf_mem_size(u8 pf_id,
QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
}
-int qed_qm_common_rt_init(
- struct qed_hwfn *p_hwfn,
- struct qed_qm_common_rt_init_params *p_params)
+int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
+ struct qed_qm_common_rt_init_params *p_params)
{
- /* init AFullOprtnstcCrdMask */
+ /* Init AFullOprtnstcCrdMask */
u32 mask = (QM_OPPOR_LINE_VOQ_DEF <<
QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
(QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) |
@@ -664,18 +815,31 @@ int qed_qm_common_rt_init(
QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
+
+ /* Enable/disable PF RL */
qed_enable_pf_rl(p_hwfn, p_params->pf_rl_en);
+
+ /* Enable/disable PF WFQ */
qed_enable_pf_wfq(p_hwfn, p_params->pf_wfq_en);
+
+ /* Enable/disable VPORT RL */
qed_enable_vport_rl(p_hwfn, p_params->vport_rl_en);
+
+ /* Enable/disable VPORT WFQ */
qed_enable_vport_wfq(p_hwfn, p_params->vport_wfq_en);
+
+ /* Init PBF CMDQ line credit */
qed_cmdq_lines_rt_init(p_hwfn,
p_params->max_ports_per_engine,
p_params->max_phys_tcs_per_port,
p_params->port_params);
+
+ /* Init BTB blocks in PBF */
qed_btb_blocks_rt_init(p_hwfn,
p_params->max_ports_per_engine,
p_params->max_phys_tcs_per_port,
p_params->port_params);
+
return 0;
}
@@ -695,24 +859,31 @@ int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
/* Map Other PQs (if any) */
- qed_other_pq_map_rt_init(p_hwfn, p_params->port_id, p_params->pf_id,
- p_params->num_pf_cids, p_params->num_tids, 0);
+ qed_other_pq_map_rt_init(p_hwfn,
+ p_params->pf_id,
+ p_params->is_pf_loading, p_params->num_pf_cids,
+ p_params->num_tids, 0);
/* Map Tx PQs */
qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb);
+ /* Init PF WFQ */
if (p_params->pf_wfq)
if (qed_pf_wfq_rt_init(p_hwfn, p_params))
return -1;
+ /* Init PF RL */
if (qed_pf_rl_rt_init(p_hwfn, p_params->pf_id, p_params->pf_rl))
return -1;
+ /* Set VPORT WFQ */
if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params))
return -1;
+ /* Set VPORT RL */
if (qed_vport_rl_rt_init(p_hwfn, p_params->start_vport,
- p_params->num_vports, vport_params))
+ p_params->num_vports, p_params->link_speed,
+ vport_params))
return -1;
return 0;
@@ -729,6 +900,7 @@ int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
}
qed_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
+
return 0;
}
@@ -737,14 +909,13 @@ int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
{
u32 inc_val = QM_RL_INC_VAL(pf_rl);
- if (inc_val > QM_RL_MAX_INC_VAL) {
+ if (inc_val > QM_PF_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
return -1;
}
- qed_wr(p_hwfn, p_ptt,
- QM_REG_RLPFCRD + pf_id * 4,
- QM_RL_CRD_REG_SIGN_BIT);
+ qed_wr(p_hwfn,
+ p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
return 0;
@@ -767,33 +938,35 @@ int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
for (tc = 0; tc < NUM_OF_TCS; tc++) {
vport_pq_id = first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID)
- qed_wr(p_hwfn, p_ptt,
- QM_REG_WFQVPWEIGHT + vport_pq_id * 4,
- inc_val);
+ qed_wr(p_hwfn,
+ p_ptt,
+ QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
}
return 0;
}
int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl)
+ struct qed_ptt *p_ptt,
+ u8 vport_id, u32 vport_rl, u32 link_speed)
{
- u32 inc_val = QM_RL_INC_VAL(vport_rl);
+ u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
- if (vport_id >= MAX_QM_GLOBAL_RLS) {
+ if (vport_id >= max_qm_global_rls) {
DP_NOTICE(p_hwfn,
"Invalid VPORT ID for rate limiter configuration\n");
return -1;
}
- if (inc_val > QM_RL_MAX_INC_VAL) {
+ inc_val = QM_RL_INC_VAL(vport_rl ? vport_rl : link_speed);
+ if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
DP_NOTICE(p_hwfn, "Invalid VPORT rate-limit configuration\n");
return -1;
}
- qed_wr(p_hwfn, p_ptt,
- QM_REG_RLGLBLCRD + vport_id * 4,
- QM_RL_CRD_REG_SIGN_BIT);
+ qed_wr(p_hwfn,
+ p_ptt,
+ QM_REG_RLGLBLCRD + vport_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
return 0;
@@ -805,23 +978,27 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
bool is_tx_pq, u16 start_pq, u16 num_pqs)
{
u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
- u32 pq_mask = 0, last_pq = start_pq + num_pqs - 1, pq_id;
+ u32 pq_mask = 0, last_pq, pq_id;
+
+ last_pq = start_pq + num_pqs - 1;
/* Set command's PQ type */
QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
+ /* Go over requested PQs */
for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
/* Set PQ bit in mask (stop command only) */
if (!is_release_cmd)
- pq_mask |= (1 << (pq_id % QM_STOP_PQ_MASK_WIDTH));
+ pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH));
/* If last PQ or end of PQ mask, write command */
if ((pq_id == last_pq) ||
(pq_id % QM_STOP_PQ_MASK_WIDTH ==
(QM_STOP_PQ_MASK_WIDTH - 1))) {
- QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD,
- PAUSE_MASK, pq_mask);
- QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD,
+ QM_CMD_SET_FIELD(cmd_arr,
+ QM_STOP_CMD, PAUSE_MASK, pq_mask);
+ QM_CMD_SET_FIELD(cmd_arr,
+ QM_STOP_CMD,
GROUP_ID,
pq_id / QM_STOP_PQ_MASK_WIDTH);
if (!qed_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR,
@@ -834,87 +1011,103 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
return true;
}
-static void
-qed_set_tunnel_type_enable_bit(unsigned long *var, int bit, bool enable)
-{
- if (enable)
- set_bit(bit, var);
- else
- clear_bit(bit, var);
-}
+#define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
+ do { \
+ typeof(var) *__p_var = &(var); \
+ typeof(offset) __offset = offset; \
+ *__p_var = (*__p_var & ~BIT(__offset)) | \
+ ((enable) ? BIT(__offset) : 0); \
+ } while (0)
#define PRS_ETH_TUNN_FIC_FORMAT -188897008
void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u16 dest_port)
{
+ /* Update PRS register */
qed_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
+
+ /* Update NIG register */
qed_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
+
+ /* Update PBF register */
qed_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
}
void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, bool vxlan_enable)
{
- unsigned long reg_val = 0;
+ u32 reg_val;
u8 shift;
+ /* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, vxlan_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
-
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
- PRS_ETH_TUNN_FIC_FORMAT);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
+ (u32)PRS_ETH_TUNN_FIC_FORMAT);
+ /* Update NIG register */
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
shift = NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, vxlan_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN,
- vxlan_enable ? 1 : 0);
+ /* Update DORQ register */
+ qed_wr(p_hwfn,
+ p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0);
}
-void qed_set_gre_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
bool eth_gre_enable, bool ip_gre_enable)
{
- unsigned long reg_val = 0;
+ u32 reg_val;
u8 shift;
+ /* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, eth_gre_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, ip_gre_enable);
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
- PRS_ETH_TUNN_FIC_FORMAT);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
+ (u32)PRS_ETH_TUNN_FIC_FORMAT);
+ /* Update NIG register */
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
shift = NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, eth_gre_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
shift = NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, ip_gre_enable);
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN,
- eth_gre_enable ? 1 : 0);
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN,
- ip_gre_enable ? 1 : 0);
+ /* Update DORQ registers */
+ qed_wr(p_hwfn,
+ p_ptt,
+ DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0);
+ qed_wr(p_hwfn,
+ p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0);
}
void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u16 dest_port)
{
+ /* Update PRS register */
qed_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
+
+ /* Update NIG register */
qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
+
+ /* Update PBF register */
qed_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
}
@@ -922,32 +1115,39 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
bool eth_geneve_enable, bool ip_geneve_enable)
{
- unsigned long reg_val = 0;
+ u32 reg_val;
u8 shift;
+ /* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, eth_geneve_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT;
- qed_set_tunnel_type_enable_bit(®_val, shift, ip_geneve_enable);
-
+ SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val)
- qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
- PRS_ETH_TUNN_FIC_FORMAT);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
+ (u32)PRS_ETH_TUNN_FIC_FORMAT);
+ /* Update NIG register */
qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
eth_geneve_enable ? 1 : 0);
qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0);
- /* EDPM with geneve tunnel not supported in BB_B0 */
+ /* EDPM with geneve tunnel not supported in BB */
if (QED_IS_BB_B0(p_hwfn->cdev))
return;
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN,
+ /* Update DORQ registers */
+ qed_wr(p_hwfn,
+ p_ptt,
+ DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
eth_geneve_enable ? 1 : 0);
- qed_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN,
+ qed_wr(p_hwfn,
+ p_ptt,
+ DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
ip_geneve_enable ? 1 : 0);
}
@@ -959,117 +1159,297 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
#define RAM_LINE_SIZE sizeof(u64)
#define REG_SIZE sizeof(u32)
-void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt, u16 pf_id)
+void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id)
{
- u32 hw_addr = PRS_REG_GFT_PROFILE_MASK_RAM +
- pf_id * RAM_LINE_SIZE;
-
- /*stop using gft logic */
+ /* Disable gft search for PF */
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
- qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, 0x0);
+
+ /* Clean ram & cam for next gft session */
+
+ /* Zero camline */
qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
- qed_wr(p_hwfn, p_ptt, hw_addr, 0);
- qed_wr(p_hwfn, p_ptt, hw_addr + 4, 0);
+
+ /* Zero ramline */
+ qed_wr(p_hwfn,
+ p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, 0);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + REG_SIZE,
+ 0);
}
-void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
- u16 pf_id, bool tcp, bool udp,
- bool ipv4, bool ipv6)
+void qed_set_gft_event_id_cm_hdr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
- union gft_cam_line_union camline;
- struct gft_ram_line ramline;
u32 rfs_cm_hdr_event_id;
+ /* Set RFS event ID to be awakened i Tstorm By Prs */
rfs_cm_hdr_event_id = qed_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
+ rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID <<
+ PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
+ rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR <<
+ PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
+ qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
+}
+
+void qed_gft_config(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ u16 pf_id,
+ bool tcp,
+ bool udp,
+ bool ipv4, bool ipv6, enum gft_profile_type profile_type)
+{
+ u32 reg_val, cam_line, ram_line_lo, ram_line_hi;
if (!ipv6 && !ipv4)
DP_NOTICE(p_hwfn,
- "set_rfs_mode_enable: must accept at least on of - ipv4 or ipv6");
+ "gft_config: must accept at least on of - ipv4 or ipv6'\n");
if (!tcp && !udp)
DP_NOTICE(p_hwfn,
- "set_rfs_mode_enable: must accept at least on of - udp or tcp");
+ "gft_config: must accept at least on of - udp or tcp\n");
+ if (profile_type >= MAX_GFT_PROFILE_TYPE)
+ DP_NOTICE(p_hwfn, "gft_config: unsupported gft_profile_type\n");
- rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID <<
- PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
- rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR <<
- PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
- qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
+ /* Set RFS event ID to be awakened i Tstorm By Prs */
+ reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
+ PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
+ reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
+ qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
- /* Configure Registers for RFS mode */
- qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
+ /* Do not load context only cid in PRS on match. */
qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
- camline.cam_line_mapped.camline = 0;
- /* Cam line is now valid!! */
- SET_FIELD(camline.cam_line_mapped.camline,
- GFT_CAM_LINE_MAPPED_VALID, 1);
+ /* Do not use tenant ID exist bit for gft search */
+ qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
+
+ /* Set Cam */
+ cam_line = 0;
+ SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
- /* filters are per PF!! */
- SET_FIELD(camline.cam_line_mapped.camline,
+ /* Filters are per PF!! */
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_PF_ID_MASK,
GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
- SET_FIELD(camline.cam_line_mapped.camline,
- GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
+ SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
+
if (!(tcp && udp)) {
- SET_FIELD(camline.cam_line_mapped.camline,
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
if (tcp)
- SET_FIELD(camline.cam_line_mapped.camline,
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_TCP_PROTOCOL);
else
- SET_FIELD(camline.cam_line_mapped.camline,
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_UDP_PROTOCOL);
}
if (!(ipv4 && ipv6)) {
- SET_FIELD(camline.cam_line_mapped.camline,
- GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
+ SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
if (ipv4)
- SET_FIELD(camline.cam_line_mapped.camline,
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV4);
else
- SET_FIELD(camline.cam_line_mapped.camline,
+ SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV6);
}
/* Write characteristics to cam */
qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
- camline.cam_line_mapped.camline);
- camline.cam_line_mapped.camline = qed_rd(p_hwfn, p_ptt,
- PRS_REG_GFT_CAM +
- CAM_LINE_SIZE * pf_id);
+ cam_line);
+ cam_line =
+ qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
/* Write line to RAM - compare to filter 4 tuple */
- ramline.lo = 0;
- ramline.hi = 0;
- SET_FIELD(ramline.hi, GFT_RAM_LINE_DST_IP, 1);
- SET_FIELD(ramline.hi, GFT_RAM_LINE_SRC_IP, 1);
- SET_FIELD(ramline.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
- SET_FIELD(ramline.lo, GFT_RAM_LINE_ETHERTYPE, 1);
- SET_FIELD(ramline.lo, GFT_RAM_LINE_SRC_PORT, 1);
- SET_FIELD(ramline.lo, GFT_RAM_LINE_DST_PORT, 1);
-
- /* Each iteration write to reg */
- qed_wr(p_hwfn, p_ptt,
+ ram_line_lo = 0;
+ ram_line_hi = 0;
+
+ if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
+ SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
+ SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1);
+ SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_SRC_PORT, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
+ } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
+ SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
+ } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_PORT) {
+ SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
+ SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
+ }
+
+ qed_wr(p_hwfn,
+ p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
- ramline.lo);
- qed_wr(p_hwfn, p_ptt,
- PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + 4,
- ramline.hi);
+ ram_line_lo);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + REG_SIZE,
+ ram_line_hi);
/* Set default profile so that no filter match will happen */
- qed_wr(p_hwfn, p_ptt,
- PRS_REG_GFT_PROFILE_MASK_RAM +
- RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH,
- ramline.lo);
- qed_wr(p_hwfn, p_ptt,
- PRS_REG_GFT_PROFILE_MASK_RAM +
- RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH + 4,
- ramline.hi);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
+ PRS_GFT_CAM_LINES_NO_MATCH, 0xffffffff);
+ qed_wr(p_hwfn,
+ p_ptt,
+ PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
+ PRS_GFT_CAM_LINES_NO_MATCH + REG_SIZE, 0x3ff);
+
+ /* Enable gft search */
+ qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
+}
+
+DECLARE_CRC8_TABLE(cdu_crc8_table);
+
+/* Calculate and return CDU validation byte per connection type/region/cid */
+static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid)
+{
+ const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
+ u8 crc, validation_byte = 0;
+ static u8 crc8_table_valid; /* automatically initialized to 0 */
+ u32 validation_string = 0;
+ u32 data_to_crc;
+
+ if (!crc8_table_valid) {
+ crc8_populate_msb(cdu_crc8_table, 0x07);
+ crc8_table_valid = 1;
+ }
+
+ /* The CRC is calculated on the String-to-compress:
+ * [31:8] = {CID[31:20],CID[11:0]}
+ * [7:4] = Region
+ * [3:0] = Type
+ */
+ if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
+ validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
+
+ if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
+ validation_string |= ((region & 0xF) << 4);
+
+ if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
+ validation_string |= (conn_type & 0xF);
+
+ /* Convert to big-endian and calculate CRC8 */
+ data_to_crc = be32_to_cpu(validation_string);
+
+ crc = crc8(cdu_crc8_table,
+ (u8 *)&data_to_crc, sizeof(data_to_crc), CRC8_INIT_VALUE);
+
+ /* The validation byte [7:0] is composed:
+ * for type A validation
+ * [7] = active configuration bit
+ * [6:0] = crc[6:0]
+ *
+ * for type B validation
+ * [7] = active configuration bit
+ * [6:3] = connection_type[3:0]
+ * [2:0] = crc[2:0]
+ */
+ validation_byte |=
+ ((validation_cfg >>
+ CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
+
+ if ((validation_cfg >>
+ CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
+ validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
+ else
+ validation_byte |= crc & 0x7F;
+
+ return validation_byte;
+}
+
+/* Calcualte and set validation bytes for session context */
+void qed_calc_session_ctx_validation(void *p_ctx_mem,
+ u16 ctx_size, u8 ctx_type, u32 cid)
+{
+ u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
+
+ p_ctx = (u8 * const)p_ctx_mem;
+ x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
+ t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
+ u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
+
+ memset(p_ctx, 0, ctx_size);
+
+ *x_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 3, cid);
+ *t_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 4, cid);
+ *u_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 5, cid);
+}
+
+/* Calcualte and set validation bytes for task context */
+void qed_calc_task_ctx_validation(void *p_ctx_mem,
+ u16 ctx_size, u8 ctx_type, u32 tid)
+{
+ u8 *p_ctx, *region1_val_ptr;
+
+ p_ctx = (u8 * const)p_ctx_mem;
+ region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
+
+ memset(p_ctx, 0, ctx_size);
+
+ *region1_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 1, tid);
+}
+
+/* Memset session context to 0 while preserving validation bytes */
+void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
+{
+ u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
+ u8 x_val, t_val, u_val;
+
+ p_ctx = (u8 * const)p_ctx_mem;
+ x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
+ t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
+ u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
+
+ x_val = *x_val_ptr;
+ t_val = *t_val_ptr;
+ u_val = *u_val_ptr;
+
+ memset(p_ctx, 0, ctx_size);
+
+ *x_val_ptr = x_val;
+ *t_val_ptr = t_val;
+ *u_val_ptr = u_val;
+}
+
+/* Memset task context to 0 while preserving validation bytes */
+void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
+{
+ u8 *p_ctx, *region1_val_ptr;
+ u8 region1_val;
+
+ p_ctx = (u8 * const)p_ctx_mem;
+ region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
+
+ region1_val = *region1_val_ptr;
+
+ memset(p_ctx, 0, ctx_size);
+
+ *region1_val_ptr = region1_val;
+}
+
+/* Enable and configure context validation */
+void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt)
+{
+ u32 ctx_validation;
+
+ /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
+ ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
+ qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
+
+ /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
+ ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
+ qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
+
+ /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
+ ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
+ qed_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_init_ops.c b/drivers/net/ethernet/qlogic/qed/qed_init_ops.c
index e3f3688..3bb76da 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_init_ops.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_init_ops.c
@@ -414,11 +414,23 @@ static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
}
/* init_ops callbacks entry point */
-static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
- struct qed_ptt *p_ptt,
- struct init_callback_op *p_cmd)
+static int qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ struct init_callback_op *p_cmd)
{
- DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n");
+ int rc;
+
+ switch (p_cmd->callback_id) {
+ case DMAE_READY_CB:
+ rc = qed_dmae_sanity(p_hwfn, p_ptt, "engine_phase");
+ break;
+ default:
+ DP_NOTICE(p_hwfn, "Unexpected init op callback ID %d\n",
+ p_cmd->callback_id);
+ return -EINVAL;
+ }
+
+ return rc;
}
static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
@@ -519,7 +531,7 @@ int qed_init_run(struct qed_hwfn *p_hwfn,
break;
case INIT_OP_CALLBACK:
- qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
+ rc = qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
break;
}
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c
index 719cdbf..d3eabcf 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.c
@@ -59,10 +59,10 @@ struct qed_pi_info {
};
struct qed_sb_sp_info {
- struct qed_sb_info sb_info;
+ struct qed_sb_info sb_info;
/* per protocol index data */
- struct qed_pi_info pi_info_arr[PIS_PER_SB];
+ struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
};
enum qed_attention_type {
@@ -82,7 +82,7 @@ struct aeu_invert_reg_bit {
#define ATTENTION_LENGTH_SHIFT (4)
#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
ATTENTION_LENGTH_SHIFT)
-#define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT)
+#define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
ATTENTION_PARITY)
@@ -1313,7 +1313,7 @@ static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
if (IS_VF(p_hwfn->cdev))
return;
- sb_offset = igu_sb_id * PIS_PER_SB;
+ sb_offset = igu_sb_id * PIS_PER_SB_E4;
memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.h b/drivers/net/ethernet/qlogic/qed/qed_int.h
index 5199634..54b4ee0 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_int.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_int.h
@@ -197,7 +197,7 @@ void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
#define QED_SB_EVENT_MASK 0x0003
#define SB_ALIGNED_SIZE(p_hwfn) \
- ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
+ ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
#define QED_SB_INVALID_IDX 0xffff
diff --git a/drivers/net/ethernet/qlogic/qed/qed_iscsi.c b/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
index 813c77c..c0d4a54 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_iscsi.c
@@ -62,22 +62,6 @@
#include "qed_sriov.h"
#include "qed_reg_addr.h"
-static int
-qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
- u8 fw_event_code,
- u16 echo, union event_ring_data *data, u8 fw_return_code)
-{
- if (p_hwfn->p_iscsi_info->event_cb) {
- struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
-
- return p_iscsi->event_cb(p_iscsi->event_context,
- fw_event_code, data);
- } else {
- DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
- return -EINVAL;
- }
-}
-
struct qed_iscsi_conn {
struct list_head list_entry;
bool free_on_delete;
@@ -105,7 +89,7 @@ struct qed_iscsi_conn {
u8 local_mac[6];
u8 remote_mac[6];
u16 vlan_id;
- u8 tcp_flags;
+ u16 tcp_flags;
u8 ip_version;
u32 remote_ip[4];
u32 local_ip[4];
@@ -122,7 +106,6 @@ struct qed_iscsi_conn {
u32 ss_thresh;
u16 srtt;
u16 rtt_var;
- u32 ts_time;
u32 ts_recent;
u32 ts_recent_age;
u32 total_rt;
@@ -144,7 +127,6 @@ struct qed_iscsi_conn {
u16 mss;
u8 snd_wnd_scale;
u8 rcv_wnd_scale;
- u32 ts_ticks_per_second;
u16 da_timeout_value;
u8 ack_frequency;
@@ -162,6 +144,22 @@ struct qed_iscsi_conn {
};
static int
+qed_iscsi_async_event(struct qed_hwfn *p_hwfn,
+ u8 fw_event_code,
+ u16 echo, union event_ring_data *data, u8 fw_return_code)
+{
+ if (p_hwfn->p_iscsi_info->event_cb) {
+ struct qed_iscsi_info *p_iscsi = p_hwfn->p_iscsi_info;
+
+ return p_iscsi->event_cb(p_iscsi->event_context,
+ fw_event_code, data);
+ } else {
+ DP_NOTICE(p_hwfn, "iSCSI async completion is not set\n");
+ return -EINVAL;
+ }
+}
+
+static int
qed_sp_iscsi_func_start(struct qed_hwfn *p_hwfn,
enum spq_mode comp_mode,
struct qed_spq_comp_cb *p_comp_addr,
@@ -214,9 +212,9 @@ struct qed_iscsi_conn {
p_init->num_sq_pages_in_ring = p_params->num_sq_pages_in_ring;
p_init->num_r2tq_pages_in_ring = p_params->num_r2tq_pages_in_ring;
p_init->num_uhq_pages_in_ring = p_params->num_uhq_pages_in_ring;
- p_init->ooo_enable = p_params->ooo_enable;
p_init->ll2_rx_queue_id = p_hwfn->hw_info.resc_start[QED_LL2_QUEUE] +
p_params->ll2_ooo_queue_id;
+
p_init->func_params.log_page_size = p_params->log_page_size;
val = p_params->num_tasks;
p_init->func_params.num_tasks = cpu_to_le16(val);
@@ -276,7 +274,7 @@ struct qed_iscsi_conn {
p_ramrod->tcp_init.two_msl_timer = cpu_to_le32(p_params->two_msl_timer);
val = p_params->tx_sws_timer;
p_ramrod->tcp_init.tx_sws_timer = cpu_to_le16(val);
- p_ramrod->tcp_init.maxfinrt = p_params->max_fin_rt;
+ p_ramrod->tcp_init.max_fin_rt = p_params->max_fin_rt;
p_hwfn->p_iscsi_info->event_context = event_context;
p_hwfn->p_iscsi_info->event_cb = async_event_cb;
@@ -304,8 +302,8 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
int rc = 0;
u32 dval;
u16 wval;
- u8 i;
u16 *p;
+ u8 i;
/* Get SPQ entry */
memset(&init_data, 0, sizeof(init_data));
@@ -371,7 +369,7 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
p_tcp->vlan_id = cpu_to_le16(p_conn->vlan_id);
- p_tcp->flags = p_conn->tcp_flags;
+ p_tcp->flags = cpu_to_le16(p_conn->tcp_flags);
p_tcp->ip_version = p_conn->ip_version;
for (i = 0; i < 4; i++) {
dval = p_conn->remote_ip[i];
@@ -436,7 +434,7 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
p_tcp2->remote_mac_addr_lo = swab16(get_unaligned(p + 2));
p_tcp2->vlan_id = cpu_to_le16(p_conn->vlan_id);
- p_tcp2->flags = p_conn->tcp_flags;
+ p_tcp2->flags = cpu_to_le16(p_conn->tcp_flags);
p_tcp2->ip_version = p_conn->ip_version;
for (i = 0; i < 4; i++) {
@@ -458,6 +456,11 @@ static int qed_sp_iscsi_conn_offload(struct qed_hwfn *p_hwfn,
p_tcp2->syn_ip_payload_length = cpu_to_le16(wval);
p_tcp2->syn_phy_addr_lo = DMA_LO_LE(p_conn->syn_phy_addr);
p_tcp2->syn_phy_addr_hi = DMA_HI_LE(p_conn->syn_phy_addr);
+ p_tcp2->cwnd = cpu_to_le32(p_conn->cwnd);
+ p_tcp2->ka_max_probe_cnt = p_conn->ka_probe_cnt;
+ p_tcp2->ka_timeout = cpu_to_le32(p_conn->ka_timeout);
+ p_tcp2->max_rt_time = cpu_to_le32(p_conn->max_rt_time);
+ p_tcp2->ka_interval = cpu_to_le32(p_conn->ka_interval);
}
return qed_spq_post(p_hwfn, p_ent, NULL);
@@ -692,8 +695,7 @@ static void __iomem *qed_iscsi_get_secondary_bdq_prod(struct qed_hwfn *p_hwfn,
}
}
-static int qed_iscsi_setup_connection(struct qed_hwfn *p_hwfn,
- struct qed_iscsi_conn *p_conn)
+static int qed_iscsi_setup_connection(struct qed_iscsi_conn *p_conn)
{
if (!p_conn->queue_cnts_virt_addr)
goto nomem;
@@ -844,7 +846,7 @@ static int qed_iscsi_acquire_connection(struct qed_hwfn *p_hwfn,
rc = qed_iscsi_allocate_connection(p_hwfn, &p_conn);
if (!rc)
- rc = qed_iscsi_setup_connection(p_hwfn, p_conn);
+ rc = qed_iscsi_setup_connection(p_conn);
if (rc) {
spin_lock_bh(&p_hwfn->p_iscsi_info->lock);
@@ -1294,7 +1296,6 @@ static int qed_iscsi_offload_conn(struct qed_dev *cdev,
con->ss_thresh = conn_info->ss_thresh;
con->srtt = conn_info->srtt;
con->rtt_var = conn_info->rtt_var;
- con->ts_time = conn_info->ts_time;
con->ts_recent = conn_info->ts_recent;
con->ts_recent_age = conn_info->ts_recent_age;
con->total_rt = conn_info->total_rt;
@@ -1316,7 +1317,6 @@ static int qed_iscsi_offload_conn(struct qed_dev *cdev,
con->mss = conn_info->mss;
con->snd_wnd_scale = conn_info->snd_wnd_scale;
con->rcv_wnd_scale = conn_info->rcv_wnd_scale;
- con->ts_ticks_per_second = conn_info->ts_ticks_per_second;
con->da_timeout_value = conn_info->da_timeout_value;
con->ack_frequency = conn_info->ack_frequency;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_iwarp.c b/drivers/net/ethernet/qlogic/qed/qed_iwarp.c
index 409041e..4290848 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_iwarp.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_iwarp.c
@@ -64,14 +64,21 @@ struct mpa_v2_hdr {
#define QED_IWARP_INVALID_TCP_CID 0xffffffff
#define QED_IWARP_RCV_WND_SIZE_DEF (256 * 1024)
-#define QED_IWARP_RCV_WND_SIZE_MIN (64 * 1024)
+#define QED_IWARP_RCV_WND_SIZE_MIN (0xffff)
#define TIMESTAMP_HEADER_SIZE (12)
+#define QED_IWARP_MAX_FIN_RT_DEFAULT (2)
#define QED_IWARP_TS_EN BIT(0)
#define QED_IWARP_DA_EN BIT(1)
#define QED_IWARP_PARAM_CRC_NEEDED (1)
#define QED_IWARP_PARAM_P2P (1)
+#define QED_IWARP_DEF_MAX_RT_TIME (0)
+#define QED_IWARP_DEF_CWND_FACTOR (4)
+#define QED_IWARP_DEF_KA_MAX_PROBE_CNT (5)
+#define QED_IWARP_DEF_KA_TIMEOUT (1200000) /* 20 min */
+#define QED_IWARP_DEF_KA_INTERVAL (1000) /* 1 sec */
+
static int qed_iwarp_async_event(struct qed_hwfn *p_hwfn,
u8 fw_event_code, u16 echo,
union event_ring_data *data,
@@ -120,11 +127,17 @@ static void qed_iwarp_cid_cleaned(struct qed_hwfn *p_hwfn, u32 cid)
spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
}
-void qed_iwarp_init_fw_ramrod(struct qed_hwfn *p_hwfn,
- struct iwarp_init_func_params *p_ramrod)
+void
+qed_iwarp_init_fw_ramrod(struct qed_hwfn *p_hwfn,
+ struct iwarp_init_func_ramrod_data *p_ramrod)
{
- p_ramrod->ll2_ooo_q_index = RESC_START(p_hwfn, QED_LL2_QUEUE) +
- p_hwfn->p_rdma_info->iwarp.ll2_ooo_handle;
+ p_ramrod->iwarp.ll2_ooo_q_index =
+ RESC_START(p_hwfn, QED_LL2_QUEUE) +
+ p_hwfn->p_rdma_info->iwarp.ll2_ooo_handle;
+
+ p_ramrod->tcp.max_fin_rt = QED_IWARP_MAX_FIN_RT_DEFAULT;
+
+ return;
}
static int qed_iwarp_alloc_cid(struct qed_hwfn *p_hwfn, u32 *cid)
@@ -699,6 +712,12 @@ int qed_iwarp_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
tcp->ttl = 0x40;
tcp->tos_or_tc = 0;
+ tcp->max_rt_time = QED_IWARP_DEF_MAX_RT_TIME;
+ tcp->cwnd = QED_IWARP_DEF_CWND_FACTOR * tcp->mss;
+ tcp->ka_max_probe_cnt = QED_IWARP_DEF_KA_MAX_PROBE_CNT;
+ tcp->ka_timeout = QED_IWARP_DEF_KA_TIMEOUT;
+ tcp->ka_interval = QED_IWARP_DEF_KA_INTERVAL;
+
tcp->rcv_wnd_scale = (u8)p_hwfn->p_rdma_info->iwarp.rcv_wnd_scale;
tcp->connect_mode = ep->connect_mode;
@@ -807,6 +826,7 @@ int qed_iwarp_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
qed_iwarp_mpa_offload(struct qed_hwfn *p_hwfn, struct qed_iwarp_ep *ep)
{
struct iwarp_mpa_offload_ramrod_data *p_mpa_ramrod;
+ struct qed_iwarp_info *iwarp_info;
struct qed_sp_init_data init_data;
dma_addr_t async_output_phys;
struct qed_spq_entry *p_ent;
@@ -874,6 +894,8 @@ int qed_iwarp_destroy_qp(struct qed_hwfn *p_hwfn, struct qed_rdma_qp *qp)
p_mpa_ramrod->common.reject = 1;
}
+ iwarp_info = &p_hwfn->p_rdma_info->iwarp;
+ p_mpa_ramrod->rcv_wnd = iwarp_info->rcv_wnd_size;
p_mpa_ramrod->mode = ep->mpa_rev;
SET_FIELD(p_mpa_ramrod->rtr_pref,
IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED, ep->rtr_type);
@@ -2745,6 +2767,7 @@ int qed_iwarp_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
/* value 0 is used for ilog2(QED_IWARP_RCV_WND_SIZE_MIN) */
iwarp_info->rcv_wnd_scale = ilog2(rcv_wnd_size) -
ilog2(QED_IWARP_RCV_WND_SIZE_MIN);
+ iwarp_info->rcv_wnd_size = rcv_wnd_size >> iwarp_info->rcv_wnd_scale;
iwarp_info->crc_needed = QED_IWARP_PARAM_CRC_NEEDED;
iwarp_info->mpa_rev = MPA_NEGOTIATION_TYPE_ENHANCED;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_iwarp.h b/drivers/net/ethernet/qlogic/qed/qed_iwarp.h
index c1ecd74..b8f612d 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_iwarp.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_iwarp.h
@@ -95,6 +95,7 @@ struct qed_iwarp_info {
spinlock_t iw_lock; /* for iwarp resources */
spinlock_t qp_lock; /* for teardown races */
u32 rcv_wnd_scale;
+ u16 rcv_wnd_size;
u16 max_mtu;
u8 mac_addr[ETH_ALEN];
u8 crc_needed;
@@ -187,7 +188,7 @@ int qed_iwarp_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
struct qed_rdma_start_in_params *params);
void qed_iwarp_init_fw_ramrod(struct qed_hwfn *p_hwfn,
- struct iwarp_init_func_params *p_ramrod);
+ struct iwarp_init_func_ramrod_data *p_ramrod);
int qed_iwarp_stop(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_l2.c b/drivers/net/ethernet/qlogic/qed/qed_l2.c
index 0853389..59ecc1e 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_l2.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_l2.c
@@ -1969,33 +1969,45 @@ void qed_reset_vport_stats(struct qed_dev *cdev)
_qed_get_vport_stats(cdev, cdev->reset_stats);
}
-static void
-qed_arfs_mode_configure(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
- struct qed_arfs_config_params *p_cfg_params)
-{
- if (p_cfg_params->arfs_enable) {
- qed_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
- p_cfg_params->tcp, p_cfg_params->udp,
- p_cfg_params->ipv4, p_cfg_params->ipv6);
- DP_VERBOSE(p_hwfn, QED_MSG_SP,
- "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
+static enum gft_profile_type
+qed_arfs_mode_to_hsi(enum qed_filter_config_mode mode)
+{
+ if (mode == QED_FILTER_CONFIG_MODE_5_TUPLE)
+ return GFT_PROFILE_TYPE_4_TUPLE;
+ if (mode == QED_FILTER_CONFIG_MODE_IP_DEST)
+ return GFT_PROFILE_TYPE_IP_DST_PORT;
+ return GFT_PROFILE_TYPE_L4_DST_PORT;
+}
+
+void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ struct qed_arfs_config_params *p_cfg_params)
+{
+ if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) {
+ qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
+ p_cfg_params->tcp,
+ p_cfg_params->udp,
+ p_cfg_params->ipv4,
+ p_cfg_params->ipv6,
+ qed_arfs_mode_to_hsi(p_cfg_params->mode));
+ DP_VERBOSE(p_hwfn,
+ QED_MSG_SP,
+ "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n",
p_cfg_params->tcp ? "Enable" : "Disable",
p_cfg_params->udp ? "Enable" : "Disable",
p_cfg_params->ipv4 ? "Enable" : "Disable",
- p_cfg_params->ipv6 ? "Enable" : "Disable");
+ p_cfg_params->ipv6 ? "Enable" : "Disable",
+ (u32)p_cfg_params->mode);
} else {
- qed_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
+ DP_VERBOSE(p_hwfn, QED_MSG_SP, "Disabled Filtering\n");
+ qed_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
}
-
- DP_VERBOSE(p_hwfn, QED_MSG_SP, "Configured ARFS mode : %s\n",
- p_cfg_params->arfs_enable ? "Enable" : "Disable");
}
-static int
-qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
+int
+qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
struct qed_spq_comp_cb *p_cb,
- dma_addr_t p_addr, u16 length, u16 qid,
- u8 vport_id, bool b_is_add)
+ struct qed_ntuple_filter_params *p_params)
{
struct rx_update_gft_filter_data *p_ramrod = NULL;
struct qed_spq_entry *p_ent = NULL;
@@ -2004,13 +2016,15 @@ void qed_reset_vport_stats(struct qed_dev *cdev)
u8 abs_vport_id = 0;
int rc = -EINVAL;
- rc = qed_fw_vport(p_hwfn, vport_id, &abs_vport_id);
+ rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
if (rc)
return rc;
- rc = qed_fw_l2_queue(p_hwfn, qid, &abs_rx_q_id);
- if (rc)
- return rc;
+ if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) {
+ rc = qed_fw_l2_queue(p_hwfn, p_params->qid, &abs_rx_q_id);
+ if (rc)
+ return rc;
+ }
/* Get SPQ entry */
memset(&init_data, 0, sizeof(init_data));
@@ -2032,17 +2046,27 @@ void qed_reset_vport_stats(struct qed_dev *cdev)
return rc;
p_ramrod = &p_ent->ramrod.rx_update_gft;
- DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
- p_ramrod->pkt_hdr_length = cpu_to_le16(length);
- p_ramrod->rx_qid_or_action_icid = cpu_to_le16(abs_rx_q_id);
- p_ramrod->vport_id = abs_vport_id;
- p_ramrod->filter_type = RFS_FILTER_TYPE;
- p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER : GFT_DELETE_FILTER;
+
+ DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr);
+ p_ramrod->pkt_hdr_length = cpu_to_le16(p_params->length);
+
+ if (p_params->qid != QED_RFS_NTUPLE_QID_RSS) {
+ p_ramrod->rx_qid_valid = 1;
+ p_ramrod->rx_qid = cpu_to_le16(abs_rx_q_id);
+ }
+
+ p_ramrod->flow_id_valid = 0;
+ p_ramrod->flow_id = 0;
+
+ p_ramrod->vport_id = cpu_to_le16((u16)abs_vport_id);
+ p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER
+ : GFT_DELETE_FILTER;
DP_VERBOSE(p_hwfn, QED_MSG_SP,
"V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n",
abs_vport_id, abs_rx_q_id,
- b_is_add ? "Adding" : "Removing", (u64)p_addr, length);
+ p_params->b_is_add ? "Adding" : "Removing",
+ (u64)p_params->addr, p_params->length);
return qed_spq_post(p_hwfn, p_ent, NULL);
}
@@ -2743,7 +2767,8 @@ static int qed_configure_filter(struct qed_dev *cdev,
}
}
-static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
+static int qed_configure_arfs_searcher(struct qed_dev *cdev,
+ enum qed_filter_config_mode mode)
{
struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
struct qed_arfs_config_params arfs_config_params;
@@ -2753,8 +2778,7 @@ static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
arfs_config_params.udp = true;
arfs_config_params.ipv4 = true;
arfs_config_params.ipv6 = true;
- arfs_config_params.arfs_enable = en_searcher;
-
+ arfs_config_params.mode = mode;
qed_arfs_mode_configure(p_hwfn, p_hwfn->p_arfs_ptt,
&arfs_config_params);
return 0;
@@ -2762,8 +2786,8 @@ static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
static void
qed_arfs_sp_response_handler(struct qed_hwfn *p_hwfn,
- void *cookie, union event_ring_data *data,
- u8 fw_return_code)
+ void *cookie,
+ union event_ring_data *data, u8 fw_return_code)
{
struct qed_common_cb_ops *op = p_hwfn->cdev->protocol_ops.common;
void *dev = p_hwfn->cdev->ops_cookie;
@@ -2771,10 +2795,10 @@ static int qed_configure_arfs_searcher(struct qed_dev *cdev, bool en_searcher)
op->arfs_filter_op(dev, cookie, fw_return_code);
}
-static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
- dma_addr_t mapping, u16 length,
- u16 vport_id, u16 rx_queue_id,
- bool add_filter)
+static int
+qed_ntuple_arfs_filter_config(struct qed_dev *cdev,
+ void *cookie,
+ struct qed_ntuple_filter_params *params)
{
struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
struct qed_spq_comp_cb cb;
@@ -2783,9 +2807,19 @@ static int qed_ntuple_arfs_filter_config(struct qed_dev *cdev, void *cookie,
cb.function = qed_arfs_sp_response_handler;
cb.cookie = cookie;
- rc = qed_configure_rfs_ntuple_filter(p_hwfn, p_hwfn->p_arfs_ptt,
- &cb, mapping, length, rx_queue_id,
- vport_id, add_filter);
+ if (params->b_is_vf) {
+ if (!qed_iov_is_valid_vfid(p_hwfn, params->vf_id, false,
+ false)) {
+ DP_INFO(p_hwfn, "vfid 0x%02x is out of bounds\n",
+ params->vf_id);
+ return rc;
+ }
+
+ params->vport_id = params->vf_id + 1;
+ params->qid = QED_RFS_NTUPLE_QID_RSS;
+ }
+
+ rc = qed_configure_rfs_ntuple_filter(p_hwfn, &cb, params);
if (rc)
DP_NOTICE(p_hwfn,
"Failed to issue a-RFS filter configuration\n");
diff --git a/drivers/net/ethernet/qlogic/qed/qed_l2.h b/drivers/net/ethernet/qlogic/qed/qed_l2.h
index cc1f248..c4030e9 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_l2.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_l2.h
@@ -190,7 +190,7 @@ struct qed_arfs_config_params {
bool udp;
bool ipv4;
bool ipv6;
- bool arfs_enable;
+ enum qed_filter_config_mode mode;
};
struct qed_sp_vport_update_params {
@@ -277,6 +277,37 @@ int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
void qed_reset_vport_stats(struct qed_dev *cdev);
+/**
+ * *@brief qed_arfs_mode_configure -
+ *
+ **Enable or disable rfs mode. It must accept atleast one of tcp or udp true
+ **and atleast one of ipv4 or ipv6 true to enable rfs mode.
+ *
+ **@param p_hwfn
+ **@param p_ptt
+ **@param p_cfg_params - arfs mode configuration parameters.
+ *
+ */
+void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
+ struct qed_ptt *p_ptt,
+ struct qed_arfs_config_params *p_cfg_params);
+
+/**
+ * @brief - qed_configure_rfs_ntuple_filter
+ *
+ * This ramrod should be used to add or remove arfs hw filter
+ *
+ * @params p_hwfn
+ * @params p_cb - Used for QED_SPQ_MODE_CB,where client would initialize
+ * it with cookie and callback function address, if not
+ * using this mode then client must pass NULL.
+ * @params p_params
+ */
+int
+qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
+ struct qed_spq_comp_cb *p_cb,
+ struct qed_ntuple_filter_params *p_params);
+
#define MAX_QUEUES_PER_QZONE (sizeof(unsigned long) * 8)
#define QED_QUEUE_CID_SELF (0xff)
diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.c b/drivers/net/ethernet/qlogic/qed/qed_ll2.c
index 047f556..21725c6 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_ll2.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.c
@@ -406,6 +406,9 @@ static void qed_ll2_rxq_parse_gsi(struct qed_hwfn *p_hwfn,
data->opaque_data_0 = le32_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrhi);
data->opaque_data_1 = le16_to_cpu(p_cqe->rx_cqe_gsi.src_mac_addrlo);
data->u.data_length_error = p_cqe->rx_cqe_gsi.data_length_error;
+ data->qp_id = le16_to_cpu(p_cqe->rx_cqe_gsi.qp_id);
+
+ data->src_qp = le32_to_cpu(p_cqe->rx_cqe_gsi.src_qp);
}
static void qed_ll2_rxq_parse_reg(struct qed_hwfn *p_hwfn,
@@ -927,7 +930,8 @@ static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
qed_chain_get_pbl_phys(&p_rx->rcq_chain));
p_ramrod->drop_ttl0_flg = p_ll2_conn->input.rx_drop_ttl0_flg;
- p_ramrod->inner_vlan_removal_en = p_ll2_conn->input.rx_vlan_removal_en;
+ p_ramrod->inner_vlan_stripping_en =
+ p_ll2_conn->input.rx_vlan_removal_en;
p_ramrod->queue_id = p_ll2_conn->queue_id;
p_ramrod->main_func_queue = p_ll2_conn->main_func_queue ? 1 : 0;
@@ -1299,8 +1303,20 @@ int qed_ll2_acquire_connection(void *cxt, struct qed_ll2_acquire_data *data)
memcpy(&p_ll2_info->input, &data->input, sizeof(p_ll2_info->input));
- p_ll2_info->tx_dest = (data->input.tx_dest == QED_LL2_TX_DEST_NW) ?
- CORE_TX_DEST_NW : CORE_TX_DEST_LB;
+ switch (data->input.tx_dest) {
+ case QED_LL2_TX_DEST_NW:
+ p_ll2_info->tx_dest = CORE_TX_DEST_NW;
+ break;
+ case QED_LL2_TX_DEST_LB:
+ p_ll2_info->tx_dest = CORE_TX_DEST_LB;
+ break;
+ case QED_LL2_TX_DEST_DROP:
+ p_ll2_info->tx_dest = CORE_TX_DEST_DROP;
+ break;
+ default:
+ return -EINVAL;
+ }
+
if (data->input.conn_type == QED_LL2_TYPE_OOO ||
data->input.secondary_queue)
p_ll2_info->main_func_queue = false;
@@ -2281,8 +2297,7 @@ static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
goto release_terminate;
}
- if (cdev->hwfns[0].hw_info.personality == QED_PCI_ISCSI &&
- cdev->hwfns[0].pf_params.iscsi_pf_params.ooo_enable) {
+ if (cdev->hwfns[0].hw_info.personality == QED_PCI_ISCSI) {
DP_VERBOSE(cdev, QED_MSG_STORAGE, "Starting OOO LL2 queue\n");
rc = qed_ll2_start_ooo(cdev, params);
if (rc) {
@@ -2340,8 +2355,7 @@ static int qed_ll2_stop(struct qed_dev *cdev)
qed_ptt_release(QED_LEADING_HWFN(cdev), p_ptt);
eth_zero_addr(cdev->ll2_mac_address);
- if (cdev->hwfns[0].hw_info.personality == QED_PCI_ISCSI &&
- cdev->hwfns[0].pf_params.iscsi_pf_params.ooo_enable)
+ if (QED_LEADING_HWFN(cdev)->hw_info.personality == QED_PCI_ISCSI)
qed_ll2_stop_ooo(cdev);
rc = qed_ll2_terminate_connection(QED_LEADING_HWFN(cdev),
diff --git a/drivers/net/ethernet/qlogic/qed/qed_mcp.c b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
index 8b99c7d..6f46cb1 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
@@ -2234,7 +2234,7 @@ int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
DRV_MSG_CODE_NVM_READ_NVRAM,
addr + offset +
(bytes_to_copy <<
- DRV_MB_PARAM_NVM_LEN_SHIFT),
+ DRV_MB_PARAM_NVM_LEN_OFFSET),
&resp, &resp_param,
&read_len,
(u32 *)(p_buf + offset));
diff --git a/drivers/net/ethernet/qlogic/qed/qed_rdma.c b/drivers/net/ethernet/qlogic/qed/qed_rdma.c
index c8c4b39..bdc46f1 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_rdma.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_rdma.c
@@ -553,7 +553,7 @@ static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
qed_iwarp_init_fw_ramrod(p_hwfn,
- &p_ent->ramrod.iwarp_init_func.iwarp);
+ &p_ent->ramrod.iwarp_init_func);
p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma;
} else {
p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
index 0cdb433..f712205 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
@@ -124,6 +124,8 @@
0x1f0434UL
#define PRS_REG_SEARCH_TAG1 \
0x1f0444UL
+#define PRS_REG_SEARCH_TENANT_ID \
+ 0x1f044cUL
#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \
0x1f0a0cUL
#define PRS_REG_SEARCH_TCP_FIRST_FRAG \
@@ -200,7 +202,13 @@
0x2e8800UL
#define CCFC_REG_STRONG_ENABLE_VF \
0x2e070cUL
-#define CDU_REG_CID_ADDR_PARAMS \
+#define CDU_REG_CCFC_CTX_VALID0 \
+ 0x580400UL
+#define CDU_REG_CCFC_CTX_VALID1 \
+ 0x580404UL
+#define CDU_REG_TCFC_CTX_VALID0 \
+ 0x580408UL
+#define CDU_REG_CID_ADDR_PARAMS \
0x580900UL
#define DBG_REG_CLIENT_ENABLE \
0x010004UL
@@ -564,7 +572,7 @@
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
#define PRS_REG_VXLAN_PORT 0x1f0738UL
-#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
+#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
@@ -580,11 +588,11 @@
#define PRS_REG_NGE_PORT 0x1f086cUL
#define NIG_REG_NGE_PORT 0x508b38UL
-#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
-#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
-#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
-#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
+#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
+#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
+#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
@@ -595,15 +603,15 @@
#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
#define QM_REG_WFQVPWEIGHT 0x2fa000UL
-#define PGLCS_REG_DBG_SELECT_K2 \
+#define PGLCS_REG_DBG_SELECT_K2_E5 \
0x001d14UL
-#define PGLCS_REG_DBG_DWORD_ENABLE_K2 \
+#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x001d18UL
-#define PGLCS_REG_DBG_SHIFT_K2 \
+#define PGLCS_REG_DBG_SHIFT_K2_E5 \
0x001d1cUL
-#define PGLCS_REG_DBG_FORCE_VALID_K2 \
+#define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \
0x001d20UL
-#define PGLCS_REG_DBG_FORCE_FRAME_K2 \
+#define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \
0x001d24UL
#define MISC_REG_RESET_PL_PDA_VMAIN_1 \
0x008070UL
@@ -615,7 +623,7 @@
0x009050UL
#define MISCS_REG_RESET_PL_HV \
0x009060UL
-#define MISCS_REG_RESET_PL_HV_2_K2 \
+#define MISCS_REG_RESET_PL_HV_2_K2_E5 \
0x009150UL
#define DMAE_REG_DBG_SELECT \
0x00c510UL
@@ -647,15 +655,15 @@
0x0500b0UL
#define GRC_REG_DBG_FORCE_FRAME \
0x0500b4UL
-#define UMAC_REG_DBG_SELECT_K2 \
+#define UMAC_REG_DBG_SELECT_K2_E5 \
0x051094UL
-#define UMAC_REG_DBG_DWORD_ENABLE_K2 \
+#define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \
0x051098UL
-#define UMAC_REG_DBG_SHIFT_K2 \
+#define UMAC_REG_DBG_SHIFT_K2_E5 \
0x05109cUL
-#define UMAC_REG_DBG_FORCE_VALID_K2 \
+#define UMAC_REG_DBG_FORCE_VALID_K2_E5 \
0x0510a0UL
-#define UMAC_REG_DBG_FORCE_FRAME_K2 \
+#define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \
0x0510a4UL
#define MCP2_REG_DBG_SELECT \
0x052400UL
@@ -717,15 +725,15 @@
0x1f0ba0UL
#define PRS_REG_DBG_FORCE_FRAME \
0x1f0ba4UL
-#define CNIG_REG_DBG_SELECT_K2 \
+#define CNIG_REG_DBG_SELECT_K2_E5 \
0x218254UL
-#define CNIG_REG_DBG_DWORD_ENABLE_K2 \
+#define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \
0x218258UL
-#define CNIG_REG_DBG_SHIFT_K2 \
+#define CNIG_REG_DBG_SHIFT_K2_E5 \
0x21825cUL
-#define CNIG_REG_DBG_FORCE_VALID_K2 \
+#define CNIG_REG_DBG_FORCE_VALID_K2_E5 \
0x218260UL
-#define CNIG_REG_DBG_FORCE_FRAME_K2 \
+#define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \
0x218264UL
#define PRM_REG_DBG_SELECT \
0x2306a8UL
@@ -997,35 +1005,35 @@
0x580710UL
#define CDU_REG_DBG_FORCE_FRAME \
0x580714UL
-#define WOL_REG_DBG_SELECT_K2 \
+#define WOL_REG_DBG_SELECT_K2_E5 \
0x600140UL
-#define WOL_REG_DBG_DWORD_ENABLE_K2 \
+#define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \
0x600144UL
-#define WOL_REG_DBG_SHIFT_K2 \
+#define WOL_REG_DBG_SHIFT_K2_E5 \
0x600148UL
-#define WOL_REG_DBG_FORCE_VALID_K2 \
+#define WOL_REG_DBG_FORCE_VALID_K2_E5 \
0x60014cUL
-#define WOL_REG_DBG_FORCE_FRAME_K2 \
+#define WOL_REG_DBG_FORCE_FRAME_K2_E5 \
0x600150UL
-#define BMBN_REG_DBG_SELECT_K2 \
+#define BMBN_REG_DBG_SELECT_K2_E5 \
0x610140UL
-#define BMBN_REG_DBG_DWORD_ENABLE_K2 \
+#define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \
0x610144UL
-#define BMBN_REG_DBG_SHIFT_K2 \
+#define BMBN_REG_DBG_SHIFT_K2_E5 \
0x610148UL
-#define BMBN_REG_DBG_FORCE_VALID_K2 \
+#define BMBN_REG_DBG_FORCE_VALID_K2_E5 \
0x61014cUL
-#define BMBN_REG_DBG_FORCE_FRAME_K2 \
+#define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \
0x610150UL
-#define NWM_REG_DBG_SELECT_K2 \
+#define NWM_REG_DBG_SELECT_K2_E5 \
0x8000ecUL
-#define NWM_REG_DBG_DWORD_ENABLE_K2 \
+#define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \
0x8000f0UL
-#define NWM_REG_DBG_SHIFT_K2 \
+#define NWM_REG_DBG_SHIFT_K2_E5 \
0x8000f4UL
-#define NWM_REG_DBG_FORCE_VALID_K2 \
+#define NWM_REG_DBG_FORCE_VALID_K2_E5 \
0x8000f8UL
-#define NWM_REG_DBG_FORCE_FRAME_K2\
+#define NWM_REG_DBG_FORCE_FRAME_K2_E5 \
0x8000fcUL
#define PBF_REG_DBG_SELECT \
0xd80060UL
@@ -1247,36 +1255,76 @@
0x1901534UL
#define USEM_REG_DBG_FORCE_FRAME \
0x1901538UL
-#define NWS_REG_DBG_SELECT_K2 \
+#define NWS_REG_DBG_SELECT_K2_E5 \
0x700128UL
-#define NWS_REG_DBG_DWORD_ENABLE_K2 \
+#define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x70012cUL
-#define NWS_REG_DBG_SHIFT_K2 \
+#define NWS_REG_DBG_SHIFT_K2_E5 \
0x700130UL
-#define NWS_REG_DBG_FORCE_VALID_K2 \
+#define NWS_REG_DBG_FORCE_VALID_K2_E5 \
0x700134UL
-#define NWS_REG_DBG_FORCE_FRAME_K2 \
+#define NWS_REG_DBG_FORCE_FRAME_K2_E5 \
0x700138UL
-#define MS_REG_DBG_SELECT_K2 \
+#define MS_REG_DBG_SELECT_K2_E5 \
0x6a0228UL
-#define MS_REG_DBG_DWORD_ENABLE_K2 \
+#define MS_REG_DBG_DWORD_ENABLE_K2_E5 \
0x6a022cUL
-#define MS_REG_DBG_SHIFT_K2 \
+#define MS_REG_DBG_SHIFT_K2_E5 \
0x6a0230UL
-#define MS_REG_DBG_FORCE_VALID_K2 \
+#define MS_REG_DBG_FORCE_VALID_K2_E5 \
0x6a0234UL
-#define MS_REG_DBG_FORCE_FRAME_K2 \
+#define MS_REG_DBG_FORCE_FRAME_K2_E5 \
0x6a0238UL
-#define PCIE_REG_DBG_COMMON_SELECT_K2 \
+#define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \
0x054398UL
-#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2 \
+#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \
0x05439cUL
-#define PCIE_REG_DBG_COMMON_SHIFT_K2 \
+#define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \
0x0543a0UL
-#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2 \
+#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \
0x0543a4UL
-#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2 \
+#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \
0x0543a8UL
+#define PTLD_REG_DBG_SELECT_E5 \
+ 0x5a1600UL
+#define PTLD_REG_DBG_DWORD_ENABLE_E5 \
+ 0x5a1604UL
+#define PTLD_REG_DBG_SHIFT_E5 \
+ 0x5a1608UL
+#define PTLD_REG_DBG_FORCE_VALID_E5 \
+ 0x5a160cUL
+#define PTLD_REG_DBG_FORCE_FRAME_E5 \
+ 0x5a1610UL
+#define YPLD_REG_DBG_SELECT_E5 \
+ 0x5c1600UL
+#define YPLD_REG_DBG_DWORD_ENABLE_E5 \
+ 0x5c1604UL
+#define YPLD_REG_DBG_SHIFT_E5 \
+ 0x5c1608UL
+#define YPLD_REG_DBG_FORCE_VALID_E5 \
+ 0x5c160cUL
+#define YPLD_REG_DBG_FORCE_FRAME_E5 \
+ 0x5c1610UL
+#define RGSRC_REG_DBG_SELECT_E5 \
+ 0x320040UL
+#define RGSRC_REG_DBG_DWORD_ENABLE_E5 \
+ 0x320044UL
+#define RGSRC_REG_DBG_SHIFT_E5 \
+ 0x320048UL
+#define RGSRC_REG_DBG_FORCE_VALID_E5 \
+ 0x32004cUL
+#define RGSRC_REG_DBG_FORCE_FRAME_E5 \
+ 0x320050UL
+#define TGSRC_REG_DBG_SELECT_E5 \
+ 0x322040UL
+#define TGSRC_REG_DBG_DWORD_ENABLE_E5 \
+ 0x322044UL
+#define TGSRC_REG_DBG_SHIFT_E5 \
+ 0x322048UL
+#define TGSRC_REG_DBG_FORCE_VALID_E5 \
+ 0x32204cUL
+#define TGSRC_REG_DBG_FORCE_FRAME_E5 \
+ 0x322050UL
#define MISC_REG_RESET_PL_UA \
0x008050UL
#define MISC_REG_RESET_PL_HV \
@@ -1415,7 +1463,7 @@
0x1940000UL
#define SEM_FAST_REG_INT_RAM \
0x020000UL
-#define SEM_FAST_REG_INT_RAM_SIZE \
+#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \
20480
#define GRC_REG_TRACE_FIFO_VALID_DATA \
0x050064UL
@@ -1433,6 +1481,8 @@
0x340800UL
#define BRB_REG_BIG_RAM_DATA \
0x341500UL
+#define BRB_REG_BIG_RAM_DATA_SIZE \
+ 64
#define SEM_FAST_REG_STALL_0_BB_K2 \
0x000488UL
#define SEM_FAST_REG_STALLED \
@@ -1451,7 +1501,7 @@
0x238c30UL
#define MISCS_REG_BLOCK_256B_EN \
0x009074UL
-#define MCP_REG_SCRATCH_SIZE \
+#define MCP_REG_SCRATCH_SIZE_BB_K2 \
57344
#define MCP_REG_CPU_REG_FILE \
0xe05200UL
@@ -1485,35 +1535,35 @@
0x008c14UL
#define NWS_REG_NWS_CMU_K2 \
0x720000UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \
0x000680UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \
0x000684UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \
0x0006c0UL
-#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \
+#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \
0x0006c4UL
-#define MS_REG_MS_CMU_K2 \
+#define MS_REG_MS_CMU_K2_E5 \
0x6a4000UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
0x000208UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
0x00020cUL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
0x000210UL
-#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \
+#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
0x000214UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
0x000208UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
0x00020cUL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
0x000210UL
-#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \
+#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
0x000214UL
-#define PHY_PCIE_REG_PHY0_K2 \
+#define PHY_PCIE_REG_PHY0_K2_E5 \
0x620000UL
-#define PHY_PCIE_REG_PHY1_K2 \
+#define PHY_PCIE_REG_PHY1_K2_E5 \
0x624000UL
#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
diff --git a/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c b/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
index a1d33f3..5e927b6 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
@@ -351,7 +351,9 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
p_ramrod->mf_mode = MF_NPAR;
}
- p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
+
+ p_ramrod->outer_tag_config.outer_tag.tci =
+ cpu_to_le16(p_hwfn->hw_info.ovlan);
/* Place EQ address in RAMROD */
DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
@@ -396,8 +398,8 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
- "Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
- sb, sb_index, p_ramrod->outer_tag);
+ "Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n",
+ sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci);
rc = qed_spq_post(p_hwfn, p_ent, NULL);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_spq.c b/drivers/net/ethernet/qlogic/qed/qed_spq.c
index be48d9a..217b62a 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_spq.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_spq.c
@@ -215,7 +215,7 @@ static int qed_spq_fill_entry(struct qed_hwfn *p_hwfn,
static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
struct qed_spq *p_spq)
{
- struct core_conn_context *p_cxt;
+ struct e4_core_conn_context *p_cxt;
struct qed_cxt_info cxt_info;
u16 physical_q;
int rc;
@@ -233,11 +233,11 @@ static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->xstorm_ag_context.flags10,
- XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags1,
- XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags9,
- XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
+ E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
/* QM physical queue */
physical_q = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.c b/drivers/net/ethernet/qlogic/qed/qed_sriov.c
index 3f40b1d..5acb91b 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_sriov.c
+++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.c
@@ -153,9 +153,9 @@ static int qed_sp_vf_stop(struct qed_hwfn *p_hwfn,
return qed_spq_post(p_hwfn, p_ent, NULL);
}
-static bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
- int rel_vf_id,
- bool b_enabled_only, bool b_non_malicious)
+bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
+ int rel_vf_id,
+ bool b_enabled_only, bool b_non_malicious)
{
if (!p_hwfn->pf_iov_info) {
DP_NOTICE(p_hwfn->cdev, "No iov info\n");
@@ -1621,7 +1621,7 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
/* fill in pfdev info */
pfdev_info->chip_num = p_hwfn->cdev->chip_num;
pfdev_info->db_size = 0;
- pfdev_info->indices_per_sb = PIS_PER_SB;
+ pfdev_info->indices_per_sb = PIS_PER_SB_E4;
pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
@@ -3582,11 +3582,11 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
{
- u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
+ u32 cons[MAX_NUM_VOQS_E4], distance[MAX_NUM_VOQS_E4];
int i, cnt;
/* Read initial consumers & producers */
- for (i = 0; i < MAX_NUM_VOQS; i++) {
+ for (i = 0; i < MAX_NUM_VOQS_E4; i++) {
u32 prod;
cons[i] = qed_rd(p_hwfn, p_ptt,
@@ -3601,7 +3601,7 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
/* Wait for consumers to pass the producers */
i = 0;
for (cnt = 0; cnt < 50; cnt++) {
- for (; i < MAX_NUM_VOQS; i++) {
+ for (; i < MAX_NUM_VOQS_E4; i++) {
u32 tmp;
tmp = qed_rd(p_hwfn, p_ptt,
@@ -3611,7 +3611,7 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
break;
}
- if (i == MAX_NUM_VOQS)
+ if (i == MAX_NUM_VOQS_E4)
break;
msleep(20);
@@ -4237,6 +4237,7 @@ static u8 *qed_iov_bulletin_get_forced_mac(struct qed_hwfn *p_hwfn,
static int qed_iov_configure_tx_rate(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, int vfid, int val)
{
+ struct qed_mcp_link_state *p_link;
struct qed_vf_info *vf;
u8 abs_vp_id = 0;
int rc;
@@ -4249,7 +4250,10 @@ static int qed_iov_configure_tx_rate(struct qed_hwfn *p_hwfn,
if (rc)
return rc;
- return qed_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val);
+ p_link = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;
+
+ return qed_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val,
+ p_link->speed);
}
static int
diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.h b/drivers/net/ethernet/qlogic/qed/qed_sriov.h
index 3955929..661caf1 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_sriov.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.h
@@ -128,6 +128,23 @@ struct qed_hw_sriov_info {
u32 first_vf_in_pf;
};
+/**
+ * @brief Check if given VF ID @vfid is valid
+ * w.r.t. @b_enabled_only value
+ * if b_enabled_only = true - only enabled VF id is valid
+ * else any VF id less than max_vfs is valid
+ *
+ * @param p_hwfn
+ * @param rel_vf_id - Relative VF ID
+ * @param b_enabled_only - consider only enabled VF
+ * @param b_non_malicious - true iff we want to validate vf isn't malicious.
+ *
+ * @return bool - true for valid VF ID
+ */
+bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
+ int rel_vf_id,
+ bool b_enabled_only, bool b_non_malicious);
+
/* This mailbox is maintained per VF in its PF contains all information
* required for sending / receiving a message.
*/
@@ -442,6 +459,13 @@ static inline int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
static inline void qed_inform_vf_link_state(struct qed_hwfn *hwfn)
{
}
+
+static inline bool
+qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
+ int rel_vf_id, bool b_enabled_only, bool b_non_malicious)
+{
+ return false;
+}
#endif
#define qed_for_each_vf(_p_hwfn, _i) \
diff --git a/drivers/net/ethernet/qlogic/qede/qede.h b/drivers/net/ethernet/qlogic/qede/qede.h
index a3a70ad..46d22e21 100644
--- a/drivers/net/ethernet/qlogic/qede/qede.h
+++ b/drivers/net/ethernet/qlogic/qede/qede.h
@@ -52,9 +52,9 @@
#include <linux/qed/qed_eth_if.h>
#define QEDE_MAJOR_VERSION 8
-#define QEDE_MINOR_VERSION 10
-#define QEDE_REVISION_VERSION 10
-#define QEDE_ENGINEERING_VERSION 21
+#define QEDE_MINOR_VERSION 33
+#define QEDE_REVISION_VERSION 0
+#define QEDE_ENGINEERING_VERSION 20
#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
__stringify(QEDE_MINOR_VERSION) "." \
__stringify(QEDE_REVISION_VERSION) "." \
diff --git a/drivers/net/ethernet/qlogic/qede/qede_filter.c b/drivers/net/ethernet/qlogic/qede/qede_filter.c
index c1a0708..3fcac47 100644
--- a/drivers/net/ethernet/qlogic/qede/qede_filter.c
+++ b/drivers/net/ethernet/qlogic/qede/qede_filter.c
@@ -98,10 +98,18 @@ static void qede_configure_arfs_fltr(struct qede_dev *edev,
u16 rxq_id, bool add_fltr)
{
const struct qed_eth_ops *op = edev->ops;
+ struct qed_ntuple_filter_params params;
if (n->used)
return;
+ memset(¶ms, 0, sizeof(params));
+
+ params.addr = n->mapping;
+ params.length = n->buf_len;
+ params.qid = rxq_id;
+ params.b_is_add = add_fltr;
+
DP_VERBOSE(edev, NETIF_MSG_RX_STATUS,
"%s arfs filter flow_id=%d, sw_id=%d, src_port=%d, dst_port=%d, rxq=%d\n",
add_fltr ? "Adding" : "Deleting",
@@ -110,8 +118,7 @@ static void qede_configure_arfs_fltr(struct qede_dev *edev,
n->used = true;
n->filter_op = add_fltr;
- op->ntuple_filter_config(edev->cdev, n, n->mapping, n->buf_len, 0,
- rxq_id, add_fltr);
+ op->ntuple_filter_config(edev->cdev, n, ¶ms);
}
static void
@@ -141,7 +148,10 @@ static void qede_configure_arfs_fltr(struct qede_dev *edev,
edev->arfs->filter_count++;
if (edev->arfs->filter_count == 1 && !edev->arfs->enable) {
- edev->ops->configure_arfs_searcher(edev->cdev, true);
+ enum qed_filter_config_mode mode;
+
+ mode = QED_FILTER_CONFIG_MODE_5_TUPLE;
+ edev->ops->configure_arfs_searcher(edev->cdev, mode);
edev->arfs->enable = true;
}
@@ -160,8 +170,11 @@ static void qede_configure_arfs_fltr(struct qede_dev *edev,
edev->arfs->filter_count--;
if (!edev->arfs->filter_count && edev->arfs->enable) {
+ enum qed_filter_config_mode mode;
+
+ mode = QED_FILTER_CONFIG_MODE_DISABLE;
edev->arfs->enable = false;
- edev->ops->configure_arfs_searcher(edev->cdev, false);
+ edev->ops->configure_arfs_searcher(edev->cdev, mode);
}
}
@@ -255,8 +268,11 @@ void qede_process_arfs_filters(struct qede_dev *edev, bool free_fltr)
if (!edev->arfs->filter_count) {
if (edev->arfs->enable) {
+ enum qed_filter_config_mode mode;
+
+ mode = QED_FILTER_CONFIG_MODE_DISABLE;
edev->arfs->enable = false;
- edev->ops->configure_arfs_searcher(edev->cdev, false);
+ edev->ops->configure_arfs_searcher(edev->cdev, mode);
}
#ifdef CONFIG_RFS_ACCEL
} else {
diff --git a/drivers/net/ethernet/qlogic/qede/qede_main.c b/drivers/net/ethernet/qlogic/qede/qede_main.c
index 8f9b3eb..22b7076 100644
--- a/drivers/net/ethernet/qlogic/qede/qede_main.c
+++ b/drivers/net/ethernet/qlogic/qede/qede_main.c
@@ -1148,7 +1148,7 @@ static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
static int qede_alloc_mem_sb(struct qede_dev *edev,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int rc;
diff --git a/drivers/scsi/qedf/drv_fcoe_fw_funcs.c b/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
index 7d91e53..a980ef7 100644
--- a/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
+++ b/drivers/scsi/qedf/drv_fcoe_fw_funcs.c
@@ -25,15 +25,17 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
u32 task_retry_id,
u8 fcp_cmd_payload[32])
{
- struct fcoe_task_context *ctx = task_params->context;
+ struct e4_fcoe_task_context *ctx = task_params->context;
+ const u8 val_byte = ctx->ystorm_ag_context.byte0;
+ struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
- struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
u32 io_size, val;
bool slow_sgl;
memset(ctx, 0, sizeof(*(ctx)));
+ ctx->ystorm_ag_context.byte0 = val_byte;
slow_sgl = scsi_is_slow_sgl(sgl_task_params->num_sges,
sgl_task_params->small_mid_sge);
io_size = (task_params->task_type == FCOE_TASK_TYPE_WRITE_INITIATOR ?
@@ -43,20 +45,20 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
y_st_ctx = &ctx->ystorm_st_context;
y_st_ctx->data_2_trns_rem = cpu_to_le32(io_size);
y_st_ctx->task_rety_identifier = cpu_to_le32(task_retry_id);
- y_st_ctx->task_type = task_params->task_type;
+ y_st_ctx->task_type = (u8)task_params->task_type;
memcpy(&y_st_ctx->tx_info_union.fcp_cmd_payload,
fcp_cmd_payload, sizeof(struct fcoe_fcp_cmd_payload));
/* Tstorm ctx */
t_st_ctx = &ctx->tstorm_st_context;
- t_st_ctx->read_only.dev_type = (task_params->is_tape_device == 1 ?
- FCOE_TASK_DEV_TYPE_TAPE :
- FCOE_TASK_DEV_TYPE_DISK);
+ t_st_ctx->read_only.dev_type = (u8)(task_params->is_tape_device == 1 ?
+ FCOE_TASK_DEV_TYPE_TAPE :
+ FCOE_TASK_DEV_TYPE_DISK);
t_st_ctx->read_only.cid = cpu_to_le32(task_params->conn_cid);
val = cpu_to_le32(task_params->cq_rss_number);
t_st_ctx->read_only.glbl_q_num = val;
t_st_ctx->read_only.fcp_cmd_trns_size = cpu_to_le32(io_size);
- t_st_ctx->read_only.task_type = task_params->task_type;
+ t_st_ctx->read_only.task_type = (u8)task_params->task_type;
SET_FIELD(t_st_ctx->read_write.flags,
FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME, 1);
t_st_ctx->read_write.rx_id = cpu_to_le16(FCOE_RX_ID);
@@ -88,6 +90,8 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
SET_FIELD(m_st_ctx->flags,
MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE,
(slow_sgl ? SCSI_TX_SLOW_SGL : SCSI_FAST_SGL));
+ m_st_ctx->sgl_params.sgl_num_sges =
+ cpu_to_le16(sgl_task_params->num_sges);
} else {
/* Tstorm ctx */
SET_FIELD(t_st_ctx->read_write.flags,
@@ -101,7 +105,9 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
sgl_task_params);
}
+ /* Init Sqe */
init_common_sqe(task_params, SEND_FCOE_CMD);
+
return 0;
}
@@ -112,14 +118,16 @@ int init_initiator_midpath_unsolicited_fcoe_task(
struct scsi_sgl_task_params *rx_sgl_task_params,
u8 fw_to_place_fc_header)
{
- struct fcoe_task_context *ctx = task_params->context;
+ struct e4_fcoe_task_context *ctx = task_params->context;
+ const u8 val_byte = ctx->ystorm_ag_context.byte0;
+ struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
- struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
u32 val;
memset(ctx, 0, sizeof(*(ctx)));
+ ctx->ystorm_ag_context.byte0 = val_byte;
/* Init Ystorm */
y_st_ctx = &ctx->ystorm_st_context;
@@ -129,7 +137,7 @@ int init_initiator_midpath_unsolicited_fcoe_task(
SET_FIELD(y_st_ctx->sgl_mode,
YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE, SCSI_FAST_SGL);
y_st_ctx->data_2_trns_rem = cpu_to_le32(task_params->tx_io_size);
- y_st_ctx->task_type = task_params->task_type;
+ y_st_ctx->task_type = (u8)task_params->task_type;
memcpy(&y_st_ctx->tx_info_union.tx_params.mid_path,
mid_path_fc_header, sizeof(struct fcoe_tx_mid_path_params));
@@ -148,7 +156,7 @@ int init_initiator_midpath_unsolicited_fcoe_task(
t_st_ctx->read_only.cid = cpu_to_le32(task_params->conn_cid);
val = cpu_to_le32(task_params->cq_rss_number);
t_st_ctx->read_only.glbl_q_num = val;
- t_st_ctx->read_only.task_type = task_params->task_type;
+ t_st_ctx->read_only.task_type = (u8)task_params->task_type;
SET_FIELD(t_st_ctx->read_write.flags,
FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME, 1);
t_st_ctx->read_write.rx_id = cpu_to_le16(FCOE_RX_ID);
@@ -182,9 +190,10 @@ int init_initiator_cleanup_fcoe_task(struct fcoe_task_params *task_params)
}
int init_initiator_sequence_recovery_fcoe_task(
- struct fcoe_task_params *task_params, u32 off)
+ struct fcoe_task_params *task_params, u32 desired_offset)
{
init_common_sqe(task_params, FCOE_SEQUENCE_RECOVERY);
- task_params->sqe->additional_info_union.seq_rec_updated_offset = off;
+ task_params->sqe->additional_info_union.seq_rec_updated_offset =
+ desired_offset;
return 0;
}
diff --git a/drivers/scsi/qedf/drv_fcoe_fw_funcs.h b/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
index f9c50fa..b5c236e 100644
--- a/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
+++ b/drivers/scsi/qedf/drv_fcoe_fw_funcs.h
@@ -13,7 +13,7 @@
struct fcoe_task_params {
/* Output parameter [set/filled by the HSI function] */
- struct fcoe_task_context *context;
+ struct e4_fcoe_task_context *context;
/* Output parameter [set/filled by the HSI function] */
struct fcoe_wqe *sqe;
diff --git a/drivers/scsi/qedf/qedf.h b/drivers/scsi/qedf/qedf.h
index 9bf7b22..c105a2e 100644
--- a/drivers/scsi/qedf/qedf.h
+++ b/drivers/scsi/qedf/qedf.h
@@ -129,7 +129,7 @@ struct qedf_ioreq {
struct delayed_work timeout_work;
struct completion tm_done;
struct completion abts_done;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
struct fcoe_task_params *task_params;
struct scsi_sgl_task_params *sgl_task_params;
int idx;
@@ -465,7 +465,7 @@ extern void qedf_cmd_timer_set(struct qedf_ctx *qedf, struct qedf_ioreq *io_req,
unsigned int timer_msec);
extern int qedf_init_mp_req(struct qedf_ioreq *io_req);
extern void qedf_init_mp_task(struct qedf_ioreq *io_req,
- struct fcoe_task_context *task_ctx, struct fcoe_wqe *wqe);
+ struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
extern u16 qedf_get_sqe_idx(struct qedf_rport *fcport);
extern void qedf_ring_doorbell(struct qedf_rport *fcport);
extern void qedf_process_els_compl(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
diff --git a/drivers/scsi/qedf/qedf_els.c b/drivers/scsi/qedf/qedf_els.c
index 59c18ca..aa22b11 100644
--- a/drivers/scsi/qedf/qedf_els.c
+++ b/drivers/scsi/qedf/qedf_els.c
@@ -19,7 +19,7 @@ static int qedf_initiate_els(struct qedf_rport *fcport, unsigned int op,
struct qedf_ioreq *els_req;
struct qedf_mp_req *mp_req;
struct fc_frame_header *fc_hdr;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
int rc = 0;
uint32_t did, sid;
uint16_t xid;
diff --git a/drivers/scsi/qedf/qedf_hsi.h b/drivers/scsi/qedf/qedf_hsi.h
index 7faef80..503c1ae 100644
--- a/drivers/scsi/qedf/qedf_hsi.h
+++ b/drivers/scsi/qedf/qedf_hsi.h
@@ -225,19 +225,6 @@ enum fcoe_cqe_type {
MAX_FCOE_CQE_TYPE
};
-
-/*
- * FCoE device type
- */
-enum fcoe_device_type {
- FCOE_TASK_DEV_TYPE_DISK,
- FCOE_TASK_DEV_TYPE_TAPE,
- MAX_FCOE_DEVICE_TYPE
-};
-
-
-
-
/*
* FCoE fast path error codes
*/
@@ -332,31 +319,6 @@ enum fcoe_sp_error_code {
MAX_FCOE_SP_ERROR_CODE
};
-
-/*
- * FCoE SQE request type
- */
-enum fcoe_sqe_request_type {
- SEND_FCOE_CMD,
- SEND_FCOE_MIDPATH,
- SEND_FCOE_ABTS_REQUEST,
- FCOE_EXCHANGE_CLEANUP,
- FCOE_SEQUENCE_RECOVERY,
- SEND_FCOE_XFER_RDY,
- SEND_FCOE_RSP,
- SEND_FCOE_RSP_WITH_SENSE_DATA,
- SEND_FCOE_TARGET_DATA,
- SEND_FCOE_INITIATOR_DATA,
- /*
- * Xfer Continuation (==1) ready to be sent. Previous XFERs data
- * received successfully.
- */
- SEND_FCOE_XFER_CONTINUATION_RDY,
- SEND_FCOE_TARGET_ABTS_RSP,
- MAX_FCOE_SQE_REQUEST_TYPE
-};
-
-
/*
* FCoE task TX state
*/
@@ -389,34 +351,4 @@ enum fcoe_task_tx_state {
MAX_FCOE_TASK_TX_STATE
};
-
-/*
- * FCoE task type
- */
-enum fcoe_task_type {
- FCOE_TASK_TYPE_WRITE_INITIATOR,
- FCOE_TASK_TYPE_READ_INITIATOR,
- FCOE_TASK_TYPE_MIDPATH,
- FCOE_TASK_TYPE_UNSOLICITED,
- FCOE_TASK_TYPE_ABTS,
- FCOE_TASK_TYPE_EXCHANGE_CLEANUP,
- FCOE_TASK_TYPE_SEQUENCE_CLEANUP,
- FCOE_TASK_TYPE_WRITE_TARGET,
- FCOE_TASK_TYPE_READ_TARGET,
- FCOE_TASK_TYPE_RSP,
- FCOE_TASK_TYPE_RSP_SENSE_DATA,
- FCOE_TASK_TYPE_ABTS_TARGET,
- FCOE_TASK_TYPE_ENUM_SIZE,
- MAX_FCOE_TASK_TYPE
-};
-
-struct scsi_glbl_queue_entry {
- /* Start physical address for the RQ (receive queue) PBL. */
- struct regpair rq_pbl_addr;
- /* Start physical address for the CQ (completion queue) PBL. */
- struct regpair cq_pbl_addr;
- /* Start physical address for the CMDQ (command queue) PBL. */
- struct regpair cmdq_pbl_addr;
-};
-
#endif /* __QEDF_HSI__ */
diff --git a/drivers/scsi/qedf/qedf_io.c b/drivers/scsi/qedf/qedf_io.c
index ded3860..943813d 100644
--- a/drivers/scsi/qedf/qedf_io.c
+++ b/drivers/scsi/qedf/qedf_io.c
@@ -579,7 +579,7 @@ static void qedf_build_fcp_cmnd(struct qedf_ioreq *io_req,
}
static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
- struct qedf_ioreq *io_req, struct fcoe_task_context *task_ctx,
+ struct qedf_ioreq *io_req, struct e4_fcoe_task_context *task_ctx,
struct fcoe_wqe *sqe)
{
enum fcoe_task_type task_type;
@@ -597,7 +597,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
/* Note init_initiator_rw_fcoe_task memsets the task context */
io_req->task = task_ctx;
- memset(task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(io_req->task_params, 0, sizeof(struct fcoe_task_params));
memset(io_req->sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
@@ -673,7 +673,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
}
void qedf_init_mp_task(struct qedf_ioreq *io_req,
- struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
+ struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
{
struct qedf_mp_req *mp_req = &(io_req->mp_req);
struct qedf_rport *fcport = io_req->fcport;
@@ -691,7 +691,7 @@ void qedf_init_mp_task(struct qedf_ioreq *io_req,
memset(&tx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(&rx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
- memset(task_ctx, 0, sizeof(struct fcoe_task_context));
+ memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(&task_fc_hdr, 0, sizeof(struct fcoe_tx_mid_path_params));
/* Setup the task from io_req for easy reference */
@@ -844,7 +844,7 @@ int qedf_post_io_req(struct qedf_rport *fcport, struct qedf_ioreq *io_req)
struct Scsi_Host *host = sc_cmd->device->host;
struct fc_lport *lport = shost_priv(host);
struct qedf_ctx *qedf = lport_priv(lport);
- struct fcoe_task_context *task_ctx;
+ struct e4_fcoe_task_context *task_ctx;
u16 xid;
enum fcoe_task_type req_type = 0;
struct fcoe_wqe *sqe;
@@ -1065,7 +1065,7 @@ void qedf_scsi_completion(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
struct qedf_ioreq *io_req)
{
u16 xid, rval;
- struct fcoe_task_context *task_ctx;
+ struct e4_fcoe_task_context *task_ctx;
struct scsi_cmnd *sc_cmd;
struct fcoe_cqe_rsp_info *fcp_rsp;
struct qedf_rport *fcport;
@@ -1722,7 +1722,7 @@ int qedf_initiate_cleanup(struct qedf_ioreq *io_req,
struct qedf_rport *fcport;
struct qedf_ctx *qedf;
uint16_t xid;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
int tmo = 0;
int rc = SUCCESS;
unsigned long flags;
@@ -1835,7 +1835,7 @@ static int qedf_execute_tmf(struct qedf_rport *fcport, struct scsi_cmnd *sc_cmd,
uint8_t tm_flags)
{
struct qedf_ioreq *io_req;
- struct fcoe_task_context *task;
+ struct e4_fcoe_task_context *task;
struct qedf_ctx *qedf = fcport->qedf;
struct fc_lport *lport = qedf->lport;
int rc = 0;
@@ -2011,11 +2011,11 @@ void qedf_process_unsol_compl(struct qedf_ctx *qedf, uint16_t que_idx,
"opaque_data.lo=%x bdq_prod_idx=%u len=%u.\n",
le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.address.hi),
le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.address.lo),
- le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.hi),
- le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.lo),
+ le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.fcoe_opaque.hi),
+ le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.fcoe_opaque.lo),
qedf->bdq_prod_idx, pktlen);
- bdq_idx = le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.lo);
+ bdq_idx = le32_to_cpu(cqe->cqe_info.unsolic_info.bd_info.opaque.fcoe_opaque.lo);
if (bdq_idx >= QEDF_BDQ_SIZE) {
QEDF_ERR(&(qedf->dbg_ctx), "bdq_idx is out of range %d.\n",
bdq_idx);
diff --git a/drivers/scsi/qedf/qedf_main.c b/drivers/scsi/qedf/qedf_main.c
index 7c00645..40800dd 100644
--- a/drivers/scsi/qedf/qedf_main.c
+++ b/drivers/scsi/qedf/qedf_main.c
@@ -1860,7 +1860,7 @@ static bool qedf_fp_has_work(struct qedf_fastpath *fp)
struct qedf_ctx *qedf = fp->qedf;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
u16 prod_idx;
/* Get the pointer to the global CQ this completion is on */
@@ -1887,7 +1887,7 @@ static bool qedf_process_completions(struct qedf_fastpath *fp)
{
struct qedf_ctx *qedf = fp->qedf;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
struct global_queue *que;
u16 prod_idx;
struct fcoe_cqe *cqe;
@@ -2352,12 +2352,12 @@ void qedf_fp_io_handler(struct work_struct *work)
static int qedf_alloc_and_init_sb(struct qedf_ctx *qedf,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedf->pdev->dev,
- sizeof(struct status_block), &sb_phys, GFP_KERNEL);
+ sizeof(struct status_block_e4), &sb_phys, GFP_KERNEL);
if (!sb_virt) {
QEDF_ERR(&(qedf->dbg_ctx), "Status block allocation failed "
@@ -2623,9 +2623,9 @@ static int qedf_alloc_bdq(struct qedf_ctx *qedf)
for (i = 0; i < QEDF_BDQ_SIZE; i++) {
pbl->address.hi = cpu_to_le32(U64_HI(qedf->bdq[i].buf_dma));
pbl->address.lo = cpu_to_le32(U64_LO(qedf->bdq[i].buf_dma));
- pbl->opaque.hi = 0;
+ pbl->opaque.fcoe_opaque.hi = 0;
/* Opaque lo data is an index into the BDQ array */
- pbl->opaque.lo = cpu_to_le32(i);
+ pbl->opaque.fcoe_opaque.lo = cpu_to_le32(i);
pbl++;
}
diff --git a/drivers/scsi/qedf/qedf_version.h b/drivers/scsi/qedf/qedf_version.h
index 397b3b8..c247805 100644
--- a/drivers/scsi/qedf/qedf_version.h
+++ b/drivers/scsi/qedf/qedf_version.h
@@ -7,9 +7,9 @@
* this source tree.
*/
-#define QEDF_VERSION "8.20.5.0"
+#define QEDF_VERSION "8.33.0.20"
#define QEDF_DRIVER_MAJOR_VER 8
-#define QEDF_DRIVER_MINOR_VER 20
-#define QEDF_DRIVER_REV_VER 5
-#define QEDF_DRIVER_ENG_VER 0
+#define QEDF_DRIVER_MINOR_VER 33
+#define QEDF_DRIVER_REV_VER 0
+#define QEDF_DRIVER_ENG_VER 20
diff --git a/drivers/scsi/qedi/qedi_debugfs.c b/drivers/scsi/qedi/qedi_debugfs.c
index 39d7781..fd8a1ee 100644
--- a/drivers/scsi/qedi/qedi_debugfs.c
+++ b/drivers/scsi/qedi/qedi_debugfs.c
@@ -152,7 +152,7 @@ struct qedi_debugfs_ops qedi_debugfs_ops[] = {
{
struct qedi_fastpath *fp = NULL;
struct qed_sb_info *sb_info = NULL;
- struct status_block *sb = NULL;
+ struct status_block_e4 *sb = NULL;
struct global_queue *que = NULL;
int id;
u16 prod_idx;
@@ -168,7 +168,7 @@ struct qedi_debugfs_ops qedi_debugfs_ops[] = {
sb_info = fp->sb_info;
sb = sb_info->sb_virt;
prod_idx = (sb->pi_array[QEDI_PROTO_CQ_PROD_IDX] &
- STATUS_BLOCK_PROD_INDEX_MASK);
+ STATUS_BLOCK_E4_PROD_INDEX_MASK);
seq_printf(s, "SB PROD IDX: %d\n", prod_idx);
que = qedi->global_queues[fp->sb_id];
seq_printf(s, "DRV CONS IDX: %d\n", que->cq_cons_idx);
diff --git a/drivers/scsi/qedi/qedi_fw.c b/drivers/scsi/qedi/qedi_fw.c
index bd302d3..092e8f9 100644
--- a/drivers/scsi/qedi/qedi_fw.c
+++ b/drivers/scsi/qedi/qedi_fw.c
@@ -87,7 +87,7 @@ static void qedi_process_text_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
- struct iscsi_task_context *task_ctx;
+ struct e4_iscsi_task_context *task_ctx;
struct iscsi_text_rsp *resp_hdr_ptr;
struct iscsi_text_response_hdr *cqe_text_response;
struct qedi_cmd *cmd;
@@ -260,7 +260,7 @@ static void qedi_process_login_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
- struct iscsi_task_context *task_ctx;
+ struct e4_iscsi_task_context *task_ctx;
struct iscsi_login_rsp *resp_hdr_ptr;
struct iscsi_login_response_hdr *cqe_login_response;
struct qedi_cmd *cmd;
@@ -326,7 +326,7 @@ static void qedi_get_rq_bdq_buf(struct qedi_ctx *qedi,
(qedi->bdq_prod_idx % qedi->rq_num_entries));
/* Obtain buffer address from rqe_opaque */
- idx = cqe->rqe_opaque.lo;
+ idx = cqe->rqe_opaque;
if (idx > (QEDI_BDQ_NUM - 1)) {
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
"wrong idx %d returned by FW, dropping the unsolicited pkt\n",
@@ -335,8 +335,7 @@ static void qedi_get_rq_bdq_buf(struct qedi_ctx *qedi,
}
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
- "rqe_opaque.lo [0x%p], rqe_opaque.hi [0x%p], idx [%d]\n",
- cqe->rqe_opaque.lo, cqe->rqe_opaque.hi, idx);
+ "rqe_opaque [0x%p], idx [%d]\n", cqe->rqe_opaque, idx);
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
"unsol_cqe_type = %d\n", cqe->unsol_cqe_type);
@@ -363,7 +362,7 @@ static void qedi_put_rq_bdq_buf(struct qedi_ctx *qedi,
struct scsi_bd *pbl;
/* Obtain buffer address from rqe_opaque */
- idx = cqe->rqe_opaque.lo;
+ idx = cqe->rqe_opaque;
if (idx > (QEDI_BDQ_NUM - 1)) {
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
"wrong idx %d returned by FW, dropping the unsolicited pkt\n",
@@ -378,8 +377,10 @@ static void qedi_put_rq_bdq_buf(struct qedi_ctx *qedi,
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
"pbl [0x%p] pbl->address hi [0x%llx] lo [0x%llx] idx [%d]\n",
pbl, pbl->address.hi, pbl->address.lo, idx);
- pbl->opaque.hi = 0;
- pbl->opaque.lo = cpu_to_le32(QEDI_U64_LO(idx));
+ pbl->opaque.iscsi_opaque.reserved_zero[0] = 0;
+ pbl->opaque.iscsi_opaque.reserved_zero[1] = 0;
+ pbl->opaque.iscsi_opaque.reserved_zero[2] = 0;
+ pbl->opaque.iscsi_opaque.opaque = cpu_to_le32(idx);
/* Increment producer to let f/w know we've handled the frame */
qedi->bdq_prod_idx += count;
@@ -1017,7 +1018,7 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_login_req *login_hdr;
struct scsi_sge *resp_sge = NULL;
@@ -1037,8 +1038,9 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1119,7 +1121,7 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_logout *logout_hdr = NULL;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct qedi_cmd *qedi_cmd;
@@ -1137,8 +1139,9 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1467,7 +1470,7 @@ static int qedi_send_iscsi_tmf(struct qedi_conn *qedi_conn,
struct iscsi_tmf_request_hdr tmf_pdu_header;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_task *ctask;
struct iscsi_tm *tmf_hdr;
@@ -1490,8 +1493,9 @@ static int qedi_send_iscsi_tmf(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1605,7 +1609,7 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_text *text_hdr;
struct scsi_sge *req_sge = NULL;
@@ -1627,8 +1631,9 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -1705,7 +1710,7 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_nopout *nopout_hdr;
struct scsi_sge *resp_sge = NULL;
struct qedi_cmd *qedi_cmd;
@@ -1725,8 +1730,9 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
qedi_cmd->task_id = tid;
@@ -2046,7 +2052,7 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
struct iscsi_task_params task_params;
struct iscsi_conn_params conn_params;
struct scsi_initiator_cmd_params cmd_params;
- struct iscsi_task_context *fw_task_ctx;
+ struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_cls_conn *cls_conn;
struct iscsi_scsi_req *hdr = (struct iscsi_scsi_req *)task->hdr;
enum iscsi_task_type task_type = MAX_ISCSI_TASK_TYPE;
@@ -2069,8 +2075,9 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
return -ENOMEM;
fw_task_ctx =
- (struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks, tid);
- memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
+ (struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
+ tid);
+ memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
cmd->task_id = tid;
diff --git a/drivers/scsi/qedi/qedi_fw_api.c b/drivers/scsi/qedi/qedi_fw_api.c
index 7df32a6..a269da1 100644
--- a/drivers/scsi/qedi/qedi_fw_api.c
+++ b/drivers/scsi/qedi/qedi_fw_api.c
@@ -203,12 +203,15 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
struct data_hdr *pdu_header,
enum iscsi_task_type task_type)
{
- struct iscsi_task_context *context;
- u16 index;
+ struct e4_iscsi_task_context *context;
u32 val;
+ u16 index;
+ u8 val_byte;
context = task_params->context;
+ val_byte = context->mstorm_ag_context.cdu_validation;
memset(context, 0, sizeof(*context));
+ context->mstorm_ag_context.cdu_validation = val_byte;
for (index = 0; index <
ARRAY_SIZE(context->ystorm_st_context.pdu_hdr.data.data);
@@ -222,7 +225,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
cpu_to_le16(task_params->conn_icid);
SET_FIELD(context->ustorm_ag_context.flags1,
- USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
+ E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
context->ustorm_st_context.task_type = task_type;
context->ustorm_st_context.cq_rss_number = task_params->cq_rss_number;
@@ -252,10 +255,9 @@ void init_initiator_rw_cdb_ystorm_context(struct ystorm_iscsi_task_st_ctx *ystc,
static
void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
- struct ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
- u32 remaining_recv_len,
- u32 expected_data_transfer_len,
- u8 num_sges, bool tx_dif_conn_err_en)
+ struct e4_ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
+ u32 remaining_recv_len, u32 expected_data_transfer_len,
+ u8 num_sges, bool tx_dif_conn_err_en)
{
u32 val;
@@ -265,12 +267,12 @@ void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
ustorm_st_cxt->exp_data_transfer_len = val;
SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges);
SET_FIELD(ustorm_ag_cxt->flags2,
- USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
+ E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
tx_dif_conn_err_en ? 1 : 0);
}
static
-void set_rw_exp_data_acked_and_cont_len(struct iscsi_task_context *context,
+void set_rw_exp_data_acked_and_cont_len(struct e4_iscsi_task_context *context,
struct iscsi_conn_params *conn_params,
enum iscsi_task_type task_type,
u32 task_size,
@@ -342,56 +344,57 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
cpu_to_le16(dif_task_params->application_tag_mask);
SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_CRC_SEED,
dif_task_params->crc_seed ? 1 : 0);
- SET_FIELD(rdif_context->flags0, RDIF_TASK_CONTEXT_HOSTGUARDTYPE,
+ SET_FIELD(rdif_context->flags0,
+ RDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
dif_task_params->host_guard_type);
SET_FIELD(rdif_context->flags0,
- RDIF_TASK_CONTEXT_PROTECTIONTYPE,
+ RDIF_TASK_CONTEXT_PROTECTION_TYPE,
dif_task_params->protection_type);
SET_FIELD(rdif_context->flags0,
- RDIF_TASK_CONTEXT_INITIALREFTAGVALID, 1);
+ RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID, 1);
SET_FIELD(rdif_context->flags0,
- RDIF_TASK_CONTEXT_KEEPREFTAGCONST,
+ RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
dif_task_params->keep_ref_tag_const ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_VALIDATEAPPTAG,
+ RDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
(dif_task_params->validate_app_tag &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_VALIDATEGUARD,
+ RDIF_TASK_CONTEXT_VALIDATE_GUARD,
(dif_task_params->validate_guard &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_VALIDATEREFTAG,
+ RDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
(dif_task_params->validate_ref_tag &&
dif_task_params->dif_on_network) ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_HOSTINTERFACE,
+ RDIF_TASK_CONTEXT_HOST_INTERFACE,
dif_task_params->dif_on_host ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_NETWORKINTERFACE,
+ RDIF_TASK_CONTEXT_NETWORK_INTERFACE,
dif_task_params->dif_on_network ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_FORWARDGUARD,
+ RDIF_TASK_CONTEXT_FORWARD_GUARD,
dif_task_params->forward_guard ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_FORWARDAPPTAG,
+ RDIF_TASK_CONTEXT_FORWARD_APP_TAG,
dif_task_params->forward_app_tag ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_FORWARDREFTAG,
+ RDIF_TASK_CONTEXT_FORWARD_REF_TAG,
dif_task_params->forward_ref_tag ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK,
+ RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
dif_task_params->forward_app_tag_with_mask ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK,
+ RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
SET_FIELD(rdif_context->flags1,
- RDIF_TASK_CONTEXT_INTERVALSIZE,
+ RDIF_TASK_CONTEXT_INTERVAL_SIZE,
dif_task_params->dif_block_size_log - 9);
SET_FIELD(rdif_context->state,
- RDIF_TASK_CONTEXT_REFTAGMASK,
+ RDIF_TASK_CONTEXT_REF_TAG_MASK,
dif_task_params->ref_tag_mask);
- SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNOREAPPTAG,
+ SET_FIELD(rdif_context->state, RDIF_TASK_CONTEXT_IGNORE_APP_TAG,
dif_task_params->ignore_app_tag);
}
@@ -399,7 +402,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
task_type == ISCSI_TASK_TYPE_INITIATOR_WRITE) {
tdif_context->app_tag_value =
cpu_to_le16(dif_task_params->application_tag);
- tdif_context->partial_crc_valueB =
+ tdif_context->partial_crc_value_b =
cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
tdif_context->partial_crc_value_a =
cpu_to_le16(dif_task_params->crc_seed ? 0xffff : 0x0000);
@@ -407,64 +410,68 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
dif_task_params->crc_seed ? 1 : 0);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_SETERRORWITHEOP,
+ TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP,
dif_task_params->tx_dif_conn_err_en ? 1 : 0);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDGUARD,
+ SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARD_GUARD,
dif_task_params->forward_guard ? 1 : 0);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDAPPTAG,
+ SET_FIELD(tdif_context->flags1,
+ TDIF_TASK_CONTEXT_FORWARD_APP_TAG,
dif_task_params->forward_app_tag ? 1 : 0);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_FORWARDREFTAG,
+ SET_FIELD(tdif_context->flags1,
+ TDIF_TASK_CONTEXT_FORWARD_REF_TAG,
dif_task_params->forward_ref_tag ? 1 : 0);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVALSIZE,
+ SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_INTERVAL_SIZE,
dif_task_params->dif_block_size_log - 9);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_HOSTINTERFACE,
+ SET_FIELD(tdif_context->flags1,
+ TDIF_TASK_CONTEXT_HOST_INTERFACE,
dif_task_params->dif_on_host ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_NETWORKINTERFACE,
+ TDIF_TASK_CONTEXT_NETWORK_INTERFACE,
dif_task_params->dif_on_network ? 1 : 0);
val = cpu_to_le32(dif_task_params->initial_ref_tag);
tdif_context->initial_ref_tag = val;
tdif_context->app_tag_mask =
cpu_to_le16(dif_task_params->application_tag_mask);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_HOSTGUARDTYPE,
+ TDIF_TASK_CONTEXT_HOST_GUARD_TYPE,
dif_task_params->host_guard_type);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_PROTECTIONTYPE,
+ TDIF_TASK_CONTEXT_PROTECTION_TYPE,
dif_task_params->protection_type);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_INITIALREFTAGVALID,
+ TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID,
dif_task_params->initial_ref_tag_is_valid ? 1 : 0);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_KEEPREFTAGCONST,
+ TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST,
dif_task_params->keep_ref_tag_const ? 1 : 0);
- SET_FIELD(tdif_context->flags1, TDIF_TASK_CONTEXT_VALIDATEGUARD,
+ SET_FIELD(tdif_context->flags1,
+ TDIF_TASK_CONTEXT_VALIDATE_GUARD,
(dif_task_params->validate_guard &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_VALIDATEAPPTAG,
+ TDIF_TASK_CONTEXT_VALIDATE_APP_TAG,
(dif_task_params->validate_app_tag &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_VALIDATEREFTAG,
+ TDIF_TASK_CONTEXT_VALIDATE_REF_TAG,
(dif_task_params->validate_ref_tag &&
dif_task_params->dif_on_host) ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK,
+ TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK,
dif_task_params->forward_app_tag_with_mask ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK,
+ TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK,
dif_task_params->forward_ref_tag_with_mask ? 1 : 0);
SET_FIELD(tdif_context->flags1,
- TDIF_TASK_CONTEXT_REFTAGMASK,
+ TDIF_TASK_CONTEXT_REF_TAG_MASK,
dif_task_params->ref_tag_mask);
SET_FIELD(tdif_context->flags0,
- TDIF_TASK_CONTEXT_IGNOREAPPTAG,
+ TDIF_TASK_CONTEXT_IGNORE_APP_TAG,
dif_task_params->ignore_app_tag ? 1 : 0);
}
}
-static void set_local_completion_context(struct iscsi_task_context *context)
+static void set_local_completion_context(struct e4_iscsi_task_context *context)
{
SET_FIELD(context->ystorm_st_context.state.flags,
YSTORM_ISCSI_TASK_STATE_LOCAL_COMP, 1);
@@ -481,7 +488,7 @@ static int init_rw_iscsi_task(struct iscsi_task_params *task_params,
struct scsi_dif_task_params *dif_task_params)
{
u32 exp_data_transfer_len = conn_params->max_burst_length;
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
bool slow_io = false;
u32 task_size, val;
u8 num_sges = 0;
@@ -494,19 +501,33 @@ static int init_rw_iscsi_task(struct iscsi_task_params *task_params,
cxt = task_params->context;
- val = cpu_to_le32(task_size);
- cxt->ystorm_st_context.pdu_hdr.cmd.expected_transfer_length = val;
- init_initiator_rw_cdb_ystorm_context(&cxt->ystorm_st_context,
- cmd_params);
- val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.lo);
- cxt->mstorm_st_context.sense_db.lo = val;
- val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.hi);
- cxt->mstorm_st_context.sense_db.hi = val;
+ if (task_type == ISCSI_TASK_TYPE_TARGET_READ) {
+ set_local_completion_context(cxt);
+ } else if (task_type == ISCSI_TASK_TYPE_TARGET_WRITE) {
+ val = cpu_to_le32(task_size +
+ ((struct iscsi_r2t_hdr *)pdu_header)->buffer_offset);
+ cxt->ystorm_st_context.pdu_hdr.r2t.desired_data_trns_len = val;
+ cxt->mstorm_st_context.expected_itt =
+ cpu_to_le32(pdu_header->itt);
+ } else {
+ val = cpu_to_le32(task_size);
+ cxt->ystorm_st_context.pdu_hdr.cmd.expected_transfer_length =
+ val;
+ init_initiator_rw_cdb_ystorm_context(&cxt->ystorm_st_context,
+ cmd_params);
+ val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.lo);
+ cxt->mstorm_st_context.sense_db.lo = val;
+
+ val = cpu_to_le32(cmd_params->sense_data_buffer_phys_addr.hi);
+ cxt->mstorm_st_context.sense_db.hi = val;
+ }
if (task_params->tx_io_size) {
init_dif_context_flags(&cxt->ystorm_st_context.state.dif_flags,
dif_task_params);
+ init_dif_context_flags(&cxt->ustorm_st_context.dif_flags,
+ dif_task_params);
init_scsi_sgl_context(&cxt->ystorm_st_context.state.sgl_params,
&cxt->ystorm_st_context.state.data_desc,
sgl_task_params);
@@ -595,7 +616,7 @@ int init_initiator_login_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -637,7 +658,7 @@ int init_initiator_nop_out_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_sgl_task_params,
struct scsi_sgl_task_params *rx_sgl_task_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -683,7 +704,7 @@ int init_initiator_logout_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
@@ -738,7 +759,7 @@ int init_initiator_text_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
- struct iscsi_task_context *cxt;
+ struct e4_iscsi_task_context *cxt;
cxt = task_params->context;
diff --git a/drivers/scsi/qedi/qedi_fw_iscsi.h b/drivers/scsi/qedi/qedi_fw_iscsi.h
index b6f24f9..c3deb77 100644
--- a/drivers/scsi/qedi/qedi_fw_iscsi.h
+++ b/drivers/scsi/qedi/qedi_fw_iscsi.h
@@ -13,7 +13,7 @@
#include "qedi_fw_scsi.h"
struct iscsi_task_params {
- struct iscsi_task_context *context;
+ struct e4_iscsi_task_context *context;
struct iscsi_wqe *sqe;
u32 tx_io_size;
u32 rx_io_size;
diff --git a/drivers/scsi/qedi/qedi_gbl.h b/drivers/scsi/qedi/qedi_gbl.h
index 63d793f..f5b5a31 100644
--- a/drivers/scsi/qedi/qedi_gbl.h
+++ b/drivers/scsi/qedi/qedi_gbl.h
@@ -52,11 +52,12 @@ void qedi_update_itt_map(struct qedi_ctx *qedi, u32 tid, u32 proto_itt,
void qedi_get_proto_itt(struct qedi_ctx *qedi, u32 tid, u32 *proto_itt);
void qedi_get_task_tid(struct qedi_ctx *qedi, u32 itt, int16_t *tid);
void qedi_process_iscsi_error(struct qedi_endpoint *ep,
- struct async_data *data);
+ struct iscsi_eqe_data *data);
void qedi_start_conn_recovery(struct qedi_ctx *qedi,
struct qedi_conn *qedi_conn);
struct qedi_conn *qedi_get_conn_from_id(struct qedi_ctx *qedi, u32 iscsi_cid);
-void qedi_process_tcp_error(struct qedi_endpoint *ep, struct async_data *data);
+void qedi_process_tcp_error(struct qedi_endpoint *ep,
+ struct iscsi_eqe_data *data);
void qedi_mark_device_missing(struct iscsi_cls_session *cls_session);
void qedi_mark_device_available(struct iscsi_cls_session *cls_session);
void qedi_reset_host_mtu(struct qedi_ctx *qedi, u16 mtu);
diff --git a/drivers/scsi/qedi/qedi_iscsi.c b/drivers/scsi/qedi/qedi_iscsi.c
index a02b34e..7ec7f6e 100644
--- a/drivers/scsi/qedi/qedi_iscsi.c
+++ b/drivers/scsi/qedi/qedi_iscsi.c
@@ -539,7 +539,6 @@ static int qedi_iscsi_offload_conn(struct qedi_endpoint *qedi_ep)
conn_info->ka_max_probe_cnt = DEF_KA_MAX_PROBE_COUNT;
conn_info->dup_ack_theshold = 3;
conn_info->rcv_wnd = 65535;
- conn_info->cwnd = DEF_MAX_CWND;
conn_info->ss_thresh = 65535;
conn_info->srtt = 300;
@@ -557,8 +556,8 @@ static int qedi_iscsi_offload_conn(struct qedi_endpoint *qedi_ep)
(qedi_ep->ip_type == TCP_IPV6),
1, (qedi_ep->vlan_id != 0));
+ conn_info->cwnd = DEF_MAX_CWND * conn_info->mss;
conn_info->rcv_wnd_scale = 4;
- conn_info->ts_ticks_per_second = 1000;
conn_info->da_timeout_value = 200;
conn_info->ack_frequency = 2;
@@ -1557,7 +1556,8 @@ char *qedi_get_iscsi_error(enum iscsi_error_types err_code)
return msg;
}
-void qedi_process_iscsi_error(struct qedi_endpoint *ep, struct async_data *data)
+void qedi_process_iscsi_error(struct qedi_endpoint *ep,
+ struct iscsi_eqe_data *data)
{
struct qedi_conn *qedi_conn;
struct qedi_ctx *qedi;
@@ -1603,7 +1603,8 @@ void qedi_process_iscsi_error(struct qedi_endpoint *ep, struct async_data *data)
qedi_start_conn_recovery(qedi_conn->qedi, qedi_conn);
}
-void qedi_process_tcp_error(struct qedi_endpoint *ep, struct async_data *data)
+void qedi_process_tcp_error(struct qedi_endpoint *ep,
+ struct iscsi_eqe_data *data)
{
struct qedi_conn *qedi_conn;
diff --git a/drivers/scsi/qedi/qedi_iscsi.h b/drivers/scsi/qedi/qedi_iscsi.h
index 3247287..ea13151 100644
--- a/drivers/scsi/qedi/qedi_iscsi.h
+++ b/drivers/scsi/qedi/qedi_iscsi.h
@@ -182,7 +182,7 @@ struct qedi_cmd {
struct scsi_cmnd *scsi_cmd;
struct scatterlist *sg;
struct qedi_io_bdt io_tbl;
- struct iscsi_task_context request;
+ struct e4_iscsi_task_context request;
unsigned char *sense_buffer;
dma_addr_t sense_buffer_dma;
u16 task_id;
diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c
index cccc34a..a000223 100644
--- a/drivers/scsi/qedi/qedi_main.c
+++ b/drivers/scsi/qedi/qedi_main.c
@@ -60,7 +60,7 @@ static int qedi_iscsi_event_cb(void *context, u8 fw_event_code, void *fw_handle)
{
struct qedi_ctx *qedi;
struct qedi_endpoint *qedi_ep;
- struct async_data *data;
+ struct iscsi_eqe_data *data;
int rval = 0;
if (!context || !fw_handle) {
@@ -72,18 +72,18 @@ static int qedi_iscsi_event_cb(void *context, u8 fw_event_code, void *fw_handle)
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_INFO,
"Recv Event %d fw_handle %p\n", fw_event_code, fw_handle);
- data = (struct async_data *)fw_handle;
+ data = (struct iscsi_eqe_data *)fw_handle;
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_INFO,
- "cid=0x%x tid=0x%x err-code=0x%x fw-dbg-param=0x%x\n",
- data->cid, data->itid, data->error_code,
- data->fw_debug_param);
+ "icid=0x%x conn_id=0x%x err-code=0x%x error-pdu-opcode-reserved=0x%x\n",
+ data->icid, data->conn_id, data->error_code,
+ data->error_pdu_opcode_reserved);
- qedi_ep = qedi->ep_tbl[data->cid];
+ qedi_ep = qedi->ep_tbl[data->icid];
if (!qedi_ep) {
QEDI_WARN(&qedi->dbg_ctx,
"Cannot process event, ep already disconnected, cid=0x%x\n",
- data->cid);
+ data->icid);
WARN_ON(1);
return -ENODEV;
}
@@ -339,12 +339,12 @@ static int qedi_init_uio(struct qedi_ctx *qedi)
static int qedi_alloc_and_init_sb(struct qedi_ctx *qedi,
struct qed_sb_info *sb_info, u16 sb_id)
{
- struct status_block *sb_virt;
+ struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedi->pdev->dev,
- sizeof(struct status_block), &sb_phys,
+ sizeof(struct status_block_e4), &sb_phys,
GFP_KERNEL);
if (!sb_virt) {
QEDI_ERR(&qedi->dbg_ctx,
@@ -858,7 +858,6 @@ static int qedi_set_iscsi_pf_param(struct qedi_ctx *qedi)
qedi->pf_params.iscsi_pf_params.gl_rq_pi = QEDI_PROTO_CQ_PROD_IDX;
qedi->pf_params.iscsi_pf_params.gl_cmd_pi = 1;
- qedi->pf_params.iscsi_pf_params.ooo_enable = 1;
err_alloc_mem:
return rval;
@@ -961,7 +960,7 @@ static bool qedi_process_completions(struct qedi_fastpath *fp)
{
struct qedi_ctx *qedi = fp->qedi;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
struct qedi_percpu_s *p = NULL;
struct global_queue *que;
u16 prod_idx;
@@ -1015,7 +1014,7 @@ static bool qedi_fp_has_work(struct qedi_fastpath *fp)
struct qedi_ctx *qedi = fp->qedi;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
- struct status_block *sb = sb_info->sb_virt;
+ struct status_block_e4 *sb = sb_info->sb_virt;
u16 prod_idx;
barrier();
@@ -1262,8 +1261,10 @@ static int qedi_alloc_bdq(struct qedi_ctx *qedi)
QEDI_INFO(&qedi->dbg_ctx, QEDI_LOG_CONN,
"pbl [0x%p] pbl->address hi [0x%llx] lo [0x%llx], idx [%d]\n",
pbl, pbl->address.hi, pbl->address.lo, i);
- pbl->opaque.hi = 0;
- pbl->opaque.lo = cpu_to_le32(QEDI_U64_LO(i));
+ pbl->opaque.iscsi_opaque.reserved_zero[0] = 0;
+ pbl->opaque.iscsi_opaque.reserved_zero[1] = 0;
+ pbl->opaque.iscsi_opaque.reserved_zero[2] = 0;
+ pbl->opaque.iscsi_opaque.opaque = cpu_to_le16(i);
pbl++;
}
diff --git a/drivers/scsi/qedi/qedi_version.h b/drivers/scsi/qedi/qedi_version.h
index d61e3ac..8a0e523 100644
--- a/drivers/scsi/qedi/qedi_version.h
+++ b/drivers/scsi/qedi/qedi_version.h
@@ -7,8 +7,8 @@
* this source tree.
*/
-#define QEDI_MODULE_VERSION "8.10.4.0"
+#define QEDI_MODULE_VERSION "8.33.0.20"
#define QEDI_DRIVER_MAJOR_VER 8
-#define QEDI_DRIVER_MINOR_VER 10
-#define QEDI_DRIVER_REV_VER 4
-#define QEDI_DRIVER_ENG_VER 0
+#define QEDI_DRIVER_MINOR_VER 33
+#define QEDI_DRIVER_REV_VER 0
+#define QEDI_DRIVER_ENG_VER 20
diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h
index 39e2a2a..2b3b350 100644
--- a/include/linux/qed/common_hsi.h
+++ b/include/linux/qed/common_hsi.h
@@ -32,14 +32,15 @@
#ifndef _COMMON_HSI_H
#define _COMMON_HSI_H
+
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/slab.h>
/* dma_addr_t manip */
-#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
-#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
+#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
+#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
#define DMA_REGPAIR_LE(x, val) do { \
@@ -47,39 +48,45 @@
(x).lo = DMA_LO_LE((val)); \
} while (0)
-#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
-#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64)
-#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
+#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
+#define HILO_64(hi, lo) \
+ HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
+#define HILO_64_REGPAIR(regpair) ({ \
+ typeof(regpair) __regpair = (regpair); \
+ HILO_64(__regpair.hi, __regpair.lo); })
#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
#ifndef __COMMON_HSI__
#define __COMMON_HSI__
+/********************************/
+/* PROTOCOL COMMON FW CONSTANTS */
+/********************************/
-#define X_FINAL_CLEANUP_AGG_INT 1
+#define X_FINAL_CLEANUP_AGG_INT 1
-#define EVENT_RING_PAGE_SIZE_BYTES 4096
+#define EVENT_RING_PAGE_SIZE_BYTES 4096
-#define NUM_OF_GLOBAL_QUEUES 128
-#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
+#define NUM_OF_GLOBAL_QUEUES 128
+#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
-#define ISCSI_CDU_TASK_SEG_TYPE 0
-#define FCOE_CDU_TASK_SEG_TYPE 0
-#define RDMA_CDU_TASK_SEG_TYPE 1
+#define ISCSI_CDU_TASK_SEG_TYPE 0
+#define FCOE_CDU_TASK_SEG_TYPE 0
+#define RDMA_CDU_TASK_SEG_TYPE 1
-#define FW_ASSERT_GENERAL_ATTN_IDX 32
+#define FW_ASSERT_GENERAL_ATTN_IDX 32
-#define MAX_PINNED_CCFC 32
+#define MAX_PINNED_CCFC 32
/* Queue Zone sizes in bytes */
-#define TSTORM_QZONE_SIZE 8
-#define MSTORM_QZONE_SIZE 16
-#define USTORM_QZONE_SIZE 8
-#define XSTORM_QZONE_SIZE 8
-#define YSTORM_QZONE_SIZE 0
-#define PSTORM_QZONE_SIZE 0
-
-#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
+#define TSTORM_QZONE_SIZE 8
+#define MSTORM_QZONE_SIZE 16
+#define USTORM_QZONE_SIZE 8
+#define XSTORM_QZONE_SIZE 8
+#define YSTORM_QZONE_SIZE 0
+#define PSTORM_QZONE_SIZE 0
+
+#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
@@ -102,8 +109,8 @@
#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
#define FW_MAJOR_VERSION 8
-#define FW_MINOR_VERSION 20
-#define FW_REVISION_VERSION 0
+#define FW_MINOR_VERSION 33
+#define FW_REVISION_VERSION 1
#define FW_ENGINEERING_VERSION 0
/***********************/
@@ -115,10 +122,10 @@
#define MAX_NUM_PORTS_BB (2)
#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
-#define MAX_NUM_PFS_K2 (16)
-#define MAX_NUM_PFS_BB (8)
-#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
-#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
+#define MAX_NUM_PFS_K2 (16)
+#define MAX_NUM_PFS_BB (8)
+#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
+#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
#define MAX_NUM_VFS_K2 (192)
#define MAX_NUM_VFS_BB (120)
@@ -141,29 +148,14 @@
/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
#define NUM_PHYS_TCS_4PORT_K2 (4)
#define NUM_OF_PHYS_TCS (8)
-
+#define PURE_LB_TC NUM_OF_PHYS_TCS
#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
-#define LB_TC (NUM_OF_PHYS_TCS)
-
-/* Num of possible traffic priority values */
-#define NUM_OF_PRIO (8)
-
-#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
-#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
-#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
-#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
-
/* CIDs */
-#define NUM_OF_CONNECTION_TYPES (8)
-#define NUM_OF_LCIDS (320)
-#define NUM_OF_LTIDS (320)
-
-/* Clock values */
-#define MASTER_CLK_FREQ_E4 (375e6)
-#define STORM_CLK_FREQ_E4 (1000e6)
-#define CLK25M_CLK_FREQ_E4 (25e6)
+#define NUM_OF_CONNECTION_TYPES_E4 (8)
+#define NUM_OF_LCIDS (320)
+#define NUM_OF_LTIDS (320)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
@@ -172,17 +164,17 @@
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
/* Tools Version */
-#define TOOLS_VERSION 10
+#define TOOLS_VERSION 10
/*****************/
/* CDU CONSTANTS */
/*****************/
-#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
-#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
+#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
+#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
-#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
-#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
@@ -201,45 +193,45 @@
#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
#define DQ_DEMS_ROCE_CQ_CONS 7
-/* XCM agg val selection */
-#define DQ_XCM_AGG_VAL_SEL_WORD2 0
-#define DQ_XCM_AGG_VAL_SEL_WORD3 1
-#define DQ_XCM_AGG_VAL_SEL_WORD4 2
-#define DQ_XCM_AGG_VAL_SEL_WORD5 3
-#define DQ_XCM_AGG_VAL_SEL_REG3 4
-#define DQ_XCM_AGG_VAL_SEL_REG4 5
-#define DQ_XCM_AGG_VAL_SEL_REG5 6
-#define DQ_XCM_AGG_VAL_SEL_REG6 7
-
-/* XCM agg val selection */
-#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
-#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
-#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
-#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
-#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
-#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
-#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
+/* XCM agg val selection (HW) */
+#define DQ_XCM_AGG_VAL_SEL_WORD2 0
+#define DQ_XCM_AGG_VAL_SEL_WORD3 1
+#define DQ_XCM_AGG_VAL_SEL_WORD4 2
+#define DQ_XCM_AGG_VAL_SEL_WORD5 3
+#define DQ_XCM_AGG_VAL_SEL_REG3 4
+#define DQ_XCM_AGG_VAL_SEL_REG4 5
+#define DQ_XCM_AGG_VAL_SEL_REG5 6
+#define DQ_XCM_AGG_VAL_SEL_REG6 7
+
+/* XCM agg val selection (FW) */
+#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
+#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
+#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
/* UCM agg val selection (HW) */
#define DQ_UCM_AGG_VAL_SEL_WORD0 0
#define DQ_UCM_AGG_VAL_SEL_WORD1 1
#define DQ_UCM_AGG_VAL_SEL_WORD2 2
#define DQ_UCM_AGG_VAL_SEL_WORD3 3
-#define DQ_UCM_AGG_VAL_SEL_REG0 4
-#define DQ_UCM_AGG_VAL_SEL_REG1 5
-#define DQ_UCM_AGG_VAL_SEL_REG2 6
-#define DQ_UCM_AGG_VAL_SEL_REG3 7
+#define DQ_UCM_AGG_VAL_SEL_REG0 4
+#define DQ_UCM_AGG_VAL_SEL_REG1 5
+#define DQ_UCM_AGG_VAL_SEL_REG2 6
+#define DQ_UCM_AGG_VAL_SEL_REG3 7
/* UCM agg val selection (FW) */
#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
@@ -263,7 +255,7 @@
#define DQ_TCM_ROCE_RQ_PROD_CMD \
DQ_TCM_AGG_VAL_SEL_WORD0
-/* XCM agg counter flag selection */
+/* XCM agg counter flag selection (HW) */
#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
@@ -273,20 +265,20 @@
#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
-/* XCM agg counter flag selection */
-#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
-#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
-#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
-#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
-#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+/* XCM agg counter flag selection (FW) */
+#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
+#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
+#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
/* UCM agg counter flag selection (HW) */
#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -317,9 +309,9 @@
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
/* TCM agg counter flag selection (FW) */
-#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
-#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
-#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
+#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
+#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
+#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
@@ -327,18 +319,18 @@
#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
/* PWM address mapping */
-#define DQ_PWM_OFFSET_DPM_BASE 0x0
-#define DQ_PWM_OFFSET_DPM_END 0x27
+#define DQ_PWM_OFFSET_DPM_BASE 0x0
+#define DQ_PWM_OFFSET_DPM_END 0x27
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
-#define DQ_PWM_OFFSET_UCM16_4 0x50
+#define DQ_PWM_OFFSET_UCM16_4 0x50
#define DQ_PWM_OFFSET_TCM16_BASE 0x58
#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
-#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
-#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
-#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
+#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
+#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
+#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
@@ -347,10 +339,11 @@
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
-#define DQ_REGION_SHIFT (12)
+
+#define DQ_REGION_SHIFT (12)
/* DPM */
-#define DQ_DPM_WQE_BUFF_SIZE (320)
+#define DQ_DPM_WQE_BUFF_SIZE (320)
/* Conn type ranges */
#define DQ_CONN_TYPE_RANGE_SHIFT (4)
@@ -359,29 +352,30 @@
/* QM CONSTANTS */
/*****************/
-/* number of TX queues in the QM */
+/* Number of TX queues in the QM */
#define MAX_QM_TX_QUEUES_K2 512
#define MAX_QM_TX_QUEUES_BB 448
#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
-/* number of Other queues in the QM */
+/* Number of Other queues in the QM */
#define MAX_QM_OTHER_QUEUES_BB 64
#define MAX_QM_OTHER_QUEUES_K2 128
#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
-/* number of queues in a PF queue group */
+/* Number of queues in a PF queue group */
#define QM_PF_QUEUE_GROUP_SIZE 8
-/* the size of a single queue element in bytes */
-#define QM_PQ_ELEMENT_SIZE 4
+/* The size of a single queue element in bytes */
+#define QM_PQ_ELEMENT_SIZE 4
-/* base number of Tx PQs in the CM PQ representation.
- * should be used when storing PQ IDs in CM PQ registers and context
+/* Base number of Tx PQs in the CM PQ representation.
+ * Should be used when storing PQ IDs in CM PQ registers and context.
*/
-#define CM_TX_PQ_BASE 0x200
+#define CM_TX_PQ_BASE 0x200
-/* number of global Vport/QCN rate limiters */
+/* Number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
+
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
@@ -400,7 +394,7 @@
#define CAU_FSM_ETH_TX 1
/* Number of Protocol Indices per Status Block */
-#define PIS_PER_SB 12
+#define PIS_PER_SB_E4 12
#define CAU_HC_STOPPED_STATE 3
#define CAU_HC_DISABLE_STATE 4
@@ -432,8 +426,7 @@
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
- MAX_TOT_SB_PER_PATH - \
- 1)
+ MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@@ -447,8 +440,7 @@
#define IGU_CMD_PROD_UPD_BASE 0x0600
#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
- MAX_TOT_SB_PER_PATH - \
- 1)
+ MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
/*****************/
@@ -514,129 +506,126 @@
PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
/* PF BAR */
-#define PXP_BAR0_START_GRC 0x0000
-#define PXP_BAR0_GRC_LENGTH 0x1C00000
-#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
- PXP_BAR0_GRC_LENGTH - 1)
-
-#define PXP_BAR0_START_IGU 0x1C00000
-#define PXP_BAR0_IGU_LENGTH 0x10000
-#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
- PXP_BAR0_IGU_LENGTH - 1)
-
-#define PXP_BAR0_START_TSDM 0x1C80000
-#define PXP_BAR0_SDM_LENGTH 0x40000
+#define PXP_BAR0_START_GRC 0x0000
+#define PXP_BAR0_GRC_LENGTH 0x1C00000
+#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
+ PXP_BAR0_GRC_LENGTH - 1)
+
+#define PXP_BAR0_START_IGU 0x1C00000
+#define PXP_BAR0_IGU_LENGTH 0x10000
+#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
+ PXP_BAR0_IGU_LENGTH - 1)
+
+#define PXP_BAR0_START_TSDM 0x1C80000
+#define PXP_BAR0_SDM_LENGTH 0x40000
#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
-#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_MSDM 0x1D00000
-#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_MSDM 0x1D00000
+#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_USDM 0x1D80000
-#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_USDM 0x1D80000
+#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_XSDM 0x1E00000
-#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_XSDM 0x1E00000
+#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_YSDM 0x1E80000
-#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_YSDM 0x1E80000
+#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_PSDM 0x1F00000
-#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_PSDM 0x1F00000
+#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
/* VF BAR */
-#define PXP_VF_BAR0 0
-
-#define PXP_VF_BAR0_START_GRC 0x3E00
-#define PXP_VF_BAR0_GRC_LENGTH 0x200
-#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
- PXP_VF_BAR0_GRC_LENGTH - 1)
-
-#define PXP_VF_BAR0_START_IGU 0
-#define PXP_VF_BAR0_IGU_LENGTH 0x3000
-#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
- PXP_VF_BAR0_IGU_LENGTH - 1)
-
-#define PXP_VF_BAR0_START_DQ 0x3000
-#define PXP_VF_BAR0_DQ_LENGTH 0x200
-#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
-#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
- PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
-#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
- + 4)
-#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
- PXP_VF_BAR0_DQ_LENGTH - 1)
-
-#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
-#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
-#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
-#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
-#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
-#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
-#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
-#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
-
-#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
-#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
-
-#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
-
-#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
-#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
+#define PXP_VF_BAR0 0
+
+#define PXP_VF_BAR0_START_IGU 0
+#define PXP_VF_BAR0_IGU_LENGTH 0x3000
+#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
+ PXP_VF_BAR0_IGU_LENGTH - 1)
+
+#define PXP_VF_BAR0_START_DQ 0x3000
+#define PXP_VF_BAR0_DQ_LENGTH 0x200
+#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
+#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
+ PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
+#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
+ + 4)
+#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
+ PXP_VF_BAR0_DQ_LENGTH - 1)
+
+#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
+#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
+#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
+#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
+#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
+#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
+#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
+#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
+
+#define PXP_VF_BAR0_START_GRC 0x3E00
+#define PXP_VF_BAR0_GRC_LENGTH 0x200
+#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
+ PXP_VF_BAR0_GRC_LENGTH - 1)
+
+#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
+#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
+
+#define PXP_VF_BAR0_START_IGU2 0x10000
+#define PXP_VF_BAR0_IGU2_LENGTH 0xD000
+#define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + \
+ PXP_VF_BAR0_IGU2_LENGTH - 1)
+
+#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
+
+#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
+#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
/* ILT Records */
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
-#define PXP_QUEUES_ZONE_MAX_NUM 320
+
+/* Host Interface */
+#define PXP_QUEUES_ZONE_MAX_NUM 320
+
/*****************/
/* PRM CONSTANTS */
/*****************/
-#define PRM_DMA_PAD_BYTES_NUM 2
+#define PRM_DMA_PAD_BYTES_NUM 2
+
/*****************/
/* SDMs CONSTANTS */
/*****************/
-#define SDM_OP_GEN_TRIG_NONE 0
-#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
-#define SDM_OP_GEN_TRIG_AGG_INT 2
-#define SDM_OP_GEN_TRIG_LOADER 4
+#define SDM_OP_GEN_TRIG_NONE 0
+#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
+#define SDM_OP_GEN_TRIG_AGG_INT 2
+#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
@@ -644,26 +633,26 @@
/* Completion types */
/********************/
-#define SDM_COMP_TYPE_NONE 0
-#define SDM_COMP_TYPE_WAKE_THREAD 1
-#define SDM_COMP_TYPE_AGG_INT 2
-#define SDM_COMP_TYPE_CM 3
-#define SDM_COMP_TYPE_LOADER 4
-#define SDM_COMP_TYPE_PXP 5
-#define SDM_COMP_TYPE_INDICATE_ERROR 6
-#define SDM_COMP_TYPE_RELEASE_THREAD 7
-#define SDM_COMP_TYPE_RAM 8
-#define SDM_COMP_TYPE_INC_ORDER_CNT 9
+#define SDM_COMP_TYPE_NONE 0
+#define SDM_COMP_TYPE_WAKE_THREAD 1
+#define SDM_COMP_TYPE_AGG_INT 2
+#define SDM_COMP_TYPE_CM 3
+#define SDM_COMP_TYPE_LOADER 4
+#define SDM_COMP_TYPE_PXP 5
+#define SDM_COMP_TYPE_INDICATE_ERROR 6
+#define SDM_COMP_TYPE_RELEASE_THREAD 7
+#define SDM_COMP_TYPE_RAM 8
+#define SDM_COMP_TYPE_INC_ORDER_CNT 9
/*****************/
-/* PBF Constants */
+/* PBF CONSTANTS */
/*****************/
/* Number of PBF command queue lines. Each line is 32B. */
-#define PBF_MAX_CMD_LINES 3328
+#define PBF_MAX_CMD_LINES 3328
/* Number of BTB blocks. Each block is 256B. */
-#define BTB_MAX_BLOCKS 1440
+#define BTB_MAX_BLOCKS 1440
/*****************/
/* PRS CONSTANTS */
@@ -671,14 +660,7 @@
#define PRS_GFT_CAM_LINES_NO_MATCH 31
-/* Async data KCQ CQE */
-struct async_data {
- __le32 cid;
- __le16 itid;
- u8 error_code;
- u8 fw_debug_param;
-};
-
+/* Interrupt coalescing TimeSet */
struct coalescing_timeset {
u8 value;
#define COALESCING_TIMESET_TIMESET_MASK 0x7F
@@ -692,23 +674,32 @@ struct common_queue_zone {
__le16 reserved;
};
+/* ETH Rx producers data */
struct eth_rx_prod_data {
__le16 bd_prod;
__le16 cqe_prod;
};
-struct regpair {
- __le32 lo;
- __le32 hi;
+struct tcp_ulp_connect_done_params {
+ __le16 mss;
+ u8 snd_wnd_scale;
+ u8 flags;
+#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
+#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
+#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
+#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
};
-struct vf_pf_channel_eqe_data {
- struct regpair msg_addr;
+struct iscsi_connect_done_results {
+ __le16 icid;
+ __le16 conn_id;
+ struct tcp_ulp_connect_done_params params;
};
struct iscsi_eqe_data {
- __le32 cid;
+ __le16 icid;
__le16 conn_id;
+ __le16 reserved;
u8 error_code;
u8 error_pdu_opcode_reserved;
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
@@ -719,52 +710,6 @@ struct iscsi_eqe_data {
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
-struct rdma_eqe_destroy_qp {
- __le32 cid;
- u8 reserved[4];
-};
-
-union rdma_eqe_data {
- struct regpair async_handle;
- struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
-};
-
-struct malicious_vf_eqe_data {
- u8 vf_id;
- u8 err_id;
- __le16 reserved[3];
-};
-
-struct initial_cleanup_eqe_data {
- u8 vf_id;
- u8 reserved[7];
-};
-
-/* Event Data Union */
-union event_ring_data {
- u8 bytes[8];
- struct vf_pf_channel_eqe_data vf_pf_channel;
- struct iscsi_eqe_data iscsi_info;
- union rdma_eqe_data rdma_data;
- struct malicious_vf_eqe_data malicious_vf;
- struct initial_cleanup_eqe_data vf_init_cleanup;
-};
-
-/* Event Ring Entry */
-struct event_ring_entry {
- u8 protocol_id;
- u8 opcode;
- __le16 reserved0;
- __le16 echo;
- u8 fw_return_code;
- u8 flags;
-#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
-#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
-#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
-#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
- union event_ring_data data;
-};
-
/* Multi function mode */
enum mf_mode {
ERROR_MODE /* Unsupported mode */,
@@ -781,13 +726,31 @@ enum protocol_type {
PROTOCOLID_CORE,
PROTOCOLID_ETH,
PROTOCOLID_IWARP,
- PROTOCOLID_RESERVED5,
+ PROTOCOLID_RESERVED0,
PROTOCOLID_PREROCE,
PROTOCOLID_COMMON,
- PROTOCOLID_RESERVED6,
+ PROTOCOLID_RESERVED1,
MAX_PROTOCOL_TYPE
};
+struct regpair {
+ __le32 lo;
+ __le32 hi;
+};
+
+/* RoCE Destroy Event Data */
+struct rdma_eqe_destroy_qp {
+ __le32 cid;
+ u8 reserved[4];
+};
+
+/* RDMA Event Data Union */
+union rdma_eqe_data {
+ struct regpair async_handle;
+ struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
+};
+
+/* Ustorm Queue Zone */
struct ustorm_eth_queue_zone {
struct coalescing_timeset int_coalescing_timeset;
u8 reserved[3];
@@ -798,62 +761,71 @@ struct ustorm_queue_zone {
struct common_queue_zone common;
};
-/* status block structure */
+/* Status block structure */
struct cau_pi_entry {
- u32 prod;
-#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
-#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
-#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
-#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
-#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
-#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
-#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
-#define CAU_PI_ENTRY_RESERVED_SHIFT 24
+ __le32 prod;
+#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
+#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
+#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
+#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
+#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
+#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
+#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
+#define CAU_PI_ENTRY_RESERVED_SHIFT 24
};
-/* status block structure */
+/* Status block structure */
struct cau_sb_entry {
- u32 data;
-#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
-#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
-#define CAU_SB_ENTRY_STATE0_MASK 0xF
-#define CAU_SB_ENTRY_STATE0_SHIFT 24
-#define CAU_SB_ENTRY_STATE1_MASK 0xF
-#define CAU_SB_ENTRY_STATE1_SHIFT 28
- u32 params;
-#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
-#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
-#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
-#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
-#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
-#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
-#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
-#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
-#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
-#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
-#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
-#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
-#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
-#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
-#define CAU_SB_ENTRY_TPH_MASK 0x1
-#define CAU_SB_ENTRY_TPH_SHIFT 31
+ __le32 data;
+#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
+#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
+#define CAU_SB_ENTRY_STATE0_MASK 0xF
+#define CAU_SB_ENTRY_STATE0_SHIFT 24
+#define CAU_SB_ENTRY_STATE1_MASK 0xF
+#define CAU_SB_ENTRY_STATE1_SHIFT 28
+ __le32 params;
+#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
+#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
+#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
+#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
+#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
+#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
+#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
+#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
+#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
+#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
+#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
+#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
+#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
+#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
+#define CAU_SB_ENTRY_TPH_MASK 0x1
+#define CAU_SB_ENTRY_TPH_SHIFT 31
};
-/* core doorbell data */
+/* Igu cleanup bit values to distinguish between clean or producer consumer
+ * update.
+ */
+enum command_type_bit {
+ IGU_COMMAND_TYPE_NOP = 0,
+ IGU_COMMAND_TYPE_SET = 1,
+ MAX_COMMAND_TYPE_BIT
+};
+
+/* Core doorbell data */
struct core_db_data {
u8 params;
-#define CORE_DB_DATA_DEST_MASK 0x3
-#define CORE_DB_DATA_DEST_SHIFT 0
-#define CORE_DB_DATA_AGG_CMD_MASK 0x3
-#define CORE_DB_DATA_AGG_CMD_SHIFT 2
-#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
-#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
-#define CORE_DB_DATA_RESERVED_MASK 0x1
-#define CORE_DB_DATA_RESERVED_SHIFT 5
-#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
- u8 agg_flags;
- __le16 spq_prod;
+#define CORE_DB_DATA_DEST_MASK 0x3
+#define CORE_DB_DATA_DEST_SHIFT 0
+#define CORE_DB_DATA_AGG_CMD_MASK 0x3
+#define CORE_DB_DATA_AGG_CMD_SHIFT 2
+#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
+#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
+#define CORE_DB_DATA_RESERVED_MASK 0x1
+#define CORE_DB_DATA_RESERVED_SHIFT 5
+#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
+ u8 agg_flags;
+ __le16 spq_prod;
};
/* Enum of doorbell aggregative command selection */
@@ -909,67 +881,69 @@ struct db_l2_dpm_sge {
struct regpair addr;
__le16 nbytes;
__le16 bitfields;
-#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
-#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
-#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
-#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
-#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
-#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
-#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
-#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
+#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
+#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
+#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
+#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
+#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
+#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
__le32 reserved2;
};
/* Structure for doorbell address, in legacy mode */
struct db_legacy_addr {
__le32 addr;
-#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
-#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
-#define DB_LEGACY_ADDR_DEMS_MASK 0x7
-#define DB_LEGACY_ADDR_DEMS_SHIFT 2
-#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
-#define DB_LEGACY_ADDR_ICID_SHIFT 5
+#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
+#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
+#define DB_LEGACY_ADDR_DEMS_MASK 0x7
+#define DB_LEGACY_ADDR_DEMS_SHIFT 2
+#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
+#define DB_LEGACY_ADDR_ICID_SHIFT 5
};
/* Structure for doorbell address, in PWM mode */
struct db_pwm_addr {
__le32 addr;
#define DB_PWM_ADDR_RESERVED0_MASK 0x7
-#define DB_PWM_ADDR_RESERVED0_SHIFT 0
-#define DB_PWM_ADDR_OFFSET_MASK 0x7F
+#define DB_PWM_ADDR_RESERVED0_SHIFT 0
+#define DB_PWM_ADDR_OFFSET_MASK 0x7F
#define DB_PWM_ADDR_OFFSET_SHIFT 3
-#define DB_PWM_ADDR_WID_MASK 0x3
-#define DB_PWM_ADDR_WID_SHIFT 10
-#define DB_PWM_ADDR_DPI_MASK 0xFFFF
-#define DB_PWM_ADDR_DPI_SHIFT 12
+#define DB_PWM_ADDR_WID_MASK 0x3
+#define DB_PWM_ADDR_WID_SHIFT 10
+#define DB_PWM_ADDR_DPI_MASK 0xFFFF
+#define DB_PWM_ADDR_DPI_SHIFT 12
#define DB_PWM_ADDR_RESERVED1_MASK 0xF
-#define DB_PWM_ADDR_RESERVED1_SHIFT 28
+#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
-/* Parameters to RoCE firmware, passed in EDPM doorbell */
+/* Parameters to RDMA firmware, passed in EDPM doorbell */
struct db_rdma_dpm_params {
__le32 params;
-#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
-#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
-#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
-#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
-#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
-#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
-#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
-#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
-#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
-#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
-#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
+#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
+#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
+#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
+#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
+#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
+#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
+#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
+#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
+#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
+#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
+#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
};
-/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
+/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
+ * DPM burst.
+ */
struct db_rdma_dpm_data {
__le16 icid;
__le16 prod_val;
@@ -987,22 +961,22 @@ enum igu_int_cmd {
/* IGU producer or consumer update command */
struct igu_prod_cons_update {
- u32 sb_id_and_flags;
-#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
-#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
-#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
-#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
-#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
-#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
-#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
-#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
-#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
-#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
- u32 reserved1;
+ __le32 sb_id_and_flags;
+#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
+#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
+#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
+#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
+#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
+#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
+#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
+#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
+#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
+#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
+ __le32 reserved1;
};
/* Igu segments access for default status block only */
@@ -1012,38 +986,63 @@ enum igu_seg_access {
MAX_IGU_SEG_ACCESS
};
+/* Enumeration for L3 type field of parsing_and_err_flags.
+ * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
+ * (This field can be filled according to the last-ethertype)
+ */
+enum l3_type {
+ e_l3_type_unknown,
+ e_l3_type_ipv4,
+ e_l3_type_ipv6,
+ MAX_L3_TYPE
+};
+
+/* Enumeration for l4Protocol field of parsing_and_err_flags.
+ * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
+ * If the packet is IPv4 fragment, and its not the first fragment, the
+ * protocol-type should be set to none.
+ */
+enum l4_protocol {
+ e_l4_protocol_none,
+ e_l4_protocol_tcp,
+ e_l4_protocol_udp,
+ MAX_L4_PROTOCOL
+};
+
+/* Parsing and error flags field */
struct parsing_and_err_flags {
__le16 flags;
-#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
-#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
-#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
-#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
-#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
-#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
-#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
-#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
-#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
-#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
-#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
-#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
-#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
-#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
+#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
+#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
+#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
+#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
+#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
+#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
+#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
+#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
+#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
+#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
+#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
+#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
+#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
+#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
};
+/* Parsing error flags bitmap */
struct parsing_err_flags {
__le16 flags;
#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
@@ -1080,266 +1079,260 @@ struct parsing_err_flags {
#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
};
+/* Pb context */
struct pb_context {
__le32 crc[4];
};
+/* Concrete Function ID */
struct pxp_concrete_fid {
__le16 fid;
-#define PXP_CONCRETE_FID_PFID_MASK 0xF
-#define PXP_CONCRETE_FID_PFID_SHIFT 0
-#define PXP_CONCRETE_FID_PORT_MASK 0x3
-#define PXP_CONCRETE_FID_PORT_SHIFT 4
-#define PXP_CONCRETE_FID_PATH_MASK 0x1
-#define PXP_CONCRETE_FID_PATH_SHIFT 6
-#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
-#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
-#define PXP_CONCRETE_FID_VFID_MASK 0xFF
-#define PXP_CONCRETE_FID_VFID_SHIFT 8
+#define PXP_CONCRETE_FID_PFID_MASK 0xF
+#define PXP_CONCRETE_FID_PFID_SHIFT 0
+#define PXP_CONCRETE_FID_PORT_MASK 0x3
+#define PXP_CONCRETE_FID_PORT_SHIFT 4
+#define PXP_CONCRETE_FID_PATH_MASK 0x1
+#define PXP_CONCRETE_FID_PATH_SHIFT 6
+#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
+#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
+#define PXP_CONCRETE_FID_VFID_MASK 0xFF
+#define PXP_CONCRETE_FID_VFID_SHIFT 8
};
+/* Concrete Function ID */
struct pxp_pretend_concrete_fid {
__le16 fid;
-#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
-#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
-#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
-#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
-#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
-#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
-#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
-#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
+#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
+#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
+#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
+#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
+#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
+#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
+#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
+#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
};
+/* Function ID */
union pxp_pretend_fid {
struct pxp_pretend_concrete_fid concrete_fid;
- __le16 opaque_fid;
+ __le16 opaque_fid;
};
-/* Pxp Pretend Command Register. */
+/* Pxp Pretend Command Register */
struct pxp_pretend_cmd {
- union pxp_pretend_fid fid;
- __le16 control;
-#define PXP_PRETEND_CMD_PATH_MASK 0x1
-#define PXP_PRETEND_CMD_PATH_SHIFT 0
-#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
-#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
-#define PXP_PRETEND_CMD_PORT_MASK 0x3
-#define PXP_PRETEND_CMD_PORT_SHIFT 2
-#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
-#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
-#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
-#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
-#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
-#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
-#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
-#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
-#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
+ union pxp_pretend_fid fid;
+ __le16 control;
+#define PXP_PRETEND_CMD_PATH_MASK 0x1
+#define PXP_PRETEND_CMD_PATH_SHIFT 0
+#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
+#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
+#define PXP_PRETEND_CMD_PORT_MASK 0x3
+#define PXP_PRETEND_CMD_PORT_SHIFT 2
+#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
+#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
+#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
+#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
+#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
+#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
+#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
+#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
+#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
};
-/* PTT Record in PXP Admin Window. */
+/* PTT Record in PXP Admin Window */
struct pxp_ptt_entry {
- __le32 offset;
-#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
-#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
-#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
-#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
- struct pxp_pretend_cmd pretend;
+ __le32 offset;
+#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
+#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
+#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
+#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
+ struct pxp_pretend_cmd pretend;
};
-/* VF Zone A Permission Register. */
+/* VF Zone A Permission Register */
struct pxp_vf_zone_a_permission {
__le32 control;
-#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
-#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
-#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
-#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
+#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
+#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
+#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
+#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
};
-/* RSS hash type */
+/* Rdif context */
struct rdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
u8 flags0;
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
-#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
-#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
+#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
+#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
u8 partial_dif_data[7];
__le16 partial_crc_value;
__le16 partial_checksum_value;
__le32 offset_in_io;
__le16 flags1;
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
-#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
-#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
+#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
+#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
__le16 state;
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
-#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
-#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
-#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
-#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
-#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
-#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
+#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
+#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
__le32 reserved2;
};
-/* RSS hash type */
-enum rss_hash_type {
- RSS_HASH_TYPE_DEFAULT = 0,
- RSS_HASH_TYPE_IPV4 = 1,
- RSS_HASH_TYPE_TCP_IPV4 = 2,
- RSS_HASH_TYPE_IPV6 = 3,
- RSS_HASH_TYPE_TCP_IPV6 = 4,
- RSS_HASH_TYPE_UDP_IPV4 = 5,
- RSS_HASH_TYPE_UDP_IPV6 = 6,
- MAX_RSS_HASH_TYPE
-};
-
-/* status block structure */
-struct status_block {
- __le16 pi_array[PIS_PER_SB];
+/* Status block structure */
+struct status_block_e4 {
+ __le16 pi_array[PIS_PER_SB_E4];
__le32 sb_num;
-#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
-#define STATUS_BLOCK_SB_NUM_SHIFT 0
-#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
-#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
-#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
-#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
+#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
+#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
+#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
+#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
+#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
+#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
__le32 prod_index;
-#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
-#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
-#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
-#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
+#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
+#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
+#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
+#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
};
+/* Tdif context */
struct tdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
- __le16 partial_crc_valueB;
- __le16 partial_checksum_valueB;
+ __le16 partial_crc_value_b;
+ __le16 partial_checksum_value_b;
__le16 stateB;
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
-#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
-#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
-#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
+#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
+#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
u8 reserved1;
u8 flags0;
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
-#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
-#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
-#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
+#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
+#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
+#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
__le32 flags1;
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
-#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
-#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
-#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
-#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
-#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
- __le32 offset_in_iob;
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
+#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
+#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
+ __le32 offset_in_io_b;
__le16 partial_crc_value_a;
- __le16 partial_checksum_valuea_;
- __le32 offset_in_ioa;
+ __le16 partial_checksum_value_a;
+ __le32 offset_in_io_a;
u8 partial_dif_data_a[8];
u8 partial_dif_data_b[8];
};
+/* Timers context */
struct timers_context {
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
@@ -1385,6 +1378,7 @@ struct timers_context {
#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
};
+/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
enum tunnel_next_protocol {
e_unknown = 0,
e_l2 = 1,
diff --git a/include/linux/qed/eth_common.h b/include/linux/qed/eth_common.h
index cb06e6e..4c281dc 100644
--- a/include/linux/qed/eth_common.h
+++ b/include/linux/qed/eth_common.h
@@ -36,150 +36,168 @@
/********************/
/* ETH FW CONSTANTS */
/********************/
-#define ETH_HSI_VER_MAJOR 3
-#define ETH_HSI_VER_MINOR 10
+
+#define ETH_HSI_VER_MAJOR 3
+#define ETH_HSI_VER_MINOR 10
#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
-#define ETH_CACHE_LINE_SIZE 64
-#define ETH_RX_CQE_GAP 32
-#define ETH_MAX_RAMROD_PER_CON 8
-#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
-#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
-#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
-#define ETH_RX_NUM_NEXT_PAGE_BDS 2
-
-#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
-#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
-
-#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
-#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
-#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
-#define ETH_TX_MAX_LSO_HDR_NBD 4
-#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
-#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
-#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
-#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
-#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
-#define ETH_TX_MAX_LSO_HDR_BYTES 510
-#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
-#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
-#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
-#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
-#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
-
-#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
+#define ETH_CACHE_LINE_SIZE 64
+#define ETH_RX_CQE_GAP 32
+#define ETH_MAX_RAMROD_PER_CON 8
+#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
+#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
+#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
+#define ETH_RX_NUM_NEXT_PAGE_BDS 2
+
+#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
+#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
+
+#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
+#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
+#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
+#define ETH_TX_MAX_LSO_HDR_NBD 4
+#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
+#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
+#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
+#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
+#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
+#define ETH_TX_MAX_LSO_HDR_BYTES 510
+#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
+#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
+#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
+#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
+#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
+
+#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
/* Maximum number of buffers, used for RX packet placement */
-#define ETH_RX_MAX_BUFF_PER_PKT 5
-#define ETH_RX_BD_THRESHOLD 12
+#define ETH_RX_MAX_BUFF_PER_PKT 5
+#define ETH_RX_BD_THRESHOLD 12
-/* num of MAC/VLAN filters */
-#define ETH_NUM_MAC_FILTERS 512
-#define ETH_NUM_VLAN_FILTERS 512
+/* Num of MAC/VLAN filters */
+#define ETH_NUM_MAC_FILTERS 512
+#define ETH_NUM_VLAN_FILTERS 512
-/* approx. multicast constants */
-#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
-#define ETH_MULTICAST_MAC_BINS 256
-#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
+/* Approx. multicast constants */
+#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
+#define ETH_MULTICAST_MAC_BINS 256
+#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
-/* ethernet vport update constants */
-#define ETH_FILTER_RULES_COUNT 10
-#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
-#define ETH_RSS_KEY_SIZE_REGS 10
-#define ETH_RSS_ENGINE_NUM_K2 207
-#define ETH_RSS_ENGINE_NUM_BB 127
+/* Ethernet vport update constants */
+#define ETH_FILTER_RULES_COUNT 10
+#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
+#define ETH_RSS_KEY_SIZE_REGS 10
+#define ETH_RSS_ENGINE_NUM_K2 207
+#define ETH_RSS_ENGINE_NUM_BB 127
/* TPA constants */
-#define ETH_TPA_MAX_AGGS_NUM 64
-#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
-#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
-#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
+#define ETH_TPA_MAX_AGGS_NUM 64
+#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
+#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
+#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
/* Control frame check constants */
#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
+/* GFS constants */
+#define ETH_GFT_TRASH_CAN_VPORT 0x1FF
+
+/* Destination port mode */
+enum dest_port_mode {
+ DEST_PORT_PHY,
+ DEST_PORT_LOOPBACK,
+ DEST_PORT_PHY_LOOPBACK,
+ DEST_PORT_DROP,
+ MAX_DEST_PORT_MODE
+};
+
+/* Ethernet address type */
+enum eth_addr_type {
+ BROADCAST_ADDRESS,
+ MULTICAST_ADDRESS,
+ UNICAST_ADDRESS,
+ UNKNOWN_ADDRESS,
+ MAX_ETH_ADDR_TYPE
+};
+
struct eth_tx_1st_bd_flags {
u8 bitfields;
-#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
-#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
-#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
-#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
-#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
-#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
-#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
-#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
+#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
+#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
+#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
+#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
+#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
+#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
+#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
+#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
};
-/* The parsing information data fo rthe first tx bd of a given packet. */
+/* The parsing information data fo rthe first tx bd of a given packet */
struct eth_tx_data_1st_bd {
__le16 vlan;
u8 nbds;
struct eth_tx_1st_bd_flags bd_flags;
__le16 bitfields;
-#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
-#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
-#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
-#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
-#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
-#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
+#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
+#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
+#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
+#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
+#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
+#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
};
-/* The parsing information data for the second tx bd of a given packet. */
+/* The parsing information data for the second tx bd of a given packet */
struct eth_tx_data_2nd_bd {
__le16 tunn_ip_size;
__le16 bitfields1;
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
-#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
-#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
-#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
-#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
-#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
-#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
+#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
+#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
+#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
+#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
+#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
+#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
__le16 bitfields2;
-#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
-#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
-#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
+#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
+#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
+#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
+#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
};
-/* Firmware data for L2-EDPM packet. */
+/* Firmware data for L2-EDPM packet */
struct eth_edpm_fw_data {
struct eth_tx_data_1st_bd data_1st_bd;
struct eth_tx_data_2nd_bd data_2nd_bd;
__le32 reserved;
};
-struct eth_fast_path_cqe_fw_debug {
- __le16 reserved2;
-};
-
-/* tunneling parsing flags */
+/* Tunneling parsing flags */
struct eth_tunnel_parsing_flags {
u8 flags;
#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
@@ -199,24 +217,24 @@ struct eth_tunnel_parsing_flags {
/* PMD flow control bits */
struct eth_pmd_flow_flags {
u8 flags;
-#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
-#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
-#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
-#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
-#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
-#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
+#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
+#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
+#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
+#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
+#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
+#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
};
-/* Regular ETH Rx FP CQE. */
+/* Regular ETH Rx FP CQE */
struct eth_fast_path_rx_reg_cqe {
u8 type;
u8 bitfields;
-#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
-#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
-#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
-#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
-#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
+#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
+#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
+#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
+#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
+#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
__le16 pkt_len;
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag;
@@ -225,13 +243,13 @@ struct eth_fast_path_rx_reg_cqe {
u8 placement_offset;
struct eth_tunnel_parsing_flags tunnel_pars_flags;
u8 bd_num;
- u8 reserved[9];
- struct eth_fast_path_cqe_fw_debug fw_debug;
- u8 reserved1[3];
+ u8 reserved;
+ __le16 flow_id;
+ u8 reserved1[11];
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-continue ETH Rx FP CQE. */
+/* TPA-continue ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_cont_cqe {
u8 type;
u8 tpa_agg_index;
@@ -243,7 +261,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-end ETH Rx FP CQE. */
+/* TPA-end ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_end_cqe {
u8 type;
u8 tpa_agg_index;
@@ -259,16 +277,16 @@ struct eth_fast_path_rx_tpa_end_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-start ETH Rx FP CQE. */
+/* TPA-start ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_start_cqe {
u8 type;
u8 bitfields;
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
-#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
+#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
__le16 seg_len;
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag;
@@ -279,7 +297,7 @@ struct eth_fast_path_rx_tpa_start_cqe {
u8 tpa_agg_index;
u8 header_len;
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
- struct eth_fast_path_cqe_fw_debug fw_debug;
+ __le16 flow_id;
u8 reserved;
struct eth_pmd_flow_flags pmd_flags;
};
@@ -295,24 +313,24 @@ struct eth_rx_bd {
struct regpair addr;
};
-/* regular ETH Rx SP CQE */
+/* Regular ETH Rx SP CQE */
struct eth_slow_path_rx_cqe {
- u8 type;
- u8 ramrod_cmd_id;
- u8 error_flag;
- u8 reserved[25];
- __le16 echo;
- u8 reserved1;
+ u8 type;
+ u8 ramrod_cmd_id;
+ u8 error_flag;
+ u8 reserved[25];
+ __le16 echo;
+ u8 reserved1;
struct eth_pmd_flow_flags pmd_flags;
};
-/* union for all ETH Rx CQE types */
+/* Union for all ETH Rx CQE types */
union eth_rx_cqe {
- struct eth_fast_path_rx_reg_cqe fast_path_regular;
- struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
- struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
- struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
- struct eth_slow_path_rx_cqe slow_path;
+ struct eth_fast_path_rx_reg_cqe fast_path_regular;
+ struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
+ struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
+ struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
+ struct eth_slow_path_rx_cqe slow_path;
};
/* ETH Rx CQE type */
@@ -339,7 +357,7 @@ enum eth_rx_tunn_type {
MAX_ETH_RX_TUNN_TYPE
};
-/* Aggregation end reason. */
+/* Aggregation end reason. */
enum eth_tpa_end_reason {
ETH_AGG_END_UNUSED,
ETH_AGG_END_SP_UPDATE,
@@ -354,59 +372,59 @@ enum eth_tpa_end_reason {
/* The first tx bd of a given packet */
struct eth_tx_1st_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_1st_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_1st_bd data;
};
/* The second tx bd of a given packet */
struct eth_tx_2nd_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_2nd_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_2nd_bd data;
};
-/* The parsing information data for the third tx bd of a given packet. */
+/* The parsing information data for the third tx bd of a given packet */
struct eth_tx_data_3rd_bd {
__le16 lso_mss;
__le16 bitfields;
-#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
-#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
-#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
-#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
-#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
-#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
+#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
+#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
+#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
+#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
+#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
+#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
u8 tunn_l4_hdr_start_offset_w;
u8 tunn_hdr_size_w;
};
/* The third tx bd of a given packet */
struct eth_tx_3rd_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_3rd_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_3rd_bd data;
};
-/* Complementary information for the regular tx bd of a given packet. */
+/* Complementary information for the regular tx bd of a given packet */
struct eth_tx_data_bd {
- __le16 reserved0;
- __le16 bitfields;
-#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
-#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
-#define ETH_TX_DATA_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
-#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
+ __le16 reserved0;
+ __le16 bitfields;
+#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
+#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
+#define ETH_TX_DATA_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
+#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
__le16 reserved3;
};
/* The common non-special TX BD ring element */
struct eth_tx_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_bd data;
};
union eth_tx_bd_types {
@@ -434,18 +452,30 @@ struct xstorm_eth_queue_zone {
/* ETH doorbell data */
struct eth_db_data {
u8 params;
-#define ETH_DB_DATA_DEST_MASK 0x3
-#define ETH_DB_DATA_DEST_SHIFT 0
-#define ETH_DB_DATA_AGG_CMD_MASK 0x3
-#define ETH_DB_DATA_AGG_CMD_SHIFT 2
-#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
-#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
-#define ETH_DB_DATA_RESERVED_MASK 0x1
-#define ETH_DB_DATA_RESERVED_SHIFT 5
-#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define ETH_DB_DATA_DEST_MASK 0x3
+#define ETH_DB_DATA_DEST_SHIFT 0
+#define ETH_DB_DATA_AGG_CMD_MASK 0x3
+#define ETH_DB_DATA_AGG_CMD_SHIFT 2
+#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
+#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
+#define ETH_DB_DATA_RESERVED_MASK 0x1
+#define ETH_DB_DATA_RESERVED_SHIFT 5
+#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 bd_prod;
};
+/** RSS hash type */
+enum rss_hash_type {
+ RSS_HASH_TYPE_DEFAULT = 0,
+ RSS_HASH_TYPE_IPV4 = 1,
+ RSS_HASH_TYPE_TCP_IPV4 = 2,
+ RSS_HASH_TYPE_IPV6 = 3,
+ RSS_HASH_TYPE_TCP_IPV6 = 4,
+ RSS_HASH_TYPE_UDP_IPV4 = 5,
+ RSS_HASH_TYPE_UDP_IPV6 = 6,
+ MAX_RSS_HASH_TYPE
+};
+
#endif /* __ETH_COMMON__ */
diff --git a/include/linux/qed/fcoe_common.h b/include/linux/qed/fcoe_common.h
index 12fc9e7..22077c5 100644
--- a/include/linux/qed/fcoe_common.h
+++ b/include/linux/qed/fcoe_common.h
@@ -8,217 +8,78 @@
#ifndef __FCOE_COMMON__
#define __FCOE_COMMON__
+
/*********************/
/* FCOE FW CONSTANTS */
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
-struct fcoe_abts_pkt {
- __le32 abts_rsp_fc_payload_lo;
- __le16 abts_rsp_rx_id;
- u8 abts_rsp_rctl;
- u8 reserved2;
-};
-
-/* FCoE additional WQE (Sq/XferQ) information */
-union fcoe_additional_info_union {
- __le32 previous_tid;
- __le32 parent_tid;
- __le32 burst_length;
- __le32 seq_rec_updated_offset;
-};
-
-struct fcoe_exp_ro {
- __le32 data_offset;
- __le32 reserved;
-};
-
-union fcoe_cleanup_addr_exp_ro_union {
- struct regpair abts_rsp_fc_payload_hi;
- struct fcoe_exp_ro exp_ro;
-};
-
-/* FCoE Ramrod Command IDs */
-enum fcoe_completion_status {
- FCOE_COMPLETION_STATUS_SUCCESS,
- FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
- FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
- MAX_FCOE_COMPLETION_STATUS
-};
-
-struct fc_addr_nw {
- u8 addr_lo;
- u8 addr_mid;
- u8 addr_hi;
-};
-
-/* FCoE connection offload */
-struct fcoe_conn_offload_ramrod_data {
- struct regpair sq_pbl_addr;
- struct regpair sq_curr_page_addr;
- struct regpair sq_next_page_addr;
- struct regpair xferq_pbl_addr;
- struct regpair xferq_curr_page_addr;
- struct regpair xferq_next_page_addr;
- struct regpair respq_pbl_addr;
- struct regpair respq_curr_page_addr;
- struct regpair respq_next_page_addr;
- __le16 dst_mac_addr_lo;
- __le16 dst_mac_addr_mid;
- __le16 dst_mac_addr_hi;
- __le16 src_mac_addr_lo;
- __le16 src_mac_addr_mid;
- __le16 src_mac_addr_hi;
- __le16 tx_max_fc_pay_len;
- __le16 e_d_tov_timer_val;
- __le16 rx_max_fc_pay_len;
- __le16 vlan_tag;
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
- __le16 physical_q0;
- __le16 rec_rr_tov_timer_val;
- struct fc_addr_nw s_id;
- u8 max_conc_seqs_c3;
- struct fc_addr_nw d_id;
- u8 flags;
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
- __le16 conn_id;
- u8 def_q_idx;
- u8 reserved[5];
-};
-
-/* FCoE terminate connection request */
-struct fcoe_conn_terminate_ramrod_data {
- struct regpair terminate_params_addr;
-};
-
-struct fcoe_slow_sgl_ctx {
- struct regpair base_sgl_addr;
- __le16 curr_sge_off;
- __le16 remainder_num_sges;
- __le16 curr_sgl_index;
- __le16 reserved;
-};
-
-union fcoe_dix_desc_ctx {
- struct fcoe_slow_sgl_ctx dix_sgl;
- struct scsi_sge cached_dix_sge;
+/* The fcoe storm task context protection-information of Ystorm */
+struct protection_info_ctx {
+ __le16 flags;
+#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
+#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
+#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
+#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
+#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
+#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
+#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
+#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
+ u8 dix_block_size;
+ u8 dst_size;
};
-struct fcoe_fast_sgl_ctx {
- struct regpair sgl_start_addr;
- __le32 sgl_byte_offset;
- __le16 task_reuse_cnt;
- __le16 init_offset_in_first_sge;
+/* The fcoe storm task context protection-information of Ystorm */
+union protection_info_union_ctx {
+ struct protection_info_ctx info;
+ __le32 value;
};
+/* FCP CMD payload */
struct fcoe_fcp_cmd_payload {
__le32 opaque[8];
};
+/* FCP RSP payload */
struct fcoe_fcp_rsp_payload {
__le32 opaque[6];
};
-struct fcoe_fcp_xfer_payload {
- __le32 opaque[3];
-};
-
-/* FCoE firmware function init */
-struct fcoe_init_func_ramrod_data {
- struct scsi_init_func_params func_params;
- struct scsi_init_func_queues q_params;
- __le16 mtu;
- __le16 sq_num_pages_in_pbl;
- __le32 reserved;
-};
-
-/* FCoE: Mode of the connection: Target or Initiator or both */
-enum fcoe_mode_type {
- FCOE_INITIATOR_MODE = 0x0,
- FCOE_TARGET_MODE = 0x1,
- FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
- MAX_FCOE_MODE_TYPE
-};
-
-struct fcoe_rx_stat {
- struct regpair fcoe_rx_byte_cnt;
- struct regpair fcoe_rx_data_pkt_cnt;
- struct regpair fcoe_rx_xfer_pkt_cnt;
- struct regpair fcoe_rx_other_pkt_cnt;
- __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
- __le32 fcoe_silent_drop_pkt_rq_full_cnt;
- __le32 fcoe_silent_drop_pkt_crc_error_cnt;
- __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
- __le32 fcoe_silent_drop_total_pkt_cnt;
- __le32 rsrv;
-};
-
-struct fcoe_stat_ramrod_data {
- struct regpair stat_params_addr;
-};
-
-struct protection_info_ctx {
- __le16 flags;
-#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
-#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
-#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
-#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
-#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
-#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
-#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
-#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
- u8 dix_block_size;
- u8 dst_size;
-};
-
-union protection_info_union_ctx {
- struct protection_info_ctx info;
- __le32 value;
-};
-
+/* FCP RSP payload */
struct fcp_rsp_payload_padded {
struct fcoe_fcp_rsp_payload rsp_payload;
__le32 reserved[2];
};
+/* FCP RSP payload */
+struct fcoe_fcp_xfer_payload {
+ __le32 opaque[3];
+};
+
+/* FCP RSP payload */
struct fcp_xfer_payload_padded {
struct fcoe_fcp_xfer_payload xfer_payload;
__le32 reserved[5];
};
+/* Task params */
struct fcoe_tx_data_params {
__le32 data_offset;
__le32 offset_in_io;
u8 flags;
-#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
-#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
-#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
-#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
-#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
+#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
+#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
+#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
+#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
+#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
u8 dif_residual;
__le16 seq_cnt;
__le16 single_sge_saved_offset;
@@ -227,6 +88,7 @@ struct fcoe_tx_data_params {
__le16 reserved3;
};
+/* Middle path parameters: FC header fields provided by the driver */
struct fcoe_tx_mid_path_params {
__le32 parameter;
u8 r_ctl;
@@ -237,11 +99,13 @@ struct fcoe_tx_mid_path_params {
__le16 ox_id;
};
+/* Task params */
struct fcoe_tx_params {
struct fcoe_tx_data_params data;
struct fcoe_tx_mid_path_params mid_path;
};
+/* Union of FCP CMD payload \ TX params \ ABTS \ Cleanup */
union fcoe_tx_info_union_ctx {
struct fcoe_fcp_cmd_payload fcp_cmd_payload;
struct fcp_rsp_payload_padded fcp_rsp_payload;
@@ -249,13 +113,29 @@ struct fcoe_tx_params {
struct fcoe_tx_params tx_params;
};
+/* Data sgl */
+struct fcoe_slow_sgl_ctx {
+ struct regpair base_sgl_addr;
+ __le16 curr_sge_off;
+ __le16 remainder_num_sges;
+ __le16 curr_sgl_index;
+ __le16 reserved;
+};
+
+/* Union of DIX SGL \ cached DIX sges */
+union fcoe_dix_desc_ctx {
+ struct fcoe_slow_sgl_ctx dix_sgl;
+ struct scsi_sge cached_dix_sge;
+};
+
+/* The fcoe storm task context of Ystorm */
struct ystorm_fcoe_task_st_ctx {
u8 task_type;
u8 sgl_mode;
-#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
-#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
-#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
-#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
+#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
+#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
+#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
+#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
u8 cached_dix_sge;
u8 expect_first_xfer;
__le32 num_pbf_zero_write;
@@ -272,49 +152,49 @@ struct ystorm_fcoe_task_st_ctx {
u8 reserved2[8];
};
-struct ystorm_fcoe_task_ag_ctx {
+struct e4_ystorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@@ -328,73 +208,73 @@ struct ystorm_fcoe_task_ag_ctx {
__le32 reg2;
};
-struct tstorm_fcoe_task_ag_ctx {
+struct e4_tstorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
u8 flags1;
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
u8 flags3;
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
u8 flags4;
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 cleanup_state;
__le16 last_sent_tid;
__le32 rec_rr_tov_exp_timeout;
@@ -407,25 +287,46 @@ struct tstorm_fcoe_task_ag_ctx {
__le32 data_offset_next;
};
+/* Cached data sges */
+struct fcoe_exp_ro {
+ __le32 data_offset;
+ __le32 reserved;
+};
+
+/* Union of Cleanup address \ expected relative offsets */
+union fcoe_cleanup_addr_exp_ro_union {
+ struct regpair abts_rsp_fc_payload_hi;
+ struct fcoe_exp_ro exp_ro;
+};
+
+/* Fields coppied from ABTSrsp pckt */
+struct fcoe_abts_pkt {
+ __le32 abts_rsp_fc_payload_lo;
+ __le16 abts_rsp_rx_id;
+ u8 abts_rsp_rctl;
+ u8 reserved2;
+};
+
+/* FW read- write (modifyable) part The fcoe task storm context of Tstorm */
struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
__le16 flags;
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
__le16 seq_cnt;
u8 seq_id;
u8 ooo_rx_seq_id;
@@ -436,6 +337,7 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
__le16 reserved1;
};
+/* FW read only part The fcoe task storm context of Tstorm */
struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
u8 task_type;
u8 dev_type;
@@ -446,54 +348,55 @@ struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
__le32 rsrv;
};
+/** The fcoe task storm context of Tstorm */
struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
};
-struct mstorm_fcoe_task_ag_ctx {
+struct e4_mstorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 icid;
u8 flags0;
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 cleanup_state;
__le32 received_bytes;
u8 byte3;
@@ -507,6 +410,7 @@ struct mstorm_fcoe_task_ag_ctx {
__le32 reg2;
};
+/* The fcoe task storm context of Mstorm */
struct mstorm_fcoe_task_st_ctx {
struct regpair rsp_buf_addr;
__le32 rsrv[2];
@@ -515,79 +419,79 @@ struct mstorm_fcoe_task_st_ctx {
__le32 data_buffer_offset;
__le16 parent_id;
__le16 flags;
-#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
-#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
-#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
-#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
-#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
-#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
-#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
+#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
+#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
+#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
+#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
+#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
+#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
+#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
struct scsi_cached_sges data_desc;
};
-struct ustorm_fcoe_task_ag_ctx {
+struct e4_ustorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
u8 flags1;
-#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 global_cq_num;
@@ -596,21 +500,189 @@ struct ustorm_fcoe_task_ag_ctx {
__le32 reg5;
};
-struct fcoe_task_context {
+/* FCoE task context */
+struct e4_fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct tdif_task_context tdif_context;
- struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
- struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
+ struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
+ struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
struct tstorm_fcoe_task_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
- struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
+ struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_st_ctx mstorm_st_context;
- struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
+ struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct rdif_task_context rdif_context;
};
+/* FCoE additional WQE (Sq/XferQ) information */
+union fcoe_additional_info_union {
+ __le32 previous_tid;
+ __le32 parent_tid;
+ __le32 burst_length;
+ __le32 seq_rec_updated_offset;
+};
+
+/* FCoE Ramrod Command IDs */
+enum fcoe_completion_status {
+ FCOE_COMPLETION_STATUS_SUCCESS,
+ FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
+ FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
+ MAX_FCOE_COMPLETION_STATUS
+};
+
+/* FC address (SID/DID) network presentation */
+struct fc_addr_nw {
+ u8 addr_lo;
+ u8 addr_mid;
+ u8 addr_hi;
+};
+
+/* FCoE connection offload */
+struct fcoe_conn_offload_ramrod_data {
+ struct regpair sq_pbl_addr;
+ struct regpair sq_curr_page_addr;
+ struct regpair sq_next_page_addr;
+ struct regpair xferq_pbl_addr;
+ struct regpair xferq_curr_page_addr;
+ struct regpair xferq_next_page_addr;
+ struct regpair respq_pbl_addr;
+ struct regpair respq_curr_page_addr;
+ struct regpair respq_next_page_addr;
+ __le16 dst_mac_addr_lo;
+ __le16 dst_mac_addr_mid;
+ __le16 dst_mac_addr_hi;
+ __le16 src_mac_addr_lo;
+ __le16 src_mac_addr_mid;
+ __le16 src_mac_addr_hi;
+ __le16 tx_max_fc_pay_len;
+ __le16 e_d_tov_timer_val;
+ __le16 rx_max_fc_pay_len;
+ __le16 vlan_tag;
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
+ __le16 physical_q0;
+ __le16 rec_rr_tov_timer_val;
+ struct fc_addr_nw s_id;
+ u8 max_conc_seqs_c3;
+ struct fc_addr_nw d_id;
+ u8 flags;
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT 4
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 5
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 7
+ __le16 conn_id;
+ u8 def_q_idx;
+ u8 reserved[5];
+};
+
+/* FCoE terminate connection request */
+struct fcoe_conn_terminate_ramrod_data {
+ struct regpair terminate_params_addr;
+};
+
+/* FCoE device type */
+enum fcoe_device_type {
+ FCOE_TASK_DEV_TYPE_DISK,
+ FCOE_TASK_DEV_TYPE_TAPE,
+ MAX_FCOE_DEVICE_TYPE
+};
+
+/* Data sgl */
+struct fcoe_fast_sgl_ctx {
+ struct regpair sgl_start_addr;
+ __le32 sgl_byte_offset;
+ __le16 task_reuse_cnt;
+ __le16 init_offset_in_first_sge;
+};
+
+/* FCoE firmware function init */
+struct fcoe_init_func_ramrod_data {
+ struct scsi_init_func_params func_params;
+ struct scsi_init_func_queues q_params;
+ __le16 mtu;
+ __le16 sq_num_pages_in_pbl;
+ __le32 reserved[3];
+};
+
+/* FCoE: Mode of the connection: Target or Initiator or both */
+enum fcoe_mode_type {
+ FCOE_INITIATOR_MODE = 0x0,
+ FCOE_TARGET_MODE = 0x1,
+ FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
+ MAX_FCOE_MODE_TYPE
+};
+
+/* Per PF FCoE receive path statistics - tStorm RAM structure */
+struct fcoe_rx_stat {
+ struct regpair fcoe_rx_byte_cnt;
+ struct regpair fcoe_rx_data_pkt_cnt;
+ struct regpair fcoe_rx_xfer_pkt_cnt;
+ struct regpair fcoe_rx_other_pkt_cnt;
+ __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
+ __le32 fcoe_silent_drop_pkt_rq_full_cnt;
+ __le32 fcoe_silent_drop_pkt_crc_error_cnt;
+ __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
+ __le32 fcoe_silent_drop_total_pkt_cnt;
+ __le32 rsrv;
+};
+
+/* FCoE SQE request type */
+enum fcoe_sqe_request_type {
+ SEND_FCOE_CMD,
+ SEND_FCOE_MIDPATH,
+ SEND_FCOE_ABTS_REQUEST,
+ FCOE_EXCHANGE_CLEANUP,
+ FCOE_SEQUENCE_RECOVERY,
+ SEND_FCOE_XFER_RDY,
+ SEND_FCOE_RSP,
+ SEND_FCOE_RSP_WITH_SENSE_DATA,
+ SEND_FCOE_TARGET_DATA,
+ SEND_FCOE_INITIATOR_DATA,
+ SEND_FCOE_XFER_CONTINUATION_RDY,
+ SEND_FCOE_TARGET_ABTS_RSP,
+ MAX_FCOE_SQE_REQUEST_TYPE
+};
+
+/* FCoe statistics request */
+struct fcoe_stat_ramrod_data {
+ struct regpair stat_params_addr;
+};
+
+/* FCoE task type */
+enum fcoe_task_type {
+ FCOE_TASK_TYPE_WRITE_INITIATOR,
+ FCOE_TASK_TYPE_READ_INITIATOR,
+ FCOE_TASK_TYPE_MIDPATH,
+ FCOE_TASK_TYPE_UNSOLICITED,
+ FCOE_TASK_TYPE_ABTS,
+ FCOE_TASK_TYPE_EXCHANGE_CLEANUP,
+ FCOE_TASK_TYPE_SEQUENCE_CLEANUP,
+ FCOE_TASK_TYPE_WRITE_TARGET,
+ FCOE_TASK_TYPE_READ_TARGET,
+ FCOE_TASK_TYPE_RSP,
+ FCOE_TASK_TYPE_RSP_SENSE_DATA,
+ FCOE_TASK_TYPE_ABTS_TARGET,
+ FCOE_TASK_TYPE_ENUM_SIZE,
+ MAX_FCOE_TASK_TYPE
+};
+
+/* Per PF FCoE transmit path statistics - pStorm RAM structure */
struct fcoe_tx_stat {
struct regpair fcoe_tx_byte_cnt;
struct regpair fcoe_tx_data_pkt_cnt;
@@ -618,51 +690,55 @@ struct fcoe_tx_stat {
struct regpair fcoe_tx_other_pkt_cnt;
};
+/* FCoE SQ/XferQ element */
struct fcoe_wqe {
__le16 task_id;
__le16 flags;
-#define FCOE_WQE_REQ_TYPE_MASK 0xF
-#define FCOE_WQE_REQ_TYPE_SHIFT 0
-#define FCOE_WQE_SGL_MODE_MASK 0x1
-#define FCOE_WQE_SGL_MODE_SHIFT 4
-#define FCOE_WQE_CONTINUATION_MASK 0x1
-#define FCOE_WQE_CONTINUATION_SHIFT 5
-#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
-#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
-#define FCOE_WQE_RESERVED_MASK 0x1
-#define FCOE_WQE_RESERVED_SHIFT 7
-#define FCOE_WQE_NUM_SGES_MASK 0xF
-#define FCOE_WQE_NUM_SGES_SHIFT 8
-#define FCOE_WQE_RESERVED1_MASK 0xF
-#define FCOE_WQE_RESERVED1_SHIFT 12
+#define FCOE_WQE_REQ_TYPE_MASK 0xF
+#define FCOE_WQE_REQ_TYPE_SHIFT 0
+#define FCOE_WQE_SGL_MODE_MASK 0x1
+#define FCOE_WQE_SGL_MODE_SHIFT 4
+#define FCOE_WQE_CONTINUATION_MASK 0x1
+#define FCOE_WQE_CONTINUATION_SHIFT 5
+#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
+#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
+#define FCOE_WQE_RESERVED_MASK 0x1
+#define FCOE_WQE_RESERVED_SHIFT 7
+#define FCOE_WQE_NUM_SGES_MASK 0xF
+#define FCOE_WQE_NUM_SGES_SHIFT 8
+#define FCOE_WQE_RESERVED1_MASK 0xF
+#define FCOE_WQE_RESERVED1_SHIFT 12
union fcoe_additional_info_union additional_info_union;
};
+/* FCoE XFRQ element */
struct xfrqe_prot_flags {
u8 flags;
-#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
-#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
-#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
-#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
-#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
-#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
-#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
-#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
+#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
+#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
+#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
+#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
+#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
+#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
+#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
+#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
};
+/* FCoE doorbell data */
struct fcoe_db_data {
u8 params;
-#define FCOE_DB_DATA_DEST_MASK 0x3
-#define FCOE_DB_DATA_DEST_SHIFT 0
-#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
-#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
-#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
-#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
-#define FCOE_DB_DATA_RESERVED_MASK 0x1
-#define FCOE_DB_DATA_RESERVED_SHIFT 5
-#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define FCOE_DB_DATA_DEST_MASK 0x3
+#define FCOE_DB_DATA_DEST_SHIFT 0
+#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
+#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
+#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
+#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
+#define FCOE_DB_DATA_RESERVED_MASK 0x1
+#define FCOE_DB_DATA_RESERVED_SHIFT 5
+#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
+
#endif /* __FCOE_COMMON__ */
diff --git a/include/linux/qed/iscsi_common.h b/include/linux/qed/iscsi_common.h
index 85e086c..64af9b9 100644
--- a/include/linux/qed/iscsi_common.h
+++ b/include/linux/qed/iscsi_common.h
@@ -32,47 +32,48 @@
#ifndef __ISCSI_COMMON__
#define __ISCSI_COMMON__
+
/**********************/
/* ISCSI FW CONSTANTS */
/**********************/
/* iSCSI HSI constants */
-#define ISCSI_DEFAULT_MTU (1500)
+#define ISCSI_DEFAULT_MTU (1500)
/* KWQ (kernel work queue) layer codes */
-#define ISCSI_SLOW_PATH_LAYER_CODE (6)
+#define ISCSI_SLOW_PATH_LAYER_CODE (6)
/* iSCSI parameter defaults */
-#define ISCSI_DEFAULT_HEADER_DIGEST (0)
-#define ISCSI_DEFAULT_DATA_DIGEST (0)
-#define ISCSI_DEFAULT_INITIAL_R2T (1)
-#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
-#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
-#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
-#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
-#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
+#define ISCSI_DEFAULT_HEADER_DIGEST (0)
+#define ISCSI_DEFAULT_DATA_DIGEST (0)
+#define ISCSI_DEFAULT_INITIAL_R2T (1)
+#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
+#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
+#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
+#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
+#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
/* iSCSI parameter limits */
-#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
-#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
-#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
-#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
-#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
-#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
+#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
+#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
+#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
+#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
+#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
+#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
-#define ISCSI_AHS_CNTL_SIZE 4
+#define ISCSI_AHS_CNTL_SIZE 4
-#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
+#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
/* iSCSI reserved params */
#define ISCSI_ITT_ALL_ONES (0xffffffff)
#define ISCSI_TTT_ALL_ONES (0xffffffff)
-#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
-#define ISCSI_OPTION_2_ON_CHIP_TCP 2
+#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
+#define ISCSI_OPTION_2_ON_CHIP_TCP 2
-#define ISCSI_INITIATOR_MODE 0
-#define ISCSI_TARGET_MODE 1
+#define ISCSI_INITIATOR_MODE 0
+#define ISCSI_TARGET_MODE 1
/* iSCSI request op codes */
#define ISCSI_OPCODE_NOP_OUT (0)
@@ -84,41 +85,48 @@
#define ISCSI_OPCODE_LOGOUT_REQUEST (6)
/* iSCSI response/messages op codes */
-#define ISCSI_OPCODE_NOP_IN (0x20)
-#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
-#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
-#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
-#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
-#define ISCSI_OPCODE_DATA_IN (0x25)
-#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
-#define ISCSI_OPCODE_R2T (0x31)
-#define ISCSI_OPCODE_ASYNC_MSG (0x32)
-#define ISCSI_OPCODE_REJECT (0x3f)
+#define ISCSI_OPCODE_NOP_IN (0x20)
+#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
+#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
+#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
+#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
+#define ISCSI_OPCODE_DATA_IN (0x25)
+#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
+#define ISCSI_OPCODE_R2T (0x31)
+#define ISCSI_OPCODE_ASYNC_MSG (0x32)
+#define ISCSI_OPCODE_REJECT (0x3f)
/* iSCSI stages */
-#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
-#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
-#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
+#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
+#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
+#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
/* iSCSI CQE errors */
-#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
+#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
+
+/* Union of data bd_opaque/ tq_tid */
+union bd_opaque_tq_union {
+ __le16 bd_opaque;
+ __le16 tq_tid;
+};
+/* ISCSI SGL entry */
struct cqe_error_bitmap {
u8 cqe_error_status_bits;
-#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
-#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
-#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
-#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
-#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
-#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
+#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
+#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
+#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
+#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
+#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
+#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
};
union cqe_error_status {
@@ -126,86 +134,133 @@ struct cqe_error_bitmap {
struct cqe_error_bitmap error_bits;
};
+/* iSCSI Login Response PDU header */
struct data_hdr {
__le32 data[12];
};
-struct iscsi_async_msg_hdr {
- __le16 reserved0;
- u8 flags_attr;
-#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
-#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
-#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
-#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
- u8 opcode;
- __le32 hdr_second_dword;
-#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
- struct regpair lun;
- __le32 all_ones;
- __le32 reserved1;
- __le32 stat_sn;
- __le32 exp_cmd_sn;
- __le32 max_cmd_sn;
- __le16 param1_rsrv;
- u8 async_vcode;
- u8 async_event;
- __le16 param3_rsrv;
- __le16 param2_rsrv;
- __le32 reserved7;
+struct lun_mapper_addr_reserved {
+ struct regpair lun_mapper_addr;
+ u8 reserved0[8];
+};
+
+/* rdif conetxt for dif on immediate */
+struct dif_on_immediate_params {
+ __le32 initial_ref_tag;
+ __le16 application_tag;
+ __le16 application_tag_mask;
+ __le16 flags1;
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_GUARD_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_GUARD_SHIFT 0
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_APP_TAG_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_APP_TAG_SHIFT 1
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_REF_TAG_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_VALIDATE_REF_TAG_SHIFT 2
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_GUARD_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_GUARD_SHIFT 3
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_SHIFT 4
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_SHIFT 5
+#define DIF_ON_IMMEDIATE_PARAMS_INTERVAL_SIZE_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_INTERVAL_SIZE_SHIFT 6
+#define DIF_ON_IMMEDIATE_PARAMS_NETWORK_INTERFACE_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_NETWORK_INTERFACE_SHIFT 7
+#define DIF_ON_IMMEDIATE_PARAMS_HOST_INTERFACE_MASK 0x3
+#define DIF_ON_IMMEDIATE_PARAMS_HOST_INTERFACE_SHIFT 8
+#define DIF_ON_IMMEDIATE_PARAMS_REF_TAG_MASK_MASK 0xF
+#define DIF_ON_IMMEDIATE_PARAMS_REF_TAG_MASK_SHIFT 10
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
+ u8 flags0;
+#define DIF_ON_IMMEDIATE_PARAMS_RESERVED_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_RESERVED_SHIFT 0
+#define DIF_ON_IMMEDIATE_PARAMS_IGNORE_APP_TAG_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_IGNORE_APP_TAG_SHIFT 1
+#define DIF_ON_IMMEDIATE_PARAMS_INITIAL_REF_TAG_IS_VALID_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_INITIAL_REF_TAG_IS_VALID_SHIFT 2
+#define DIF_ON_IMMEDIATE_PARAMS_HOST_GUARD_TYPE_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_HOST_GUARD_TYPE_SHIFT 3
+#define DIF_ON_IMMEDIATE_PARAMS_PROTECTION_TYPE_MASK 0x3
+#define DIF_ON_IMMEDIATE_PARAMS_PROTECTION_TYPE_SHIFT 4
+#define DIF_ON_IMMEDIATE_PARAMS_CRC_SEED_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_CRC_SEED_SHIFT 6
+#define DIF_ON_IMMEDIATE_PARAMS_KEEP_REF_TAG_CONST_MASK 0x1
+#define DIF_ON_IMMEDIATE_PARAMS_KEEP_REF_TAG_CONST_SHIFT 7
+ u8 reserved_zero[5];
+};
+
+/* iSCSI dif on immediate mode attributes union */
+union dif_configuration_params {
+ struct lun_mapper_addr_reserved lun_mapper_address;
+ struct dif_on_immediate_params def_dif_conf;
+};
+
+/* Union of data/r2t sequence number */
+union iscsi_seq_num {
+ __le16 data_sn;
+ __le16 r2t_sn;
};
-struct iscsi_cmd_hdr {
- __le16 reserved1;
- u8 flags_attr;
-#define ISCSI_CMD_HDR_ATTR_MASK 0x7
-#define ISCSI_CMD_HDR_ATTR_SHIFT 0
-#define ISCSI_CMD_HDR_RSRV_MASK 0x3
-#define ISCSI_CMD_HDR_RSRV_SHIFT 3
-#define ISCSI_CMD_HDR_WRITE_MASK 0x1
-#define ISCSI_CMD_HDR_WRITE_SHIFT 5
-#define ISCSI_CMD_HDR_READ_MASK 0x1
-#define ISCSI_CMD_HDR_READ_SHIFT 6
-#define ISCSI_CMD_HDR_FINAL_MASK 0x1
-#define ISCSI_CMD_HDR_FINAL_SHIFT 7
- u8 hdr_first_byte;
-#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
-#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
-#define ISCSI_CMD_HDR_IMM_MASK 0x1
-#define ISCSI_CMD_HDR_IMM_SHIFT 6
-#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
-#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
- __le32 hdr_second_dword;
-#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
- struct regpair lun;
- __le32 itt;
- __le32 expected_transfer_length;
- __le32 cmd_sn;
- __le32 exp_stat_sn;
- __le32 cdb[4];
+/* iSCSI DIF flags */
+struct iscsi_dif_flags {
+ u8 flags;
+#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
+#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
+#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
+#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
+#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
+#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
};
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_state {
+ struct scsi_cached_sges data_desc;
+ struct scsi_sgl_params sgl_params;
+ __le32 exp_r2t_sn;
+ __le32 buffer_offset;
+ union iscsi_seq_num seq_num;
+ struct iscsi_dif_flags dif_flags;
+ u8 flags;
+#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
+#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
+#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
+#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
+#define YSTORM_ISCSI_TASK_STATE_SET_DIF_OFFSET_MASK 0x1
+#define YSTORM_ISCSI_TASK_STATE_SET_DIF_OFFSET_SHIFT 2
+#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x1F
+#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 3
+};
+
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_rxmit_opt {
+ __le32 fast_rxmit_sge_offset;
+ __le32 scan_start_buffer_offset;
+ __le32 fast_rxmit_buffer_offset;
+ u8 scan_start_sgl_index;
+ u8 fast_rxmit_sgl_index;
+ __le16 reserved;
+};
+
+/* iSCSI Common PDU header */
struct iscsi_common_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 hdr_first_byte;
-#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
-#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
-#define ISCSI_COMMON_HDR_IMM_MASK 0x1
-#define ISCSI_COMMON_HDR_IMM_SHIFT 6
-#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
-#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
+#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
+#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
+#define ISCSI_COMMON_HDR_IMM_MASK 0x1
+#define ISCSI_COMMON_HDR_IMM_SHIFT 6
+#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
+#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
__le32 hdr_second_dword;
-#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun_reserved;
__le32 itt;
__le32 ttt;
@@ -215,86 +270,60 @@ struct iscsi_common_hdr {
__le32 data[3];
};
-struct iscsi_conn_offload_params {
- struct regpair sq_pbl_addr;
- struct regpair r2tq_pbl_addr;
- struct regpair xhq_pbl_addr;
- struct regpair uhq_pbl_addr;
- __le32 initial_ack;
- __le16 physical_q0;
- __le16 physical_q1;
- u8 flags;
-#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
-#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
- u8 pbl_page_size_log;
- u8 pbe_page_size_log;
- u8 default_cq;
- __le32 stat_sn;
-};
-
-struct iscsi_slow_path_hdr {
- u8 op_code;
- u8 flags;
-#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
-#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
-#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
-#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
-#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
-#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
-};
-
-struct iscsi_conn_update_ramrod_params {
- struct iscsi_slow_path_hdr hdr;
- __le16 conn_id;
- __le32 fw_cid;
- u8 flags;
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
- u8 reserved0[3];
- __le32 max_seq_size;
- __le32 max_send_pdu_length;
- __le32 max_recv_pdu_length;
- __le32 first_seq_length;
+/* iSCSI Command PDU header */
+struct iscsi_cmd_hdr {
+ __le16 reserved1;
+ u8 flags_attr;
+#define ISCSI_CMD_HDR_ATTR_MASK 0x7
+#define ISCSI_CMD_HDR_ATTR_SHIFT 0
+#define ISCSI_CMD_HDR_RSRV_MASK 0x3
+#define ISCSI_CMD_HDR_RSRV_SHIFT 3
+#define ISCSI_CMD_HDR_WRITE_MASK 0x1
+#define ISCSI_CMD_HDR_WRITE_SHIFT 5
+#define ISCSI_CMD_HDR_READ_MASK 0x1
+#define ISCSI_CMD_HDR_READ_SHIFT 6
+#define ISCSI_CMD_HDR_FINAL_MASK 0x1
+#define ISCSI_CMD_HDR_FINAL_SHIFT 7
+ u8 hdr_first_byte;
+#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
+#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
+#define ISCSI_CMD_HDR_IMM_MASK 0x1
+#define ISCSI_CMD_HDR_IMM_SHIFT 6
+#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
+#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
+ __le32 hdr_second_dword;
+#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
+ struct regpair lun;
+ __le32 itt;
+ __le32 expected_transfer_length;
+ __le32 cmd_sn;
__le32 exp_stat_sn;
+ __le32 cdb[4];
};
+/* iSCSI Command PDU header with Extended CDB (Initiator Mode) */
struct iscsi_ext_cdb_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
-#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
-#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
-#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
-#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
-#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
-#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
+#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
+#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
+#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
+#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
+#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
+#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
+#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
-#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
+#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
+#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 expected_transfer_length;
@@ -303,26 +332,27 @@ struct iscsi_ext_cdb_cmd_hdr {
struct scsi_sge cdb_sge;
};
+/* iSCSI login request PDU header */
struct iscsi_login_req_hdr {
u8 version_min;
u8 version_max;
u8 flags_attr;
-#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
-#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
-#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
-#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
-#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
-#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
-#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
+#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
+#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
+#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
+#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
+#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
+#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
+#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
@@ -334,6 +364,7 @@ struct iscsi_login_req_hdr {
__le32 reserved2[4];
};
+/* iSCSI logout request PDU header */
struct iscsi_logout_req_hdr {
__le16 reserved0;
u8 reason_code;
@@ -348,13 +379,14 @@ struct iscsi_logout_req_hdr {
__le32 reserved4[4];
};
+/* iSCSI Data-out PDU header */
struct iscsi_data_out_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
-#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
-#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
-#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
+#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
+#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
+#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
+#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -368,22 +400,23 @@ struct iscsi_data_out_hdr {
__le32 reserved5;
};
+/* iSCSI Data-in PDU header */
struct iscsi_data_in_hdr {
u8 status_rsvd;
u8 reserved1;
u8 flags;
-#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
-#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
-#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
-#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
-#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
-#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
-#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
-#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
-#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
-#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
-#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
-#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
+#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
+#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
+#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
+#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
+#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
+#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
+#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
+#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
+#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
+#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
+#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
+#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -397,6 +430,7 @@ struct iscsi_data_in_hdr {
__le32 residual_count;
};
+/* iSCSI R2T PDU header */
struct iscsi_r2t_hdr {
u8 reserved0[3];
u8 opcode;
@@ -412,13 +446,14 @@ struct iscsi_r2t_hdr {
__le32 desired_data_trns_len;
};
+/* iSCSI NOP-out PDU header */
struct iscsi_nop_out_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
-#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
-#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
-#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
+#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
+#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
+#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
+#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -432,19 +467,20 @@ struct iscsi_nop_out_hdr {
__le32 reserved6;
};
+/* iSCSI NOP-in PDU header */
struct iscsi_nop_in_hdr {
__le16 reserved0;
u8 flags_attr;
-#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
-#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
-#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
-#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
+#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
+#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
+#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
+#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -456,26 +492,27 @@ struct iscsi_nop_in_hdr {
__le32 reserved7;
};
+/* iSCSI Login Response PDU header */
struct iscsi_login_response_hdr {
u8 version_active;
u8 version_max;
u8 flags_attr;
-#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
-#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
-#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
-#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
-#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
-#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
-#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
+#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
+#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
+#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
+#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
+#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
+#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
+#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
@@ -490,16 +527,17 @@ struct iscsi_login_response_hdr {
__le32 reserved4[2];
};
+/* iSCSI Logout Response PDU header */
struct iscsi_logout_response_hdr {
u8 reserved1;
u8 response;
u8 flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 reserved2[2];
__le32 itt;
__le32 reserved3;
@@ -512,21 +550,22 @@ struct iscsi_logout_response_hdr {
__le32 reserved5[1];
};
+/* iSCSI Text Request PDU header */
struct iscsi_text_request_hdr {
__le16 reserved0;
u8 flags_attr;
-#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
-#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
-#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
-#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
-#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
-#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
+#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
+#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
+#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
+#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
+#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
+#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -535,21 +574,22 @@ struct iscsi_text_request_hdr {
__le32 reserved4[4];
};
+/* iSCSI Text Response PDU header */
struct iscsi_text_response_hdr {
__le16 reserved1;
u8 flags;
-#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
-#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
-#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
-#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
-#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
-#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
+#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
+#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
+#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
+#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
+#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
+#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -559,15 +599,16 @@ struct iscsi_text_response_hdr {
__le32 reserved4[3];
};
+/* iSCSI TMF Request PDU header */
struct iscsi_tmf_request_hdr {
__le16 reserved0;
u8 function;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 rtt;
@@ -584,10 +625,10 @@ struct iscsi_tmf_response_hdr {
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 itt;
__le32 reserved1;
@@ -597,16 +638,17 @@ struct iscsi_tmf_response_hdr {
__le32 reserved4[3];
};
+/* iSCSI Response PDU header */
struct iscsi_response_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 snack_tag;
@@ -618,16 +660,17 @@ struct iscsi_response_hdr {
__le32 residual_count;
};
+/* iSCSI Reject PDU header */
struct iscsi_reject_hdr {
u8 reserved4;
u8 hdr_reason;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 all_ones;
__le32 reserved2;
@@ -638,6 +681,35 @@ struct iscsi_reject_hdr {
__le32 reserved3[2];
};
+/* iSCSI Asynchronous Message PDU header */
+struct iscsi_async_msg_hdr {
+ __le16 reserved0;
+ u8 flags_attr;
+#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
+#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
+#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
+#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
+ u8 opcode;
+ __le32 hdr_second_dword;
+#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
+ struct regpair lun;
+ __le32 all_ones;
+ __le32 reserved1;
+ __le32 stat_sn;
+ __le32 exp_cmd_sn;
+ __le32 max_cmd_sn;
+ __le16 param1_rsrv;
+ u8 async_vcode;
+ u8 async_event;
+ __le16 param3_rsrv;
+ __le16 param2_rsrv;
+ __le32 reserved7;
+};
+
+/* PDU header part of Ystorm task context */
union iscsi_task_hdr {
struct iscsi_common_hdr common;
struct data_hdr data;
@@ -661,6 +733,348 @@ struct iscsi_reject_hdr {
struct iscsi_async_msg_hdr async_msg;
};
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_st_ctx {
+ struct ystorm_iscsi_task_state state;
+ struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
+ union iscsi_task_hdr pdu_hdr;
+};
+
+struct e4_ystorm_iscsi_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 word0;
+ u8 flags0;
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 byte2;
+ __le32 TTT;
+ u8 byte3;
+ u8 byte4;
+ __le16 word1;
+};
+
+struct e4_mstorm_iscsi_task_ag_ctx {
+ u8 cdu_validation;
+ u8 byte1;
+ __le16 task_cid;
+ u8 flags0;
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
+ u8 flags1;
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 byte2;
+ __le32 reg0;
+ u8 byte3;
+ u8 byte4;
+ __le16 word1;
+};
+
+struct e4_ustorm_iscsi_task_ag_ctx {
+ u8 reserved;
+ u8 state;
+ __le16 icid;
+ u8 flags0;
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
+ u8 flags1;
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+ u8 flags2;
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
+ u8 flags3;
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+ __le32 dif_err_intervals;
+ __le32 dif_error_1st_interval;
+ __le32 rcv_cont_len;
+ __le32 exp_cont_len;
+ __le32 total_data_acked;
+ __le32 exp_data_acked;
+ u8 next_tid_valid;
+ u8 byte3;
+ __le16 word1;
+ __le16 next_tid;
+ __le16 word3;
+ __le32 hdr_residual_count;
+ __le32 exp_r2t_sn;
+};
+
+/* The iscsi storm task context of Mstorm */
+struct mstorm_iscsi_task_st_ctx {
+ struct scsi_cached_sges data_desc;
+ struct scsi_sgl_params sgl_params;
+ __le32 rem_task_size;
+ __le32 data_buffer_offset;
+ u8 task_type;
+ struct iscsi_dif_flags dif_flags;
+ __le16 dif_task_icid;
+ struct regpair sense_db;
+ __le32 expected_itt;
+ __le32 reserved1;
+};
+
+struct iscsi_reg1 {
+ __le32 reg1_map;
+#define ISCSI_REG1_NUM_SGES_MASK 0xF
+#define ISCSI_REG1_NUM_SGES_SHIFT 0
+#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
+#define ISCSI_REG1_RESERVED1_SHIFT 4
+};
+
+struct tqe_opaque {
+ __le16 opaque[2];
+};
+
+/* The iscsi storm task context of Ustorm */
+struct ustorm_iscsi_task_st_ctx {
+ __le32 rem_rcv_len;
+ __le32 exp_data_transfer_len;
+ __le32 exp_data_sn;
+ struct regpair lun;
+ struct iscsi_reg1 reg1;
+ u8 flags2;
+#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
+ struct iscsi_dif_flags dif_flags;
+ __le16 reserved3;
+ struct tqe_opaque tqe_opaque_list;
+ __le32 reserved5;
+ __le32 reserved6;
+ __le32 reserved7;
+ u8 task_type;
+ u8 error_flags;
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
+#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
+ u8 flags;
+#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
+#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
+#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
+#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
+#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
+#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
+ u8 cq_rss_number;
+};
+
+/* iscsi task context */
+struct e4_iscsi_task_context {
+ struct ystorm_iscsi_task_st_ctx ystorm_st_context;
+ struct e4_ystorm_iscsi_task_ag_ctx ystorm_ag_context;
+ struct regpair ystorm_ag_padding[2];
+ struct tdif_task_context tdif_context;
+ struct e4_mstorm_iscsi_task_ag_ctx mstorm_ag_context;
+ struct regpair mstorm_ag_padding[2];
+ struct e4_ustorm_iscsi_task_ag_ctx ustorm_ag_context;
+ struct mstorm_iscsi_task_st_ctx mstorm_st_context;
+ struct ustorm_iscsi_task_st_ctx ustorm_st_context;
+ struct rdif_task_context rdif_context;
+};
+
+/* iSCSI connection offload params passed by driver to FW in ISCSI offload
+ * ramrod.
+ */
+struct iscsi_conn_offload_params {
+ struct regpair sq_pbl_addr;
+ struct regpair r2tq_pbl_addr;
+ struct regpair xhq_pbl_addr;
+ struct regpair uhq_pbl_addr;
+ __le32 initial_ack;
+ __le16 physical_q0;
+ __le16 physical_q1;
+ u8 flags;
+#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
+#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
+ u8 pbl_page_size_log;
+ u8 pbe_page_size_log;
+ u8 default_cq;
+ __le32 stat_sn;
+};
+
+/* iSCSI connection statistics */
+struct iscsi_conn_stats_params {
+ struct regpair iscsi_tcp_tx_packets_cnt;
+ struct regpair iscsi_tcp_tx_bytes_cnt;
+ struct regpair iscsi_tcp_tx_rxmit_cnt;
+ struct regpair iscsi_tcp_rx_packets_cnt;
+ struct regpair iscsi_tcp_rx_bytes_cnt;
+ struct regpair iscsi_tcp_rx_dup_ack_cnt;
+ __le32 iscsi_tcp_rx_chksum_err_cnt;
+ __le32 reserved;
+};
+
+/* spe message header */
+struct iscsi_slow_path_hdr {
+ u8 op_code;
+ u8 flags;
+#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
+#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
+#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
+#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
+#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
+#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
+};
+
+/* iSCSI connection update params passed by driver to FW in ISCSI update
+ *ramrod.
+ */
+struct iscsi_conn_update_ramrod_params {
+ struct iscsi_slow_path_hdr hdr;
+ __le16 conn_id;
+ __le32 fw_cid;
+ u8 flags;
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_IMM_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_IMM_EN_SHIFT 6
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_LUN_MAPPER_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_LUN_MAPPER_EN_SHIFT 7
+ u8 reserved0[3];
+ __le32 max_seq_size;
+ __le32 max_send_pdu_length;
+ __le32 max_recv_pdu_length;
+ __le32 first_seq_length;
+ __le32 exp_stat_sn;
+ union dif_configuration_params dif_on_imme_params;
+};
+
+/* iSCSI CQ element */
struct iscsi_cqe_common {
__le16 conn_id;
u8 cqe_type;
@@ -669,6 +1083,7 @@ struct iscsi_cqe_common {
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
struct iscsi_cqe_solicited {
__le16 conn_id;
u8 cqe_type;
@@ -678,10 +1093,11 @@ struct iscsi_cqe_solicited {
u8 fw_dbg_field;
u8 caused_conn_err;
u8 reserved0[3];
- __le32 reserved1[1];
+ __le32 data_truncated_bytes;
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
struct iscsi_cqe_unsolicited {
__le16 conn_id;
u8 cqe_type;
@@ -689,16 +1105,19 @@ struct iscsi_cqe_unsolicited {
__le16 reserved0;
u8 reserved1;
u8 unsol_cqe_type;
- struct regpair rqe_opaque;
+ __le16 rqe_opaque;
+ __le16 reserved2[3];
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
union iscsi_cqe {
struct iscsi_cqe_common cqe_common;
struct iscsi_cqe_solicited cqe_solicited;
struct iscsi_cqe_unsolicited cqe_unsolicited;
};
+/* iSCSI CQE type */
enum iscsi_cqes_type {
ISCSI_CQE_TYPE_SOLICITED = 1,
ISCSI_CQE_TYPE_UNSOLICITED,
@@ -708,6 +1127,7 @@ enum iscsi_cqes_type {
MAX_ISCSI_CQES_TYPE
};
+/* iSCSI CQE type */
enum iscsi_cqe_unsolicited_type {
ISCSI_CQE_UNSOLICITED_NONE,
ISCSI_CQE_UNSOLICITED_SINGLE,
@@ -717,37 +1137,28 @@ enum iscsi_cqe_unsolicited_type {
MAX_ISCSI_CQE_UNSOLICITED_TYPE
};
-
+/* iscsi debug modes */
struct iscsi_debug_modes {
u8 flags;
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7
-};
-
-struct iscsi_dif_flags {
- u8 flags;
-#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
-#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
-#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
-#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
-#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
-#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
-};
-
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_OR_DATA_DIGEST_ERROR_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_OR_DATA_DIGEST_ERROR_SHIFT 6
+#define ISCSI_DEBUG_MODES_ASSERT_IF_HQ_CORRUPT_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_HQ_CORRUPT_SHIFT 7
+};
+
+/* iSCSI kernel completion queue IDs */
enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_INIT_FUNC = 0,
ISCSI_EVENT_TYPE_DESTROY_FUNC,
@@ -756,9 +1167,9 @@ enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_CLEAR_SQ,
ISCSI_EVENT_TYPE_TERMINATE_CONN,
ISCSI_EVENT_TYPE_MAC_UPDATE_CONN,
+ ISCSI_EVENT_TYPE_COLLECT_STATS_CONN,
ISCSI_EVENT_TYPE_ASYN_CONNECT_COMPLETE,
ISCSI_EVENT_TYPE_ASYN_TERMINATE_DONE,
- RESERVED9,
ISCSI_EVENT_TYPE_START_OF_ERROR_TYPES = 10,
ISCSI_EVENT_TYPE_ASYN_ABORT_RCVD,
ISCSI_EVENT_TYPE_ASYN_CLOSE_RCVD,
@@ -772,6 +1183,7 @@ enum iscsi_eqe_opcode {
MAX_ISCSI_EQE_OPCODE
};
+/* iSCSI EQE and CQE completion status */
enum iscsi_error_types {
ISCSI_STATUS_NONE = 0,
ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN = 1,
@@ -823,7 +1235,7 @@ enum iscsi_error_types {
MAX_ISCSI_ERROR_TYPES
};
-
+/* iSCSI Ramrod Command IDs */
enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_UNUSED = 0,
ISCSI_RAMROD_CMD_ID_INIT_FUNC = 1,
@@ -833,22 +1245,11 @@ enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_TERMINATION_CONN = 5,
ISCSI_RAMROD_CMD_ID_CLEAR_SQ = 6,
ISCSI_RAMROD_CMD_ID_MAC_UPDATE = 7,
+ ISCSI_RAMROD_CMD_ID_CONN_STATS = 8,
MAX_ISCSI_RAMROD_CMD_ID
};
-struct iscsi_reg1 {
- __le32 reg1_map;
-#define ISCSI_REG1_NUM_SGES_MASK 0xF
-#define ISCSI_REG1_NUM_SGES_SHIFT 0
-#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
-#define ISCSI_REG1_RESERVED1_SHIFT 4
-};
-
-union iscsi_seq_num {
- __le16 data_sn;
- __le16 r2t_sn;
-};
-
+/* iSCSI connection termination request */
struct iscsi_spe_conn_mac_update {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -859,6 +1260,9 @@ struct iscsi_spe_conn_mac_update {
u8 reserved0[2];
};
+/* iSCSI and TCP connection (Option 1) offload params passed by driver to FW in
+ * iSCSI offload ramrod.
+ */
struct iscsi_spe_conn_offload {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -867,6 +1271,9 @@ struct iscsi_spe_conn_offload {
struct tcp_offload_params tcp;
};
+/* iSCSI and TCP connection(Option 2) offload params passed by driver to FW in
+ * iSCSI offload ramrod.
+ */
struct iscsi_spe_conn_offload_option2 {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -875,6 +1282,17 @@ struct iscsi_spe_conn_offload_option2 {
struct tcp_offload_params_opt2 tcp;
};
+/* iSCSI collect connection statistics request */
+struct iscsi_spe_conn_statistics {
+ struct iscsi_slow_path_hdr hdr;
+ __le16 conn_id;
+ __le32 fw_cid;
+ u8 reset_stats;
+ u8 reserved0[7];
+ struct regpair stats_cnts_addr;
+};
+
+/* iSCSI connection termination request */
struct iscsi_spe_conn_termination {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -885,12 +1303,14 @@ struct iscsi_spe_conn_termination {
struct regpair query_params_addr;
};
+/* iSCSI firmware function destroy parameters */
struct iscsi_spe_func_dstry {
struct iscsi_slow_path_hdr hdr;
__le16 reserved0;
__le32 reserved1;
};
+/* iSCSI firmware function init parameters */
struct iscsi_spe_func_init {
struct iscsi_slow_path_hdr hdr;
__le16 half_way_close_timeout;
@@ -898,283 +1318,19 @@ struct iscsi_spe_func_init {
u8 num_r2tq_pages_in_ring;
u8 num_uhq_pages_in_ring;
u8 ll2_rx_queue_id;
- u8 ooo_enable;
+ u8 flags;
+#define ISCSI_SPE_FUNC_INIT_COUNTERS_EN_MASK 0x1
+#define ISCSI_SPE_FUNC_INIT_COUNTERS_EN_SHIFT 0
+#define ISCSI_SPE_FUNC_INIT_RESERVED0_MASK 0x7F
+#define ISCSI_SPE_FUNC_INIT_RESERVED0_SHIFT 1
struct iscsi_debug_modes debug_mode;
__le16 reserved1;
__le32 reserved2;
- __le32 reserved3;
- __le32 reserved4;
struct scsi_init_func_params func_params;
struct scsi_init_func_queues q_params;
};
-struct ystorm_iscsi_task_state {
- struct scsi_cached_sges data_desc;
- struct scsi_sgl_params sgl_params;
- __le32 exp_r2t_sn;
- __le32 buffer_offset;
- union iscsi_seq_num seq_num;
- struct iscsi_dif_flags dif_flags;
- u8 flags;
-#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
-#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
-#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
-#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
-#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
-#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
-};
-
-struct ystorm_iscsi_task_rxmit_opt {
- __le32 fast_rxmit_sge_offset;
- __le32 scan_start_buffer_offset;
- __le32 fast_rxmit_buffer_offset;
- u8 scan_start_sgl_index;
- u8 fast_rxmit_sgl_index;
- __le16 reserved;
-};
-
-struct ystorm_iscsi_task_st_ctx {
- struct ystorm_iscsi_task_state state;
- struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
- union iscsi_task_hdr pdu_hdr;
-};
-
-struct ystorm_iscsi_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 word0;
- u8 flags0;
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 byte2;
- __le32 TTT;
- u8 byte3;
- u8 byte4;
- __le16 word1;
-};
-
-struct mstorm_iscsi_task_ag_ctx {
- u8 cdu_validation;
- u8 byte1;
- __le16 task_cid;
- u8 flags0;
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
- u8 flags1;
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 byte2;
- __le32 reg0;
- u8 byte3;
- u8 byte4;
- __le16 word1;
-};
-
-struct ustorm_iscsi_task_ag_ctx {
- u8 reserved;
- u8 state;
- __le16 icid;
- u8 flags0;
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
- u8 flags1;
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
- u8 flags2;
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
- u8 flags3;
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
- __le32 dif_err_intervals;
- __le32 dif_error_1st_interval;
- __le32 rcv_cont_len;
- __le32 exp_cont_len;
- __le32 total_data_acked;
- __le32 exp_data_acked;
- u8 next_tid_valid;
- u8 byte3;
- __le16 word1;
- __le16 next_tid;
- __le16 word3;
- __le32 hdr_residual_count;
- __le32 exp_r2t_sn;
-};
-
-struct mstorm_iscsi_task_st_ctx {
- struct scsi_cached_sges data_desc;
- struct scsi_sgl_params sgl_params;
- __le32 rem_task_size;
- __le32 data_buffer_offset;
- u8 task_type;
- struct iscsi_dif_flags dif_flags;
- u8 reserved0[2];
- struct regpair sense_db;
- __le32 expected_itt;
- __le32 reserved1;
-};
-
-struct ustorm_iscsi_task_st_ctx {
- __le32 rem_rcv_len;
- __le32 exp_data_transfer_len;
- __le32 exp_data_sn;
- struct regpair lun;
- struct iscsi_reg1 reg1;
- u8 flags2;
-#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
- struct iscsi_dif_flags dif_flags;
- __le16 reserved3;
- __le32 reserved4;
- __le32 reserved5;
- __le32 reserved6;
- __le32 reserved7;
- u8 task_type;
- u8 error_flags;
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
-#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
- u8 flags;
-#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
-#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
-#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
-#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
-#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
-#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
- u8 cq_rss_number;
-};
-
-struct iscsi_task_context {
- struct ystorm_iscsi_task_st_ctx ystorm_st_context;
- struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
- struct regpair ystorm_ag_padding[2];
- struct tdif_task_context tdif_context;
- struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
- struct regpair mstorm_ag_padding[2];
- struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
- struct mstorm_iscsi_task_st_ctx mstorm_st_context;
- struct ustorm_iscsi_task_st_ctx ustorm_st_context;
- struct rdif_task_context rdif_context;
-};
-
+/* iSCSI task type */
enum iscsi_task_type {
ISCSI_TASK_TYPE_INITIATOR_WRITE,
ISCSI_TASK_TYPE_INITIATOR_READ,
@@ -1186,53 +1342,57 @@ enum iscsi_task_type {
ISCSI_TASK_TYPE_TARGET_READ,
ISCSI_TASK_TYPE_TARGET_RESPONSE,
ISCSI_TASK_TYPE_LOGIN_RESPONSE,
+ ISCSI_TASK_TYPE_TARGET_IMM_W_DIF,
MAX_ISCSI_TASK_TYPE
};
+/* iSCSI DesiredDataTransferLength/ttt union */
union iscsi_ttt_txlen_union {
__le32 desired_tx_len;
__le32 ttt;
};
+/* iSCSI uHQ element */
struct iscsi_uhqe {
__le32 reg1;
-#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
-#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
-#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
-#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
-#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
-#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
-#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
-#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
-#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
-#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
-#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
-#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
+#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
+#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
+#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
+#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
+#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
+#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
+#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
+#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
+#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
+#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
+#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
+#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
__le32 reg2;
-#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
-#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
-#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
-#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
+#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
+#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
+#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
+#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
};
-
+/* iSCSI WQ element */
struct iscsi_wqe {
__le16 task_id;
u8 flags;
-#define ISCSI_WQE_WQE_TYPE_MASK 0x7
-#define ISCSI_WQE_WQE_TYPE_SHIFT 0
-#define ISCSI_WQE_NUM_SGES_MASK 0xF
-#define ISCSI_WQE_NUM_SGES_SHIFT 3
-#define ISCSI_WQE_RESPONSE_MASK 0x1
-#define ISCSI_WQE_RESPONSE_SHIFT 7
+#define ISCSI_WQE_WQE_TYPE_MASK 0x7
+#define ISCSI_WQE_WQE_TYPE_SHIFT 0
+#define ISCSI_WQE_NUM_SGES_MASK 0xF
+#define ISCSI_WQE_NUM_SGES_SHIFT 3
+#define ISCSI_WQE_RESPONSE_MASK 0x1
+#define ISCSI_WQE_RESPONSE_SHIFT 7
struct iscsi_dif_flags prot_flags;
__le32 contlen_cdbsize;
-#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
-#define ISCSI_WQE_CONT_LEN_SHIFT 0
-#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
-#define ISCSI_WQE_CDB_SIZE_SHIFT 24
+#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
+#define ISCSI_WQE_CONT_LEN_SHIFT 0
+#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
+#define ISCSI_WQE_CDB_SIZE_SHIFT 24
};
+/* iSCSI wqe type */
enum iscsi_wqe_type {
ISCSI_WQE_TYPE_NORMAL,
ISCSI_WQE_TYPE_TASK_CLEANUP,
@@ -1244,6 +1404,7 @@ enum iscsi_wqe_type {
MAX_ISCSI_WQE_TYPE
};
+/* iSCSI xHQ element */
struct iscsi_xhqe {
union iscsi_ttt_txlen_union ttt_or_txlen;
__le32 exp_stat_sn;
@@ -1251,120 +1412,134 @@ struct iscsi_xhqe {
u8 total_ahs_length;
u8 opcode;
u8 flags;
-#define ISCSI_XHQE_FINAL_MASK 0x1
-#define ISCSI_XHQE_FINAL_SHIFT 0
-#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
-#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
-#define ISCSI_XHQE_NUM_SGES_MASK 0xF
-#define ISCSI_XHQE_NUM_SGES_SHIFT 2
-#define ISCSI_XHQE_RESERVED0_MASK 0x3
-#define ISCSI_XHQE_RESERVED0_SHIFT 6
+#define ISCSI_XHQE_FINAL_MASK 0x1
+#define ISCSI_XHQE_FINAL_SHIFT 0
+#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
+#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
+#define ISCSI_XHQE_NUM_SGES_MASK 0xF
+#define ISCSI_XHQE_NUM_SGES_SHIFT 2
+#define ISCSI_XHQE_RESERVED0_MASK 0x3
+#define ISCSI_XHQE_RESERVED0_SHIFT 6
union iscsi_seq_num seq_num;
__le16 reserved1;
};
+/* Per PF iSCSI receive path statistics - mStorm RAM structure */
struct mstorm_iscsi_stats_drv {
struct regpair iscsi_rx_dropped_pdus_task_not_valid;
+ struct regpair iscsi_rx_dup_ack_cnt;
};
+/* Per PF iSCSI transmit path statistics - pStorm RAM structure */
struct pstorm_iscsi_stats_drv {
struct regpair iscsi_tx_bytes_cnt;
struct regpair iscsi_tx_packet_cnt;
};
+/* Per PF iSCSI receive path statistics - tStorm RAM structure */
struct tstorm_iscsi_stats_drv {
struct regpair iscsi_rx_bytes_cnt;
struct regpair iscsi_rx_packet_cnt;
struct regpair iscsi_rx_new_ooo_isle_events_cnt;
+ struct regpair iscsi_rx_tcp_payload_bytes_cnt;
+ struct regpair iscsi_rx_tcp_pkt_cnt;
+ struct regpair iscsi_rx_pure_ack_cnt;
__le32 iscsi_cmdq_threshold_cnt;
__le32 iscsi_rq_threshold_cnt;
__le32 iscsi_immq_threshold_cnt;
};
+/* Per PF iSCSI receive path statistics - uStorm RAM structure */
struct ustorm_iscsi_stats_drv {
struct regpair iscsi_rx_data_pdu_cnt;
struct regpair iscsi_rx_r2t_pdu_cnt;
struct regpair iscsi_rx_total_pdu_cnt;
};
+/* Per PF iSCSI transmit path statistics - xStorm RAM structure */
struct xstorm_iscsi_stats_drv {
struct regpair iscsi_tx_go_to_slow_start_event_cnt;
struct regpair iscsi_tx_fast_retransmit_event_cnt;
+ struct regpair iscsi_tx_pure_ack_cnt;
+ struct regpair iscsi_tx_delayed_ack_cnt;
};
+/* Per PF iSCSI transmit path statistics - yStorm RAM structure */
struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_data_pdu_cnt;
struct regpair iscsi_tx_r2t_pdu_cnt;
struct regpair iscsi_tx_total_pdu_cnt;
+ struct regpair iscsi_tx_tcp_payload_bytes_cnt;
+ struct regpair iscsi_tx_tcp_pkt_cnt;
};
-struct tstorm_iscsi_task_ag_ctx {
+struct e4_tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
@@ -1376,18 +1551,20 @@ struct tstorm_iscsi_task_ag_ctx {
__le32 reg1;
__le32 reg2;
};
+
+/* iSCSI doorbell data */
struct iscsi_db_data {
u8 params;
-#define ISCSI_DB_DATA_DEST_MASK 0x3
-#define ISCSI_DB_DATA_DEST_SHIFT 0
-#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
-#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
-#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
-#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
-#define ISCSI_DB_DATA_RESERVED_MASK 0x1
-#define ISCSI_DB_DATA_RESERVED_SHIFT 5
-#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define ISCSI_DB_DATA_DEST_MASK 0x3
+#define ISCSI_DB_DATA_DEST_SHIFT 0
+#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
+#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
+#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
+#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
+#define ISCSI_DB_DATA_RESERVED_MASK 0x1
+#define ISCSI_DB_DATA_RESERVED_SHIFT 5
+#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
diff --git a/include/linux/qed/iwarp_common.h b/include/linux/qed/iwarp_common.h
index b8b3e1c..c6cfd39 100644
--- a/include/linux/qed/iwarp_common.h
+++ b/include/linux/qed/iwarp_common.h
@@ -29,9 +29,12 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
+
#ifndef __IWARP_COMMON__
#define __IWARP_COMMON__
+
#include <linux/qed/rdma_common.h>
+
/************************/
/* IWARP FW CONSTANTS */
/************************/
@@ -40,14 +43,14 @@
#define IWARP_PASSIVE_MODE 1
#define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000)
-#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
-#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
-#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
-#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
+#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
+#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
+#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
+#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
-#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128)
-#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176)
+#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128)
+#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176)
-#define IWARP_MAX_QPS (64 * 1024)
+#define IWARP_MAX_QPS (64 * 1024)
#endif /* __IWARP_COMMON__ */
diff --git a/include/linux/qed/qed_eth_if.h b/include/linux/qed/qed_eth_if.h
index d60de4a..147d08c 100644
--- a/include/linux/qed/qed_eth_if.h
+++ b/include/linux/qed/qed_eth_if.h
@@ -61,6 +61,35 @@ struct qed_txq_start_ret_params {
void *p_handle;
};
+enum qed_filter_config_mode {
+ QED_FILTER_CONFIG_MODE_DISABLE,
+ QED_FILTER_CONFIG_MODE_5_TUPLE,
+ QED_FILTER_CONFIG_MODE_L4_PORT,
+ QED_FILTER_CONFIG_MODE_IP_DEST,
+};
+
+struct qed_ntuple_filter_params {
+ /* Physically mapped address containing header of buffer to be used
+ * as filter.
+ */
+ dma_addr_t addr;
+
+ /* Length of header in bytes */
+ u16 length;
+
+ /* Relative queue-id to receive classified packet */
+#define QED_RFS_NTUPLE_QID_RSS ((u16)-1)
+ u16 qid;
+
+ /* Identifier can either be according to vport-id or vfid */
+ bool b_is_vf;
+ u8 vport_id;
+ u8 vf_id;
+
+ /* true iff this filter is to be added. Else to be removed */
+ bool b_is_add;
+};
+
struct qed_dev_eth_info {
struct qed_dev_info common;
@@ -316,13 +345,12 @@ struct qed_eth_ops {
int (*tunn_config)(struct qed_dev *cdev,
struct qed_tunn_params *params);
- int (*ntuple_filter_config)(struct qed_dev *cdev, void *cookie,
- dma_addr_t mapping, u16 length,
- u16 vport_id, u16 rx_queue_id,
- bool add_filter);
+ int (*ntuple_filter_config)(struct qed_dev *cdev,
+ void *cookie,
+ struct qed_ntuple_filter_params *params);
int (*configure_arfs_searcher)(struct qed_dev *cdev,
- bool en_searcher);
+ enum qed_filter_config_mode mode);
int (*get_coalesce)(struct qed_dev *cdev, u16 *coal, void *handle);
};
diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h
index cc646ca..15e398c 100644
--- a/include/linux/qed/qed_if.h
+++ b/include/linux/qed/qed_if.h
@@ -244,16 +244,11 @@ struct qed_fcoe_pf_params {
/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
struct qed_iscsi_pf_params {
u64 glbl_q_params_addr;
- u64 bdq_pbl_base_addr[2];
- u32 max_cwnd;
+ u64 bdq_pbl_base_addr[3];
u16 cq_num_entries;
u16 cmdq_num_entries;
u32 two_msl_timer;
- u16 dup_ack_threshold;
u16 tx_sws_timer;
- u16 min_rto;
- u16 min_rto_rt;
- u16 max_rto;
/* The following parameters are used during HW-init
* and these parameters need to be passed as arguments
@@ -264,8 +259,8 @@ struct qed_iscsi_pf_params {
/* The following parameters are used during protocol-init */
u16 half_way_close_timeout;
- u16 bdq_xoff_threshold[2];
- u16 bdq_xon_threshold[2];
+ u16 bdq_xoff_threshold[3];
+ u16 bdq_xon_threshold[3];
u16 cmdq_xoff_threshold;
u16 cmdq_xon_threshold;
u16 rq_buffer_size;
@@ -281,10 +276,11 @@ struct qed_iscsi_pf_params {
u8 gl_cmd_pi;
u8 debug_mode;
u8 ll2_ooo_queue_id;
- u8 ooo_enable;
u8 is_target;
- u8 bdq_pbl_num_entries[2];
+ u8 is_soc_en;
+ u8 soc_num_of_blocks_log;
+ u8 bdq_pbl_num_entries[3];
};
struct qed_rdma_pf_params {
@@ -316,16 +312,16 @@ enum qed_int_mode {
};
struct qed_sb_info {
- struct status_block *sb_virt;
- dma_addr_t sb_phys;
- u32 sb_ack; /* Last given ack */
- u16 igu_sb_id;
- void __iomem *igu_addr;
- u8 flags;
-#define QED_SB_INFO_INIT 0x1
-#define QED_SB_INFO_SETUP 0x2
+ struct status_block_e4 *sb_virt;
+ dma_addr_t sb_phys;
+ u32 sb_ack; /* Last given ack */
+ u16 igu_sb_id;
+ void __iomem *igu_addr;
+ u8 flags;
+#define QED_SB_INFO_INIT 0x1
+#define QED_SB_INFO_SETUP 0x2
- struct qed_dev *cdev;
+ struct qed_dev *cdev;
};
enum qed_dev_type {
@@ -939,7 +935,7 @@ static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
u16 rc = 0;
prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
- STATUS_BLOCK_PROD_INDEX_MASK;
+ STATUS_BLOCK_E4_PROD_INDEX_MASK;
if (sb_info->sb_ack != prod) {
sb_info->sb_ack = prod;
rc |= QED_SB_IDX;
diff --git a/include/linux/qed/qed_iscsi_if.h b/include/linux/qed/qed_iscsi_if.h
index 111e606..675610c 100644
--- a/include/linux/qed/qed_iscsi_if.h
+++ b/include/linux/qed/qed_iscsi_if.h
@@ -37,6 +37,7 @@
typedef int (*iscsi_event_cb_t) (void *context,
u8 fw_event_code, void *fw_handle);
+
struct qed_iscsi_stats {
u64 iscsi_rx_bytes_cnt;
u64 iscsi_rx_packet_cnt;
@@ -102,7 +103,6 @@ struct qed_iscsi_params_offload {
u32 ss_thresh;
u16 srtt;
u16 rtt_var;
- u32 ts_time;
u32 ts_recent;
u32 ts_recent_age;
u32 total_rt;
@@ -124,7 +124,6 @@ struct qed_iscsi_params_offload {
u16 mss;
u8 snd_wnd_scale;
u8 rcv_wnd_scale;
- u32 ts_ticks_per_second;
u16 da_timeout_value;
u8 ack_frequency;
};
@@ -135,7 +134,6 @@ struct qed_iscsi_params_update {
#define QED_ISCSI_CONN_DD_EN BIT(1)
#define QED_ISCSI_CONN_INITIAL_R2T BIT(2)
#define QED_ISCSI_CONN_IMMEDIATE_DATA BIT(3)
-
u32 max_seq_size;
u32 max_recv_pdu_length;
u32 max_send_pdu_length;
diff --git a/include/linux/qed/qed_ll2_if.h b/include/linux/qed/qed_ll2_if.h
index e755954..266c1fb 100644
--- a/include/linux/qed/qed_ll2_if.h
+++ b/include/linux/qed/qed_ll2_if.h
@@ -116,7 +116,7 @@ struct qed_ll2_comp_rx_data {
u32 opaque_data_1;
/* GSI only */
- u32 gid_dst[4];
+ u32 src_qp;
u16 qp_id;
union {
diff --git a/include/linux/qed/rdma_common.h b/include/linux/qed/rdma_common.h
index a9b3050..c1a446e 100644
--- a/include/linux/qed/rdma_common.h
+++ b/include/linux/qed/rdma_common.h
@@ -32,28 +32,29 @@
#ifndef __RDMA_COMMON__
#define __RDMA_COMMON__
+
/************************/
/* RDMA FW CONSTANTS */
/************************/
-#define RDMA_RESERVED_LKEY (0)
-#define RDMA_RING_PAGE_SIZE (0x1000)
+#define RDMA_RESERVED_LKEY (0)
+#define RDMA_RING_PAGE_SIZE (0x1000)
-#define RDMA_MAX_SGE_PER_SQ_WQE (4)
-#define RDMA_MAX_SGE_PER_RQ_WQE (4)
+#define RDMA_MAX_SGE_PER_SQ_WQE (4)
+#define RDMA_MAX_SGE_PER_RQ_WQE (4)
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x80000000)
-#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
-#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
+#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
+#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
-#define RDMA_MAX_CQS (64 * 1024)
-#define RDMA_MAX_TIDS (128 * 1024 - 1)
-#define RDMA_MAX_PDS (64 * 1024)
+#define RDMA_MAX_CQS (64 * 1024)
+#define RDMA_MAX_TIDS (128 * 1024 - 1)
+#define RDMA_MAX_PDS (64 * 1024)
-#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
-#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
-#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
+#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
+#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
+#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)
diff --git a/include/linux/qed/roce_common.h b/include/linux/qed/roce_common.h
index fe6a33e..e15e0da 100644
--- a/include/linux/qed/roce_common.h
+++ b/include/linux/qed/roce_common.h
@@ -33,13 +33,18 @@
#ifndef __ROCE_COMMON__
#define __ROCE_COMMON__
-#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
-#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
+/************************/
+/* ROCE FW CONSTANTS */
+/************************/
-#define ROCE_MAX_QPS (32 * 1024)
-#define ROCE_DCQCN_NP_MAX_QPS (64)
-#define ROCE_DCQCN_RP_MAX_QPS (64)
+#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
+#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
+#define ROCE_MAX_QPS (32 * 1024)
+#define ROCE_DCQCN_NP_MAX_QPS (64)
+#define ROCE_DCQCN_RP_MAX_QPS (64)
+
+/* Affiliated asynchronous events / errors enumeration */
enum roce_async_events_type {
ROCE_ASYNC_EVENT_NONE = 0,
ROCE_ASYNC_EVENT_COMM_EST = 1,
diff --git a/include/linux/qed/storage_common.h b/include/linux/qed/storage_common.h
index 08df82a..505c0b4 100644
--- a/include/linux/qed/storage_common.h
+++ b/include/linux/qed/storage_common.h
@@ -33,43 +33,77 @@
#ifndef __STORAGE_COMMON__
#define __STORAGE_COMMON__
-#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
-#define BDQ_NUM_RESOURCES (4)
-
-#define BDQ_ID_RQ (0)
-#define BDQ_ID_IMM_DATA (1)
-#define BDQ_NUM_IDS (2)
-
-#define SCSI_NUM_SGES_SLOW_SGL_THR 8
+/*********************/
+/* SCSI CONSTANTS */
+/*********************/
+
+#define SCSI_MAX_NUM_OF_CMDQS (NUM_OF_GLOBAL_QUEUES / 2)
+#define BDQ_NUM_RESOURCES (4)
+
+#define BDQ_ID_RQ (0)
+#define BDQ_ID_IMM_DATA (1)
+#define BDQ_ID_TQ (2)
+#define BDQ_NUM_IDS (3)
+
+#define SCSI_NUM_SGES_SLOW_SGL_THR 8
+
+#define BDQ_MAX_EXTERNAL_RING_SIZE BIT(15)
+
+/* SCSI op codes */
+#define SCSI_OPCODE_COMPARE_AND_WRITE (0x89)
+#define SCSI_OPCODE_READ_10 (0x28)
+#define SCSI_OPCODE_WRITE_6 (0x0A)
+#define SCSI_OPCODE_WRITE_10 (0x2A)
+#define SCSI_OPCODE_WRITE_12 (0xAA)
+#define SCSI_OPCODE_WRITE_16 (0x8A)
+#define SCSI_OPCODE_WRITE_AND_VERIFY_10 (0x2E)
+#define SCSI_OPCODE_WRITE_AND_VERIFY_12 (0xAE)
+#define SCSI_OPCODE_WRITE_AND_VERIFY_16 (0x8E)
+
+/* iSCSI Drv opaque */
+struct iscsi_drv_opaque {
+ __le16 reserved_zero[3];
+ __le16 opaque;
+};
-#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
+/* Scsi 2B/8B opaque union */
+union scsi_opaque {
+ struct regpair fcoe_opaque;
+ struct iscsi_drv_opaque iscsi_opaque;
+};
+/* SCSI buffer descriptor */
struct scsi_bd {
struct regpair address;
- struct regpair opaque;
+ union scsi_opaque opaque;
};
+/* Scsi Drv BDQ struct */
struct scsi_bdq_ram_drv_data {
__le16 external_producer;
__le16 reserved0[3];
};
+/* SCSI SGE entry */
struct scsi_sge {
struct regpair sge_addr;
__le32 sge_len;
__le32 reserved;
};
+/* Cached SGEs section */
struct scsi_cached_sges {
struct scsi_sge sge[4];
};
+/* Scsi Drv CMDQ struct */
struct scsi_drv_cmdq {
__le16 cmdq_cons;
__le16 reserved0;
__le32 reserved1;
};
+/* Common SCSI init params passed by driver to FW in function init ramrod */
struct scsi_init_func_params {
__le16 num_tasks;
u8 log_page_size;
@@ -77,6 +111,7 @@ struct scsi_init_func_params {
u8 reserved2[12];
};
+/* SCSI RQ/CQ/CMDQ firmware function init parameters */
struct scsi_init_func_queues {
struct regpair glbl_q_params_addr;
__le16 rq_buffer_size;
@@ -84,39 +119,45 @@ struct scsi_init_func_queues {
__le16 cmdq_num_entries;
u8 bdq_resource_id;
u8 q_validity;
-#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
-#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
-#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
-#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
-#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
+#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
+#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
+#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
+#define SCSI_INIT_FUNC_QUEUES_TQ_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_TQ_VALID_SHIFT 3
+#define SCSI_INIT_FUNC_QUEUES_SOC_EN_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_SOC_EN_SHIFT 4
+#define SCSI_INIT_FUNC_QUEUES_SOC_NUM_OF_BLOCKS_LOG_MASK 0x7
+#define SCSI_INIT_FUNC_QUEUES_SOC_NUM_OF_BLOCKS_LOG_SHIFT 5
+ __le16 cq_cmdq_sb_num_arr[SCSI_MAX_NUM_OF_CMDQS];
u8 num_queues;
u8 queue_relative_offset;
u8 cq_sb_pi;
u8 cmdq_sb_pi;
- __le16 cq_cmdq_sb_num_arr[NUM_OF_CMDQS_CQS];
- __le16 reserved0;
u8 bdq_pbl_num_entries[BDQ_NUM_IDS];
+ u8 reserved1;
struct regpair bdq_pbl_base_address[BDQ_NUM_IDS];
__le16 bdq_xoff_threshold[BDQ_NUM_IDS];
- __le16 bdq_xon_threshold[BDQ_NUM_IDS];
__le16 cmdq_xoff_threshold;
+ __le16 bdq_xon_threshold[BDQ_NUM_IDS];
__le16 cmdq_xon_threshold;
- __le32 reserved1;
};
+/* Scsi Drv BDQ Data struct (2 BDQ IDs: 0 - RQ, 1 - Immediate Data) */
struct scsi_ram_per_bdq_resource_drv_data {
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
};
+/* SCSI SGL types */
enum scsi_sgl_mode {
SCSI_TX_SLOW_SGL,
SCSI_FAST_SGL,
MAX_SCSI_SGL_MODE
};
+/* SCSI SGL parameters */
struct scsi_sgl_params {
struct regpair sgl_addr;
__le32 sgl_total_length;
@@ -126,10 +167,16 @@ struct scsi_sgl_params {
u8 reserved;
};
+/* SCSI terminate connection params */
struct scsi_terminate_extra_params {
__le16 unsolicited_cq_count;
__le16 cmdq_count;
u8 reserved[4];
};
+/* SCSI Task Queue Element */
+struct scsi_tqe {
+ __le16 itid;
+};
+
#endif /* __STORAGE_COMMON__ */
diff --git a/include/linux/qed/tcp_common.h b/include/linux/qed/tcp_common.h
index dbf7a43..4a48451 100644
--- a/include/linux/qed/tcp_common.h
+++ b/include/linux/qed/tcp_common.h
@@ -33,8 +33,13 @@
#ifndef __TCP_COMMON__
#define __TCP_COMMON__
-#define TCP_INVALID_TIMEOUT_VAL -1
+/********************/
+/* TCP FW CONSTANTS */
+/********************/
+#define TCP_INVALID_TIMEOUT_VAL -1
+
+/* OOO opaque data received from LL2 */
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
@@ -43,25 +48,29 @@ struct ooo_opaque {
u8 ooo_isle;
};
+/* tcp connect mode enum */
enum tcp_connect_mode {
TCP_CONNECT_ACTIVE,
TCP_CONNECT_PASSIVE,
MAX_TCP_CONNECT_MODE
};
+/* tcp function init parameters */
struct tcp_init_params {
__le32 two_msl_timer;
__le16 tx_sws_timer;
- u8 maxfinrt;
+ u8 max_fin_rt;
u8 reserved[9];
};
+/* tcp IPv4/IPv6 enum */
enum tcp_ip_version {
TCP_IPV4,
TCP_IPV6,
MAX_TCP_IP_VERSION
};
+/* tcp offload parameters */
struct tcp_offload_params {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@@ -70,24 +79,29 @@ struct tcp_offload_params {
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
__le16 vlan_id;
- u8 flags;
-#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
-#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
-#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
-#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
-#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
-#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
-#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
-#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
+ __le16 flags;
+#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
+#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
+#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
+#define TCP_OFFLOAD_PARAMS_ECN_SENDER_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_ECN_SENDER_EN_SHIFT 3
+#define TCP_OFFLOAD_PARAMS_ECN_RECEIVER_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_ECN_RECEIVER_EN_SHIFT 4
+#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 5
+#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 6
+#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 7
+#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 8
+#define TCP_OFFLOAD_PARAMS_RESERVED_MASK 0x7F
+#define TCP_OFFLOAD_PARAMS_RESERVED_SHIFT 9
u8 ip_version;
+ u8 reserved0[3];
__le32 remote_ip[4];
__le32 local_ip[4];
__le32 flow_label;
@@ -99,17 +113,21 @@ struct tcp_offload_params {
u8 rcv_wnd_scale;
u8 connect_mode;
__le16 srtt;
- __le32 cwnd;
__le32 ss_thresh;
- __le16 reserved1;
+ __le32 rcv_wnd;
+ __le32 cwnd;
u8 ka_max_probe_cnt;
u8 dup_ack_theshold;
+ __le16 reserved1;
+ __le32 ka_timeout;
+ __le32 ka_interval;
+ __le32 max_rt_time;
+ __le32 initial_rcv_wnd;
__le32 rcv_next;
__le32 snd_una;
__le32 snd_next;
__le32 snd_max;
__le32 snd_wnd;
- __le32 rcv_wnd;
__le32 snd_wl1;
__le32 ts_recent;
__le32 ts_recent_age;
@@ -122,16 +140,13 @@ struct tcp_offload_params {
u8 rt_cnt;
__le16 rtt_var;
__le16 fw_internal;
- __le32 ka_timeout;
- __le32 ka_interval;
- __le32 max_rt_time;
- __le32 initial_rcv_wnd;
u8 snd_wnd_scale;
u8 ack_frequency;
__le16 da_timeout_value;
- __le32 reserved3[2];
+ __le32 reserved3;
};
+/* tcp offload parameters */
struct tcp_offload_params_opt2 {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@@ -140,16 +155,19 @@ struct tcp_offload_params_opt2 {
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
__le16 vlan_id;
- u8 flags;
-#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
-#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
-#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
-#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
-#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
+ __le16 flags;
+#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
+#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
+#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
+#define TCP_OFFLOAD_PARAMS_OPT2_ECN_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_ECN_EN_SHIFT 3
+#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0xFFF
+#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 4
u8 ip_version;
+ u8 reserved1[3];
__le32 remote_ip[4];
__le32 local_ip[4];
__le32 flow_label;
@@ -163,9 +181,16 @@ struct tcp_offload_params_opt2 {
__le16 syn_ip_payload_length;
__le32 syn_phy_addr_lo;
__le32 syn_phy_addr_hi;
- __le32 reserved1[22];
+ __le32 cwnd;
+ u8 ka_max_probe_cnt;
+ u8 reserved2[3];
+ __le32 ka_timeout;
+ __le32 ka_interval;
+ __le32 max_rt_time;
+ __le32 reserved3[16];
};
+/* tcp IPv4/IPv6 enum */
enum tcp_seg_placement_event {
TCP_EVENT_ADD_PEN,
TCP_EVENT_ADD_NEW_ISLE,
@@ -177,40 +202,41 @@ enum tcp_seg_placement_event {
MAX_TCP_SEG_PLACEMENT_EVENT
};
+/* tcp init parameters */
struct tcp_update_params {
__le16 flags;
-#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
-#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
-#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
-#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
-#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
-#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
-#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
-#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
-#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
-#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
-#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
-#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
-#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
-#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
-#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
-#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
-#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
-#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
+#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
+#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
+#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
+#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
+#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
+#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
+#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
+#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
+#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
+#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
+#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
+#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
+#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
+#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
+#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
+#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
+#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
+#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
@@ -226,6 +252,7 @@ struct tcp_update_params {
u8 reserved1[7];
};
+/* toe upload parameters */
struct tcp_upload_params {
__le32 rcv_next;
__le32 snd_una;
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH net-next] netdevsim: correctly check return value of debugfs_create_dir
From: David Miller @ 2017-12-19 14:11 UTC (permalink / raw)
To: bhole_prashant_q7; +Cc: jakub.kicinski, netdev
In-Reply-To: <014801d37884$3cc5d290$b65177b0$@lab.ntt.co.jp>
From: "Prashant Bhole" <bhole_prashant_q7@lab.ntt.co.jp>
Date: Tue, 19 Dec 2017 13:45:47 +0900
> I tried to evaluate whether fixing return value of debugfs_create_dir() (and
> friends) will be useful or not because it has not been changed since very
> long time. Now I am not much convinced about changing this api.
>
> Important and possible error codes could be -EEXIST and -ENOMEM. Suppose
> -EEXIST is returned, IMO the directory shouldn't exists in the first place
> because it is specific to particular module. Also, there is no point in
> creating file in such directory, because directory owner (creator) might
> remove it too. This means there are less chances that api change will be
> useful. Please let me know your opinion on it.
>
> If you are ok with above explanation, shall I submit v2 for this patch?
Well, something is seriously wrong if the directory exists already.
It could be that two netdevsim modules, independantly compiled, are trying
to be loaded.
Wouldn't it clearly be desirable to fail and not load the module in
that case?
This is why I think ignoring debugfs errors is foolish.
^ permalink raw reply
* Re: [PATCH V4 14/26] pch_gbe: deprecate pci_get_bus_and_slot()
From: David Miller @ 2017-12-19 14:13 UTC (permalink / raw)
To: okaya
Cc: linux-pci, timur, linux-arm-msm, linux-arm-kernel, keescook,
edumazet, tklauser, andriy.shevchenko, netdev, linux-kernel
In-Reply-To: <1513661883-28662-15-git-send-email-okaya@codeaurora.org>
From: Sinan Kaya <okaya@codeaurora.org>
Date: Tue, 19 Dec 2017 00:37:50 -0500
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Use the domain information from pdev while calling into
> pci_get_domain_bus_and_slot() function.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply
* Re: [PATCH V4 13/26] bnx2x: deprecate pci_get_bus_and_slot()
From: David Miller @ 2017-12-19 14:14 UTC (permalink / raw)
To: okaya
Cc: linux-pci, timur, linux-arm-msm, linux-arm-kernel, ariel.elior,
everest-linux-l2, netdev, linux-kernel
In-Reply-To: <1513661883-28662-14-git-send-email-okaya@codeaurora.org>
From: Sinan Kaya <okaya@codeaurora.org>
Date: Tue, 19 Dec 2017 00:37:49 -0500
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Introduce bnx2x_vf_domain() function to extract the domain information
> and save it to VF specific data structure.
>
> Use the saved domain value while calling pci_get_domain_bus_and_slot().
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: David S. Miller <davem@davemloft.net>
^ permalink raw reply
* [PATCH net] ipv4: fib: Fix metrics match when deleting a route
From: Phil Sutter @ 2017-12-19 14:17 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Xin Long
The recently added fib_metrics_match() causes a regression for routes
with both RTAX_FEATURES and RTAX_CC_ALGO if the latter has
TCP_CONG_NEEDS_ECN flag set:
| # ip link add d0 type dummy
| # ip link set d0 up
| # ip route add 172.29.29.0/24 dev d0 features ecn congctl dctcp
| # ip route del 172.29.29.0/24 dev d0 features ecn congctl dctcp
| RTNETLINK answers: No such process
During route insertion, fib_convert_metrics() detects that the given CC
algo requires ECN and hence sets DST_FEATURE_ECN_CA bit in
RTAX_FEATURES.
During route deletion though, fib_metrics_match() compares stored
RTAX_FEATURES value with that from userspace (which obviously has no
knowledge about DST_FEATURE_ECN_CA) and fails.
Fixes: 5f9ae3d9e7e4a ("ipv4: do metrics match when looking up and deleting a route")
Signed-off-by: Phil Sutter <phil@nwl.cc>
---
net/ipv4/fib_semantics.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c
index f04d944f8abe0..c586597da20db 100644
--- a/net/ipv4/fib_semantics.c
+++ b/net/ipv4/fib_semantics.c
@@ -698,7 +698,7 @@ bool fib_metrics_match(struct fib_config *cfg, struct fib_info *fi)
nla_for_each_attr(nla, cfg->fc_mx, cfg->fc_mx_len, remaining) {
int type = nla_type(nla);
- u32 val;
+ u32 fi_val, val;
if (!type)
continue;
@@ -715,7 +715,11 @@ bool fib_metrics_match(struct fib_config *cfg, struct fib_info *fi)
val = nla_get_u32(nla);
}
- if (fi->fib_metrics->metrics[type - 1] != val)
+ fi_val = fi->fib_metrics->metrics[type - 1];
+ if (type == RTAX_FEATURES)
+ fi_val &= ~DST_FEATURE_ECN_CA;
+
+ if (fi_val != val)
return false;
}
--
2.13.1
^ permalink raw reply related
* Re: [PATCH 2/3] rhashtable: Add rhashtable_walk_curr
From: David Miller @ 2017-12-19 14:35 UTC (permalink / raw)
To: agruenba; +Cc: herbert, cluster-devel, tgraf, netdev, tom
In-Reply-To: <CAHc6FU5JLviUSt9SO3oXZfWRE5ScBZ7O2f+2YubPJwCxQGW-2g@mail.gmail.com>
From: Andreas Gruenbacher <agruenba@redhat.com>
Date: Tue, 19 Dec 2017 09:35:47 +0100
> By the way, git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
> master doesn't merge cleanly with current mainline.
Yes, this is the case more often than not :-)
^ permalink raw reply
* [RFC PATCH net-next] tools/bpf: fix build with binutils >= 2.28
From: Roman Gushchin @ 2017-12-19 14:38 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, kernel-team, Roman Gushchin, Jakub Kicinski,
Alexei Starovoitov, Daniel Borkmann
Bpftool build is broken with binutils version 2.28 and later.
The cause is commit 003ca0fd2286 ("Refactor disassembler selection")
in the binutils repo, which changed the disassembler() function
signature.
Fix this by checking binutils version and use an appropriate
disassembler() signature.
Signed-off-by: Roman Gushchin <guro@fb.com>
Cc: Jakub Kicinski <jakub.kicinski@netronome.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Daniel Borkmann <daniel@iogearbox.net>
---
tools/bpf/Makefile | 6 ++++++
tools/bpf/bpf_jit_disasm.c | 7 +++++++
tools/bpf/bpftool/Makefile | 6 ++++++
tools/bpf/bpftool/jit_disasm.c | 5 +++++
4 files changed, 24 insertions(+)
diff --git a/tools/bpf/Makefile b/tools/bpf/Makefile
index 07a6697466ef..3fd32fd0daa1 100644
--- a/tools/bpf/Makefile
+++ b/tools/bpf/Makefile
@@ -6,8 +6,14 @@ LEX = flex
YACC = bison
MAKE = make
+BINUTILS_VER := $(word 4, $(shell readelf -v | head -n 1))
+BINUTILS_VER_MAJ := $(word 1, $(subst ., , $(subst -, , ${BINUTILS_VER})))
+BINUTILS_VER_MIN := $(word 2, $(subst ., , $(subst -, , ${BINUTILS_VER})))
+
CFLAGS += -Wall -O2
CFLAGS += -D__EXPORTED_HEADERS__ -I../../include/uapi -I../../include
+CFLAGS += -DBINUTILS_VER_MAJ=${BINUTILS_VER_MAJ}
+CFLAGS += -DBINUTILS_VER_MIN=${BINUTILS_VER_MIN}
%.yacc.c: %.y
$(YACC) -o $@ -d $<
diff --git a/tools/bpf/bpf_jit_disasm.c b/tools/bpf/bpf_jit_disasm.c
index 75bf526a0168..3ef7c8bdc0f3 100644
--- a/tools/bpf/bpf_jit_disasm.c
+++ b/tools/bpf/bpf_jit_disasm.c
@@ -72,7 +72,14 @@ static void get_asm_insns(uint8_t *image, size_t len, int opcodes)
disassemble_init_for_target(&info);
+#if (BINUTILS_VER_MAJ >= 2) && (BINUTILS_VER_MIN >= 28)
+ disassemble = disassembler(bfd_get_arch(bfdf),
+ bfd_big_endian(bfdf),
+ bfd_get_mach(bfdf),
+ bfdf);
+#else
disassemble = disassembler(bfdf);
+#endif
assert(disassemble);
do {
diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile
index 3f17ad317512..94ad51bf14b5 100644
--- a/tools/bpf/bpftool/Makefile
+++ b/tools/bpf/bpftool/Makefile
@@ -40,6 +40,12 @@ CFLAGS += -W -Wall -Wextra -Wno-unused-parameter -Wshadow
CFLAGS += -D__EXPORTED_HEADERS__ -I$(srctree)/tools/include/uapi -I$(srctree)/tools/include -I$(srctree)/tools/lib/bpf -I$(srctree)/kernel/bpf/
LIBS = -lelf -lbfd -lopcodes $(LIBBPF)
+BINUTILS_VER := $(word 4, $(shell readelf -v | head -n 1))
+BINUTILS_VER_MAJ := $(word 1, $(subst ., , $(subst -, , ${BINUTILS_VER})))
+BINUTILS_VER_MIN := $(word 2, $(subst ., , $(subst -, , ${BINUTILS_VER})))
+CFLAGS += -DBINUTILS_VER_MAJ=${BINUTILS_VER_MAJ}
+CFLAGS += -DBINUTILS_VER_MIN=${BINUTILS_VER_MIN}
+
INSTALL ?= install
RM ?= rm -f
diff --git a/tools/bpf/bpftool/jit_disasm.c b/tools/bpf/bpftool/jit_disasm.c
index 1551d3918d4c..eaa7127e9eeb 100644
--- a/tools/bpf/bpftool/jit_disasm.c
+++ b/tools/bpf/bpftool/jit_disasm.c
@@ -107,7 +107,12 @@ void disasm_print_insn(unsigned char *image, ssize_t len, int opcodes)
disassemble_init_for_target(&info);
+#if (BINUTILS_VER_MAJ >= 2) && (BINUTILS_VER_MIN >= 28)
+ disassemble = disassembler(bfd_get_arch(bfdf), bfd_big_endian(bfdf),
+ bfd_get_mach(bfdf), bfdf);
+#else
disassemble = disassembler(bfdf);
+#endif
assert(disassemble);
if (json_output)
--
2.14.3
^ permalink raw reply related
* Re: pull-request: mac80211 2017-12-19
From: David Miller @ 2017-12-19 14:39 UTC (permalink / raw)
To: johannes; +Cc: netdev, linux-wireless
In-Reply-To: <20171219095710.16889-1-johannes@sipsolutions.net>
From: Johannes Berg <johannes@sipsolutions.net>
Date: Tue, 19 Dec 2017 10:57:09 +0100
> Other work has been hectic, and I got caught by rc4. We still
> have a few more fixes though - and more build issues were
> reported.
>
> Please pull and let me know if there's any problem.
Pulled, thanks Johannes.
^ permalink raw reply
* Re: [PATCH V4 14/26] pch_gbe: deprecate pci_get_bus_and_slot()
From: David Miller @ 2017-12-19 14:53 UTC (permalink / raw)
To: okaya
Cc: andriy.shevchenko, linux-pci, timur, linux-arm-msm,
linux-arm-kernel, keescook, edumazet, tklauser, netdev,
linux-kernel
In-Reply-To: <ef7d09ce-06af-ad3e-1048-3b413cc32e9b@codeaurora.org>
From: Sinan Kaya <okaya@codeaurora.org>
Date: Tue, 19 Dec 2017 07:17:41 -0500
> Then hard code the domain number as 0 while calling
> pci_get_domain_bus_and_slot() if you know for sure that this device
> will never work on a non-zero domain.
Agreed, it's so much better to be explicit about this.
^ permalink raw reply
* Re: [PATCH v3 net-next 3/6] net: Add SW fallback infrastructure for offloaded sockets
From: Marcelo Ricardo Leitner @ 2017-12-19 15:05 UTC (permalink / raw)
To: Ilya Lesokhin
Cc: netdev@vger.kernel.org, davem@davemloft.net, davejwatson@fb.com,
tom@herbertland.com, hannes@stressinduktion.org, Boris Pismenny,
Aviad Yehezkel, Liran Liss, Steffen Klassert
In-Reply-To: <AM4PR0501MB2723B5452037B69253A0459BD40F0@AM4PR0501MB2723.eurprd05.prod.outlook.com>
On Tue, Dec 19, 2017 at 07:51:02AM +0000, Ilya Lesokhin wrote:
> On Monday, December 18, 2017 9:18 PM, Marcelo Ricardo Leitner wrote:
>
> > > +
> > > + if (sk && sk_fullsock(sk) && sk->sk_offload_check)
> >
> > Isn't this going to hurt the fast path, checking for sk fields here?
> >
>
> We do add code to the fast path but it seems unavoidable if you want to have SW fallback.
> The XFRM device offload also does that
> http://elixir.free-electrons.com/linux/v4.14.7/source/net/core/dev.c#L3058
Right, although a bit different. It's accessing skb->sp and not the
socket and depending on how compiler is doing things, the check
http://elixir.free-electrons.com/linux/v4.14.7/source/net/xfrm/xfrm_device.c#L32
will help in some cases.
But more importantly, all the above only exists if CONFIG_XFRM_OFFLOAD
is enabled.
>
> The check can be optimized but I didn't want to do that before I saw that it's an issue.
> I'm also not sure what the correct solution is.
> I don't like that fact that each "stateful protocol" we offload requires its own check.
> We need to think if we can find a generic way of doing it.
>
> Perhaps we can hold the expected netdev somewhere in the SKB and only if we don't
> Go out of the expected netdev go to a slow path that does a check for each protocol.
This could be a good switch, yes.
Thanks,
Marcelo
^ permalink raw reply
* Re: [PATCH v3 net-next 6/6] tls: Add generic NIC offload infrastructure.
From: Marcelo Ricardo Leitner @ 2017-12-19 15:11 UTC (permalink / raw)
To: Ilya Lesokhin
Cc: netdev@vger.kernel.org, davem@davemloft.net, davejwatson@fb.com,
tom@herbertland.com, hannes@stressinduktion.org, Boris Pismenny,
Aviad Yehezkel, Liran Liss
In-Reply-To: <AM4PR0501MB27235B47E8E4DDA2B9E8B757D40F0@AM4PR0501MB2723.eurprd05.prod.outlook.com>
On Tue, Dec 19, 2017 at 07:31:24AM +0000, Ilya Lesokhin wrote:
> On Mon, Monday, December 18, 2017 9:54 PM, Marcelo Ricardo Leitner wrote:
>
> > On Mon, Dec 18, 2017 at 01:10:33PM +0200, Ilya Lesokhin wrote:
> > > This patch adds a generic infrastructure to offload TLS crypto to a
> > > network devices. It enables the kernel TLS socket to skip encryption
> > > and authentication operations on the transmit side of the data path.
> > > Leaving those computationally expensive operations to the NIC.
> >
> > I have a hard time understanding why this was named 'tls_device' if no
> > net_device's are registered.
> >
> I'm not quite sure what you mean by "no net_device's are registered"
> Presumably you mean there is no device that implements the
> NETIF_F_HW_TLS_TX capability yet.
Not really. Let me try again. This patchset is using the expression
"tls_device". When I read that, I expect a new interface type, like a
tunnel, that would be created on top of another interface that has the
offloading capability. That's why I'm confused. IMHO "tls_offload" is
a better fit. Makes sense?
> I'll just say that the IPSEC device offload infrastructure was also submitted
> https://github.com/torvalds/linux/commit/d77e38e612a017480157fe6d2c1422f42cb5b7e3
> before the first implementation
> https://github.com/torvalds/linux/commit/bebb23e6cb02d2fc752905e39d09ff6152852c6c
>
> And we did provide a link to an implementation
> https://github.com/Mellanox/tls-offload/tree/tls_device_v3
> for people who want to take a look.
> Unfortunately it is not ready for upstream submission yet
Yep, although I still have to get there.
Thanks,
Marcelo
^ permalink raw reply
* Re: [patch iproute2] tc: add -bs option for batch mode
From: Stephen Hemminger @ 2017-12-19 15:15 UTC (permalink / raw)
To: Chris Mi; +Cc: netdev, gerlitz.or
In-Reply-To: <20171219063346.19300-1-chrism@mellanox.com>
On Tue, 19 Dec 2017 15:33:46 +0900
Chris Mi <chrism@mellanox.com> wrote:
> Currently in tc batch mode, only one command is read from the batch
> file and sent to kernel to process. With this patch, we can accumulate
> several commands before sending to kernel. The batch size is specified
> using option -bs or -batchsize.
>
> To accumulate the commands in tc, we allocate an array of struct iovec.
> If batchsize is bigger than 1 and we haven't accumulated enough
> commands, rtnl_talk() will return without actually sending the message.
> One exception is that there is no more command in the batch file.
>
> But please note that kernel still processes the requests one by one.
> To process the requests in parallel in kernel is another effort.
> The time we're saving in this patch is the user mode and kernel mode
> context switch. So this patch works on top of the current kernel.
>
> Using the following script in kernel, we can generate 1,000,000 rules.
> tools/testing/selftests/tc-testing/tdc_batch.py
>
> Without this patch, 'tc -b $file' exection time is:
>
> real 0m14.916s
> user 0m6.808s
> sys 0m8.046s
>
> With this patch, 'tc -b $file -bs 10' exection time is:
>
> real 0m12.286s
> user 0m5.903s
> sys 0m6.312s
>
> The insertion rate is improved more than 10%.
>
> Signed-off-by: Chris Mi <chrism@mellanox.com>
I think this is probably optmizing for an unrealistic use case.
If there are 1M rules then it should be managed by a dynmaic process
like a routing daemon with a real database and API. Such a daemon
would talk to kernel directly. Plus at scale netlink gets overwhelmed
and the daemon has to handle resync.
Not convinced that the added complexity and error handling issues
warrant the change. The batch mode already sucks at handling
errors.
^ permalink raw reply
* Re: [PATCH v7 2/3] sock: Move the socket inuse to namespace.
From: David Miller @ 2017-12-19 15:19 UTC (permalink / raw)
To: xiyou.wangcong; +Cc: xiangxia.m.yue, netdev
In-Reply-To: <CAM_iQpXhuQ03LB+DsVU4z=m5BCOWKTP1j1oUnBX7-rWC=z_oSA@mail.gmail.com>
From: Cong Wang <xiyou.wangcong@gmail.com>
Date: Mon, 18 Dec 2017 13:38:39 -0800
> On Mon, Dec 18, 2017 at 11:30 AM, David Miller <davem@davemloft.net> wrote:
>> From: Tonghao Zhang <xiangxia.m.yue@gmail.com>
>> Date: Thu, 14 Dec 2017 05:51:58 -0800
>>
>>> In some case, we want to know how many sockets are in use in
>>> different _net_ namespaces. It's a key resource metric.
>>
>> Useful or not, you're not exporting this value.
>>
>> All this patch series does is convert the existing export of the
>> global tally to add up the per-net values.
>>
>> So if you're not exporting the per-net value on it's own in any way,
>> this patch series isn't achieving the stated goal.
>>
>> I'm not applying this series, sorry.
>
>
> This value is already exported via procfs:
> sockstat_seq_show() -> socket_seq_show().
>
> And the proc file itself should already be per-net:
>
> static int sockstat_seq_open(struct inode *inode, struct file *file)
> {
> return single_open_net(inode, file, sockstat_seq_show);
> }
>
>
> This patch just makes that value to be per-net too.
Ok, I've applied this patch series.
Thanks for your patience and understanding.
^ permalink raw reply
* Re: [PATCH -tip v3 3/6] net: sctp: Add SCTP ACK tracking trace event
From: Steven Rostedt @ 2017-12-19 15:20 UTC (permalink / raw)
To: Masami Hiramatsu
Cc: Ingo Molnar, Ian McDonald, Vlad Yasevich, Stephen Hemminger,
Peter Zijlstra, Thomas Gleixner, LKML, H . Peter Anvin,
Gerrit Renker, David S . Miller, Neil Horman, dccp, netdev,
linux-sctp, Stephen Rothwell
In-Reply-To: <151367390483.32364.4432870291926458046.stgit@devbox>
On Tue, 19 Dec 2017 17:58:25 +0900
Masami Hiramatsu <mhiramat@kernel.org> wrote:
> +TRACE_EVENT(sctp_probe,
> +
> + TP_PROTO(const struct sctp_endpoint *ep,
> + const struct sctp_association *asoc,
> + struct sctp_chunk *chunk),
> +
> + TP_ARGS(ep, asoc, chunk),
> +
> + TP_STRUCT__entry(
> + __field(__u64, asoc)
> + __field(__u32, mark)
> + __field(__u16, bind_port)
> + __field(__u16, peer_port)
> + __field(__u32, pathmtu)
> + __field(__u32, rwnd)
> + __field(__u16, unack_data)
> + ),
> +
> + TP_fast_assign(
> + struct sctp_transport *sp;
> + struct sk_buff *skb = chunk->skb;
> +
> + __entry->asoc = (__u64)asoc;
> + __entry->mark = skb->mark;
> + __entry->bind_port = ep->base.bind_addr.port;
> + __entry->peer_port = asoc->peer.port;
> + __entry->pathmtu = asoc->pathmtu;
> + __entry->rwnd = asoc->peer.rwnd;
> + __entry->unack_data = asoc->unack_data;
> +
> + if (trace_sctp_probe_path_enabled()) {
> + list_for_each_entry(sp, &asoc->peer.transport_addr_list,
> + transports) {
> + trace_sctp_probe_path(sp, asoc);
> + }
> + }
I thought you were going to move this into the code, like I suggested?
-- Steve
> + ),
> +
> + TP_printk("asoc=%#llx mark=%#x bind_port=%d peer_port=%d pathmtu=%d "
> + "rwnd=%u unack_data=%d",
> + __entry->asoc, __entry->mark, __entry->bind_port,
> + __entry->peer_port, __entry->pathmtu, __entry->rwnd,
> + __entry->unack_data)
> +);
> +
^ permalink raw reply
* Re: [patch iproute2] tc: add -bs option for batch mode
From: Stephen Hemminger @ 2017-12-19 15:22 UTC (permalink / raw)
To: Chris Mi; +Cc: netdev, gerlitz.or
In-Reply-To: <20171219063346.19300-1-chrism@mellanox.com>
On Tue, 19 Dec 2017 15:33:46 +0900
Chris Mi <chrism@mellanox.com> wrote:
> Currently in tc batch mode, only one command is read from the batch
> file and sent to kernel to process. With this patch, we can accumulate
> several commands before sending to kernel. The batch size is specified
> using option -bs or -batchsize.
>
> To accumulate the commands in tc, we allocate an array of struct iovec.
> If batchsize is bigger than 1 and we haven't accumulated enough
> commands, rtnl_talk() will return without actually sending the message.
> One exception is that there is no more command in the batch file.
>
> But please note that kernel still processes the requests one by one.
> To process the requests in parallel in kernel is another effort.
> The time we're saving in this patch is the user mode and kernel mode
> context switch. So this patch works on top of the current kernel.
>
> Using the following script in kernel, we can generate 1,000,000 rules.
> tools/testing/selftests/tc-testing/tdc_batch.py
>
> Without this patch, 'tc -b $file' exection time is:
>
> real 0m14.916s
> user 0m6.808s
> sys 0m8.046s
>
> With this patch, 'tc -b $file -bs 10' exection time is:
>
> real 0m12.286s
> user 0m5.903s
> sys 0m6.312s
>
> The insertion rate is improved more than 10%.
>
> Signed-off-by: Chris Mi <chrism@mellanox.com>
> ---
> include/libnetlink.h | 27 ++++++++++++++++
> include/utils.h | 8 +++++
> lib/libnetlink.c | 30 +++++++++++++-----
> lib/utils.c | 20 ++++++++++++
> man/man8/tc.8 | 5 +++
> tc/m_action.c | 63 ++++++++++++++++++++++++++++---------
> tc/tc.c | 27 ++++++++++++++--
> tc/tc_common.h | 3 ++
> tc/tc_filter.c | 89 ++++++++++++++++++++++++++++++++++++----------------
> 9 files changed, 221 insertions(+), 51 deletions(-)
In addition to my earlier comments, these are the implementation
issues.
>
> diff --git a/include/libnetlink.h b/include/libnetlink.h
> index a4d83b9e..07e88c94 100644
> --- a/include/libnetlink.h
> +++ b/include/libnetlink.h
> @@ -13,6 +13,8 @@
> #include <linux/netconf.h>
> #include <arpa/inet.h>
>
> +#define MSG_IOV_MAX 256
> +
> struct rtnl_handle {
> int fd;
> struct sockaddr_nl local;
> @@ -93,6 +95,31 @@ int rtnl_dump_filter_nc(struct rtnl_handle *rth,
> void *arg, __u16 nc_flags);
> #define rtnl_dump_filter(rth, filter, arg) \
> rtnl_dump_filter_nc(rth, filter, arg, 0)
> +
> +extern int msg_iov_index;
> +static inline int get_msg_iov_index(void)
> +{
> + return msg_iov_index;
> +}
> +static inline void set_msg_iov_index(int index)
> +{
> + msg_iov_index = index;
> +}
> +static inline void incr_msg_iov_index(void)
> +{
> + ++msg_iov_index;
> +}
> +
> +extern int batch_size;
> +static inline int get_batch_size(void)
> +{
> + return batch_size;
> +}
> +static inline void set_batch_size(int size)
> +{
> + batch_size = size;
> +}
Iproute2 is C not C++; no accessors for every variable.
> int rtnl_talk(struct rtnl_handle *rtnl, struct nlmsghdr *n,
> struct nlmsghdr **answer)
> __attribute__((warn_unused_result));
> diff --git a/include/utils.h b/include/utils.h
> index d3895d56..66cb4747 100644
> --- a/include/utils.h
> +++ b/include/utils.h
> @@ -235,6 +235,14 @@ void print_nlmsg_timestamp(FILE *fp, const struct nlmsghdr *n);
>
> extern int cmdlineno;
> ssize_t getcmdline(char **line, size_t *len, FILE *in);
> +
> +extern int cmdlinetotal;
> +static inline int getcmdlinetotal(void)
> +{
> + return cmdlinetotal;
> +}
> +void setcmdlinetotal(const char *name);
> +
> int makeargs(char *line, char *argv[], int maxargs);
> int inet_get_addr(const char *src, __u32 *dst, struct in6_addr *dst6);
>
> diff --git a/lib/libnetlink.c b/lib/libnetlink.c
> index 00e6ce0c..f9be1c6d 100644
> --- a/lib/libnetlink.c
> +++ b/lib/libnetlink.c
> @@ -24,6 +24,7 @@
> #include <sys/uio.h>
>
> #include "libnetlink.h"
> +#include "utils.h"
>
> #ifndef SOL_NETLINK
> #define SOL_NETLINK 270
> @@ -581,6 +582,10 @@ static void rtnl_talk_error(struct nlmsghdr *h, struct nlmsgerr *err,
> strerror(-err->error));
> }
>
> +static struct iovec msg_iov[MSG_IOV_MAX];
> +int msg_iov_index;
> +int batch_size = 1;
> +
> static int __rtnl_talk(struct rtnl_handle *rtnl, struct nlmsghdr *n,
> struct nlmsghdr **answer,
> bool show_rtnl_err, nl_ext_ack_fn_t errfn)
> @@ -589,23 +594,34 @@ static int __rtnl_talk(struct rtnl_handle *rtnl, struct nlmsghdr *n,
> unsigned int seq;
> struct nlmsghdr *h;
> struct sockaddr_nl nladdr = { .nl_family = AF_NETLINK };
> - struct iovec iov = {
> - .iov_base = n,
> - .iov_len = n->nlmsg_len
> - };
> + struct iovec *iov = &msg_iov[get_msg_iov_index()];
> + int index;
> + char *buf;
> +
> + iov->iov_base = n;
> + iov->iov_len = n->nlmsg_len;
> +
> + incr_msg_iov_index();
> struct msghdr msg = {
> .msg_name = &nladdr,
> .msg_namelen = sizeof(nladdr),
> - .msg_iov = &iov,
> - .msg_iovlen = 1,
> + .msg_iov = msg_iov,
> + .msg_iovlen = get_msg_iov_index(),
> };
> - char *buf;
>
> n->nlmsg_seq = seq = ++rtnl->seq;
>
> if (answer == NULL)
> n->nlmsg_flags |= NLM_F_ACK;
Your real performance win is just not asking for ACK for every rule.
If you switched to pure streaming mode, then the batching wouldn't
be necessary.
>
> + index = get_msg_iov_index() % get_batch_size();
> + if (index != 0 && get_batch_size() > 1 &&
> + cmdlineno != getcmdlinetotal() &&
> + (n->nlmsg_type == RTM_NEWTFILTER ||
> + n->nlmsg_type == RTM_NEWACTION))
> + return 3;
> + set_msg_iov_index(index);
> +
> status = sendmsg(rtnl->fd, &msg, 0);
> if (status < 0) {
> perror("Cannot talk to rtnetlink");
> diff --git a/lib/utils.c b/lib/utils.c
> index 7ced8c06..53ca389f 100644
> --- a/lib/utils.c
> +++ b/lib/utils.c
> @@ -1202,6 +1202,26 @@ ssize_t getcmdline(char **linep, size_t *lenp, FILE *in)
> return cc;
> }
>
> +int cmdlinetotal;
> +
> +void setcmdlinetotal(const char *name)
> +{
> + char *line = NULL;
> + size_t len = 0;
> +
> + if (name && strcmp(name, "-") != 0) {
> + if (freopen(name, "r", stdin) == NULL) {
> + fprintf(stderr, "Cannot open file \"%s\" for reading: %s\n",
> + name, strerror(errno));
> + return;
> + }
> + }
> +
> + cmdlinetotal = 0;
> + while (getcmdline(&line, &len, stdin) != -1)
> + cmdlinetotal++;
> +}
> +
> /* split command line into argument vector */
> int makeargs(char *line, char *argv[], int maxargs)
> {
> diff --git a/man/man8/tc.8 b/man/man8/tc.8
> index ff071b33..de137e16 100644
> --- a/man/man8/tc.8
> +++ b/man/man8/tc.8
> @@ -601,6 +601,11 @@ must exist already.
> read commands from provided file or standard input and invoke them.
> First failure will cause termination of tc.
>
> +.TP
> +.BR "\-bs", " \-bs size", " \-batchsize", " \-batchsize size"
> +How many commands are accumulated before sending to kernel.
> +By default, it is 1. It only takes effect in batch mode.
> +
> .TP
> .BR "\-force"
> don't terminate tc on errors in batch mode.
> diff --git a/tc/m_action.c b/tc/m_action.c
> index 13f942bf..574b78ca 100644
> --- a/tc/m_action.c
> +++ b/tc/m_action.c
> @@ -23,6 +23,7 @@
> #include <arpa/inet.h>
> #include <string.h>
> #include <dlfcn.h>
> +#include <errno.h>
>
> #include "utils.h"
> #include "tc_common.h"
> @@ -546,33 +547,65 @@ bad_val:
> return ret;
> }
>
> +typedef struct {
> + struct nlmsghdr n;
> + struct tcamsg t;
> + char buf[MAX_MSG];
> +} tc_action_req;
> +
> +static tc_action_req *action_reqs;
> +
> +void free_action_reqs(void)
> +{
> + if (action_reqs)
> + free(action_reqs);
> +}
> +
> +static tc_action_req *get_action_req(void)
> +{
> + tc_action_req *req;
> +
> + if (action_reqs == NULL) {
> + action_reqs = malloc(get_batch_size() * sizeof (tc_action_req));
> + if (action_reqs == NULL)
> + return NULL;
> + }
> + req = &action_reqs[get_msg_iov_index()];
> + memset(req, 0, sizeof (*req));
> +
> + return req;
> +}
> +
> static int tc_action_modify(int cmd, unsigned int flags,
> int *argc_p, char ***argv_p)
> {
> int argc = *argc_p;
> char **argv = *argv_p;
> int ret = 0;
> - struct {
> - struct nlmsghdr n;
> - struct tcamsg t;
> - char buf[MAX_MSG];
> - } req = {
> - .n.nlmsg_len = NLMSG_LENGTH(sizeof(struct tcamsg)),
> - .n.nlmsg_flags = NLM_F_REQUEST | flags,
> - .n.nlmsg_type = cmd,
> - .t.tca_family = AF_UNSPEC,
> - };
> - struct rtattr *tail = NLMSG_TAIL(&req.n);
> + tc_action_req *req;
> +
> + req = get_action_req();
> + if (req == NULL) {
> + fprintf(stderr, "get_action_req error: not enough buffer\n");
> + return -ENOMEM;
> + }
> +
> + req->n.nlmsg_len = NLMSG_LENGTH(sizeof(struct tcamsg));
> + req->n.nlmsg_flags = NLM_F_REQUEST | flags;
> + req->n.nlmsg_type = cmd;
> + req->t.tca_family = AF_UNSPEC;
> + struct rtattr *tail = NLMSG_TAIL(&req->n);
>
> argc -= 1;
> argv += 1;
> - if (parse_action(&argc, &argv, TCA_ACT_TAB, &req.n)) {
> + if (parse_action(&argc, &argv, TCA_ACT_TAB, &req->n)) {
> fprintf(stderr, "Illegal \"action\"\n");
> return -1;
> }
> - tail->rta_len = (void *) NLMSG_TAIL(&req.n) - (void *) tail;
> + tail->rta_len = (void *) NLMSG_TAIL(&req->n) - (void *) tail;
>
> - if (rtnl_talk(&rth, &req.n, NULL) < 0) {
> + ret = rtnl_talk(&rth, &req->n, NULL);
> + if (ret < 0) {
> fprintf(stderr, "We have an error talking to the kernel\n");
> ret = -1;
> }
> @@ -739,5 +772,5 @@ int do_action(int argc, char **argv)
> return -1;
> }
>
> - return 0;
> + return ret;
> }
> diff --git a/tc/tc.c b/tc/tc.c
> index ad9f07e9..9c8e828b 100644
> --- a/tc/tc.c
> +++ b/tc/tc.c
> @@ -189,7 +189,7 @@ static void usage(void)
> fprintf(stderr, "Usage: tc [ OPTIONS ] OBJECT { COMMAND | help }\n"
> " tc [-force] -batch filename\n"
> "where OBJECT := { qdisc | class | filter | action | monitor | exec }\n"
> - " OPTIONS := { -s[tatistics] | -d[etails] | -r[aw] | -p[retty] | -b[atch] [filename] | -n[etns] name |\n"
> + " OPTIONS := { -s[tatistics] | -d[etails] | -r[aw] | -p[retty] | -b[atch] [filename] | -bs | -batchsize [size] | -n[etns] name |\n"
> " -nm | -nam[es] | { -cf | -conf } path } | -j[son]\n");
> }
>
> @@ -223,6 +223,9 @@ static int batch(const char *name)
> size_t len = 0;
> int ret = 0;
>
> + if (get_batch_size() > 1)
> + setcmdlinetotal(name);
> +
> batch_mode = 1;
> if (name && strcmp(name, "-") != 0) {
> if (freopen(name, "r", stdin) == NULL) {
> @@ -248,15 +251,22 @@ static int batch(const char *name)
> if (largc == 0)
> continue; /* blank line */
>
> - if (do_cmd(largc, largv)) {
> + ret = do_cmd(largc, largv);
> + if (ret != 0 && ret != 3) {
> fprintf(stderr, "Command failed %s:%d\n", name, cmdlineno);
> ret = 1;
> if (!force)
> break;
> }
> }
> + if (ret == 3)
> + fprintf(stderr,
> + "Command is not sent to kernel due to internal error %s:%d\n",
> + name, cmdlineno);
> if (line)
> free(line);
> + free_filter_reqs();
> + free_action_reqs();
>
> rtnl_close(&rth);
> return ret;
> @@ -267,6 +277,7 @@ int main(int argc, char **argv)
> {
> int ret;
> char *batch_file = NULL;
> + int size;
>
> while (argc > 1) {
> if (argv[1][0] != '-')
> @@ -297,6 +308,16 @@ int main(int argc, char **argv)
> if (argc <= 1)
> usage();
> batch_file = argv[1];
> + } else if (matches(argv[1], "-batchsize") == 0 ||
> + matches(argv[1], "-bs") == 0) {
> + argc--; argv++;
> + if (argc <= 1)
> + usage();
> + size = atoi(argv[1]);
> + if (size > MSG_IOV_MAX)
> + set_batch_size(MSG_IOV_MAX);
> + else
> + set_batch_size(size);
> } else if (matches(argv[1], "-netns") == 0) {
> NEXT_ARG();
> if (netns_switch(argv[1]))
> @@ -342,6 +363,8 @@ int main(int argc, char **argv)
> }
>
> ret = do_cmd(argc-1, argv+1);
> + free_filter_reqs();
> + free_action_reqs();
> Exit:
> rtnl_close(&rth);
>
> diff --git a/tc/tc_common.h b/tc/tc_common.h
> index 264fbdac..fde8db1b 100644
> --- a/tc/tc_common.h
> +++ b/tc/tc_common.h
> @@ -24,5 +24,8 @@ struct tc_sizespec;
> extern int parse_size_table(int *p_argc, char ***p_argv, struct tc_sizespec *s);
> extern int check_size_table_opts(struct tc_sizespec *s);
>
> +extern void free_filter_reqs(void);
> +extern void free_action_reqs(void);
> +
> extern int show_graph;
> extern bool use_names;
> diff --git a/tc/tc_filter.c b/tc/tc_filter.c
> index 545cc3a1..dc53c128 100644
> --- a/tc/tc_filter.c
> +++ b/tc/tc_filter.c
> @@ -19,6 +19,7 @@
> #include <arpa/inet.h>
> #include <string.h>
> #include <linux/if_ether.h>
> +#include <errno.h>
>
> #include "rt_names.h"
> #include "utils.h"
> @@ -42,18 +43,51 @@ static void usage(void)
> "OPTIONS := ... try tc filter add <desired FILTER_KIND> help\n");
> }
>
> +typedef struct {
> + struct nlmsghdr n;
> + struct tcmsg t;
> + char buf[MAX_MSG];
> +} tc_filter_req;
> +
> +static tc_filter_req *filter_reqs;
> +
> +void free_filter_reqs(void)
> +{
> + if (filter_reqs)
> + free(filter_reqs);
> +}
You don't need to check for NULL when calling free.
free(NULL) is a nop.
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