* Re: [**EXTERNAL**] Re: VRF with enslaved L3 enabled bridge
From: David Ahern @ 2018-09-07 16:09 UTC (permalink / raw)
To: D'Souza, Nelson, netdev@vger.kernel.org; +Cc: Ido Schimmel
In-Reply-To: <BYAPR04MB3797F5219C2164F3C0B6DE57AD000@BYAPR04MB3797.namprd04.prod.outlook.com>
On 9/7/18 9:56 AM, D'Souza, Nelson wrote:
> ------------------------------------------------------------------------
> *From:* David Ahern <dsa@cumulusnetworks.com>
> *Sent:* Thursday, September 6, 2018 5:27 PM
> *To:* D'Souza, Nelson; netdev@vger.kernel.org
> *Subject:* Re: [**EXTERNAL**] Re: VRF with enslaved L3 enabled bridge
>
> On 9/5/18 12:00 PM, D'Souza, Nelson wrote:
>> Just following up.... would you be able to confirm that this is a
> Linux VRF issue?
>
> I can confirm that I can reproduce the problem. Need to find time to dig
> into it.
bridge's netfilter hook is dropping the packet.
bridge's netfilter code registers hook operations that are invoked when
nh_hook is called. It then sees all subsequent calls to nf_hook.
Packet wise, the bridge netfilter hook runs first. br_nf_pre_routing
allocates nf_bridge, sets in_prerouting to 1 and calls NF_HOOK for
NF_INET_PRE_ROUTING. It's finish function, br_nf_pre_routing_finish,
then resets in_prerouting flag to 0. Any subsequent calls to nf_hook
invoke ip_sabotage_in. That function sees in_prerouting is not
set and steals (drops) the packet.
The simplest change is to have ip_sabotage_in recognize that the bridge
can be enslaved to a VRF (L3 master device) and allow the packet to
continue.
Thanks to Ido for the hint on ip_sabotage_in.
This patch works for me:
diff --git a/net/bridge/br_netfilter_hooks.c
b/net/bridge/br_netfilter_hooks.c
index 6e0dc6bcd32a..37278dc280eb 100644
--- a/net/bridge/br_netfilter_hooks.c
+++ b/net/bridge/br_netfilter_hooks.c
@@ -835,7 +835,8 @@ static unsigned int ip_sabotage_in(void *priv,
struct sk_buff *skb,
const struct nf_hook_state *state)
{
- if (skb->nf_bridge && !skb->nf_bridge->in_prerouting) {
+ if (skb->nf_bridge && !skb->nf_bridge->in_prerouting &&
+ !netif_is_l3_master(skb->dev)) {
state->okfn(state->net, state->sk, skb);
return NF_STOLEN;
}
^ permalink raw reply related
* RE: [PATCH v3 1/2] net: ethernet: i40e: fix build error
From: Keller, Jacob E @ 2018-09-07 21:42 UTC (permalink / raw)
To: Wang, Dongsheng, Kirsher, Jeffrey T,
sergei.shtylyov@cogentembedded.com
Cc: davem@davemloft.net, intel-wired-lan@lists.osuosl.org,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
Wyborny, Carolyn
In-Reply-To: <f2b0bdfcb53c461191e71603257874ac@HXTBJIDCEMVIW02.hxtcorp.net>
> -----Original Message-----
> From: Wang, Dongsheng [mailto:dongsheng.wang@hxt-semitech.com]
> Sent: Friday, September 07, 2018 5:41 AM
> To: Kirsher, Jeffrey T <jeffrey.t.kirsher@intel.com>;
> sergei.shtylyov@cogentembedded.com
> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; davem@davemloft.net; intel-
> wired-lan@lists.osuosl.org; netdev@vger.kernel.org; linux-
> kernel@vger.kernel.org; Wyborny, Carolyn <carolyn.wyborny@intel.com>
> Subject: Re: [PATCH v3 1/2] net: ethernet: i40e: fix build error
>
> Hello all,
>
> The i40e_ethtool_stats.h is just included by i40e/i40e_ethtool.c. So the
> static doesn't make any affect. And Carolyn's team is working rebuild
> i40e and i40evf.
>
> Cheers,
> Dongsheng
Dave wanted a fix sent to netdev by end of day today. I think the best immediate solution is to just migrate that code back into the i40e_ethtool.c and i40evf_ethtool.c files, rather than only the single function.
I'm going to send that patch to netdev now, since Jeff Kirsher is on vacation.
Thanks,
Jake
^ permalink raw reply
* Re: [PATCH] ethernet: hnae: add unlikely() to assert()
From: David Miller @ 2018-09-07 21:46 UTC (permalink / raw)
To: igor.stoppa
Cc: huangdaode, igor.stoppa, yisen.zhuang, salil.mehta, netdev,
linux-kernel
In-Reply-To: <20180907172650.29408-1-igor.stoppa@huawei.com>
From: Igor Stoppa <igor.stoppa@gmail.com>
Date: Fri, 7 Sep 2018 20:26:50 +0300
> The assert() condition is likely to be true.
Worse than that is that drivers should not be definiting their own
private "assert()" macro.
I'd rather have that fixed instead. We have tons of standard kernel
facilities that do what they are trying to do here, without overloading
the standard C namespace in this way.
^ permalink raw reply
* Re: [PATCH] PCI: Reprogram bridge prefetch registers on resume
From: Bjorn Helgaas @ 2018-09-07 21:48 UTC (permalink / raw)
To: Daniel Drake
Cc: bhelgaas, linux-pci, linux, nouveau, linux-pm, peter, kherbst,
andriy.shevchenko, rafael.j.wysocki, keith.busch, mika.westerberg,
jonathan.derrick, kugel, davem, hkallweit1, netdev, nic_swsd,
linux-kernel
In-Reply-To: <20180907053614.6540-1-drake@endlessm.com>
[+cc LKML]
On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote:
> On 38+ Intel-based Asus products, the nvidia GPU becomes unusable
> after S3 suspend/resume. The affected products include multiple
> generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs
> many errors such as:
>
> fifo: fault 00 [READ] at 0000005555555000 engine 00 [GR] client 04 [HUB/FE] reason 4a [] on channel -1 [007fa91000 unknown]
> DRM: failed to idle channel 0 [DRM]
>
> Similarly, the nvidia proprietary driver also fails after resume
> (black screen, 100% CPU usage in Xorg process). We shipped a sample
> to Nvidia for diagnosis, and their response indicated that it's a
> problem with the parent PCI bridge (on the Intel SoC), not the GPU.
>
> Runtime suspend/resume works fine, only S3 suspend is affected.
>
> We found a workaround: on resume, rewrite the Intel PCI bridge
> 'Prefetchable Base Upper 32 Bits' register (PCI_PREF_BASE_UPPER32). In
> the cases that I checked, this register has value 0 and we just have to
> rewrite that value.
>
> It's very strange that rewriting the exact same register value
> makes a difference, but it definitely makes the issue go away.
> It's not just acting as some kind of memory barrier, because rewriting
> other bridge registers does not work around the issue. There's something
> magic in this particular register. We have confirmed this on all
> the affected models we have in-hands (X542UQ, UX533FD, X530UN, V272UN).
>
> Additionally, this workaround solves an issue where r8169 MSI-X
> interrupts were broken after S3 suspend/resume on Asus X441UAR. This
> issue was recently worked around in commit 7bb05b85bc2d ("r8169:
> don't use MSI-X on RTL8106e"). It also fixes the same issue on
> RTL6186evl/8111evl on an Aimfor-tech laptop that we had not yet
> patched. I suspect it will also fix the issue that was worked around in
> commit 7c53a722459c ("r8169: don't use MSI-X on RTL8168g").
This is crazy. I would think *lots* of devices, like anything that
uses prefetchable memory, would be affected by this.
> Thomas Martitz reports that this workaround also solves an issue where
> the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive
> after S3 suspend/resume.
>
> From our testing, the affected Intel PCI bridges are:
> Intel Skylake PCIe Controller (x16) [8086:1901] (rev 05)
> Intel Skylake PCIe Controller (x16) [8086:1901] (rev 07)
> Intel Device [8086:31d8] (rev f3)
> Intel Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1 [8086:5ad6] (rev fb)
> Intel Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port A #1 [8086:5ad8] (rev fb)
> Intel Sunrise Point-LP PCI Express Root Port [8086:9d10] (rev f1)
> Intel Sunrise Point-LP PCI Express Root Port #5 [8086:9d14] (rev f1)
> Intel Device [8086:9dbc] (rev f0)
>
> On resume, reprogram the PCI bridge prefetch registers, including the
> magic register mentioned above.
>
> This matches Win10 behaviour, which also rewrites these registers
> during S3 resume (checked with qemu tracing).
>
> Link: https://marc.info/?i=CAD8Lp46Y2eOR7WE28xToUL8s-aYiqPa0nS=1GSD0AxkddXq6+A@mail.gmail.com
Can you use
https://lkml.kernel.org/r/CAD8Lp46Y2eOR7WE28xToUL8s-aYiqPa0nS=1GSD0AxkddXq6+A@mail.gmail.com
instead, so we don't depend on marc.info? lkml.kernel.org doesn't have
linux-pci archives, but it might someday, and it does redirect to other
archives already.
> Link: https://bugs.freedesktop.org/show_bug.cgi?id=105760
I would really like to have a bugzilla.kernel.org issue with the
excellent debugging you and Peter did attached. Then we don't also
have to depend on github.com, etc., sticking around.
The list of platforms below could also be attached there, since you
went to a lot of trouble to collect it, but it's probably more than is
necessary for the changelog.
> Signed-off-by: Daniel Drake <drake@endlessm.com>
> ---
>
> Notes:
> Replaces patch:
> PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
>
> Below is the list of Asus products with Intel/Nvidia that we
> believe are affected by the GPU resume issue.
>
> I revised my counting method from my last patch to eliminate duplicate
> platforms that had multiple SKUs with the same DMI/GPU/bridge, that's why
> the product count reduced from 43 to 38.
>
> sys_vendor: ASUSTeK COMPUTER INC.
> board_name: FX502VD
> product_name: FX502VD
> 01:00.0 3D controller [0302]: NVIDIA Corporation Device [10de:1c8d] (rev ff) (prog-if ff)
> !!! Unknown header type 7f
> 00:01.0 PCI bridge [0604]: Intel Corporation Device [8086:1901] (rev 05) (prog-if 00 [Normal decode])
> ...
^ permalink raw reply
* Re: [PATCH] freescale: ethernet: remove unnecessary unlikely()
From: David Miller @ 2018-09-07 21:50 UTC (permalink / raw)
To: igor.stoppa; +Cc: madalin.bucur, igor.stoppa, netdev, linux-kernel
In-Reply-To: <20180907172318.29014-1-igor.stoppa@huawei.com>
From: Igor Stoppa <igor.stoppa@gmail.com>
Date: Fri, 7 Sep 2018 20:23:18 +0300
> Both WARN_ON() and WARN_ONCE() already contain an unlikely(), so it's not
> necessary to wrap it into another.
>
> Signed-off-by: Igor Stoppa <igor.stoppa@huawei.com>
Applied.
^ permalink raw reply
* Re: [PATCH net-next] net: dsa: Expose tagging protocol to user-space
From: David Miller @ 2018-09-07 21:51 UTC (permalink / raw)
To: f.fainelli; +Cc: netdev, andrew, vivien.didelot, linux-kernel
In-Reply-To: <20180907180908.3223-1-f.fainelli@gmail.com>
From: Florian Fainelli <f.fainelli@gmail.com>
Date: Fri, 7 Sep 2018 11:09:02 -0700
> There is no way for user-space to know what a given DSA network device's
> tagging protocol is. Expose this information through a dsa/tagging
> attribute which reflects the tagging protocol currently in use.
>
> This is helpful for configuration (e.g: none behaves dramatically
> different wrt. bridges) as well as for packet capture tools when there
> is not a proper Ethernet type available.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Applied, thanks Florian.
^ permalink raw reply
* Re: [PATCH] r8169: set TxConfig register after TX / RX is enabled, just like RxConfig
From: David Miller @ 2018-09-07 21:53 UTC (permalink / raw)
To: mail; +Cc: nic_swsd, netdev, linux-kernel, a3at.mail, hkallweit1
In-Reply-To: <fd32f0db-373a-2ee4-8a99-5fe6c5441606@maciej.szmigiero.name>
From: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name>
Date: Fri, 7 Sep 2018 20:15:22 +0200
> Commit 3559d81e76bf ("r8169: simplify rtl_hw_start_8169") changed order of
> two register writes:
> 1) Caused RxConfig to be written before TX / RX is enabled,
> 2) Caused TxConfig to be written before TX / RX is enabled.
>
> At least on XIDs 10000000 ("RTL8169sb/8110sb") and
> 18000000 ("RTL8169sc/8110sc") such writes are ignored by the chip, leaving
> values in these registers intact.
>
> Change 1) was reverted by
> commit 05212ba8132b42 ("r8169: set RxConfig after tx/rx is enabled for RTL8169sb/8110sb devices"),
> however change 2) wasn't.
>
> In practice, this caused TxConfig's "InterFrameGap time" and "Max DMA Burst
> Size per Tx DMA Burst" bits to be zero dramatically reducing TX performance
> (in my tests it dropped from around 500Mbps to around 50Mbps).
>
> This patch fixes the issue by moving TxConfig register write a bit later in
> the code so it happens after TX / RX is already enabled.
>
> Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
> Fixes: 05212ba8132b42 ("r8169: set RxConfig after tx/rx is enabled for RTL8169sb/8110sb devices")
> ---
> "Fixes" tag points to the RxConfig fix instead of the actual commit that
> introduced this regression to maintain patch ordering since the RxConfig fix
> partially affects the same code lines as this fix.
Applied, thanks.
Please, in the future, always put your Fixes: tag first in the set of tags.
Thank you.
^ permalink raw reply
* Re: [PATCH v3 3/3] IB/ipoib: Log sysfs 'dev_id' accesses from userspace
From: Doug Ledford @ 2018-09-07 17:14 UTC (permalink / raw)
To: Leon Romanovsky, Arseny Maslennikov; +Cc: linux-rdma, Jason Gunthorpe, netdev
In-Reply-To: <20180906130358.GJ3142@mtr-leonro.mtl.com>
[-- Attachment #1: Type: text/plain, Size: 3831 bytes --]
On Thu, 2018-09-06 at 16:03 +0300, Leon Romanovsky wrote:
> On Thu, Sep 06, 2018 at 10:04:33AM +0300, Arseny Maslennikov wrote:
> > On Wed, Sep 05, 2018 at 04:50:35PM +0300, Leon Romanovsky wrote:
> > > On Mon, Sep 03, 2018 at 07:13:16PM +0300, Arseny Maslennikov wrote:
> > > > Signed-off-by: Arseny Maslennikov <ar@cs.msu.ru>
> > > > ---
> > > > drivers/infiniband/ulp/ipoib/ipoib_main.c | 38 +++++++++++++++++++++++
> > > > 1 file changed, 38 insertions(+)
> > > >
> > > > diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > index 30f840f874b3..7386e5bde3d3 100644
> > > > --- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > @@ -2386,6 +2386,42 @@ int ipoib_add_pkey_attr(struct net_device *dev)
> > > > return device_create_file(&dev->dev, &dev_attr_pkey);
> > > > }
> > > >
> > > > +/*
> > > > + * We erroneously exposed the iface's port number in the dev_id
> > > > + * sysfs field long after dev_port was introduced for that purpose[1],
> > > > + * and we need to stop everyone from relying on that.
> > > > + * Let's overload the shower routine for the dev_id file here
> > > > + * to gently bring the issue up.
> > > > + *
> > > > + * [1] https://www.spinics.net/lists/netdev/msg272123.html
> > > > + */
> > > > +static ssize_t dev_id_show(struct device *dev,
> > > > + struct device_attribute *attr, char *buf)
> > > > +{
> > > > + struct net_device *ndev = to_net_dev(dev);
> > > > + ssize_t ret = -EINVAL;
> > > > +
> > > > + if (ndev->dev_id == ndev->dev_port) {
> > > > + netdev_info_once(ndev,
> > > > + "\"%s\" wants to know my dev_id. "
> > > > + "Should it look at dev_port instead?\n",
> > > > + current->comm);
> > > > + netdev_info_once(ndev,
> > > > + "See Documentation/ABI/testing/sysfs-class-net for more info.\n");
> > > > + }
> > > > +
> > > > + ret = sprintf(buf, "%#x\n", ndev->dev_id);
> > > > +
> > > > + return ret;
> > > > +}
> > > > +static DEVICE_ATTR_RO(dev_id);
> > > > +
> > >
> > > I don't see this field among exposed by IPoIB, why should we expose it now?
> > >
> >
> > To deviate from standard netdev behaviour, which only prints the
> > field out. Doug wanted this to also print a deprecation message, and
> > netdev (obviously) does not do that. See below.
> >
> > > > +int ipoib_intercept_dev_id_attr(struct net_device *dev)
> > > > +{
> > > > + device_remove_file(&dev->dev, &dev_attr_dev_id);
> > > > + return device_create_file(&dev->dev, &dev_attr_dev_id);
> > >
> > > Why isn't enough to rely on netdev code?
> > >
> >
> > Netdev code relies on macros around a *static* function 'netdev_show',
> > which is defined in net/core/net-sysfs.c; it is not listed in any header
> > files, and the macros aren't as well. This all leads me to believe it
> > was not really meant to be used from outside net/core/net-sysfs.
> >
> > The only way we could use any netdev code here is to set up our own
> > handler (again), printk() a message, then call netdev_show — but we have
> > no access to it.
> >
> > Of course, it also may be that I'm terribly missing a clue.
>
> Thanks,
>
> IMHO, the end result of adequate Doug's request is a little bit too much.
> I don't think that it justifies such remove->create construction.
>
> Personal opinion.
I agree with you that the end result is kinda bulky, *but*, we will need
to know if there are things using the old dev_id before we can remove
it. In particular, I'm concerned the IPoIB handling code of
NetworkManager uses it. It's worth the cost I think.
--
Doug Ledford <dledford@redhat.com>
GPG KeyID: B826A3330E572FDD
Key fingerprint = AE6B 1BDA 122B 23B4 265B 1274 B826 A333 0E57 2FDD
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply
* Re: [PATCH v4 3/3] IB/ipoib: Log sysfs 'dev_id' accesses from userspace
From: Doug Ledford @ 2018-09-07 17:14 UTC (permalink / raw)
To: Jason Gunthorpe, Arseny Maslennikov; +Cc: linux-rdma, netdev
In-Reply-To: <20180907154359.GA14627@ziepe.ca>
[-- Attachment #1: Type: text/plain, Size: 3054 bytes --]
On Fri, 2018-09-07 at 09:43 -0600, Jason Gunthorpe wrote:
> On Thu, Sep 06, 2018 at 05:51:12PM +0300, Arseny Maslennikov wrote:
> > Some tools may currently be using only the deprecated attribute;
> > let's print an elaborate and clear deprecation notice to kmsg.
> >
> > To do that, we have to replace the whole sysfs file, since we inherit
> > the original one from netdev.
> >
> > Signed-off-by: Arseny Maslennikov <ar@cs.msu.ru>
> > drivers/infiniband/ulp/ipoib/ipoib_main.c | 31 +++++++++++++++++++++++
> > 1 file changed, 31 insertions(+)
> >
> > diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > index 30f840f874b3..74732726ec6f 100644
> > +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > @@ -2386,6 +2386,35 @@ int ipoib_add_pkey_attr(struct net_device *dev)
> > return device_create_file(&dev->dev, &dev_attr_pkey);
> > }
> >
> > +/*
> > + * We erroneously exposed the iface's port number in the dev_id
> > + * sysfs field long after dev_port was introduced for that purpose[1],
> > + * and we need to stop everyone from relying on that.
> > + * Let's overload the shower routine for the dev_id file here
> > + * to gently bring the issue up.
> > + *
> > + * [1] https://www.spinics.net/lists/netdev/msg272123.html
> > + */
> > +static ssize_t dev_id_show(struct device *dev,
> > + struct device_attribute *attr, char *buf)
> > +{
> > + struct net_device *ndev = to_net_dev(dev);
> > +
> > + if (ndev->dev_id == ndev->dev_port)
> > + netdev_info_once(ndev,
> > + "\"%s\" wants to know my dev_id. Should it look at dev_port instead? See Documentation/ABI/testing/sysfs-class-net for more info.\n",
> > + current->comm);
> > +
> > + return sprintf(buf, "%#x\n", ndev->dev_id);
> > +}
> > +static DEVICE_ATTR_RO(dev_id);
> > +
> > +int ipoib_intercept_dev_id_attr(struct net_device *dev)
> > +{
> > + device_remove_file(&dev->dev, &dev_attr_dev_id);
> > + return device_create_file(&dev->dev, &dev_attr_dev_id);
> > +}
>
> Isn't this racey with userspace? Ie what happens if udev is querying
> the dev_id right here?
>
> Do we know there is no userspace doing this?
I don't think that it can race (or reasonably can). The intercept
function is done as part of ipoib_add_port() so the port itself isn't
live yet. Things like udev shouldn't be scanning it until after we've
finished bringing it up and added it to the system, so any race here is
unimportant IMO.
> > static struct net_device *ipoib_add_port(const char *format,
> > struct ib_device *hca, u8 port)
> > {
> > @@ -2427,6 +2456,8 @@ static struct net_device *ipoib_add_port(const char *format,
> > */
> > ndev->priv_destructor = ipoib_intf_free;
> >
> > + if (ipoib_intercept_dev_id_attr(ndev))
> > + goto sysfs_failed;
>
> No device_remove_file needed?
>
> Jason
--
Doug Ledford <dledford@redhat.com>
GPG KeyID: B826A3330E572FDD
Key fingerprint = AE6B 1BDA 122B 23B4 265B 1274 B826 A333 0E57 2FDD
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 0/5] introduce setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 functions
From: David Miller @ 2018-09-07 21:57 UTC (permalink / raw)
To: clabbe
Cc: Gilles.Muller, Julia.Lawall, agust, alexandre.torgue, alistair,
benh, carlo, galak, joabreu, khilman, maxime.ripard, michal.lkml,
mpe, mporter, nicolas.palix, oss, paulus, peppe.cavallaro, tj,
vitb, wens, cocci, linux-amlogic, linux-arm-kernel, linux-ide,
linux-kernel, linuxppc-dev, netdev, linux-sunxi
In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com>
If you are going to do this, please add for_each_set_bit64() and similar.
For example, see:
https://marc.info/?l=linux-netdev&m=153633391214025&w=2
^ permalink raw reply
* RE: linux-next: build failure after merge of the net-next tree
From: Keller, Jacob E @ 2018-09-07 22:03 UTC (permalink / raw)
To: David Miller
Cc: sfr@canb.auug.org.au, netdev@vger.kernel.org,
linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
Kirsher, Jeffrey T, Bowers, AndrewX
In-Reply-To: <20180907.103112.1943018536705670414.davem@davemloft.net>
> -----Original Message-----
> From: David Miller [mailto:davem@davemloft.net]
> Sent: Friday, September 07, 2018 10:31 AM
> To: Keller, Jacob E <jacob.e.keller@intel.com>
> Cc: sfr@canb.auug.org.au; netdev@vger.kernel.org; linux-next@vger.kernel.org;
> linux-kernel@vger.kernel.org; Kirsher, Jeffrey T <jeffrey.t.kirsher@intel.com>;
> Bowers, AndrewX <andrewx.bowers@intel.com>
> Subject: Re: linux-next: build failure after merge of the net-next tree
>
> From: "Keller, Jacob E" <jacob.e.keller@intel.com>
> Date: Fri, 7 Sep 2018 15:30:42 +0000
>
> > There's some discussion about this going on in the intel-wired-lan
> > mailing list.
>
> I really want to see a pull request in my inbox fixing this by the end
> of today or I'll apply a fix directly at my discretion.
Jeff is out, so I just opted to email a fix to netdev. I hope this is acceptable.
I opted to essentially revert the patch that moved code to i40e_ethtool_stats.h, rather than anything fancier, since it was fast, and correct.
There was a suggestion to only move the one offending function, but I felt that it was better to move everything back into the .c files.
Thanks,
Jake
^ permalink raw reply
* Re: [PATCH v4 3/3] IB/ipoib: Log sysfs 'dev_id' accesses from userspace
From: Jason Gunthorpe @ 2018-09-07 17:24 UTC (permalink / raw)
To: Doug Ledford; +Cc: Arseny Maslennikov, linux-rdma, netdev
In-Reply-To: <2615124df732cc4d8926a708eaf11a47cbac4b3a.camel@redhat.com>
On Fri, Sep 07, 2018 at 01:14:51PM -0400, Doug Ledford wrote:
> On Fri, 2018-09-07 at 09:43 -0600, Jason Gunthorpe wrote:
> > On Thu, Sep 06, 2018 at 05:51:12PM +0300, Arseny Maslennikov wrote:
> > > Some tools may currently be using only the deprecated attribute;
> > > let's print an elaborate and clear deprecation notice to kmsg.
> > >
> > > To do that, we have to replace the whole sysfs file, since we inherit
> > > the original one from netdev.
> > >
> > > Signed-off-by: Arseny Maslennikov <ar@cs.msu.ru>
> > > drivers/infiniband/ulp/ipoib/ipoib_main.c | 31 +++++++++++++++++++++++
> > > 1 file changed, 31 insertions(+)
> > >
> > > diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > index 30f840f874b3..74732726ec6f 100644
> > > +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > @@ -2386,6 +2386,35 @@ int ipoib_add_pkey_attr(struct net_device *dev)
> > > return device_create_file(&dev->dev, &dev_attr_pkey);
> > > }
> > >
> > > +/*
> > > + * We erroneously exposed the iface's port number in the dev_id
> > > + * sysfs field long after dev_port was introduced for that purpose[1],
> > > + * and we need to stop everyone from relying on that.
> > > + * Let's overload the shower routine for the dev_id file here
> > > + * to gently bring the issue up.
> > > + *
> > > + * [1] https://www.spinics.net/lists/netdev/msg272123.html
> > > + */
> > > +static ssize_t dev_id_show(struct device *dev,
> > > + struct device_attribute *attr, char *buf)
> > > +{
> > > + struct net_device *ndev = to_net_dev(dev);
> > > +
> > > + if (ndev->dev_id == ndev->dev_port)
> > > + netdev_info_once(ndev,
> > > + "\"%s\" wants to know my dev_id. Should it look at dev_port instead? See Documentation/ABI/testing/sysfs-class-net for more info.\n",
> > > + current->comm);
> > > +
> > > + return sprintf(buf, "%#x\n", ndev->dev_id);
> > > +}
> > > +static DEVICE_ATTR_RO(dev_id);
> > > +
> > > +int ipoib_intercept_dev_id_attr(struct net_device *dev)
> > > +{
> > > + device_remove_file(&dev->dev, &dev_attr_dev_id);
> > > + return device_create_file(&dev->dev, &dev_attr_dev_id);
> > > +}
> >
> > Isn't this racey with userspace? Ie what happens if udev is querying
> > the dev_id right here?
> >
> > Do we know there is no userspace doing this?
>
> I don't think that it can race (or reasonably can). The intercept
> function is done as part of ipoib_add_port() so the port itself isn't
> live yet.
The above code is after register_netdev, so the port itself is
certainly live as far as userspace is concerned..
All the other sysfs stuff in add_port is already wrong/racy.. See
Parav's recent series fixing this for the main devices..
Jason
^ permalink raw reply
* Re: [PATCH v3 3/3] IB/ipoib: Log sysfs 'dev_id' accesses from userspace
From: Leon Romanovsky @ 2018-09-07 17:28 UTC (permalink / raw)
To: Doug Ledford; +Cc: Arseny Maslennikov, linux-rdma, Jason Gunthorpe, netdev
In-Reply-To: <adc47601cbf388f7909bc01dd3b122d6558cc74e.camel@redhat.com>
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On Fri, Sep 07, 2018 at 01:14:37PM -0400, Doug Ledford wrote:
> On Thu, 2018-09-06 at 16:03 +0300, Leon Romanovsky wrote:
> > On Thu, Sep 06, 2018 at 10:04:33AM +0300, Arseny Maslennikov wrote:
> > > On Wed, Sep 05, 2018 at 04:50:35PM +0300, Leon Romanovsky wrote:
> > > > On Mon, Sep 03, 2018 at 07:13:16PM +0300, Arseny Maslennikov wrote:
> > > > > Signed-off-by: Arseny Maslennikov <ar@cs.msu.ru>
> > > > > ---
> > > > > drivers/infiniband/ulp/ipoib/ipoib_main.c | 38 +++++++++++++++++++++++
> > > > > 1 file changed, 38 insertions(+)
> > > > >
> > > > > diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > index 30f840f874b3..7386e5bde3d3 100644
> > > > > --- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > @@ -2386,6 +2386,42 @@ int ipoib_add_pkey_attr(struct net_device *dev)
> > > > > return device_create_file(&dev->dev, &dev_attr_pkey);
> > > > > }
> > > > >
> > > > > +/*
> > > > > + * We erroneously exposed the iface's port number in the dev_id
> > > > > + * sysfs field long after dev_port was introduced for that purpose[1],
> > > > > + * and we need to stop everyone from relying on that.
> > > > > + * Let's overload the shower routine for the dev_id file here
> > > > > + * to gently bring the issue up.
> > > > > + *
> > > > > + * [1] https://www.spinics.net/lists/netdev/msg272123.html
> > > > > + */
> > > > > +static ssize_t dev_id_show(struct device *dev,
> > > > > + struct device_attribute *attr, char *buf)
> > > > > +{
> > > > > + struct net_device *ndev = to_net_dev(dev);
> > > > > + ssize_t ret = -EINVAL;
> > > > > +
> > > > > + if (ndev->dev_id == ndev->dev_port) {
> > > > > + netdev_info_once(ndev,
> > > > > + "\"%s\" wants to know my dev_id. "
> > > > > + "Should it look at dev_port instead?\n",
> > > > > + current->comm);
> > > > > + netdev_info_once(ndev,
> > > > > + "See Documentation/ABI/testing/sysfs-class-net for more info.\n");
> > > > > + }
> > > > > +
> > > > > + ret = sprintf(buf, "%#x\n", ndev->dev_id);
> > > > > +
> > > > > + return ret;
> > > > > +}
> > > > > +static DEVICE_ATTR_RO(dev_id);
> > > > > +
> > > >
> > > > I don't see this field among exposed by IPoIB, why should we expose it now?
> > > >
> > >
> > > To deviate from standard netdev behaviour, which only prints the
> > > field out. Doug wanted this to also print a deprecation message, and
> > > netdev (obviously) does not do that. See below.
> > >
> > > > > +int ipoib_intercept_dev_id_attr(struct net_device *dev)
> > > > > +{
> > > > > + device_remove_file(&dev->dev, &dev_attr_dev_id);
> > > > > + return device_create_file(&dev->dev, &dev_attr_dev_id);
> > > >
> > > > Why isn't enough to rely on netdev code?
> > > >
> > >
> > > Netdev code relies on macros around a *static* function 'netdev_show',
> > > which is defined in net/core/net-sysfs.c; it is not listed in any header
> > > files, and the macros aren't as well. This all leads me to believe it
> > > was not really meant to be used from outside net/core/net-sysfs.
> > >
> > > The only way we could use any netdev code here is to set up our own
> > > handler (again), printk() a message, then call netdev_show — but we have
> > > no access to it.
> > >
> > > Of course, it also may be that I'm terribly missing a clue.
> >
> > Thanks,
> >
> > IMHO, the end result of adequate Doug's request is a little bit too much.
> > I don't think that it justifies such remove->create construction.
> >
> > Personal opinion.
>
> I agree with you that the end result is kinda bulky, *but*, we will need
> to know if there are things using the old dev_id before we can remove
> it. In particular, I'm concerned the IPoIB handling code of
> NetworkManager uses it. It's worth the cost I think.
I did my checks now and saw that ibdev2netdev uses the value provided
from this dev_id, so every invocation of that script will generate the
warning.
See this line in Parav's repo
https://github.com/Mellanox/container_scripts/blob/master/ibdev2netdev#L112
Thanks
>
> --
> Doug Ledford <dledford@redhat.com>
> GPG KeyID: B826A3330E572FDD
> Key fingerprint = AE6B 1BDA 122B 23B4 265B 1274 B826 A333 0E57 2FDD
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^ permalink raw reply
* Re: [PATCH v3 2/2] net: ethernet: i40evf: fix underlying build error
From: Wang, Dongsheng @ 2018-09-07 17:29 UTC (permalink / raw)
To: Wyborny, Carolyn, Kirsher, Jeffrey T,
sergei.shtylyov@cogentembedded.com
Cc: Keller, Jacob E, davem@davemloft.net,
intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <9BBC4E0CF881AA4299206E2E1412B6267C604A79@ORSMSX102.amr.corp.intel.com>
On 9/7/2018 11:27 PM, Wyborny, Carolyn wrote:
>> -----Original Message-----
>> From: Wang, Dongsheng [mailto:dongsheng.wang@hxt-semitech.com]
>> Sent: Friday, September 07, 2018 5:34 AM
>> To: Kirsher, Jeffrey T <jeffrey.t.kirsher@intel.com>;
>> sergei.shtylyov@cogentembedded.com
>> Cc: Keller, Jacob E <jacob.e.keller@intel.com>; davem@davemloft.net;
>> intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; linux-
>> kernel@vger.kernel.org; Wyborny, Carolyn <carolyn.wyborny@intel.com>
>> Subject: Re: [PATCH v3 2/2] net: ethernet: i40evf: fix underlying build error
>>
>> Hello Jacob,
>>
>> Since Carolyn' team is working this, I think we don't need this patch
>> anymore because this header file is only for ethtool.c.
>> [..]
> Hello Dongsheng,
>
> The commonization effort we're working on is prioritizing our newest drivers. The i40e work is still being scoped, so we should fix this problem as needed now and not wait.
After Sergei agree. ;)
Cheers,
Dongsheng
> I apologize for any miscommunication. Was trying to let people know that we aware of the issue and are trying to make progress in that direction.
>
> Thanks,
>
> Carolyn
>
^ permalink raw reply
* Re: [PATCH] PCI: Reprogram bridge prefetch registers on resume
From: Bjorn Helgaas @ 2018-09-07 22:26 UTC (permalink / raw)
To: Peter Wu
Cc: Daniel Drake, bhelgaas, linux-pci, linux, nouveau, linux-pm,
kherbst, andriy.shevchenko, rafael.j.wysocki, keith.busch,
mika.westerberg, jonathan.derrick, kugel, davem, hkallweit1,
netdev, nic_swsd, linux-kernel, Dave Jones, Luming Yu
In-Reply-To: <20180907150515.GA28739@al>
[+cc LKML, Dave, Luming]
On Fri, Sep 07, 2018 at 05:05:15PM +0200, Peter Wu wrote:
> On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote:
> <..>
> > Thomas Martitz reports that this workaround also solves an issue where
> > the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive
> > after S3 suspend/resume.
>
> Where was this claimed? It is not stated in the linked bug:
> (https://bugs.freedesktop.org/show_bug.cgi?id=105760
>
> > On resume, reprogram the PCI bridge prefetch registers, including the
> > magic register mentioned above.
> >
> > This matches Win10 behaviour, which also rewrites these registers
> > during S3 resume (checked with qemu tracing).
>
> Windows 10 unconditionally rewrites these registers (BAR, I/O Base +
> Limit, Memory Base + Limit, etc. from top to bottom), see annotations:
> https://www.spinics.net/lists/linux-pci/msg75856.html
>
> Linux has a generic "restore" operation that works backwards from the
> end of the PCI config space to the beginning, see
> pci_restore_config_space. Do you have a dmesg where you see the
> "restoring config space at offset" messages?
>
> Would it be reasonable to unconditionally write these registers in
> pci_restore_config_dword, like Windows does?
That sounds reasonable to me.
We did write them unconditionally, prior to 04d9c1a1100b ("[PATCH]
PCI: Improve PCI config space writeback") [1]. That commit apparently
fixed suspend on some laptop.
But at that time, we restored the config space in order of dword 0, 1,
2, ... 15, which means we restored the command register before the
BARs and windows, and it's conceivable that the problem was the
ordering, not the rewriting of the same value.
Only a week later, we reversed the order with 8b8c8d280ab2 ("[PATCH]
PCI: reverse pci config space restore order") [2], which seems like a
good idea and even includes a spec reference. I found similar
language in the Intel ICH 10 datasheet, sec 14.1.3 [3].
So it seems reasonable to me to try writing them unconditionally in
reverse order (the same order we use today).
[1] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=04d9c1a1100b
[2] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=8b8c8d280ab2
[3] Intel ICH 10 IBL 373635
^ permalink raw reply
* Re: [PATCH net-next] veth: report NEWLINK event when moving the peer device in a new namespace
From: Thomas Haller @ 2018-09-07 18:52 UTC (permalink / raw)
To: David Ahern, Lorenzo Bianconi; +Cc: David S. Miller, Network Development
In-Reply-To: <76fe95ba-d80f-e420-1982-97019aa09d7c@gmail.com>
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Hi David,
On Mon, 2018-09-03 at 20:54 -0600, David Ahern wrote:
> From init_net:
> $ ip monitor all-nsid
I thought the concern of the patch is the overhead of sending one
additional RTM_NEWLINK message. This workaround has likely higher
overhead. More importantly, it's so cumbersome, that I doubt anybody
would implementing such a solution.
When the events of one namespace are not sufficient to get all relevant
information (local to the namespace itself), the solution is not
monitor all-nsid.
You might save complexity and performance overhead in kernel. But what
you save here is just moved to user-space, which faces higher
complexity (at multiple places/projects, where developers are not
experts in netlink) and higher overhead.
RTM_GETLINK/NLM_F_DUMP allows to fetch information. The same
information is usually also emitted on changes via RTM_NEWLINK
notifications.
Yes, the information may be avilable somehow, but how cumbersome:
a) receive RTM_DELLINK, recognize that the message belongs to a
veth that was moved to another netns, and recognize that the peer's
IFLA_LINK changed. This approach only works when the veth is moved
away from the current namespace.
b) or, enable monitor all-nsid, receive RTM_NEWLINK, recognize that
the event is for moving a veth between netns, find the peer in the
other netns and recognize that the peer's IFLA_LINK changed.
best,
THomas
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^ permalink raw reply
* Re: [PATCH net-next v2] net: sched: change tcf_del_walker() to take idrinfo->lock
From: Cong Wang @ 2018-09-07 19:12 UTC (permalink / raw)
To: Vlad Buslov
Cc: Linux Kernel Network Developers, Jamal Hadi Salim, Jiri Pirko,
David Miller
In-Reply-To: <1536328317-8170-1-git-send-email-vladbu@mellanox.com>
On Fri, Sep 7, 2018 at 6:52 AM Vlad Buslov <vladbu@mellanox.com> wrote:
>
> Action API was changed to work with actions and action_idr in concurrency
> safe manner, however tcf_del_walker() still uses actions without taking a
> reference or idrinfo->lock first, and deletes them directly, disregarding
> possible concurrent delete.
>
> Add tc_action_wq workqueue to action API. Implement
> tcf_idr_release_unsafe() that assumes external synchronization by caller
> and delays blocking action cleanup part to tc_action_wq workqueue. Extend
> tcf_action_cleanup() with 'async' argument to indicate that function should
> free action asynchronously.
Where exactly is blocking in tcf_action_cleanup()?
>From your code, it looks like free_tcf(), but from my observation,
the only blocking function inside is tcf_action_goto_chain_fini()
which calls __tcf_chain_put(). But, __tcf_chain_put() is blocking
_ONLY_ when tc_chain_notify() is called, for tc action it is never
called.
So, what else is blocking?
^ permalink raw reply
* [PATCH 2/5] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64 in linux/setbits.h
From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, alexandre.torgue, alistair,
benh, carlo, davem, galak, joabreu, khilman, maxime.ripard,
michal.lkml, mpe, mporter, nicolas.palix, oss, paulus,
peppe.cavallaro, tj, vitb, wens
Cc: cocci, linux-amlogic, linux-arm-kernel, linux-ide, linux-kernel,
linuxppc-dev, netdev, linux-sunxi, Corentin Labbe
In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com>
This patch adds setbits32/clrbits32/clrsetbits32 and
setbits64/clrbits64/clrsetbits64 in linux/setbits.h header.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
include/linux/setbits.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 include/linux/setbits.h
diff --git a/include/linux/setbits.h b/include/linux/setbits.h
new file mode 100644
index 000000000000..3e1e273551bb
--- /dev/null
+++ b/include/linux/setbits.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_SETBITS_H
+#define __LINUX_SETBITS_H
+
+#include <linux/io.h>
+
+#define __setbits(readfunction, writefunction, addr, set) \
+ writefunction((readfunction(addr) | (set)), addr)
+#define __clrbits(readfunction, writefunction, addr, mask) \
+ writefunction((readfunction(addr) & ~(mask)), addr)
+#define __clrsetbits(readfunction, writefunction, addr, mask, set) \
+ writefunction(((readfunction(addr) & ~(mask)) | (set)), addr)
+#define __setclrbits(readfunction, writefunction, addr, mask, set) \
+ writefunction(((readfunction(addr) | (seti)) & ~(mask)), addr)
+
+#define setbits32(addr, set) __setbits(readl, writel, addr, set)
+#define setbits32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \
+ addr, set)
+
+#define clrbits32(addr, mask) __clrbits(readl, writel, addr, mask)
+#define clrbits32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \
+ addr, mask)
+
+#define clrsetbits32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set)
+#define clrsetbits32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \
+ writel_relaxed, \
+ addr, mask, set)
+
+#define setclrbits32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set)
+#define setclrbits32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \
+ writel_relaxed, \
+ addr, mask, set)
+
+/* We cannot use CONFIG_64BIT as some x86 drivers use writeq */
+#if defined(writeq) && defined(readq)
+#define setbits64(addr, set) __setbits(readq, writeq, addr, set)
+#define setbits64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \
+ addr, set)
+
+#define clrbits64(addr, mask) __clrbits(readq, writeq, addr, mask)
+#define clrbits64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \
+ addr, mask)
+
+#define clrsetbits64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set)
+#define clrsetbits64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \
+ writeq_relaxed, \
+ addr, mask, set)
+
+#define setclrbits64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set)
+#define setclrbits64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \
+ writeq_relaxed, \
+ addr, mask, set)
+#endif /* writeq/readq */
+
+#endif /* __LINUX_SETBITS_H */
--
2.16.4
^ permalink raw reply related
* [PATCH RFC 3/5] coccinelle: add xxxsetbitsXX converting spatch
From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, alexandre.torgue, alistair,
benh, carlo, davem, galak, joabreu, khilman, maxime.ripard,
michal.lkml, mpe, mporter, nicolas.palix, oss, paulus,
peppe.cavallaro, tj, vitb, wens
Cc: cocci, linux-amlogic, linux-arm-kernel, linux-ide, linux-kernel,
linuxppc-dev, netdev, linux-sunxi, Corentin Labbe
In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com>
This patch add a spatch which convert all open coded of setbits32/clrbits32/clrsetbits32
and their 64 bits counterparts.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
scripts/coccinelle/misc/setbits.cocci | 423 ++++++++++++++++++++++++++++++++++
1 file changed, 423 insertions(+)
create mode 100644 scripts/coccinelle/misc/setbits.cocci
diff --git a/scripts/coccinelle/misc/setbits.cocci b/scripts/coccinelle/misc/setbits.cocci
new file mode 100644
index 000000000000..c01ab6d75eb4
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits.cocci
@@ -0,0 +1,423 @@
+virtual context
+
+@pclrsetbits32a@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, reg);
++ clrsetbits32(reg, clear, set);
+
+@pclrsetbits32b@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- rr |= set;
+- rr &= ~clear;
+- writel(rr, reg);
++ clrsetbits32(reg, clear, set);
+
+@pclrbits32@
+identifier rr;
+expression reg;
+expression clear;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- rr &= ~clear;
+- writel(rr, reg);
++ clrbits32(reg, clear);
+
+@psetbits32@
+identifier rr;
+expression reg;
+expression set;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- rr |= set;
+- writel(rr, reg);
++ setbits32(reg, set);
+
+@psetbits32b@
+identifier rr;
+expression reg;
+expression set1;
+expression set2;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- rr |= set1;
+- rr |= set2;
+- writel(rr, reg);
++ setbits32(reg, set1 | set2);
+
+@pclrsetbits64a@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+- rr &= ~clear;
+- rr |= set;
+- writeq(rr, reg);
++ clrsetbits64(reg, clear, set);
+
+@pclrsetbits64b@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+- rr |= set;
+- rr &= ~clear;
+- writeq(rr, reg);
++ clrsetbits64(reg, clear, set);
+
+@pclrbits64@
+identifier rr;
+expression reg;
+expression clear;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+- rr &= ~clear;
+- writeq(rr, reg);
++ clrbits64(reg, clear);
+
+@psetbits64@
+identifier rr;
+expression reg;
+expression set;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+- rr |= set;
+- writeq(rr, reg);
++ setbits64(reg, set);
+
+@@
+expression dwmac;
+expression reg;
+expression mask;
+expression value;
+@@
+
+- meson8b_dwmac_mask_bits(dwmac, reg, mask, value);
++ clrsetbits32(dwmac->regs + reg, mask, value);
+
+@ppclrsetbits32a@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+- u32 rr = readl(reg);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, reg);
++ clrsetbits32(reg, clear, set);
+
+@ppclrsetbits32b@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+- u32 rr = readl(reg);
+- rr |= set;
+- rr &= ~clear;
+- writel(rr, reg);
++ clrsetbits32(reg, clear, set);
+
+@ppclrbits32@
+identifier rr;
+expression reg;
+expression clear;
+@@
+
+- u32 rr = readl(reg);
+- rr &= ~clear;
+- writel(rr, reg);
++ clrbits32(reg, clear);
+
+@ppsetbits32@
+identifier rr;
+expression reg;
+expression set;
+@@
+
+- u32 rr = readl(reg);
+- rr |= set;
+- writel(rr, reg);
++ setbits32(reg, set);
+
+@ppclrsetbits64a@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+- u64 rr = readq(reg);
+- rr &= ~clear;
+- rr |= set;
+- writeq(rr, reg);
++ clrsetbits64(reg, clear, set);
+
+@ppclrsetbits64b@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+- u64 rr = readq(reg);
+- rr |= set;
+- rr &= ~clear;
+- writeq(rr, reg);
++ clrsetbits64(reg, clear, set);
+
+@ppclrbits64@
+identifier rr;
+expression reg;
+expression clear;
+@@
+
+- u64 rr = readq(reg);
+- rr &= ~clear;
+- writeq(rr, reg);
++ clrbits64(reg, clear);
+
+@ppsetbits64@
+identifier rr;
+expression reg;
+expression set;
+@@
+
+- u64 rr = readq(reg);
+- rr |= set;
+- writeq(rr, reg);
++ setbits64(reg, set);
+
+@pif_set_clr@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+ if (...)
+- rr |= set;
++ setbits32(reg, set);
+ else
+- rr &= ~clear;
++ clrbits32(reg, clear);
+- writel(rr, reg);
+
+@pifclrset@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+ if (...)
+- rr &= ~clear;
++ clrbits32(reg, clear);
+ else
+- rr |= set;
++ setbits32(reg, set);
+- writel(rr, reg);
+
+@pif_set_clr64@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+ if (...)
+- rr |= set;
++ setbits64(reg, set);
+ else
+- rr &= ~clear;
++ clrbits64(reg, clear);
+- writeq(rr, reg);
+
+@pif_clr_set64@
+identifier rr;
+expression reg;
+expression set;
+expression clear;
+@@
+
+ u64 rr;
+ ...
+- rr = readq(reg);
+ if (...)
+- rr &= ~clear;
++ clrbits64(reg, clear);
+ else
+- rr |= set;
++ setbits32(reg, set);
+- writeq(rr, reg);
+
+
+@p_setbits32_m2@
+identifier rr;
+expression reg;
+expression set;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- writel(rr | set, reg);
++ setbits32(reg, set);
+
+@p_clrbits32_m2@
+identifier rr;
+expression reg;
+expression mask;
+@@
+
+ u32 rr;
+ ...
+- rr = readl(reg);
+- writel(rr & ~mask, reg);
++ clrbits32(reg, mask);
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writel(readl(addr) | set, addr);
++ setbits32(addr, set);
+
+@p_clrbits_oneliner@
+expression addr;
+expression mask;
+@@
+- writel(readl(addr) & ~mask, addr);
++ clrbits32(addr, mask);
+
+@p_clrsetbits_oneliner_a@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel(readl(addr) | set & ~mask, addr);
++ clrsetbits32(addr, mask, set);
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel(readl(addr) & ~mask | set, addr);
++ clrsetbits32(addr, mask, set);
+
+@p_clrsetbits_oneliner_a2@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel((readl(addr) | set) & ~mask, addr);
++ clrsetbits32(addr, mask, set);
+
+@p_clrsetbits_oneliner_b2@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel((readl(addr) & ~mask) | set, addr);
++ clrsetbits32(addr, mask, set);
+
+
+
+
+
+
+
+
+
+
+
+// sub optimal way to add header
+@header1 depends on psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b@
+@@
+ #include <linux/io.h>
++ #include <linux/setbits.h>
+
+@header2 depends on (psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b) && !header1@
+@@
+ #include <linux/interrupt.h>
++ #include <linux/setbits.h>
+
+@header3 depends on (psetbits32 || pclrbits32 || pclrsetbits32a || pclrsetbits32b || psetbits64 || pclrbits64 || pclrsetbits64a || pclrsetbits64b || ppsetbits32 || ppclrbits32 || ppclrsetbits32a || ppclrsetbits32b || ppsetbits64 || ppclrbits64 || ppclrsetbits64a || ppclrsetbits64b) && !header2@
+@@
+ #include <linux/of.h>
++ #include <linux/setbits.h>
+
+@@
+expression base;
+expression offset;
+expression value;
+@@
+
+- mtu3_setbits(base, offset, value);
++ setbits32(base + offset, value);
+
+@@
+expression base;
+expression offset;
+expression mask;
+@@
+
+- mtu3_clrbits(base, offset, mask);
++ clrbits32(base + offset, mask);
+
--
2.16.4
^ permalink raw reply related
* [PATCH 1/5] powerpc: rename setbits32/clrbits32 to setbits32_be/clrbits32_be
From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, alexandre.torgue, alistair,
benh, carlo, davem, galak, joabreu, khilman, maxime.ripard,
michal.lkml, mpe, mporter, nicolas.palix, oss, paulus,
peppe.cavallaro, tj, vitb, wens
Cc: cocci, linux-amlogic, linux-arm-kernel, linux-ide, linux-kernel,
linuxppc-dev, netdev, linux-sunxi, Corentin Labbe
In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com>
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h | 5 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 ++++-----
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 10 ++--
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 ++--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 ++--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 4 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 4 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 4 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 ++++-----
arch/powerpc/platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +--
arch/powerpc/platforms/embedded6xx/wii.c | 10 ++--
arch/powerpc/sysdev/cpm1.c | 26 ++++-----
arch/powerpc/sysdev/cpm2.c | 16 ++---
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 8 +--
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 8 +--
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74 ++++++++++++------------
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 8 +--
arch/powerpc/sysdev/mpic_timer.c | 12 ++--
41 files changed, 178 insertions(+), 177 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..55d7aa0c27cf 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits32_be(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index e0331e754568..29ecefd41ecb 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -873,8 +873,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits32_be(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
@@ -904,6 +904,7 @@ static inline void * bus_to_virt(unsigned long address)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+#define clrsetbits32_be(addr, clear, set) clrsetbits(be32, addr, clear, set)
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..7145a730769d 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x42000000);
- setbits32((vaddr + GPIO0_TSRH), 0x42000000);
+ setbits32_be((vaddr + GPIO0_OSRH), 0x42000000);
+ setbits32_be((vaddr + GPIO0_TSRH), 0x42000000);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --git a/arch/powerpc/platforms/4xx/gpio.c b/arch/powerpc/platforms/4xx/gpio.c
index 2238e369cde4..e84f2d20674e 100644
--- a/arch/powerpc/platforms/4xx/gpio.c
+++ b/arch/powerpc/platforms/4xx/gpio.c
@@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
if (val)
- setbits32(®s->or, GPIO_MASK(gpio));
+ setbits32_be(®s->or, GPIO_MASK(gpio));
else
- clrbits32(®s->or, GPIO_MASK(gpio));
+ clrbits32_be(®s->or, GPIO_MASK(gpio));
}
static void
@@ -112,18 +112,18 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&chip->lock, flags);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits32_be(®s->odr, GPIO_MASK(gpio));
/* Float the pin */
- clrbits32(®s->tcr, GPIO_MASK(gpio));
+ clrbits32_be(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits32_be(®s->osrl, GPIO_MASK2(gpio));
+ clrbits32_be(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits32_be(®s->osrh, GPIO_MASK2(gpio));
+ clrbits32_be(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
@@ -145,18 +145,18 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
__ppc4xx_gpio_set(gc, gpio, val);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits32_be(®s->odr, GPIO_MASK(gpio));
/* Drive the pin */
- setbits32(®s->tcr, GPIO_MASK(gpio));
+ setbits32_be(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL, bits 16-31 use TSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits32_be(®s->osrl, GPIO_MASK2(gpio));
+ clrbits32_be(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits32_be(®s->osrh, GPIO_MASK2(gpio));
+ clrbits32_be(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
index dc81f05e0bce..283925e49096 100644
--- a/arch/powerpc/platforms/512x/pdm360ng.c
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -38,7 +38,7 @@ static int pdm360ng_get_pendown_state(void)
reg = in_be32(pdm360ng_gpio_base + 0xc);
if (reg & 0x40)
- setbits32(pdm360ng_gpio_base + 0xc, 0x40);
+ setbits32_be(pdm360ng_gpio_base + 0xc, 0x40);
reg = in_be32(pdm360ng_gpio_base + 0x8);
@@ -69,8 +69,8 @@ static int __init pdm360ng_penirq_init(void)
return -ENODEV;
}
out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff);
- setbits32(pdm360ng_gpio_base + 0x18, 0x2000);
- setbits32(pdm360ng_gpio_base + 0x10, 0x40);
+ setbits32_be(pdm360ng_gpio_base + 0x18, 0x2000);
+ setbits32_be(pdm360ng_gpio_base + 0x10, 0x40);
return 0;
}
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 565e3a83dc9e..8a8b3d79798d 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -314,13 +314,13 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
/* enable gpio pins for output */
setbits8(&wkup_gpio->wkup_gpioe, reset);
- setbits32(&simple_gpio->simple_gpioe, sync | out);
+ setbits32_be(&simple_gpio->simple_gpioe, sync | out);
setbits8(&wkup_gpio->wkup_ddr, reset);
- setbits32(&simple_gpio->simple_ddr, sync | out);
+ setbits32_be(&simple_gpio->simple_ddr, sync | out);
/* Assert cold reset */
- clrbits32(&simple_gpio->simple_dvo, sync | out);
+ clrbits32_be(&simple_gpio->simple_dvo, sync | out);
clrbits8(&wkup_gpio->wkup_dvo, reset);
/* wait for 1 us */
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 17cf249b18ee..88eef86f802c 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -142,7 +142,7 @@ static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ setbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -152,7 +152,7 @@ static void mpc52xx_gpt_irq_mask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -308,7 +308,7 @@ static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
+ clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
@@ -482,7 +482,7 @@ int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
return -EBUSY;
}
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
+ clrbits32_be(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
}
@@ -639,7 +639,7 @@ static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
unsigned long flags;
raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
- clrbits32(&gpt_wdt->regs->mode,
+ clrbits32_be(&gpt_wdt->regs->mode,
MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 8fec050f2d5b..da4fee98085f 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -262,7 +262,7 @@ static void __init ep8248e_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
ep8248e_bcsr_node =
of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index 28860e40b5db..b5b34f8b1a9b 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -157,9 +157,9 @@ static void __init init_ioports(void)
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
/* Force USB FULL SPEED bit to '1' */
- setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
+ setbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
/* clear USB_SLAVE */
- clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
+ clrbits32_be(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
}
static void __init km82xx_setup_arch(void)
@@ -172,7 +172,7 @@ static void __init km82xx_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
init_ioports();
diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c
index d23c10a96bde..a9c8cd13a4b5 100644
--- a/arch/powerpc/platforms/82xx/mpc8272_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c
@@ -164,13 +164,13 @@ static void __init mpc8272_ads_setup_arch(void)
#define BCSR3_FETHIEN2 0x10000000
#define BCSR3_FETH2_RST 0x08000000
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits32_be(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits32_be(&bcsr[3], BCSR3_FETHIEN2);
+ setbits32_be(&bcsr[3], BCSR3_FETH2_RST);
- clrbits32(&bcsr[3], BCSR3_USB_nEN);
+ clrbits32_be(&bcsr[3], BCSR3_USB_nEN);
iounmap(bcsr);
diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c
index c4f7029fc9ae..43a9a948f064 100644
--- a/arch/powerpc/platforms/82xx/pq2.c
+++ b/arch/powerpc/platforms/82xx/pq2.c
@@ -25,7 +25,7 @@
void __noreturn pq2_restart(char *cmd)
{
local_irq_disable();
- setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
+ setbits32_be(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 8b065bdf7412..b691de4c580a 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -47,7 +47,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- setbits32(&priv->regs->mask, 1 << irq);
+ setbits32_be(&priv->regs->mask, 1 << irq);
mb();
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
@@ -63,7 +63,7 @@ static void pq2ads_pci_unmask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- clrbits32(&priv->regs->mask, 1 << irq);
+ clrbits32_be(&priv->regs->mask, 1 << irq);
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
}
}
diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c
index 6c654dc74a4b..05e9c743712f 100644
--- a/arch/powerpc/platforms/82xx/pq2fads.c
+++ b/arch/powerpc/platforms/82xx/pq2fads.c
@@ -140,18 +140,18 @@ static void __init pq2fads_setup_arch(void)
/* Enable the serial and ethernet ports */
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits32_be(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits32_be(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits32_be(&bcsr[3], BCSR3_FETHIEN2);
+ setbits32_be(&bcsr[3], BCSR3_FETH2_RST);
iounmap(bcsr);
init_ioports();
/* Enable external IRQs */
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
+ clrbits32_be(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
pq2_init_pci();
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index d8642a4afc74..d13f11aac111 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -101,19 +101,19 @@ static void quirk_mpc8360e_qe_enet10(void)
* UCC1: write 0b11 to bits 18:19
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x00003000);
+ setbits32_be((base + 0xa8), 0x00003000);
/*
* UCC2 option 1: write 0b11 to bits 4:5
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x0c000000);
+ setbits32_be((base + 0xa8), 0x0c000000);
/*
* UCC2 option 2: write 0b11 to bits 16:17
* at address IMMRBAR+0x14AC
*/
- setbits32((base + 0xac), 0x0000c000);
+ setbits32_be((base + 0xac), 0x0000c000);
}
iounmap(base);
of_node_put(np_par);
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index fd44dd03e1f3..56e638fdbbc5 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -118,7 +118,7 @@ static void __init mpc836x_mds_setup_arch(void)
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
- setbits32(immap, 0x0c003000);
+ setbits32_be(immap, 0x0c003000);
/*
* IMMR + 0x14AC[20:27] = 10101010
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e6dba3..06c18149dc5a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -262,7 +262,7 @@ static void __init mpc85xx_mds_qe_init(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
index f05325f0cc03..b1bb81a49a7f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
@@ -60,9 +60,9 @@ static void mpc85xx_freeze_time_base(bool freeze)
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
if (freeze)
- setbits32(&guts->devdisr, mask);
+ setbits32_be(&guts->devdisr, mask);
else
- clrbits32(&guts->devdisr, mask);
+ clrbits32_be(&guts->devdisr, mask);
in_be32(&guts->devdisr);
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 10069503e39f..13ae0b12dd5a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -115,7 +115,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
* and QE12 for QE MII management singals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 9fb57f78cdbe..adb7abdd291f 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -405,11 +405,11 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
+ clrbits32_be(&guts->clkdvdr,
CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 276e00ab3dde..97698230f031 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -75,11 +75,11 @@ void p1022rdk_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
+ clrbits32_be(&guts->clkdvdr,
CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
index dac36ba82fea..c11f95711a8a 100644
--- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -114,11 +114,11 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
+ clrbits32_be(scfg + CCSR_SCFG_PIXCLKCR,
PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
+ setbits32_be(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
iounmap(scfg);
}
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f6253e9ff..b678ee2665d0 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -95,7 +95,7 @@ static void __init twr_p1025_setup_arch(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
* Set QE mux bits in PMUXCR */
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits32_be(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index a5d73fabe4d1..78472179b05a 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -261,11 +261,11 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 31);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
+ clrbits32_be(&guts->clkdvdr,
CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits32_be(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/8xx/adder875.c b/arch/powerpc/platforms/8xx/adder875.c
index bcef9f66191e..d21d0b8fd2a7 100644
--- a/arch/powerpc/platforms/8xx/adder875.c
+++ b/arch/powerpc/platforms/8xx/adder875.c
@@ -77,7 +77,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init adder875_setup(void)
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index 027c42d8966c..2ed24abd0b40 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -103,7 +103,7 @@ void __init mpc8xx_calibrate_decr(void)
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
- setbits32(&clk_r2->car_sccr, 0x02000000);
+ setbits32_be(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
@@ -203,7 +203,7 @@ void __noreturn mpc8xx_restart(char *cmd)
local_irq_disable();
- setbits32(&clk_r->car_plprcr, 0x00000080);
+ setbits32_be(&clk_r->car_plprcr, 0x00000080);
/* Clear the ME bit in MSR to cause checkstop on machine check
*/
mtmsr(mfmsr() & ~0x1000);
diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
index 8d02f5ff4481..a25e5ab15d65 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
@@ -87,7 +87,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc86xads_setup_arch(void)
@@ -112,7 +112,7 @@ static void __init mpc86xads_setup_arch(void)
return;
}
- clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
+ clrbits32_be(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
iounmap(bcsr_io);
}
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index a0c83c1905c6..8aad0fb9090b 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -123,7 +123,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits32_be(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc885ads_setup_arch(void)
@@ -148,33 +148,33 @@ static void __init mpc885ads_setup_arch(void)
return;
}
- clrbits32(&bcsr[1], BCSR1_RS232EN_1);
+ clrbits32_be(&bcsr[1], BCSR1_RS232EN_1);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- setbits32(&bcsr[1], BCSR1_RS232EN_2);
+ setbits32_be(&bcsr[1], BCSR1_RS232EN_2);
#else
- clrbits32(&bcsr[1], BCSR1_RS232EN_2);
+ clrbits32_be(&bcsr[1], BCSR1_RS232EN_2);
#endif
- clrbits32(bcsr5, BCSR5_MII1_EN);
- setbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits32_be(bcsr5, BCSR5_MII1_EN);
+ setbits32_be(bcsr5, BCSR5_MII1_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits32_be(bcsr5, BCSR5_MII1_RST);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- clrbits32(bcsr5, BCSR5_MII2_EN);
- setbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits32_be(bcsr5, BCSR5_MII2_EN);
+ setbits32_be(bcsr5, BCSR5_MII2_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits32_be(bcsr5, BCSR5_MII2_RST);
#else
- setbits32(bcsr5, BCSR5_MII2_EN);
+ setbits32_be(bcsr5, BCSR5_MII2_EN);
#endif
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
- clrbits32(&bcsr[4], BCSR4_ETH10_RST);
+ clrbits32_be(&bcsr[4], BCSR4_ETH10_RST);
udelay(1000);
- setbits32(&bcsr[4], BCSR4_ETH10_RST);
+ setbits32_be(&bcsr[4], BCSR4_ETH10_RST);
- setbits32(&bcsr[1], BCSR1_ETHEN);
+ setbits32_be(&bcsr[1], BCSR1_ETHEN);
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
#else
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
index db0be007fd06..6df4533aa851 100644
--- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -53,7 +53,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + FLIPPER_IMR, mask);
+ clrbits32_be(io_base + FLIPPER_IMR, mask);
/* this is at least needed for RSW */
out_be32(io_base + FLIPPER_ICR, mask);
}
@@ -72,7 +72,7 @@ static void flipper_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + FLIPPER_IMR, 1 << irq);
+ clrbits32_be(io_base + FLIPPER_IMR, 1 << irq);
}
static void flipper_pic_unmask(struct irq_data *d)
@@ -80,7 +80,7 @@ static void flipper_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + FLIPPER_IMR, 1 << irq);
+ setbits32_be(io_base + FLIPPER_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 8112b39879d6..5487710bed1c 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -50,7 +50,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + HW_BROADWAY_IMR, mask);
+ clrbits32_be(io_base + HW_BROADWAY_IMR, mask);
out_be32(io_base + HW_BROADWAY_ICR, mask);
}
@@ -67,7 +67,7 @@ static void hlwd_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ clrbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq);
}
static void hlwd_pic_unmask(struct irq_data *d)
@@ -75,10 +75,10 @@ static void hlwd_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ setbits32_be(io_base + HW_BROADWAY_IMR, 1 << irq);
/* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */
- clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
+ clrbits32_be(io_base + HW_STARLET_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c
index 403523c061ba..dd511e19147a 100644
--- a/arch/powerpc/platforms/embedded6xx/wii.c
+++ b/arch/powerpc/platforms/embedded6xx/wii.c
@@ -134,7 +134,7 @@ static void __init wii_setup_arch(void)
hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE);
if (hw_gpio) {
/* turn off the front blue led and IR light */
- clrbits32(hw_gpio + HW_GPIO_OUT(0),
+ clrbits32_be(hw_gpio + HW_GPIO_OUT(0),
HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
}
}
@@ -145,7 +145,7 @@ static void __noreturn wii_restart(char *cmd)
if (hw_ctrl) {
/* clear the system reset pin to cause a reset */
- clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
+ clrbits32_be(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
}
wii_spin();
}
@@ -159,13 +159,13 @@ static void wii_power_off(void)
* set the owner of the shutdown pin to ARM, because it is
* accessed through the registers for the ARM, below
*/
- clrbits32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
+ clrbits32_be(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
/* make sure that the poweroff GPIO is configured as output */
- setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
+ setbits32_be(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
/* drive the poweroff GPIO high */
- setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
+ setbits32_be(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
}
wii_spin();
}
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 4f8dcf124828..9de5f13c51cb 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -60,14 +60,14 @@ static void cpm_mask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ clrbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_unmask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ setbits32_be(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_end_irq(struct irq_data *d)
@@ -188,7 +188,7 @@ unsigned int cpm_pic_init(void)
if (setup_irq(eirq, &cpm_error_irqaction))
printk(KERN_ERR "Could not allocate CPM error IRQ!");
- setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
+ setbits32_be(&cpic_reg->cpic_cicr, CICR_IEN);
end:
of_node_put(np);
@@ -317,14 +317,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
&mpc8xx_immr->im_cpm.cp_pedir;
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop->dir, pin);
+ setbits32_be(&iop->dir, pin);
else
- clrbits32(&iop->dir, pin);
+ clrbits32_be(&iop->dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop->par, pin);
+ setbits32_be(&iop->par, pin);
else
- clrbits32(&iop->par, pin);
+ clrbits32_be(&iop->par, pin);
if (port == CPM_PORTB) {
if (flags & CPM_PIN_OPENDRAIN)
@@ -335,14 +335,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
if (port == CPM_PORTE) {
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop->sor, pin);
+ setbits32_be(&iop->sor, pin);
else
- clrbits32(&iop->sor, pin);
+ clrbits32_be(&iop->sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ setbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin);
else
- clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ clrbits32_be(&mpc8xx_immr->im_cpm.cp_peodr, pin);
}
}
@@ -732,7 +732,7 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits32_be(&iop->dir, pin_mask);
__cpm1_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
@@ -750,7 +750,7 @@ static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits32_be(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 07718b9a2c99..445d6e45a6de 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -335,22 +335,22 @@ void cpm2_set_pin(int port, int pin, int flags)
pin = 1 << (31 - pin);
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop[port].dir, pin);
+ setbits32_be(&iop[port].dir, pin);
else
- clrbits32(&iop[port].dir, pin);
+ clrbits32_be(&iop[port].dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop[port].par, pin);
+ setbits32_be(&iop[port].par, pin);
else
- clrbits32(&iop[port].par, pin);
+ clrbits32_be(&iop[port].par, pin);
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop[port].sor, pin);
+ setbits32_be(&iop[port].sor, pin);
else
- clrbits32(&iop[port].sor, pin);
+ clrbits32_be(&iop[port].sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&iop[port].odr, pin);
+ setbits32_be(&iop[port].odr, pin);
else
- clrbits32(&iop[port].odr, pin);
+ clrbits32_be(&iop[port].odr, pin);
}
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index b74508175b67..d36a95708aaf 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -165,7 +165,7 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits32_be(&iop->dir, pin_mask);
__cpm2_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
@@ -183,7 +183,7 @@ static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits32_be(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index c27058e5df26..2b7e2b4a2543 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -124,23 +124,23 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
switch (ways) {
case LOCK_WAYS_EIGHTH:
- setbits32(&l2ctlr->ctl,
+ setbits32_be(&l2ctlr->ctl,
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
break;
case LOCK_WAYS_TWO_EIGHTH:
- setbits32(&l2ctlr->ctl,
+ setbits32_be(&l2ctlr->ctl,
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
break;
case LOCK_WAYS_HALF:
- setbits32(&l2ctlr->ctl,
+ setbits32_be(&l2ctlr->ctl,
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
break;
case LOCK_WAYS_FULL:
default:
- setbits32(&l2ctlr->ctl,
+ setbits32_be(&l2ctlr->ctl,
L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
break;
}
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 5340a483cf55..994233e41b91 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -192,7 +192,7 @@ static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* clear event registers */
- setbits32(&lbc->ltesr, LTESR_CLEAR);
+ setbits32_be(&lbc->ltesr, LTESR_CLEAR);
out_be32(&lbc->lteatr, 0);
out_be32(&lbc->ltear, 0);
out_be32(&lbc->lteccr, LTECCR_CLEAR);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 918be816b097..17aa5ee63d34 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1196,11 +1196,11 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
pci = hose->private_data;
/* Enable PTOD, ENL23D & EXL23D */
- clrbits32(&pci->pex_pme_mes_disr,
+ clrbits32_be(&pci->pex_pme_mes_disr,
PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
out_be32(&pci->pex_pme_mes_ier, 0);
- setbits32(&pci->pex_pme_mes_ier,
+ setbits32_be(&pci->pex_pme_mes_ier,
PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
/* PME Enable */
@@ -1218,7 +1218,7 @@ static void send_pme_turnoff_message(struct pci_controller *hose)
int i;
/* Send PME_Turn_Off Message Request */
- setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
+ setbits32_be(&pci->pex_pmcr, PEX_PMCR_PTOMR);
/* Wait trun off done */
for (i = 0; i < 150; i++) {
@@ -1254,7 +1254,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
int i;
/* Send Exit L2 State Message */
- setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
+ setbits32_be(&pci->pex_pmcr, PEX_PMCR_EXL2S);
/* Wait exit done */
for (i = 0; i < 150; i++) {
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 232225e7f863..bbcf4cb89bb6 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -37,7 +37,7 @@ static int pmc_suspend_enter(suspend_state_t state)
{
int ret;
- setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+ setbits32_be(&pmc_regs->pmcsr, PMCSR_SLP);
/* At this point, the CPU is asleep. */
/* Upon resume, wait for SLP bit to be clear. */
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
index 9259a94f70e1..bd2a7606bfce 100644
--- a/arch/powerpc/sysdev/fsl_rcpm.c
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -33,10 +33,10 @@ static void rcpm_v1_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v1_regs->cpmimr, mask);
- setbits32(&rcpm_v1_regs->cpmcimr, mask);
- setbits32(&rcpm_v1_regs->cpmmcmr, mask);
- setbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ setbits32_be(&rcpm_v1_regs->cpmimr, mask);
+ setbits32_be(&rcpm_v1_regs->cpmcimr, mask);
+ setbits32_be(&rcpm_v1_regs->cpmmcmr, mask);
+ setbits32_be(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_mask(int cpu)
@@ -44,10 +44,10 @@ static void rcpm_v2_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v2_regs->tpmimr0, mask);
- setbits32(&rcpm_v2_regs->tpmcimr0, mask);
- setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ setbits32_be(&rcpm_v2_regs->tpmimr0, mask);
+ setbits32_be(&rcpm_v2_regs->tpmcimr0, mask);
+ setbits32_be(&rcpm_v2_regs->tpmmcmr0, mask);
+ setbits32_be(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_irq_unmask(int cpu)
@@ -55,10 +55,10 @@ static void rcpm_v1_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v1_regs->cpmimr, mask);
- clrbits32(&rcpm_v1_regs->cpmcimr, mask);
- clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
- clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ clrbits32_be(&rcpm_v1_regs->cpmimr, mask);
+ clrbits32_be(&rcpm_v1_regs->cpmcimr, mask);
+ clrbits32_be(&rcpm_v1_regs->cpmmcmr, mask);
+ clrbits32_be(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_unmask(int cpu)
@@ -66,26 +66,26 @@ static void rcpm_v2_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v2_regs->tpmimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ clrbits32_be(&rcpm_v2_regs->tpmimr0, mask);
+ clrbits32_be(&rcpm_v2_regs->tpmcimr0, mask);
+ clrbits32_be(&rcpm_v2_regs->tpmmcmr0, mask);
+ clrbits32_be(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ setbits32_be(&rcpm_v1_regs->ippdexpcr, mask);
else
- clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ clrbits32_be(&rcpm_v1_regs->ippdexpcr, mask);
}
static void rcpm_v2_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ setbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask);
else
- clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ clrbits32_be(&rcpm_v2_regs->ippdexpcr[0], mask);
}
static void rcpm_v1_cpu_enter_state(int cpu, int state)
@@ -95,10 +95,10 @@ static void rcpm_v1_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v1_regs->cdozcr, mask);
+ setbits32_be(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v1_regs->cnapcr, mask);
+ setbits32_be(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -114,16 +114,16 @@ static void rcpm_v2_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
/* one bit corresponds to one thread for PH10 of 6500 */
- setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
+ setbits32_be(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15setr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph15setr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20setr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph20setr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30setr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph30setr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -172,10 +172,10 @@ static void rcpm_v1_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- clrbits32(&rcpm_v1_regs->cdozcr, mask);
+ clrbits32_be(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- clrbits32(&rcpm_v1_regs->cnapcr, mask);
+ clrbits32_be(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -196,16 +196,16 @@ static void rcpm_v2_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
+ setbits32_be(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15clrr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph15clrr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20clrr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph20clrr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30clrr, mask);
+ setbits32_be(&rcpm_v2_regs->pcph30clrr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -226,7 +226,7 @@ static int rcpm_v1_plat_enter_state(int state)
switch (state) {
case PLAT_PM_SLEEP:
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
+ setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_SLP);
/* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
result = spin_event_timeout(
@@ -253,9 +253,9 @@ static int rcpm_v2_plat_enter_state(int state)
switch (state) {
case PLAT_PM_LPM20:
/* clear previous LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
+ setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
/* enter LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
+ setbits32_be(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
/* At this point, the device is in LPM20 status. */
@@ -291,9 +291,9 @@ static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
if (freeze) {
mask = in_be32(tben_reg);
- clrbits32(tben_reg, mask);
+ clrbits32_be(tben_reg, mask);
} else {
- setbits32(tben_reg, mask);
+ setbits32_be(tben_reg, mask);
}
/* read back to push the previous write */
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 5011ffea4e4b..278e63cc8afe 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -668,10 +668,10 @@ int fsl_rio_setup(struct platform_device *dev)
out_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0);
/* Set 1x lane */
- setbits32(priv->regs_win
+ setbits32_be(priv->regs_win
+ RIO_CCSR + i*0x20, 0x02000000);
/* Enable ports */
- setbits32(priv->regs_win
+ setbits32_be(priv->regs_win
+ RIO_CCSR + i*0x20, 0x00600000);
msleep(100);
if (in_be32((priv->regs_win
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 88b35a3dcdc5..134ba53f0fcb 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -355,7 +355,7 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
dmsg->sid, dmsg->tid,
dmsg->info);
}
- setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
+ setbits32_be(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
}
@@ -909,10 +909,10 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
out_be32(&rmu->msg_regs->imr, 0x001b0060);
/* Set number of queue entries */
- setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
+ setbits32_be(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
/* Now enable the unit */
- setbits32(&rmu->msg_regs->imr, 0x1);
+ setbits32_be(&rmu->msg_regs->imr, 0x1);
out:
return rc;
@@ -1015,7 +1015,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
out1:
- setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
+ setbits32_be(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
out2:
return buf;
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 87e7c42777a8..70b02ba90220 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -154,7 +154,7 @@ static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
tcr = casc_priv->tcr_value |
(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
- setbits32(priv->group_tcr, tcr);
+ setbits32_be(priv->group_tcr, tcr);
tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
@@ -253,7 +253,7 @@ void mpic_start_timer(struct mpic_timer *handle)
struct timer_group_priv *priv = container_of(handle,
struct timer_group_priv, timer[handle->num]);
- clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ clrbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP);
}
EXPORT_SYMBOL(mpic_start_timer);
@@ -269,7 +269,7 @@ void mpic_stop_timer(struct mpic_timer *handle)
struct timer_group_priv, timer[handle->num]);
struct cascade_priv *casc_priv;
- setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ setbits32_be(&priv->regs[handle->num].gtbcr, TIMER_STOP);
casc_priv = priv->timer[handle->num].cascade_handle;
if (casc_priv) {
@@ -340,7 +340,7 @@ void mpic_free_timer(struct mpic_timer *handle)
u32 tcr;
tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
MPIC_TIMER_TCR_ROVR_OFFSET);
- clrbits32(priv->group_tcr, tcr);
+ clrbits32_be(priv->group_tcr, tcr);
priv->idle |= casc_priv->cascade_map;
priv->timer[handle->num].cascade_handle = NULL;
} else {
@@ -508,7 +508,7 @@ static void timer_group_init(struct device_node *np)
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
list_add_tail(&priv->node, &timer_group_list);
@@ -531,7 +531,7 @@ static void mpic_timer_resume(void)
list_for_each_entry(priv, &timer_group_list, node) {
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits32_be(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
}
}
--
2.16.4
^ permalink raw reply related
* [PATCH 5/5] ata: ahci_sunxi: use xxxsetbits32 functions
From: Corentin Labbe @ 2018-09-07 19:41 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, alexandre.torgue, alistair,
benh, carlo, davem, galak, joabreu, khilman, maxime.ripard,
michal.lkml, mpe, mporter, nicolas.palix, oss, paulus,
peppe.cavallaro, tj, vitb, wens
Cc: cocci, linux-amlogic, linux-arm-kernel, linux-ide, linux-kernel,
linuxppc-dev, netdev, linux-sunxi, Corentin Labbe
In-Reply-To: <1536349307-20714-1-git-send-email-clabbe@baylibre.com>
This patch converts ahci_sunxi to use xxxsetbits32 functions
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/ata/ahci_sunxi.c | 51 ++++++++++++------------------------------------
1 file changed, 12 insertions(+), 39 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..0799441f1237 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include <linux/setbits.h>
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,22 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits32(reg_base + AHCI_PHYCS0R,
(0x7 << 24),
(0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
+ clrsetbits32(reg_base + AHCI_PHYCS1R,
(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
+ setbits32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits32(reg_base + AHCI_PHYCS0R,
(0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
+ clrsetbits32(reg_base + AHCI_PHYCS2R,
(0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +103,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +131,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
+ clrsetbits32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.16.4
^ permalink raw reply related
* Re: [PATCH net-next 13/13] net: sched: add flags to Qdisc class ops struct
From: Cong Wang @ 2018-09-07 19:50 UTC (permalink / raw)
To: Vlad Buslov
Cc: Linux Kernel Network Developers, Jamal Hadi Salim, Jiri Pirko,
David Miller, Stephen Hemminger, Kirill Tkhai, Paul E. McKenney,
Nicolas Dichtel, Leon Romanovsky, Greg KH, mark.rutland,
Florian Westphal, David Ahern, lucien xin, Jakub Kicinski,
Christian Brauner, Jiri Benc
In-Reply-To: <1536220742-25650-14-git-send-email-vladbu@mellanox.com>
On Thu, Sep 6, 2018 at 12:59 AM Vlad Buslov <vladbu@mellanox.com> wrote:
>
> Extend Qdisc_class_ops with flags. Create enum to hold possible class ops
> flag values. Add first class ops flags value QDISC_CLASS_OPS_DOIT_UNLOCKED
> to indicate that class ops functions can be called without taking rtnl
> lock.
We don't add anything that is not used.
This is the last patch in this series, so I am pretty sure you split
it in a wrong way, it certainly belongs to next series, not this series.
^ permalink raw reply
* Re: [PATCH net-next 09/13] net: sched: extend tcf_block with rcu
From: Cong Wang @ 2018-09-07 19:52 UTC (permalink / raw)
To: Vlad Buslov
Cc: Linux Kernel Network Developers, Jamal Hadi Salim, Jiri Pirko,
David Miller, Stephen Hemminger, Kirill Tkhai, Paul E. McKenney,
Nicolas Dichtel, Leon Romanovsky, Greg KH, mark.rutland,
Florian Westphal, David Ahern, lucien xin, Jakub Kicinski,
Christian Brauner, Jiri Benc
In-Reply-To: <1536220742-25650-10-git-send-email-vladbu@mellanox.com>
On Thu, Sep 6, 2018 at 12:59 AM Vlad Buslov <vladbu@mellanox.com> wrote:
>
> Extend tcf_block with rcu to allow safe deallocation when it is accessed
> concurrently.
This sucks, please fold this patch into where you call rcu_read_lock()
on tcf block.
This patch _alone_ is apparently not complete. This is not how
we split patches.
^ permalink raw reply
* Re: [PATCH v3 3/3] IB/ipoib: Log sysfs 'dev_id' accesses from userspace
From: Doug Ledford @ 2018-09-07 20:02 UTC (permalink / raw)
To: Leon Romanovsky; +Cc: Arseny Maslennikov, linux-rdma, Jason Gunthorpe, netdev
In-Reply-To: <20180907172821.GS3142@mtr-leonro.mtl.com>
[-- Attachment #1: Type: text/plain, Size: 4629 bytes --]
On Fri, 2018-09-07 at 20:28 +0300, Leon Romanovsky wrote:
> On Fri, Sep 07, 2018 at 01:14:37PM -0400, Doug Ledford wrote:
> > On Thu, 2018-09-06 at 16:03 +0300, Leon Romanovsky wrote:
> > > On Thu, Sep 06, 2018 at 10:04:33AM +0300, Arseny Maslennikov wrote:
> > > > On Wed, Sep 05, 2018 at 04:50:35PM +0300, Leon Romanovsky wrote:
> > > > > On Mon, Sep 03, 2018 at 07:13:16PM +0300, Arseny Maslennikov wrote:
> > > > > > Signed-off-by: Arseny Maslennikov <ar@cs.msu.ru>
> > > > > > ---
> > > > > > drivers/infiniband/ulp/ipoib/ipoib_main.c | 38 +++++++++++++++++++++++
> > > > > > 1 file changed, 38 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > > index 30f840f874b3..7386e5bde3d3 100644
> > > > > > --- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > > +++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
> > > > > > @@ -2386,6 +2386,42 @@ int ipoib_add_pkey_attr(struct net_device *dev)
> > > > > > return device_create_file(&dev->dev, &dev_attr_pkey);
> > > > > > }
> > > > > >
> > > > > > +/*
> > > > > > + * We erroneously exposed the iface's port number in the dev_id
> > > > > > + * sysfs field long after dev_port was introduced for that purpose[1],
> > > > > > + * and we need to stop everyone from relying on that.
> > > > > > + * Let's overload the shower routine for the dev_id file here
> > > > > > + * to gently bring the issue up.
> > > > > > + *
> > > > > > + * [1] https://www.spinics.net/lists/netdev/msg272123.html
> > > > > > + */
> > > > > > +static ssize_t dev_id_show(struct device *dev,
> > > > > > + struct device_attribute *attr, char *buf)
> > > > > > +{
> > > > > > + struct net_device *ndev = to_net_dev(dev);
> > > > > > + ssize_t ret = -EINVAL;
> > > > > > +
> > > > > > + if (ndev->dev_id == ndev->dev_port) {
> > > > > > + netdev_info_once(ndev,
> > > > > > + "\"%s\" wants to know my dev_id. "
> > > > > > + "Should it look at dev_port instead?\n",
> > > > > > + current->comm);
> > > > > > + netdev_info_once(ndev,
> > > > > > + "See Documentation/ABI/testing/sysfs-class-net for more info.\n");
> > > > > > + }
> > > > > > +
> > > > > > + ret = sprintf(buf, "%#x\n", ndev->dev_id);
> > > > > > +
> > > > > > + return ret;
> > > > > > +}
> > > > > > +static DEVICE_ATTR_RO(dev_id);
> > > > > > +
> > > > >
> > > > > I don't see this field among exposed by IPoIB, why should we expose it now?
> > > > >
> > > >
> > > > To deviate from standard netdev behaviour, which only prints the
> > > > field out. Doug wanted this to also print a deprecation message, and
> > > > netdev (obviously) does not do that. See below.
> > > >
> > > > > > +int ipoib_intercept_dev_id_attr(struct net_device *dev)
> > > > > > +{
> > > > > > + device_remove_file(&dev->dev, &dev_attr_dev_id);
> > > > > > + return device_create_file(&dev->dev, &dev_attr_dev_id);
> > > > >
> > > > > Why isn't enough to rely on netdev code?
> > > > >
> > > >
> > > > Netdev code relies on macros around a *static* function 'netdev_show',
> > > > which is defined in net/core/net-sysfs.c; it is not listed in any header
> > > > files, and the macros aren't as well. This all leads me to believe it
> > > > was not really meant to be used from outside net/core/net-sysfs.
> > > >
> > > > The only way we could use any netdev code here is to set up our own
> > > > handler (again), printk() a message, then call netdev_show — but we have
> > > > no access to it.
> > > >
> > > > Of course, it also may be that I'm terribly missing a clue.
> > >
> > > Thanks,
> > >
> > > IMHO, the end result of adequate Doug's request is a little bit too much.
> > > I don't think that it justifies such remove->create construction.
> > >
> > > Personal opinion.
> >
> > I agree with you that the end result is kinda bulky, *but*, we will need
> > to know if there are things using the old dev_id before we can remove
> > it. In particular, I'm concerned the IPoIB handling code of
> > NetworkManager uses it. It's worth the cost I think.
>
> I did my checks now and saw that ibdev2netdev uses the value provided
> from this dev_id, so every invocation of that script will generate the
> warning.
>
> See this line in Parav's repo
> https://github.com/Mellanox/container_scripts/blob/master/ibdev2netdev#L112
I'm pretty sure libvirt + qemu will trigger it too.
--
Doug Ledford <dledford@redhat.com>
GPG KeyID: B826A3330E572FDD
Key fingerprint = AE6B 1BDA 122B 23B4 265B 1274 B826 A333 0E57 2FDD
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH net-next 08/13] net: sched: rename tcf_block_get{_ext}() and tcf_block_put{_ext}()
From: Cong Wang @ 2018-09-07 20:09 UTC (permalink / raw)
To: Vlad Buslov
Cc: Linux Kernel Network Developers, Jamal Hadi Salim, Jiri Pirko,
David Miller, Stephen Hemminger, Kirill Tkhai, Paul E. McKenney,
Nicolas Dichtel, Leon Romanovsky, Greg KH, mark.rutland,
Florian Westphal, David Ahern, lucien xin, Jakub Kicinski,
Christian Brauner, Jiri Benc
In-Reply-To: <1536220742-25650-9-git-send-email-vladbu@mellanox.com>
On Thu, Sep 6, 2018 at 12:59 AM Vlad Buslov <vladbu@mellanox.com> wrote:
>
> Functions tcf_block_get{_ext}() and tcf_block_put{_ext}() actually
> attach/detach block to specific Qdisc besides just taking/putting
> reference. Rename them according to their purpose.
Where exactly does it attach to?
Each qdisc provides a pointer to a pointer of a block, like
&cl->block. It is where the result is saved to. It takes a parameter
of Qdisc* merely for read-only purpose.
So, renaming it to *attach() is even confusing, at least not
any better. Please find other names or leave them as they are.
^ permalink raw reply
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