* Re: [RFC PATCH v2 06/10] udp: cope with UDP GRO packet misdirection
From: Subash Abhinov Kasiviswanathan @ 2018-10-24 0:55 UTC (permalink / raw)
To: Paolo Abeni; +Cc: netdev, Willem de Bruijn, Steffen Klassert
In-Reply-To: <b5aed6412c3eee1c34a3b872d8e18c47deb9179f.camel@redhat.com>
>> Is the "likely" required here?
>
> Not required, but currently helpful IMHO, as we should hit the above
> only on unlikey and really unwonted configuration.
>
> Note that only SKB_GSO_UDP_L4 GSO packets will not match the above
> likely condition.
>
>> HW can coalesce all incoming streams of UDP and may not know the
>> socket
>> state.
>> In that case, a socket not having UDP GRO option might see a penalty
>> here.
>
> Really? Is there any HW creating SKB_GSO_UDP_L4 packets on RX? if the
> HW is doing that, without this patch, I think it's breaking existing
> applications (which may expext that the read UDP frame length
> implicitly describe the application level message length).
>
Hi
Yes, I agree that existing HW would not work without the patch.
My question was based on how UDP GRO packets from any future HW would
interact
with this code path and if they might be potentially have any side
effects
due to socket option not being set.
We do not have control over the application and the socket options being
used
on systems like Android. The packet count reduction due to UDP GRO would
help
when there are multiple firewall rules present even if we do not take
advantage of the reduced recvmsg() calls.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [RFC PATCH 0/3] M_CAN Framework rework
From: Dan Murphy @ 2018-10-24 11:39 UTC (permalink / raw)
To: Faiz Abbas, wg, mkl, davem; +Cc: linux-can, netdev, linux-kernel
In-Reply-To: <8247a28f-ae33-1ab1-b6d1-c89b839d357c@ti.com>
On 10/24/2018 02:33 AM, Faiz Abbas wrote:
> Hi Dan,
>
> On Thursday 18 October 2018 01:51 AM, Dan Murphy wrote:
>> Bump
>>
>> On 10/10/2018 09:20 AM, Dan Murphy wrote:
>>> All
>>>
>>> This patch series creates a m_can core framework that devices can register
>>> to. The m_can core manages the Bosch IP and CAN frames. Each device that
>>> is registered is responsible for managing device specific functions.
>>>
>>> This rewrite was suggested in a device driver submission for the TCAN4x5x
>>> device
>>> Reference upstream post:
>>> https://lore.kernel.org/patchwork/patch/984163/
>>>
>>> For instance the TCAN device is a SPI device that uses a specific data payload to
>>> determine writes and reads. In addition the device has a reset input as well
>>> as a wakeup pin. The register offset of the m_can registers differs and must
>>> be set by the device attached to the core.
>>>
>>> The m_can core will use iomapped writes and reads as the default mechanism for
>>> writing and reading. The device driver can provide over rides for this.
>>>
>>> This patch series is not complete as it does not handle the CAN interrupts
>>> nor can perform a CAN write. If this patch series is deemed acceptable I will
>>> finish debugging the driver and post a non RFC series.
>>>
>>> Finally I did attempt to reduce the first patch with various git format patch
>>> directives but none seemed to reduce the patch.
>>>
>>> Dan
>>>
>>> Dan Murphy (3):
>>> can: m_can: Create m_can core to leverage common code
>>> dt-bindings: can: tcan4x5x: Add DT bindings for TCAN4x5X driver
>>> can: tcan4x5x: Add tcan4x5x driver to the kernel
>>>
>>> .../devicetree/bindings/net/can/tcan4x5x.txt | 34 +
>>> drivers/net/can/m_can/Kconfig | 18 +
>>> drivers/net/can/m_can/Makefile | 4 +-
>>> drivers/net/can/m_can/m_can.c | 1683 +----------------
>>> .../net/can/m_can/{m_can.c => m_can_core.c} | 479 +++--
>>> drivers/net/can/m_can/m_can_core.h | 100 +
>>> drivers/net/can/m_can/tcan4x5x.c | 321 ++++
>>> 7 files changed, 722 insertions(+), 1917 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/net/can/tcan4x5x.txt
>>> copy drivers/net/can/m_can/{m_can.c => m_can_core.c} (83%)
>>> create mode 100644 drivers/net/can/m_can/m_can_core.h
>>> create mode 100644 drivers/net/can/m_can/tcan4x5x.c
>>>
>
> Patch 1/3 never arrived for me. Its not there on lkml either.
> https://lkml.org/lkml/2018/10/10/611
>
LKML seems to have issue with 1/3. Here they were posted.
Maybe the patch is to large but I received all 3 + the cover letter.
https://lore.kernel.org/patchwork/patch/998019/
https://lore.kernel.org/patchwork/patch/998017/
https://lore.kernel.org/patchwork/patch/998020/
> Can you resend the complete series?
>
> Thanks,
> Faiz
>
--
------------------
Dan Murphy
^ permalink raw reply
* Re: [PATCH net v2] net/ipv6: Add anycast addresses to a global hashtable
From: Eric Dumazet @ 2018-10-24 3:12 UTC (permalink / raw)
To: Jeff Barnhill, netdev; +Cc: davem, kuznet, yoshfuji
In-Reply-To: <20181024015832.16607-1-0xeffeff@gmail.com>
On 10/23/2018 06:58 PM, Jeff Barnhill wrote:
> icmp6_send() function is expensive on systems with a large number of
> interfaces. Every time it’s called, it has to verify that the source
> address does not correspond to an existing anycast address by looping
> through every device and every anycast address on the device. This can
> result in significant delays for a CPU when there are a large number of
> neighbors and ND timers are frequently timing out and calling
> neigh_invalidate().
>
> Add anycast addresses to a global hashtable to allow quick searching for
> matching anycast addresses. This is based on inet6_addr_lst in addrconf.c.
>
> Signed-off-by: Jeff Barnhill <0xeffeff@gmail.com>
> ---
> include/net/addrconf.h | 2 +
> include/net/if_inet6.h | 8 +++
> net/ipv6/af_inet6.c | 5 ++
> net/ipv6/anycast.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 4 files changed, 145 insertions(+), 2 deletions(-)
>
> diff --git a/include/net/addrconf.h b/include/net/addrconf.h
> index 6def0351bcc3..0cee3f99c41d 100644
> --- a/include/net/addrconf.h
> +++ b/include/net/addrconf.h
> @@ -312,6 +312,8 @@ bool ipv6_chk_acast_addr(struct net *net, struct net_device *dev,
> const struct in6_addr *addr);
> bool ipv6_chk_acast_addr_src(struct net *net, struct net_device *dev,
> const struct in6_addr *addr);
> +int anycast_init(void);
> +void anycast_cleanup(void);
>
> /* Device notifier */
> int register_inet6addr_notifier(struct notifier_block *nb);
> diff --git a/include/net/if_inet6.h b/include/net/if_inet6.h
> index d7578cf49c3a..55a4a1d8cebc 100644
> --- a/include/net/if_inet6.h
> +++ b/include/net/if_inet6.h
> @@ -142,6 +142,14 @@ struct ipv6_ac_socklist {
> struct ipv6_ac_socklist *acl_next;
> };
>
> +struct ipv6_ac_addrlist {
> + struct in6_addr acal_addr;
> + possible_net_t acal_pnet;
> + int acal_users;
That would be a refcount_t acal_users; so that CONFIG_REFCOUNT_FULL brings debugging for free.
> + struct hlist_node acal_lst; /* inet6_acaddr_lst */
> + struct rcu_head rcu;
> +};
> +
> struct ifacaddr6 {
> struct in6_addr aca_addr;
> struct fib6_info *aca_rt;
> diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c
> index 9a4261e50272..971a05fdd3bd 100644
> --- a/net/ipv6/af_inet6.c
> +++ b/net/ipv6/af_inet6.c
> @@ -1001,6 +1001,9 @@ static int __init inet6_init(void)
> err = ip6_flowlabel_init();
> if (err)
> goto ip6_flowlabel_fail;
> + err = anycast_init();
> + if (err)
> + goto anycast_fail;
> err = addrconf_init();
> if (err)
> goto addrconf_fail;
> @@ -1091,6 +1094,8 @@ static int __init inet6_init(void)
> ipv6_exthdrs_fail:
> addrconf_cleanup();
> addrconf_fail:
> + anycast_cleanup();
> +anycast_fail:
> ip6_flowlabel_cleanup();
> ip6_flowlabel_fail:
> ndisc_late_cleanup();
> diff --git a/net/ipv6/anycast.c b/net/ipv6/anycast.c
> index 4e0ff7031edd..def1e156d857 100644
> --- a/net/ipv6/anycast.c
> +++ b/net/ipv6/anycast.c
> @@ -44,8 +44,22 @@
>
> #include <net/checksum.h>
>
> +#define IN6_ADDR_HSIZE_SHIFT 8
> +#define IN6_ADDR_HSIZE BIT(IN6_ADDR_HSIZE_SHIFT)
> +/* anycast address hash table
> + */
> +static struct hlist_head inet6_acaddr_lst[IN6_ADDR_HSIZE];
> +static DEFINE_SPINLOCK(acaddr_hash_lock);
> +
> static int ipv6_dev_ac_dec(struct net_device *dev, const struct in6_addr *addr);
>
> +static u32 inet6_acaddr_hash(struct net *net, const struct in6_addr *addr)
> +{
> + u32 val = ipv6_addr_hash(addr) ^ net_hash_mix(net);
> +
> + return hash_32(val, IN6_ADDR_HSIZE_SHIFT);
> +}
> +
> /*
> * socket join an anycast group
> */
> @@ -204,6 +218,83 @@ void ipv6_sock_ac_close(struct sock *sk)
> rtnl_unlock();
> }
>
> +static struct ipv6_ac_addrlist *acal_alloc(struct net *net,
> + const struct in6_addr *addr)
> +{
> + struct ipv6_ac_addrlist *acal;
> +
> + acal = kzalloc(sizeof(*acal), GFP_ATOMIC);
> + if (!acal)
> + return NULL;
> +
> + acal->acal_addr = *addr;
> + write_pnet(&acal->acal_pnet, get_net(net));
I am not sure why you grab a reference on the netns.
The ipv6 address will be freed at some point before the netns disappears.
It would automatically remove the associated struct ipv6_ac_addrlist.
> + acal->acal_users = 1;
> + INIT_HLIST_NODE(&acal->acal_lst);
> +
> + return acal;
> +}
> +
> +static void acal_free_rcu(struct rcu_head *h)
> +{
> + struct ipv6_ac_addrlist *acal;
> +
> + acal = container_of(h, struct ipv6_ac_addrlist, rcu);
> + WARN_ON(acal->acal_users);
Not needed with refcount_t debugging infra.
> + put_net(read_pnet(&acal->acal_pnet));
> + kfree(acal);
So this could use kfree_rcu() in the caller, and get rid of acal_free_rcu() completely.
> +}
> +
> +static int ipv6_add_acaddr_hash(struct net *net, const struct in6_addr *addr)
> +{
> + unsigned int hash = inet6_acaddr_hash(net, addr);
> + struct ipv6_ac_addrlist *acal;
> + int err = 0;
> +
> + spin_lock(&acaddr_hash_lock);
> + hlist_for_each_entry(acal, &inet6_acaddr_lst[hash], acal_lst) {
> + if (!net_eq(read_pnet(&acal->acal_pnet), net))
> + continue;
> + if (ipv6_addr_equal(&acal->acal_addr, addr)) {
> + acal->acal_users++;
> + goto out;
> + }
> + }
> +
> + acal = acal_alloc(net, addr);
> + if (!acal) {
> + err = -ENOMEM;
> + goto out;
> + }
> +
> + hlist_add_head_rcu(&acal->acal_lst, &inet6_acaddr_lst[hash]);
> +
> +out:
> + spin_unlock(&acaddr_hash_lock);
> + return err;
> +}
> +
> +static void ipv6_del_acaddr_hash(struct net *net, const struct in6_addr *addr)
> +{
> + unsigned int hash = inet6_acaddr_hash(net, addr);
> + struct ipv6_ac_addrlist *acal;
> +
> + spin_lock(&acaddr_hash_lock);
> + hlist_for_each_entry(acal, &inet6_acaddr_lst[hash], acal_lst) {
> + if (!net_eq(read_pnet(&acal->acal_pnet), net))
> + continue;
> + if (ipv6_addr_equal(&acal->acal_addr, addr)) {
> + if (--acal->acal_users < 1) {
> + hlist_del_init_rcu(&acal->acal_lst);
> + call_rcu(&acal->rcu, acal_free_rcu);
> + }
> + spin_unlock(&acaddr_hash_lock);
> + return;
> + }
> + }
> + spin_unlock(&acaddr_hash_lock);
> +}
> +
> static void aca_get(struct ifacaddr6 *aca)
> {
> refcount_inc(&aca->aca_refcnt);
> @@ -275,6 +366,13 @@ int __ipv6_dev_ac_inc(struct inet6_dev *idev, const struct in6_addr *addr)
> err = -ENOMEM;
> goto out;
> }
> + err = ipv6_add_acaddr_hash(dev_net(idev->dev), addr);
> + if (err) {
> + fib6_info_release(f6i);
> + fib6_info_release(f6i);
Double call to fib6_info_release() ? Why ?
> + kfree(aca);
> + goto out;
> + }
>
> aca->aca_next = idev->ac_list;
> idev->ac_list = aca;
> @@ -324,6 +422,7 @@ int __ipv6_dev_ac_dec(struct inet6_dev *idev, const struct in6_addr *addr)
> prev_aca->aca_next = aca->aca_next;
> else
> idev->ac_list = aca->aca_next;
> + ipv6_del_acaddr_hash(dev_net(idev->dev), &aca->aca_addr);
> write_unlock_bh(&idev->lock);
> addrconf_leave_solict(idev, &aca->aca_addr);
>
> @@ -350,6 +449,8 @@ void ipv6_ac_destroy_dev(struct inet6_dev *idev)
> write_lock_bh(&idev->lock);
> while ((aca = idev->ac_list) != NULL) {
> idev->ac_list = aca->aca_next;
> + ipv6_del_acaddr_hash(dev_net(idev->dev), &aca->aca_addr);
> +
> write_unlock_bh(&idev->lock);
>
> addrconf_leave_solict(idev, &aca->aca_addr);
> @@ -391,16 +492,22 @@ bool ipv6_chk_acast_addr(struct net *net, struct net_device *dev,
> const struct in6_addr *addr)
> {
> bool found = false;
> + unsigned int hash = inet6_acaddr_hash(net, addr);
> + struct ipv6_ac_addrlist *acal;
Reorder variable declaration in longest to shortest (reverse xmas tree),
per David Miller request :)
>
> rcu_read_lock();
> if (dev)
> found = ipv6_chk_acast_dev(dev, addr);
> else
> - for_each_netdev_rcu(net, dev)
> - if (ipv6_chk_acast_dev(dev, addr)) {
> + hlist_for_each_entry_rcu(acal, &inet6_acaddr_lst[hash],
> + acal_lst) {
> + if (!net_eq(read_pnet(&acal->acal_pnet), net))
> + continue;
> + if (ipv6_addr_equal(&acal->acal_addr, addr)) {
> found = true;
> break;
> }
> + }
> rcu_read_unlock();
> return found;
> }
> @@ -539,4 +646,25 @@ void ac6_proc_exit(struct net *net)
> {
> remove_proc_entry("anycast6", net->proc_net);
> }
> +
> +/* Init / cleanup code
> + */
> +int __init anycast_init(void)
> +{
> + int i;
> +
> + for (i = 0; i < IN6_ADDR_HSIZE; i++)
> + INIT_HLIST_HEAD(&inet6_acaddr_lst[i]);
> + return 0;
> +}
> +
> +void anycast_cleanup(void)
> +{
> + int i;
> +
> + spin_lock(&acaddr_hash_lock);
> + for (i = 0; i < IN6_ADDR_HSIZE; i++)
> + WARN_ON(!hlist_empty(&inet6_acaddr_lst[i]));
> + spin_unlock(&acaddr_hash_lock);
> +}
> #endif
>
^ permalink raw reply
* Re: [PATCH] bpf: btf: Fix a missing-check bug
From: Wenwen Wang @ 2018-10-24 11:36 UTC (permalink / raw)
To: daniel
Cc: ys114321, Kangjie Lu, ast, open list:NETWORKING [GENERAL],
open list, Wenwen Wang
In-Reply-To: <ff23c4af-9e31-8a79-9c37-95766bff7619@iogearbox.net>
On Wed, Oct 24, 2018 at 4:39 AM Daniel Borkmann <daniel@iogearbox.net> wrote:
>
> Hi Wenwen,
>
> On 10/22/2018 05:57 PM, Y Song wrote:
> > On Fri, Oct 19, 2018 at 3:30 PM Wenwen Wang <wang6495@umn.edu> wrote:
> >>
> >> In btf_parse(), the header of the user-space btf data 'btf_data' is firstly
> >> parsed and verified through btf_parse_hdr(). In btf_parse_hdr(), the header
> >> is copied from user-space 'btf_data' to kernel-space 'btf->hdr' and then
> >> verified. If no error happens during the verification process, the whole
> >> data of 'btf_data', including the header, is then copied to 'data' in
> >> btf_parse(). It is obvious that the header is copied twice here. More
> >> importantly, no check is enforced after the second copy to make sure the
> >> headers obtained in these two copies are same. Given that 'btf_data'
> >> resides in the user space, a malicious user can race to modify the header
> >> between these two copies. By doing so, the user can inject inconsistent
> >> data, which can cause undefined behavior of the kernel and introduce
> >> potential security risk.
> >>
> >> To avoid the above issue, this patch rewrites the header after the second
> >> copy, using 'btf->hdr', which is obtained in the first copy.
> >>
> >> Signed-off-by: Wenwen Wang <wang6495@umn.edu>
> >> ---
> >> kernel/bpf/btf.c | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/kernel/bpf/btf.c b/kernel/bpf/btf.c
> >> index 138f030..2a85f91 100644
> >> --- a/kernel/bpf/btf.c
> >> +++ b/kernel/bpf/btf.c
> >> @@ -2202,6 +2202,9 @@ static struct btf *btf_parse(void __user *btf_data, u32 btf_data_size,
> >> goto errout;
> >> }
> >>
> >> + memcpy(data, &btf->hdr,
> >> + min_t(u32, btf->hdr.hdr_len, sizeof(btf->hdr)));
> >
> > Could you restructure the code to memcpy the header followed by copying
> > the rest of btf_data with copy_from_user? This way, each byte is only
> > copied once.
> > Could you add some comments right before memcpy so later people will know
> > why we implement this way?
>
> Thanks for the fix! Agree with Yonghong that we should rework this a bit, so
> please respin a v2 with the feedback addressed, thanks.
Hi Yonghong and Daniel,
Thanks for your suggestions! No problem, I will work on the v2 and
resubmit the patch.
Wenwen
^ permalink raw reply
* Re: [RFC PATCH 0/3] M_CAN Framework rework
From: Dan Murphy @ 2018-10-24 11:36 UTC (permalink / raw)
To: Wolfgang Grandegger, mkl, davem; +Cc: linux-can, netdev, linux-kernel
In-Reply-To: <8d7fcd11-b537-97c1-ee50-ba30f236b5ec@grandegger.com>
Wolfgang
On 10/24/2018 02:43 AM, Wolfgang Grandegger wrote:
> Hallo Dan,
>
> I will have a closer look later this week. Unfortunately you already
> renamed file names and structs making the patch almost unreadable. More
> soon..
>
I tried to format the patch to eliminate the massive change but format patch kept
giving me the same result.
It is a massive change regardless not sure how else to make is smaller.
I guess this is why I opt'd to just create the dedicated TCAN driver.
Dan
> Thanks for you patience,
>
> Wolfgang.
>
> Am 17.10.2018 um 22:21 schrieb Dan Murphy:
>> Bump
>>
>> On 10/10/2018 09:20 AM, Dan Murphy wrote:
>>> All
>>>
>>> This patch series creates a m_can core framework that devices can register
>>> to. The m_can core manages the Bosch IP and CAN frames. Each device that
>>> is registered is responsible for managing device specific functions.
>>>
>>> This rewrite was suggested in a device driver submission for the TCAN4x5x
>>> device
>>> Reference upstream post:
>>> https://lore.kernel.org/patchwork/patch/984163/
>>>
>>> For instance the TCAN device is a SPI device that uses a specific data payload to
>>> determine writes and reads. In addition the device has a reset input as well
>>> as a wakeup pin. The register offset of the m_can registers differs and must
>>> be set by the device attached to the core.
>>>
>>> The m_can core will use iomapped writes and reads as the default mechanism for
>>> writing and reading. The device driver can provide over rides for this.
>>>
>>> This patch series is not complete as it does not handle the CAN interrupts
>>> nor can perform a CAN write. If this patch series is deemed acceptable I will
>>> finish debugging the driver and post a non RFC series.
>>>
>>> Finally I did attempt to reduce the first patch with various git format patch
>>> directives but none seemed to reduce the patch.
>>>
>>> Dan
>>>
>>> Dan Murphy (3):
>>> can: m_can: Create m_can core to leverage common code
>>> dt-bindings: can: tcan4x5x: Add DT bindings for TCAN4x5X driver
>>> can: tcan4x5x: Add tcan4x5x driver to the kernel
>>>
>>> .../devicetree/bindings/net/can/tcan4x5x.txt | 34 +
>>> drivers/net/can/m_can/Kconfig | 18 +
>>> drivers/net/can/m_can/Makefile | 4 +-
>>> drivers/net/can/m_can/m_can.c | 1683 +----------------
>>> .../net/can/m_can/{m_can.c => m_can_core.c} | 479 +++--
>>> drivers/net/can/m_can/m_can_core.h | 100 +
>>> drivers/net/can/m_can/tcan4x5x.c | 321 ++++
>>> 7 files changed, 722 insertions(+), 1917 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/net/can/tcan4x5x.txt
>>> copy drivers/net/can/m_can/{m_can.c => m_can_core.c} (83%)
>>> create mode 100644 drivers/net/can/m_can/m_can_core.h
>>> create mode 100644 drivers/net/can/m_can/tcan4x5x.c
>>>
>>
>>
--
------------------
Dan Murphy
^ permalink raw reply
* Re: [RFC PATCH net-next 3/4] net: ethernet: ti: cpsw: fix vlan mcast
From: Ivan Khoronzhuk @ 2018-10-24 11:36 UTC (permalink / raw)
To: grygorii.strashko, davem
Cc: linux-omap, netdev, linux-kernel, alexander.h.duyck
In-Reply-To: <20181016182035.18234-4-ivan.khoronzhuk@linaro.org>
On Tue, Oct 16, 2018 at 09:20:34PM +0300, Ivan Khoronzhuk wrote:
>At this moment, mcast addresses are added only for real device only
>(reserved vlans for dual-emac mode), even if a mcast address was added
>for some vlan only, thus ALE doesn't have corresponding vlan mcast
>entries after vlan socket joined multicast group. So ALE drops vlan
>frames with mcast addresses intended for vlans and potentially can
>receive mcast frames for base ndev. That's not correct. So, fix it by
>creating only vlan/mcast entries as requested. Patch doesn't use any
>additional lists and is based on device mc address list and cpsw ALE
>table entries.
>
>Also, move device to allmulti state if no space for new mcast entries.
>
>Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
I won't update allmulti state on v2, will do that separately as it
requires also splitting allmulti between interfaces in dual-mac mode.
Would be nice to move allmulti and promisc to ndo_change_rx_flags()
and do updates only if flag is changed, not for every address change.
Also there is an ability to set allmulti per vlan device and even
dev->allmulti counter can be used for that and it works, but in case
of allmulti flag there is no event from dev core if it's already set
(only allmuilti counter is changed w/o event). Thus no event to
segregate it between vlans. Adding update to dev core can lead to
more frequent rx_mode event and w/o reason for those devices who
doesn't care. I'm just wondering, why not to add smth like
IFF_VLAN_MCAST_FLT to dev->priv_flags and based on it generate
event differently or even do more stuff ....
Or leave it as is and set allmulti for every vlan, that seems
like a stub.
[...]
--
Regards,
Ivan Khoronzhuk
^ permalink raw reply
* Re: [PATCH] r8169: Add new device ID support
From: David Miller @ 2018-10-24 2:19 UTC (permalink / raw)
To: shawn.lin; +Cc: nic_swsd, netdev
In-Reply-To: <1540345607-110155-1-git-send-email-shawn.lin@rock-chips.com>
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Wed, 24 Oct 2018 09:46:47 +0800
> It's found my r8169 ethernet card at hand has a device ID
> of 0x0000 which wasn't on the list of rtl8169_pci_tbl. Add
> a new entry to make it work:
...
> 01:00.0 Class 0200: 10ec:0000
I don't know about this.
A value of zero could mean the device is mis-responding to
PCI config space requests or something like that.
^ permalink raw reply
* [PATCH net v2] net/ipv6: Add anycast addresses to a global hashtable
From: Jeff Barnhill @ 2018-10-24 1:58 UTC (permalink / raw)
To: netdev; +Cc: davem, kuznet, yoshfuji, Jeff Barnhill
In-Reply-To: <CAL6e_pfbKTr0LftQKOkOBLvS4N_mJLi62TS_h_23zuU_pFi+Vg@mail.gmail.com>
icmp6_send() function is expensive on systems with a large number of
interfaces. Every time it’s called, it has to verify that the source
address does not correspond to an existing anycast address by looping
through every device and every anycast address on the device. This can
result in significant delays for a CPU when there are a large number of
neighbors and ND timers are frequently timing out and calling
neigh_invalidate().
Add anycast addresses to a global hashtable to allow quick searching for
matching anycast addresses. This is based on inet6_addr_lst in addrconf.c.
Signed-off-by: Jeff Barnhill <0xeffeff@gmail.com>
---
include/net/addrconf.h | 2 +
include/net/if_inet6.h | 8 +++
net/ipv6/af_inet6.c | 5 ++
net/ipv6/anycast.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++++-
4 files changed, 145 insertions(+), 2 deletions(-)
diff --git a/include/net/addrconf.h b/include/net/addrconf.h
index 6def0351bcc3..0cee3f99c41d 100644
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -312,6 +312,8 @@ bool ipv6_chk_acast_addr(struct net *net, struct net_device *dev,
const struct in6_addr *addr);
bool ipv6_chk_acast_addr_src(struct net *net, struct net_device *dev,
const struct in6_addr *addr);
+int anycast_init(void);
+void anycast_cleanup(void);
/* Device notifier */
int register_inet6addr_notifier(struct notifier_block *nb);
diff --git a/include/net/if_inet6.h b/include/net/if_inet6.h
index d7578cf49c3a..55a4a1d8cebc 100644
--- a/include/net/if_inet6.h
+++ b/include/net/if_inet6.h
@@ -142,6 +142,14 @@ struct ipv6_ac_socklist {
struct ipv6_ac_socklist *acl_next;
};
+struct ipv6_ac_addrlist {
+ struct in6_addr acal_addr;
+ possible_net_t acal_pnet;
+ int acal_users;
+ struct hlist_node acal_lst; /* inet6_acaddr_lst */
+ struct rcu_head rcu;
+};
+
struct ifacaddr6 {
struct in6_addr aca_addr;
struct fib6_info *aca_rt;
diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c
index 9a4261e50272..971a05fdd3bd 100644
--- a/net/ipv6/af_inet6.c
+++ b/net/ipv6/af_inet6.c
@@ -1001,6 +1001,9 @@ static int __init inet6_init(void)
err = ip6_flowlabel_init();
if (err)
goto ip6_flowlabel_fail;
+ err = anycast_init();
+ if (err)
+ goto anycast_fail;
err = addrconf_init();
if (err)
goto addrconf_fail;
@@ -1091,6 +1094,8 @@ static int __init inet6_init(void)
ipv6_exthdrs_fail:
addrconf_cleanup();
addrconf_fail:
+ anycast_cleanup();
+anycast_fail:
ip6_flowlabel_cleanup();
ip6_flowlabel_fail:
ndisc_late_cleanup();
diff --git a/net/ipv6/anycast.c b/net/ipv6/anycast.c
index 4e0ff7031edd..def1e156d857 100644
--- a/net/ipv6/anycast.c
+++ b/net/ipv6/anycast.c
@@ -44,8 +44,22 @@
#include <net/checksum.h>
+#define IN6_ADDR_HSIZE_SHIFT 8
+#define IN6_ADDR_HSIZE BIT(IN6_ADDR_HSIZE_SHIFT)
+/* anycast address hash table
+ */
+static struct hlist_head inet6_acaddr_lst[IN6_ADDR_HSIZE];
+static DEFINE_SPINLOCK(acaddr_hash_lock);
+
static int ipv6_dev_ac_dec(struct net_device *dev, const struct in6_addr *addr);
+static u32 inet6_acaddr_hash(struct net *net, const struct in6_addr *addr)
+{
+ u32 val = ipv6_addr_hash(addr) ^ net_hash_mix(net);
+
+ return hash_32(val, IN6_ADDR_HSIZE_SHIFT);
+}
+
/*
* socket join an anycast group
*/
@@ -204,6 +218,83 @@ void ipv6_sock_ac_close(struct sock *sk)
rtnl_unlock();
}
+static struct ipv6_ac_addrlist *acal_alloc(struct net *net,
+ const struct in6_addr *addr)
+{
+ struct ipv6_ac_addrlist *acal;
+
+ acal = kzalloc(sizeof(*acal), GFP_ATOMIC);
+ if (!acal)
+ return NULL;
+
+ acal->acal_addr = *addr;
+ write_pnet(&acal->acal_pnet, get_net(net));
+ acal->acal_users = 1;
+ INIT_HLIST_NODE(&acal->acal_lst);
+
+ return acal;
+}
+
+static void acal_free_rcu(struct rcu_head *h)
+{
+ struct ipv6_ac_addrlist *acal;
+
+ acal = container_of(h, struct ipv6_ac_addrlist, rcu);
+ WARN_ON(acal->acal_users);
+ put_net(read_pnet(&acal->acal_pnet));
+ kfree(acal);
+}
+
+static int ipv6_add_acaddr_hash(struct net *net, const struct in6_addr *addr)
+{
+ unsigned int hash = inet6_acaddr_hash(net, addr);
+ struct ipv6_ac_addrlist *acal;
+ int err = 0;
+
+ spin_lock(&acaddr_hash_lock);
+ hlist_for_each_entry(acal, &inet6_acaddr_lst[hash], acal_lst) {
+ if (!net_eq(read_pnet(&acal->acal_pnet), net))
+ continue;
+ if (ipv6_addr_equal(&acal->acal_addr, addr)) {
+ acal->acal_users++;
+ goto out;
+ }
+ }
+
+ acal = acal_alloc(net, addr);
+ if (!acal) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ hlist_add_head_rcu(&acal->acal_lst, &inet6_acaddr_lst[hash]);
+
+out:
+ spin_unlock(&acaddr_hash_lock);
+ return err;
+}
+
+static void ipv6_del_acaddr_hash(struct net *net, const struct in6_addr *addr)
+{
+ unsigned int hash = inet6_acaddr_hash(net, addr);
+ struct ipv6_ac_addrlist *acal;
+
+ spin_lock(&acaddr_hash_lock);
+ hlist_for_each_entry(acal, &inet6_acaddr_lst[hash], acal_lst) {
+ if (!net_eq(read_pnet(&acal->acal_pnet), net))
+ continue;
+ if (ipv6_addr_equal(&acal->acal_addr, addr)) {
+ if (--acal->acal_users < 1) {
+ hlist_del_init_rcu(&acal->acal_lst);
+ call_rcu(&acal->rcu, acal_free_rcu);
+ }
+ spin_unlock(&acaddr_hash_lock);
+ return;
+ }
+ }
+ spin_unlock(&acaddr_hash_lock);
+}
+
static void aca_get(struct ifacaddr6 *aca)
{
refcount_inc(&aca->aca_refcnt);
@@ -275,6 +366,13 @@ int __ipv6_dev_ac_inc(struct inet6_dev *idev, const struct in6_addr *addr)
err = -ENOMEM;
goto out;
}
+ err = ipv6_add_acaddr_hash(dev_net(idev->dev), addr);
+ if (err) {
+ fib6_info_release(f6i);
+ fib6_info_release(f6i);
+ kfree(aca);
+ goto out;
+ }
aca->aca_next = idev->ac_list;
idev->ac_list = aca;
@@ -324,6 +422,7 @@ int __ipv6_dev_ac_dec(struct inet6_dev *idev, const struct in6_addr *addr)
prev_aca->aca_next = aca->aca_next;
else
idev->ac_list = aca->aca_next;
+ ipv6_del_acaddr_hash(dev_net(idev->dev), &aca->aca_addr);
write_unlock_bh(&idev->lock);
addrconf_leave_solict(idev, &aca->aca_addr);
@@ -350,6 +449,8 @@ void ipv6_ac_destroy_dev(struct inet6_dev *idev)
write_lock_bh(&idev->lock);
while ((aca = idev->ac_list) != NULL) {
idev->ac_list = aca->aca_next;
+ ipv6_del_acaddr_hash(dev_net(idev->dev), &aca->aca_addr);
+
write_unlock_bh(&idev->lock);
addrconf_leave_solict(idev, &aca->aca_addr);
@@ -391,16 +492,22 @@ bool ipv6_chk_acast_addr(struct net *net, struct net_device *dev,
const struct in6_addr *addr)
{
bool found = false;
+ unsigned int hash = inet6_acaddr_hash(net, addr);
+ struct ipv6_ac_addrlist *acal;
rcu_read_lock();
if (dev)
found = ipv6_chk_acast_dev(dev, addr);
else
- for_each_netdev_rcu(net, dev)
- if (ipv6_chk_acast_dev(dev, addr)) {
+ hlist_for_each_entry_rcu(acal, &inet6_acaddr_lst[hash],
+ acal_lst) {
+ if (!net_eq(read_pnet(&acal->acal_pnet), net))
+ continue;
+ if (ipv6_addr_equal(&acal->acal_addr, addr)) {
found = true;
break;
}
+ }
rcu_read_unlock();
return found;
}
@@ -539,4 +646,25 @@ void ac6_proc_exit(struct net *net)
{
remove_proc_entry("anycast6", net->proc_net);
}
+
+/* Init / cleanup code
+ */
+int __init anycast_init(void)
+{
+ int i;
+
+ for (i = 0; i < IN6_ADDR_HSIZE; i++)
+ INIT_HLIST_HEAD(&inet6_acaddr_lst[i]);
+ return 0;
+}
+
+void anycast_cleanup(void)
+{
+ int i;
+
+ spin_lock(&acaddr_hash_lock);
+ for (i = 0; i < IN6_ADDR_HSIZE; i++)
+ WARN_ON(!hlist_empty(&inet6_acaddr_lst[i]));
+ spin_unlock(&acaddr_hash_lock);
+}
#endif
--
2.14.1
^ permalink raw reply related
* Re: [PATCH net-next] tcp: add tcp_reset_xmit_timer() helper
From: David Miller @ 2018-10-24 2:49 UTC (permalink / raw)
To: edumazet; +Cc: ncardwell, ycheng, soheil, vanj, netdev, eric.dumazet
In-Reply-To: <20181023185416.182102-1-edumazet@google.com>
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 23 Oct 2018 11:54:16 -0700
> With EDT model, SRTT no longer is inflated by pacing delays.
>
> This means that RTO and some other xmit timers might be setup
> incorrectly. This is particularly visible with either :
>
> - Very small enforced pacing rates (SO_MAX_PACING_RATE)
> - Reduced rto (from the default 200 ms)
>
> This can lead to TCP flows aborts in the worst case,
> or spurious retransmits in other cases.
>
> For example, this session gets far more throughput
> than the requested 80kbit :
>
> $ netperf -H 127.0.0.2 -l 100 -- -q 10000
> MIGRATED TCP STREAM TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 127.0.0.2 () port 0 AF_INET
> Recv Send Send
> Socket Socket Message Elapsed
> Size Size Size Time Throughput
> bytes bytes bytes secs. 10^6bits/sec
>
> 540000 262144 262144 104.00 2.66
>
> With the fix :
>
> $ netperf -H 127.0.0.2 -l 100 -- -q 10000
> MIGRATED TCP STREAM TEST from 0.0.0.0 (0.0.0.0) port 0 AF_INET to 127.0.0.2 () port 0 AF_INET
> Recv Send Send
> Socket Socket Message Elapsed
> Size Size Size Time Throughput
> bytes bytes bytes secs. 10^6bits/sec
>
> 540000 262144 262144 104.00 0.12
>
> EDT allows for better control of rtx timers, since TCP has
> a better idea of the earliest departure time of each skb
> in the rtx queue. We only have to eventually add to the
> timer the difference of the EDT time with current time.
>
> Signed-off-by: Eric Dumazet <edumazet@google.com>
Applied.
^ permalink raw reply
* Re: [PATCH v2] wireless: mark expected switch fall-throughs
From: Julian Calaby @ 2018-10-24 9:40 UTC (permalink / raw)
To: gustavo
Cc: David S. Miller, Johannes Berg, linux-wireless, netdev,
linux-kernel@vger.kernel.org, Kees Cook
In-Reply-To: <94958073867a5bbf8161d7ea8851aaea026762b1.camel@sipsolutions.net>
Hi Gustavo,
On Wed, Oct 24, 2018 at 7:36 AM Johannes Berg <johannes@sipsolutions.net> wrote:
>
> On Tue, 2018-10-23 at 12:58 +0200, Gustavo A. R. Silva wrote:
> > On 10/23/18 10:59 AM, Gustavo A. R. Silva wrote:
> > >
> > > On 10/23/18 9:01 AM, Johannes Berg wrote:
> > > > On Tue, 2018-10-23 at 02:13 +0200, Gustavo A. R. Silva wrote:
> > > > > In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> > > > > where we are expecting to fall through.
> > > > >
> > > > > Warning level 3 was used: -Wimplicit-fallthrough=3
> > > > >
> > > > > This code was not tested and GCC 7.2.0 was used to compile it.
> > > >
> > > > Look, I'm not going to make this any clearer: I'm not applying patches
> > > > like that where you've invested no effort whatsoever on verifying that
> > > > they're correct.
> > > >
> > >
> > > How do you suggest me to verify that every part is correct in this type
> > > of patches?
> > >
> >
> > BTW... I'm under the impression you think that I don't even look at
> > the code. Is that correct?
>
> That's what your commit log looks like, yes. This is your full commit
> log:
>
> In preparation to enabling -Wimplicit-fallthrough, mark switch cases
> where we are expecting to fall through.
>
> Warning level 3 was used: -Wimplicit-fallthrough=3
>
> This code was not tested and GCC 7.2.0 was used to compile it.
>
> For all I know, you could've run spatch to add the comments wherever
> there was no break, and then compiled it once.
It might also help to split these up by the "type" of change. For
example this patch contains:
1. A whole lot of places where there's a "if (condition) { break; }"
just before the fall through
You could add a line describing the logic there to the commit message,
maybe something like:
As there's a conditional break at the end of the case, the fall
through appears to be intentional.
2. Reformatting an existing comment
These should definitely be split out as they're just reformatting
comments to match gcc's expectations. You could describe this like:
Reformat existing fall through messages into the format expected by gcc.
Thanks,
--
Julian Calaby
Email: julian.calaby@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
^ permalink raw reply
* Re: [PATCH v3 0/7] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64
From: Russell King - ARM Linux @ 2018-10-24 8:57 UTC (permalink / raw)
To: Corentin Labbe
Cc: Gilles.Muller, maxime.ripard, dri-devel, linux-ide, linux-sunxi,
paulus, linux-amlogic, cocci, mpe, narmstrong, galak, airlied,
wens, joabreu, vitb, mporter, agust, alexandre.torgue, alistair,
nicolas.palix, oss, Julia.Lawall, linux-mediatek, matthias.bgg,
peppe.cavallaro, linux-arm-kernel, michal.lkml, netdev,
linux-kernel, khilman, carlo, tj, linuxppc-dev, davem
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
On Wed, Oct 24, 2018 at 07:35:46AM +0000, Corentin Labbe wrote:
> This patchset adds a new set of functions which are open-coded in lot of
> place.
> Basicly the pattern is always the same, "read, modify a bit, write"
> some driver and the powerpc arch already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b)
The advantage of them being open-coded is that it's _obvious_ to the
reviewer that there is a read-modify-write going on which, in a multi-
threaded environment, may need some locking (so it should trigger a
review of the locking around that code.)
With it hidden inside a helper which has no locking itself, it becomes
much easier to pass over in review, which means that races are much
more likely to go unspotted - and that is bad news.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH net-next v2 0/6] net/ncsi: Allow enabling multiple packages & channels
From: David Miller @ 2018-10-23 23:55 UTC (permalink / raw)
To: sam; +Cc: netdev, Justin.Lee1, linux-kernel, openbmc
In-Reply-To: <20181023215201.27315-1-sam@mendozajonas.com>
From: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Date: Wed, 24 Oct 2018 10:51:55 +1300
> This series extends the NCSI driver to configure multiple packages
> and/or channels simultaneously. Since the RFC series this includes a few
> extra changes to fix areas in the driver that either made this harder or
> were roadblocks due to deviations from the NCSI specification.
>
> Patches 1 & 2 fix two issues where the driver made assumptions about the
> capabilities of the NCSI topology.
> Patches 3 & 4 change some internal semantics slightly to make multi-mode
> easier.
> Patch 5 introduces a cleaner way of reconfiguring the NCSI configuration
> and keeping track of channel states.
> Patch 6 implements the main multi-package/multi-channel configuration,
> configured via the Netlink interface.
>
> Readers who have an interesting NCSI setup - especially multi-package
> with HWA - please test! I think I've covered all permutations but I
> don't have infinite hardware to test on.
>
> Changes in v2:
> - Updated use of the channel lock in ncsi_reset_dev(), making the
> channel invisible and leaving the monitor check to
> ncsi_stop_channel_monitor().
> - Fixed ncsi_channel_is_tx() to consider the state of channels in other
> packages.
net-next is closed, please resubmit this when net-next opens back up.
Thank you.
^ permalink raw reply
* Re: [GIT] Networking
From: Kalle Valo @ 2018-10-24 8:05 UTC (permalink / raw)
To: Linus Torvalds
Cc: bjorn.andersson@linaro.org, Govind Singh, David Miller,
Andrew Morton, netdev@vger.kernel.org, Linux Kernel Mailing List,
linux-wireless@vger.kernel.org, ath10k@lists.infradead.org,
Jeff Kirsher, niklas.cassel@linaro.org, Andy Gross, David Brown
In-Reply-To: <87lg6nu6k1.fsf@codeaurora.org>
Kalle Valo <kvalo@codeaurora.org> writes:
> Linus Torvalds <torvalds@linux-foundation.org> writes:
>
>> On Wed, Oct 24, 2018 at 7:01 AM Linus Torvalds
>> <torvalds@linux-foundation.org> wrote:
>>>
>>> Hmm. Tentatively pulled, but there's something wrong with the Kconfig rules.
>>
>> Confirmed.
>
> BTW, our emails crossed and more info in the other email[1].
>
>> I did a978a5b8d83f ("net/kconfig: Make QCOM_QMI_HELPERS available when
>> COMPILE_TEST") to fix the breakage.
>
> Thanks, though I don't see it yet as I guess you haven't pushed it yet.
> Do note that it _might_ conflict the other commit which I suspect is in
> also coming to you:
>
> ccfb464cd106 ("soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs")
git.kernel.org is alive again for me so I can now check both commits. It
seems that Niklas' commit[1] is more finegrained than what Linus did[2].
I guess either of the commits should be reverted when Niklas' commit
goes to Linus tree, or what's the best course of action?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git/commit/?h=for-next&id=ccfb464cd106890cfa51070f75921a273e2852e5
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a978a5b8d83f795e107a2ff759b28643739be70e
--
Kalle Valo
^ permalink raw reply
* Re: [PATCH v3 4/7] ata: ahci_sunxi: use xxxsetbitsi_le32 functions
From: Sergei Shtylyov @ 2018-10-24 7:57 UTC (permalink / raw)
To: Corentin Labbe, Gilles.Muller-L2FTfq7BK8M,
Julia.Lawall-L2FTfq7BK8M, agust-ynQEQJNshbs, airlied-cv59FeDIM0c,
alexandre.torgue-qxv4g6HH51o, alistair-Y4h6yKqj69EXC2x5gXVKYQ,
benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
carlo-KA+7E9HrN00dnm+yROfE0A, davem-fT/PcQaiUtIeIZ0/mPfg9Q,
galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
joabreu-HKixBCOQz3hWk0Htik3J/w, khilman-rdvid1DuHRBWk0Htik3J/w,
matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ,
michal.lkml-yyZNWGI4GtDR7s880joybQ, mpe-Gsx/Oe8HsFggBc27wqDAHg,
mporter-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
narmstrong-rdvid1DuHRBWk0Htik3J/w, nicolas.palix-wMUr/XMoy4A,
oss-fOR+EgIDQEHk1uMJSBkQmQ, paulus-eUNUBHrolfbYtjvyW6yDsg,
peppe.cavallaro-qxv4g6HH51o, tj-DgEjT+Ai2ygdnm+yROfE0A,
vitb-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r, wens-jdAy2FN1RRM
Cc: cocci-/FJkirnvOdkvYVN+rsErww,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ,
netdev-u79uwXL29TY76Z2rM5mHXA, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <1540366553-18541-5-git-send-email-clabbe-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Hello!
Typo in the subject: s/xxxsetbitsi/xxxsetbits/.
On 24.10.2018 10:35, Corentin Labbe wrote:
> This patch converts ahci_sunxi to use xxxsetbits_le32 functions
>
> Signed-off-by: Corentin Labbe <clabbe-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
[...]
MBR, Sergei
^ permalink raw reply
* Re: [RFC PATCH 0/3] M_CAN Framework rework
From: Wolfgang Grandegger @ 2018-10-24 7:43 UTC (permalink / raw)
To: Dan Murphy, mkl, davem; +Cc: linux-can, netdev, linux-kernel
In-Reply-To: <e8485e2e-df04-0905-7055-c2228c0f1fa4@ti.com>
Hallo Dan,
I will have a closer look later this week. Unfortunately you already
renamed file names and structs making the patch almost unreadable. More
soon..
Thanks for you patience,
Wolfgang.
Am 17.10.2018 um 22:21 schrieb Dan Murphy:
> Bump
>
> On 10/10/2018 09:20 AM, Dan Murphy wrote:
>> All
>>
>> This patch series creates a m_can core framework that devices can register
>> to. The m_can core manages the Bosch IP and CAN frames. Each device that
>> is registered is responsible for managing device specific functions.
>>
>> This rewrite was suggested in a device driver submission for the TCAN4x5x
>> device
>> Reference upstream post:
>> https://lore.kernel.org/patchwork/patch/984163/
>>
>> For instance the TCAN device is a SPI device that uses a specific data payload to
>> determine writes and reads. In addition the device has a reset input as well
>> as a wakeup pin. The register offset of the m_can registers differs and must
>> be set by the device attached to the core.
>>
>> The m_can core will use iomapped writes and reads as the default mechanism for
>> writing and reading. The device driver can provide over rides for this.
>>
>> This patch series is not complete as it does not handle the CAN interrupts
>> nor can perform a CAN write. If this patch series is deemed acceptable I will
>> finish debugging the driver and post a non RFC series.
>>
>> Finally I did attempt to reduce the first patch with various git format patch
>> directives but none seemed to reduce the patch.
>>
>> Dan
>>
>> Dan Murphy (3):
>> can: m_can: Create m_can core to leverage common code
>> dt-bindings: can: tcan4x5x: Add DT bindings for TCAN4x5X driver
>> can: tcan4x5x: Add tcan4x5x driver to the kernel
>>
>> .../devicetree/bindings/net/can/tcan4x5x.txt | 34 +
>> drivers/net/can/m_can/Kconfig | 18 +
>> drivers/net/can/m_can/Makefile | 4 +-
>> drivers/net/can/m_can/m_can.c | 1683 +----------------
>> .../net/can/m_can/{m_can.c => m_can_core.c} | 479 +++--
>> drivers/net/can/m_can/m_can_core.h | 100 +
>> drivers/net/can/m_can/tcan4x5x.c | 321 ++++
>> 7 files changed, 722 insertions(+), 1917 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/net/can/tcan4x5x.txt
>> copy drivers/net/can/m_can/{m_can.c => m_can_core.c} (83%)
>> create mode 100644 drivers/net/can/m_can/m_can_core.h
>> create mode 100644 drivers/net/can/m_can/tcan4x5x.c
>>
>
>
^ permalink raw reply
* [PATCH v3 5/7] net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits_le32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: cocci, dri-devel, linux-amlogic, linux-arm-kernel, linux-ide,
linux-kernel, linux-mediatek, linuxppc-dev, netdev, linux-sunxi,
Corentin Labbe
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +++++--------------
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index f9a61f90cfbc..74067a59af50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -28,6 +28,7 @@
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/stmmac.h>
+#include <linux/setbits.h>
#include "stmmac.h"
#include "stmmac_platform.h"
@@ -342,50 +343,30 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+ EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+ EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v &= ~EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ clrbits_le32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v |= EMAC_RX_DMA_START;
- v |= EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ setbits_le32(ioaddr + EMAC_RX_CTL1,
+ EMAC_RX_DMA_START | EMAC_RX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v &= ~EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ clrbits_le32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_EN);
}
static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
@@ -578,7 +559,6 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
if (!addr) {
writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
@@ -588,9 +568,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
EMAC_MACADDR_LO(reg_n));
if (reg_n > 0) {
- v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
- v |= MAC_ADDR_TYPE_DST;
- writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
+ setbits_le32(ioaddr + EMAC_MACADDR_HI(reg_n),
+ MAC_ADDR_TYPE_DST);
}
}
@@ -608,11 +587,8 @@ static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
- v |= EMAC_RX_DO_CRC;
- writel(v, ioaddr + EMAC_RX_CTL0);
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_DO_CRC);
return 1;
}
@@ -662,21 +638,15 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
unsigned int pause_time, u32 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
if (fc == FLOW_AUTO)
- v |= EMAC_RX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
else
- v &= ~EMAC_RX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_RX_CTL0);
-
- v = readl(ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
if (fc == FLOW_AUTO)
- v |= EMAC_TX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
else
- v &= ~EMAC_TX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
}
static int sun8i_dwmac_reset(struct stmmac_priv *priv)
--
2.18.1
^ permalink raw reply related
* [PATCH v3 4/7] ata: ahci_sunxi: use xxxsetbitsi_le32 functions
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: cocci, dri-devel, linux-amlogic, linux-arm-kernel, linux-ide,
linux-kernel, linux-mediatek, linuxppc-dev, netdev, linux-sunxi,
Corentin Labbe
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/ata/ahci_sunxi.c | 62 +++++++++++-----------------------------
1 file changed, 17 insertions(+), 45 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..69c2e01c3d52 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include <linux/setbits.h>
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,21 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
- (0x7 << 24),
- (0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
- (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
- (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
- (0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
- (0x1f << 5), (0x19 << 5));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 24),
+ (0x5 << 24) | BIT(23) | BIT(18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 << 20), (0x3 << 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R,
+ (0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +102,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +130,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits_le32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.18.1
^ permalink raw reply related
* [PATCH v3 3/7 DONOTMERGE] coccinelle: add xxxsetbits_leXX converting spatch
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: cocci, dri-devel, linux-amlogic, linux-arm-kernel, linux-ide,
linux-kernel, linux-mediatek, linuxppc-dev, netdev, linux-sunxi,
Corentin Labbe
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch add a spatch which convert all open coded of setbits_le32/clrbits_le32/clrsetbits_le32
and their 64 bits counterparts.
Note that 64 and 32_relaxed are generated via
cp scripts/coccinelle/misc/setbits32.cocci scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,readl,readl_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,writel,writel_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,setbits_le32,setbits_le32_relaxed,g' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,clrbits_le32,clrbits_le32_relaxed,g' scripts/coccinelle/misc/setbits32_relaxed.cocci
cp scripts/coccinelle/misc/setbits32.cocci scripts/coccinelle/misc/setbits64.cocci
sed -i 's,readl,readq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,writel,writeq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,le32,le64,' scripts/coccinelle/misc/setbits64.cocci
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
scripts/add_new_include_in_source.py | 61 +++
scripts/coccinelle/misc/setbits32.cocci | 487 ++++++++++++++++++
.../coccinelle/misc/setbits32_relaxed.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits64.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits_dev.cocci | 235 +++++++++
5 files changed, 1757 insertions(+)
create mode 100755 scripts/add_new_include_in_source.py
create mode 100644 scripts/coccinelle/misc/setbits32.cocci
create mode 100644 scripts/coccinelle/misc/setbits32_relaxed.cocci
create mode 100644 scripts/coccinelle/misc/setbits64.cocci
create mode 100644 scripts/coccinelle/misc/setbits_dev.cocci
diff --git a/scripts/add_new_include_in_source.py b/scripts/add_new_include_in_source.py
new file mode 100755
index 000000000000..a43ccfbf9921
--- /dev/null
+++ b/scripts/add_new_include_in_source.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+# add <linux/setbits.h>
+
+import os, sys
+import re
+import shutil
+
+if len(sys.argv) < 2:
+ print("Usage: %s pathtosourcefile" % (sys.argv[0]))
+ sys.exit(1)
+
+found_global_headers = False
+found_local_headers = False
+#first check it does already here
+with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if re.search("#include <linux/setbits.h>\n", line):
+ print("INFO: header already here")
+ sys.exit(0)
+ if re.search("^#include <", line):
+ found_global_headers = True
+ if re.search("^#include \"", line):
+ found_local_headers = True
+ fp.close()
+
+if not found_global_headers and not found_local_headers:
+ print("No header included do it at hand")
+ sys.exit(1)
+
+if found_global_headers:
+ done = False
+ inheader = False
+ with open("%s.new" % sys.argv[1], 'w') as fw:
+ with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if re.search("^#include <linux/", line):
+ inheader = True
+ if (not done and line[16] >= "s" and line[17] >= "e" and line[18] >= "t" and line[19] >= 'b'):
+ done = True
+ fw.write("#include <linux/setbits.h>\n")
+ if not done and not re.search("^#include <linux/", line) and inheader:
+ done = True
+ fw.write("#include <linux/setbits.h>\n")
+ fw.write(line)
+ fw.close()
+ fp.close()
+else:
+ done = False
+ with open("%s.new" % sys.argv[1], 'w') as fw:
+ with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if not done and re.search("^#include \"", line):
+ fw.write("#include <linux/setbits.h>\n")
+ done = True
+ fw.write(line)
+ fw.close()
+ fp.close()
+
+shutil.move("%s.new" % sys.argv[1], sys.argv[1])
+print("%s done" % sys.argv[1])
diff --git a/scripts/coccinelle/misc/setbits32.cocci b/scripts/coccinelle/misc/setbits32.cocci
new file mode 100644
index 000000000000..71400cac6830
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l4@
+p1 << p_clrsetbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear | set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l3@
+p1 << p_clrsetbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) & ~mask | set, addr);
++ clrsetbits_le32(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p((readl(addr) & ~mask) | set, addr);
++ clrsetbits_le32(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set;
+- rr &= ~clear;
+- writel(rr, addr);
++ setclrbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_l4@
+p1 << p_setclrbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set & ~clear;
+- writel(rr, addr);
++ setclrbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_l3@
+p1 << p_setclrbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) | set & ~mask, addr);
++ setclrbits_le32(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p((readl(addr) | set) & ~mask, addr);
++ setclrbits_le32(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- writel(rr, addr);
++ clrbits_le32(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l3@
+p1 << p_clrbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- writel(rr & ~mask, addr);
++ clrbits_le32(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l2_a@
+p1 << p_clrbits_le32_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr) & ~mask;
+- writel(rr, addr);
++ clrbits_le32(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l2_b@
+p1 << p_clrbits_le32_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) & ~mask, addr);
++ clrbits_le32(addr, mask);
+
+@script:python depends on p_clrbits_le32_oneliner@
+p1 << p_clrbits_le32_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_l3@
+p1 << p_setbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set1;
+- rr |= set2;
+- writel(rr, addr);
++ setbits_le32(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_l4@
+p1 << p_setbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le32@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr);
+- rr |= set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le32_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr);
+- writel(rr | set, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le32_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr) | set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writel(readl(addr) | set, addr);
++ setbits_le32(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+ if (...)
+- rr |= set;
++ setbits_le32(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le32(addr, clear);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le32(addr, clear);
+ else
+- rr |= set;
++ setbits_le32(addr, set);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le32(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le32(addr, clear, set2);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le32(addr, clear, set);
++ else
++ setbits_le32(addr, set);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readl(addr) & ~mask);
+//- writel(rr, addr);
+//+ setmask_le32(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits32_relaxed.cocci b/scripts/coccinelle/misc/setbits32_relaxed.cocci
new file mode 100644
index 000000000000..edf8c39e939e
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32_relaxed.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel_relaxed(rr, addr);
++ clrsetbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_relaxed_l4@
+p1 << p_clrsetbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear | set;
+- writel_relaxed(rr, addr);
++ clrsetbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_relaxed_l3@
+p1 << p_clrsetbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) & ~mask | set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p((readl_relaxed(addr) & ~mask) | set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set;
+- rr &= ~clear;
+- writel_relaxed(rr, addr);
++ setclrbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_relaxed_l4@
+p1 << p_setclrbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set & ~clear;
+- writel_relaxed(rr, addr);
++ setclrbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_relaxed_l3@
+p1 << p_setclrbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) | set & ~mask, addr);
++ setclrbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p((readl_relaxed(addr) | set) & ~mask, addr);
++ setclrbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+- writel_relaxed(rr, addr);
++ clrbits_le32_relaxed(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l3@
+p1 << p_clrbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- writel_relaxed(rr & ~mask, addr);
++ clrbits_le32_relaxed(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l2_a@
+p1 << p_clrbits_le32_relaxed_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr) & ~mask;
+- writel_relaxed(rr, addr);
++ clrbits_le32_relaxed(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l2_b@
+p1 << p_clrbits_le32_relaxed_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) & ~mask, addr);
++ clrbits_le32_relaxed(addr, mask);
+
+@script:python depends on p_clrbits_le32_relaxed_oneliner@
+p1 << p_clrbits_le32_relaxed_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_relaxed_l3@
+p1 << p_setbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set1;
+- rr |= set2;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_relaxed_l4@
+p1 << p_setbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le32_relaxed@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr);
+- rr |= set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le32_relaxed_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr);
+- writel_relaxed(rr | set, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le32_relaxed_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr) | set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writel_relaxed(readl_relaxed(addr) | set, addr);
++ setbits_le32_relaxed(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+ if (...)
+- rr |= set;
++ setbits_le32_relaxed(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le32_relaxed(addr, clear);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le32_relaxed(addr, clear);
+ else
+- rr |= set;
++ setbits_le32_relaxed(addr, set);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le32_relaxed(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le32_relaxed(addr, clear, set2);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le32_relaxed(addr, clear, set);
++ else
++ setbits_le32_relaxed(addr, set);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readl_relaxed(addr) & ~mask);
+//- writel_relaxed(rr, addr);
+//+ setmask_le32(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits64.cocci b/scripts/coccinelle/misc/setbits64.cocci
new file mode 100644
index 000000000000..00df21005b18
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits64.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+- rr |= set;
+- writeq(rr, addr);
++ clrsetbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le64_l4@
+p1 << p_clrsetbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear | set;
+- writeq(rr, addr);
++ clrsetbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le64_l3@
+p1 << p_clrsetbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) & ~mask | set, addr);
++ clrsetbits_le64(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p((readq(addr) & ~mask) | set, addr);
++ clrsetbits_le64(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set;
+- rr &= ~clear;
+- writeq(rr, addr);
++ setclrbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le64_l4@
+p1 << p_setclrbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set & ~clear;
+- writeq(rr, addr);
++ setclrbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le64_l3@
+p1 << p_setclrbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) | set & ~mask, addr);
++ setclrbits_le64(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p((readq(addr) | set) & ~mask, addr);
++ setclrbits_le64(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+- writeq(rr, addr);
++ clrbits_le64(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l3@
+p1 << p_clrbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- writeq(rr & ~mask, addr);
++ clrbits_le64(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l2_a@
+p1 << p_clrbits_le64_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr) & ~mask;
+- writeq(rr, addr);
++ clrbits_le64(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l2_b@
+p1 << p_clrbits_le64_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) & ~mask, addr);
++ clrbits_le64(addr, mask);
+
+@script:python depends on p_clrbits_le64_oneliner@
+p1 << p_clrbits_le64_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le64_l3@
+p1 << p_setbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set1;
+- rr |= set2;
+- writeq(rr, addr);
++ setbits_le64(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le64_l4@
+p1 << p_setbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le64@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr);
+- rr |= set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le64_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr);
+- writeq(rr | set, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le64_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr) | set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writeq(readq(addr) | set, addr);
++ setbits_le64(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+ if (...)
+- rr |= set;
++ setbits_le64(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le64(addr, clear);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le64(addr, clear);
+ else
+- rr |= set;
++ setbits_le64(addr, set);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le64(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le64(addr, clear, set2);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le64(addr, clear, set);
++ else
++ setbits_le64(addr, set);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readq(addr) & ~mask);
+//- writeq(rr, addr);
+//+ setmask_le64(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits_dev.cocci b/scripts/coccinelle/misc/setbits_dev.cocci
new file mode 100644
index 000000000000..859bd0526fcc
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits_dev.cocci
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+// ========================================================================
+// driver specific changes
+// to be removed after conversion
+
+
+// mtk_hdmi_phy_mask
+@p_setmask_b@
+local idexpression rr;
+expression addr;
+expression set;
+expression mask;
+@@
+- rr = readl(addr);
+- rr = (rr & ~mask) | (set & mask);
+- writel(rr, addr);
++ setmask_le32(addr, set, mask);
+
+@p_setmask_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression mask;
+@@
+- rr = readl(addr);
+- rr = (set & mask) | (rr & ~mask);
+- writel(rr, addr);
++ setmask_le32(addr, set, mask);
+
+
+@p_net_meson_clean@
+@@
+- meson8b_dwmac_mask_bits(...) {
+- ...
+- }
+
+@p_net_meson@
+expression dwmac;
+expression addr;
+expression mask;
+expression value;
+@@
+
+- meson8b_dwmac_mask_bits(dwmac, addr, mask, value);
++ clrsetbits_le32(dwmac->regs + addr, mask, value);
+
+// meson DRM
+@p_meson_drm_writel@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel_bits_relaxed(mask, set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@p_mtu3_setbits@
+expression base;
+expression offset;
+expression value;
+@@
+
+- mtu3_setbits(base, offset, value);
++ setbits_le32(base + offset, value);
+
+@p_mtu3_clrbits@
+expression base;
+expression offset;
+expression mask;
+@@
+
+- mtu3_clrbits(base, offset, mask);
++ clrbits_le32(base + offset, mask);
+
+//
+@p_fimc_clean_set@
+@@
+- static void fimc_set_bits(...) {
+- ...
+- }
+
+@p_fimc_clean_clrt@
+@@
+- static void fimc_clear_bits(...) {
+- ...
+- }
+
+@p_fimc_setbits@
+expression fimc;
+expression offset;
+expression value;
+@@
+
+- fimc_set_bits(fimc, offset, value);
++ setbits_le32(fimc->regs + offset, value);
+
+@p_fimc_clrbits@
+expression fimc;
+expression offset;
+expression mask;
+@@
+
+- fimc_clear_bits(fimc, offset, mask);
++ clrbits_le32(fimc->regs + offset, mask);
+
+//
+@p_sif_clean_clr@
+@@
+- static void sif_clr_bit(...) {
+- ...
+- }
+
+@p_sif_clean_set@
+@@
+- static void sif_set_bit(...) {
+- ...
+- }
+
+@p_sif_setbits@
+expression sif;
+expression offset;
+expression value;
+@@
+
+- sif_set_bit(sif, offset, value);
++ setbits_le32(sif->regs + offset, value);
+
+@p_sif_clrbits@
+expression sif;
+expression offset;
+expression mask;
+@@
+
+- sif_clr_bit(sif, offset, mask);
++ clrbits_le32(sif->regs + offset, mask);
+
+// mediatek
+@p_mtk_clean_clr@
+@@
+- static void mtk_cec_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_clean_set@
+@@
+- static void mtk_cec_set_bits(...) {
+- ...
+- }
+
+@p_mtk_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_cec_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_cec_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+// mediatek HDMI
+@p_mtk_hdmi_clean_set@
+@@
+- static void mtk_hdmi_set_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_clean_clr@
+@@
+- static void mtk_hdmi_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_hdmi_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_hdmi_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_hdmi_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+// mediatek HDMI
+@p_mtk_hdmi_phy_clean_set@
+@@
+- static void mtk_hdmi_phy_set_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_phy_clean_clr@
+@@
+- static void mtk_hdmi_phy_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_phy_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_hdmi_phy_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_hdmi_phy_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_hdmi_phy_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+
+
--
2.18.1
^ permalink raw reply related
* [PATCH v3 1/7] powerpc: rename setbits32/clrbits32 to setbits_be32/clrbits_be32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: cocci, dri-devel, linux-amlogic, linux-arm-kernel, linux-ide,
linux-kernel, linux-mediatek, linuxppc-dev, netdev, linux-sunxi,
Corentin Labbe
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 +++----
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 12 +--
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 +--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 6 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 6 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 6 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 6 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +++----
.../platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-
arch/powerpc/platforms/embedded6xx/wii.c | 12 +--
arch/powerpc/sysdev/cpm1.c | 26 +++----
arch/powerpc/sysdev/cpm2.c | 16 ++--
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 16 ++--
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 12 +--
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74 +++++++++----------
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 9 ++-
arch/powerpc/sysdev/mpic_timer.c | 12 +--
41 files changed, 190 insertions(+), 189 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..4d6a56b48a28 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits_be32(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 0a034519957d..bc2fc014fd4f 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -882,8 +882,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..6aeb4ca64d09 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x42000000);
- setbits32((vaddr + GPIO0_TSRH), 0x42000000);
+ setbits_be32((vaddr + GPIO0_OSRH), 0x42000000);
+ setbits_be32((vaddr + GPIO0_TSRH), 0x42000000);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --git a/arch/powerpc/platforms/4xx/gpio.c b/arch/powerpc/platforms/4xx/gpio.c
index 2238e369cde4..8436da0617fd 100644
--- a/arch/powerpc/platforms/4xx/gpio.c
+++ b/arch/powerpc/platforms/4xx/gpio.c
@@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
if (val)
- setbits32(®s->or, GPIO_MASK(gpio));
+ setbits_be32(®s->or, GPIO_MASK(gpio));
else
- clrbits32(®s->or, GPIO_MASK(gpio));
+ clrbits_be32(®s->or, GPIO_MASK(gpio));
}
static void
@@ -112,18 +112,18 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&chip->lock, flags);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits_be32(®s->odr, GPIO_MASK(gpio));
/* Float the pin */
- clrbits32(®s->tcr, GPIO_MASK(gpio));
+ clrbits_be32(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
@@ -145,18 +145,18 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
__ppc4xx_gpio_set(gc, gpio, val);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits_be32(®s->odr, GPIO_MASK(gpio));
/* Drive the pin */
- setbits32(®s->tcr, GPIO_MASK(gpio));
+ setbits_be32(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL, bits 16-31 use TSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
index dc81f05e0bce..06b95795267a 100644
--- a/arch/powerpc/platforms/512x/pdm360ng.c
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -38,7 +38,7 @@ static int pdm360ng_get_pendown_state(void)
reg = in_be32(pdm360ng_gpio_base + 0xc);
if (reg & 0x40)
- setbits32(pdm360ng_gpio_base + 0xc, 0x40);
+ setbits_be32(pdm360ng_gpio_base + 0xc, 0x40);
reg = in_be32(pdm360ng_gpio_base + 0x8);
@@ -69,8 +69,8 @@ static int __init pdm360ng_penirq_init(void)
return -ENODEV;
}
out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff);
- setbits32(pdm360ng_gpio_base + 0x18, 0x2000);
- setbits32(pdm360ng_gpio_base + 0x10, 0x40);
+ setbits_be32(pdm360ng_gpio_base + 0x18, 0x2000);
+ setbits_be32(pdm360ng_gpio_base + 0x10, 0x40);
return 0;
}
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 565e3a83dc9e..edfe619d67bf 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -314,13 +314,13 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
/* enable gpio pins for output */
setbits8(&wkup_gpio->wkup_gpioe, reset);
- setbits32(&simple_gpio->simple_gpioe, sync | out);
+ setbits_be32(&simple_gpio->simple_gpioe, sync | out);
setbits8(&wkup_gpio->wkup_ddr, reset);
- setbits32(&simple_gpio->simple_ddr, sync | out);
+ setbits_be32(&simple_gpio->simple_ddr, sync | out);
/* Assert cold reset */
- clrbits32(&simple_gpio->simple_dvo, sync | out);
+ clrbits_be32(&simple_gpio->simple_dvo, sync | out);
clrbits8(&wkup_gpio->wkup_dvo, reset);
/* wait for 1 us */
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 17cf249b18ee..833cc33ebf91 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -142,7 +142,7 @@ static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ setbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -152,7 +152,7 @@ static void mpc52xx_gpt_irq_mask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -308,7 +308,7 @@ static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
@@ -482,7 +482,7 @@ int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
return -EBUSY;
}
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
}
@@ -639,8 +639,8 @@ static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
unsigned long flags;
raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
- clrbits32(&gpt_wdt->regs->mode,
- MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
+ clrbits_be32(&gpt_wdt->regs->mode,
+ MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
#endif
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 8fec050f2d5b..18626cd3db16 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -262,7 +262,7 @@ static void __init ep8248e_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
ep8248e_bcsr_node =
of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index 28860e40b5db..27d16d1a89f5 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -157,9 +157,9 @@ static void __init init_ioports(void)
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
/* Force USB FULL SPEED bit to '1' */
- setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
+ setbits_be32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
/* clear USB_SLAVE */
- clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
+ clrbits_be32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
}
static void __init km82xx_setup_arch(void)
@@ -172,7 +172,7 @@ static void __init km82xx_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
init_ioports();
diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c
index d23c10a96bde..75338e9e8acc 100644
--- a/arch/powerpc/platforms/82xx/mpc8272_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c
@@ -164,13 +164,13 @@ static void __init mpc8272_ads_setup_arch(void)
#define BCSR3_FETHIEN2 0x10000000
#define BCSR3_FETH2_RST 0x08000000
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits_be32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits_be32(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits_be32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits_be32(&bcsr[3], BCSR3_FETH2_RST);
- clrbits32(&bcsr[3], BCSR3_USB_nEN);
+ clrbits_be32(&bcsr[3], BCSR3_USB_nEN);
iounmap(bcsr);
diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c
index c4f7029fc9ae..92f2b4a5dcc8 100644
--- a/arch/powerpc/platforms/82xx/pq2.c
+++ b/arch/powerpc/platforms/82xx/pq2.c
@@ -25,7 +25,7 @@
void __noreturn pq2_restart(char *cmd)
{
local_irq_disable();
- setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
+ setbits_be32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 8b065bdf7412..060400ec3ebb 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -47,7 +47,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- setbits32(&priv->regs->mask, 1 << irq);
+ setbits_be32(&priv->regs->mask, 1 << irq);
mb();
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
@@ -63,7 +63,7 @@ static void pq2ads_pci_unmask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- clrbits32(&priv->regs->mask, 1 << irq);
+ clrbits_be32(&priv->regs->mask, 1 << irq);
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
}
}
diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c
index 6c654dc74a4b..84b637e019ed 100644
--- a/arch/powerpc/platforms/82xx/pq2fads.c
+++ b/arch/powerpc/platforms/82xx/pq2fads.c
@@ -140,18 +140,18 @@ static void __init pq2fads_setup_arch(void)
/* Enable the serial and ethernet ports */
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits_be32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits_be32(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits_be32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits_be32(&bcsr[3], BCSR3_FETH2_RST);
iounmap(bcsr);
init_ioports();
/* Enable external IRQs */
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
pq2_init_pci();
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index d8642a4afc74..d036b179dc65 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -101,19 +101,19 @@ static void quirk_mpc8360e_qe_enet10(void)
* UCC1: write 0b11 to bits 18:19
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x00003000);
+ setbits_be32((base + 0xa8), 0x00003000);
/*
* UCC2 option 1: write 0b11 to bits 4:5
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x0c000000);
+ setbits_be32((base + 0xa8), 0x0c000000);
/*
* UCC2 option 2: write 0b11 to bits 16:17
* at address IMMRBAR+0x14AC
*/
- setbits32((base + 0xac), 0x0000c000);
+ setbits_be32((base + 0xac), 0x0000c000);
}
iounmap(base);
of_node_put(np_par);
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index fd44dd03e1f3..83a5e27e2f63 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -118,7 +118,7 @@ static void __init mpc836x_mds_setup_arch(void)
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
- setbits32(immap, 0x0c003000);
+ setbits_be32(immap, 0x0c003000);
/*
* IMMR + 0x14AC[20:27] = 10101010
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e6dba3..52b4fb179c9e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -262,7 +262,7 @@ static void __init mpc85xx_mds_qe_init(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
index f05325f0cc03..926d0f9dc29d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
@@ -60,9 +60,9 @@ static void mpc85xx_freeze_time_base(bool freeze)
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
if (freeze)
- setbits32(&guts->devdisr, mask);
+ setbits_be32(&guts->devdisr, mask);
else
- clrbits32(&guts->devdisr, mask);
+ clrbits_be32(&guts->devdisr, mask);
in_be32(&guts->devdisr);
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 10069503e39f..fdea28dd90dd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -115,7 +115,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
* and QE12 for QE MII management singals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 9fb57f78cdbe..a2fbe4a592f0 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -405,11 +405,11 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 276e00ab3dde..7eaec20faa95 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -75,11 +75,11 @@ void p1022rdk_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
index dac36ba82fea..dffe44451fb9 100644
--- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -114,11 +114,11 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
- PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
+ clrbits_be32(scfg + CCSR_SCFG_PIXCLKCR,
+ PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
+ setbits_be32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
iounmap(scfg);
}
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f6253e9ff..5c385ebf6cac 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -95,7 +95,7 @@ static void __init twr_p1025_setup_arch(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
* Set QE mux bits in PMUXCR */
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index a5d73fabe4d1..ddd5a525dd3f 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -261,11 +261,11 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 31);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/8xx/adder875.c b/arch/powerpc/platforms/8xx/adder875.c
index bcef9f66191e..7bfae1617cfa 100644
--- a/arch/powerpc/platforms/8xx/adder875.c
+++ b/arch/powerpc/platforms/8xx/adder875.c
@@ -77,7 +77,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init adder875_setup(void)
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index f1c805c8adbc..ebdc3754b99f 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -103,7 +103,7 @@ void __init mpc8xx_calibrate_decr(void)
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
- setbits32(&clk_r2->car_sccr, 0x02000000);
+ setbits_be32(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
@@ -204,7 +204,7 @@ void __noreturn mpc8xx_restart(char *cmd)
local_irq_disable();
- setbits32(&clk_r->car_plprcr, 0x00000080);
+ setbits_be32(&clk_r->car_plprcr, 0x00000080);
/* Clear the ME bit in MSR to cause checkstop on machine check
*/
mtmsr(mfmsr() & ~0x1000);
diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
index 8d02f5ff4481..88c611ecee0a 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
@@ -87,7 +87,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc86xads_setup_arch(void)
@@ -112,7 +112,7 @@ static void __init mpc86xads_setup_arch(void)
return;
}
- clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
+ clrbits_be32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
iounmap(bcsr_io);
}
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index a0c83c1905c6..17e10250830b 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -123,7 +123,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc885ads_setup_arch(void)
@@ -148,33 +148,33 @@ static void __init mpc885ads_setup_arch(void)
return;
}
- clrbits32(&bcsr[1], BCSR1_RS232EN_1);
+ clrbits_be32(&bcsr[1], BCSR1_RS232EN_1);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- setbits32(&bcsr[1], BCSR1_RS232EN_2);
+ setbits_be32(&bcsr[1], BCSR1_RS232EN_2);
#else
- clrbits32(&bcsr[1], BCSR1_RS232EN_2);
+ clrbits_be32(&bcsr[1], BCSR1_RS232EN_2);
#endif
- clrbits32(bcsr5, BCSR5_MII1_EN);
- setbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits_be32(bcsr5, BCSR5_MII1_EN);
+ setbits_be32(bcsr5, BCSR5_MII1_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits_be32(bcsr5, BCSR5_MII1_RST);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- clrbits32(bcsr5, BCSR5_MII2_EN);
- setbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits_be32(bcsr5, BCSR5_MII2_EN);
+ setbits_be32(bcsr5, BCSR5_MII2_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits_be32(bcsr5, BCSR5_MII2_RST);
#else
- setbits32(bcsr5, BCSR5_MII2_EN);
+ setbits_be32(bcsr5, BCSR5_MII2_EN);
#endif
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
- clrbits32(&bcsr[4], BCSR4_ETH10_RST);
+ clrbits_be32(&bcsr[4], BCSR4_ETH10_RST);
udelay(1000);
- setbits32(&bcsr[4], BCSR4_ETH10_RST);
+ setbits_be32(&bcsr[4], BCSR4_ETH10_RST);
- setbits32(&bcsr[1], BCSR1_ETHEN);
+ setbits_be32(&bcsr[1], BCSR1_ETHEN);
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
#else
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
index db0be007fd06..658f972d277a 100644
--- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -53,7 +53,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + FLIPPER_IMR, mask);
+ clrbits_be32(io_base + FLIPPER_IMR, mask);
/* this is at least needed for RSW */
out_be32(io_base + FLIPPER_ICR, mask);
}
@@ -72,7 +72,7 @@ static void flipper_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + FLIPPER_IMR, 1 << irq);
+ clrbits_be32(io_base + FLIPPER_IMR, 1 << irq);
}
static void flipper_pic_unmask(struct irq_data *d)
@@ -80,7 +80,7 @@ static void flipper_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + FLIPPER_IMR, 1 << irq);
+ setbits_be32(io_base + FLIPPER_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 8112b39879d6..a5431ad4a529 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -50,7 +50,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + HW_BROADWAY_IMR, mask);
+ clrbits_be32(io_base + HW_BROADWAY_IMR, mask);
out_be32(io_base + HW_BROADWAY_ICR, mask);
}
@@ -67,7 +67,7 @@ static void hlwd_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ clrbits_be32(io_base + HW_BROADWAY_IMR, 1 << irq);
}
static void hlwd_pic_unmask(struct irq_data *d)
@@ -75,10 +75,10 @@ static void hlwd_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ setbits_be32(io_base + HW_BROADWAY_IMR, 1 << irq);
/* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */
- clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
+ clrbits_be32(io_base + HW_STARLET_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c
index ecf703ee3a76..a7a62871e68f 100644
--- a/arch/powerpc/platforms/embedded6xx/wii.c
+++ b/arch/powerpc/platforms/embedded6xx/wii.c
@@ -134,8 +134,8 @@ static void __init wii_setup_arch(void)
hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE);
if (hw_gpio) {
/* turn off the front blue led and IR light */
- clrbits32(hw_gpio + HW_GPIO_OUT(0),
- HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
+ clrbits_be32(hw_gpio + HW_GPIO_OUT(0),
+ HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
}
}
@@ -145,7 +145,7 @@ static void __noreturn wii_restart(char *cmd)
if (hw_ctrl) {
/* clear the system reset pin to cause a reset */
- clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
+ clrbits_be32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
}
wii_spin();
}
@@ -159,13 +159,13 @@ static void wii_power_off(void)
* set the owner of the shutdown pin to ARM, because it is
* accessed through the registers for the ARM, below
*/
- clrbits32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
+ clrbits_be32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
/* make sure that the poweroff GPIO is configured as output */
- setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
+ setbits_be32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
/* drive the poweroff GPIO high */
- setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
+ setbits_be32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
}
wii_spin();
}
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 4f8dcf124828..7fcbf8c059eb 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -60,14 +60,14 @@ static void cpm_mask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ clrbits_be32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_unmask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ setbits_be32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_end_irq(struct irq_data *d)
@@ -188,7 +188,7 @@ unsigned int cpm_pic_init(void)
if (setup_irq(eirq, &cpm_error_irqaction))
printk(KERN_ERR "Could not allocate CPM error IRQ!");
- setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
+ setbits_be32(&cpic_reg->cpic_cicr, CICR_IEN);
end:
of_node_put(np);
@@ -317,14 +317,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
&mpc8xx_immr->im_cpm.cp_pedir;
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop->dir, pin);
+ setbits_be32(&iop->dir, pin);
else
- clrbits32(&iop->dir, pin);
+ clrbits_be32(&iop->dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop->par, pin);
+ setbits_be32(&iop->par, pin);
else
- clrbits32(&iop->par, pin);
+ clrbits_be32(&iop->par, pin);
if (port == CPM_PORTB) {
if (flags & CPM_PIN_OPENDRAIN)
@@ -335,14 +335,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
if (port == CPM_PORTE) {
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop->sor, pin);
+ setbits_be32(&iop->sor, pin);
else
- clrbits32(&iop->sor, pin);
+ clrbits_be32(&iop->sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ setbits_be32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
else
- clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
}
}
@@ -732,7 +732,7 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits_be32(&iop->dir, pin_mask);
__cpm1_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
@@ -750,7 +750,7 @@ static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits_be32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 07718b9a2c99..e8c7a0117eed 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -335,22 +335,22 @@ void cpm2_set_pin(int port, int pin, int flags)
pin = 1 << (31 - pin);
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop[port].dir, pin);
+ setbits_be32(&iop[port].dir, pin);
else
- clrbits32(&iop[port].dir, pin);
+ clrbits_be32(&iop[port].dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop[port].par, pin);
+ setbits_be32(&iop[port].par, pin);
else
- clrbits32(&iop[port].par, pin);
+ clrbits_be32(&iop[port].par, pin);
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop[port].sor, pin);
+ setbits_be32(&iop[port].sor, pin);
else
- clrbits32(&iop[port].sor, pin);
+ clrbits_be32(&iop[port].sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&iop[port].odr, pin);
+ setbits_be32(&iop[port].odr, pin);
else
- clrbits32(&iop[port].odr, pin);
+ clrbits_be32(&iop[port].odr, pin);
}
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index b74508175b67..8f4fba3067c9 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -165,7 +165,7 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits_be32(&iop->dir, pin_mask);
__cpm2_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
@@ -183,7 +183,7 @@ static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits_be32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index c27058e5df26..cf80b8dc3366 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -124,24 +124,24 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
switch (ways) {
case LOCK_WAYS_EIGHTH:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
break;
case LOCK_WAYS_TWO_EIGHTH:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
break;
case LOCK_WAYS_HALF:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
break;
case LOCK_WAYS_FULL:
default:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
break;
}
eieio();
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 5340a483cf55..0264f8c67a96 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -192,7 +192,7 @@ static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* clear event registers */
- setbits32(&lbc->ltesr, LTESR_CLEAR);
+ setbits_be32(&lbc->ltesr, LTESR_CLEAR);
out_be32(&lbc->lteatr, 0);
out_be32(&lbc->ltear, 0);
out_be32(&lbc->lteccr, LTECCR_CLEAR);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 918be816b097..9290d8a7335b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1196,12 +1196,12 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
pci = hose->private_data;
/* Enable PTOD, ENL23D & EXL23D */
- clrbits32(&pci->pex_pme_mes_disr,
- PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+ clrbits_be32(&pci->pex_pme_mes_disr,
+ PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
out_be32(&pci->pex_pme_mes_ier, 0);
- setbits32(&pci->pex_pme_mes_ier,
- PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+ setbits_be32(&pci->pex_pme_mes_ier,
+ PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
/* PME Enable */
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
@@ -1218,7 +1218,7 @@ static void send_pme_turnoff_message(struct pci_controller *hose)
int i;
/* Send PME_Turn_Off Message Request */
- setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
+ setbits_be32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
/* Wait trun off done */
for (i = 0; i < 150; i++) {
@@ -1254,7 +1254,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
int i;
/* Send Exit L2 State Message */
- setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
+ setbits_be32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
/* Wait exit done */
for (i = 0; i < 150; i++) {
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 232225e7f863..ff29fa6af01c 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -37,7 +37,7 @@ static int pmc_suspend_enter(suspend_state_t state)
{
int ret;
- setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+ setbits_be32(&pmc_regs->pmcsr, PMCSR_SLP);
/* At this point, the CPU is asleep. */
/* Upon resume, wait for SLP bit to be clear. */
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
index 9259a94f70e1..fce703c400e6 100644
--- a/arch/powerpc/sysdev/fsl_rcpm.c
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -33,10 +33,10 @@ static void rcpm_v1_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v1_regs->cpmimr, mask);
- setbits32(&rcpm_v1_regs->cpmcimr, mask);
- setbits32(&rcpm_v1_regs->cpmmcmr, mask);
- setbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmcimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmmcmr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_mask(int cpu)
@@ -44,10 +44,10 @@ static void rcpm_v2_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v2_regs->tpmimr0, mask);
- setbits32(&rcpm_v2_regs->tpmcimr0, mask);
- setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmcimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmmcmr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_irq_unmask(int cpu)
@@ -55,10 +55,10 @@ static void rcpm_v1_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v1_regs->cpmimr, mask);
- clrbits32(&rcpm_v1_regs->cpmcimr, mask);
- clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
- clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmcimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmmcmr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_unmask(int cpu)
@@ -66,26 +66,26 @@ static void rcpm_v2_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v2_regs->tpmimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmcimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmmcmr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ setbits_be32(&rcpm_v1_regs->ippdexpcr, mask);
else
- clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ clrbits_be32(&rcpm_v1_regs->ippdexpcr, mask);
}
static void rcpm_v2_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ setbits_be32(&rcpm_v2_regs->ippdexpcr[0], mask);
else
- clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ clrbits_be32(&rcpm_v2_regs->ippdexpcr[0], mask);
}
static void rcpm_v1_cpu_enter_state(int cpu, int state)
@@ -95,10 +95,10 @@ static void rcpm_v1_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v1_regs->cdozcr, mask);
+ setbits_be32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v1_regs->cnapcr, mask);
+ setbits_be32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -114,16 +114,16 @@ static void rcpm_v2_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
/* one bit corresponds to one thread for PH10 of 6500 */
- setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
+ setbits_be32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph15setr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph20setr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph30setr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -172,10 +172,10 @@ static void rcpm_v1_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- clrbits32(&rcpm_v1_regs->cdozcr, mask);
+ clrbits_be32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- clrbits32(&rcpm_v1_regs->cnapcr, mask);
+ clrbits_be32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -196,16 +196,16 @@ static void rcpm_v2_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
+ setbits_be32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph15clrr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph20clrr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph30clrr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -226,7 +226,7 @@ static int rcpm_v1_plat_enter_state(int state)
switch (state) {
case PLAT_PM_SLEEP:
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
/* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
result = spin_event_timeout(
@@ -253,9 +253,9 @@ static int rcpm_v2_plat_enter_state(int state)
switch (state) {
case PLAT_PM_LPM20:
/* clear previous LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
/* enter LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
/* At this point, the device is in LPM20 status. */
@@ -291,9 +291,9 @@ static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
if (freeze) {
mask = in_be32(tben_reg);
- clrbits32(tben_reg, mask);
+ clrbits_be32(tben_reg, mask);
} else {
- setbits32(tben_reg, mask);
+ setbits_be32(tben_reg, mask);
}
/* read back to push the previous write */
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 5011ffea4e4b..891e11d12222 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -668,10 +668,10 @@ int fsl_rio_setup(struct platform_device *dev)
out_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0);
/* Set 1x lane */
- setbits32(priv->regs_win
+ setbits_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0x02000000);
/* Enable ports */
- setbits32(priv->regs_win
+ setbits_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0x00600000);
msleep(100);
if (in_be32((priv->regs_win
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 88b35a3dcdc5..b4f49049d75d 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -355,7 +355,7 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
dmsg->sid, dmsg->tid,
dmsg->info);
}
- setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
+ setbits_be32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
}
@@ -909,10 +909,11 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
out_be32(&rmu->msg_regs->imr, 0x001b0060);
/* Set number of queue entries */
- setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
+ setbits_be32(&rmu->msg_regs->imr,
+ (get_bitmask_order(entries) - 2) << 12);
/* Now enable the unit */
- setbits32(&rmu->msg_regs->imr, 0x1);
+ setbits_be32(&rmu->msg_regs->imr, 0x1);
out:
return rc;
@@ -1015,7 +1016,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
out1:
- setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
+ setbits_be32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
out2:
return buf;
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 87e7c42777a8..5cc8216a85e5 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -154,7 +154,7 @@ static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
tcr = casc_priv->tcr_value |
(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
- setbits32(priv->group_tcr, tcr);
+ setbits_be32(priv->group_tcr, tcr);
tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
@@ -253,7 +253,7 @@ void mpic_start_timer(struct mpic_timer *handle)
struct timer_group_priv *priv = container_of(handle,
struct timer_group_priv, timer[handle->num]);
- clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ clrbits_be32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
}
EXPORT_SYMBOL(mpic_start_timer);
@@ -269,7 +269,7 @@ void mpic_stop_timer(struct mpic_timer *handle)
struct timer_group_priv, timer[handle->num]);
struct cascade_priv *casc_priv;
- setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ setbits_be32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
casc_priv = priv->timer[handle->num].cascade_handle;
if (casc_priv) {
@@ -340,7 +340,7 @@ void mpic_free_timer(struct mpic_timer *handle)
u32 tcr;
tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
MPIC_TIMER_TCR_ROVR_OFFSET);
- clrbits32(priv->group_tcr, tcr);
+ clrbits_be32(priv->group_tcr, tcr);
priv->idle |= casc_priv->cascade_map;
priv->timer[handle->num].cascade_handle = NULL;
} else {
@@ -508,7 +508,7 @@ static void timer_group_init(struct device_node *np)
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits_be32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
list_add_tail(&priv->node, &timer_group_list);
@@ -531,7 +531,7 @@ static void mpic_timer_resume(void)
list_for_each_entry(priv, &timer_group_list, node) {
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits_be32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
}
}
--
2.18.1
^ permalink raw reply related
* Re: [RFC PATCH 0/3] M_CAN Framework rework
From: Faiz Abbas @ 2018-10-24 7:33 UTC (permalink / raw)
To: Dan Murphy, wg, mkl, davem; +Cc: linux-can, netdev, linux-kernel
In-Reply-To: <e8485e2e-df04-0905-7055-c2228c0f1fa4@ti.com>
Hi Dan,
On Thursday 18 October 2018 01:51 AM, Dan Murphy wrote:
> Bump
>
> On 10/10/2018 09:20 AM, Dan Murphy wrote:
>> All
>>
>> This patch series creates a m_can core framework that devices can register
>> to. The m_can core manages the Bosch IP and CAN frames. Each device that
>> is registered is responsible for managing device specific functions.
>>
>> This rewrite was suggested in a device driver submission for the TCAN4x5x
>> device
>> Reference upstream post:
>> https://lore.kernel.org/patchwork/patch/984163/
>>
>> For instance the TCAN device is a SPI device that uses a specific data payload to
>> determine writes and reads. In addition the device has a reset input as well
>> as a wakeup pin. The register offset of the m_can registers differs and must
>> be set by the device attached to the core.
>>
>> The m_can core will use iomapped writes and reads as the default mechanism for
>> writing and reading. The device driver can provide over rides for this.
>>
>> This patch series is not complete as it does not handle the CAN interrupts
>> nor can perform a CAN write. If this patch series is deemed acceptable I will
>> finish debugging the driver and post a non RFC series.
>>
>> Finally I did attempt to reduce the first patch with various git format patch
>> directives but none seemed to reduce the patch.
>>
>> Dan
>>
>> Dan Murphy (3):
>> can: m_can: Create m_can core to leverage common code
>> dt-bindings: can: tcan4x5x: Add DT bindings for TCAN4x5X driver
>> can: tcan4x5x: Add tcan4x5x driver to the kernel
>>
>> .../devicetree/bindings/net/can/tcan4x5x.txt | 34 +
>> drivers/net/can/m_can/Kconfig | 18 +
>> drivers/net/can/m_can/Makefile | 4 +-
>> drivers/net/can/m_can/m_can.c | 1683 +----------------
>> .../net/can/m_can/{m_can.c => m_can_core.c} | 479 +++--
>> drivers/net/can/m_can/m_can_core.h | 100 +
>> drivers/net/can/m_can/tcan4x5x.c | 321 ++++
>> 7 files changed, 722 insertions(+), 1917 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/net/can/tcan4x5x.txt
>> copy drivers/net/can/m_can/{m_can.c => m_can_core.c} (83%)
>> create mode 100644 drivers/net/can/m_can/m_can_core.h
>> create mode 100644 drivers/net/can/m_can/tcan4x5x.c
>>
Patch 1/3 never arrived for me. Its not there on lkml either.
https://lkml.org/lkml/2018/10/10/611
Can you resend the complete series?
Thanks,
Faiz
^ permalink raw reply
* Re: [GIT] Networking
From: Kalle Valo @ 2018-10-24 7:30 UTC (permalink / raw)
To: Linus Torvalds
Cc: davem, Andrew Morton, netdev, Linux Kernel Mailing List,
linux-wireless, ath10k, Jeff Kirsher, Niklas Cassel, Andy Gross,
David Brown
In-Reply-To: <CAHk-=whuhCGujWKO8JObGQaSdWOpJBXdkM-B-vD80QZifveScw@mail.gmail.com>
+ linux-wireless, ath10k, niklas, jeff, andy, david
Linus Torvalds <torvalds@linux-foundation.org> writes:
> On Wed, Oct 24, 2018 at 4:30 AM David Miller <davem@davemloft.net> wrote:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
>
> Hmm. Tentatively pulled, but there's something wrong with the Kconfig rules.
>
> Doing "make allmodconfig" (not even the build itself, just the config
> phase), I get
>
> WARNING: unmet direct dependencies detected for QCOM_QMI_HELPERS
> Depends on [n]: ARCH_QCOM && NET [=y]
> Selected by [m]:
> - ATH10K_SNOC [=m] && NETDEVICES [=y] && WLAN [=y] &&
> WLAN_VENDOR_ATH [=y] && ATH10K [=m] && (ARCH_QCOM || COMPILE_TEST
> [=y])
>
> because I'm obviously not building on ARCH_QCOM.
>
> I suspect that QCOM_QMI_HELPERS needs to have
>
> depends on (ARCH_QCOM || COMPILE_TEST) && NET
>
> or similar. I'll see if this builds for me at all despite the Kconfig warning.
I had missed this warning, sorry about that. Jeff reported the same
problem while I was on vacation and according to Niklas[1] it should be
fixed by this commit in linux-next:
ccfb464cd106 ("soc: qcom: Allow COMPILE_TEST of qcom SoC Kconfigs")
I'm hoping you will get the commit during this merge window but not sure
about that and via which tree it would come. Adding Andy and David who
hopefully know more.
[1] http://lists.infradead.org/pipermail/ath10k/2018-October/012330.html
--
Kalle Valo
^ permalink raw reply
* Re: [GIT] Networking
From: Linus Torvalds @ 2018-10-24 7:23 UTC (permalink / raw)
To: Bjorn Andersson, Govind Singh, Kalle Valo, David Miller
Cc: Andrew Morton, netdev, Linux Kernel Mailing List
In-Reply-To: <CAHk-=whuhCGujWKO8JObGQaSdWOpJBXdkM-B-vD80QZifveScw@mail.gmail.com>
On Wed, Oct 24, 2018 at 7:01 AM Linus Torvalds
<torvalds@linux-foundation.org> wrote:
>
> Hmm. Tentatively pulled, but there's something wrong with the Kconfig rules.
Confirmed.
I did a978a5b8d83f ("net/kconfig: Make QCOM_QMI_HELPERS available when
COMPILE_TEST") to fix the breakage.
Why wasn't this noticed in testing?
Linus
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Joakim Tjernlund @ 2018-10-23 22:15 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org, netdev@vger.kernel.org,
f.fainelli@gmail.com
Cc: andrew@lunn.ch
In-Reply-To: <adaad568-bbaf-fd5d-a2c3-ae7bf1be3d31@gmail.com>
On Tue, 2018-10-23 at 13:07 -0700, Florian Fainelli wrote:
>
> On 10/23/18 1:02 PM, Joakim Tjernlund wrote:
> > On Tue, 2018-10-23 at 11:20 -0700, Florian Fainelli wrote:
> > > On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
> > > > >
> > > > > On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
> > > > > > SPI (and others) has a way to define bus number in a aliases:
> > > > > > aliases {
> > > > > > ethernet4 = &enet4;
> > > > > > ethernet0 = &enet0;
> > > > > > ethernet1 = &enet1;
> > > > > > ethernet2 = &enet2;
> > > > > > ethernet3 = &enet3;
> > > > > > spi0 = &spi0
> > > > > > };
> > > > > > The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
> > > > > > I am looking for the same for ethernet devices:
> > > > > > ethernet4 = &enet4; /* should become eth4 */
> > > > > > ethernet0 = &enet0; /* should become eth0 */
> > > > > > but I cannot find something like that for eth devices.
> > > > > >
> > > > > > Could such functionality be added?
> > > > >
> > > > > It could, do we want and need to, no. You have the Ethernet alias in
> > > > > /sys/class/net/*/device/uevent already that would allow you to perform
> > > > > that (re)naming in user-space:
> > > > >
> > > > > # cat /sys/class/net/eth0/device/uevent
> > > > > DRIVER=bcmgenet
> > > > > OF_NAME=ethernet
> > > > > OF_FULLNAME=/rdb/ethernet@f0480000
> > > > > OF_TYPE=network
> > > > > OF_COMPATIBLE_0=brcm,genet-v5
> > > > > OF_COMPATIBLE_N=1
> > > > > OF_ALIAS_0=eth0 <==================
> > > > > MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
> > > >
> > > > Yes, one can if one uses udev and can find something to identify the hw I/F with, my
> > > > cat /sys/class/net/eth0/device/uevent looks like:
> > > > DRIVER=fsl_dpa
> > > > MODALIAS=platform:dpaa-ethernet
> > >
> > > Does not dpaa have a notion of Ethernet ports and those should have
> > > proper information? Maybe that is part of your problem here, it should
> > > have the OF_ALIAS information somehow available.
> >
> > I cannot say ATM, but this lack of standard does not make it easier to rename I/F's in udev.
> >
> > > > not sure mdev supports this, does it?
> > > > Our simple installer FS(initramfs) doesn't have either udev or mdev.
> > >
> > > I don't know, but you could have a simple shell script that looks at
> > > specific network device properties to decide on the naming and call
> > > ifrename.
> >
> > This reinventing of the wheel is what I am trying to avoid.
>
> Embedded is all about being a special snowflake and re-inventing the
> wheel, but having some desktop-like distribution user-space would
> certainly allow you to re-invent other parts of the wheel.
>
> > > > I also noted that using status = "disabled" didn't work either to create a fix name scheme.
> > > > Even worse, all the eth I/F after gets renumbered. It seems to me there
> > > > is value in having stability in eth I/F naming at boot.
> > > > Then userspace(udev) can rename if need be.
> > > >
> > > > Sure would like to known more about why this feature is not wanted ?
> > > >
> > > > I found
> > > > https://patchwork.kernel.org/patch/4122441/
> > > > You quote policy as reason but surely it must be better to
> > > > have something stable, connected to the hardware name, than semirandom naming?
> > >
> > > If the Device Tree nodes are ordered by ascending base register address,
> > > my understanding is that you get the same order as far as
> > > platform_device creation goes, this may not be true in the future if Rob
> > > decides to randomize that, but AFAICT this is still true. This may not
> > > work well with status = disabled properties being inserted here and
> > > there, but we have used that here and it has worked for as far as I can
> > > remember doing it.
> >
> > I recall it is the order in which the eth alias appear that controls the naming,
> > not 100% sure though.
>
> Aliases are not looked up at all by the platform bus code other that
> with of_get_alias() and friends, it is the order in which the nodes are
> declared in the Device Tree, preferably ordered by base address that
> dictates the order in which platform devices are created.
I see, thanks.
>
> > > Second, you might want to name network devices ethX, but what if I want
> > > to name them ethernetX or fooX or barX? Should we be accepting a
> > > mechanism in the kernel that would allow someone to name the interfaces
> > > the way they want straight from a name being provided in Device Tree?
> >
> > I just want to have stable boot names, aka ethX, which can defined in
> > the platforms DT. Then userspace can go from there to whatever it needs,
> > udev could possibly use these stable boot names to identify the I/F's to rename.
> >
> > ATM, it is pretty hard to even use udev when /sys/class/net/eth0/device/uevent
> > can look different even for OF created interfaces.
>
> network devices have a gazillion of other sysfs attributes that all make
> them unique enough to create stable names.
That is kind of my point, there doesn't seem to be any stable source of info
that can be relied on. Each platform/driver is it own, DT/OF created I/F's should
look the same in /sys/class/net/eth0/device/uevent but that is not so.
I am sure I can find something though.
>
> > > Aliases are fine for providing relative stability within the Device Tree
> > > itself and boot programs that might need to modify the Device Tree (e.g:
> > > inserting MAC addresses) such that you don't have to encode logic to
> > > search for nodes by compatible strings etc. but outside of that use
> > > case, it seems to me that you can resolve every naming decision in
> > > user-space.
> >
> > Well, you can resolve MAC address assignment in user space too but most
> > will agree that is not convenient. I suggest it is also handy to have
> > some control of I/F enumeration(ethX that is) from platform code like DT.
>
> If that is what you desire because you do not want to use user-space to
> do that job, that is probably fine, it's open source after all, an not
> every patch is a candidate for being included upstream. A patch doing
> what you describe would likely be rejected again.
> --
Of course, but I didn't start this thread just to hack my own patch. I wanted
buy in from the community and that is not happening so I will rest now.
Thanks you for taking the time to discuss this,
Jocke
^ permalink raw reply
* [PATCH net v2] net: udp: fix handling of CHECKSUM_COMPLETE packets
From: Sean Tranchetti @ 2018-10-23 22:04 UTC (permalink / raw)
To: eric.dumazet, davem, netdev; +Cc: Sean Tranchetti, Sam Kumar, Eric Dumazet
Current handling of CHECKSUM_COMPLETE packets by the UDP stack is
incorrect for any packet that has an incorrect checksum value.
udp4/6_csum_init() will both make a call to
__skb_checksum_validate_complete() to initialize/validate the csum
field when receiving a CHECKSUM_COMPLETE packet. When this packet
fails validation, skb->csum will be overwritten with the pseudoheader
checksum so the packet can be fully validated by software, but the
skb->ip_summed value will be left as CHECKSUM_COMPLETE so that way
the stack can later warn the user about their hardware spewing bad
checksums. Unfortunately, leaving the SKB in this state can cause
problems later on in the checksum calculation.
Since the the packet is still marked as CHECKSUM_COMPLETE,
udp_csum_pull_header() will SUBTRACT the checksum of the UDP header
from skb->csum instead of adding it, leaving us with a garbage value
in that field. Once we try to copy the packet to userspace in the
udp4/6_recvmsg(), we'll make a call to skb_copy_and_csum_datagram_msg()
to checksum the packet data and add it in the garbage skb->csum value
to perform our final validation check.
Since the value we're validating is not the proper checksum, it's possible
that the folded value could come out to 0, causing us not to drop the
packet. Instead, we believe that the packet was checksummed incorrectly
by hardware since skb->ip_summed is still CHECKSUM_COMPLETE, and we attempt
to warn the user with netdev_rx_csum_fault(skb->dev);
Unfortunately, since this is the UDP path, skb->dev has been overwritten
by skb->dev_scratch and is no longer a valid pointer, so we end up
reading invalid memory.
This patch addresses this problem in two ways:
1) Do not use the dev pointer when calling netdev_rx_csum_fault()
from skb_copy_and_csum_datagram_msg(). Since this gets called
from the UDP path where skb->dev has been overwritten, we have
no way of knowing if the pointer is still valid. Also for the
sake of consistency with the other uses of
netdev_rx_csum_fault(), don't attempt to call it if the
packet was checksummed by software.
2) Add better CHECKSUM_COMPLETE handling to udp4/6_csum_init().
If we receive a packet that's CHECKSUM_COMPLETE that fails
verification (i.e. skb->csum_valid == 0), check who performed
the calculation. It's possible that the checksum was done in
software by the network stack earlier (such as Netfilter's
CONNTRACK module), and if that says the checksum is bad,
we can drop the packet immediately instead of waiting until
we try and copy it to userspace. Otherwise, we need to
mark the SKB as CHECKSUM_NONE, since the skb->csum field
no longer contains the full packet checksum after the
call to __skb_checksum_validate_complete().
Fixes: e6afc8ace6dd ("udp: remove headers from UDP packets before queueing")
Fixes: c84d949057ca ("udp: copy skb->truesize in the first cache line")
Cc: Sam Kumar <samanthakumar@google.com>
Cc: Eric Dumazet <edumazet@google.com>
Signed-off-by: Sean Tranchetti <stranche@codeaurora.org>
---
net/core/datagram.c | 5 +++--
net/ipv4/udp.c | 20 ++++++++++++++++++--
net/ipv6/ip6_checksum.c | 20 ++++++++++++++++++--
3 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/net/core/datagram.c b/net/core/datagram.c
index 9aac0d6..df16493 100644
--- a/net/core/datagram.c
+++ b/net/core/datagram.c
@@ -808,8 +808,9 @@ int skb_copy_and_csum_datagram_msg(struct sk_buff *skb,
return -EINVAL;
}
- if (unlikely(skb->ip_summed == CHECKSUM_COMPLETE))
- netdev_rx_csum_fault(skb->dev);
+ if (unlikely(skb->ip_summed == CHECKSUM_COMPLETE) &&
+ !skb->csum_complete_sw)
+ netdev_rx_csum_fault(NULL);
}
return 0;
fault:
diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
index c32a4c1..f8183fd 100644
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -2120,8 +2120,24 @@ static inline int udp4_csum_init(struct sk_buff *skb, struct udphdr *uh,
/* Note, we are only interested in != 0 or == 0, thus the
* force to int.
*/
- return (__force int)skb_checksum_init_zero_check(skb, proto, uh->check,
- inet_compute_pseudo);
+ err = (__force int)skb_checksum_init_zero_check(skb, proto, uh->check,
+ inet_compute_pseudo);
+ if (err)
+ return err;
+
+ if (skb->ip_summed == CHECKSUM_COMPLETE && !skb->csum_valid) {
+ /* If SW calculated the value, we know it's bad */
+ if (skb->csum_complete_sw)
+ return 1;
+
+ /* HW says the value is bad. Let's validate that.
+ * skb->csum is no longer the full packet checksum,
+ * so don't treat it as such.
+ */
+ skb_checksum_complete_unset(skb);
+ }
+
+ return 0;
}
/* wrapper for udp_queue_rcv_skb tacking care of csum conversion and
diff --git a/net/ipv6/ip6_checksum.c b/net/ipv6/ip6_checksum.c
index 547515e..3777170 100644
--- a/net/ipv6/ip6_checksum.c
+++ b/net/ipv6/ip6_checksum.c
@@ -88,8 +88,24 @@ int udp6_csum_init(struct sk_buff *skb, struct udphdr *uh, int proto)
* Note, we are only interested in != 0 or == 0, thus the
* force to int.
*/
- return (__force int)skb_checksum_init_zero_check(skb, proto, uh->check,
- ip6_compute_pseudo);
+ err = (__force int)skb_checksum_init_zero_check(skb, proto, uh->check,
+ ip6_compute_pseudo);
+ if (err)
+ return err;
+
+ if (skb->ip_summed == CHECKSUM_COMPLETE && !skb->csum_valid) {
+ /* If SW calculated the value, we know it's bad */
+ if (skb->csum_complete_sw)
+ return 1;
+
+ /* HW says the value is bad. Let's validate that.
+ * skb->csum is no longer the full packet checksum,
+ * so don't treat is as such.
+ */
+ skb_checksum_complete_unset(skb);
+ }
+
+ return 0;
}
EXPORT_SYMBOL(udp6_csum_init);
--
1.9.1
^ permalink raw reply related
* Re: [PATCH nf] netfilter: ipv6: fix oops when defragmenting locally generated fragments
From: Florian Westphal @ 2018-10-23 22:04 UTC (permalink / raw)
To: Maciej Żenczykowski
Cc: Florian Westphal, netfilter-devel, Lorenzo Colitti, Eric Dumazet,
Linux NetDev
In-Reply-To: <CANP3RGfCDumc40Tr2gr0KHenQ6x29tWAjhnM+8yk7nK5nNHRFA@mail.gmail.com>
Maciej Żenczykowski <maze@google.com> wrote:
> > ret = -EINPROGRESS;
> > if (fq->q.flags == (INET_FRAG_FIRST_IN | INET_FRAG_LAST_IN) &&
> > - fq->q.meat == fq->q.len &&
> > - nf_ct_frag6_reasm(fq, skb, dev))
> > - ret = 0;
> > - else
> > + fq->q.meat == fq->q.len) {
> > + unsigned long orefdst = skb->_skb_refdst;
> > +
> > + skb->_skb_refdst = 0UL;
> > + if (nf_ct_frag6_reasm(fq, skb, dev))
> > + ret = 0;
> > + skb->_skb_refdst = orefdst;
> > + } else {
> > skb_dst_drop(skb);
> > + }
> >
> > out_unlock:
> > spin_unlock_bh(&fq->q.lock);
> > --
> > 2.18.1
> >
>
> I don't quite follow how this fixes things, but I'll trust you on it.
The problematic spot is skb_morph() in nf_ct_frag6_reasm(), when we hit
this code path we take dst from a dst-less skb that got queued earlier.
> (nor do I understand why only 4.9 LTS appears to crash with a null ptr deref)
Newer kernels need nft or iptables rule that enables defrag, such as
"ip6tables -A INPUT -m conntrack --ctstate NEW"; 4.9 still enables it by
default.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox